GR-TMTC-MEZZ
Contents
1. Table 3 15 JP5 GPIO Signal Header 1 FUNCTION FPGA FPGA CONNECTOR PIN EPGA FUNCTION signal Pin Pin signal GPIO16 GENIO151 AM2 1 2 AG8 GENIO150 GPIO17 GPIO18 GENIO149 AP1 3 4 AK4 GENIO148 GPIO19 GPIO20 GENIO 147 AL5 5 6 AL4 GENIO146 GPIO21 GPIO22 GENIO145 AK6 7 8 AM3 144 GPIO23 GPIO24 GENIO143 AP2 9 10 AL3 GENIO142 GPIO25 GPIO26 GENIO141 AN2 11 12 AL6 GENIO140 GPIO27 GPIO28 GENIO131 13 14 AR2 GENIO130 GPIO29 GPIO30 GENIO129 AU3 15 16 AR3 128 GPIO31 3 3V 17 18 3 3V DGND 19 20 Table 3 16 JP6 GPIO Signal Header 2 FPGA FUNCTION FPGA signal PIN OPEN SWITCH CLOSED SWITCHO GENIO159 AG7 1 T SWITCH1 GENIO158 f 2 0 SWITCH2 GENIO157 AK1 T 3 T SWITCH3 GENIO156 AH3 4 0 SWITCH4 GENIO155 AL1 qt 5 0 SWITCH5 GENIO154 AH7 E 6 0 SWITCH6 GENIO153 AM1 f 7 SWITCH7 GENIO152 AK2 8 Table 3 17 DIP Switch 51 definition 1 2 RAM Bank 0 3 4 RAM Bank 1 5 6 RAM Bank 2 7 8 RAM Bank 3 Jumpers JP7 amp JP8 RAM Bank selection Both jumpers must be set the same Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 20 Pin Name FPGA Signal FPGA Pin Comment 1 DINO GENIO110 AF38 Data In ve 6 DINO GENIO110 Data In ve 2 SINO GENIO112. TMTC Redundant Header renen 18 4 Auxilliary Spare Signal Header 18 JP5 GPIO Signal Header 1 rr ia ee bie an 19 JP6 GPIO Signal Header 2 sin i 19 DIP Switch S1 19 J5 Spacewire interface connections 20 J6 Spacewire interface connections nn nnnnnnnnnnna anna nn 20 J12 Spacewire interface connections 20 J13 Spacewire interface connections 20 FIGURES RSPR TIM Assembly EE 5 GR TMTC Assembly mounted in Compact 6 Block Diagram of GR TMTC assembly and 8 GR CPCI XC4V board with GR TMTC FLEX Mezzanine and front panel 10 Front Panel view Pin1 s marked with red Circle nn 11 Assembly Photo Top view 16 Assembly Photo Bottom view Oblique nanna nr 16 Mezzanine Photo Top View n 21 Mezzanine Photo Bottom view 21 REVISION HISTORY Revision Date Page Description 0 1 2006 09 07 All First issue Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine
3. znpz GR TMTC Mezzanine ELECTRONIC DESIGN User Manual GAISLER RESEARCH PENDER ELECTRONIC DESIGN Rev 0 1 2007 10 07 GR TMTC Mezzanine User Manual 2 Pender Electronic Design GmbH info pender ch GR TMTC Mezzanine User Manual Copyright 2007 Gaisler Research Pender Electronic Design GmbH Permission is granted to make and distribute verbatim copies of this document provided the copyright notice and this permission notice are preserved on all copies Third party brands names and trademarks are the property of their respective owners Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 3 TABLE OF CONTENTS 1 INTRODUGTION ua um u a A 5 1 1 P PERLE 5 1 2 erat 7 ke Ha dlinighuy UR 7 1 4 Abbreviation Sisaren i a a a a SES ER 7 2 ELECIRICAE DESIGN uuu u u Z uuu E 8 2 1 5316 4 23 RR RR E te A ee 8 2 2 Configuration for FPGA VLDS signals nn 10 3 INTERFACES AND CONFIGURATIONN 11 3 1 List of Front Panel Connectors 11 3 2 List of Mezzanine Connectors annann nrnna 17 Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 4 LIST OF TABLES Table 3 1 List of Front
4. User Manual 13 Pin Name Comment 1 DINO Data In ve 6 DINO Data In ve 2 SINO Strobe In ve 7 SINO Strobe In ve 3 SHIELD Inner Shield 8 SOUTO Strobe Out ve 4 SOUTO Strobe Out ve 9 DOUTO Data Out ve 5 DOUTO Data Out ve Table 3 5 SPW 0 Spacewire interface connections Pin Name Comment 1 DIN1 Data In ve 6 DIN1 Data In ve 2 SIN1 Strobe In ve 7 SIN1 Strobe In ve 3 SHIELD Inner Shield 8 SOUT1 Strobe Out ve 4 500 1 Strobe Out ve 9 DOUT1 Data Out ve 5 DOUT1 Data Out ve Table 3 6 SPW 1 Spacewire interface connections Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 14 Pin Name Comment 10 1 TC CLK_N TC Clock ve RS422 Prime 19 11 2 TC CLK_P TC Clock ve RS422 Prime 20 12 3 TC DATA_P TC Data ve RS422 Prime 21 13 TM CLK_P TM Clock ve RS422 Prime 4 TC DATA_N TC Data ve RS422 Prime 22 14 TM CLK_N TM Clock ve RS422 Prime 5 TC Spare_P TC Spare ve RS422 Prime 23 15 TM DATA_N TM Data ve RS422 Prime 6 TC Spare_N TC Spare ve RS422 Prime 24 16 TM DATA_P TM Data RS422 Prime 7 TC Active P TC Active ve RS422 Prime 25 17 8 TC Active N TC Active ve RS422 Prime 26 18 9 DGND Ground Table 3 7 TMTC TMTC interface connections Pender Electronic Des
5. User Manual 5 1 INTRODUCTION 1 1 Overview The GR TMTC equipment provides a hardware platform for the implementation of LEON3 systems together with IP cores which implement TMTC RS422 and SPACEWIRE interfaces The assembly Figure 1 1 consists of the following hardware elements e FPGA Development Board GR TMTC Mezzanine Interface Board with Front Panel and wiring Harness The FPGA development board must be programmed with an suitable FPGA configuration Although the equipment can be used stand alone on the bench top it is intended to be installed in a Compact PCI rack The GR TMTC assembly requires one Compact PCI back plane slot However the width of the front panel requires two slot widths 8 TE It is also possible to add the optional GR CPCI RS232 accessory board to the assembly This accessory board provides two UART serial RS232 interfaces connected by ribbon cable to J4 and a Reset switch which can be connected to the JP5 reset header on the GR CPCI XC4V board Figure 1 1 GR TMTC Assembly Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 13535 EBr o EB VO9d4 tf W E cx 3 Hm gt E x Figure 1 2 GR TMTC Assembly mounted in Compact PCI rack The GR TMTC mezzanine front panel provides circuits and connectors for serial Debug Support Unit interface D9 Female connector Ethernet interface RJ45 connector J
6. 1 AG37 Strobe In ve 7 SINO GENIO111 Strobe In ve 3 SHIELD Inner Shield 8 SOUTO GENIO109 AG38 Strobe Out ve 4 SOUTO GENIO109 Strobe Out ve 9 DOUTO GENIO108 AF39 Data Out ve 5 DOUTO GENIO108 Data Out ve Table 3 18 J5 Spacewire interface connections Pin Name FPGA Signal FPGA Pin Comment 1 DIN1 GENIO106 AH39 Data In ve 6 DIN1 GENIO106 Data In ve 2 SIN1 GENIO107 AB28 Strobe In ve q SIN1 GENIO107 Strobe In ve 3 SHIELD Inner Shield 8 SOUT1 GENIO105 AB27 Strobe Out ve 4 SOUT1 GENIO105 Strobe Out ve 9 DOUT1 GENIO104 AJ39 Data Out ve 5 DOUT1 GENIO104 Data Out ve Table 3 19 J6 Spacewire interface connections Pin Name FPGA Signal FPGA Pin Comment 1 DIN2 GENIO126 AA34 Data In ve 6 DIN2 GENIO124 AA35 Data In ve 2 SIN2 GENIO127 AA31 Strobe In ve if SIN2 GENIO125 Y31 Strobe In ve 3 SHIELD Inner Shield 8 SOUT2 GENIO120 AC35 Strobe Out ve 4 SOUT2 GENIO122 AB35 Strobe Out ve 9 DOUT2 GENIO121 Y29 Data Out ve 5 DOUT2 GENIO123 AA30 Data Out ve Table 3 20 J12 Spacewire interface connections Pin Name FPGA Signal FPGA Pin Comment 1 DIN3 GENIO118 AC38 Data In ve 6 DIN3 GENIO116 AC39 Data In ve 2 SIN3 GENIO119 AE34 Strobe In ve Z SIN3 GENIO117 AD34 Strobe In ve 3 SHIELD Inner Shield 8 SOUT3 GENIO112 AE39 Strobe Out ve 4 SOUT3 GENIO114 AD39 Strobe Out ve 9 DOUT3 GENIO113 AD31 Data Out ve 5 DOUT3 GENIO115 AD32 Data Out ve Table 3 21 J13 Spacewire interface c
7. 5 5 6 GENIO52 IN 0 P GENIO53 E27 7 8 GENIO53 TM OUT GENIO54 G26 9 10 GENIO54 OUT TM CIKO TM 0 P OUT GENIO55 D27 11 12 GENIO55 OUT 0 TM_Spare1_P OUT GENIO57 D29 13 14 GENIO57 OUT TM_Spare1_N TM_Spare2_P OUT GENIO59 E29 15 16 GENIO59 OUT TM_Spare2_N 17 18 me DGND 19 20 DGND Table 3 11 JP1 TMTC Prime Header FUNCTION FPGA FPGA CONNECTOR PIN FPGA FUNCTION signal Pin Pin signal CLCWIn PO IN GENIO28 L34 1 2 GENIO28 IN CLCWIn NO CLCWIn P1 IN GENIO29 M33 3 4 GENIO29 IN CLCWIn N1 CLCWOut OUT GENIO24 N34 5 6 GENIO24 OUT CLCWOut NO CLCWOut P1 OUT GENIO25 P35 7 8 GENIO25 OUT CLCWOut 1 CPDU BIDI GENIO32 K33 9 10 GENIO33 BIDI CPDU Data CPDU Arm BIDI GENIO35 U37 11 12 GENIO34 BIDI CPDU Strobe TW In P IN GENIO30 L33 13 14 GENIO30 IN TW_In_N TW_Out_P OUT GENIO26 M35 15 16 GENIO26 OUT TW_Out_N Datation 0 BIDI GENIO139 AMS 17 18 GENIO135 BIDI Pulses 0 Datation 1 BIDI GENIO138 AN3 19 20 GENIO134 BIDI Pulses 1 Datation 2 BIDI GENIO137 4 21 22 GENIO133 BIDI Pulses 2 Datation 3 BIDI GENIO136 AN4 23 24 GENIO132 BIDI Pulses_3 DGND 25 26 3 3V Table 3 12 JP2 TMTC Aux I O Header FUNCTION FPGA FPGA CONNECTOR PIN EPGA EPGA FUNCTION signal Pin Pin signal TC IN GENIO47 N37 1 2 GENIO47 IN TC_CIk0_N TC_Data0_P IN GENIO46 J37 3 4 GENIO46 IN TC_Data0_N TC_Active0_P IN GENIO45 P37 5 6 G
8. C AUX 2 row x 13 pin 0 1 Header Auxilliary RS422 and TTL signals JP3 TMTC Redun 2 row x 10 pin 0 1 Header RS422 TMTC signals Redundant set JP4 AUX 2 row x 2 pin 0 1 Header 2 Auxilliary RS232 signals JP5 GPIO Signal Header 1 2 row x 10 pin 0 1 Header General purpose TTL signals JP6 GPIO Signal Header 2 2 row x 10 pin 0 1 Header General purpose TTL signals JP7 RAMSN bank config 2 row x 4 pin 0 1 Header Jumpers to select RAM bank JP8 RAMOEN bank config 2 row x 4 pin 0 1 Header Jumpers to select RAM bank J5 SPW 0 MDMSS footprint SPW interface with LVDS driver receivers J6 SPW 1 MDMSS footprint SPW interface with LVDS driver receivers J12 SPW 2 MDMSS footprint SPW interface direct to FPGA J13 SPW 3 MDMSS footprint SPW interface direct to FPGA Table 3 10 List of Mezzanine Headers Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 18 FUNCTION EPGA FEGA CONNECTOR PIN FPGA FPGA FUNCTION signal Pin Pin signal TC_CIk0_P IN GENIO50 F28 2 GENIO50 TC CIkO TC Data P IN GENIO51 A26 3 4 GENIO51 TC_Data0_N 0 GENIO52 G2
9. ENIO45 IN TC_Active0_N TC_Spare0_P IN GENIO44 K36 7 8 GENIO44 IN TC_Spare0_N TM_CIk0_P OUT GENIO43 P36 9 10 GENIO43 OUT TM_CIk0_N TM_Data0_P OUT GENIO42 L36 11 12 GENIO42 OUT TM_Data0_N TM_Spare1_P OUT GENIO41 R37 13 14 GENIO41 OUT TM_Spare1_N TM_Spare2_P OUT 040 M36 15 16 GENIO40 OUT TM_Spare2_N 17 18 19 20 Table 3 13 JP3 TMTC Redundant Header FUNCTION FPGA FPGA CONNECTOR PIN FPGA FPGA FUNCTION signal Pin Pin signal AUX_OUT_P OUT GENIO27 N33 1 m 2 GENIO27 OUT AUX OUT N AUX IN P IN GENIO31 V37 nn 4 GENIO31 IN AUX_IN_N Table 3 14 JP4 Auxilliary Spare Signal Header Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 19 FUNCTION EPGA FEGA CONNECTOR PIN FPGA EPGA FUNCTION signal Pin Pin signal GPIOO GENIO95 AD37 1 2 AL38 GENIO94 GPIO1 GPIO2 GENIO92 AL39 3 4 AC37 GENIO93 GPIO3 GPIO4 GENIO90 AM38 5 6 AD36 GENIO91 GPIO5 GPIO6 GENIO88 AM37 7 8 AD35 GENIO89 GPIO7 GPIO8 GENIO86 AC32 9 10 AF36 GENIO87 GPIO9 GPIO10 GENIO84 AB31 11 12 AE36 GENIO85 GPIO11 GPIO12 GENIO82 AB30 13 14 AG36 GENIO83 GPIO13 GPIO14 GENIO80 AC30 15 16 AG35 GENIO81 GPIO15 3 3V 17 18 3 3V DGND 19 20
10. Panel 4 11 Table 3 2 J1 DSU Debug Support Unit connections 12 Table 3 3 J2 RJ45 ETHERNET Connector T 12 Table 3 4 J3 FPGA Programming Connector 12 Table 3 5 SPW 0 Spacewire interface connections 13 Table 3 6 SPW 1 Spacewire interface connections 13 Table 3 7 TMTC TMTC interface 22000000 0 00 0 000 nennen 14 Table 3 8 TMTC AUX TMTC Auxilliarv interface 15 Table 3 9 List of Front Panel LED s and their driving 15 Table 3 10 Table 3 11 Table 3 12 Table 3 13 Table 3 14 Table 3 15 Table 3 16 Table 3 17 Table 3 18 Table 3 19 Table 3 20 Table 3 21 LIST OF Figure 1 1 Figure 1 2 Figure 2 1 Figure 2 2 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 List of Mezzanine 17 JP1 TMTC Prime Header r 18 2 TMTC Aux I O Header nann nnnn nennen 18
11. TAG connector for FPGA programming two LVDS Spacewire type electrical interfaces Microminiature MDM9S connectors TMTC RS422 interfaces HDD26 Male connector Auxilliary TMTC RS422 and TTL signals 0 1 Shrouded Headers power indicator LED and three user definable LED indicators The GR CPCI RS232 front panel provides circuits and connectors for two serial RS232 interfaces D9 Female connectors push button for system reset To enable convenient connection to the interfaces the connector types and pin outs are compatible with the standard connector types for these types of interfaces The pin out information is listed in section 3 of this document Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 7 1 2 References More detailed information concerning the implementation and configuration of the elements making up the GR TMTC assembly is provided in the following documents RD 1 GR CPCI XC4V Leon Development Board Users Manual RD 2 GR CPCI XCAV schematic pdf Schematic RD 3 GR CPCI XCAV drawing pdf Assembly Drawing RD 4 GR TMTC MEZZ schematic pdf Schematic RD 5 GR TMTC MEZZ assy drawing pdf Assembly Drawing RD 6 GR TMTC Harness schematic pdf Schematic 1 3 Handling ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES This board contains sensitive electronic components which can be damaged by Electrostatic Discharges ESD When handling or installing the boa
12. TC kit for two of the SPW interfaces the LVDS receiver and transmitter pairs are provided directly from LVDS pairs of the FPGA and there are no discrete LVDS receiver transmitter devices on the mezzanine board For these sets of signals This requires that the FPGA design must be appropriately configured for LVDS input outputs on the appropriate pins and that the FPGA bank voltage for the LVDS signals is set for 2 5V This is the default configuration for the GR CPCI XC4V board Also the Virtex4 FPGA on the GR CPCI XC4V board provides the possiblity to provide 100 Ohm termination for the LVDS receiver pairs internally to the FPGA eliminating the need to provide termination on the mezzanine board itself However for this to operate the following resistors are require to be installed on the GR CPCI XC4V board R112 50Ohms and R137 50 Ohms which are not normally fitted in the default configuration for the GR CPCI XCAV board Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 11 3 INTERFACES AND CONFIGURATION 3 1 List of Front Panel Connectors Name Function Type Description J1 DSU D9S J2 ETHERNET RJ45 Ethernet network connector J3 JTAG FPGA 2x7 pin shrouded 2mm header FPGA configuration and programming SPW 0 J SPW 0 MDM9 S female LVDS connections for Spacewire Interface 0 SPW 1 SPW 1 MDM9 S female LVDS connections for Spacewire Interface 1 TMTC TMTC HDDP26 The connector pinn
13. der Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 16 Figure 3 2 Assembly Photo Top view Oblique Figure 3 3 Assembly Photo Bottom view Oblique Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 17 3 2 List of Mezzanine Connectors Figure 3 4 And Figure 3 5 show views of the Mezzanine board which is mounted to the GR CPCI XCAV board The following tables list In the default configuration only connectors JP1 JP2 J5 and J6 are connected to the front panel The connections from the mezzanine board to the front panel are described by the schematic RD 6 The mezzanine board also provided a number of other headers which if appropriate could be used in other configurations to provide additional signal input outputs The following table list the headers and signals on the Mezzanine board In the tables the name of the corresponding GENIO signal on the FPGA which drives the function of the pin and its pin number are indicated in the tables Note that signals which are the negative pin of an differential pair driver receiver are shown in brackets as they are driven receive the same effective signal as its corresponding positive pin of the pair In the event of discrepancies please refer to the schematic drawings Name Function Type Description JP1 TMTC Prime 2 row x 10 pin 0 1 Header RS422 TMTC signals Prime set JP2 TMT
14. ign GmbH Rev 0 1 GR TMTC Mezzanine User Manual 15 Pin Name Comment 1 CLCWIn PO CLCWInO ve RS422 2 CLCWIn NO CLCWInO ve RS422 3 CLCWIn P1 CLCWIn1 ve RS422 4 CLCWIn N1 CLCWIn1 ve 5422 5 CLCWOut CLCWOut0 ve RS422 6 CLCWOut NO CLCWOutO ve RS422 7 CLCWOut P1 CLCWOut1 RS422 8 CLCWOut N1 CLCWOut1 ve RS422 9 CPDU_Clk CPDU_Clk LVTTL 10 CPDU_Data CPDU_Data LVTTL 11 CPDU_Arm CPDU_Arm LVTTL 12 CPDU_Strobe CPDU Strobe LVTTL 13 TW In P TW In ve RS422 14 TW In N TW In ve RS422 15 TW Out P TW Out ve RS422 16 TW Out TW Out ve RS422 17 Datation 0 Datation 0 LVTTL 18 Pulses 0 Pulses 0 LVTTL 19 Datation 1 Datation 1 LVTTL 20 Pulses 1 Pulses 1 LVTTL 21 Datation 2 Datation 2 LVTTL 22 Pulses 2 Pulses 2 LVTTL 23 Datation 3 Datation 3 LVTTL 24 Pulses 3 Pulses 3 LVTTL 25 DGND DGND 26 3 3V 3 3V Table 3 8 TMTC AUX TMTC Auxilliary interface connections LED FPGA FPGA Pin Comment signal LED P 3 3V 3 3V power present on board LEDA LED1 User definable LED e g connect to processor signal DSUACT LED 2 LED2 User definable LED e g connect to processor signal ERRORN LED 3 LED2 User definable LED e g connect to processor signal WATCHDOG Table 3 9 List of Front Panel LED s and their driving signals Pen
15. ignals LVTTL 8 pole DIP Switch for general purpose use Two sets of SPW signals These signals are LVTTL input ouputs to the FPGA and are provided with driver receiver IC s on the mezzanine to provide the level conversion from single ended LVTTL to from LVDS differential signals Two sets of SPW signals These signals are LVDS input ouputs directly to the FPGA No driver receiver circuits are required on the Mezzanine However the FPGA design must be appropriately configured for LVDS levels and termination on these inputs outputs more information in section 2 2 RS422 differential drivers for 12 signal pairs RS422 differential receivers for 12 signal pairs 12 single ended LVTTL signals which can be defined as inputs or outputs Wiring from two front panel MDM9S connectors two 20 pin headers each providing an additional 16 general purpose LVTTL I O signals connected directyl to the FPGA Wire and ribbon cable harness connecting from headers on mezzanine to connectors on GR TMTC Front Panel Figure 2 2 shows the completed GR TMTC assembly including the cabling and harness to the front panel Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 10 Pp Ai ii 42 Mn H Hz c 2007 PED Figure 2 2 GR CPCI XC4V board with GR TMTC FLEX Mezzanine and front panel 2 2 Configuration for FPGA VLDS signals In the GR TM
16. ing and naming for this connector has been defined to be compoatible with the i TMTC AUX 26 pin shrouded 0 1 header Table 3 1 List of Front Panel Connectors GA CPC J3 FPGA J2 ETH Figure 3 1 Front Panel view Pin1 s marked with red circle Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 12 Pin Name Comment 1 No connect 6 No connect 2 DSU TX Transmit pin from DSU UART 7 No connect 3 DSU RX Receive pin to DSU UART 8 No connect 4 No connect 9 No connect 5 GND Ground Table 3 2 J1 DSU Debug Support Unit connections Pin Name Comment 1 TPFOP Output ve 2 TPFON Output ve 3 TPFIP Input ve 4 TPFOC Output center tap 5 No connect 6 TPFIN Input ve 7 TPFIC Input Center tap 8 No connect Table 3 3 J2 RJ45 ETHERNET Connector Pin Name Comment 1 DGND Ground 2 VREF VREF 3 3V 3 DGND Ground 4 TMS PROG JTAG TMS or Slave serial PROG 5 DGND Ground 6 TCK CCLK JTAG TCK or Slave serial CCLK 7 DGND Ground 8 TDO DONE JTAG TDO or Slave serial DONE 9 DGND Ground 10 TDI DIN JTAG TDI or Slave serial DIN 11 DGND Ground 12 NC NC No connect 13 DGND Ground 14 NC INIT JTAG no connect or Slave serial INIT Table 3 4 J3 FPGA Programming Connector Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine
17. onnections Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 21 HE ER GE GE ma ua Jil 11 n 11 FID2 E Deno O BRDYN c 2007 PED 8 B 2 7 Figure 3 5 Mezzanine Photo Bottom view Pender Electronic Design GmbH Rev 0 1
18. rd observe appropriate precautions and ESD safe practices When not in use store the board in an electrostatic protective container or bag When configuring the jumpers on the board or connecting disconnecting cables ensure that the board is in an unpowered state 1 4 Abbreviations ESD Electro Static Discharge FPGA Field Programmable Gate Array FT Fault Tolerant GPIO General Purpose Input Output I O Input Output LVDS Low Voltage Digital Signaling PCB Printed Circuit Board SPW Spacewire Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 8 2 ELECTRICAL DESIGN 2 1 Block Diagram The GR TMTC assembly provides the electrical functions and interfaces as represented in the block diagram Figure 2 1 GR CPCI XC4V GR CPCI RS232 FPGA DEVELOPMENT BOARD ACCESSORY BOARD a UART I F GR TMTC MEZZANINE BOARD LVDS DRIVER BUS SPW 1 MDM9 S MDM9 S RECEIVERS SPW I F amp ITERMINATION mes ni RS422 DIFFERENTIAL PAIRS 4 TMTC I F Q a 25 TMTC 5 AUX 5 LVTTL SIGNALS GR TMTC FRONT PANEL Figure 2 1 Block Diagram of GR TMTC assembly and harness Pender Electronic Design GmbH Rev 0 1 GR TMTC Mezzanine User Manual 9 As shown in the block diagram the GR TMTC Mezzanine contains the following circuits 40Mbit IMWord x 40 bit SRAM memory 10ns 8 pin DIL socket and SMA connector for user defined oscillator Headers for 2 x 16 General Purpose I O s
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GR TMTC MEZZ