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Z8 Encore!™ Microcontrollers with Flash Memory and 10

1. Z8 Encore Z 211 ZiLOG Ordering Information Table 128 Ordering Information Flash RAM Max Speed Temp Voltage Part KB Bytes KB Bytes MHz C V Package Part Number Z8 Encore with 16KB Flash Standard Temperature Z8 16 16 384 2 2048 20 Oto 70 3 0 3 6 PDIP 40 Z8F1601PMO20SC Z8 16 16 384 2 2048 20 0to 70 3 0 3 6 LQFP 44 Z8F1601ANO20SC 78 16 16 384 2 2048 20 0to 70 3 0 3 6 PLCC 44 Z8F1601VNO20SC Z8 16 16 384 2 2048 20 0to 70 3 0 3 6 LQFP 64 Z8F1602AR020SC Z8 16 16 384 2 2048 20 0to 70 3 0 3 6 PLCC 68 Z8F1602VS020SC Z8 Encore with 24KB Flash Standard Temperature Z8 24 24 576 2 2048 20 Oto 70 3 0 3 6 PDIP 40 Z8F2401PMO20SC Z8 24 24 576 2 2048 20 0to 70 3 0 3 6 LQFP 44 Z8F2401ANO20SC 78 24 24 576 2 2048 20 0to 70 3 0 3 6 PLCC 44 Z8F2401VNO20SC 78 24 24 576 2 2048 20 0to 70 3 0 3 6 LQFP 64 Z8F2402AR020SC Z8 24 24 576 2 2048 20 0to 70 3 0 3 6 PLCC 68 Z8F2402VS020SC Z8 Encore with 32KB Flash Standard Temperature Z8 32 32 768 2 2048 20 Oto 70 3 0 3 6 PDIP 40 Z8F3201PMO20SC Z8 32 32 768 2 2048 20 0to 70 3 0 3 6 LQFP 44 Z8F3201ANO20SC Z8 32 32 768 2 2048 20 0to 70 3 0 3 6 PLCC 44 Z8F3201VNO20SC Z8
2. BITS 7 6 5 4 3 2 1 0 FIELD ADCD L Reserved RESET x x R W R R ADDR F73H ADCD_L ADC Data Low Bits These are the least significant two bits of the 10 bit ADC output During a conversion this value is invalid These bits are undefined after a Reset Reserved These bits are reserved and are always undefined PS017610 0404 Analog to Digital Converter Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 138 ZiLOG Flash Memory Overview The Z8F640x family features up to 64KB 65 536 bytes of non volatile Flash memory with read write erase capability The Flash Memory can be programmed and erased in cir cuit by either user code or through the On Chip Debugger The Flash memory array is arranged in pages with 512 bytes per page The 512 byte page is the minimum Flash block size that can be erased Each page is divided into 8 rows of 64 bytes The Flash memory also contains a High Sector that can be enabled for writes and erase separately from the rest of the Flash array The first 2 bytes of the Flash Program memory are used as Option Bits Refer to the Option Bits chapter for more information on their operation Table 83 describes the Flash memory configuration for each device in the Z8F640x fam ily Figure 84 illustrates the Flash memory arrangement Table 83 Z8F640x family Flash Memory Configurations Flash Size Flash Program Memory Flash High Sector Size High Sector
3. 1 Port Value Changes to 0 0 Value May Be Read From Port Input Data Register Figure 93 Port Input Sample Timing Table 107 GPIO Port Input Timing Delay ns Parameter Abbreviation Minimum Maximum Ts Port Input Transition to XIN Rise Setup Time 5 Not pictured Tu PORT XIN Rise to Port Input Transition Hold Time 3 Not pictured TSMR GPIO Port Pin Pulse Width to Insure Stop Mode Recovery lus for GPIO Port Pins enabled as SMR sources PS017610 0404 Electrical Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore ZiLOG General Purpose I O Port Output Timing Figure 94 and Table 108 provide timing information for GPIO Port pins TCLK a XIN TP E fe ren M _ Figure 94 GPIO Port Output Timing Table 108 GPIO Port Output Timing Delay ns Parameter Abbreviation Minimum Maximum 15 T5 XIN Rise to Port Output Hold Time 2 Rise to Port Output Valid Delay PS017610 0404 Electrical Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 211 08 On Chip Debugger Timing Figure 95 and Table 109 provide timing information for DBG pins The timing specifica tions presume a rise and fall time on of less than 4 5 TCLK ag XIN d Output Data utput 1 1 T3 T
4. 189 Load Instructions 189 Logical Instructions 190 Program Control 190 Rotate and Shift Instructions 191 eZ8 CPU Instruction Summary 191 Opcode Map Abbreviations 203 Ordering Information 211 Z8 Encore 211 08 List of Tables Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Manual Objectives This Product Specification provides detailed operating information for the Z8F640x Z8F480x Z8F320x Z8F240x and Z8F160x devices within the Z8 Encore Microcon troller MCU family of products Within this document the Z8F640x Z8F480x Z8F320x Z8F240x and Z8F160x are referred to collectively as Z8 Encore or the Z8F640x family unless specifically stated otherwise About This Manual ZiLOG recommends that the user read and understand everything in this manual before setting up and using the product However we recognize that there are different styles of learning Therefore we have designed this Product Specification to be used either as a how to procedural manual or a reference guide to important data Intended Audience This document is written for ZiLOG customers who are experienced at working with microcontrollers integrated circuits or printed circuit assemblies Manual Conventions
5. CTS Figure 67 UART Block Diagram Operation Data Format Zi ZiLOG The UART always transmits and receives data in an 8 bit data format least significant bit first An even or odd parity bit can be optionally added to the data stream Each character begins with an active Low Start bit and ends with either 1 or 2 active High Stop bits PS017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG Figures 68 and 69 illustrates the asynchronous data format employed by the UART with out parity and with parity respectively T Data Field StopBit s Idle State of Line msb 1 of Bito Bit Bite Bit3 Bit4 Bit5 Bit6 Bit7 0 2 Figure 68 UART Asynchronous Data Format without Parity p Data Field hal Stop Bit s Idle State of Line 26 Bito Bit1 Bit2 Bit3 Bit4 Bit5 Ys Bit7 0 ES l 1 2 Figure 69 UART Asynchronous Data Format with Parity Transmitting Data using the Polled Method Follow these steps to transmit data using the polled method of operation 1 Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate 2 Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation 3 Write to the UART Control register to enable Multiprocessor 9
6. Part Number KB Bytes Pages Addresses KB Bytes Addresses 78 160 16 16 384 32 0000H 3FFFH 1 1024 3C00H 3FFFH Z8F240x 24 24 576 48 0000H SFFFH 2 2048 5800H 5 Z8F320x 32 32 768 64 0000H 7FFFH 2 2048 7800H 7FFFH Z8F480x 48 49 152 96 0000H BFFFH 4 4096 BOOOH BFFFH Z8F640x 64 65 536 128 0000H FFFFH 8 8192 E000H FFFFH PS017610 0404 Flash Memory Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 64KB Flash Program Memory Addresses FFFFH FEO0H FDFFH FCOOH FBFFH 1 128 Pages 512 Bytes per Page 1 05 0400H 0200H 01FFH Y 0000H Figure 84 Flash Memory Arrangement Operation The Flash Controller programs and erases the Flash memory The Flash Controller pro vides the proper Flash controls and timing for byte programming Page Erase and Mass Erase of the Flash memory The Flash Controller contains a protection mechanism via the Flash Control register FCTL to prevent accidental programming or erasure The Flow Chart in Figure 85 illustrates basic Flash Controller operation The following subsections provide details on the various operations Lock Unlock Byte Programming Page Erase and Mass Erase listed in Figure 85 PS017610 0404 Flash Memory Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Reset t Lock St
7. 32 32 768 2 2048 20 0to 70 3 0 3 6 LQFP 64 Z8F3202AR020SC Z8 32 32 768 2 2048 20 0to 70 3 0 3 6 PLCC 68 Z8F3202VS020SC Z8 Encore with 48KB Flash Standard Temperature Z8 48 49 152 4 4096 20 Oto 70 3 0 3 6 PDIP 40 Z8F4801PMO20SC 78 48 49 152 4 4096 20 0to 70 3 0 3 6 LQFP 44 Z8F4801ANO20SC Z8 48 49 152 4 4096 20 Oto 70 3 0 3 6 PLCC 44 Z8F4801VNO20SC Z8 48 49 152 4 4096 20 70 3 0 3 6 LQFP 64 Z8F4802AR020SC 78 48 49 152 4 4096 20 010 70 3 0 3 6 PLCC 68 Z8F4802VS020SC Z8 48 49 152 4 4096 20 Oto 70 3 0 3 6 QFP 80 Z8F4803FT020SC PS017610 0404 Ordering Information Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 7 212 ZiLoG Table 128 Ordering Information Continued Flash RAM Max Speed Temp Voltage Part KB Bytes KB Bytes MHz C V Package Part Number Z8 Encore with 64KB Flash Standard Temperature 78 64 65 536 4 4096 20 70 3 0 3 6 PDIP 40 Z8F6401PM020SC 78 64 65 536 4 4096 20 0 to 70 3 0 3 6 LQFP 44 Z8F6401ANO20SC 78 64 65 536 4 4096 20 70 3 0 3 6 PLCC 44 Z8F6401VNO20SC 78 64 65 536 4 4096 20 Oto 70 3 0 3 6 LQFP 64 Z8F6402AR020SC Z8 64 65 536 4 4096 20 0 to 70 3
8. Operating Mode Stop Mode Recovery Source Action Stop mode Watch Dog Timer time out Stop Mode Recovery when configured for Reset Watch Dog Timer time out Stop Mode Recovery followed by interrupt if when configured for interrupt interrupts are enabled Data transition on any GPIO Port pin Stop Mode Recovery enabled as a Stop Mode Recovery source Stop Mode Recovery Using Watch Dog Timer Time Out If the Watch Dog Timer times out during Stop mode the Z8F640x family device under goes a STOP Mode Recovery sequence In the Watch Dog Timer Control register the WDT and STOP bits are set to 1 If the Watch Dog Timer is configured to generate an inter rupt upon time out and the device is configured to respond to interrupts the Z8F640x fam ily device services the Watch Dog Timer interrupt request following the normal Stop Mode Recovery sequence PS017610 0404 Reset and Stop Mode Recovery Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG Stop Mode Recovery Using a GPIO Port Pin Transition Each of the GPIO Port pins may be configured as a Stop Mode Recovery input source On any GPIO pin enabled as a Stop Mode Recover source a change in the input pin value from High to Low or from Low to High initiates Stop Mode Recovery In the Watch Dog Timer Control register the STOP bit is set to 1 Caution In Stop mode the GPIO Port Input Data registers PxIN are disabled The Port Input Data registers record th
9. Part Flash RAM 16 bit Timers ADC UARTS 40 44 pin 64 68 pin 80 pin Number KB KB IO with PWM Inputs with IrDA PC SPI packages packages package Z8F1601 16 2 31 3 8 2 1 1 X Z8F1602 16 2 46 4 12 2 1 1 X Z8F2401 24 2 31 3 8 2 1 1 X Z8F2402 24 2 46 4 12 2 1 1 X Z8F3201 32 2 31 3 8 2 1 1 X Z8F3202 32 2 46 4 12 2 1 1 X Z8F4801 48 4 31 3 8 2 1 1 X Z8F4802 48 4 46 4 12 2 1 1 X Z8F4803 48 4 60 4 12 2 1 1 X Z8F6401 64 4 31 3 8 2 1 1 X Z8F6402 64 4 46 4 12 2 1 1 X Z8F6403 64 4 60 4 12 2 1 1 X PS017610 0404 Introduction Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 7 211 08 Block Diagram Figure 55 illustrates the block diagram of the architecture of the Z8 XTAL RC On Chip Oscillator 4 Y Y Debugger 78 POR VBO amp Reset CPU Interrupt WDT with System lt 9 Controller Controller RC Oscillator Memory Busses Register Bus Timers UARTs IPC SPI Flash RAM Controller Controller IrDA Flash i Memory RAM GPIO Figure 55 Z8 Encore Block Diagram CPU and Peripheral Overview eZ8 CPU Features The eZ8 ZiLOG s latest 8 bit Central Processing Unit CPU meets the continuing demand for faster and more code efficient microcontrollers The eZ8 CPU executes a superset of th
10. 164 OCD Watchpoint Data Register 164 On Chip Oscillator csse o Sse a e e re eee cin oS ape es Sarees eae 165 20MHz Crystal Oscillator 165 Electrical Characteristics cece cree eee nn 167 Absolute Maximum Ratings 167 DC Characteristics cerna haart ted He tie aed ae ver tk ees 169 AG Charactensues lt sites oec o oL P XY Rr 172 On Chip Peripheral AC and DC Electrical Characteristics 173 General Purpose I O Port Input Data Sample Timing 176 General Purpose Port Output Timing 177 On Chip Debugger Timing 178 SPI Master Mode Timing 179 SPI Slave Mode Timing 180 I2C Timing ese 181 eZ8 CPU Instruction Set 182 Assembly Language Programming Introduction 182 PS017610 0404 Z8 Encore 211 08 Table of Contents Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 211 08 Assembly Language Syntax 183 eZ8 CPU Instruction 183 Condition Codes eoru 186 eZ8 CPU Instruction Classes 187 eZ8 CPU Instruction Summary 191 Flags RegisteE 212 RR PRU
11. EEG 201 Opcode MAPS edes enero edi Eon eq e e ie NOR ale ears e RU 202 Packaging i e rere En die On OR o RR I cei 206 Ordering Information 211 Part Number Description 214 Precharacterization Product 215 Document Information eee ee ee nnn 215 Document Number Description 215 Customer Feedback 216 PS017610 0404 Table of Contents Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 017610 0404 78 Encore Block Diagram eee REESE digi keene 3 Z8Fxx01 in 40 Pin Dual Inline Package DIP 7 Z8Fxx01 in 44 Pin Plastic Leaded Chip Carrier PLCC 8 Z8Fxx01 in 44 Pin Low Profile Quad Flat Package LQFP 9 Z8Fxx02 in 64 Pin Low Profile Quad Flat Package LQFP 10 Z8Fxx02 in 68 Pin Plastic Leaded Chip Carrier PLCC 11 Z8Fxx03 in 80 Pin Quad Flat Package 12 Power On Reset Operation 27 Voltage Brown Out Reset Operation
12. PADxENH Port A or Port D Bit x Interrupt Request Enable High Bit Refer to the Interrupt Port Select register for selection of either Port A or Port D as the interrupt source Table 31 IRQ1 Enable Low Bit Register IRQIENL BITS 7 6 5 4 3 2 1 0 FIELD PAD7ENL PADOENL PADSENL PAD4ENL PAD3ENL PAD2ENL PADIENL PADOENL RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR 5 PADxENL Port A or Port D Bit x Interrupt Request Enable Low Bit Refer to the Interrupt Port Select register for selection of either Port A or Port D as the interrupt source IRQ2 Enable High and Low Bit Registers The IRQ2 Enable High and Low Bit registers Tables 33 and 34 form a priority encoded enabling for interrupts in the Interrupt Request 2 register Priority is generated by setting bits in each register Table 32 describes the priority control for IRQ2 Table 32 IRQ2 Enable and Priority Encoding IRQ2ENH x IRQ2ENL x Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Nominal 1 1 Level3 High where x indicates the register bits from 0 through 7 PS017610 0404 Interrupt Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 54 ZiLOG Table 33 IRQ2 Enable High Bit Register IRQ2ENH BITS 7 6 5 4 3 2 1 0 FIELD T3ENH UIRENH UITENH DMAENH C3ENH C2ENH CIENH COENH RESET 0
13. 145 Flash Page Select Register 146 Flash Frequency High and Low Byte Registers 147 PS017610 0404 Table of Contents Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Option Bits 148 Bas 148 Operation s arnie i ame ARRE EANA 148 Option Bit Configuration By 148 Option Bit Address Space 148 Program Memory Address 0000H 149 Program Memory Address 0001H 150 On Chip Debugger a dre E a RR a 151 OVELVIEW sete eee 151 Architecture ET 151 Operation suir aidan rre n des 152 OCD Interface 152 Debus Mode 153 OCD Data Format 154 OCD Auto Baud Detector Generator 154 OCD Serial Errors eec Ree 155 Breakpoifits 155 WatchpointS Sine as 155 Runtime Counter ALES e a ROREM ods 156 On Chip Debugger Commands 156 On Chip Debugger Control Register Definitions 161 OCD Control Register assecc iieri eee eee 161 OCD Status Register cee eee cee eee 162 OCD Watchpoint Control 163 OCD Watchpoint Address Register
14. 2 211 08 IRQO Enable High and Low Bit Registers The IRQO Enable High and Low Bit registers Tables 27 and 28 form a priority encoded enabling for interrupts in the Interrupt Request 0 register Priority is generated by setting bits in each register Table 26 describes the priority control for IRQO Table 26 IRQ0 Enable and Priority Encoding IRQOENH x IRQOENL x Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Nominal 1 1 Level 3 High where x indicates the register bits from 0 through 7 Table 27 IRQ0 Enable High Bit Register IRQOENH BITS 7 6 5 4 3 2 1 0 FIELD 2 TIENH TOENH UORENH UOTENH I2CENH SPIENH ADCENH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FCIH T2ENH Timer 2 Interrupt Request Enable High Bit T1ENH Timer 1 Interrupt Request Enable High Bit Timer 0 Interrupt Request Enable High Bit UORENH UART 0 Receive Interrupt Request Enable High Bit UOTENH UART 0 Transmit Interrupt Request Enable High Bit I2CENH I C Interrupt Request Enable High Bit SPIENH SPI Interrupt Request Enable High Bit ADCENH ADC Interrupt Request Enable High Bit PS017610 0404 Interrupt Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Table 28 IRQ0 Enable Low Bit Register IRQOENL Zi 211 08 7 6 5 4 3 2 1 0
15. Q a a 2 3 r Ir 43 2 4 R R 44 3 3 R IR 45 3 4 R IM 46 3 3 IR IM 47 3 4 ORX dst src dst dst OR src ER ER 48 0 4 3 ER IM 49 4 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 197 21108 Table 126 eZ8 CPU Instruction Summary Continued Address Mode Flags Assembly Opcode s Fetch Instr Mnemonic Symbolic Operation dst src Hex Z S V D Cycles Cycles POP dst dst lt SP R 50 MM I SL 2 2 SP SP 1 IR 51 5 3 POPX dst dst lt SP D8 M I SL 3 2 lt 5 1 PUSH src SP lt SP 1 R 70 MM I SL 2 2 QSP lt src IR m 2 3 PUSHX src SP lt SP 1 ER C8 DLE ZZ SLE 3 2 SP src RCF Cc 0 CF 0 e 1 2 lt SP MM I SL 1 4 SP lt 5 2 n 5 HEC RLC dst R 10 o ek ks dee dms ue 2 2 IR T 2 3 RR dst R EO Wo OR RS m 2 2 ipeo prios IR El 2 3 RRC dst R CO NT 2 2 IR Cl 2 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Table 126 eZ8 CPU
16. XORX dst src Logical Exclusive OR using Extended Addressing Table 124 Program Control Instructions Mnemonic Operands Instruction BRK On Chip Debugger Break BTJ p bit src DA Bit Test and Jump BTJNZ bit src DA Bit Test and Jump if Non Zero BTJZ bit src DA Bit Test and Jump if Zero CALL dst Call Procedure DJNZ dst src RA Decrement and Jump Non Zero IRET Interrupt Return JP dst Jump JP cc dst Jump Conditional JR DA Jump Relative JR cc DA Jump Relative Conditional RET Return TRAP vector Software Trap PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Table 125 Rotate and Shift Instructions Mnemonic Operands Instruction BSWAP dst Bit Swap RL dst Rotate Left RLC dst Rotate Left through Carry RR dst Rotate Right RRC dst Rotate Right through Carry SRA dst Shift Right Arithmetic SRL dst Shift Right Logical SWAP dst Swap Nibbles eZ8 CPU Instruction Summary Table 126 summarizes the eZ8 CPU instructions The table identifies the addressing modes employed by the instruction the effect upon the Flags register the number of CPU clock cycles required for the instruction fetch and the number of CPU clock cycles required for the instruction execution Table 126 eZ8 CPU Instruction Summary Assembly Address Mode Opcode s Flags Fetc
17. 95 Watch Dog Timer Reload Upper High and Low Byte Registers 76 UART 78 OVEIVIEW cele RR EI eU YT ep Te need dei ERO RC hoes 78 Architecture T T 78 79 Data Format 79 Transmitting Data using the Polled Method 80 Transmitting Data using the Interrupt Driven Method 81 Receiving Data using the Polled Method 82 Receiving Data using the Interrupt Driven Method 82 Receiving Data using the Direct Memory Access Controller 83 Multiprocessor 9 61 Mode 84 UART Inteir pts 22e 85 UART Baud Rate 85 UART Control Register Definitions 86 UARTXx Transmit Data Register 86 UARTx Receive Data 87 UARTX Status 0 and Status 1 Registers 87 UARTX Control 0 and Control 1 89 UARTx Baud Rate High and Low Byte Registers 91 Infrared Encoder Decoder 95 OVERVIEW cce Ados DOG CIS P eder 95 Architecture PEDI 95 Operation EO ER EORR ERR 96 PS017610 0404 Table of Contents Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore VAR ZiLOG Transmi
18. ZiLOG Table 6 provides the address map for the Register File of the Z8F640x family of products Not all devices and package styles in the Z8F640x family support Timer 3 and all of the GPIO Ports Consider registers for unimplemented peripherals as Reserved Table 6 Register File Address Map Address Hex Register Description Mnemonic Reset Hex Page General Purpose RAM 000 EFF General Purpose Register File RAM XX Timer 0 F00 Timer 0 High Byte TOH 00 66 F01 Timer 0 Low Byte TOL 01 66 F02 Timer 0 Reload High Byte TORH FF 67 F03 Timer 0 Reload Low Byte TORL FF 67 F04 Timer 0 PWM High Byte TOPWMH 00 69 F05 Timer 0 PWM Low Byte TOPWML 00 69 F06 Reserved XX F07 Timer 0 Control TOCTL 00 70 Timer 1 F08 Timer 1 High Byte TIH 00 66 F09 Timer 1 Low Byte TIL 01 66 F0A Timer 1 Reload High Byte TIRH FF 67 Timer 1 Reload Low Byte TIRL FF 67 FOC Timer 1 PWM High Byte TIPWMH 00 69 FOD Timer 1 PWM Low Byte TIPWML 00 69 FOE Reserved XX FOF Timer 1 Control TICTL 00 70 Timer 2 F10 Timer 2 High Byte T2H 00 66 Fil Timer 2 Low Byte T2L 01 66 F12 Timer 2 Reload High Byte T2RH FF 67 F13 Timer 2 Reload Low Byte T2RL FF 67 F14 Timer 2 PWM High Byte T2PWMH 00 69 F15 Timer 2 PWM Low Byte T2PWML 00 69 F16 Reserved XX F17 Timer 2 Control T2CTL 00 70 XX Undefined PS017610 0404 Register File Address Map Z8F640x Z8F480x Z8F320x
19. 114 Reading a Transaction with a 7 Bit Address 115 Reading a Transaction with a 10 Bit Address 116 I2C Control Register 118 PC Data Register 3 2 deny cet ee aed es 118 DC Status Register 118 I2C Control Register 0 0 0 0 eee eee 119 I2C Baud Rate High and Low Byte Registers 121 Direct Memory Access Controller 122 OV EEVIC We scone aM dup ade 122 Operation RE Re e PORE RO RF E NR 122 DMAO Operation 122 Configuring DMAO DMAI for Data 123 PS017610 0404 Table of Contents Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 DMA_ADC Operation 123 Configuring DMA_ADC for Data Transfer 124 DMA Control Register Definitions 124 DMAx Control Register 124 DMAx I O Address Register 125 DMAx Address High Nibble Register 126 DMAx Start Current Address Low Byte Register 127 DMAx End Address Low Byte Register 128 DMA_ADC Address Register 128 DMA_ADC Control Register 130 Status Register 131 Analog to Di
20. 28 GPIO Port Pin Block 34 Interrupt Controller Block Diagram 46 Timer Block Diagram 58 UART Block Diagram 79 UART Asynchronous Data Format without Parity 80 UART Asynchronous Data Format with Parity 80 UART Asynchronous Multiprocessor 9 bit Mode Data Format ss ssis ieee eee he whee UES Deke eR Ra 84 Infrared Data Communication System Block Diagram 95 Infrared Data Transmission 97 Infrared Data 98 SPI Configured as a Master in a Single Master Single Slave Syst m 99 SPI Configured as a Master in a Single Master Multiple Slave 100 SPI Configured as a Slave 100 SPI Timing When PHASE is 0 103 SPI Timing When PHASE isl 104 7 Bit Addressed Slave Data Transfer Format 113 10 Bit Addressed Slave Data Transfer Format 114 Receive Data Transfer Format for a 7 Bit Addressed Slave 0 2 115 Receive Data Format for a 10 Bit Addressed Slave 116 Analog to Digital Converter Block Diagram 133 Flash Memory Arrangement 139 Z8 Encore List of Figures Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36
21. 4 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 Ifusing the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 6 Write to the Timer Control register to enable the timer and initiate counting In One Shot mode the system clock always provides the timer input The timer period is given by the following equation One Shot Mode Time Out Period s Reload Value Start Value x Prescale System Clock Frequency Hz Continuous Mode In Continuous mode the timer counts up to the 16 bit Reload value stored in the Timer Reload High and Low Byte registers The timer input is the system clock Upon reaching the Reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low upon timer Reload The steps for configuring a timer for Continuous mode and initiating the count are as fol lows 1 Write to the Timer Control register to Disable the timer Configure the timer for Continuous mode Set the prescale value PS017610 0404 Timers Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG If using the Timer Output alternate function set the initial output level High or
22. 4 Write to the Interrupt control registers to enable the UART Transmitter interrupt and set the desired priority 5 Wirite to the UART Control 1 register to enable Multiprocessor 9 bit mode functions if desired 6 Wirite to the UART Control 0 register to Set the transmit enable bit TEN to enable the UART for data transmission Enable parity if desired and select either even or odd parity Setorclear the CTSE bit to enable or disable control from the receiver via the CTS pin 7 Execute an El instruction to enable interrupts The UART is now configured for interrupt driven data transmission When the UART Transmit interrupt is detected the associated interrupt service routine ISR should per form the following 8 Write the data byte to the UART Transmit Data register The transmitter will automatically transfer the data to the Transmit Shift register and transmit the data 9 Clear the UART Transmit interrupt bit in the applicable Interrupt Request register 10 Execute the IRET instruction to return from the interrupt service routine and wait for the Transmit Data register to again become empty 017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Receiving Data using the Polled Method Follow these steps to configure the UART for polled data reception l Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate Enable the UART pin fu
23. 7 39 PA7 SDA 2 PD6 CTS1 PC2 S55 PC3 SCK RESET VSS VDD I VDD VSS 12 34 PC7 T20UT PD1 T2IN PDO DBG XOUT I PC1 T1OUT XIN PCO T1IN VDD 17 29 VSS 18 23 28 rT T T T T T TTL TI Qo rc00 wL WN C x lt lt lt o SZ22222222e5 gt lt lt lt lt lt lt lt lt 4 gt lt Or st i0 cn cn cO co cn Figure 57 Z8Fxx01 in 44 Pin Plastic Leaded Chip Carrier PLCC 017610 0404 Signal and Pin Descriptions Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 9 ZiLOG 5 DD a amp _ lt lt lt c o0o n0 nn nannnnn js 28 5 TOIN 34 22 PA7 SDA PD2 PD6 CTS1 PC2 SS PC3 SCK RESET VSS VDD VDD vss 39 17 _ PC7 T OUT PD1 PC6 T2IN DBG XOUT PC1 T1OUT XIN PC0O T1IN VDD 44 12 VSS 1 6 11 Lud a Or sb i0 Q QN LL a lt ox ox oc x ox X X ogg 22222225569 lt lt ta Or st i10 ONON cn cO cO CO a Note Timer 3 is not supported ooaaanaaa Figure 58 Z8Fxx01 in 44 Pin Low Profile Quad Flat Package LQFP PS017610 0404 Signal and Pin Descriptions Z8F640x Z8F480x Z8F320x Z8F240x Z8F
24. Data Memory Address 15 8 lt Data Memory Address 7 0 Size 15 8 DBG Size 7 0 DBG 1 65536 data bytes On Chip Debugger 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Read Data Memory 0DH The Read Data Memory command reads from Data Memory This command is equivalent to the LDE and LDEI instructions Data can be read 1 65536 bytes at a time 65536 bytes can be read by setting size to zero If the Z8F640x family device is not in Debug mode this command returns FFH for the data DBG ODH lt Data Memory Address 15 8 Data Memory Address 7 0 DBG Size 15 8 DBG Size 7 0 gt 1 65536 data bytes Read Program Memory CRC 0EH The Read Program Memory CRC command computes and returns the CRC cyclic redundancy check of Program Memory using the 16 bit CRC CCITT polynomial If the Z8F640x family device is not in Debug mode this command returns FFFFH for the CRC value Unlike most other OCD Read commands there is a delay from issuing of the command until the OCD returns the data The OCD reads the Program Memory calculates the CRC value and returns the result The delay is a function of the Program Memory size and is approximately equal to the system clock period multiplied by the number of bytes in the Program Memory DBG gt CRC 15 8 DBG CRC 7 0 Step Instruction 10H
25. The following assumptions and conventions are adopted to provide clarity and ease of use Courier Typeface Commands code lines and fragments bits equations hexadecimal addresses and various executable items are distinguished from general text by the use of the Courier typeface Where the use of the font is not indicated as in the Index the name of the entity is pre sented in upper case e Example FLAGS 1 15 smr Hexadecimal Values Hexadecimal values are designated by uppercase H suffix and appear in the Courier typeface e Example R1 is set to F8H Brackets The square brackets indicate a register or bus Example for the register R1 7 0 R1 is an 8 bit register R1 7 is the most significant bit and R1 0 is the least significant bit PS017610 0404 Manual Objectives Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 211 08 The curly braces indicate a single register or bus created by concatenating some com bination of smaller registers buses or individual bits e Example the 12 bit register address RP 7 4 R1 3 0 is composed of a 4 bit hexadecimal value 0H and two 4 bit register values taken from the Register Pointer RP and Working Register R1 0H is the most significant nibble 4 bit value of the 12 bit register and R1 3 0 is the least significant nibble of the 12 bit register Parentheses The parentheses indicate an indirect register add
26. eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Table 121 CPU Control Instructions Mnemonic Operands Instruction CCF Complement Carry Flag DI Disable Interrupts EI Enable Interrupts HALT Halt Mode NOP x No Operation RCF x Reset Carry Flag SCF Set Carry Flag SRP src Set Register Pointer STOP Stop Mode WDT Watch Dog Timer Refresh Table 122 Load Instructions Mnemonic Operands Instruction CLR dst Clear LD dst src Load LDC dst src Load Constant to from Program Memory LDCI dst src Load Constant to from Program Memory and Auto Increment Addresses LDE dst src Load External Data to from Data Memory LDEI dst sre Load External Data to from Data Memory and Auto Increment Addresses LDX dst src Load using Extended Addressing LEA dst X src Load Effective Address POP dst Pop POPX dst Pop using Extended Addressing PUSH src Push PUSHX src Push using Extended Addressing PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Table 123 Logical Instructions Mnemonic Operands Instruction AND dst src Logical AND ANDX dst src Logical AND using Extended Addressing COM dst Complement OR dst src Logical OR ORX dst src Logical OR using Extended Addressing XOR dst src Logical Exclusive OR
27. BITS 7 6 5 4 3 2 1 0 FIELD TEN REN CTSE PEN PSEL SBRK STOP LBEN RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F42H and F4AH TEN Transmit Enable This bit enables or disables the transmitter The enable is also controlled by the CTS signal and the CTSE bit If the CTS signal is low and the CTSE bit is 1 the transmitter is enabled 0 Transmitter disabled 1 Transmitter enabled REN Receive Enable This bit enables or disables the receiver 0 Receiver disabled 1 Receiver enabled PS017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG CTSE CTS Enable 0 The CTS signal has no effect on the transmitter 1 The UART recognizes the CTS signal as an enable control from the transmitter PEN Parity Enable This bit enables or disables parity Even or odd is determined by the PSEL bit 0 Parity is disabled 1 The transmitter sends data with an additional parity bit and the receiver receives an additional parity bit PSEL Parity Select 0 Even parity is transmitted and expected on all received data 1 Odd parity is transmitted and expected on all received data SBRK Send Break This bit pauses or breaks data transmission Sending a break interrupts any transmission in progress so insure that the transmitter has finished sending data before setting this bit 0 No break is sent 1 The output of the transmitter is zero STOP Stop Bit
28. Enable the ADC interrupt request if desired Select the number of ADC Analog Inputs to convert Enable the DMA ADC channel Caution When using the DMA ADC to perform conversions on multiple ADC in puts and the IN field in the DMA_ADC Control Register is greater than 000b the Analog to Digital Converter must be configured for Single Shot mode Continuous mode operation of the ADC can only be used in conjunction with DMA_ADC if the ADC IN field in the DMA_ADC Control Register is reset to 000b to enable conversion on ADC Analog Input 0 only DMA Control Register Definitions DMAx Control Register The DMAx Control register is used to enable and select the mode of operation for DMAx Table 71 DMAx Control Register DMAxCTL BITS 7 6 5 4 3 2 1 0 FIELD DEN DLE DDIR IRQEN WSEL RSS RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FBOH FB8H DEN DMAx Enable 0 DMAx is disabled and data transfer requests are disregarded PS017610 0404 Direct Memory Access Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z6 211 08 1 DMAx is enabled and initiates a data transfer upon receipt of a request from the trigger source DLE DMAx Loop Enable 0 DMAx reloads the original Start Address and is then disabled after the End Address data is transferred 1 DMAx after the End Address data is transferred reloads the original St
29. If the TPOL bit in the Timer Control register is set to 0 the Timer Output signal begins as a Low 0 and then transitions to a High 1 when the timer value matches the PWM value The Timer Output signal returns to a Low 0 after the timer reaches the Reload value and is reset to 0001H The steps for configuring a timer for PWM mode and initiating the PWM operation are as follows 1 Write to the Timer Control register to PS017610 0404 Timers Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG Disable the timer Configure the timer for PWM mode Set the prescale value Set the initial logic level High or Low PWM High Low transition for the Timer Output alternate function 2 Write to the Timer High and Low Byte registers to set the starting count value typically 0001H This only affects the first pass in PWM mode After the first timer reset in PWM mode counting always begins at the reset value of 0001H Write to the PWM High and Low Byte registers to set the PWM value 4 Write to the Timer Reload High and Low Byte registers to set the Reload value PWM period The Reload value must be greater than the PWM value 5 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 6 Configure the associated GPIO port pin for the Timer Output alternate function 7 Write to the Timer Control register to enable the timer a
30. PS017610 0404 Manual Objectives Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 211 08 Use of Uppercase Letters The use of all uppercase letters designates the names of states and commands Example 1 The bus is considered BUSY after the Start condition Example 2 A START command triggers the processing of the initialization sequence Bit Numbering Bits are numbered from 0 to n where n indicates the total number of bits For example the 8 bits of a register are numbered from 0 to 7 Safeguards It is important that all users understand the following safety terms which are defined here Caution Indicates a procedure or file may become corrupted if the user does not fol low directions Trademarks ZiLOG eZ8 Z8 Encore and Z8 are trademarks of ZiL OG Inc in the U S A and other countries All other trademarks are the property of their respective corporations PS017610 0404 Manual Objectives Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore ZiLOG Introduction The Z8 Encore MCU family of products are the first in a line of ZiLOG microcontroller products based upon the new 8 bit eZ8 CPU The Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x products are referred to collectively as either Z8 Encore or the Z8F640x fam The Z8F640x family of products introduce Flash memory to ZiLOG s extensive line of 8 bit microcontrollers The Flash in circuit programming capability allows for faster
31. R W R R R R R R R R ADDR F41H and F49H RDA Receive Data Available This bit indicates that the UART Receive Data register has received data Reading the UART Receive Data register clears this bit 0 The UART Receive Data register is empty 1 There is a byte in the UART Receive Data register PE Parity Error This bit indicates that a parity error has occurred Reading the UART Receive Data regis ter clears this bit PS017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 0 No parity error has occurred 1 A parity error has occurred OE Overrun Error This bit indicates that an overrun error has occurred An overrun occurs when new data is received and the UART Receive Data register has not been read If the RDA bit is reset to 0 then reading the UART Receive Data register clears this bit 0 No overrun error occurred 1 An overrun error occurred FE Framing Error This bit indicates that a framing error no Stop bit following data reception was detected Reading the UART Receive Data register clears this bit 0 No framing error occurred 1 A framing error occurred BRKD Break Detect This bit indicates that a break occurred If the data bits parity multiprocessor bit and Stop bit s are all zeros then this bit is set to 1 Reading the UART Receive Data register clears this bit 0 No break occurred 1 A break occurred TDRE Transmitter Data Regi
32. Table 127 Opcode Lower Nibble Fetch Cycles Instruction Cycles 4 3 3 Opcode Upper Nibble 9 CP R2 R1 First Operand Second Operand After Assembly After Assembly Figure 100 Opcode Map Cell Description PS017610 0404 Opcode Maps Table 127 Opcode Map Abbreviations Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Abbreviation Description Abbreviation Description b Bit position IRR Indirect Register Pair cc Condition code p Polarity 0 or 1 X 8 bit signed index or displacement r 4 bit Working Register DA Destination address R 8 bit register ER Extended Addressing register rl R1 11 171 181 rrl Destination address RR1 IRRI ERI IM Immediate data value r2 R2 Ir2 Irr2 IR2 rr2 Source address RR2 IRR2 ER2 Ir Indirect Working Register RA Relative IR Indirect register Working Register Pair Irr Indirect Working Register Pair RR Register Pair PS017610 0404 Opcode Maps 23 ADD rt 24 ADD r1 lr2 3 4 ADD IR2 R1 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Lower Nibble Hex 6 3 3 ADD 7 34 ADD IR1 IM 8 43 ADDX ER2 ER1 9 43 ADDX 1 2 3 ADC 1 2 24 ADC r1 lr2 3 4 ADC IR2 R1 3 3 ADC 34 ADC 4 3 ADCX ER2 ER1 43 ADCX 1 2 3 SUB rt 24 SUB r1 lr2 3 4 SUB IR2 R1 3 3 SUB 34 SUB 4 3 SUBX ER2 ER1 4 3 SUBX
33. The Step Instruction command steps one assembly instruction at the current Program Counter PC location If the Z8F640x family device is not in Debug mode or the Read Protect Option Bit is enabled the OCD ignores this command DBG 10H Stuff Instruction 11H The Stuff Instruction command steps one assembly instruction and allows specification of the first byte of the instruction The remaining 0 4 bytes of the instruction are read from Program Memory This command is useful for stepping over instructions where the first byte of the instruction has been overwritten by a Breakpoint If the Z8F640x family device is not in Debug mode or the Read Protect Option Bit is enabled the OCD ignores this command DBG 11H DBG opcode 7 0 Execute Instruction 12H The Execute Instruction command allows sending an entire instruction to be executed to the eZ8 CPU This command can also step over Breakpoints The number of bytes to send for the instruction depends on the opcode If the Z8F640x family device is not in Debug mode or the Read Protect Option Bit is enabled this command reads and discards one byte DBG 12H DBG 1 5 byte opcode On Chip Debugger Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z4 211 08 Write Watchpoint 20H The Write Watchpoint command sets and configures the debug Watchpoint If the Z8F640x family device is not in Debug mode or the Read Protect Option Bit is enabled the WPT
34. Timer Output 0 3 These signals are output pins from the timers The Timer T20UT T30UT Output signals are multiplexed with general purpose I O pins T2OUT is not supported in the 40 pin package T3OUT is not supported in the 40 and 44 pin packages TOIN TLIN I Timer Input 0 3 These signals are used as the capture gating and counter inputs T2IN T3IN The Timer Input signals are multiplexed with general purpose I O pins T3IN is not supported in the 40 and 44 pin packages Analog 11 0 Analog Input These signals are inputs to the analog to digital converter ADC The ADC analog inputs are multiplexed with general purpose I O pins VREF I Analog to digital converter reference voltage input The VREF pin should be left unconnected or capacitively coupled to analog ground if the internal voltage reference is selected as the ADC reference voltage Oscillators XIN I External Crystal Input This is the input pin to the crystal oscillator A crystal can be connected between it and the XOUT pin to form the oscillator XOUT External Crystal Output This pin is the output of the crystal oscillator A crystal can be connected between it and the XIN pin to form the oscillator When the system clock is referred to in this manual it refers to the frequency of the signal at this pin RCOUT RC Oscillator Output This signal is the output of the RC oscillator It is On Chip Debugger DBG IO multiplexed with a general purpose
35. Watch Dog Timer UART Overview Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 78 ZiLOG The Universal Asynchronous Receiver Transmitter UART is a full duplex communica tion channel capable of handling asynchronous data transfers The Z8F640x family device contains two fully independent UARTs The UART uses a single 8 bit data mode with selectable parity Features of the UART include Architecture 8 bit asynchronous data transfer Selectable even and odd parity generation and checking Option of one or two Stop bits Separate transmit and receive interrupts Framing parity overrun and break detection Separate transmit and receive enables Selectable 9 bit multiprocessor 9 bit mode 16 bit Baud Rate Generator BRG The UART consists of three primary functional blocks transmitter receiver and baud rate generator The UART s transmitter and receiver function independently but employ the same baud rate and data format Figure 67 illustrates the UART architecture PS017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore gt Parity Checker Receiver Control TD Receive Shifter LA Control Register System Bus Ti it D Status Register Baud Rate Generator v Transmit Shift TXD Register Transmitter Control
36. XX Serial Peripheral Interface SPI F60 SPI Data SPIDATA XX 106 F61 SPI Control SPICTL 00 107 XX Undefined 017610 0404 Register File Address Map Table 6 Register File Address Map Continued Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Address Hex Register Description Mnemonic Reset Hex Page F62 SPI Status SPISTAT 01 108 F63 SPI Mode SPIMODE 00 109 F64 F65 Reserved XX F66 SPI Baud Rate High Byte SPIBRH FF 110 F67 SPI Baud Rate Low Byte SPIBRL FF 110 F68 F69 Reserved XX Analog to Digital Converter ADC F70 ADC Control ADCCTL 20 135 F71 Reserved XX F72 ADC Data High Byte ADCD H XX 137 F73 ADC Data Low Bits ADCDL XX 137 F74 FAF Reserved XX DMA 0 FBO DMAO Control DMAOCTL 00 124 1 Address DMAOIO XX 125 FB2 DMAO End Start Address High Nibble DMAOH XX 126 FB3 DMAO Start Address Low Byte DMAOSTART XX 127 FB4 DMAO End Address Low Byte DMAOEND XX 128 DMA 1 FB8 Control DMAICTL 00 124 FB9 DMAI I O Address DMAIIO XX 125 FBA DMAI End Start Address High Nibble DMAIH XX 126 FBB DMAI Start Address Low Byte DMAISTART XX 127 FBC DMAI End Address Low Byte DMAIEND XX 128 DMA ADC FBD DMA_ADC Address DMAA ADDR XX 128 FBE ADC Control DMAACTL 00 130 FBF DMA_ADC Status DMAASTAT 00 131 Interrupt Controller FCO Interrupt Requ
37. Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 SPI Baud Rate High and Low Byte Registers The SPI Baud Rate High and Low Byte registers combine to form a 16 bit reload value BRG 15 0 for the SPI Baud Rate Generator The reload value must be greater than or equal to 00028 for proper SPI operation maximum baud rate is system clock frequency divided by 4 The SPI baud rate is calculated using the following equation SPI Baud Rate bits s System Clock Frequency Hz 2 x BRG 15 0 Table 64 SPI Baud Rate High Byte Register SPIBRH BITS 7 6 5 4 3 2 1 0 FIELD BRH RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR F66H BRH SPI Baud Rate High Byte Most significant byte BRG 15 8 of the SPI Baud Rate Generator s reload value Table 65 SPI Baud Rate Low Byte Register SPIBRL BITS 7 6 5 4 3 2 1 0 FIELD BRL RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R w ADDR F67H 017610 0404 BRL SPI Baud Rate Low Byte Least significant byte BRG 7 0 of the SPI Baud Rate Generator s reload value Serial Peripheral Interface Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 111 ZiLOG PC Controller Overview The Controller makes the Z8F640x family device bus compatible with the Poem pro tocol The Controller consists of two bidirectional bus lines a serial data s
38. ZiLOG Z8F640x Z8F480x Z8F320x Z8F240x and Z8F160x Z8 Encore Microcontrollers with Flash Memory and 10 Bit A D Converter Product Specification PS017610 0404 ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 3432 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com Z ZiLOG This publication is subject to replacement by a later edition To determine whether a later edition exists or to request copies of publications contact ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc in the United States and in other countries All other products and or service names mentioned herein may be trademarks of the companies with which they are associated 2004 by ZiLOG Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZiLOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE Devices sold by ZiLOG Inc are covered by warranty and limitation of liability provisions
39. 001Ch Port A5 or Port D5 rising or falling input edge Single assertion pulse 001Eh Port A4 or Port D4 rising or falling input edge Single assertion pulse 0020h Port A3 or Port D3 rising or falling input edge Single assertion pulse 0022h Port A2 or Port D2 rising or falling input edge Single assertion pulse 0024h Port Al or Port D1 rising or falling input edge Single assertion pulse 0026h Port AO or Port DO rising or falling input edge Single assertion pulse 0028h Timer 3 not available in 40 44 pin packages Single assertion pulse 002Ah UART 1 receiver Continuous assertion 002Ch UART 1 transmitter Continuous assertion 002Eh DMA Single assertion pulse 0030h Port C3 both input edges Single assertion pulse 0032h Port C2 both input edges Single assertion pulse 0034h Port C1 both input edges Single assertion pulse Lowest 0036h Port CO both input edges Single assertion pulse 017610 0404 Interrupt Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Architecture Operation Z8 Encore Z 46 211 08 Figure 65 illustrates a block diagram of the interrupt controller Port Interrupts ue Vector Priority Medium Mux IRQ Request Priority gt Internal Interrupts 1 Interrupt Request Latches and Control Low Jj Priority Figure 65 Interrupt Controller Block Diagram Master Interrupt Enable 017610 0404 The master interrupt enable bit in the Interr
40. 159 read program memory CRC 0EH 160 read register 09H 158 read runtime counter 03H 157 Preliminary Index read watchpoint 21H 161 step instruction 10H 160 stuff instruction 11H 160 write data memory 0CH 159 write OCD control register 04H 158 write program counter 06H 158 write program memory 0AH 159 write register 08H 158 write watchpoint 20H 161 on chip debugger 5 on chip debugger OCD 151 on chip debugger signals 14 on chip oscillator 165 one shot mode 70 opcode map abbreviations 203 cell description 202 first 204 second after 1FH 205 OR 190 ordering information 211 ORX 190 oscillator signals 14 P p 184 packaging LQFP 44 lead 207 64 lead 208 PDIP 206 PLCC 44 lead 207 68 lead 209 QFP 210 part number description 214 part selection guide 2 PC 185 PDIP 206 peripheral AC and DC electrical characteristics 173 PHASE O0 timing SPI 103 PHASE 1 timing SPI 104 pin characteristics 15 017610 0404 Preliminary Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z z ZiLOG PLCC 44 lead 207 68 lead 209 polarity 184 POP 189 pop using extended addressing 189 POPX 189 port availability device 33 port input timing GPIO 176 port output timing GPIO 177 power supply signals 15 power down automatic ADC 133 power on and voltage brown out 173 power on reset POR 27 problem description or suggestion 217 product information 216 program control instructions 190 program c
41. Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Flash Controller Operation Flow Chart On Chip Debugger Block Diagram Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface 1 2 6 kee eee Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface 2 OCD Data Format Recommended Crystal Oscillator Configuration Q0MHzoperation Nominal ICC Versus System Clock Frequency Nominal Halt Mode ICC Versus System Clock Frequency iesus em Port Input Sample Timing GPIO Port Output Timing On Chip Debugger Timing SPI Master Mode Timing SPI Slave Mode PC Timing RTT TS Elags R gislet xen ach aust Opcode Map Cell Description First Opcode Second Opcode Map after 1 40 Lead Plastic Dual Inline Package PDIP 44 Lead Low Profile Quad Flat Package LQFP 44 Lead Plastic Lead Chip Carrier Package PLCC 64 Lead Low Profile Quad
42. If Current Address does not equal End Address the Current Address increments by 1 single byte transfer or 2 two byte word transfer Direct Memory Access Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Configuring DMAO for Data Transfer Follow these steps to configure and enable DMAO or DMAI l Write to the DMAx I O Address register to set the Register File address identifying the on chip peripheral control register The upper nibble of the 12 bit address for on chip peripheral control registers is always FH The full address is FH DMAx IO 7 0 Determine the 12 bit Start and End Register File addresses The 12 bit Start Address is given by DMAx H 3 0 DMA_START 7 0 The 12 bit End Address is given by DMAx H 7 4 DMA_END 7 0 Write the Start and End Register File address high nibbles to the DMAx End Start Address High Nibble register Write the lower byte of the Start Address to the DMAx Start Current Address register Write the lower byte of the End Address to the DMAx End Address register Write to the DMAx Control register to complete the following Select loop or single pass mode operation Select the data transfer direction either from the Register File RAM to the on chip peripheral control register or from the on chip peripheral control register to the Register File RAM Enable the DMAx interrupt request if desired Select Word or Byte mode
43. Low 2 Write to the Timer High and Low Byte registers to set the starting count value usually 0001H This only affects the first pass in Continuous mode After the first timer Reload in Continuous mode counting always begins at the reset value of 0001H Write to the Timer Reload High and Low Byte registers to set the Reload value 4 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 Ifusing the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 6 Write to the Timer Control register to enable the timer and initiate counting In Continuous mode the system clock always provides the timer input The timer period is given by the following equation Reload Value x Prescale Continuous Mode Time Out Period s System Clock Frequency Hz If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers the One Shot mode equation must be used to determine the first time out period Counter Mode In Counter mode the timer counts input transitions from a GPIO port pin The timer input is taken from the GPIO Port pin Timer Input alternate function The TPOL bit in the Timer Control Register selects whether the count occurs on the rising edge or the falling edge of the Timer Input signal In Counter mode the prescaler is d
44. OCD Status Register OCDSTAT BITS 7 6 5 4 3 2 1 0 FIELD DBG HALT RPEN Reserved RESET 0 0 0 0 0 0 0 0 R W R R R R R R R R DBG Debug Status 0 The Z8F640x family device is operating in normal mode 1 The Z8F640x family device is in Debug mode HALT Halt Mode 0 The Z8F640x family device is not in Halt mode 1 The Z8F640x family device is in Halt mode PS017610 0404 On Chip Debugger Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 RPEN Read Protect Option Bit Enabled 0 The Read Protect Option Bit is disabled 1 0 The Read Protect Option Bit is enabled 0 disabling many OCD commands Reserved These bits are always 0 OCD Watchpoint Control Register The OCD Watchpoint Control register is used to configure the debug Watchpoint Table 96 OCD Watchpoint Control Address WPTCTL BITS 7 6 5 4 3 2 1 0 FIELD WPW WPR WPDM Reserved WPTADDR 11 8 RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W WPW Watchpoint Break on Write This bit cannot be set if the Read Protect Option Bit is enabled 0 Watchpoint Break on Register File write is disabled 1 Watchpoint Break on Register File write is enabled WPR Watchpoint Break on Read This bit cannot be set if the Read Protect Option Bit is enabled 0 Watchpoint Break on Register File read is disabled Watchpoint Break on Register
45. Select the DMAx request trigger Enable the DMAx channel DMA ADC Operation DMA ADC transfers data from the ADC to the Register File The sequence of operations in a DMA ADC data transfer is 017610 0404 1 ADC completes conversion on the current ADC input channel and signals the DMA controller that two bytes of ADC data are ready for transfer DMA ADC requests control of the system bus address and data from the eZ8 CPU After the eZ8 CPU acknowledges the bus request DMA_ADC transfers the two byte ADC output value to the Register File and then returns system bus control back to the eZ8 CPU If the current ADC Analog Input is the highest numbered input to be converted DMA ADC resets the ADC Analog Input number to 0 and initiates data conversion on ADC Analog Input 0 If configured to generate an interrupt ADC sends an interrupt request to the Interrupt Controller Direct Memory Access Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG If the current ADC Analog Input is not the highest numbered input to be converted DMA_ADC initiates data conversion in the next higher numbered ADC Analog Input Configuring DMA ADC for Data Transfer Follow these steps to configure and enable DMA ADC 1 Write the DMA ADC Address register with the 7 most significant bits of the Register File address for data transfers 2 Wirite to the DMA ADC Control register to complete the following
46. Table 116 Table 117 Table 118 Table 119 Table 120 Table 121 Table 122 Table 123 Table 124 Table 125 Table 126 Table 127 Table 128 Table 129 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Absolute Maximum Ratings 167 DG Characteristics soccer dk RR ew 169 AC Characteristics 172 Power On Reset and Voltage Brown Out Electrical Characteristics and Timing 173 Flash Memory Electrical Characteristics and Timing 173 Watch Dog Timer Electrical Characteristics and Timing 174 Analog to Digital Converter Electrical Characteristics and Timing Shae RR E eee 174 GPIO Port Input Timing 176 GPIO Port Output Timing 177 On Chip Debugger Timing 178 SPI Master Mode Timing 179 SPI Slave Mode Timing 180 I2 C Timing pesca ga oe dias et eed ye Nace teer Es 181 Assembly Language Syntax Example 183 Assembly Language Syntax Example2 183 Notational Shorthand 184 Additional Symbols 185 Condition Codes EEEE 186 Arithmetic Instructions 187 Bit Manipulation Instructions 188 Block Transfer Instructions 188 CPU Control
47. can be defined to be 1 through 8 bits by the NUMBITS field in the SPI Mode register The SPI in Slave mode generates an interrupt when the SS signal deasserts to indicate comple tion of the data transfer Writing a 1 to the IRQ bit in the SPI Status Register clears the pending interrupt request If the SPI is disabled an SPI interrupt can be generated by a Baud Rate Generator time out SPI Baud Rate Generator In SPI Master mode the Baud Rate Generator creates a lower frequency serial clock SCK for data transmission synchronization between the Master and the external Slave The input to the Baud Rate Generator is the system clock The SPI Baud Rate High and Low Byte registers combine to form a 16 bit reload value BRG 15 0 for the SPI Baud Rate Generator The reload value must be greater than or equal to 0002H for SPI operation maximum baud rate is system clock frequency divided by 4 The SPI baud rate is calcu lated using the following equation System Clock Frequency Hz SPI Baud Rate bits s 2 x BRG 15 0 When the SPI is disabled the Baud Rate Generator can function as a basic 16 bit timer with interrupt on time out To configure the Baud Rate Generator as a timer with interrupt on time out complete the following procedure PS017610 0404 Serial Peripheral Interface Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 1 Disable the SPI by clearing the SPIEN bit in the SPI Control register to 0 2
48. is the SPI slave this pin is the input slave select It is multiplexed with a general purpose I O pin SCK T O SPI Serial Clock The SPI master supplies this pin If the Z8 Encore is the SPI master this pin is an output If the Z8 Encore is the SPI slave this pin is an input It is multiplexed with a general purpose I O pin MOSI IO Master Out Slave In This signal is the data output from the SPI master device and the data input to the SPI slave device It is multiplexed with a general purpose I O pin MISO IO Master In Slave Out This pin is the data input to the SPI master device and the data output from the SPI slave device It is multiplexed with a general purpose I O pin PS017610 0404 Signal and Pin Descriptions Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 7 ZiLOG Table 2 Signal Descriptions Continued Signal Mnemonic Description UART Controllers TXDO0 1 Transmit Data These signals are the transmit outputs from the UARTs The TXD signals are multiplexed with general purpose I O pins RXDO0 RXDI I Receive Data These signals are the receiver inputs for the UARTs and IrDAs The RXD signals are multiplexed with general purpose I O pins CTS0 CTS1 I Clear To Send These signals are control inputs for the UARTs The CTS signals are multiplexed with general purpose I O pins Timers Timer 3 is unavailable in the 40 and 44 pin packages TOOUT TIOUT
49. parity is not an option as the Parity bit location 9th bit becomes the Multiprocessor control bit The UART Control 1 and Status 1 registers pro vide multiprocessor 9 bit mode control and status information 017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 UART Interrupts The UART features separate interrupts for the transmitter and the receiver In addition when the UART primary functionality is disabled the Baud Rate Generator can also func tion as a basic timer with interrupt capability Transmitter Interrupts The transmitter generates an interrupt anytime the Transmit Data Register Empty bit TDRE is set to 1 This indicates that the transmitter is ready to accept new data for trans mission Writing to the UART Transmit Data register clears the UART Transmit interrupt Receiver Interrupts The receiver generates an interrupt when any of the following occurs e data byte has been received and is available in UART Receive Data register This interrupt can be disabled independent of the other receiver interrupt sources e break is received e An overrun is detected A data framing error is detected Baud Rate Generator Interrupts If the Baud Rate Generator BRG interrupt enable is set the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads This action allows the Baud Rate Generator to function as an additional counter if the UART functiona
50. vcc SPI Master E To Slave 2 s SS Pin Ai GPIO To Slave 1 5 SS Pin GPIO 8 bit Shift Register Bit 7 Bit 0 From Slave LN To Slave a 5 Baud Rate To Slave lt w u uue ev lcu 4 8 bit Shift Register Bit 7 A Bit 0 To Master From Master From Master Figure 76 SPI Configured as a Slave Operation The SPI is a full duplex synchronous character oriented channel that supports a four wire interface serial clock transmit receive and Slave select The SPI block consists of trans PS017610 0404 Serial Peripheral Interface Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 mitter and receiver sections a Baud Rate clock Generator and a control unit The trans mitter and receiver sections use the same clock During an SPI transfer data is sent and received simultaneously by both the Master and the Slave SPI devices Separate signals are required for data and the serial clock When an SPI transfer occurs a multi bit typically 8 bit character is shifted out one data pin and an multi bit character is simultaneously shifted in on a second data pin An 8 bit shift register in the Master and another 8 bit shift register in the Slave are connected as a circular buffer The SPI shift register is single buffered in the transmit and receive directions New data to be transmitted cannot be
51. 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC7H T3ENH Timer 3 Interrupt Request Enable High Bit UIRENH UART 1 Receive Interrupt Request Enable High Bit UITENH UART 1 Transmit Interrupt Request Enable High Bit DMAENH DMA Interrupt Request Enable High Bit C3ENH Port C3 Interrupt Request Enable High Bit C2ENH Port C2 Interrupt Request Enable High Bit C1ENH Port C1 Interrupt Request Enable High Bit COENH Port Interrupt Request Enable High Bit Table 34 IRQ2 Enable Low Bit Register IRQZENL BITS 7 6 5 4 3 2 1 0 FIELD T3ENL UIRENL UITENL DMAENL C3ENL C2ENL CIENL COENL RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC8H T3ENL Timer 3 Interrupt Request Enable Low Bit UIRENL UART 1 Receive Interrupt Request Enable Low Bit UITENL UART 1 Transmit Interrupt Request Enable Low Bit DMAENL DMA Interrupt Request Enable Low Bit C3ENL Port C3 Interrupt Request Enable Low Bit C2ENL Port C2 Interrupt Request Enable Low Bit C1ENL Port Interrupt Request Enable Low Bit COENL Port CO Interrupt Request Enable Low Bit Interrupt Edge Select Register The Interrupt Edge Select IRQES register Table 35 determines whether an interrupt is generated for the rising edge or falling edge on the selected GPIO Port input pin The PS017610 0404 Interrupt Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z
52. 34 LD 3 2 POPX ER1 22 BIT p b r1 2 3 LD r1 lr2 3 3 LD IR2 R1 3 2 LD 3 3 LD 42 LDX ER2 ER1 2 6 TRAP Vector 2 3 LD Ir1 2 Figure 101 First Opcode Map 017610 0404 3 3 LD R2 IR1 3 3 3 4 78 204 211 08 Opcode Maps Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Lower Nibble Hex Upper Nibble Hex 5 3 ER2 ER1 Figure 102 Second Opcode Map after 1FH PS017610 0404 Opcode Maps Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 206 ZiLOG Packaging Figure 103 PS017610 0404 Figure 103 illustrates the 40 pin PDIP plastic dual inline package available for the Z8F1601 Z8F2401 Z8F3201 Z8F4801 and Z8F6401 devices 40 Lead Plastic Dual Inline Package PDIP Packaging Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z r ZiLOG Figure 104 illustrates the 44 pin LQFP low profile quad flat package available for the Z8F1601 Z8F2401 Z8F3201 Z8F4801 and Z8F6401 devices MILLIMETER SYMBOL MIN MIN MAX 0 055 0 063 i 0 002 0 006 0 053 0 057 0 012 0018 0 004 0 008 0 463 0 482 E HE 0 390 0 398 0463 0 482 DETAILA 0 390 0 398 0 031 BSC iz 045 0 018 0 030 1 00 0 039 REF
53. 5 44 architecture 44 interrupt assertion types 47 interrupt vectors and priority 47 operation 46 register definitions 48 interrupt edge select register 54 interrupt port select register 55 interrupt request 0 register 48 interrupt request 1 register 49 interrupt request 2 register 50 interrupt return 190 interrupt vector listing 44 interrupts not acknowledge 112 receive 112 SPI 105 transmit 112 UART 85 introduction 1 IR 184 Ir 184 IrDA architecture 95 PS017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z z ZiLOG block diagram 95 control register definitions 98 jitter 98 operation 96 receiving data 97 transmitting data 96 IRET 190 IRQO enable high and low bit registers 51 IRQI enable high and low bit registers 52 IRQ2 enable high and low bit registers 53 IRR 184 Irr 184 J jitter 98 JP 190 jump conditional relative and relative conditional 190 L LD 189 LDC 189 LDCI 188 189 LDE 189 LDEI 188 189 LDX 189 LEA 189 load 189 load constant 188 load constant to from program memory 189 load constant with auto increment addresses 189 load effective address 189 load external data 189 load external data to from data memory and auto increment addresses 188 load external to from data memory and auto incre ment addresses 189 load instructions 189 load using extended addressing 189 logical AND 190 logical AND extended addressing 190 logical exclusive O
54. File write is enabled WPDM Watchpoint Data Match If this bit is set then the Watchpoint only generates a Debug Break if the data being read or written matches the specified Watchpoint data Either the WPR and or WPW bits must also be set for this bit to affect operation This bit cannot be set if the Read Protect Option Bit is enabled 0 Watchpoint Break on read and or write does not require a data match 1 Watchpoint Break on read and or write requires a data match Reserved This bit is reserved and must be 0 RADDR 11 8 Register address These bits specify the upper 4 bits of the Register File address to match when generating a Watchpoint Debug Break The full 12 bit Register File address is given by WPTCTL3 0 WPTADDR 7 0 PS017610 0404 On Chip Debugger Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z w ZiLOG OCD Watchpoint Address Register The OCD Watchpoint Address register specifies the lower 8 bits of the Register File address bus to match when generating Watchpoint Debug Breaks The full 12 bit Register File address is given by WPTCTL3 0 WPTADDR 7 0 Table 97 OCD Watchpoint Address WPTADDR BITS 7 6 5 4 3 2 1 0 FIELD WPTADDR 7 0 RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W WPTADDR 7 0 Watchpoint Register File Address These bits specify the lower eight bits of the register address to match when generating a Watchpoint De
55. Flat Package LQFP 68 Lead Plastic Lead Chip Carrier Package PLCC 80 Lead Quad Flat Package QFP Z8 Encore 2 211 08 List of Figures Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 017610 0404 Z8F640x Family Part Selection Guide Z8F640x Family Package Options Signal Descriptions Pin Characteristics of the Z8F640x family Z8F640x Family Program Memory Maps Z8F640x Family Data Memory Maps Register File Address Map Reset and STOP Mode Recovery Characteristics and Latency esee 4s hes ead Shed cele AME Reset Sources and Resulting Reset Type STOP Mode Recovery Sources and Resulting Action Port Availability by Device and Package Type Port Alternate Function Mapping Port A H GPIO Address Registers PXADDR GPIO Port Registers and Sub Registers Port A H Control Registers PXCTL Port A H Data Direction Sub Registers Port
56. I O pin Debug This pin is the control and data input and output to and from the On Chip Debugger For operation of the On chip debugger all power pins Vpp and AVpp must be supplied with power and all ground pins Vss and 55 must be grounded This pin is open drain and must have an external pull up resistor to ensure proper operation 017610 0404 Signal and Pin Descriptions Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 15 21108 Table 2 Signal Descriptions Continued Signal Mnemonic UO Description Reset RESET I RESET Generates a Reset when asserted driven Low Power Supply VDD I Power Supply AVDD I Analog Power Supply VSS I Ground AVSS I Analog Ground Pin Characteristics Table 3 provides detailed information on the characteristics for each pin available on the Z8F640x family products Data in Table 3 is sorted alphabetically by the pin symbol mne monic Table 3 Pin Characteristics of the Z8F640x family Active Low Internal Schmitt Symbol Reset or Tri State Pull upor Trigger Open Drain Mnemonic Direction Direction Active High Output Pull down Input Output AVSS N A N A N A N A No No N A AVDD N A N A N A N A No No N A DBG 1 N A Yes No Yes Yes VSS N A N A N A N A No No N A PA 7 0 Io I N A Yes No Yes Yes Programmable PB 7 0 Io I N A Yes No Yes Yes Programmable PC 7 0 Io I N A Yes No Yes Yes Programmable PD 7 0 Io I N A Ye
57. IM ER1 23 SBC 24 SBC r1 lr2 3 4 SBC IR2 R1 3 3 SBC 34 SBC IR1 M 43 SBCX ER2 ER1 4 3 SBCX IM ER1 23 OR rt 24 OR r1 lr2 3 4 OR IR2 R1 3 3 OR 34 OR IR1 M 43 ORX ER2 ER1 43 ORX 1 1 2 3 AND rt 24 AND r1 lr2 3 4 AND IR2 R1 3 3 AND R1 IM 3 4 AND IR1 IM 43 ANDX ER2 ER1 4 3 1 23 TCM rt 24 TCM r1 lr2 3 4 TCM IR2 R1 3 3 TCM R1 IM 34 TCM IR1 IM 43 TCMX ER2 ER1 43 TCMX 1 23 TM 1 2 24 TM r1 lr2 3 4 TM IR2 R1 3 3 TM R1 IM 3 4 TM IR1 IM 43 TMX ER2 ER1 43 TMX IM ER1 Upper Nibble Hex 25 LDE r1 lrr2 29 LDEI Ir1 Irr2 3 3 LDX Irt ER2 34 LDX IRR2 R1 3 5 LDX IRR2 IR1 3 4 LDX r1 rr2 X 3 4 LDX rr r2 X 2 5 LDE r2 lrri 2 9 LDEI Ir2 lrri 3 3 LDX Ir2 ER1 34 LDX R2 IRR1 3 5 LDX IR2 IRR1 3 3 LEA r1 r2 X 3 5 LEA rr1 rr2 X 2 3 CP 1 2 24 CP r1 lr2 3 4 CP IR2 R1 3 3 CP 34 IR1 M 43 CPX ER2 ER1 4 3 CPX 1 1 2 3 XOR 1 2 24 XOR r1 lr2 3 4 XOR IR2 R1 3 3 XOR R1 IM 3 4 XOR IR1 IM 43 XORX ER2 ER1 43 XORX 1 2 5 LDC r1 lrr2 2 9 LDCI 11 172 2 9 LDC Irt Irr2 3 3 LD 3 2 PUSHX ER2 2 5 LDC r2 lrri 2 9 LDCI Ir2 lrri 2 2 BSWAP R1 33 CALL DA
58. Instruction Summary Continued Assembly Mode Opcode s ne Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles SBC dst src dst lt dst src C r r 32 ode x 2 3 r Ir 33 2 4 R R 34 3 3 R IR 35 3 4 R IM 36 3 3 IR IM 37 3 4 SBCX dst src dst lt dst src C ER ER 38 4 3 IM 39 4 3 SCF Cel DF l e 1 2 SRA dst r3 R DO QO 2 2 bi uw SRL dst 7 IF CO 3 IR IFCI 3 SRP src RP lt src IM 01 2 2 Stop Mode 6F DLE ZZ S 1 2 SUB dst src dst dst src r r 22 e ce qo 2 3 r Ir 23 2 4 R R 24 3 3 R IR 25 3 4 R IM 26 3 3 IR IM 27 3 4 dst src dst lt dst src ER ER 28 Woo 4 3 ER IM 29 4 3 SWAP dst dst 7 4 lt gt dst 3 0 R FO xX X 2 2 IR F1 2 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 7 199 211089 Table 126 eZ8 CPU Instruction Summary Continued Address Mode Flags Assembly Opcode s Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles TCM dst src NOT dst AND src r r 62
59. Load the desired 16 bit count value into the SPI Baud Rate High and Low Byte registers 3 Enable the Baud Rate Generator timer function and associated interrupt by setting the BIRQ bit in the SPI Control register to 1 SPI Control Register Definitions SPI Data Register The SPI Data register stores both the outgoing transmit data and the incoming received data Reads from the SPI Data register always return the current contents of the 8 bit shift register With the SPI configured as a Master writing a data byte to this register initiates the data transmission With the SPI configured as a Slave writing a data byte to this register loads the shift register in preparation for the next data transfer with the external Master In either the Master or Slave modes if a transmission is already in progress writes to this register are ignored and the Overrun error flag OVR is set in the SPI Status register When the character length is less than 8 bits as set by the NUMBITS field in the SPI Mode register the transmit character must be left justified in the SPI Data register A received character of less than 8 bits will be right justified For example if the SPI is configured for 4 bit characters the transmit characters must be written to SPIDATA 7 4 and the received characters are read from SPIDATA 3 0 Table 60 SPI Data Register SPIDATA BITS 7 6 5 4 3 2 1 0 FIELD DATA RESET x x
60. Mode ICC Versus System Clock Frequency PS017610 0404 Electrical Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG AC Characteristics The section provides information on the AC characteristics and timing of the 78 Encore AC timing information assumes a standard load of 50pF on all outputs Table 102 AC Characteristics Vpp 3 0 3 6V T4 40 C to 105 C Symbol Parameter Minimum Maximum Units Conditions Fyyscik System Clock Frequency 20 0 MHz Read only from Flash memory 0 032768 20 0 MHz Program or erasure of the Flash memory Fxra Crystal Oscillator Frequency 1 0 20 0 MHz System clock frequencies below the crystal oscillator minimum require an external clock driver System Clock Period 50 nS Tek WF yscik System Clock High Time 20 30 ns 50ns System Clock Low Time 20 30 ns 50ns System Clock Rise Time 3 ns 50ns _ System Clock Fall Time 3 ns 50ns 017610 0404 Electrical Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z z ZiLOG On Chip Peripheral AC and DC Electrical Characteristics Table 103 Power On Reset and Voltage Brown Out Electrical Characteristics and Timing 40 C to 105 C Symbol Parameter Minimum Typical Maximum Units C
61. On Chip Debugger Commands Enabled when NOT Disabled by Debug Command Command Byte in Debug mode Read Protect Option Bit Write Program Memory Disabled Read Program Memory OBH Disabled Write Data Memory OCH Yes Read Data Memory Read Program Memory OEH Reserved OFH Step Instruction 10H Disabled Stuff Instruction 11H Disabled Execute Instruction 12H Disabled Reserved 13H 1FH Write Watchpoint 20H Disabled Read Watchpoint 21H Reserved 22H FFH In the following bulleted list of Commands data and commands sent from the host to the On Chip Debugger are identified by DBG lt Command Data Data sent from the On Chip Debugger back to the host is identified by DBG gt Data Read OCD Revision 00H The Read OCD Revision command is used to determine the version of the On Chip Debugger If OCD commands are added removed or changed this revision number changes DBG 00H DBG gt OCDREV 15 8 Major revision number gt OCDREV 7 0 Minor revision number Read OCD Status Register 02H The Read OCD Status Register command is used to read the OCDSTAT register DBG 02H DBG OCDSTAT 7 0 Read Runtime Counter 03H The Runtime Counter is used to count Z8 Encore system clock cycles in between Breakpoints The 16 bit Runtime Counter counts up from 0000H and stops at the maximum count of FFFFH The Runtime Coun
62. P PDIP PLCC F QFP Pin Count H 20 pins J 28 pins M 40 pins N 44 pins R 64 pins S 68 pins T 80 pins Speed 020 20MHz Temperature 0 to 70 40 C to 105 Environmental Flow C Plastic Standard Example Part number Z8F06401 ANO20SC is an 8 bit microcontroller product in an LQFP package using 44 pins operating with a maximum 20MHz external clock frequency over a 0 C to 70 C temperature range and built using the Plastic Standard environmental flow PS017610 0404 Ordering Information Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z z ZiLOG Precharacterization Product The product represented by this document is newly introduced and ZiLOG has not com pleted the full characterization of the product The document states what ZiLOG knows about this product at this time but additional features or nonconformance with some aspects of the document might be found either by ZiLOG or its customers in the course of further application and characterization work In addition ZiLOG cautions that delivery might be uncertain at times due to start up yield issues ZiLOG Inc 532 Race Street San Jose CA 95126 Telephone 408 558 8500 FAX 408 558 8300 Internet www zilog com Document Information Document Number Description 017610 0404 The Document Control Number that appears in the footer on each page of this document contains unique identifying attributes as indicated
63. PWM Low Byte Register TXPWML BITS 7 6 5 4 3 0 FIELD PWML RESET 0 0 0 0 0 0 R W R W R W R W R W R W R W ADDR F05H FODH F15H FIDH PWMH and PWML Pulse Width Modulator High and Low Bytes These two bytes PWMH 7 0 PWML 7 0 form a 16 bit value that is compared to the current 16 bit timer count When a match occurs the PWM output changes state The PWM output value is set by the TPOL bit in the Timer Control Register TxCTL register The TxPWMH and TxPWML registers also store the 16 bit captured timer value when operating in Capture or Capture Compare modes 017610 0404 Timers Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Zi 211 08 Timer 0 3 Control Registers The Timer 0 3 Control TxCTL registers enable disable the timers set the prescaler value and determine the timer operating mode Table 44 Timer 0 3 Control Register TxCTL BITS 7 6 5 4 3 2 1 0 FIELD TEN TPOL PRES TMODE RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F07H FOFH F17H TEN Timer Enable 0 Timer is disabled 1 Timer enabled to count TPOL Timer Input Output Polarity Operation of this bit is a function of the current operating mode of the timer 017610 0404 One Shot mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented up
64. RESET pin power on reset Watch Dog Timer WDT Stop mode exit or Voltage Brown Out VBO warning signal On Chip Debugger The Z8 Encore features an integrated On Chip Debugger OCD The OCD provides a rich set of debugging capabilities such as reading and writing registers programming the Flash setting breakpoints and executing code A single pin interface provides communi cation to the OCD DMA Controller The Z8F640x family features three channels of DMA Two of the channels are for register RAM to and from I O operations The third channel automatically controls the transfer of data from the ADC to the memory PS017610 0404 Introduction Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore ZiLOG Signal and Pin Descriptions Overview The Z8F640x family products are available in a variety of packages styles and pin config urations This chapter describes the signals and available pin configurations for each of the package styles For information regarding the physical package specifications please refer to the chapter Packaging on page 206 Available Packages Table 2 identifies the package styles that are available for each device within the Z8F640x family product line Table 2 Z8F640x family Package Options 40 pin 44 pin 44 pin 64 pin 68 pin 80 pin Part Number PDIP LQFP PLCC LQFP PLCC QFP Z8F1601 X X X Z8F1602 X X Z8F2401 X X X Z8F2402 X X Z8F3201 X X X Z8F32
65. Ratings at 70 C to 105 C Total power dissipation 500 mW Maximum current into Vpp or out of Vss 140 mA 64 Pin LQFP Maximum Ratings at 40 C to 70 C Total power dissipation 1000 mW Maximum current into Vpp or out of 2775 mA 64 Pin LQFP Maximum Ratings at 70 C to 105 C Total power dissipation 540 mW Maximum current into Vpp or out of Vss 150 mA 44 Pin PLCC Maximum Ratings at 40 C to 70 C Total power dissipation 750 mW Maximum current into Vpp or out of Vss 200 mA 44 Pin PLCC Maximum Ratings at 70 C to 105 C Total power dissipation 295 mW Maximum current into Vpp or out of Vas 83 mA 44 pin LOFP Maximum Ratings at 40 C to 70 C Total power dissipation 750 mW Maximum current into or out of Vss 200 mA 44 pin LQFP Maximum Ratings at 70 C to 105 C Total power dissipation 410 mW Maximum current into Vpp or out of Vss 114 mA 40 Pin PDIP Maximum Ratings at 40 C to 70 C Total power dissipation 1000 mW Maximum current into Vpp or out of 275 mA 40 Pin PDIP Maximum Ratings at 70 C to 105 C Total power dissipation 540 mW Maximum current into Vpp or out of Vas 150 mA Notes 1 This voltage applies to all pins except the following Vpp AVpp pins supporting analog input Port B and Port H RESET and where noted otherwise 017610 0404 Electrical Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z w ZiLOG DC Characteristics Table 101 lists the DC characte
66. Than or Equal COR 4 1 0100 4 OV Overflow 1 0101 5 MI Minus 1 0110 6 Z Zero Z 1 0110 6 EQ Equal Z 1 0111 7 Carry 1 0111 7 ULT Unsigned Less Than 1 1000 8 T or blank Always True 1001 9 GE Greater Than or Equal S XOR V 0 1010 A GT Greater Than Z OR S XOR V 0 1011 B UGT Unsigned Greater Than 0 AND 7 0 1 1100 NOV No Overflow 0 1101 PL Plus S 0 1110 E NZ Non Zero Z 0 1110 E NE Not Equal Z 0 1111 F NC No Carry 0 1111 F UGE Unsigned Greater Than or Equal C 0 PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 eZ8 CPU Instruction Classes eZ8 CPU instructions can be divided functionally into the following groups e Arithmetic Bit Manipulation Block Transfer CPU Control e Load Logical Program Control Rotate and Shift Tables 118 through 125 contain the instructions belonging to each group and the number of operands required for each instruction Some instructions appear in more than one table as these instruction can be considered as a subset of more than one category Within these tables the source operand is identified as src the destination operand is dst and a con dition code is cc Table 118 Arithmetic Instructions Mnemonic Operands Instruction ADC dst src Add with Carry ADCX dst src Add with Carry using Extended Addressing ADD dst src
67. The ADC accepts inputs from up to 12 different analog input sources UARTs Each UART is full duplex and capable of handling asynchronous data transfers The UARTs support 8 and 9 bit data modes and selectable parity PC The inter integrated circuit controller makes the Z8 Encore compatible with the protocol The controller consists of two bidirectional bus lines a serial data SDA line and a serial clock SCL line PS017610 0404 Introduction Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Serial Peripheral Interface The serial peripheral interface SPI allows the Z8 Encore to exchange data between other peripheral devices such as EEPROMs A D converters and ISDN devices The SPI is a full duplex synchronous character oriented channel that supports a four wire interface Timers Up to four 16 bit reloadable timers can be used for timing counting events or for motor control operations These timers provide a 16 bit programmable reload counter and oper ate in One Shot Continuous Gated Capture Compare Capture and Compare and PWM modes Only 3 timers Timers 0 2 are available in the 40 and 44 pin packages Interrupt Controller The Z8F640x family products support up to 24 interrupts These interrupts consist of 12 internal and 12 general purpose I O pins The interrupts have 3 levels of programmable interrupt priority Reset Controller The Z8F640x family can be reset using the
68. The data transfer format for a 10 bit addressed slave is illustrated in the figure below Shaded regions indicate data transferred from the PC Controller to slaves and unshaded regions indicate data transferred from the slaves to the Controller Slave Address e Slave Address E Figure 80 10 Bit Addressed Slave Data Transfer Format The first seven bits transmitted in the first byte are 11110xx The two bits Xx are the two most significant bits of the 10 bit address The lowest bit of the first byte transferred is the write signal The transmit operation is carried out in the same manner as 7 bit addressing The data transfer format for a transmit operation on a 10 bit addressed slave is as follows 1 Software asserts the bit in the Control register 2 Software asserts the TXI bit of the Control register to enable Transmit interrupts 3 The IC interrupt asserts because the PC Data register is empty 4 Software responds to the TDRE bit by writing the first slave address byte The least significant bit must be 0 for the write operation e Software asserts the START bit of the C Control register 6 The Controller sends the START condition to the slave PS017609 0803 12C Controller 10 11 12 13 14 15 16 17 18 19 20 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 The Controller loads the Shift register with the contents of the PC Da
69. Timer 2 is awaiting service T1I Timer 1 Interrupt Request 0 No interrupt request is pending for Timer 1 1 An interrupt request from Timer 1 is awaiting service TOI Timer 0 Interrupt Request 0 1 No interrupt request is pending for Timer 0 An interrupt request from Timer 0 is awaiting service UORXI UART O0 Receiver Interrupt Request 0 No interrupt request is pending for the UART 0 receiver 1 An interrupt request from the UART 0 receiver is awaiting service UOTXI UART 0 Transmitter Interrupt Request 0 No interrupt request is pending for the UART 0 transmitter 1 An interrupt request from the UART 0 transmitter is awaiting service 017610 0404 Interrupt Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG PcI PC Interrupt Request 0 No interrupt request is pending for the PC 1 An interrupt request from the is awaiting service SPII SPI Interrupt Request 0 No interrupt request is pending for the SPI 1 An interrupt request from the SPI is awaiting service ADCI ADC Interrupt Request 0 No interrupt request is pending for the Analog to Digital Converter 1 An interrupt request from the Analog to Digital Converter is awaiting service Interrupt Request 1 Register The Interrupt Request 1 IRQ1 register Table 24 stores interrupt requests for both vec tored and polled interrupts When a request is presented to the interrup
70. Timer interrupt if enabled and Illegal Instruction Trap always have highest Level 3 priority Interrupt Assertion Types Two types of interrupt assertion single assertion pulse and continuous assertion are used within the Z8F640x family device The type of interrupt assertion for each interrupt source is listed in Table 22 Single Assertion Pulse Interrupt Sources Some interrupt sources assert their interrupt requests for only a single system clock period single pulse When the interrupt request is acknowledged by the eZ8 CPU the corre sponding bit in the Interrupt Request register is cleared until the next interrupt occurs Writing a 0 to the corresponding bit in the Interrupt Request register likewise clears the interrupt request Continuous Assertion Interrupt Sources Other interrupt sources continuously assert their interrupt requests until cleared at the source For these continuous assertion interrupt sources interrupt acknowledgement by the eZ8 CPU does not clear the corresponding bit in the Interrupt Request register Writing a 0 to the corresponding bit in the Interrupt Request register only clears the interrupt for a single clock cycle Since the source is continuously asserting the interrupt request the interrupt request bit is set to 1 again during the next clock cycle The only way to clear continuous assertion interrupts is at the source of the interrupt for example in the UART or SPI peripherals The sourc
71. and Low Bit Registers 53 Interrupt Edge Select Register 54 Interrupt Port Select Register 55 Interrupt Control 56 TAMERS 57 ul AM T 57 Architecture siya cosa tA hath ESQ RM 57 Operation acid dis px REUS RR E RO utet Ea MU ds 58 PS017610 0404 Table of Contents Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 211 08 Timer Operating Modes 58 Reading the Timer Count Values 66 Timer Output Signal Operation 66 Timer Control Register Definitions 66 Timer 0 3 High and Low Byte Registers 66 Timer Reload High and Low Byte Registers 67 Timer 0 3 PWM High and Low Byte Registers 69 Timer 0 3 Control Registers 70 Watch Dog Timer 4 6 e eee e e OE ERA EE RR ERES 72 OVERVIEW iude bei pha eben eU ERE Ee epe estes 72 Operation o r opia unea IS pe ee PR ERI 72 Watch Dog Timer Refresh 73 Watch Dog Timer Time Out Response 73 Watch Dog Timer Reload Unlock Sequence 74 Watch Dog Timer Control Register Definitions 75 Watch Dog Timer Control Register
72. be set as an input The SS input signal on the Master must be High If the SS signal goes Low indicating another Master is driving the SPI bus a Mode Fault error flag is set in the SPI Status register SPI Clock Phase and Polarity Control The SPI supports four combinations of serial clock phase and polarity using two bits in the SPI Control register The clock polarity bit CLKPOL selects an active high or active low clock and has no effect on the transfer format Table 59 lists the SPI Clock Phase and Polarity Operation parameters The clock phase bit PHASE selects one of two fundamen tally different transfer formats For proper data transmission the clock phase and polarity must be identical for the SPI Master and the SPI Slave The Master always places data on the MOSI line a half cycle before the clock edge SCK signal in order for the Slave to latch the data Table 59 SPI Clock Phase PHASE and Clock Polarity CLKPOL Operation SCK SCK SCK Transmit Receive Idle PHASE CLKPOL Edge Edge State 0 0 Falling Rising Low 0 1 Rising Falling High 1 0 Rising Falling Low 1 1 Falling Rising High PS017610 0404 Serial Peripheral Interface Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Transfer Format PHASE Equals Zero Figure 77 illustrates the timing diagram for an SPI transfer in which PHASE is cleared to 0 The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to
73. bit mode functions if desired 4 Write to the UART Control 0 register to Set the transmit enable bit TEN to enable the UART for data transmission Enable parity if desired and select either even or odd parity Setor clear the CTSE bit to enable or disable control from the receiver using the CTS pin 017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG 5 Check the bit in the UART Status 0 register to determine if the Transmit Data register is empty indicated by a 1 If empty continue to Step 6 If the Transmit Data register is full indicated by a 0 continue to monitor the TDRE bit until the Transmit Data register becomes available to receive new data 6 Wirite the data byte to the UART Transmit Data register The transmitter automatically transfers the data to the Transmit Shift register and transmit the data 7 transmit additional bits return to Step 5 Transmitting Data using the Interrupt Driven Method The UART Transmitter interrupt indicates the availability of the Transmit Data register to accept new data for transmission Follow these steps to configure the UART for interrupt driven data transmission 1 Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate 2 Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation Execute a DI instruction to disable interrupts
74. contained within the Z8F640x family device s Flash memory can be pro tected against external access via the On Chip Debugger Programming the RP Option Bit prevents reading of the user code through the On Chip Debugger Refer to the Option Bits chapter and the On Chip Debugger chapter for more information Flash Code Protection Against Accidental Program and Erasure The Z8F640x family device provides several levels of protection against accidental pro gram and erasure of the Flash memory contents This protection is provided by a combina tion of the Option bits and the locking mechanism of the Flash Controller PS017610 0404 Flash Memory Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Flash Code Protection Using the Option Bits The FHSWP and FWP Option Bits combine to provide three levels of Flash Program Mem ory protection as listed in Table 84 Refer to the Option Bits chapter for more informa tion Table 84 Flash Code Protection Using the Option Bits FHSWP FWP Flash Code Protection Description 0 0 Programming and erasure disabled for all of Flash Program Memory In user code programming Page Erase and Mass Erase are all disabled Mass Erase is available through the On Chip Debugger 1 0 Programming and Page Erase are enabled for the High Sector of the Flash Program Memory only The High Sector on the Z8F640x family device contains IKB to 4KB of Flash with addresses at the top of the available F
75. count are as follows 1 Write to the Timer Control register to Disable the timer Configure the timer for Capture Compare mode Set the prescale value Set the Capture edge rising or falling for the Timer Input 2 Write to the Timer High and Low Byte registers to set the starting count value typically 0001H Write to the Timer Reload High and Low Byte registers to set the Compare value 4 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers PS017610 0404 Timers Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG 5 Configure the associated GPIO port pin for the Timer Input alternate function 6 Write to the Timer Control register to enable the timer 7 Counting begins on the first appropriate transition of the Timer Input signal No interrupt is generated by this first edge In Capture Compare mode the elapsed time from timer start to Capture event can be cal culated using the following equation Capture Elapsed Time s Capture Value Start Value x Prescale System Clock Frequency Hz Reading the Timer Count Values The current count value in the timers can be read while counting enabled This capability has no effect on timer operation When the timer is enabled and the Timer High Byte reg ister is read the contents of the Timer Low Byte register are placed in a holding register A subsequent read from the
76. crystal Recommended crystal specifica tions are provided in Table 99 Resistor Ry limits total power dissipation by the crystal Printed circuit board layout should add no more than 4pF of stray capacitance to either the pins If oscillation does not occur reduce the values of capacitors C and to decrease loading On Chip Oscillator 165 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 On Chip Oscillator XIN XOUT 20MHz Crystal R1 2200 Fundamental Mode R2 100kQ C1 22pF C2 22pF Figure 90 Recommended Crystal Oscillator Configuration 20MHz operation Table 99 Recommended Crystal Oscillator Specifications 20MHz Operation Parameter Value Units Comments Frequency 20 MHz Resonance Parallel Mode Fundamental Series Resistance Rs 25 Maximum Load Capacitance C 20 pF Maximum Shunt Capacitance 7 pF Maximum Drive Level 1 mW Maximum PS017610 0404 On Chip Oscillator Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Electrical Characteristics Absolute Maximum Ratings Z8 Encore ZiLOG Stresses greater than those listed in Table 100 may cause permanent damage to the device These ratings are stress ratings only Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied Exposure to absolute max
77. data rate is calculated using the following equation System Clock Frequency Hz 16 x UART Baud Rate Divisor Value Transmitting IrDA Data PS017610 0404 The data to be transmitted using the infrared transceiver is first sent to the UART The UART s transmit signal TXD and baud rate clock are used by the IrDA to generate the modulation signal IR TXD that drives the infrared transceiver Each UART Infrared data bit is 16 clocks wide If the data to be transmitted is 1 the IR TXD signal remains low for the full 16 clock period If the data to be transmitted is 0 a 3 clock high pulse is output following a 7 clock low period After the 3 clock high pulse a 6 clock low pulse is output to complete the full 16 clock data period Figure 72 illustrates IrDA data transmis sion When the Infrared Endec is enabled the UART s TXD signal is internal to the Z8F640x family device while the TXD signal is output through the TXD pin Infrared Encoder Decoder Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 16 clock F period gt sene ioc Start Bit 0 Data Bit 0 1 Data Bit 1 0 Data Bit 2 1 Data Bit 3 1 3 clock pulse IR TXD Clock lt delay Figure 72 Infrared Data Transmission Receiving IrDA Data Data received from the infrared transceiver via the IR signal through the pin is dec
78. means for writing an application program without having to be concerned with actual memory addresses or machine instruction for mats A program written in assembly language is called a source program Assembly lan guage allows the use of symbolic addresses to identify memory locations It also allows mnemonic codes opcodes and operands to represent the instructions themselves The opcodes identify the instruction while the operands represent memory locations registers or immediate data values Each assembly language program consists of a series of symbolic commands called state ments Each statement can contain labels operations operands and comments Labels can be assigned to a particular instruction step in a source program The label iden tifies that step in the program as an entry point for use by other instructions The assembly language also includes assembler directives that supplement the machine instruction The assembler directives or pseudo ops are not translated into a machine instruction Rather the pseudo ops are interpreted as directives that control or assist the assembly process The source program is processed assembled by the assembler to obtain a machine lan guage program called the object code The object code is executed by the eZ8 CPU An example segment of an assembly language program is detailed in the following example Assembly Language Source Program Example JP START Everything after the semicolon is
79. opcode 00H which corresponds to the fully programmed state of a byte in Flash memory To implement a Breakpoint write 00H to the desired address over writing the current instruction To remove a Breakpoint the corresponding page of Flash memory must be erased and reprogrammed with the original data Watchpoints The On Chip Debugger can set one Watchpoint to cause a Debug Break The Watchpoint identifies a single Register File address The Watchpoint can be set to break on reads and or writes of the selected Register File address Additionally the Watchpoint can be config ured to break only when a specific data value is read and or written from the specified reg PS017610 0404 On Chip Debugger Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG ister When the Watchpoint event occurs the Z8F640x family device enters Debug mode and the DBGMODE bit in the OCDCTL register becomes 1 Runtime Counter The On Chip Debugger contains a 16 bit Runtime Counter It counts system clock cycles between Breakpoints The counter starts counting when the On Chip Debugger leaves Debug mode and stops counting when it enters Debug mode again or when it reaches the maximum count of FFFFH On Chip Debugger Commands The host communicates to the On Chip Debugger by sending OCD commands using the DBG interface During normal operation of the Z8F640x family device only a subset of the OCD commands are available In Debug mode all OCD co
80. operation Refer to the eZ8 CPU User Manual for more information regarding interrupt servicing by the eZ8 CPU The eZ8 CPU User Man ual is available for download at www zilog com Interrupt Vector Listing 017610 0404 Table 22 lists all of the interrupts available on the Z8F640x family device in order of pri ority The interrupt vector is stored with the most significant byte MSB at the even Pro gram Memory address and the least significant byte LSB at the following odd Program Memory address Interrupt Controller 44 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Table 22 Interrupt Vectors in Order of Priority Zi 211 08 Program Memory Priority Vector Address Interrupt Source Interrupt Assertion Type Highest 0002h Reset not an interrupt Not applicable 0004h Watch Dog Timer Continuous assertion 0006h Illegal Instruction Trap not an interrupt Not applicable 0008h Timer 2 Single assertion pulse 000Ah Timer 1 Single assertion pulse 000Ch Timer 0 Single assertion pulse 000Eh UART 0 receiver Continuous assertion 0010h UART 0 transmitter Continuous assertion 0012h PC Continuous assertion 0014h SPI Continuous assertion 0016h ADC Single assertion pulse 0018h Port A7 or Port D7 rising or falling input edge Single assertion pulse 001Ah Port A6 or Port D6 rising or falling input edge Single assertion pulse
81. out by the SDA signal 11 The slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL The Controller sets the bit in the Status register 12 The Controller loads the contents of the PC Shift register with the contents of the PC Data register 13 The Controller shifts the data out of via the SDA signal After the first bit is sent the Transmit interrupt is asserted PS017609 0803 12C Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore a ZiLOG 14 Software responds by setting the STOP bit of the Control register 15 If no new data is to be sent or address is to be sent software responds by clearing the TXI bit of the Control register 16 The PC Controller completes transmission of the data on the SDA signal 17 The C Controller sends the STOP condition to the IC bus Writing a Transaction with a 10 Bit Address 1 The Controller shifts the Shift register out onto SDA signal 2 The Controller waits for the slave to send an Acknowledge by pulling the SDA signal Low If the slave pulls the SDA signal High Not Acknowledge the PC Controller sends a Stop signal 3 Ifthe slave needs to service an interrupt it pulls the SCL signal low which halts re operation 4 If there is no other data in the Data register or the STOP bit in the Control register is set by software then the Stop signal is sent
82. set to 1 a STOP Mode Recovery occurred If the STOP and WDT bits are both set to 1 the STOP Mode Recovery occurred due to a WDT time out If the STOP bit is 1 and the WDT bit is 0 the STOP Mode Recovery was not caused by a WDT time out This bit is reset by a Power On Reset or a WDT time out that occurred while not in STOP mode Reading this register also resets this bit WDT Watch Dog Timer Time Out Indicator If this bit is set to 1 a WDT time out occurred A Power On Reset resets this pin Stop Mode Recovery from a change in an input pin also resets this bit Reading this register resets this bit EXT External Reset Indicator If this bit is set to 1 a Reset initiated by the external RESET pin occurred A Power On Reset or a Stop Mode Recovery from a change in an input pin resets this bit Reading this register resets this bit PS017610 0404 Watch Dog Timer Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Reserved These bits are reserved and must be 0 Watch Dog Timer Reload Upper High and Low Byte Registers The Watch Dog Timer Reload Upper High and Low Byte WDTU WDTH WDTL reg isters Tables 47 through 49 form the 24 bit reload value that is loaded into the Watch Dog Timer when a WDT instruction executes The 24 bit reload value is WDTU 7 0 WDTH 7 0 WDTL 7 0 Writing to these registers sets the desired Reload Value Read ing from these registers returns the current Watch Dog Timer coun
83. the default for unprogrammed erased Flash PS017610 0404 Option Bits Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 151 ZiLOG On Chip Debugger Overview The Z8F640x family devices have an integrated On Chip Debugger OCD that provides advanced debugging features including Reading and writing of the Register File e Reading and writing of Program and Data Memory Setting of Breakpoints and Watchpoints Execution of eZ8 CPU instructions Architecture The On Chip Debugger consists of four primary functional blocks transmitter receiver auto baud generator and debug controller Figure 86 illustrates the architecture of the On Chip Debugger System Auto Baud eZ8 CPU Clock Detector Generator Control Transmitter A Debug Controller DBG Pin gt Receiver Figure 86 On Chip Debugger Block Diagram PS017610 0404 On Chip Debugger Operation OCD Interface Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG The On Chip Debugger uses the DBG pin for communication with an external host This one pin interface is a bi directional open drain interface that transmits and receives data Data transmission is half duplex in that transmit and receive cannot occur simultaneously The serial data on the DBG pin is sent using the standard asynchronous data format defined in RS 232 This pin can interface the Z8F640x family device t
84. time 65536 bytes can be written by setting size to zero The on chip Flash Controller must be written to and unlocked for the programming operation to occur If the Flash Controller is not unlocked the data is discarded If the Z8F640x family device is not in Debug mode or if the Read Protect Option Bit is enabled the data is discarded OAH Program Memory Address 15 8 DBG Program Memory Address 7 0 DBG Size 15 8 DBG Size 7 0 DBG 1 65536 data bytes Read Program Memory 0BH The Read Program Memory command reads data from Program Memory This command is equivalent to the LDC and LDCI instructions Data can be read 1 65536 bytes at a time 65536 bytes can be read by setting size to zero If the Z8F640x family device is not in Debug mode or if the Read Protect Option Bit is enabled this command returns FFH for the data Program Memory Address 15 8 Program Memory Address 7 0 Size 15 8 DBG Size 7 0 gt 1 65536 data bytes Write Data Memory 0CH The Write Data Memory command writes data to Data Memory This command is equivalent to the LDE and LDEI instructions Data can be written 1 65536 bytes at a time 65536 bytes can be written by setting size to zero If the Z8F640x family device is not in Debug mode or if the Read Protect Option Bit is enabled the data is discarded lt
85. to source MISO output data SCK falling edge used to sample MOSI input data Z8 Encore 211 08 MISO MM Output Data Output T2 TS lt gt Input SS N Input Figure 97 SPI Slave Mode Timing Table 111 SPI Slave Mode Timing Delay ns Parameter Abbreviation Minimum Maximum SCK transmit edge to MISO output Valid Delay 2 Xin 3 Xin period period 20 nsec MOSI input to SCK receive edge Setup Time 0 T3 MOSI input to SCK receive edge Hold Time 3 Xin period T4 SS input assertion to SCK setup 1 Xin period PS017610 0404 Electrical Characteristics 180 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 181 211089 IC Timing Figure 98 and Table 112 provide timing information for I2C pins 1 1 SCL Output T1 SDA X Output Data Output 1 T He lax e is X ae iia AE Input Figure 98 I C Timing Table 112 2 Timing Delay ns Parameter Abbreviation Minimum Maximum T SCL Fall to SDA output delay SCL period 4 T SDA Input to SCL rising edge Setup Time 0 T3 SDA Input to SCL falling edge Hold Time 0 PS017610 0404 Electrical Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 182 ZiLOG eZ8 CPU Instruction Set Assembly Language Programming Introduction The eZ8 CPU assembly language provides a
86. using the following equation A e System Clock Frequency Hz VART Baud Rate plius UART Baud Rate Divisor Value For a given UART data rate the integer baud rate divisor value is calculated using the fol lowing equation UART Baud Rate Divisor Value Round Clock Freyuency Han 16 x UART Data Rate bits s The baud rate error relative to the desired baud rate is calculated using the following equa tion Actual Data Rate Desired Data Rate UART Baud Rate Error 100 x Desired Data Rate For reliable communication the UART baud rate error must never exceed 5 percent Table 58 provides information on data rate errors for popular baud rates and commonly used crystal oscillator frequencies 017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 93 211 08 Table 58 UART Baud Rates 20 0 MHz System Clock 18 432 MHz System Clock Desired Rate BRG Divisor Actual Rate Error Desired Rate BRG Divisor Actual Rate Error kHz Decimal kHz 90 kHz Decimal kHz 90 1250 0 1 1250 0 0 00 1250 0 1 1152 0 7 84 625 0 2 625 0 0 00 625 0 2 576 0 7 84 250 0 5 250 0 0 00 250 0 5 230 4 7 84 115 2 11 113 6 1 36 115 2 10 115 2 0 00 57 6 22 56 8 1 36 57 6 20 57 6 0 00 38 4 33 37 9 1 36 38 4 30 38 4 0 00 19 2 65 19 2 0 16 19 2 60 19 2 0 00 9 60 130 9 62 0 16 9 60 120 9 60 0 00 4 80 260 4 81 0 16
87. written into the shift register until the previous transmission is complete and receive data if valid has been read SPI Signals The four basic SPI signals are e MISO Master In Slave Out e Master Out Slave In SCK SPI Serial Clock SS Slave Select The following paragraphs discuss these SPI signals Each signal is described in both Mas ter and Slave modes Master In Slave Out The Master In Slave Out MISO pin is configured as an input in a Master device and as an output in a Slave device It is one of the two lines that transfer serial data with the most significant bit sent first The MISO pin of a Slave device is placed in a high impedance state if the Slave is not selected When the SPI is not enabled this signal is in a high impedance state Master Out Slave In The Master Out Slave In MOSI pin is configured as an output in a Master device and as an input in a Slave device It is one of the two lines that transfer serial data with the most significant bit sent first When the SPI is not enabled this signal is in a high impedance state Serial Clock The Serial Clock SCK is used to synchronize data movement both in and out of the device through its MOSI and MISO pins In Master mode the SPI s Baud Rate Generator creates the serial clock The Master drives the serial clock out its own SCK pin to the Slave s SCK pin When the SPI is configured as a Slave the SCK pin is an input and the clock
88. 0 Counting is started on the first rising edge of the Timer Input signal The current count is captured on subsequent rising edges of the Timer Input signal 1 Counting is started on the first falling edge of the Timer Input signal The current count is captured on subsequent falling edges of the Timer Input signal PRES Prescale value The timer input clock is divided by 2 where PRES can be set from 0 to 7 The prescaler is reset each time the Timer is disabled This insures proper clock division each time the Timer is restarted 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 TMODE Timer mode 000 One Shot mode 001 2 Continuous mode 010 2 Counter mode 011 PWM mode 100 Capture mode 101 Compare mode 110 2 Gated mode 111 Capture Compare mode Timers Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 72 ZiLOG Watch Dog Timer Overview Operation The Watch Dog Timer WDT helps protect against corrupt or unreliable software power faults and other system level problems which may place the Z8 Encore into unsuitable operating states The Watch Dog Timer includes the following features e On chip RC oscillator e selectable time out response Short Reset or interrupt e 24 bit programmable time out value The Watch Dog Timer WDT is a retriggerable one shot timer that rese
89. 0 00 38 4 16 39 1 1 73 38 4 9 38 4 0 00 19 2 33 18 9 0 16 19 2 18 19 2 0 00 9 60 65 9 62 0 16 9 60 36 9 60 0 00 4 80 130 4 81 0 16 4 80 72 4 80 0 00 2 40 260 2 40 0 03 2 40 144 2 40 0 00 1 20 521 1 20 0 03 1 20 288 1 20 0 00 0 60 1042 0 60 0 03 0 60 576 0 60 0 00 0 30 2083 0 30 0 02 0 30 1152 0 30 0 00 3 579545 MHz System Clock 1 8432 MHz System Clock Desired Rate BRG Divisor Actual Rate Error Desired Rate BRG Divisor Actual Rate Error kHz Decimal kHz 90 kHz Decimal kHz 90 1250 0 N A N A N A 1250 0 N A N A N A 625 0 N A N A N A 625 0 N A N A N A 250 0 1 223 72 10 51 250 0 N A 115 2 2 111 9 2 90 115 2 1 115 2 0 00 57 6 4 55 9 2 90 57 6 2 57 6 0 00 38 4 6 37 3 2 90 38 4 3 38 4 0 00 19 2 12 18 6 2 90 19 2 6 19 2 0 00 9 60 23 9 73 1 32 9 60 12 9 60 0 00 4 80 47 4 76 0 83 4 80 24 4 80 0 00 2 40 93 2 41 0 23 2 40 48 2 40 0 00 1 20 186 1 20 0 23 1 20 96 1 20 0 00 0 60 373 0 60 0 04 0 60 192 0 60 0 00 0 30 746 0 30 0 04 0 30 384 0 30 0 00 017610 0404 UART 94 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Infrared Encoder Decoder Overview Z8 Encore ZiLOG The Z8F640x family products contain two fully functional high performance UART to Infrared Encoder Decoders Endecs Each Infrared Endec is integrated with an on chip UART to allow easy communication between the Z8F640x family device and IrDA Phys ical Layer Specification Version 1 3 compliant infrared transceivers Infrared communica tion provi
90. 0 3 6 PLCC 68 Z8F6402VS020SC 78 64 65 536 4 4096 20 Oto 70 3 0 3 6 QFP 80 Z8F6403FT020SC Z8 Encore with 16KB Flash Extended Temperature Z8 16 16 384 2 2048 20 40to 105 3 0 3 6 PDIP 40 Z8F1601PM020EC Z8 Encore 16 16 384 2 2048 20 40to 105 3 0 3 6 LQFP 44 Z8F1601AN020EC Z8 Encore 16 16 384 2 2048 20 40to 105 3 0 3 6 PLCC 44 Z8F1601VN020EC Z8 Encore 16 16 384 2 2048 20 4010 105 3 0 3 6 LQFP 64 Z8F1602AR020EC Z8 16 16 384 2 2048 20 4010 105 3 0 3 6 PLCC 68 Z8F1602VS020EC Z8 Encore with 24KB Flash Extended Temperature 78 Encore 24 24 576 2 2048 20 40to 105 3 0 3 6 PDIP 40 Z8F2401PMO20EC Z8 Encore 24 24 576 2 2048 20 40to 105 3 0 3 6 LQFP 44 Z8F2401ANO20EC Z8 Encore 24 24 576 2 2048 20 40to 105 3 0 3 6 PLCC 44 Z8F2401VNO20EC Z8 Encore 24 24 576 2 2048 20 4010 105 3 0 3 6 LQFP 64 Z8F2402AR020EC Z8 24 24 576 2 2048 20 4010 105 3 0 3 6 PLCC 68 Z8F2402VS020EC Z8 Encore with 32KB Flash Extended Temperature Z8 Encore 32 32 768 2 2048 20 4010 105 3 0 3 6 PDIP 40 Z8F3201PMO20EC Z8 Encore 32 32 768 2 2048 20 4010 105 3 0 3 6 LQFP 44 Z8F3201ANO20EC 78 Encore 32 32 768 2 2048 20 4010 105 3 0 3 6 PLCC 44 7Z8F3201VN020EC Z8 Encore 32 32 768 2 2048 20 40to 105 3 0 3 6 LQFP 64 Z8F3202AR020EC Z8 Encore 32 32 768 2 2048 20 4010 105 3 0 3 6 PLCC 68 Z8F3202VS020EC PS01
91. 02 X X Z8F4801 X X X Z8F4802 X X Z8F4803 X Z8F6401 X X X Z8F6402 X X Z8F6403 X PS017610 0404 Signal and Pin Descriptions Pin Configurations Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 211 08 Figures 56 through 61 illustrate the pin configurations for all of the packages available in the Z8 Encore MCU family Refer to Table 2 for a description of the signals PDA RXD1 PD3 PC5 MISO 0 PA1 TOOUT 2 5 VDD vss PD1 PDO XOUT XIN AVDD PBO PB1 ANA1 PB4 ANA4 5 ANA5 40 35 30 25 21 PD5 TXD1 PC4 MOSI PA4 RXDO L PA5 TXDO SCL PA7 SDA PD6 CTS1 PC3 SCK vss VDD PC6 T2IN DBG PC1 T1OUT PCO T1IN AVSS VREF 2 7 ANA7 PB6 ANA6 Note Timer 3 is not supported 2 is not supported Figure 56 Z8Fxx01 in 40 Pin Dual Inline Package DIP 017610 0404 Signal and Pin Descriptions Note Timer 3 is not supported Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 8 ZiLOG lute ee DD aa C amp ZNO YIGIT O lt lt lt lt c 0o n0 nn nnnnnn i ds
92. 04H in Port A H Address Register accessible via Port A H Control Register PHDE 7 0 Port High Drive Enabled 0 The Port pin is configured for standard output current drive 1 The Port pin is configured for high output current drive Port A H Stop Mode Recovery Source Enable Sub Registers The Port A H STOP Mode Recovery Source Enable sub register Table 19 is accessed through the Port A H Control register by writing 05H to the Port A H Address register Setting the bits in the Port A H STOP Mode Recovery Source Enable sub registers to 1 configures the specified Port pins as a STOP Mode Recovery source During STOP Mode any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates STOP Mode Recovery PS017610 0404 General Purpose I O Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Zi 211 08 Table 19 Port A H STOP Mode Recovery Source Enable Sub Registers BITS 7 6 5 4 3 2 1 0 FIELD PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMREI PSMREO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR If 05H in Port A H Address Register accessible via Port A H Control Register PSMRE 7 0 Port STOP Mode Recovery Source Enabled 0 The Port pin is not configured as a STOP Mode Recovery source Transitions on this pin during Stop mode do not initiate STOP Mode Recovery 1 The Port pin is configured as a STOP Mode Recov
93. 0ZCO Contact ZILOG s worldwide customer support center for more information on ordering the Z8 Encore The customer support center is open from 7 a m to 7 p m Pacific Time The customer support toll free number for ZiLOG is 1 877 ZiLOGCS 1 877 945 6427 For Z8 Encore the customer support toll free number is 1 866 498 3636 The FAX num ber for the customer support center is 1 603 316 0345 Customers can also gain access to customer support using the ZiLOG website Z8 Encore has its own web page at www zilog com z8encore For customer service navigate your browser to e M http register zilog com login asp login servicelogin For technical support navigate your browser to http register zilog com login asp login supportlogin PS017610 0404 Ordering Information Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z z ZiLOG For valuable information about hardware and software development tools visit the ZiLOG web site at www zilog com The latest released version of ZDS can be down loaded from this site Part Number Description ZiLOG part numbers consist of a number of components as indicated in the following examples ZiLOG Base Products Z8 ZiLOG 8 bit microcontroller product F6 Flash Memory 64 Program Memory Size 01 Device Number A Package N Pin Count 020 Speed S Temperature Range Environmental Flow Packages LQFP SOIC SSOP
94. 0x Z8F320x Z8F240x Z8F160x Z8 Encore limit to the amount of data transferred in one operation When transmitting data or acknowledging read data from the slave the SDA signal changes in the middle of the low period of SCL and is sampled in the middle of the high period of SCL Interrupts the PC Controller contains three sources of interrupts Transmit Receive and Not Acknowledge interrupts interrupts occur when a Not Acknowledge is received from the slave or sent by the Controller and the Start or Stop bit is set This source sets bit 0 and can only be cleared by setting the Start or Stop bit When this inter rupt occurs the Controller waits until it is cleared before performing any action In an interrupt service routine this interrupt must be the first thing polled Receive interrupts occur when a byte of data has been received by the PC master This interrupt is cleared by reading from the PC Data register If no action is taken the PC Controller waits until this interrupt is cleared before performing any other action For Transmit interrupts to occur the TXI bit must be 1 in the VC Control register Trans mit interrupts occur under the following conditions when the transmit data register is empty The PC Controller is idle not performing an operation START bit is set and there is no valid data in the Shift or Data register to shift out The first bit of the byte of
95. 1 CONTROLLING DIMENSIONS mm 2 MAX COPLANARITY 10 0004 L 57 DETAIL A Figure 104 44 Lead Low Profile Quad Flat Package LQFP Figure 105 illustrates the 44 pin PLCC plastic lead chip carrier package available for the Z8F1601 Z8F2401 Z8F3201 Z8F4801 and Z8F6401 devices 1 ALE i D1 0 71 0 51 45 0287 020 a N 8 1 40 lt Lirinmmmmnmmmunrpr 1 iL H39 E rr q H js zs ESL 8 0 168 0 180 A L 051 0 36 q Pul EL 1 0590700014 a2 0 095 0 115 n jam m 1765 0 685 0 695 r1 q H L L 0 81 0 66 16 66 0 650 0 656 q 1 0 032 0 026 69 16 00 0 600 0 630 0 L3 re 1 27 BSC 0 050 BSC aci C R114064 2 NOTES 0 045 0 025 1 CONTROLLING DIMENSION INCH 2 LEADS ARE COPLANAR WITHIN 0 004 3 DIMENSION MM INCH Figure 105 44 Lead Plastic Lead Chip Carrier Package PLCC PS017610 0404 Packaging 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Figure 105 illustrates the 64 pin LQFP low profile quad flat package available for the Z8F1602 Z8F2402 Z8F3202 Z8F4802 and Z8F6402 devices MILLIMETER INCH SYMBOL MIN MAX MIN MAX A 140 1 60 0 055 0 063 AT 0 05 0 15 0 002 0 006 A2 135 145 0 053 0 057 b 0 17 0 27 0 007 0 011 c 0 09 0 20 0 004 0 008 HD 1175 1225 0 463 0482 D 9 90 10
96. 10 0 390 0 398 HE 1175 1225 0 463 0482 9 90 10 10 0 390 0 398 DETAIL a 0 50 BSC 0 0197 BSC 1 LE k 045 075 0 018 0 030 LE 100 REF 0 039 REF el n DETAIL A Figure 106 64 Lead Low Profile Quad Flat Package LQFP 1 CONTROLLING DIMENSIONS mm 2 COPLANARITY 0 10 0 004 Packaging Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 ZiLOG Figure 107 illustrates the 68 pin PLCC plastic lead chip carrier package available for the Z8F1602 Z8F2402 Z8F3202 Z8F4802 and Z8F6402 devices Figure 107 68 Lead Plastic Lead Chip Carrier Package PLCC PS017610 0404 Packaging Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Figure 108 illustrates the 80 pin QFP quad flat package available for the Z8F4803 and Z8F6403 devices D A2 1 1 1 DETAIL Esel L 1 DETAIL A Figure 108 80 Lead Quad Flat Package QFP 017610 0404 SYMBOL MILLIMETER INCH MIN MAX MIN MAX A1 0 10 0 38 004 015 A2 2 60 2 80 102 110 b 0 30 0 45 012 018 c 0 13 0 20 005 008 HD 23 70 24 15 933 951 D 19 90 20 10 783 791 17 70 18 15 697 415 E 13 90 14 10 547 555 0 80 BSC 0315 BSC 0 70 1 10 028 043 1 CONTROLLING DIMENSIONS MILLIMETER 2 LEAD COPLANARITY MAX 10 004 Packaging Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x
97. 160x Z8 Encore Zl o ZiLOG 2 Bg 88 P iF zz29000708g28po9z2s RE 2 _ ds TOIN 49 32 7 SDA PD2 PD6 CTS1 PC2 55 PC3 SCK RESET I PD7 RCOUT VDD VSS PE4 PES PE6 vss 56 251 PE7 PE2 VDD PE1 PEO VDD vss PC7 T20UT PD1 T30UT PC6 T2IN PDO T3IN 4 DBG XOUT I PC1 T1OUT XIN 64 17 PCO T1IN 1 8 16 e O O gt Figure 59 Z8Fxx02 64 Pin Low Profile Quad Flat Package LQFP PS017610 0404 Signal and Pin Descriptions Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 11 ZiLOG 5 o 8o o o 208 e lt gt lt 2 B gt Zaoog QroosduodQ0cuusuz iucoo lt lt lt lt lt aaa gt gt gt gt PAO 10 60 PA7 SDA PD2 PD6 CTS1 PC2 SS PC3 SCK RESET PD7 RCOUT VDD I VSS PE4 PES I vss I PE7 118 S2 VDD PEI PEO VDD vss I 7 T20UT VDD I PC6 T2IN PD1 TSOUT DBG T3IN I PC1 T1OUT XOUT I PCO T1IN 26 44 VSS 27 35 43 rT T Tt Tt to Tt Tt re ty 1 283222222222 509 ae SSS ses TT
98. 191 BTJ 190 BTJNZ 190 BTJZ 190 CALL procedure 190 capture mode 71 capture compare mode 71 Preliminary Index cc 184 CCF 189 characteristics electrical 167 clear 189 clock phase SPI 102 CLR 189 COM 190 compare 71 compare extended addressing 187 compare mode 71 compare with carry 187 compare with carry extended addressing 187 complement 190 complement carry flag 188 189 condition code 184 continuous assertion interrupt sources 47 continuous conversion ADC 134 continuous mode 70 control register definition UART 86 control register I2C 119 counter modes 70 CP 187 CPC 187 CPCX 187 CPU and peripheral overview 3 CPU control instructions 189 CPX 187 customer feedback form 216 customer information 216 customer service 213 D DA 184 187 data memory 19 data register I2C 118 DC characteristics 169 debugger on chip 151 DEC 187 decimal adjust 187 decrement 187 decrement and jump non zero 190 decrement word 187 DECW 187 PS017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z z ZiLOG destination operand 185 device port availability 33 DI 189 direct address 184 direct memory access controller 122 disable interrupts 189 DJNZ 190 DMA address high nibble register 126 configuring for DMA ADC data transfer 124 confiigurting DMAO 1 data transfer 123 control of ADC 135 control register 124 control register definitions 124 controller 5 DMA_ADC address regis
99. 21H 722H 723H 724H 725H 726H 727H 728H 729H 72AH 72BH 72CH 72DH 72bEH 72FH 730H 731H OPAL ND ta bv 732H 733H 734H 735H 11 736H 737H DMAA_ADDR set to 72H Table 77 Address Register DMAA ADDR BITS 7 6 5 4 3 2 1 0 FIELD DMAA ADDR Reserved RESET X X X X X X X X R W R W R W R W R W R W R W R W R W ADDR FBDH DMAA ADDR DMA ADC Address These bits specify the seven most significant bits of the 12 bit Register File addresses used for storing the ADC output data The ADC Analog Input Number defines the five least significant bits of the Register File address Full 12 bit address is DMAA_ADDR 7 1 4 bit ADC Analog Input Number 0 Reserved This bit is reserved and must be 0 PS017610 0404 Direct Memory Access Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Z ZiLOG DMA_ADC Control Register The DMA_ADC Control register enables and sets options DMA enable and interrupt enable for ADC operation Table 78 DMA ADC Control Register DMAACTL BITS 7 6 5 4 3 2 1 0 FIELD DAEN IRQEN Reserved ADC IN RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FBEH DAEN DMA ADC Enable 0 DMA ADC is disabled and the ADC Analog Input Number ADC IN is reset to 0 1 DMA ADC is enabled IRQEN Inte
100. 320x Z8F240x Z8F160x Z8 Encore 122 ZiLOG Direct Memory Access Controller Overview Operation DMAO PS017610 0404 The Z8F640x family device s Direct Memory Access DMA Controller provides three independent Direct Memory Access channels Two of the channels DMAO and DMA1 transfer data between the on chip peripherals and the Register File The third channel DMA_ADC controls the Analog to Digital Converter ADC operation and transfers the Single Shot mode ADC output data to the Register File and DMA1 Operation DMAO referred to collectively as DMAx transfer data either from the on chip peripheral control registers to the Register File or from the Register File to the on chip peripheral control registers The sequence of operations in a DMAx data transfer 15 1 DMAx trigger source requests a DMA data transfer 2 DMAx requests control of the system bus address and data from the eZ8 CPU 3 After the eZ8 CPU acknowledges the bus request DMAx transfers either a single byte or a two byte word depending upon configuration and then returns system bus control back to the eZ8 CPU 4 If Current Address equals End Address DMAxreloads the original Start Address If configured to generate an interrupt DMAx sends an interrupt request to the Interrupt Controller Ifconfigured for single pass operation DMAx resets the DEN bit in the DMAx Control register to 0 and the is disabled
101. 4 lt j iis dt e Input Figure 95 On Chip Debugger Timing Table 109 On Chip Debugger Timing Delay ns Parameter Abbreviation Minimum Maximum DBG Ti XIN Rise to DBG Valid Delay 15 T5 XIN Rise to DBG Output Hold Time 2 T3 DBG to XIN Rise Input Setup Time 10 T4 DBG to XIN Rise Input Hold Time DBG frequency System Clock 4 PS017610 0404 Electrical Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x SPI Master Mode Timing Figure 96 and Table 110 provide timing information for SPI Master mode pins Timing is shown with SCK rising edge used to source MOSI output data SCK falling edge used to sample MISO input data Timing on the SS output pin s is controlled by software AN N AM UMS iin MOSI Output Z8 Encore Z6 211 08 T2 TS lt P 4 gt Input 5017610 0404 Figure 96 SPI Master Mode Timing Table 110 SPI Master Mode Timing Parameter Abbreviation Delay ns Minimum Maximum T SCK Rise to MOSI output Valid Delay 5 5 To MISO input to SCK receive edge Setup Time 20 T3 MISO input to SCK receive edge Hold Time 0 Electrical Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x SPI Slave Mode Timing Figure 97 and Table 111 provide timing information for the SPI slave mode pins Timing is shown with SCK rising edge used
102. 4 80 240 4 80 0 00 2 40 521 2 40 0 03 2 40 480 2 40 0 00 1 20 1042 1 20 0 03 1 20 960 1 20 0 00 0 60 2083 0 60 0 02 0 60 1920 0 60 0 00 0 30 4167 0 30 0 01 0 30 3840 0 30 0 00 16 667 MHz System Clock 11 0592 MHz System Clock Desired Rate BRG Divisor Actual Rate Error Desired Rate BRG Divisor Actual Rate Error kHz Decimal kHz 90 kHz Decimal kHz 90 1250 0 1 1041 69 16 67 1250 0 N A N A N A 625 0 2 520 8 16 67 625 0 1 691 2 10 59 250 0 4 260 4 4 17 250 0 3 230 4 7 84 115 2 9 115 7 0 47 115 2 6 115 2 0 00 57 6 18 57 87 0 47 57 6 12 57 6 0 00 38 4 27 38 6 0 47 38 4 18 38 4 0 00 19 2 54 19 3 0 47 19 2 36 19 2 0 00 9 60 109 9 56 0 45 9 60 72 9 60 0 00 4 80 217 4 80 0 83 4 80 144 4 80 0 00 2 40 434 2 40 0 01 2 40 288 2 40 0 00 1 20 868 1 20 0 01 1 20 576 1 20 0 00 0 60 1736 0 60 0 01 0 60 1152 0 60 0 00 0 30 3472 0 30 0 01 0 30 2304 0 30 0 00 017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 211 08 Table 58 UART Baud Rates Continued 10 0 MHz System Clock 5 5296 MHz System Clock Desired Rate BRG Divisor Actual Rate Error Desired Rate BRG Divisor Actual Rate Error kHz Decimal kHz 90 kHz Decimal kHz 90 1250 0 N A N A N A 1250 0 N A N A N A 625 0 1 625 0 0 00 625 0 N A N A 250 0 3 208 33 16 67 250 0 1 345 6 38 24 115 2 5 125 0 8 51 115 2 3 115 2 0 00 57 6 11 56 8 1 36 57 6 6 57 6
103. 7 0 N A No alternate functions Port F PF 7 0 N A No alternate functions Port G 7 0 N A No alternate functions Port H PHO ANA8 ADC Analog Input 8 PHI 9 ADC Analog Input 9 PH2 ANAIO ADC Analog Input 10 PH3 Analog Input 11 GPIO Interrupts Many of the GPIO port pins can be used as interrupt sources Some port pins may be con figured to generate an interrupt request on either the rising edge or falling edge of the pin input signal Other port pin interrupts generate an interrupt when any edge occurs both rising and falling Refer to the Interrupt Controller chapter for more information on interrupts using the GPIO pins GPIO Control Register Definitions Four registers for each Port provide access to GPIO control input data and output data Table 12 lists these Port registers Use the Port A H Address and Control registers together to provide access to sub registers for Port configuration and control 017610 0404 General Purpose I O Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG Table 12 GPIO Port Registers and Sub Registers Port Register Mnemonic Port Register Name PxADDR Port A H Address Register Selects sub registers PxCTL Port A H Control Register Provides access to sub registers PxIN Port A H Input Data Register PxOUT Port A H Output Data Register Port Sub Register Mnemonic Port Register Name PxDD Data Direction PxAF Alterna
104. 7610 0404 Ordering Information Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 213 ZiLoG Table 128 Ordering Information Continued Flash RAM Max Speed Temp Voltage Part KB Bytes KB Bytes MHz C V Package Part Number 78 Encore with 48KB Flash Extended Temperature Z8 48 49 152 4 4096 20 4010 105 3 0 3 6 PDIP 40 Z8F4801PMO20EC 78 48 49 152 4 4096 20 4010 105 3 0 3 6 LQFP 44 Z8F4801ANO20EC 78 48 49 152 4 4096 20 4010 105 3 0 3 6 PLCC 44 Z8F4801VNO20EC 78 48 49 152 4 4096 20 4010 105 3 0 3 6 LQFP 64 Z8F4802AR020EC Z8 48 49 152 4 4096 20 40to 105 3 0 3 6 PLCC 68 Z8F4802VS020EC 78 48 49 152 4 4096 20 4010 105 3 0 3 6 80 Z8F4803FT020EC Z8 Encore with 64KB Flash Extended Temperature 78 64 65 536 4 4096 20 4010 105 3 0 3 6 PDIP 40 Z8F6401PMO20EC 78 Encore 64 65 536 4 4096 20 4010 105 3 0 3 6 LQFP 44 Z8F6401ANO20EC 78 Encore 64 65 536 4 4096 20 4010 105 3 0 3 6 PLCC 44 Z8F6401VNO20EC Z8 Encore 64 65 536 4 4096 20 4010 105 3 0 3 6 LQFP 64 Z8F6402AR020EC Z8 64 65 536 4 4096 20 4010 105 3 0 3 6 PLCC 68 Z8F6402VS020EC 78 64 65 536 4 4096 20 4010 105 3 0 3 6 80 Z8F6403FTO20EC Z8 Encore Development Tools Z8 Encore Developer Kit Z8ENCORE00
105. A 106 SPI Control Register SPICTL 107 SPI Status Register 108 SPI Mode Register SPIMODE 109 SPI Baud Rate High Byte Register SPIBRH 110 SPI Baud Rate Low Byte Register SPIBRL 110 Z8 Encore 2 211 08 List of Tables Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x 12 Data Register DCDATA 118 I2C Status Register 12 118 Control Register 12 119 I2C Baud Rate High Byte Register DOCBRH 121 Baud Rate Low Byte Register DCBRL 121 DMAx Control Register DMAxCTL 124 DMAx I O Address Register 126 DMAx Address High Nibble Register DMAxH 126 DMAx End Address Low Byte Register DMAxEND 128 DMAx Start Current Address Low Byte Register 128 DMA ADC Register File Address Example 129 DMA ADC Address Register DMAA
106. A H Alternate Function Sub Registers Port A H Output Control Sub Registers Port A H High Drive Enable Sub Registers Port A H Input Data Registers Port A H STOP Mode Recovery Source Enable SUD RESI1S ELS Hehe ee ete Port A H Output Data Register PXOUT Interrupt Vectors in Order of Priority Interrupt Request 0 Register IRQO Interrupt Request 1 Register IRQ1 Interrupt Request 2 Register IRQ2 IRQO Enable and Priority Encoding IRQO Enable High Bit Register IRQOENH IRQO Enable Low Bit Register IRQOENL IRQI Enable and Priority Encoding IRQI Enable Low Bit Register IRQIENL Z8 Encore Zl ZiLOG List of Tables Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x 1802 Enable and Priority Encoding 53 IRQI Enable High Bit Register IRQIENH 53 IRQ2 Enable Low Bit Register IRQ2ENL 54 IRQ2 En
107. ADDR 129 DMA ADC Control Register DMAACTL 130 DMA ADC Status Register DMAA STAT 131 ADC Control Register ADCCTL 135 ADC Data High Byte Register ADCD H 137 ADC Data Low Bits Register ADCD L 137 Z8F640x family Flash Memory Configurations 138 Flash Code Protection Using the Option Bits 142 Flash Control Register 144 Flash Status Register FSTAT 145 Flash Page Select Register 5 146 Flash Frequency High Byte Register FFREQH 147 Flash Frequency Low Byte Register FFREQL 147 Option Bits At Program Memory Address 0000H 149 Options Bits at Program Memory Address 0001H 150 OCD Baud Rate Limits 154 On Chip Debugger Commands 156 OCD Control Register OCDCTL 161 OCD Status Register OCDSTAT 162 OCD Watchpoint Control Address WPTCTL 163 OCD Watchpoint Address WPTADDR 164 OCD Watchpoint Data WPTDATA 164 Recommended Crystal Oscillator Specifications 2OMHz Operation 166 78 2 211 08 List of Tables Table 101 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 Table 111 Table 112 Table 113 Table 114 Table 115
108. Add ADDX dst src Add using Extended Addressing CP dst src Compare CPC dst src Compare with Carry CPCX dst src Compare with Carry using Extended Addressing CPX dst src Compare using Extended Addressing DA dst Decimal Adjust DEC dst Decrement DECW dst Decrement Word INC dst Increment INCW dst Increment Word MULT dst Multiply PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Table 118 Arithmetic Instructions Continued Mnemonic Operands Instruction SBC dst src Subtract with Carry SBCX dst src Subtract with Carry using Extended Addressing SUB dst src Subtract SUBX dst src Subtract using Extended Addressing Table 119 Bit Manipulation Instructions Mnemonic Operands Instruction BCLR bit dst Bit Clear BIT p bit dst Bit Set or Clear BSET bit dst Bit Set BSWAP dst Bit Swap CCF Complement Carry Flag RCF mE Reset Carry Flag SCF Set Carry Flag TCM dst src Test Complement Under Mask TCMX dst src Test Complement Under Mask using Extended Addressing dst src Test Under Mask TMX dst src Test Under Mask using Extended Addressing Table 120 Block Transfer Instructions Mnemonic Operands Instruction LDCI dst src Load Constant to from Program Memory and Auto Increment Addresses LDEI dst src Load External Data to from Data Memory and Auto Increment Addresses PS017610 0404
109. CSTTx D m 1 0d0rncowN gt I I m d d m non nan nn Figure 60 Z8Fxx02 in 68 Pin Plastic Leaded Chip Carrier PLCC PS017610 0404 Signal and Pin Descriptions 12 ZiLOG Z8 Encore Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Signal and Pin Descriptions 5 5 5 lt j xQ oz oz A AN om E E 5 PEDES 65 89565 88955895889 nnn anuon nunnnu nunnu nunununmn L e 1111 108 9va 83 d m x I SSAV 1 SYd J3HA pd I LIVNV SSA I OLWNY 294 ISOW tOd I EVNV 8d I ZYNY 49 tad 9VNV 98d edd I 99 OSIN S9d I VNV vad lid I IVNV Ld I OVNV 09 SSA I 6VNV LHd 0819 Vd I 8YNY 0Hd aday 10001 8 Q4N SSA m T N N I ee IITTI 2 cdostcogw ocunwM onoununurtzrc z SELES 3 amp Bk 5 8 ir PEZ lt n n n Figure 61 Z8Fxx03 in 80 Pin Quad Flat Package QFP 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Signal Descriptions Table 2 describes the Z8F640x family signals Refer to the section Pin Configurations
110. CTL bits are all set to zero DBG 20H DBG WPTCTL 7 0 WPTADDR 7 0 DBG WPTDATA 7 0 e Read Watchpoint 21H The Read Watchpoint command reads the current Watchpoint registers DBG 21H gt WPTCTL 7 0 gt WPTADDR 7 0 gt WPTDATA 7 0 On Chip Debugger Control Register Definitions OCD Control Register The OCD Control register controls the state of the On Chip Debugger This register enters or exits Debug mode and enables the BRK instruction It can also reset the Z8F640x fam ily device A reset and stop function can be achieved by writing 81H to this register A reset and go function can be achieved by writing 41H to this register If the Z8F640x family device is in Debug mode a run function can be implemented by writing 40H to this register Table 94 OCD Control Register OCDCTL BITS 7 6 5 4 3 2 1 0 FIELD BRKEN DBGACK Reserved RST RESET 0 0 0 0 0 0 0 0 R W R W R W R W R R R R R W DBGMODE Debug Mode Setting this bit to 1 causes the Z8F640x family device to enter Debug mode When in Debug mode the eZ8 CPU stops fetching new instructions Clearing this bit causes the eZ8 CPU to start running again This bit is automatically set when a BRK instruction is decoded and Breakpoints are enabled or when a Watchpoint Debug Break is detected If the Read Protect Option Bit is enabled th
111. Chip Debugger commands are enabled This setting is the default for unprogrammed erased Flash PS017610 0404 Option Bits Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG FHSWP Flash High Sector Write Protect FWP Flash Write Protect These two Option Bits combine to provide 3 levels of Program Memory protection FHSWP FWP Description 0 0 Programming and erasure disabled for all of Program Memory Programming Page Erase and Mass Erase via User Code is disabled Mass Erase is available through the On Chip Debugger 1 0 Programming and Page Erase are enabled for the High Sector of the Program Memory only The High Sector on the Z8F640x family device contains IKB to 4KB of Flash with addresses at the top of the available Flash memory Programming and Page Erase are disabled for the other portions of the Program Memory Mass erase through user code is disabled Mass Erase is available through the On Chip Debugger 1 1 Programming Page Erase and Mass Erase are enabled for all of Program Memory Program Memory Address 0001H Table 91 Options Bits at Program Memory Address 0001H BITS 7 6 5 4 3 2 1 0 FIELD Reserved RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Program Memory 0001H Note U Unchanged by Reset R W Read Write Reserved These Option Bits are reserved for future use and must always be 1 This setting is
112. Control Register Definitions ADC Control Register The ADC Control register selects the analog input channel and initiates the analog to dig ital conversion Table 80 ADC Control Register ADCCTL BITS 7 6 5 4 3 2 1 0 FIELD CEN Reserved VREF CONT ANAIN 3 0 RESET 0 0 0 0 0000 R W R W R W R W R W R W ADDR F70H CEN Conversion Enable 0 Conversion is complete Writing a 0 produces no effect The ADC automatically clears PS017610 0404 Analog to Digital Converter 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 this bit to O when a conversion has been completed Begin conversion Writing a 1 to this bit starts a conversion If a conversion is already in progress the conversion restarts This bit remains 1 until the conversion is complete Reserved This bit is reserved and must be 0 VREF 0 Internal voltage reference generator enabled The VREF pin should be left uncon nected or capacitively coupled to analog ground 1 Internal voltage reference generator disabled An external voltage reference must be provided through the VREF pin CONT 0 Single shot conversion ADC data is output once at completion of the 5129 system clock cycles 1 Continuous conversion ADC data updated every 256 system clock cycles ANAIN Analog Input Select These bits select the analog input for conversion Not all Port pins in this list a
113. F160x Z8 Encore Z ZiLOG Flash Frequency High and Low Byte Registers The Flash Frequency High and Low Byte registers combine to form a 16 bit value FFREQ to control timing for Flash program and erase operations The 16 bit binary Flash Frequency value must contain the system clock frequency in kHz and is calculated using the following equation FFREQ I5 0 FFREQH 7 0 FFREQL 7 0 UTR Caution Flash programming and erasure is not supported for system clock frequen cies below 32KHz 32768Hz or above 20MHz The Flash Frequency High and Low Byte registers must be loaded with the correct value to in sure proper operation of the Z8F640x family device Table 88 Flash Frequency High Byte Register FFREQH BITS 7 6 5 4 3 2 1 0 FIELD FFREQH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FFAH FFREQH Flash Frequency High Byte High byte of the 16 bit Flash Frequency value Table 89 Flash Frequency Low Byte Register FFREQL BITS 7 6 5 4 3 2 1 0 FIELD FFREQL RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FFBH FFREQL Flash Frequency Low Byte Low byte of the 16 bit Flash Frequency value PS017610 0404 Flash Memory 147 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore ZiLOG Option Bits Overview Option Bits allow user configuration of certain aspects of Z8F640x fam
114. FIELD T2ENL TIENL TOENL UORENL UOTENL I2CENL SPIENL ADCENL RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC2H T2ENL Timer 2 Interrupt Request Enable Low Bit TIENL Timer 1 Interrupt Request Enable Low Bit TOENL Timer 0 Interrupt Request Enable Low Bit UORENL UART 0 Receive Interrupt Request Enable Low Bit UOTENL UART 0 Transmit Interrupt Request Enable Low Bit I2CENL C Interrupt Request Enable Low Bit SPIENL SPI Interrupt Request Enable Low Bit ADCENL ADC Interrupt Request Enable Low Bit IRQ1 Enable High and Low Bit Registers The IRQ1 Enable High and Low Bit registers Tables 30 and 31 form a priority encoded enabling for interrupts in the Interrupt Request 1 register Priority is generated by setting bits in each register Table 29 describes the priority control for IRQ1 Table 29 IRQ1 Enable and Priority Encoding IRQIENH x IRQIENL x Priority Description 0 0 Disabled Disabled 0 1 Level 1 Low 1 0 Level 2 Nominal 1 1 Level3 High where x indicates the register bits from 0 through 7 017610 0404 Interrupt Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore i A 53 ZiLOG Table 30 IRQ1 Enable High Bit Register IRQ1ENH BITS 7 6 5 4 3 2 1 0 FIELD PAD7ENH PAD6ENH PADSENH PAD4ENH PAD3ENH PAD2ENH PADIENH PADOENH RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC4H
115. Flash Control Register Definitions Flash Control Register Table 85 Flash Control Register FCTL Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore a 211 08 The Flash Controller must be unlocked via Flash Control register before programming or erasing the Flash memory Writing the sequence 73H 8CH sequentially to the Flash Control register unlocks the Flash Controller When the Flash Controller is unlocked writ ing to the Flash Control register can initiate either Page Erase or Mass Erase of the Flash memory Writing an invalid value or an invalid sequence returns the Flash Controller to its locked state The Write only Flash Control Register shares its Register File address with the Read only Flash Status Register BITS 7 6 0 FIELD FCMD RESET 0 0 0 R W W W ADDR FF8H FCMD Flash Command 73H First unlock command 8CH Second unlock command 95H Page erase command must be third command in sequence to initiate Page Erase 63H Mass erase command must be third command in sequence to initiate Mass Erase 017610 0404 Flash Memory Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore a ZiLOG Flash Status Register The Flash Status register indicates the current state of the Flash Controller This register can be read at any time The Read only Flash Status Register shares its Register File address with the Write only Flash Control Registe
116. H Address register The Port A H Alternate Function sub registers select the alternate functions for the selected pins Refer to the GPIO Alternate Functions section to determine the alternate function associated with each port pin Caution Do not enable alternate function for GPIO port pins which do not have an associated alternate function Failure to follow this guideline may result in unpredictable operation Table 16 Port A H Alternate Function Sub Registers BITS 7 6 5 4 3 2 1 0 FIELD AF7 AF6 AF5 AF4 AF3 AF2 AFI RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR If 02H in Port A H Address Register accessible via Port A H Control Register PS017610 0404 General Purpose I O Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 AF 7 0 Port Alternate Function enabled 0 The port pin is in normal mode and the DDx bit in the Port A H Data Direction sub register determines the direction of the pin 1 The alternate function is selected Port pin operation is controlled by the alternate function Port A H Output Control Sub Registers The Port A H Output Control sub register Table 17 is accessed through the Port A H Control register by writing 03H to the Port A H Address register Setting the bits in the Port A H Output Control sub registers to 1 configures the specified port pins for open drain operation These sub registers affect the pi
117. L XX XX Undefined 017610 0404 Register File Address Map Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Reset and Stop Mode Recovery Overview The Reset Controller within the Z8F640x family devices controls Reset and STOP Mode Recovery operation In typical operation the following events cause a Reset to occur Power On Reset POR Voltage Brown Out VBO Watch Dog Timer time out when configured via the WDT RES Option Bit to initiate a reset External RESET pin assertion On Chip Debugger initiated Reset OCDCTL 1 set to 1 When the Z8F640x family device is in Stop mode a Stop Mode Recovery is initiated by either of the following Reset Types Watch Dog Timer time out GPIO Port input pin transition on an enabled Stop Mode Recovery source DBG pin driven Low The Z8F640x family provides several different types of Reset operation Stop Mode Recovery is considered a form of Reset The type of Reset is a function of both the current operating mode of the Z8F640x family device and the source of the Reset Table 7 lists the types of Reset and their operating characteristics The System Reset is longer than the Short Reset to allow additional time for external oscillator start up Table 7 Reset and Stop Mode Recovery Characteristics and Latency Reset Type Reset Characteristics and Latency Control Registers eZ8 CPU Reset Latency Delay System Reset Reset as applicable Rese
118. MISO pin to the MISO Master pin For a Master device operating in a multi master system if the SS pin is configured as an input and is driven Low by another Master the COL bit is set to 1 in the SPI Status Regis ter The COL bit indicates the occurrence of a multi master collision mode fault error con dition PS017610 0404 Serial Peripheral Interface Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z w ZiLOG Error Detection The SPI contains error detection logic to support SPI communication protocols and recog nize when communication errors have occurred The SPI Status register indicates when a data transmission error has been detected Overrun Write Collision An overrun error write collision indicates a write to the SPI Data register was attempted while a data transfer is in progress An overrun sets the OVR bit in the SPI Status register to 1 Writing a 1 to OVR clears this error flag Mode Fault Multi Master Collision A mode fault indicates when more than one Master is trying to communicate at the same time a multi master collision The mode fault is detected when the enabled Master s SS pin is asserted A mode fault sets the COL bit in the SPI Status register to 1 Writing a 1 to COL clears this error flag SPI Interrupts When SPI interrupts are enabled the SPI generates an interrupt after data transmission The SPI in Master mode generates an interrupt after a character has been sent A character
119. PxCTL BITS 7 6 5 4 3 2 1 0 FIELD PCTL RESET 00H R W R W ADDR FD5H FD9H FDDH FE1H FESH FE9H FEDH PCTL 7 0 Port Control The Port Control register provides access to all sub registers that configure the GPIO Port operation PS017610 0404 General Purpose I O Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Port Data Direction Sub Registers The Port A H Data Direction sub register is accessed through the Port A H Control regis ter by writing 01 to the Port A H Address register Table 15 Table 15 Port A H Data Direction Sub Registers BITS 7 6 5 4 3 2 1 0 FIELD DD7 DD6 DDS DD4 DD3 DD2 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR If 01H in Port A H Address Register accessible via Port A H Control Register DD 7 0 Data Direction These bits control the direction of the associated port pin Port Alternate Function opera tion overrides the Data Direction register setting 0 Output Data in the Port A H Output Data register is driven onto the port pin 1 Input The port pin is sampled and the value written into the Port A H Input Data Reg ister The output driver is tri stated Port A H Alternate Function Sub Registers The Port A H Alternate Function sub register Table 16 is accessed through the Port A H Control register by writing 02H to the Port A
120. R 190 Preliminary Index logical exclusive OR extended addressing 190 logical instructions 190 logical OR 190 logical OR extended addressing 190 low power modes 31 LQFP 44 lead 207 64 lead 208 M master interrupt enable 46 master in slave out and in 101 memory data 19 program 18 MISO 101 mode capture 71 capture compare 71 continuous 70 counter 70 gated 71 one shot 70 PWM 70 modes 71 MOSI 101 MULT 187 multiply 187 multiprocessor mode UART 84 N NOP no operation 189 not acknowledge interrupt 112 notation b 184 cc 184 DA 184 ER 184 IM 184 IR 184 Ir 184 IRR 184 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z z ZiLOG Irr 184 p 184 R 184 r 184 RA 184 RR 184 rr 184 vector 184 X 184 notational shorthand 184 OCD architecture 151 auto baud detector generator 154 baud rate limits 154 block diagram 151 breakpoints 155 commands 156 control register 161 data format 154 DBG pin to RS 232 Interface 152 debug mode 153 debugger break 190 interface 152 serial errors 155 status register 162 timing 178 watchpoint address register 164 watchpoint control register 163 watchpoint data register 164 watchpoints 155 OCD commands execute instruction 12H 160 read data memory 0DH 160 read OCD control register 05H 158 read OCD revision 00H 157 read OCD status register 02H 157 read program counter 07H 158 read program memory 0BH
121. RTx Transmit Data Register Data bytes written to the UARTx Transmit Data register Table 50 are shifted out on the TXDx pin The Write only UARTx Transmit Data register shares a Register File address with the Read only UARTx Receive Data register Table 50 UARTx Transmit Data Register Ux TXD BITS 7 6 5 4 3 2 1 0 FIELD TXD RESET X X X X X X X X R W W W W W W W W WwW ADDR F40H and F48H TXD Transmit Data UART transmitter data byte to be shifted out through the TXDx pin PS017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 UART x Receive Data Register Data bytes received through the RXDx pin are stored in the UARTx Receive Data register Table 51 The Read only UARTx Receive Data register shares a Register File address with the Write only UARTx Transmit Data register Table 51 UARTx Receive Data Register UxRXD BITS 7 6 5 4 3 2 1 0 FIELD RXD RESET X X X X X X X X R W R R R R R R R R ADDR F40H and F48H RXD Receive Data UART receiver data byte from the RXDx pin UARTx Status 0 and Status 1 Registers The UART x Status 0 and Status 1 registers Table 52 and 53 identify the current UART operating configuration and status Table 52 UARTx Status 0 Register UxSTATO BITS 7 6 5 4 3 2 1 0 FIELD RDA PE OE FE BRKD TDRE TXE CTS RESET 0 0 0 0 0 1 1 X
122. SIC Source Operand Indirect Address Prefix SP Stack Pointer PC Program Counter FLAGS Flags Register RP Register Pointer Immediate Operand Prefix Binary Number Suffix Hexadecimal Number Prefix Hexadecimal Number Suffix Assignment of a value is indicated by an arrow For example dst lt dst src Z8 Encore 2 211 08 indicates the source data is added to the destination data and the result is stored in the des tination location 017610 0404 eZ8 CPU Instruction Set Condition Codes Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 The 7 S and V flags control the operation of the conditional jump cc and JR cc instructions Sixteen frequently useful functions of the flag settings are encoded in a 4 bit field called the condition code cc which forms Bits 7 4 of the conditional jump instruc tions The condition codes are summarized in Table 117 Some binary condition codes can be created using more than one assembly code mnemonic The result of the flag test oper ation is used to decide if the conditional jump is executed Table 117 Condition Codes Assembly Binary Hex Mnemonic Definition Flag Test Operation 0000 0 F Always False 0001 1 LT Less Than S XOR 1 0010 2 LE Less Than or Equal Z OR 5 XOR V 1 0011 3 ULE Unsigned Less
123. Select 0 The transmitter sends one stop bit 1 The transmitter sends two stop bits LBEN Loop Back Enable 0 Normal operation 1 All transmitted data is looped back to the receiver Table 55 UARTx Control 1 Register UxCTL1 BITS 7 6 5 4 3 2 1 0 FIELD MPM MPE MPBT Reserved RDAIRQ IREN RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F43H and FABH BIRQ Baud Rate Generator Interrupt Request This bit sets an interrupt request when the Baud Rate Generator times out and is only set if a UART is not enabled The is bit produces no effect when the UART is enabled 0 Interrupts behave as set by UART control 1 The Baud Rate Generator generates a receive interrupt when it counts down to zero MPM Multiprocessor 9 bit mode Select This bit is used to enable Multiprocessor 9 bit mode 017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 0 Disable Multiprocessor mode 1 Enable Multiprocessor mode MPE Multiprocessor Enable 0 The UART processes all received data bytes 1 The UART processes only data bytes in which the multiprocessor data bit 9th bit is set to 1 MPBT Multiprocessor Bit Transmitter This bit is applicable only when Multiprocessor 9 bit mode is enabled 0 Send a 0 in the multiprocessor bit location of the data stream 9th bit 1 Senda 1 in the multiprocessor bit l
124. Start Current Address High Nibble These bits used with the DMAx Start Current Address Low register form a 12 bit Start Current Address The full 12 bit address is given by DMA_START_H 3 0 DMA_START 7 0 PS017610 0404 Direct Memory Access Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG DMAx Start Current Address Low Byte Register The DMAx Start Current Address Low register in conjunction with the DMAx Address High Nibble register forms a 12 bit Start Current Address Writes to this register set the Start Address for DMA operations Each time the DMA completes a data transfer the 12 bit Start Current Address increments by either 1 single byte transfer or 2 two byte word transfer Reads from this register return the low byte of the Current Address to be used for the next DMA data transfer PS017610 0404 Direct Memory Access Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 128 Table 74 DMAx Start Current Address Low Byte Register DMAxSTART BITS 7 6 5 4 3 2 1 0 FIELD DMA START RESET X X X X X X X X R W R W R W R W R W R W R W R W R W ADDR FB3H FHBH DMA START DMAx Start Current Address Low These bits with the four lower bits of the DMAx H register form the 12 bit Start Current address The full 12 bit address is given by DMA START H 3 0 START 7 0 DMAx End Address Low Byte Register The DMAx End A
125. The timers can be configured to operate in the following modes One Shot Mode In One Shot mode the timer counts up to the 16 bit Reload value stored in the Timer Reload High and Low Byte registers The timer input is the system clock Upon reaching the Reload value the timer generates an interrupt and the count value in the Timer High and Low Byte registers is reset to 0001H Then the timer is automatically disabled and stops counting Also if the Timer Output alternate function is enabled the Timer Output pin changes state for one system clock cycle from Low to High or from High to Low upon timer Reload If it is desired to have the Timer Output make a permanent state change upon One Shot time PS017610 0404 Timers Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG out first set the TPOL bit in the Timer Control Register to the start value before beginning One Shot mode Then after starting the timer set TPOL to the opposite bit value The steps for configuring a timer for One Shot mode and initiating the count are as fol lows 1 Write to the Timer Control register to Disable the timer Configure the timer for One Shot mode Set the prescale value Ifusing the Timer Output alternate function set the initial output level High or Low 2 Write to the Timer High and Low Byte registers to set the starting count value Write to the Timer Reload High and Low Byte registers to set the Reload value
126. This bit is active high while data is being transmitted to or from the PC Shift register NCKI NACK Interrupt This bit is set high when a Not Acknowledge condition is received or sent and neither the START nor the STOP bit is active When set this bit generates an interrupt that can only be cleared by setting the START or STOP bit allowing the user to specify whether he wants to perform a STOP or a repeated START Control Register The PC Control register enables the operation Table 68 2 Control Register IZCCTL BITS 7 6 5 4 3 2 1 0 FIELD IEN START STOP BIRQ TXI NAK FLUSH FILTEN RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR 52 017609 0803 IEN I C Enable This bit enables the 12 transmitter and receiver 12C Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 START Send Start Condition This bit sends the Start condition Once asserted it is cleared by the VC Controller after it sends the START condition or by deasserting the IEN bit After this bit is set the Start condition is sent if there is data in the Data or C Shift register If there is no data in one of these registers the Controller waits until data is loaded If this bit is set while the PC Controller is shifting out data it generates a START condition after the byte shifts and the acknowledge phase completed If the STOP bit is
127. Timer Low Byte register returns the value in the holding register This operation allows accurate reads of the full 16 bit timer count value while enabled When the timers are not enabled a read from the Timer Low Byte register returns the actual value in the counter Timer Output Signal Operation Timer Output is a GPIO Port pin alternate function Generally the Timer Output is toggled every time the counter is reloaded Timer Control Register Definitions Timers 0 2 are available in all packages Timer 3 is available only in the 64 68 and 80 pin packages Timer 0 3 High and Low Byte Registers The Timer 0 3 High and Low Byte TxH and TxL registers Tables 38 and 39 contain the current 16 bit timer count value When the timer is enabled a read from TxH causes the value in TxL to be stored in a temporary holding register read from TMRL always returns this temporary register when the timers are enabled When the timer is disabled reads from the TMRL reads the register directly Writing to the Timer High and Low Byte registers while the timer is enabled is not recom mended There are no temporary holding registers available for write operations so simul taneous 16 bit writes are not possible If either the Timer High or Low Byte registers are PS017610 0404 Timers Table 38 Timer 0 3 High Byte Register TxH Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 written during counting the 8 bit writte
128. Trap 0008 0037 Interrupt Vectors 0038 7FFFH Program Memory See Table 22 on page 45 for a list of the interrupt vectors 017610 0404 Address Space Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG Table 4 Z8F640x Family Program Memory Maps Continued Program Memory Address Hex Function Z8F480x Products 0000 0001 Flash Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 BFFFH Program Memory Z8F640x Products 0000 0001 Flash Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 FFFFH Program Memory See Table 22 on page 45 for a list of the interrupt vectors Data Memory PS017610 0404 The Z8F640x family devices contain 128 bytes of read only memory at the top of the eZ8 CPU s 64KB Data Memory address space The eZ8 CPU s LDE and LDEI instructions provide access to the Data Memory information Table 5 describes the Z8F640x family s Data Memory Map Table 5 Z8F640x family Data Memory Maps Data Memory Address Hex Function 0000H FFBFH Reserved FFCOH FFD3H Part Number 20 character ASCII alphanumeric code Left justified and filled with zeros FFDAH FFFFH Reserved Address Space Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Register File Address Map Z8 Encore
129. U Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Table 126 eZ8 CPU Instruction Summary Continued Z8 Encore Z ZiLOG Address Mode Flags Assembly Opcode s Fetch Instr Mnemonic Symbolic Operation dst src Hex Z S D Cycles Cycles DA dst dst lt DA dst R 40 X 2 2 IR 41 2 3 DEC dst dst lt dst 1 R 30 Hu E M 2 2 IR 31 2 3 DECW dst dst lt dst 1 RR 80 E 2 5 IRR 81 2 6 DI IRQCTL 7 lt 0 M LC 1 2 DJNZ dst RA dst lt dst 1 r OA FA ML S S o 2 3 if dst 0 lt PC X IRQCTL 7 1 9F ML CC 1 2 HALT Halt Mode TF 1 2 INC dst dst lt dst 1 R 20 2 2 IR 21 2 3 r OE FE 1 2 INCW dst dst lt dst 1 RR AO 2 5 IRR AI 2 6 IRET FLAGS lt Q SP BF we oe 1 5 SP lt SP 1 PC lt SP SP lt 2 IRQCTL 7 1 JP dst PC lt dst DA 8D M CC 3 2 IRR C4 2 3 JP cc dst if cc is true DA 0D FD ML S SZ 3 2 PC lt dst JR dst lt DA 8B 2 2 JR cc dst if cc is true DA OB FB 2 2 PC lt PC X Flags Notation Value is a function of the result of the operation Unaffected X Undefined 0 Reset to 0 1 Set to 1 PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Table 126 eZ8 CPU Instruct
130. X X X X X X R W R W R W R W R W R W R W R W R W ADDR F60H DATA Data Transmit and or receive data PS017610 0404 Serial Peripheral Interface Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 SPI Control Register The SPI Control register configures the SPI for transmit and receive operations Table 61 SPI Control Register SPICTL BITS 7 6 5 4 3 2 1 0 FIELD IRQE STR BIRQ PHASE CLKPOL WOR MMEN SPIEN RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F61H IRQE Interrupt Request Enable 0 SPI interrupts are disabled No interrupt requests are sent to the Interrupt Controller 1 SPI interrupts are enabled Interrupt requests are sent to the Interrupt Controller STR Start an SPI Interrupt Request 0 No effect 1 Setting this bit to 1 also sets the IRQ bit in the SPI Status register to 1 Setting this bit forces the SPI to send an interrupt request to the Interrupt Control This bit can be used by software for a function similar to transmit buffer empty in a UART BIRQ BRG Timer Interrupt Request If the SPI is enabled this bit has no effect If the SPI is disabled 0 The Baud Rate Generator timer function is disabled 1 The Baud Rate Generator timer function and time out interrupt are enabled PHASE Phase Select Sets the phase relationship of the data to the clock Refer to the SPI Clock Phase and Polarity Control secti
131. Z8F240x Z8F160x 2 Z8 Encore 21108 Table 6 Register File Address Map Continued Address Hex Register Description Mnemonic Reset Hex Page Timer 3 not available in 40 and 44 Pin Packages F18 Timer 3 High Byte T3H 00 66 F19 Timer 3 Low Byte T3L 01 66 FIA Timer 3 Reload High Byte T3RH FF 67 FIB Timer 3 Reload Low Byte T3RL FF 67 FIC Timer 3 PWM High Byte T3PWMH 00 69 FID Timer 3 PWM Low Byte T3PWML 00 69 FIE Reserved XX FIF Timer 3 Control T3CTL 00 70 F20 F3F Reserved XX UART 0 F40 UARTO Transmit Data UOTXD XX 86 UARTO Receive Data UORXD XX 87 F41 UARTO Status 0 UOSTATO 0000011Xb 87 F42 UARTO Control 0 UOCTLO 00 89 F43 UARTO Control 1 00 89 F44 UARTO Status 1 UOSTATI 00 87 F45 Reserved XX F46 UARTO Baud Rate High Byte UOBRH FF 91 F47 UARTO Baud Rate Low Byte UOBRL FF 91 UART 1 F48 UARTI Transmit Data UITXD XX 86 UART Receive Data UIRXD XX 87 F49 UARTI Status 0 UISTATO 0000011Xb 87 F4A UARTI Control 0 UICTLO 00 89 F4B UARTI Control 1 UICTLI 00 89 FAC UARTI Status 1 UISTATI 00 87 FAD Reserved XX 4 UARTI Baud Rate High Byte UIBRH FF 91 4 UARTI Baud Rate Low Byte UIBRL FF 91 F50 Data DCDATA 00 118 F51 Status I2CSTAT 80 118 F52 PC Control DCCTL 00 119 F53 Baud Rate High Byte DCBRH FF 121 F54 Baud Rate Low Byte DCBRL FF 121 F55 F5F Reserved
132. Z8F640x family device is in STOP mode the Watch Dog Timer initiates a Stop Mode Recovery Both the WDT sta tus bit and the STOP bit in the Watch Dog Timer Control register are set to 1 following WDT time out in STOP mode Refer to the Reset and Stop Mode Recovery chapter for more information Watch Dog Timer Reload Unlock Sequence Writing the unlock sequence to the Watch Dog Timer Control register WDTCTL unlocks the three Watch Dog Timer Reload Byte registers WDTU WDTH and WDTL to allow changes to the time out period These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register The locking mechanism prevents spurious writes to the Reload registers The follow sequence is required to unlock the Watch Dog Timer Reload Byte registers WDTU WDTH and WDTL for write access 1 Write 55H to the Watch Dog Timer Control register WDTCTL 2 Write AAH to the Watch Dog Timer Control register WDTCTL 3 Write the Watch Dog Timer Reload Upper Byte register 4 Wirite the Watch Dog Timer Reload High Byte register WDTH 5 Write the Watch Dog Timer Reload Low Byte register WDTL All three Watch Dog Timer Reload registers must be written in the order just listed There must be no other register writes between each of these operations If a register write occurs the lock state machine resets and no further writes can occur unless the sequence is restarted The value in the Watch Dog Timer Rel
133. a comment START A label called START The first instruction JP START in this example causes program execution to jump to the point within the program where the START label occurs LD R4 R7 A Load LD instruction with two operands The first operand Working Register R4 is the destination The second operand Working Register R7 is the source The contents of R7 is written into R4 LD 234H 01 Another Load LD instruction with two operands The first operand Extended Mode Register Address 234H identifies the destination The second operand Immediate Data PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG value 01H is the source The value 01H is written into the Register at address 234H Assembly Language Syntax For proper instruction execution eZ8 CPU assembly language syntax requires that the operands be written as destination source After assembly the object code usually has the operands in the order source destination but ordering is opcode dependent The fol lowing instruction examples illustrate the format of some basic assembly instructions and the resulting object code produced by the assembler This binary format must be followed by users that prefer manual program coding or intend to implement their own assembler Example 1 If the contents of Registers 43H and 08H are added and the result is stored in 43H th
134. able High Bit Register IRQ2ENH 54 Interrupt Edge Select Register IRQES 55 Interrupt Port Select Register IRQPS 55 Interrupt Control Register IRQCTL 56 Timer 0 3 High Byte Register TXH 67 Timer 0 3 Low Byte Register TXL 67 Timer 0 3 Reload High Byte Register 68 Timer 0 3 Reload Low Byte Register TXRL 68 Timer 0 3 PWM High Byte Register TXPWMH 69 Timer 0 3 PWM Low Byte Register TXPWML 69 Timer 0 3 Control Register TXCTL 70 Watch Dog Timer Approximate Time Out Delays 73 Watch Dog Timer Control Register WDTCTL 75 Watch Dog Timer Reload Upper Byte Register WDTU 76 Watch Dog Timer Reload High Byte Register WDTH 76 Watch Dog Timer Reload Low Byte Register WDTL 77 UARTx Transmit Data Register UXTXD 86 UARTX Receive Data Register UXRXD 87 UARTX Status 0 Register UXSTATO 87 UARTX Control 0 Register UxCTLO 89 UARTX Status 1 Register UXSTATI 89 UARTX Control 1 Register UxCTL1 90 UARTx Baud Rate High Byte Register UXBRH 9 UARTx Baud Rate Low Byte Register UxBRL 92 UART Baud Rates 93 SPI Clock Phase PHASE and Clock Polarity CLKPOL Operation 102 SPI Data Register SPIDAT
135. also set it also waits until the STOP condition is sent before the START condition If this bit is 1 it cannot be cleared to 0 by writing to the register This bit clears when the PC is disabled STOP Send Stop Condition This bit causes the Controller to issue a Stop condition after the byte in the PC Shift register has completed transmission or after a byte has been received in a receive opera tion Once set this bit is reset by the PC Controller after Stop condition has been sent or by deasserting the bit If this bit is 1 it cannot be cleared to 0 by writing to the regis ter This bit clears when the IC is disabled BIRQ Baud Rate Generator Interrupt Request This bit causes an interrupt to occur every time the baud rate generator counts down to zero This bit allows the I C Controller to be used as an additional counter when it is not being used elsewhere This bit must only be set when the PC Controller is disabled TXI Enable TDRE interrupts This bit enables interrupts when the PC Data register is empty on the PC Controller NAK Send This bit sends a Not Acknowledge condition after the next byte of data has been read from the PC slave Once asserted it is deasserted after a Not Acknowledge is sent or the bit is deasserted FLUSH Flush Data Setting this bit to 1 clears the PC Data register and sets the TDRE bit to 1 This bit allows flushing of the PC Data register when an NAK is received afte
136. amily products support all 8 ports A H Table 10 lists the port pins available with each device and package type Table 10 Port Availability by Device and Package Type Device Packages PortA PortB PortC PortD PortE PortF PortG PortH Z8F1601 40 pin 7 0 7 0 6 0 6 3 1 0 Z8F1601 44 pin 7 0 7 0 7 0 6 0 Z8F1602 64 and 68 pin 7 0 7 0 7 0 7 0 7 0 7 3 3 0 Z8F2401 40 pin 7 0 7 0 6 0 6 3 1 0 Z8F2401 44 pin 7 0 7 0 7 0 6 0 Z8F2402 64 and 68 pin 7 0 7 0 7 0 7 0 7 0 7 3 3 0 Z8F3201 40 pin 7 0 7 0 6 0 6 3 1 0 Z8F3201 44 pin 7 0 7 0 7 0 6 0 Z8F3202 64 and 68 pin 7 0 7 0 7 0 7 0 7 0 7 3 3 0 Z8F4801 40 pin 7 0 7 0 6 0 6 3 1 0 Z8F4801 44 pin 7 0 7 0 7 0 6 0 Z8F4802 64 and 68 pin 7 0 7 0 7 0 7 0 7 0 7 3 3 0 Z8F4803 80 pin 7 0 7 0 7 0 7 0 7 0 7 0 7 0 3 0 Z8F6401 40 pin 7 0 7 0 6 0 6 3 1 0 PS017610 0404 General Purpose I O Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 34 211089 Table 10 Port Availability by Device and Package Type Continued Device Packages PortA PortB PortC PortD PortE PortF PortG Port H Z8F6401 44 pin 7 0 7 0 7 0 6 0 Z8F6402 64 and 68 pin 7 0 7 0 7 0 7 0 7 0 7 3 3 0 Z8F6403 80 pin 7 0 7 0 7 0 7 0 7 0 7 0 7 0 3 0 Archite
137. an address is shifting out and the RD bit of the Status register is deasserted first bit of a 10 bit address shifts out first bit of write data shifted out Note Writing to the PC Data register always clears a Transmit interrupt Start and Stop Conditions The master PC drives all Start and Stop signals and initiates all transactions To start a transaction the Controller generates a START condition by pulling the SDA signal low while SCL is high Then a high to low transition occurs on the SDA signal while the clock is High To complete a transaction the PC Controller generates a Stop condition by creating a low to high transition of the SDA signal in the middle of the high period of the SCL signal When the SCL signal is High the master generates a Start bit by pulling a High SDA signal Low and generates a Stop bit by releasing the SDA signal The Start and Stop signals are found in the PC Control register and must be written by software when the Z8F640x family device must begin or end a transaction Writing a Transaction with a 7 Bit Address 1 The Controller shifts the Shift register out onto SDA signal 017609 0803 12C Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 The Controller waits for the slave to send an Acknowledge by pulling the SDA signal Low If the slave pulls the SDA signal High Not Acknowledge the rc Controller sends a Stop signal 3 Ift
138. and Timing Continued Vpp 3 0 3 6V 40 C to 105 C Symbol Parameter Minimum Typical Maximum Units Conditions DC Offset Error 50 25 mV 40 pin PDIP 44 pin LQFP 44 pin PLCC and 68 pin PLCC packages VREF Internal Reference Voltage 2 0 V Single Shot Conversion 5129 cycles System clock cycles Time Continuous Conversion Time 256 cycles System clock cycles Sampling Rate System Clock 256 Hz Signal Input Bandwidth 3 5 kHz Rg Analog Source Impedance 10 Zin Input Impedance 150 kQ 20MHz system clock Input impedance increases with lower system clock frequency VREF External Reference Voltage AVDD V AVDD lt VDD When using an external reference voltage decoupling capacitance should be placed from VREF to AVSS Analog source impedance affects the ADC offset voltage because of leakage and input settling time 017610 0404 Electrical Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore ZI ZiLOG General Purpose I O Port Input Data Sample Timing Figure 93 illustrates timing of the GPIO Port input sampling The input value on a GPIO Port pin is sampled on the rising edge of the system clock The Port value is then available to the eZ8 CPU on the second rising clock edge following the change of the Port value System Clock Port Pin Input Value Port Input Data Register Latch TCLK
139. appearing in the ZiLOG Inc Terms and Conditions of Sale ZiLOG Inc makes no warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG use of information devices or technology as critical components of life support systems is not authorized No licenses are conveyed implicitly or otherwise by this document under any intellectual property rights 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Table of Contents hitroduction ya Rr E Sena Dee eae ee 1 E6at reS zc cde PRSE E ET YES 1 Part Selection Guide eee ene nee 2 Block Diagraitts 3 CPU and Peripheral Overview 3 eZ8 CPU B atures RA RR Rp e ded 3 General Purpose VO sisare gie t N eee 4 Flash Controllet 4 10 Bit Analog to Digital Converter 4 VARTS oiana 4 ee 4 Serial Peripheral 5 9 Interrupt Controller eec e RR Rea 5 Reset Controller eR Eee CO ve dak des 5 On Chip Debugger 25 5 er e acm xe rwn 5 DMA Controller ERROR dt Signal and Pin Descriptions 6 OVerVIeW nde Eu Es 6 Available Packages 6 P
140. art Address and continues operating DDIR DMAx Data Transfer Direction 0 Register File on chip peripheral control register 1 on chip peripheral control register Register File IRQEN DMAx Interrupt Enable 0 DMAx does not generate any interrupts 1 DMAx generates an interrupt when the End Address data is transferred WSEL Word Select 0 DMAx transfers a single byte per request 1 DMAx transfers two byte word per request The address for the on chip peripheral control register must be an even address RSS Request Trigger Source Select The Request Trigger Source Select field determines the peripheral that can initiate a DMA request transfer The corresponding interrupts do not need to be enabled within the Inter rupt Controller to initiate a DMA transfer However if the Request Trigger Source can enable or disable the interrupt request sent to the Interrupt Controller the interrupt request must be enabled within the Request Trigger Source block 000 Timer 0 001 Timer 1 010 Timer 2 011 Timer 3 100 DMAO Control register UARTO Received Data register contains valid data DMA1 Control register UARTO Transmit Data register empty 101 DMAO Control register UARTI Received Data register contains valid data DMA1 Control register UARTI Transmit Data register empty 110 DMAO Control register PC Receiver Interrupt DMA1 Control register PC Trans mitter Interrupt register empty 111 Reser
141. atchpoint control 163 OCD watchpoint data 164 SPI baud rate high byte SPIBRH 110 SPI baud rate low byte SPIBRL 110 SPI control SPICTL 107 SPI data SPIDATA 106 SPI status SPISTAT 108 PS017610 0404 Preliminary Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z z ZiLOG status I2C 118 status SPI 108 UARTX baud rate high byte UXBRH 91 UARTx baud rate low byte UxBRL 92 UARTX Control 0 UxCTLO 89 UARTx control 1 UxCTL1 90 UARTx receive data UxRXD 87 UARTx status 0 UXSTATO 87 UARTx status 1 UXSTATI 89 UARTx transmit data UxTXD 86 watch dog timer control WDTCTL 75 watch dog timer reload high byte WDTH 76 watch dog timer reload low byte WDTL 77 watch dog timer reload upper byte WDTU 76 register file 17 register file address map 20 register pair 184 register pointer 185 reset and stop mode characteristics 25 and stop mode recovery 25 carry flag 188 controller 5 sources 26 RET 190 return 190 return information 216 RL 191 RLC 191 rotate and shift instructions 191 rotate left 191 rotate left through carry 191 rotate right 191 rotate right through carry 191 RP 185 RR 184 191 rr 184 RRC 191 S SBC 188 SCF 188 189 SCK 101 Index SDA and SCL IrDA signals 111 second opcode map after 1FH 205 serial clock 101 serial peripheral interface SPI 99 set carry flag 188 189 set register pointer 189 shift right arithmetic 191 shift right logical 191 signal de
142. ate 0 Write FCTL Byte Program Write FCTL 73H Mass Erase Yes Y Lock State 1 Write FCTL o Yes Unlocked Program Erase 3 amp Enabled Figure 85 Flash Controller Operation Flow Chart PS017610 0404 Flash Memory Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Flash Operation Timing Using the Flash Frequency Registers Before performing either a program or erase operation on the Flash memory the user must first configure the Flash Frequency High and Low Byte registers The Flash Frequency registers allow programming and erasure of the Flash with system clock frequencies rang ing from 32KHz 32768Hz through 20MHz The Flash Frequency High and Low Byte registers combine to form a 16 bit value FFREQ to control timing for Flash program and erase operations The 16 bit binary Flash Frequency value must contain the system clock frequency in kHz This value is calcu lated using the following equation System Clock Frequency Hz FFREQ 15 0 Z Caution Flash programming and erasure are not supported for system clock fre quencies below 32KHz 32768Hz or above 20MHz The Flash Frequency High and Low Byte registers must be loaded with the correct value to in sure proper operation of the Z8F640x family device Flash Code Protection Against External Access The user code
143. bug Break OCD Watchpoint Data Register The OCD Watchpoint Data register specifies the data to match if Watchpoint data match is enabled Table 98 OCD Watchpoint Data WPTDATA BITS 7 6 5 4 3 2 1 0 FIELD RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W WPTDATA 7 0 Watchpoint Register File Data These bits specify the Register File data to match when generating Watchpoint Debug Breaks with the WPDM bit WPTCTL 5 is set to 1 PS017610 0404 On Chip Debugger Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore ZiLOG On Chip Oscillator The Z8F640x family devices feature an on chip oscillator for use with an external 1 20MHz crystal This oscillator generates the primary system clock for the internal eZ8 CPU and the majority of the on chip peripherals Alternatively the input pin can also accept a CMOS level clock input signal 32kHz 20MHz If an external clock generator is used the pin must be left unconnected The Z8F640x family device does not con tain in internal clock divider The frequency of the signal on the input pin determines the frequency of the system clock The Z8F640x family device on chip oscillator does not support external RC networks or ceramic resonators 20MHz Crystal Oscillator Operation 017610 0404 Figure 90 illustrates a recommended configuration for connection with an external 20MHz fundamental mode parallel resonant
144. ck Frequency Hz Gated Mode In Gated mode the timer counts only when the Timer Input signal is in its active state asserted as determined by the TPOL bit in the Timer Control register When the Timer Input signal is asserted counting begins A timer interrupt is generated when the Timer Input signal is deasserted or a timer reload occurs To determine if a Timer Input signal deassertion generated the interrupt read the associated GPIO input value and compare to the value stored in the TPOL bit The timer counts up to the 16 bit Reload value stored in the Timer Reload High and Low Byte registers The timer input is the system clock When reaching the Reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes assuming the Timer Input signal is still asserted Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low at timer reset The steps for configuring a timer for Gated mode and initiating the count are as follows 1 Write to the Timer Control register to Disable the timer Timers Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Configure the timer for Gated mode Set the prescale value 2 Write to the Timer High and Low Byte registers to set the starting count value This only affects the first pass in Gated mode After the first timer
145. ctored interrupts the interrupt controller passes an interrupt request to the eZ8 CPU If interrupts are globally disabled polled interrupts the eZ8 CPU can read the Interrupt Request 1 register to determine if any interrupt requests are pending Table 25 Interrupt Request 2 Register IRQ2 BITS 7 6 5 4 3 2 1 0 FIELD UIRXI UITXI DMAI PC3I PCOI PCOI RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR 5017610 0404 T3I Timer 3 Interrupt Request 0 No interrupt request is pending for Timer 3 1 An interrupt request from Timer 3 is awaiting service UIRXI UART 1 Receive Interrupt Request 0 No interrupt request is pending for the UARTI receiver 1 An interrupt request from UARTI receiver is awaiting service UITXI UART 1 Transmit Interrupt Request 0 No interrupt request is pending for the UART 1 transmitter 1 An interrupt request from the UART 1 transmitter is awaiting service DMAI DMA Interrupt Request 0 No interrupt request is pending for the 1 An interrupt request from the is awaiting service PCxI Port C Pin x Interrupt Request 0 No interrupt request is pending for GPIO Port C pin x 1 An interrupt request from GPIO Port C pin x is awaiting service where x indicates the specific GPIO Port C pin number 0 through 3 Interrupt Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore
146. cture Figure 64 illustrates a simplified block diagram of a GPIO port pin In this figure the abil ity to accommodate alternate functions and variable port current drive strength are not illustrated Port Input Schmitt Trigger Data Register Q D Q D System Clock VDD Port Output Control Port Output mm SS Data Register DATA j Bus D Q 5o Port Pin System Clock b Port Data Direction GND Figure 64 GPIO Port Pin Block Diagram GPIO Alternate Functions Many of the GPIO port pins can be used as both general purpose I O and to provide access to on chip peripheral functions such as the timers and serial communication devices The Port A H Alternate Function sub registers configure these pins for either general purpose T O or alternate function operation When pin is configured for alternate function control PS017610 0404 General Purpose I O 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG of the port pin direction input output is passed from the Port A H Data Direction regis ters to the alternate function assigned to this pin Table 11 lists the alternate functions asso ciated with each port pin Table 11 Port Alternate Function Mapping Port Pin Mnemonic Alternate Function Description PortA TOIN Timer 0 I
147. d by the OCD When the OCD detects one of these errors it aborts any command currently in progress transmits a four character long Serial Break back to the host and resets the Auto Baud Detector Generator A Framing Error or Transmit Collision may be caused by the host sending a Serial Break to the OCD Because of the open drain nature of the interface returning a Serial Break break back to the host only extends the length of the Serial Break if the host releases the Serial Break early The host should transmit a Serial Break on the DBG pin when first connecting to the Z8F640x family device or when recovering from an error A Serial Break from the host resets the Auto Baud Generator Detector but does not reset the OCD Control register A Serial Break leaves the Z8F640x family device in Debug mode if that is the current mode The OCD is held in Reset until the end of the Serial Break when the DBG pin returns High Because of the open drain nature of the DBG pin the host can send a Serial Break to the OCD even if the OCD is transmitting a character Breakpoints Execution Breakpoints are generated using the BRK instruction opcode 00H When the eZ8 CPU decodes a BRK instruction it signals the On Chip Debugger If Breakpoints are enabled the OCD enters Debug mode and idles the eZ8 CPU If Breakpoints are not enabled the OCD ignores the BRK signal and the BRK instruction operates as an NOP Breakpoints in Flash Memory The BRK instruction is
148. ddress Low Byte register in conjunction with the DMAx H register forms a 12 bit End Address Table 75 DMAx End Address Low Byte Register DMAxEND BITS 7 6 5 4 3 2 1 0 FIELD DMA END RESET X X X X X X X X R W R W R W R W R W R W R W R W R W ADDR DMA END DMAx End Address Low These bits with the four upper bits of the DMAx H register form a 12 bit address This address is the ending location of the DMAx transfer The full 12 bit address is given by DMA END H 3 0 DMA END 7 0 DMA ADC Address Register The DMA ADC Address register points to a block of the Register File to store ADC con version values as illustrated in Table 76 This register contains the seven most significant bits of the 12 bit Register File addresses The five least significant bits are calculated from the ADC Analog Input number 5 bit base address is equal to twice the ADC Analog Input number The 10 bit ADC conversion data is stored as two bytes with the most significant byte of the ADC data stored at the even numbered Register File address PS017610 0404 Direct Memory Access Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Table 76 provides an example of the Register File addresses if ADC Address register contains the value 72H Table 76 DMA ADC Register File Address Example ADC Analog Input Register File Address Hex 0 720H 7
149. des secure reliable low cost point to point communication between PCs PDAs cell phones printers and other infrared enabled devices Architecture Figure 71 illustrates the architecture of the Infrared Endec Interrupt y o Signal Address System Clock RxD 28 TxD Infrared UART m Encoder Decoder Baud Rate Endec L Clock p Data RXD TXD ZiLOG ZHX1810 RXD TXD Infrared Transceiver Figure 71 Infrared Data Communication System Block Diagram 017610 0404 Infrared Encoder Decoder 95 Operation Infrared Data Rate bits s Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG When the Infrared Endec is enabled the transmit data from the associated on chip UART is encoded as digital signals in accordance with the IrDA standard and output to the infra red transceiver via the TXD pin Likewise data received from the infrared transceiver is passed to the Infrared Endec via the RXD pin decoded by the Infrared Endec and then passed to the UART Communication is half duplex which means simultaneous data transmission and reception is not allowed The baud rate is set by the UART s Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to 115 2 kbaud Higher baud rates are possible but do not meet IrDA specifications The UART must be enabled to use the Infrared Endec The Infrared Endec
150. development time and program changes in the field The new eZ8 CPU is upward compat ible with existing Z8 instructions The rich peripheral set of the Z8F640x family makes it suitable for a variety of applications including motor control security systems home appliances personal electronic devices and sensors Features 017610 0404 eZ8 CPU 20 MHz operation 12 channel 10 bit analog to digital converter ADC 3 channel DMA Up to 64KB Flash memory with in circuit programming capability Up to 4KB register RAM Serial communication protocols Serial Peripheral Interface Two full duplex 9 bit UARTS 24 interrupts with programmable priority Three or four 16 bit timers with capture compare and PWM capability Single pin On Chip Debugger Two Infrared Data Association IrDA compliant infrared encoder decoders integrated with the UARTs Watch Dog Timer WDT with internal RC oscillator Up to 60 I O pins Voltage Brown out Protection VBO Introduction Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore ZI ZiLOG e Power On Reset POR e 3 0 3 6V operating voltage with 5V tolerant inputs 0 to 70 C standard temperature and 40 to 105 C extended temperature operating ranges Part Selection Guide Table 1 identifies the basic features and package styles available for each device within the Z8F640x family product line Table 1 Z8F640x Family Part Selection Guide
151. dress space returns an undefined value Writing to these Register File addresses produces no effect Refer to the Part Selection Guide sec tion of the Introduction chapter to determine the amount of RAM available for the spe cific Z8F640x family device PS017610 0404 Address Space 17 Program Memory Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 The eZ8 CPU supports 64KB of Program Memory address space The Z8F640x family devices contain 16KB to 64KB of on chip Flash memory in the Program Memory address space Reading from Program Memory addresses outside the available Flash memory addresses returns FFH Writing to these unemployments Program Memory addresses pro duces no effect Table 4 describes the Program Memory Maps for the Z8F640x family products Table 4 Z8F640x Family Program Memory Maps Program Memory Address Hex Function Z8F160x Products 0000 0001 Flash Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 3FFFH Program Memory 78 240 Products 0000 0001 Flash Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction Trap 0008 0037 Interrupt Vectors 0038 5FFFH Program Memory Z8F320x Products 0000 0001 Flash Option Bits 0002 0003 Reset Vector 0004 0005 WDT Interrupt Vector 0006 0007 Illegal Instruction
152. e DMA and UART can coordinate automatic data transfer from the UART Receive Data register to general purpose Register File RAM This reduces the eZ8 CPU process ing overhead required to support UART data reception The UART Receiver interrupt must then only notify the eZ8 CPU of error conditions Follow these steps to configure the UART and DMA for automatic data handling l 017610 0404 Write to the control registers to configure the to transfer data from the UART Receive Data register to general purpose Register File RAM Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation Write to the Interrupt control registers to enable the UART Receiver interrupt and set the desired priority Write to the UART Control 1 register to Enable Multiprocessor 9 bit mode functions if desired Disable the UART interrupt for received data by clearing RDAIRQ to 0 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 6 Write to the UART Control 0 register to Set the receive enable bit REN to enable the UART for data reception Enable parity if desired and select either even or odd parity The UART and DMA are now configured for data reception and automatic data transfer to the Register File When a valid data byte is received by the UART the follow
153. e Port transition only if the signal stays on the Port pin through the end of the STOP Mode Recovery delay Thus short pulses on the Port pin can initiate STOP Mode Recovery without be ing written to the Port Input Data register or without initiating an interrupt Gf enabled for that pin PS017610 0404 Reset and Stop Mode Recovery Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 31 ZiLOG Low Power Modes Overview Stop Mode Halt Mode PS017610 0404 The Z8F640x family products contain power saving features The highest level of power reduction is provided by Stop mode The next level of power reduction is provided by the Halt mode Execution of the eZ8 CPU s STOP instruction places the Z8F640x family device into Stop mode In Stop mode the operating characteristics are e Primary crystal oscillator is stopped e System clock is stopped e eZ8 CPU is stopped Program counter PC stops incrementing e Watch Dog Timer s internal RC oscillator continues to operate e If enabled the Watch Dog Timer continues to operate e All other on chip peripherals are idle To minimize current in Stop mode all GPIO pins that are configured as digital inputs must be driven to one of the supply rails Vcc or GND The Z8F640x family device can be brought out of Stop mode using Stop Mode Recovery For more information on STOP Mode Recovery refer to the Reset and Stop Mode Recovery chapter Execution of the eZ8 CPU s HALT instruc
154. e SDA signal Low during the next high period of SCL The PC slave sends a byte of data A Receive interrupt is generated Software responds by reading the PC Data register Software responds by setting the STOP bit of the PC Control register condition is sent to the 12 slave STOP condition is sent to the I C slave 12C Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 Control Register Definitions 2 Data Register The Data register holds the data that is to be loaded into the PC Shift register during a write to a slave This register also holds data that is loaded from the PC Shift register dur ing a read from a slave The Shift is not accessible in the Register File address space but is used only to buffer incoming and outgoing data Table 66 I C Data Register IZCDATA BITS 7 6 5 4 3 2 1 0 FIELD DATA RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR F50H 12 Status Register The Read only Status register indicates the status of the Controller Table 67 P C Status Register IZCSTAT BITS 7 6 5 4 3 2 1 0 FIELD TDRE RDRF ACK 10B RD TAS DSS NCKI RESET 1 0 0 0 0 0 0 0 R W R R R R R R R R ADDR F51H TDRE Transmit Data Register Empty When the Controller is enabled this bit is 1 when the PC Data register is empty When active this bit causes
155. e assembly syntax and resulting object code is Table 113 Assembly Language Syntax Example 1 Assembly Language Code ADD 08H ADD dst src Object Code 04 08 43 OPC src dst Example 2 In general when an instruction format requires an 8 bit register address that address can specify any register location in the range 0 255 or using Escaped Mode Addressing a Working Register RO R15 If the contents of Register 43H and Working Register R8 are added and the result is stored in 43H the assembly syntax and resulting object code is Table 114 Assembly Language Syntax Example 2 Assembly Language Code ADD 43H R8 ADD dst src Object Code 04 E8 43 OPC src dst See the device specific Product Specification to determine the exact register file range available The register file size varies depending on the device type eZ8 CPU Instruction Notation In the eZ8 CPU Instruction Summary and Description sections the operands condition codes status flags and address modes are represented by a notational shorthand that is described in Table 115 PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 7 184 211089 Table 115 Notational Shorthand Notation Description Operand Range b Bit b b represents a value from 0 to 7 000B to 111B cc Condition Code See Condition Codes overview in the eZ8 CPU User Manual DA Direct Address Add
156. e of the interrupt must be cleared first After the interrupt is cleared at the source the corresponding bit in the Interrupt Request register must also be cleared to 0 Both the interrupt source and the IRQ register must be cleared PS017610 0404 Interrupt Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Interrupt Control Register Definitions Z8 Encore Zi 211 08 For all interrupts other than the Watch Dog Timer interrupt the interrupt control registers enable individual interrupts set interrupt priorities and indicate interrupt requests Interrupt Request 0 Register The Interrupt Request 0 IRQO register Table 23 stores the interrupt requests for both vectored and polled interrupts When a request is presented to the interrupt controller the corresponding bit in the IRQO register becomes 1 If interrupts are globally enabled vec tored interrupts the interrupt controller passes an interrupt request to the eZ8 CPU If interrupts are globally disabled polled interrupts the eZ8 CPU can read the Interrupt Request 0 register to determine if any interrupt requests are pending Table 23 Interrupt Request 0 Register IRQO BITS 7 6 5 4 3 2 1 0 FIELD T2I TII TOI UORXI UOTXI I2CI SPII ADCI RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FCOH T2I Timer 2 Interrupt Request 0 No interrupt request is pending for Timer 2 1 An interrupt request from
157. e original Z8 instruction set The eZ8 CPU features include Direct register to register architecture allows each register to function as an accumulator improving execution time and decreasing the required program memory PS017610 0404 Introduction Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG e Software stack allows much greater depth in subroutine calls and interrupts than hardware stacks Compatible with existing Z8 code e Expanded internal Register File allows access of up to 4KB e New instructions improve execution efficiency for code developed using higher level programming languages including C Pipelined instruction fetch and execution e New instructions for improved performance including BIT BSWAP CPC LDC LEA MULT and SRL e New instructions support 12 bit linear addressing of the Register File e Upto 10 MIPS operation e C Compiler friendly 2 9 clock cycles per instruction For more information regarding the eZ8 CPU refer to the eZ8 CPU User Manual avail able for download at www zilog com General Purpose I O The Z8 Encore features seven 8 bit ports Ports A G and one 4 bit port Port for general purpose I O GPIO Each pin is individually programmable Flash Controller The Flash Controller programs and erases the Flash memory 10 Bit Analog to Digital Converter The Analog to Digital Converter ADC converts an analog input signal to a 10 bit binary number
158. em clock frequency Timer output pin Timer interrupt In addition to the timers described in this chapter the Baud Rate Generators for any unused UART SPI or PC peripherals may also be used to provide basic timing function ality Refer to the respective serial communication peripheral chapters for information on using the Baud Rate Generators as timers Timer 3 is unavailable in the 40 and 44 pin packages Architecture Figure 66 illustrates the architecture of the timers 017610 0404 Timers Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Timer Block Data Timer Bus lt Block Control 16 Bit Interrupt Timer Reload Register PWM Interrupt System Timer Output Timer Control Output Clock 16 Bit Counter with Prescaler EN Input Gate gt Input 16 Bit PWM Compare Input LE o Lo LL cR em imd E Figure 66 Timer Block Diagram Operation The timers are 16 bit up counters Minimum time out delay is set by loading the value 0001H into the Timer Reload High and Low Byte registers and setting the prescale value to 1 Maximum time out delay is set by loading the value 0000H into the Timer Reload High and Low Byte registers and setting the prescale value to 128 If the Timer reaches FFFFH the timer rolls over to 0000H and continues counting Timer Operating Modes
159. enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers Configure the associated GPIO port pin for the Timer Input alternate function 6 Ifusing the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 7 Write to the Timer Control register to enable the timer In Counter mode the number of Timer Input transitions since the timer start is given by the following equation Counter Mode Timer Input Transitions Current Count Value Start Value PWM Mode In PWM mode the timer outputs a Pulse Width Modulator PWM output signal through a GPIO Port pin The timer input is the system clock The timer first counts up to the 16 bit PWM match value stored in the Timer PWM High and Low Byte registers When the timer count value matches the PWM value the Timer Output toggles The timer continues counting until it reaches the Reload value stored in the Timer Reload High and Low Byte registers Upon reaching the Reload value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes If the TPOL bit in the Timer Control register is set to 1 the Timer Output signal begins as a High 1 and then transitions to a Low 0 when the timer value matches the PWM value The Timer Output signal returns to a High 1 after the timer reaches the Reload value and is reset to 0001H
160. ery source Any logic transition on this pin during Stop mode initiates STOP Mode Recovery Port A H Input Data Registers Reading from the Port A H Input Data registers Table 20 returns the sampled values from the corresponding port pins The Port A H Input Data registers are Read only Table 20 Port A H Input Data Registers PxIN BITS 7 6 5 1 3 2 1 0 FIELD PIN7 PING PINS PIN4 PIN3 PIN2 PINI PINO RESET x x x X x X X R W R R R R R R R R ADDR FD2H FD6H FDAH FDEH FE2H FE6H FEAH FEEH PIN 7 0 Port Input Data Sampled data from the corresponding port pin input 0 Input data is logical 0 Low 1 Input data is logical 1 High PS017610 0404 General Purpose I O Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Port A H Output Data Register The Port A H Output Data register Table 21 writes output data to the pins Table 21 Port A H Output Data Register PxOUT BITS 7 6 5 4 3 2 1 0 FIELD POUT7 POUT6 POUTS POUT4 POUT3 POUT2 POUTI POUTO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FD3H FD7H FDBH FDFH FE3H FE7H FEBH FEFH POUT 7 0 Port Output Data These bits contain the data to be driven out from the port pins The values are only driven if the corresponding pin is configured as an output and the pin is not configured for alter nate function operati
161. ese three address spaces are covered briefly in the following subsections For more detailed information regarding the eZ8 CPU and its address space refer to the eZ8 CPU User Manual available for download at www zilog com Register File The Register File address space in the Z8 Encore is 4 4096 bytes The Register File is composed of two sections control registers and general purpose registers When instructions are executed registers are read from when defined as sources and written to when defined as destinations The architecture of the eZ8 CPU allows all general purpose registers to function as accumulators address pointers index registers stack areas or scratch pad memory The upper 256 bytes of the 4KB Register File address space are reserved for control of the eZ8 CPU the on chip peripherals and the I O ports These registers are located at addresses from to FFFH Some of the addresses within the 256 byte control register section are reserved unavailable Reading from an reserved Register File addresses returns an undefined value Writing to reserved Register File addresses is not recom mended and can produce unpredictable results The on chip RAM always begins at address 000H in the Register File address space The Z8F640x family products contain 2KB to 4KB of on chip RAM depending upon the device Reading from Register File addresses outside the available RAM addresses and not within in the control register ad
162. est 0 IRQO 00 48 FC1 IRQO Enable High Bit IRQOENH 00 51 FC2 IRQO Enable Low Bit IRQOENL 00 51 FC3 Interrupt Request 1 IRQI 00 49 FC4 IRQI Enable High Bit IRQIENH 00 52 5 IRQI Enable Low Bit IRQIENL 00 52 FC6 Interrupt Request 2 IRQ2 00 50 FC7 IRQ2 Enable High Bit IRQ2ENH 00 53 FC8 IRQ2 Enable Low Bit IRQ2ENL 00 53 FC9 FCC Reserved XX FCD Interrupt Edge Select IRQES 00 54 XX Undefined 017610 0404 Register File Address Map Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Table 6 Register File Address Map Continued Address Hex Register Description Mnemonic Reset Hex Page FCE Interrupt Port Select IRQPS 00 55 FCF Interrupt Control IRQCTL 00 56 GPIO Port A FDO Port A Address PAADDR 00 37 FDI Port A Control PACTL 00 38 FD2 Port A Input Data PAIN XX 42 FD3 Port A Output Data PAOUT 00 43 GPIO Port B FDA Port B Address PBADDR 00 37 FD5 Port B Control PBCTL 00 38 FD6 Port B Input Data PBIN XX 42 FD7 Port B Output Data PBOUT 00 43 GPIO Port C FD8 Port C Address PCADDR 00 37 FD9 Port C Control PCCTL 00 38 FDA Port C Input Data PCIN XX 42 FDB Port C Output Data PCOUT 00 43 GPIO Port D FDC Port D Address PDADDR 00 37 FDD Port D Control PDCTL 00 38 FDE Port D Input Data PDIN XX 42 FDF Port D Output Data PDOUT 00 43 GPIO Port E FEO Port E Address PEADDR 00 37 FEI Port E Contro
163. ge Current 5 5 HA Vpp 3 6V Vin VDD or VSS ITL Tri State Leakage Current 5 5 HA Vpp 3 6 Cpap GPIO Port Pad Capacitance 8 0 pF Pad Capacitance 8 0 pF Cxour XOUT Pad Capacitance 9 5 pF PS017610 0404 Electrical Characteristics Table 101 DC Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore L ZiLOG 40 C to 105 C Symbol Parameter Minimum Typical Maximum Units Conditions Ipy Weak Pull up Current 30 100 350 HA Vpp 3 0 3 6V Iccs Supply Current in Stop 600 HA Vpp 3 3V Mode This condition excludes all pins that have on chip pull ups when driven Low These values are provided for design guidance only and are not tested in production Figure 91 illustrates the typical current consumption while operating at 25 C 3 3V versus the system clock frequency 39 9 20 0 lt 10 0 0 0 0 5 10 15 20 Frequency MHz Figure 91 Nominal ICC Versus System Clock Frequency 017610 0404 Electrical Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 211 08 Figure 92 illustrates the typical current consumption in Halt mode while operating at 25 3 3V versus the system clock frequency 15 000 10 000 ICC in Halt mode mA 5 000 0 000 0 5 10 15 20 Frequency MHz Figure 92 Nominal Halt
164. gister 118 I2CSTAT register 118 IM 184 immediate data 184 immediate operand prefix 185 INC 187 increment 187 increment word 187 INCW 187 indexed 184 indirect address prefix 185 indirect register 184 indirect register pair 184 indirect working register 184 indirect working register pair 184 infrared encoder decoder IrDA 95 instruction set ez8 CPU 182 instructions ADC 187 ADCX 187 ADD 187 ADDX 187 AND 190 ANDX 190 arithmetic 187 BCLR 188 BIT 188 bit manipulation 188 block transfer 188 BRK 190 BSET 188 BSWAP 188 191 BTJ 190 BTJNZ 190 BTJZ 190 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 CALL 190 188 189 189 190 187 187 187 CPU control 189 CPX 187 DA 187 DEC 187 DECW 187 DI 189 DJNZ 190 EI 189 HALT 189 INC 187 INCW 187 IRET 190 JP 190 LD 189 LDC 189 LDCI 188 189 LDE 189 LDEI 188 LDX 189 LEA 189 load 189 logical 190 MULT 187 NOP 189 OR 190 ORX 190 POP 189 POPX 189 program control 190 PUSH 189 PUSHX 189 RCF 188 189 RET 190 RL 191 RLC 191 rotate and shift 191 RR 191 Preliminary Index RRC 191 SBC 188 SCF 188 189 SRA 191 SRL 191 SRP 189 STOP 189 SUB 188 SUBX 188 SWAP 191 TCM 188 TCMX 188 TM 188 TMX 188 TRAP 190 watch dog timer refresh 189 XOR 190 XORX 190 instructions eZ8 classes of 187 interrupt control register 56 interrupt controller
165. gital Converter 132 OVERVIEW eS Deke Lethe pu aud 132 Architectute we 132 Operation ees aee a e re OCC ECC P EC DP SS 133 Automatic Power Down 133 Single Shot Conversion 133 Continuous 1 134 DMA Control of the ADC 135 ADC Control Register Definitions 135 ADC Control Register 0 0 2 eee 135 ADC Data High Byte Register 137 ADC Data Low Bits Register 137 Flash Memory pe et UEPYV EUR e ER e ee a eine a Us sees 138 OVERVIEW Ere REP RE ea ead 138 Operation eese Cbr E ek ea eens eee eee ein 139 Flash Operation Timing Using the Flash Frequency Registers 141 Flash Code Protection Against External Access 141 Flash Code Protection Against Accidental Program and Erasure 141 Byte Programming 0 cece eee 142 Page sige Ae cae eG stat wee WS eR Sees Tee aie 143 Mass Efase neresi Sema M need Ese mies a cedi me seus Rida 143 Flash Controller Bypass 143 Flash Control Register Definitions 144 Flash Control Register 0 0 eee eee eee eee 144 Flash Status
166. grammed state PS017610 0404 Option Bits 148 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Z 149 Program Memory Address 0000H Table 90 Option Bits At Program Memory Address 0000H BITS 7 6 5 4 3 2 1 0 FIELD WDT RES WDT AO Reserved RP FHSWP FWP RESET U U U U U U U U R W R W R W R W R W R W R W R W R W ADDR Program Memory 0000H Note U Unchanged by Reset R W Read Write WDT_RES Watch Dog Timer Reset 0 Watch Dog Timer time out generates an interrupt request Interrupts must be globally enabled for the eZ8 CPU to acknowledge the interrupt request 1 Watch Dog Timer time out causes a Short Reset This setting is the default for unpro grammed erased Flash AO Watch Dog Timer Always On 0 Watch Dog Timer is automatically enabled upon application of system power Watch Dog Timer can not be disabled 1 Watch Dog Timer is enabled upon execution of the WDT instruction Once enabled the Watch Dog Timer can only be disabled by a Reset or Stop Mode Recovery This set ting is the default for unprogrammed erased Flash Reserved These Option Bits are reserved for future use and must always be set to 1 This setting is the default for unprogrammed erased Flash RP Read Protect 0 User program code is inaccessible Limited control features are available through the On Chip Debugger 1 User program code is accessible All On
167. h Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles ADC dst src dst lt dst src C r r 12 Qo 2 3 r Ir 13 2 4 R R 14 3 3 R IR 15 3 4 R IM 16 3 3 IR IM 17 3 4 ADCX dst src dst lt dst src C ER ER 18 4 3 ER IM 19 4 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 ZiLoG Table 126 eZ8 CPU Instruction Summary Continued Assembly Mode Opcode s me Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles ADD dst src dst dst src r r 02 E o 2 3 r Ir 03 2 4 R R 04 3 3 R IR 05 3 4 R IM 06 3 3 IR IM 07 3 4 ADDX dst src dst lt dst src ER ER 08 ok 4 3 IM 09 4 3 AND dst src dst dst AND src r r 52 0 2 3 r Ir 53 2 4 R R 54 3 3 R IR 55 3 4 R IM 56 3 3 IR IM 57 3 4 dst src dst dst AND src ER ER 58 Q a a 4 3 ER IM 59 4 3 BCLR bit dst dst bit lt 0 r E2 Qo 2 2 BIT p bit dst dst bit lt p r E2 Q 2 2 BRK Debugger Break 00 BEEN 1 1 BSET bit dst dst bit lt 1 r E2 Q e 2 2 BSWAP dst dst 7 0 lt dst 0 7 R D5 X QO 2 2 BTJ p bit src dst if src bi
168. he slave needs to service an interrupt it pulls the SCL signal Low which halts PC operation 4 If there is no other data in the Data register or the STOP bit in the Control register is set by software then the Stop signal is sent Figure 79 illustrates the data transfer format for a 7 bit addressed slave Shaded regions indicate data transferred from the 12 Controller to slaves and unshaded regions indicate data transferred from the slaves to the Controller Figure 79 7 Bit Addressed Slave Data Transfer Format The data transfer format for a transmit operation on a 7 bit addressed slave is as follows 1 Software asserts the bit in the Control register 2 Software asserts the TXI bit of the Control register to enable Transmit interrupts 3 The IC interrupt asserts because the Data register is empty 4 Software responds to the TDRE bit by writing a 7 bit slave address followed by a 0 write to the Data register bd Software asserts the START bit of the Control register 6 The C Controller sends the START condition to the I7C slave 7 The PC Controller loads the C Shift register with the contents of the Data register 8 After one bit of address has been shifted out by the SDA signal the Transmit interrupt is asserted 9 Software responds by writing the contents of the data into the PC Data register 10 The PC Controller shifts the rest of the address and write bit
169. i ZiLOG Interrupt Port Select register selects between Port A and Port D for the individual inter rupts Table 35 Interrupt Edge Select Register IRQES BITS 7 6 5 4 3 2 1 0 FIELD IES7 IES6 IESS IES4 IES3 IES2 IES1 IESO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FCDH IESx Interrupt Edge Select x where x indicates the specific GPIO Port pin number 0 through 7 The pulse width should be greater than 1 system clock to guarantee capture of the edge triggered interrupt 0 An interrupt request is generated on the falling edge of the PAx PDx input 1 An interrupt request is generated on the rising edge of the PAx PDx input Interrupt Port Select Register The Port Select IRQPS register Table 36 determines the port pin that generates the PAx PDx interrupts This register allows either Port A or Port D pins to be used as inter rupts The Interrupt Edge Select register controls the active interrupt edge Table 36 Interrupt Port Select Register IRQPS BITS 7 6 5 4 3 D 1 0 FIELD PAD7S PAD6S PADSS PAD4S PAD3S PAD2S PADIS PADOS RESET 0 0 0 0 0 0 0 0 R w R W R W R W R W R W R W R W R W ADDR FCEH 017610 0404 PADxS PAx PDx Selection 0 PAx is used for the interrupt for PAx PDx interrupt request 1 PDx is used for the interrupt for PAx PDx interrupt request where x indicates the specific GPIO Por
170. ignal SDA and a serial clock signal SCL Features of the PC Controller include Transmit and Receive Operation in Master mode Maximum data rate of 400kbit sec 7 and 10 bit Addressing Modes for Slaves Unrestricted Number of Data Bytes Transmitted per Transfer The Controller in the Z8F640x family device does not operate in Slave mode Operation The Controller operates in Master mode to transmit and receive data Only a single master is supported Arbitration between two masters must be accomplished in software supports the following operations Master transmits to a 7 bit slave Master transmits to a 10 bit slave Master receives from a 7 bit slave Master receives from a 10 bit slave SDA and SCL Signals sends all addresses data and acknowledge signals over the SDA line most significant bit first SCL is the common clock for the Controller When the SDA and SCL pin alternate functions are selected for their respective GPIO ports the pins are automatically configured for open drain operation The master is responsible for driving the SCL clock signal although the clock signal can become skewed by a slow slave device During the high period of the clock the slave pulls the SCL signal Low to suspend the transaction When the slave has released the line the PC Controller continues the transaction data is transferred in bytes and there is no 017609 0803 12C Controller Z8F640x Z8F48
171. ily device opera tion The feature configuration data is stored in the Program Memory and read during Reset The features available for control via the Option Bits are Operation Watch Dog Timer time out response selection interrupt or Short Reset Watch Dog Timer enabled at Reset The ability to prevent unwanted read access to user code in Program Memory The ability to prevent accidental programming and erasure of all or a portion of the user code in Program Memory Option Bit Configuration By Reset Each time the Option Bits are programmed or erased the Z8F640x family device must be Reset for the change to take place During any reset operation System Reset Short Reset or Stop Mode Recovery the Option Bits are automatically read from the Program Mem ory and written to Option Configuration registers The Option Configuration registers con trol operation of the Z8F640x family device Option Bit control of the Z8F640x family device is established before the device exits Reset and the eZ8 CPU begins code execu tion The Option Configuration registers are not part of the Register File and are not acces sible for read or write access Option Bit Address Space The first two bytes of Program Memory at addresses 0000H and 0001H are reserved for the user Option Bits The byte at Program Memory address 0000H is used to configure user options The byte at Program Memory address 0001H is reserved for future use and must be left in its unpro
172. imum rating conditions for extended periods may affect device reliability For improved reliability unused inputs must be tied to one of the supply voltages Vpp or Vss Table 100 Absolute Maximum Ratings Parameter Minimum Maximum Units Notes Ambient temperature under bias 40 105 Storage temperature 65 150 Voltage on any pin with respect to 0 3 5 5 1 Voltage on pin with respect to Vss 0 3 3 6 V Maximum current on input and or inactive output pin 5 5 uA Maximum output current from active output pin 25 25 mA 80 Pin QFP Maximum Ratings at 40 C to 70 C Total power dissipation 550 mW Maximum current into Vpp or out of Vas 150 mA 80 Pin QFP Maximum Ratings at 70 C to 105 Total power dissipation 200 mW Maximum current into or out of Vss 56 mA 68 Pin PLCC Maximum Ratings at 40 to 70 Total power dissipation 1000 mW Maximum current into Vpp or out of Vas 275 mA Notes 1 This voltage applies to all pins except the following AVpp pins supporting analog input Port and Port H RESET and where noted otherwise 017610 0404 Electrical Characteristics 167 Table 100 Absolute Maximum Ratings Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Parameter Minimum Maximum Units Notes 68 Pin PLCC Maximum
173. in Configurations celere eee Seas PIA Seed ee 7 Signal Descriptions eee eee 13 Pin Characteristics ene ecb ehh ee he 15 Address cues So 4 08 anaes EORR ee a TOUS 17 OVELVIEW err EpL PP IPC end Sea head 17 Resister File MR 17 Program e br 18 Data Memory ez ih RES DERE UE ERR RESP MER ES 19 Register File Address Map 0 Reset and Stop Mode Recovery 25 OVE EW 25 Reset Types iacet e bed eR ERE ROLES RE E 25 System and Short 26 Reset SOUFCceS s cope e p SR Gd Seaweed eee eas 26 Power On Reset eese niece sled ERR 27 Voltage Brown Out 27 Watch Dog Timer Reset 28 PS017610 0404 Table of Contents Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 211 08 External Pin Reset eee 20 Stop Mode Recovery 29 Stop Mode Recovery Using Watch Dog Timer Time Out 29 Stop Mode Recovery Using a GPIO Port Pin Transition 30 Low Power Modes 3 OVERVIEW eite Gone Leeda 31 Stop MOJE EQ sad 31 Halt Mode ERE CAD Fani EE 31 Ge
174. in the following table PS Product Specification 0176 Unique Document Number 01 Revision Number 0702 Month and Year Published Document Information Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z z ZiLOG Customer Feedback Form The Z8 Encore Product Specification If you experience any problems while operating this product or if you note any inaccuracies while reading this Product Specification please copy and complete this form then mail or fax it to ZILOG see Return Information below We also welcome your suggestions Customer Information Name Country Company Phone Address Fax City State Zip E Mail Product Information Part Serial Board Fab st or Rev Software Version Document Number Host Computer Description Type Return Information ZiLOG 532 Race Street San Jose CA 95126 Fax 408 558 8536 Email tools zilog com PS017610 0404 Customer Feedback Form Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Problem Description or Suggestion Provide a complete description of the problem or your suggestion If you are reporting a specific problem include all steps leading up to the occurrence of the problem Attach additional pages as necessary PS017610 0404 Customer Feedback Form Index Symbols 185 185 185 Numerics 10 bit ADC 4 40 lead plastic dual in
175. ing occurs 7 The UART notifies DMA Controller that a data byte is available in the UART Receive Data register 8 The DMA Controller requests control of the system bus from the eZ8 CPU 9 The eZ8 CPU acknowledges the bus request 10 The DMA Controller transfers the data from the UART Receive Data register to another location in RAM and then return bus control back to the eZ8 CPU The UART and DMA can continue to transfer incoming data bytes without eZ8 CPU intervention When a UART error is detected the UART Receiver interrupt is generated The associated interrupt service routine ISR should perform the following 11 Check the UART Status 0 register to determine the source of the UART error or break condition and then respond appropriately Multiprocessor 9 bit mode The UART has a Multiprocessor mode that uses an extra 9th bit for selective communi cation when a number of processors share a common UART bus In Multiprocessor 9 bit mode also referred to as 9 Bit mode the multiprocessor bit MP is transmitted immedi ately following the 8 bits of data and immediately preceding the STOP bit s as illustrated in Figure 70 The character format is p Data Field STOP Bit s Idle State m of Line 1 ul me Bito y Bit Bit2 Bit3 Bit4 Bit5 Bit6 ys Bit7 2 MP J 0 eme s e 2 Figure 70 UART Asynchronous Multiprocessor 9 bit Mode Data Format In Multiprocessor 9 bit mode
176. ion To prevent spurious signals during IrDA data transmission set the IREN bit in the UARTx Control 1 register to 1 to enable the Infrared Encoder Decoder before enabling the GPIO Port alternate function for the corre sponding pin PS017610 0404 Infrared Encoder Decoder Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 99 ZiLOG Serial Peripheral Interface Overview The Serial Peripheral Interface SPI is a synchronous interface allowing several SPI type devices to be interconnected SPI compatible devices include EEPROMs Analog to Digital Converters and ISDN devices Features of the SPI include e Full duplex synchronous character oriented communication Four wire interface Data transfers rates up to a maximum of one fourth the system clock frequency Hrror detection e Write and mode collision detection e Dedicated Baud Rate Generator Architecture The SPI may be configured as either a Master in single or multi master systems or a Slave as illustrated in Figures 74 through 76 SPI Master To Slave s SS Pin _1 55 MISO 8 bit Shift Register From Slave Bit 7 A Bit 0 To Slave SCK Baud Rate ee d Figure 74 SPI Configured as a Master in a Single Master Single Slave System PS017610 0404 Serial Peripheral Interface Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG
177. ion Summary Continued Assembly Opcode s ue Fetch Instr Mnemonic Symbolic Operation dst src Hex Z S V D H Cycles Cycles LD dst rc dst src r IM 0 2 2 r X r C7 3 3 X r r D7 3 4 r Ir E3 2 3 R R E4 3 2 R IR E5 3 3 R IM E6 3 3 IR IM E7 3 3 Ir r F3 2 3 IR R F5 3 3 LDC dst src dst src r Irr C2 EE LLL 2 5 Ir Irr C5 2 9 Irr r D2 2 5 LDCI dst src dst lt src Ir Irr C3 2 9 1 Irr Ir D3 2 9 LDE dst src dst lt src r Irr 82 E LLL 2 5 r 92 2 5 LDEI dst src dst src Ir Irr 83 EM LLLI 2 9 1 Irr Ir 93 2 9 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 196 ZiLoG Table 126 eZ8 CPU Instruction Summary Continued Assembly Opcode s ue Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles LDX dst src dst src r ER 84 EE LLLI 3 2 Ir ER 85 3 3 R IRR 86 3 4 IR IRR 87 3 5 r X rr 88 3 4 X rr r 89 3 4 ER r 94 3 2 ER Ir 95 3 3 IRR R 96 3 4 IRR IR 97 3 5 ER ER E8 4 2 ER IM E9 4 2 LEA dst X src dst lt src X r X r 98 3 3 IT X rr 99 3 5 MULT dst dst 15 0 lt RR F4 MM I SL 2 8 dst 15 8 dst 7 0 NOP No operation OF DLE ZZ SC 1 2 OR dst src dst dst OR src r r 42
178. ion or rotate and shift operation The Flags Register contains six bits of status information that are set or cleared by CPU operations Four of the bits C V Z and S can be tested for use with conditional jump instructions Two flags H and D can not be tested and are used for Binary Coded Decimal BCD arithmetic The two remaining bits User Flags F1 and F2 are available as general purpose status bits User Flags are unaffected by arithmetic operations and must be set or cleared by instructions The User Flags cannot be used with conditional Jumps They are undefined at initial power up and are unaffected by Reset Figure 99 illustrates the flags and their bit positions in the Flags Register Bit Bit 7 0 IC Z S V D H F2 Ft Flags Register E User Flags Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag U Undefined Figure 99 Flags Register Interrupts the Software Trap TRAP instruction and Illegal Instruction Traps all write the value of the Flags Register to the stack Executing an Interrupt Return IRET instruc tion restores the value saved on the stack into the Flags Register PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 202 ZiLOG Opcode Maps Figures 101 and 102 provide information on each of the eZ8 CPU instructions A descrip tion of the opcode map data and the abbreviations are provided in Figure 100 and
179. irst bit has been shifted out a Transmit interrupt is asserted Software responds by writing eight bits of address to the PC Data register The Controller completes shifting of the two address bits and a 0 write The PC slave sends an acknowledge by pulling the SDA signal Low during the next high period of SCL The PC Controller loads the Shift register with the contents of the PC Data register The C Controller shifts out the next eight bits of address After the first bits are shifted the Controller generates a Transmit interrupt Software responds by setting the START bit of the PC Control register to generate a repeated START Software responds by writing 11110B followed by the 2 bit slave address and a 1 read Software responds by setting the NAK bit of the PC Control register so that a Not Acknowledge is sent after the first byte of data has been read If you want to read only one byte software responds by setting the NAK bit of the PC Control register After the PC Controller shifts out the address bits mentioned in step 9 the slave sends an acknowledge by pulling the SDA signal Low during the next high period of SCL The Controller sends the repeated START condition The Controller loads the Shift register with the contents of the PC Data register The Controller sends 111108 followed by the 2 bit slave read and a 1 read The PC slave sends an acknowledge by pulling th
180. is bit can only be cleared by resetting the Z8F640x family device it cannot be written to 0 0 The Z8F640x family device is operating in normal mode 1 The Z8F640x family device is in Debug mode PS017610 0404 On Chip Debugger Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 BRKEN Breakpoint Enable This bit controls the behavior of the BRK instruction opcode 00H By default Break points are disabled and the BRK instruction behaves like a If this bit is set to 1 when a BRK instruction is decoded the DBGMODE bit of the OCDCTL register is automatically set to one 0 Breakpoints are disabled 1 Breakpoints are enabled DBGACK Debug Acknowledge This bit enables the debug acknowledge feature If this bit is set to 1 then the OCD sends an Debug Acknowledge character FFH to the host when a Breakpoint or Watchpoint occurs 0 Debug Acknowledge is disabled 1 Debug Acknowledge is enabled Reserved These bits are reserved and must be 0 RST Reset Setting this bit to 1 resets the Z8F640x family device The device goes through a normal Power On Reset sequence with the exception that the On Chip Debugger is not reset This bit is automatically cleared to 0 when the reset finishes 0 No effect 1 Reset Z8F640x family device OCD Status Register The OCD Status register reports status information about the current state of the debugger and the Z8F640x family device Table 95
181. isabled Caution The input frequency of the Timer Input signal must not exceed one fourth the system clock frequency Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low at timer Reload The steps for configuring a timer for Counter mode and initiating the count are as follows 1 Write to the Timer Control register to Disable the timer Configure the timer for Counter mode PS017610 0404 Timers Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Select either the rising edge or falling edge of the Timer Input signal for the count This also sets the initial logic level High or Low for the Timer Output alternate function However the Timer Output function does not have to be enabled 2 Write to the Timer High and Low Byte registers to set the starting count value This only affects the first pass in Counter mode After the first timer Reload in Counter mode counting always begins at the reset value of 0001H Generally in Counter mode the Timer High and Low Byte registers must be written with the value 0001H Write to the Timer Reload High and Low Byte registers to set the Reload value 4 If desired
182. l PECTL 00 38 FE2 Port E Input Data PEIN XX 42 FE3 Port E Output Data PEOUT 00 43 GPIO Port F 4 Port Address PFADDR 00 37 FES Port F Control PFCTL 00 38 FE6 Port F Input Data PFIN XX 42 FE7 Port F Output Data PFOUT 00 43 GPIO Port G FE8 Port G Address PGADDR 00 37 FE9 Port G Control PGCTL 00 38 FEA Port G Input Data PGIN XX 42 FEB Port G Output Data PGOUT 00 43 GPIO Port H FEC Port H Address PHADDR 00 37 XX Undefined 017610 0404 Register File Address Map Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z6 21108 Table 6 Register File Address Map Continued Address Hex Register Description Mnemonic Reset Hex Page FED Port H Control PHCTL 00 38 FEE Port H Input Data PHIN XX 42 FEF Port H Output Data PHOUT 00 43 Watch Dog Timer WDT FFO Watch Dog Timer Control WDTCTL XXX00000b 75 Watch Dog Timer Reload Upper Byte WDTU FF 76 FF2 Watch Dog Timer Reload High Byte WDTH FF 76 FF3 Watch Dog Timer Reload Low Byte WDTL FF 76 FF4 FF7 Reserved XX Flash Memory Controller FF8 Flash Control FCTL 00 144 FF8 Flash Status FSTAT 00 145 FF9 Flash Page Select FPS 00 146 FFA Flash Programming Frequency High Byte FFREQH 00 147 FFB Flash Programming Frequency Low Byte FFREQL 00 147 eZ8 CPU FFC Flags XX Refer to the eZ8 FFD Register Pointer RP XX CPU User FFE Stack Pointer High Byte SPH XX Manual FFF Stack Pointer Low Byte SP
183. lash memory Programming and Page Erase are disabled for the other portions of the Flash Program Memory Mass erase through user code is disabled Mass Erase is available through the On Chip Debugger Oorl 1 Programming Page Erase and Mass Erase are enabled for all of Flash Program Memory Flash Code Protection Using the Flash Controller At Reset the Flash Controller locks to prevent accidental program or erasure of the Flash memory To program or erase the Flash memory unlock the Flash Controller by making two consecutive writes to the Flash Control register with the values 73H and 8CH sequen tially After unlocking the Flash Controller the Flash can be programmed or erased When the Flash Controller is unlocked any value written to the Flash Control register locks the Flash Controller Writing the Mass Erase or Page Erase commands executes the function before locking the Flash Controller Byte Programming When the Flash Controller is unlocked all writes to Program Memory program a byte into the Flash An erased Flash byte contains all 1 s FFH The programming operation can only be used to change bits from 1 to 0 To change a Flash bit or multiple bits from 0 to 1 requires execution of either the Page Erase or Mass Erase commands Byte Programming can be accomplished using the On Chip Debugger s Write Memory command or eZ8 CPU execution of the LDC or LDCI instructions Refer to the eZ8 CPU User Manual for a description of
184. line package 206 44 lead low profile quad flat package 207 44 lead plastic lead chip carrier package 207 64 lead low profile quad flat package 208 68 lead plastic lead chip carrier package 209 80 lead quad flat package 210 A absolute maximum ratings 167 AC characteristics 172 ADC 187 architecture 132 automatic power down 133 block diagram 133 continuous conversion 134 control register 135 control register definitions 135 data high byte register 137 data low bits register 137 DMA control 135 electrical characteristics and timing 174 operation 133 single shot conversion 133 ADCCTL register 135 ADCDH register 137 ADCDL register 137 ADCX 187 ADD 187 add extended addressing 187 add with carry 187 add with carry extended addressing 187 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z6 ZiLOG additional symbols 185 address space 17 ADDX 187 analog signals 14 analog to digital converter ADC 132 AND 190 ANDX 190 arithmetic instructions 187 assembly language programming 182 assembly language syntax 183 B B 185 b 184 baud rate generator UART 85 BCLR 188 binary number suffix 185 BIT 188 bit 184 clear 188 manipulation instructions 188 set 188 set or clear 188 swap 188 test and jump 190 test and jump if non zero 190 test and jump if zero 190 bit jump and test if non zero 190 bit swap 191 block diagram 3 block transfer instructions 188 BRK 190 BSET 188 BSWAP 188
185. lity is not employed UART Baud Rate Generator The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans mission The input to the Baud Rate Generator is the system clock The UARTx Baud Rate High and Low Byte registers combine to create a 16 bit baud rate divisor value BRG 15 0 that sets the data transmission rate baud rate of the UART The UART data rate is calculated using the following equation System Clock Frequency Hz ART Data Rate bits s 2251620 Clock Frequency Hz ata Rate UART Baud Rate Divisor Valie When the UART is disabled the Baud Rate Generator can function as a basic 16 bit timer with interrupt on time out To configure the Baud Rate Generator as a timer with interrupt on time out complete the following procedure 1 Disable the UART by clearing the REN and TEN bits in the UART Control 0 register to 0 2 Load the desired 16 bit count value into the UART Baud Rate High and Low Byte registers 017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 3 Enable the Baud Rate Generator timer function and associated interrupt by setting the BIRQ bit in the UARTx Control 1 register to 1 UART Control Register Definitions The UART control registers support both the UARTS and the associated Infrared Encoder Decoders For more information on the infrared operation refer to the Infrared Encoder Decoder chapter on page 95 UA
186. llator frequency Hex Decimal Typical Description 000004 4 80us Minimum time out delay FFFFFF 16 777 215 335 5s Maximum time out delay Watch Dog Timer Refresh When first enabled the Watch Dog Timer is loaded with the value in the Watch Dog Timer Reload registers The Watch Dog Timer then counts down to 000000H unless a WDT instruction is executed by the eZ8 CPU Execution of the WDT instruction causes the downcounter to be reloaded with the WDT Reload value stored in the Watch Dog Timer Reload registers Counting resumes following the reload operation V When the Z8F640x family device is operating in Debug Mode via the On Chip Debug ger the Watch Dog Timer is continuously refreshed to prevent spurious Watch Dog Timer time outs Watch Dog Timer Time Out Response The Watch Dog Timer times out when the counter reaches 000000H A time out of the Watch Dog Timer generates either an interrupt or a Short Reset The WDT RES Option Bit determines the time out response of the Watch Dog Timer Refer to the Option Bits chap ter for information regarding programming of the WDT RES Option Bit WDT Interrupt in Normal Operation If configured to generate an interrupt when a time out occurs the Watch Dog Timer issues an interrupt request to the interrupt controller and sets the WDT status bit in the Watch Dog Timer Control register If interrupts are enabled the eZ8 CPU responds to the interrupt request by fetching the Watch Dog Timer interrup
187. llowing Reset The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter Program execution begins at the Reset vector address Reset Sources Table 8 lists the reset sources and type of Reset as a function of the Z8F640x family device operating mode The text following provides more detailed information on the indi vidual Reset sources Please note that Power On Reset Voltage Brown Out events always have priority over all other possible reset sources to insure a full system reset occurs Table 8 Reset Sources and Resulting Reset Type Operating Mode Reset Source Reset Type Normal or Halt modes Power On Reset Voltage Brown Out System Reset Watch Dog Timer time out Short Reset when configured for Reset RESET pin assertion Short Reset On Chip Debugger initiated Reset System Reset except the On Chip Debugger is OCDCTL 1 set to 1 unaffected by the reset Stop mode Power On Reset Voltage Brown Out System Reset RESET pin assertion System Reset DBG pin driven Low System Reset PS017610 0404 Reset and Stop Mode Recovery Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore ZI ZiLOG Power On Reset The Z8F640x family products contain an internal Power On Reset POR circuit The POR circuit monitors the supply voltage and holds the device in the Reset state until the supply voltage reaches a safe operating level After the supply v
188. llustrates the data transfer format for a receive operation on a 7 bit addressed slave The shaded regions indicate data transferred from the Controller to slaves and unshaded regions indicate data transferred from the slaves to the PC Controller Slave Address 1 Data A Data A P Figure 81 Receive Data Transfer Format for a 7 Bit Addressed Slave The data transfer format for a receive operation on a 7 bit addressed slave is as follows 017609 0803 12C Controller 9 10 11 Reading Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Software writes the Data register with a 7 bit slave address followed by a 1 read Software asserts the START bit of the C Control register Software asserts the bit of the Control register so that after the first byte of data has been read by the PC Controller a Not Acknowledge is sent to the PC slave The Controller sends the START condition The C Controller sends the address and read bit by the SDA signal The slave sends an Acknowledge by pulling the SDA signal Low during the next high period of SCL The Controller reads the first byte of data from the slave The PC Controller asserts the Receive interrupt Software responds by reading the PC Data register The PC Controller sends a to the slave ANAK interrupt is generated by the PC Controller 12 13 Sof
189. mmands become available unless the user code and control registers are protected by programming the Read Protect Option Bit RP The Read Protect Option Bit prevents the code in memory from being read out of the Z8F640x family device When this option is enabled several of the OCD commandis are disabled Table 93 contains a summary of the On Chip Debugger com mands Each OCD command is described in further detail in the bulleted list following Table 93 Table 93 indicates those commands that operate when the Z8F640x family device is not in Debug mode normal operation and those commands that are disabled by programming the Read Protect Option Bit Table 93 On Chip Debugger Commands Enabled when NOT Disabled by Debug Command Command Byte in Debug mode Read Protect Option Bit Read OCD Revision 00H Yes Reserved 01H Read OCD Status Register 02H Yes Read Runtime Counter 03H Write OCD Control Register 04H Yes Cannot clear DBGMODE bit Read OCD Control Register 05H Yes Write Program Counter 06H Disabled Read Program Counter 07H Disabled Write Register 08H Only writes of the Flash Memory Control registers are allowed Additionally only the Mass Erase command is allowed to be written to the Flash Control register Read Register 09H Disabled 017610 0404 On Chip Debugger Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 157 ZiLOG Table 93
190. n is asserted the device progresses through the Short Reset sequence While the RESET input pin is asserted Low the Z8F640x family device continues to be held in the Reset state If the RESET pin is held Low beyond the Short Reset time out the device exits the Reset state immediately following RESET pin deassertion Following a Short Reset initi ated by the external RESET pin the EXT status bit in the Watch Dog Timer Control WDTCTL register is set to 1 Stop Mode Recovery Stop mode is entered by execution of a STOP instruction by the eZ8 CPU Refer to the Low Power Modes chapter for detailed Stop mode information During Stop Mode Recovery the Z8F640x family device is held in reset for 514 cycles of the Watch Dog Timer oscillator followed by 16 cycles of the system clock crystal oscillator Stop Mode Recovery does not affect any values in the Register File including the Stack Pointer Reg ister Pointer Flags and general purpose RAM The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002H and 0003H and loads that value into the Program Counter Program execution begins at the Reset vec tor address Following Stop Mode Recovery the STOP bit in the Watch Dog Timer Con trol Register is set to 1 Table 9 lists the Stop Mode Recovery sources and resulting actions The text following provides more detailed information on each of the Stop Mode Recovery sources Table 9 Stop Mode Recovery Sources and Resulting Action
191. n value is placed in the counter High or Low Byte at the next clock edge The counter continues counting from the new value BITS 7 6 5 4 3 0 FIELD RESET 0 0 0 0 0 0 R W R W R W R W R W R W R W ADDR FOOH F08H F10H F18H Table 39 gt Timer 0 3 Low Byte Register TxL BITS 7 6 5 4 3 0 FIELD RESET 0 0 0 0 0 1 R W R W R W R W R W R W R W ADDR F01H F09H F11H F19H TH and TL Timer High and Low Bytes These 2 bytes TMRH 7 0 TMRL 7 0 contain the current 16 bit timer count value Timer Reload High and Low Byte Registers The Timer 0 3 Reload High and Low Byte TxRH and TxRL registers Tables 40 and 41 store a 16 bit reload value TRH 7 0 TRL 7 0 Values written to the Timer Reload High Byte register are stored in a temporary holding register When a write to the Timer Reload Low Byte register occurs the temporary holding register value is written to the Timer High Byte register This operation allows simultaneous updates of the 16 bit Timer Reload value In Compare mode the Timer Reload High and Low Byte registers store the 16 bit Com pare value In single byte DMA transactions to the Timer Reload High Byte register the temporary holding register is bypassed and the value is written directly to the register If the DMA is 017610 0404 Timers Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 se
192. nctions by configuring the associated GPIO Port pins for alternate function operation Write to the UART Control 1 register to enable Multiprocessor 9 bit mode functions if desired Write to the UART Control 0 register to Set the receive enable bit REN to enable the UART for data reception Enable parity if desired and select either even or odd parity Check the RDA bit in the UART Status 0 register to determine if the Receive Data register contains a valid data byte indicated by a 1 If RDA is set to 1 to indicate available data continue to Step 6 If the Receive Data register is empty indicated by a 0 continue to monitor the RDA bit awaiting reception of the valid data Read data from the UART Receive Data register If operating in Multiprocessor 9 bit mode first read the Multiprocessor Receive flag MPRX to determine if the data was directed to this UART before reading the data Return to Step 6 to receive additional data Receiving Data using the Interrupt Driven Method The UART Receiver interrupt indicates the availability of new data as well as error con ditions Follow these steps to configure the UART receiver for interrupt driven operation l 017610 0404 Write to the UART Baud Rate High and Low Byte registers to set the desired baud rate Enable the UART pin functions by configuring the associated GPIO Port pins for alternate function operation Execute a DI instruction to disable inter
193. nd initiate counting The PWM period is given by the following equation PWM Period s Reload Value x Prescale System Clock Frequency Hz If an initial starting value other than 0001H is loaded into the Timer High and Low Byte registers the One Shot mode equation must be used to determine the first PWM time out period If TPOL is set to 0 the ratio of the PWM output High time to the total period is given by Reload Value PWM Value PWM Output High Time Ratio Reload Value 100 If TPOL is set to 1 the ratio of the PWM output High time to the total period is given by 3 PWM Value PWM Output High Time Ratio Reload Value x 100 Capture Mode In Capture mode the current timer count value is recorded when the desired external Timer Input transition occurs The Capture count value is written to the Timer PWM High and Low Byte Registers The timer input is the system clock The TPOL bit in the Timer Control register determines if the Capture occurs on a rising edge or a falling edge of the PS017610 0404 Timers Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Timer Input signal When the Capture event occurs an interrupt is generated and the timer continues counting The timer continues counting up to the 16 bit Reload value stored in the Timer Reload High and Low Byte registers Upon reaching the Reload value the timer generates an interrupt and continues counting The steps for co
194. neral Purpose n nnn 33 OVERVIEW dee M ec M E Ee eda 33 GPIO Port Availability By Device 33 ZArchitecttte ue etur serate hope seen esas eere daas ade arn 34 GPIO Alternate Functions 34 GPIO Interr pts i Eee dece RR es 36 GPIO Control Register Definitions 36 Port A H Address Registers 37 Port A H Control 38 Port A H Input Data Registers 42 Port A H Output Data 43 Interrupt Controller eee n nnn 44 oa 44 Interrupt Vector Listing 44 Powers d MP Em 46 Operation LEE TIPO II I e px ogee Eas san 46 Master Interrupt Enable 46 Interrupt Vectors and Priority 47 Interrupt Assertion Types 47 Interrupt Control Register 48 Interrupt Request 0 Register 48 Interrupt Request 1 Register 49 Interrupt Request 2 Register 50 IRQO Enable High and Low Bit Registers 51 IRQI Enable High and Low Bit Registers 52 IRQ2 Enable High
195. nfiguring a timer for Capture mode and initiating the count are as follows 1 Write to the Timer Control register to Disable the timer Configure the timer for Capture mode Set the prescale value Set the Capture edge rising or falling for the Timer Input 2 Write to the Timer High and Low Byte registers to set the starting count value typically 0001H Write to the Timer Reload High and Low Byte registers to set the Reload value 4 Clear the Timer PWM High and Low Byte registers to 0000H This allows user software to determine if interrupts were generated by either a capture event or a reload If the PWM High and Low Byte registers still contain 0000H after the interrupt then the interrupt was generated by a Reload 5 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 6 Configure the associated GPIO port pin for the Timer Input alternate function 7 Write to the Timer Control register to enable the timer and initiate counting In Capture mode the elapsed time from timer start to Capture event can be calculated using the following equation Capture Elapsed Time s Capture Value Start Value x Prescale System Clock Frequency Hz Compare Mode In Compare mode the timer counts up to the 16 bit maximum Compare value stored in the Timer Reload High and Low Byte registers The timer input is the system clock Upon reaching the Compa
196. nput TOOUT Timer 0 Output PA2 N A No alternate function PA3 CTSO UART 0 Clear to Send PA4 RXDO IRRXO UART 0 IrDA 0 Receive Data PAS TXDO IRTXO UART 0 IrDA 0 Transmit Data PA6 SCL PC Clock automatically open drain 7 SDA PC Data automatically open drain PortB PBO ANAO ADC Analog Input 0 1 1 ADC Analog Input 1 PB2 ANA2 ADC Analog Input 2 PB3 ANA3 ADC Analog Input 3 PB4 ANA4 ADC Analog Input 4 PB5 ANAS ADC Analog Input 5 PB6 ANAG ADC Analog Input 6 PB7 Analog Input 7 Port C PCO Timer 1 Input PCI TIOUT Timer 1 Output PC2 SS SPI Slave Select PC3 SCK SPI Serial Clock PC4 MOSI SPI Master Out Slave In PCS MISO SPI Master In Slave Out PC6 T2IN Timer 2 In PC7 T20UT Timer 2 Out not available in 40 pin packages General Purpose I O Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Table 11 Port Alternate Function Mapping Continued Port Pin Mnemonic Alternate Function Description PortD PDO T3IN Timer 3 In not available in 40 and 44 pin packages PDI T3OUT Timer 3 Out not available in 40 and 44 pin packages PD2 N A No alternate function PD3 N A No alternate function PD4 RXD1 IRRX1 UART 1 1 Receive Data PDS TXD1 IRTX1 UART1 IrDA 1 Transmit Data PD6 CTSI UART 1 Clear to Send PD7 RCOUT Watch Dog Timer RC Oscillator Output Port E
197. ns directly and as a result alternate func tions are also affected Table 17 Port A H Output Control Sub Registers BITS 7 6 5 4 3 2 1 0 FIELD POC7 POC6 5 4 2 1 POCO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR If 03H in Port A H Address Register accessible via Port A H Control Register POC 7 0 Port Output Control These bits function independently of the alternate function bit and disables the drains if set to 1 0 The drains are enabled for any output mode 1 The drain of the associated pin is disabled open drain mode PS017610 0404 General Purpose I O Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 2 211 08 Port A H High Drive Enable Sub Registers The Port A H High Drive Enable sub register Table 18 is accessed through the Port A H Control register by writing 04H to the Port A H Address register Setting the bits in the Port A H High Drive Enable sub registers to 1 configures the specified port pins for high current output drive operation The Port A H High Drive Enable sub register affects the pins directly and as a result alternate functions are also affected Table 18 Port A H High Drive Enable Sub Registers BITS 7 6 5 4 3 2 1 0 FIELD PHDE7 PHDE6 PHDES PHDE4 PHDE3 PHDE2 PHDEI PHDEO RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR If
198. o Single Address Before 2 Next Erase Flash Row Program Time 8 ms Cumulative program time for single row cannot exceed limit before next erase This parameter is only an issue when bypassing the Flash Controller Data Retention 100 years 25 C Endurance 10 000 cycles Program erase cycles Table 105 Watch Dog Timer Electrical Characteristics and Timing Vpp 3 0 3 6V 40 C to 105 C Symbol Parameter Minimum Typical Maximum Units Conditions Fwpr WDT Oscillator Frequency 25 50 100 kHz Table 106 Analog to Digital Converter Electrical Characteristics and Timing Vpp 3 0 3 6V 40 C to 105 C Symbol Parameter Minimum Typical Maximum Units Conditions Resolution 10 bits External 3 0V Rg lt 3 0 Differential Nonlinearity 1 0 1 0 LSB External 3 0V DNL Rg lt 3 0kQ Integral Nonlinearity INL 3 0 3 0 LSB External Vggr 3 0V Rg lt 3 0kQ DC Offset Error 35 25 mV 80 pin QFP and 64 pin LQFP packages Analog source impedance affects ADC offset voltage because of pin leakage and input settling time PS017610 0404 Electrical Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Table 106 Analog to Digital Converter Electrical Characteristics
199. o the serial port of a host PC using minimal external hardware Two different methods for connecting pin to an RS 232 interface are depicted in Figures 87 and 88 Caution For operation of the On Chip Debugger all power pins VDD and AVDD must be supplied with power and ground pins VSS and AVSS must be properly grounded The DBG pin is open drain and must always be connected to Vpp through an external pull up resistor to ensure proper operation RS 232 TX RS 232 Transceiver VDD Diode 10K Ohm DBG Pin RS 232 RX ES Figure 87 Interfacing the On Chip Debugger s DBG Pin with an RS 232 Interface 1 017610 0404 On Chip Debugger Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG VDD RS 232 Transceiver Open Drain 10K Ohm Buffer DBG Pin RS 232 TX RS 232 RX Figure 88 Interfacing the On Chip Debugger s Pin with an RS 232 Interface 2 Debug Mode The operating characteristics of the Z8F640x family devices in Debug mode are The eZ8 CPU fetch unit stops idling the eZ8 CPU unless directed by OCD to execute specific instructions The system clock operates unless in Stop mode e All enabled on chip peripherals operate unless in Stop mode e Automatically exits Halt mode e Constantly refreshes the Watch Dog Timer if enabled Entering Debug Mode The Z8F640x family device enters Debug m
200. oad registers is loaded into the counter when the Watch Dog Timer is first enabled and every time a WDT instruction is executed PS017610 0404 Watch Dog Timer Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG Watch Dog Timer Control Register Definitions Watch Dog Timer Control Register The Watch Dog Timer Control WDTCTL register detailed in Table 46 is a Read Only register that indicates the source of the most recent Reset event indicates a Stop Mode Recovery event and indicates a Watch Dog Timer time out Reading this register resets the upper four bits to 0 Writing the 55H AAH unlock sequence to the Watch Dog Timer Control WDTCTL reg ister address unlocks the three Watch Dog Timer Reload Byte registers WDTU WDTH and WDTL to allow changes to the time out period These write operations to the WDTCTL register address produce no effect on the bits in the WDTCTL register The locking mechanism prevents spurious writes to the Reload registers Table 46 Watch Dog Timer Control Register WDTCTL BITS 7 6 5 4 3 2 1 0 FIELD POR STOP WDT EXT Reserved RESET X X X 0 0 R W R R R R R R R R ADDR FFO POR Power On Reset Indicator If this bit is set to 1 a Power On Reset event occurred This bit is reset to 0 if a WDT time out or Stop Mode Recovery occurs This bit is also reset to 0 when the register is read STOP STOP Mode Recovery Indicator If this bit is
201. ocation of the data stream 9th bit Reserved These bits are reserved and must be 0 RDAIRQ Receive Data Interrupt Enable 0 Received data and receiver errors generates an interrupt request to the Interrupt Con troller 1 Received data does not generate an interrupt request to the Interrupt Controller Only receiver errors generate an interrupt request The associated DMA will still be notified that received data is available IREN Infrared Encoder Decoder Enable 0 Infrared Encoder Decoder is disabled UART operates normally operation 1 Infrared Encoder Decoder is enabled The UART transmits and receives data through the Infrared Encoder Decoder UARTx Baud Rate High and Low Byte Registers The UARTx Baud Rate High and Low Byte registers Tables 56 and 57 combine to create a 16 bit baud rate divisor value BRG 15 0 that sets the data transmission rate baud rate of the UART Table 56 UARTx Baud Rate High Byte Register UxBRH BITS 7 6 5 4 3 2 1 0 FIELD BRH RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR F46H and FAEH 017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 92 21108 Table 57 UARTx Baud Rate Low Byte Register UxBRL BITS 7 6 5 4 3 2 1 0 FIELD BRL RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R w ADDR F47H and 4 The UART data rate is calculated
202. ode following any of the following opera tions Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface eZ8 CPU execution of a BRK Breakpoint instruction when enabled Break upon a Watchpoint match e Ifthe DBG pin is Low when the Z8F640x family device exits Reset the On Chip Debugger automatically puts the device into Debug mode Exiting Debug Mode The device exits Debug mode following any of the following operations Clearing the DBGMODE bit in the OCD Control Register to 0 PS017610 0404 On Chip Debugger Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Power on reset e Voltage Brownout reset Asserting the RESET pin Low to initiate a Reset e Driving the pin Low while the Z8F640x family device is in Stop mode initiates a System Reset OCD Data Format START The OCD interface uses the asynchronous data format defined for RS 232 Each character is transmitted as 1 Start bit 8 data bits least significant bit first and 1 5 Stop bits Figure 89 DO D1 D2 D3 D4 D5 D6 D7 STOP Figure 89 OCD Data Format OCD Auto Baud Detector Generator 017610 0404 To run over a range of baud rates data bits per second with various system clock frequen cies the On Chip Debugger has an Auto Baud Detector Generator After a reset the OCD is idle until it receives data The OCD requires that the first character sen
203. oded by the Infrared Endec and passed to the UART The UART s baud rate clock is used by the Infrared Endec to generate the demodulated signal RXD that drives the UART Each UART Infrared data bit is 16 clocks wide Figure 73 illustrates data recep tion When the Infrared Endec is enabled the UART s RXD signal is internal to the Z8F640x family device while the IR RXD signal is received through the RXD pin PS017610 0404 Infrared Encoder Decoder Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 16 clock period gt I Sene II Start Bit 0 Data Bit 0 1 Data Bit 1 0 Data Bit 2 1 Data Bit 3 1 IR_RXD min 1 6us lt pulse 1 UART s RXD Start Bit 0 Data Bit 0 1 Data Bit 1 2 0 Data Bit 2 1 Data Bit 3 1 8 clock y delay 16 clock 16 clock 16 clock 16 clock lt period 7 period gt lt period gt lt period gt Figure 73 Infrared Data Reception Jitter Because of the inherent sampling of the received IR RXD signal by the bit rate clock some jitter can be expected on the first bit in any sequence of data subsequent bits in the received data stream are a fixed 16 clock periods wide Infrared Encoder Decoder Control Register Definitions AII Infrared Endec configuration and status information is set by the UART control regis ters as defined beginning on page 86 AN Caut
204. oe 2 3 r Ir 63 2 4 R R 64 3 3 R IR 65 3 4 R IM 66 3 3 IR IM 67 3 4 dst src NOT dst AND src ER ER 68 OR d 4 3 ER IM 69 4 3 dst src dst AND src r r 72 Q 2 3 r Ir 73 2 4 R R 74 3 3 R IR 75 3 4 R IM 76 3 3 IR IM 77 3 4 dst src dst AND src ER ER 78 Q a a 4 3 ER IM 79 4 3 TRAP Vector SP lt SP 2 Vector F2 2 6 QSP lt PC SP lt SP 1 QSP lt FLAGS PC lt QG Vector WDT 5 1 2 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 5 to 1 X Undefined PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 200 ZiLoG Table 126 eZ8 CPU Instruction Summary Continued Assembly Opcode s Een Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D H Cycles Cycles XOR dst src dst dst XOR src r r B2 Q0 2 3 r Ir B3 2 4 R R B4 3 3 R IR B5 3 4 R IM B6 3 3 IR IM B7 3 4 XORX dst src dst lt dst XOR src ER ER B8 0 e 4 3 ER IM B9 4 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Flags Register The Flags Register contains the status information regarding the most recent arithmetic logical bit manipulat
205. oltage exceeds the POR voltage threshold the POR Counter is enabled and counts 514 cycles of the Watch Dog Timer oscillator After the POR counter times out the XTAL Counter is enabled to count a total of 16 system clock pulses The Z8F640x family device is held in the Reset state until both the POR Counter and XTAL counter have timed out After the device exits the Power On Reset state the eZ8 CPU fetches the Reset vector Following Power On Reset the POR status bit in the Watch Dog Timer Control WDTCTL register is set to 1 Figure 62 illustrates Power On Reset operation Refer to the Electrical Characteristics chapter for the POR threshold voltage Vpog VCC 3 3V Crystal Oscillator mm ds XOUT Oscillator Start up Internal RESET signal I 1 X gt lt gt POR XTAL counter delay counter delay Figure 62 Power On Reset Operation not to scale Voltage Brown Out Reset The devices in the Z8F640x family provide low Voltage Brown Out VBO protection The VBO circuit senses when the supply voltage drops to an unsafe level below the VBO PS017610 0404 Reset and Stop Mode Recovery Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 threshold voltage Vygo and forces the device into the Reset state While the supply volt age remains below the Power On Reset voltage threshold the VBO block holds the Z8F640x family device in the Reset state Af
206. omplement under mask 188 test under mask 188 timer signals 14 timers 5 57 architecture 57 block diagram 58 capture mode 62 71 capture compare mode 65 71 compare mode 63 71 continuous mode 59 70 counter mode 60 counter modes 70 Preliminary Index gated mode 64 71 one shot mode 58 70 operating mode 58 PWM mode 61 70 reading the timer count values 66 reload high and low byte registers 67 timer control register definitions 66 timer output signal operation 66 timers 0 3 control registers 70 high and low byte registers 66 69 TM TMX 188 tools hardware and software 214 transmit IrDA data 96 transmit interrupt 112 transmitting UART data polled method 80 transmitting UART data interrupt driven method 81 TRAP 190 U UART 4 architecture 78 asynchronous data format without with parity 80 baud rate generator 85 baud rates table 93 control register definitions 86 controller signals 14 data format 79 interrupts 85 multiprocessor mode 84 receiving data using DMA controller 83 receiving data using interrupt driven method 82 receiving data using the polled method 82 transmitting data using the interrupt driven method 81 transmitting data using the polled method 80 x baud rate high and low registers 91 x control 0 and control registers 89 x status 0 and status 1 registers 87 UxBRH register 91 017610 0404 Preliminary Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z z ZiLOG UxBRL register 92 U
207. on 0 Drive a logical 0 Low 1 Drive a logical 1 High High value is not driven if the drain has been disabled by set ting the corresponding Port Output Control register bit to 1 PS017610 0404 General Purpose I O Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore ZiLOG Interrupt Controller Overview The interrupt controller on the Z8F640x family device prioritizes the interrupt requests from the on chip peripherals and the GPIO port pins The features of the interrupt control ler on the Z8F640x family device include the following 24 unique interrupt vectors 12 GPIO port pin interrupt sources 12 on chip peripheral interrupt sources Flexible GPIO interrupts 8 selectable rising and falling edge GPIO interrupts 4 dual edge interrupts 3 levels of individually programmable interrupt priority Watch Dog Timer can be configured to generate an interrupt Interrupt requests IRQs allow peripheral devices to suspend CPU operation in an orderly manner and force the CPU to start an interrupt service routine ISR Usually this interrupt service routine is involved with the exchange of data status information or control infor mation between the CPU and the interrupting peripheral When the service routine is com pleted the CPU returns to the operation from which it was interrupted The eZ8 CPU supports both vectored and polled interrupt handling For polled interrupts the interrupt control has no effect on
208. on page 7 to determine the signals available for the specific package styles Table 2 Signal Descriptions Signal Mnemonic Description General Purpose I O Ports A H PA 7 0 IO Port A 7 0 These pins are used for general purpose I O PB 7 0 IO Port B 7 0 These pins are used for general purpose I O PC 7 0 IO Port C 7 0 These pins are used for general purpose I O PD 7 0 IO Port D 7 0 These pins are used for general purpose I O PE 7 0 IO Port E 7 0 These pins are used for general purpose I O PF 7 0 IO Port F 7 0 These pins are used for general purpose I O PG 7 0 IO Port G 7 0 These pins are used for general purpose I O PH 3 0 IO Port H 3 0 These pins are used for general purpose I O Pc Controller SCL Serial Clock This is the output clock for the This pin is multiplexed with a general purpose I O pin When the general purpose I O pin is configured for alternate function to enable the SCL function this pin is open drain SDA IO Serial Data This open drain pin is used to transfer data between the PC anda slave This pin is multiplexed with a general purpose I O pin When the general purpose I O pin is configured for alternate function to enable the SDA function this pin is open drain SPI Controller SS T O Slave Select This signal can be an output or an input If the Z8 Encore is the SPI master this pin may be configured as the Slave Select output If the Z8 Encore
209. on for more information on operation of the PHASE bit CLKPOL Clock Polarity 0 SCK idles Low 0 1 SCK idle High 1 WOR Wire OR Open Drain Mode Enabled 0 SPI signal pins not configured for open drain 1 All four SPI signal pins SCK SS MISO MOSI configured for open drain function This setting is typically used for multi master and or multi slave configurations MMEN SPI Master Mode Enable 0 SPI configured in Slave mode 1 SPI configured in Master mode PS017610 0404 Serial Peripheral Interface Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 7 108 21108 SPIEN SPI Enable 0 SPI disabled 2 SPI enabled SPI Status Register The SPI Status register indicates the current state of the SPI Table 62 SPI Status Register SPISTAT BITS 7 6 5 4 3 2 1 0 FIELD IRQ OVR COL Reserved TXST SLAS RESET 0 0 0 0 0 1 R W R W R W R W R R R ADDR F62H R W Read access Write a 1 to clear the bit to 0 017610 0404 IRQ Interrupt Request 0 No SPI interrupt request pending 1 SPI interrupt request is pending OVR Overrun 0 An overrun error has not occurred 1 An overrun error has been detected COL Collision 0 A multi master collision mode fault has not occurred 2 A multi master collision mode fault has been detected Reserved These bits are reserved and must be 0 TXST Transmit Status 0 No data transmission cu
210. on timer Reload Continuous mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload Counter mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload PWM mode 0 Timer Output is forced Low 0 when the timer is disabled When enabled the Timer Output is forced High 1 upon PWM count match and forced Low 0 upon Reload 1 Timer Output is forced High 1 when the timer is disabled When enabled the Timer Output is forced Low 0 upon PWM count match and forced High 1 upon Reload Timers 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Capture mode 0 Count is captured on the rising edge of the Timer Input signal 1 Count is captured on the falling edge of the Timer Input signal Compare mode When the timer is disabled the Timer Output signal is set to the value of this bit When the timer is enabled the Timer Output signal is complemented upon timer Reload Gated mode 0 Timer counts when the Timer Input signal is High 1 and interrupts are generated on the falling edge of the Timer Input 1 Timer counts when the Timer Input signal is Low 0 and interrupts are generated on the rising edge of the Timer Input Capture Compare mode
211. onditions Vpog Power On Reset Voltage 2 40 2 70 2 90 Vpp Vpor Threshold _ Voltage Brown Out Reset 2 30 2 60 2 85 V Vypo Voltage Threshold Vpor to hysteresis 50 100 mV Starting voltage to Vss V ensure valid Power On Reset only and are not tested in production 1 Data in the typical column is from characterization at 3 3V and These values provided for design guidance Tana Power On Reset Analog 50 HS gt Tpog Digital Delay Reset delay follows Tana Tpor Power On Reset Digital 10 2 ms 512 WDT Oscillator cycles Delay 50 70 System Clock cycles 20MHz Tygo Voltage Brown Out Pulse 10 nS lt Vypo to generate a Reset Rejection Period Tramp Time for VDD to transition 0 10 100 ms from Vss to Vpop to ensure valid Reset Table 104 Flash Memory Electrical Characteristics and Timing Vpp 7 3 0 3 6V 400 to 105 C Parameter Minimum Typical Maximum Units Notes Flash Byte Read Time 50 z ns Flash Byte Program Time 20 40 us Flash Page Erase Time 10 ms 017610 0404 Electrical Characteristics Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Table 104 Flash Memory Electrical Characteristics and Timing Continued Vpp 3 0 3 6V 400 to 105 C Parameter Minimum Typical Maximum Units Notes Writes t
212. one The diagram may be interpreted as either a Master or Slave timing diagram since the SCK Master In Slave Out MISO and Master Out Slave In MOSI pins are directly connected between the Master and the Slave SCK CLKPOL 0 SCK CLKPOL 1 MOSI MISO Figure 77 SPI Timing When PHASE is 0 Transfer Format PHASE Equals One Figure 78 illustrates the timing diagram for an SPI transfer in which PHASE is one Two waveforms are depicted for SCK one for CLKPOL reset to 0 and another for CLKPOL set to 1 PS017610 0404 Serial Peripheral Interface Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG SCK CLKPOL 0 SCK CLKPOL 1 MOSI MISO Input Sample Time SS J Figure 78 SPI Timing When PHASE is 1 Multi Master Operation In a multi master SPI system all SCK pins are tied together all MOSI pins are tied together and all MISO pins are tied together All SPI pins must then be configured in open drain mode to prevent bus contention At any one time only one SPI device is con figured as the Master and all other SPI devices on the bus are configured as Slaves The Master enables a single Slave by asserting the SS pin on that Slave only Then the single Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the Slaves including those which are not enabled The enabled Slave drives data out its
213. otect Option Bit is enabled this command returns FFFFH DBG 07H ProgramCounter 15 8 DBG ProgramCounter 7 0 Write Register 08H The Write Register command writes data to the Register File Data can be written 1 256 bytes at a time 256 bytes can be written by setting size to zero If the Z8F640x family device is not in Debug mode the address and data values are discarded If the Read Protect Option Bit is enabled then only writes to the Flash Control Registers are allowed and all other register write data values are discarded DBG 08H DBG 4 hO Register Address 11 8 Register Address 7 0 DBG Size 7 0 DBG 1 256 data bytes Read Register 09H The Read Register command reads data from the Register File Data can be read 1 256 bytes at a time 256 bytes can be read by setting size to On Chip Debugger 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 zero If the Z8F640x family device is not in Debug mode or if the Read Protect Option Bit is enabled this command returns FFH for all the data values DBG 09H lt 4 h0 Register Address 11 8 DBG Register Address 7 0 DBG Size 7 0 DBG 1 256 data bytes Write Program Memory 0AH The Write Program Memory command writes data to Program Memory This command is equivalent to the LDC and LDCI instructions Data can be written 1 65536 bytes at a
214. ounter 185 program memory 18 PUSH 189 push using extended addressing 189 PUSHX 189 PWM mode 70 PxADDR register 37 PxCTL register 38 Q QFP 210 R R 184 r 184 RA register address 184 RCF 188 189 receive 10 bit data format I2C 116 7 bit data transfer format I2C 115 IrDA data 97 receive interrupt 112 receiving UART data DMA controller 83 receiving UART data interrupt driven method 82 receiving UART data polled method 82 Index register 109 126 184 ADC control ADCCTL 135 ADC data high byte ADCDH 137 ADC data low bits ADCDL 137 baud low and high byte I2C 121 baud rate high and low byte SPI 110 control SPI 107 control I2C 119 data SPI 106 DMA status DMAA STAT 131 DMA_ADC address 128 DMA ADC control DMAACTL 130 DMAx address high nibble DMAxH 126 DMAx control DMAxCTL 124 DMAx end address low byte DMAxEND 128 DMAx start current address low byte register DMAxSTART 128 flash control FCTL 144 flash high and low byte FFREQH and FREEQL 147 flash page select FPS 146 flash status FSTAT 145 GPIO port A H address PXADDR 37 GPIO port A H alternate function sub registers 39 GPIO port A H control address PXCTL 38 GPIO port A H data direction sub registers 39 I2C baud rate high IZCBRH 121 12 control I2CCTL 119 12 data I2CDATA 118 I2C status 118 I2C status I2CSTAT 118 I2Cbaud rate low IZ2CBRL 121 mode SPI 109 OCD control 161 OCD status 162 OCD watchpoint address 164 OCD w
215. r Table 86 Flash Status Register FSTAT BITS 7 6 5 4 3 2 1 0 FIELD Reserved FSTAT RESET 0 0 0 0 0 0 0 0 R W R R R R R R R R ADDR FF8H Reserved These bits are reserved and must be 0 FSTAT Flash Controller Status 000000 Flash Controller locked 000001 First unlock command received 000010 Flash Controller unlocked second unlock command received 001xxx Program operation in progress 010xxx Page erase operation in progress 100xxx Mass erase operation in progress PS017610 0404 Flash Memory Flash Page Select Register Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 The Flash Page Select register is used to select one of the 128 available Flash memory pages to be erased in a Page Erase operation Each Flash Page contains 512 bytes of Flash memory During a Page Erase operation all Flash memory having addresses with the most significant 7 bits given by FPS 6 0 are erased all bytes written to FFH Table 87 Flash Page Select Register FPS BITS 7 6 5 3 0 FIELD Reserved PAGE RESET 0 0 0 0 0 R W R W R W R W R W R W R W ADDR FF9H Reserved This bit is reserved and must be 0 PAGE Page Select This 7 bit field identifies the Flash memory page for Page Erase operation Program Memory Address 15 9 PAGE 6 0 017610 0404 Flash Memory Z8F640x Z8F480x Z8F320x Z8F240x Z8
216. r the data has been sent to the Data register Reading this bit always returns 0 FILTEN PC Signal Filter Enable Setting this bit to 1 enables low pass digital filters on the SDA and SCL input signals These filters reject any input pulse with periods less than a full system clock cycle The fil ters introduce a 3 system clock cycle latency on the inputs PS017609 0803 12C Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore L ZiLOG 12 Baud Rate High and Low Byte Registers The Baud Rate High and Low Byte registers combine to form a 16 bit reload value BRG 15 0 for the PC Baud Rate Generator The 12 baud rate is calculated using the fol lowing equation I2C Baud Rate bits s S stem Clock Frequency Hz Hz Table 69 12 Baud Rate High Byte Register IZCBRH BITS 7 6 5 4 3 2 1 0 FIELD BRH RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR F53H Baud Rate High Byte Most significant byte BRG 15 8 of the Baud Rate Generator s reload value Table 70 12 Baud Rate Low Byte Register IZCBRL BITS 7 6 5 4 3 2 1 0 FIELD BRL RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR F54H BRL Baud Rate Low Byte Least significant byte BRG 7 0 of the Baud Rate Generator s reload value PS017609 0803 12C Controller Z8F640x Z8F480x Z8F
217. re available in all packages for the Z8F640x family of products Refer to the Signal and Pin Descrip tions chapter for information regarding the Port pins available with each package style Do not enable unavailable analog inputs 0000 2 ANAO 0001 2 ANAI 0010 2 ANA2 0011 ANA3 0100 4 0101 ANAS 0110 ANA6 0111 ANA7 1000 ANA8 1001 ANA9 1010 ANA10 1011 1 11XX Reserved Analog to Digital Converter Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore A ZiLOG ADC Data High Byte Register The ADC Data High Byte register contains the upper eight bits of the 10 bit ADC output During a conversion this value is invalid Access to the ADC Data High Byte register is read only The full 10 bit ADC result is given by ADCD H 7 0 ADCD L 7 6 Table 81 ADC Data High Byte Register ADCD H BITS 7 6 5 4 3 2 1 0 FIELD ADCD H RESET X R W R ADDR F72H ADCD_H ADC Data High Byte This byte contains the upper eight bits of the 10 bit ADC output These bits are not valid during a conversion These bits are undefined after a Reset ADC Data Low Bits Register The ADC Data Low Bits register contains the lower two bits of the conversion value Dur ing a conversion this value is invalid Access to the ADC Data Low Bits register is read only The full 10 bit ADC result is given by ADCD H 7 0 ADCD L 7 6 Table 82 ADC Data Low Bits Register ADCD L
218. re value the timer generates an interrupt and counting continues the timer value is not reset to 0001H Also if the Timer Output alternate function is enabled the Timer Output pin changes state from Low to High or from High to Low upon Com pare PS017610 0404 Timers 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi ZiLOG If the Timer reaches FFFFH the timer rolls over to 0000H and continue counting The steps for configuring a timer for Compare mode and initiating the count are as fol lows 1 Write to the Timer Control register to Disable the timer Configure the timer for Compare mode Set the prescale value Set the initial logic level High or Low for the Timer Output alternate function if desired 2 Write to the Timer High and Low Byte registers to set the starting count value Write to the Timer Reload High and Low Byte registers to set the Compare value 4 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 Ifusing the Timer Output function configure the associated GPIO port pin for the Timer Output alternate function 6 Wirite to the Timer Control register to enable the timer and initiate counting In Compare mode the system clock always provides the timer input The Compare time is given by the following equation Compare Mode Time s Compare Value Start Value x Prescale System Clo
219. read this register must process all three interrupt sources from the DMA Table 79 DMA_ADC Status Register DMAA STAT BITS 7 6 5 4 3 2 1 0 FIELD CADC 3 0 Reserved IRQA IRQI IRQO RESET 0 0 0 0 0 0 0 0 R W R R R R R R R R ADDR FBFH CADC 3 0 Current ADC Analog Input This field identifies the Analog Input that the ADC is currently converting Reserved This bit is reserved and must be 0 IRQA DMA ADC Interrupt Request Indicator This bit is automatically reset to 0 each time a read from this register occurs 0 is not the source of the interrupt from the DMA Controller 1 DMA_ADC completed transfer of data from the last ADC Analog Input and generated an interrupt IRQI DMAI Interrupt Request Indicator This bit is automatically reset to 0 each time a read from this register occurs 0 DMAI is not the source of the interrupt from the DMA Controller 1 DMAI completed transfer of data to from the End Address and generated an interrupt IRQ0 DMAO Interrupt Request Indicator This bit is automatically reset to 0 each time a read from this register occurs 0 DMAO is not the source of the interrupt from the DMA Controller 1 DMAO completed transfer of data to from the End Address and generated an interrupt PS017610 0404 Direct Memory Access Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 132 ZiLOG Analog to Digital Converter Over
220. reset in Gated mode counting always begins at the reset value of 0001H Write to the Timer Reload High and Low Byte registers to set the Reload value 4 If desired enable the timer interrupt and set the timer interrupt priority by writing to the relevant interrupt registers 5 Configure the associated GPIO port pin for the Timer Input alternate function 6 Wirite to the Timer Control register to enable the timer 7 Assert the Timer Input signal to initiate the counting Capture Compare Mode In Capture Compare mode the timer begins counting on the first external Timer Input transition The desired transition rising edge or falling edge is set by the TPOL bit in the Timer Control Register The timer input is the system clock Every subsequent desired transition after the first of the Timer Input signal captures the current count value The Capture value is written to the Timer PWM High and Low Byte Registers When the Capture event occurs an interrupt is generated the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes If no Capture event occurs the timer counts up to the 16 bit Compare value stored in the Timer Reload High and Low Byte registers Upon reaching the Compare value the timer generates an interrupt the count value in the Timer High and Low Byte registers is reset to 0001H and counting resumes The steps for configuring a timer for Capture Compare mode and initiating the
221. ress lookup Example is the memory location referenced by the address contained in the Working Register R1 Parentheses Bracket Combinations The parentheses indicate an indirect register address lookup and the square brackets indicate a register or bus e Example assume PC 15 0 contains the value 1234h PC 15 0 then refers to the contents of the memory location at address 1234h Use of the Words Set Reset and Clear The word set implies that a register bit or a condition contains a logical 1 The words reset or clear imply that a register bit or a condition contains a logical 0 When either of these terms is followed by a number the word ogical may not be included however it is implied Notation for Bits and Similar Registers A field of bits within a register is designated as Register n n Example ADDR 15 0 refers to bits 15 through bit 0 of the Address Use of the Terms LSB MSB Isb and msb In this document the terms LSB and MSB when appearing in upper case mean least sig nificant byte and most significant byte respectively The lowercase forms sb and msb mean least significant bit and most significant bit respectively Use of Initial Uppercase Letters Initial uppercase letters designate settings modes and conditions in general text e Example 1 Stop mode Example 2 The receiver forces the SCL line to Low The Master can generate a Stop condition to abort the transfer
222. ristics of the Z8F640x family devices All voltages are ref erenced to Vss the primary system ground Table 101 DC Characteristics T 40 C to 105 C Symbol Parameter Minimum Typical Maximum Units Conditions Vpp Supply Voltage 3 0 3 6 V Vg Low Level Input Voltage 0 3 0 3 Vpp V For all input pins except RESET DBG and XIN Low Level Input Voltage 0 3 0 2 Vpp V For RESET and XIN Vig High Level Input Voltage 0 7 Vpp 5 5 V Port A C D E and G pins Vio High Level Input Voltage 0 7 Vpp Vpp40 3 V Port B and H pins Vig3 High Level Input Voltage 0 8 Vpp Vppt 0 3 V and XIN pins Level Output Voltage 0 4 Vpp 3 0V Io 2mA High Output Drive disabled Von High Level Output Voltage 2 4 Vpp 3 0V 2mA High Output Drive disabled Vor Level Output Voltage 0 6 Vpp 3 3V Io 20mA High Output Drive enabled 40 C to 70 C Vor3 Level Output Voltage 0 6 V Vpp 3 3 15mA High Output Drive enabled 70 C to 105 C 2 High Level Output Voltage 2 4 Vpp 3 3 20mA High Output Drive enabled 40 C to 70 C High Level Output Voltage 2 4 Vpp 3 3 I5mA High Output Drive enabled 70 C to 105 C Ig Input Leaka
223. rogress for 160 consecutive system clock cycles portions of the ADC are automatically powered down From this power down state the ADC requires 40 system clock cycles to power up The ADC powers up when a conver sion is requested using the ADC Control register Single Shot Conversion When configured for single shot conversion the ADC performs a single analog to digital conversion on the selected analog input channel After completion of the conversion the ADC shuts down The steps for setting up the ADC and initiating a single shot conversion are as follows PS017610 0404 Analog to Digital Converter Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Enable the desired analog inputs by configuring the general purpose I O pins for alternate function This configuration disables the digital input and output drivers Write to the ADC Control register to configure the ADC and begin the conversion The bit fields in the ADC Control register can be written simultaneously Write to ANAIN 3 0 to select one of the 12 analog input sources Clear CONT to 0 to select a single shot conversion Write to VREF to enable or disable the internal voltage reference generator Set CEN to 1 to start the conversion CEN remains 1 while the conversion is in progress A single shot conversion requires 5129 system clock cycles to complete If a single shot conversion is requested from an ADC powered down state the ADC
224. rrently in progress 1 Data transmission currently in progress SLAS Slave Select If SPI enabled as a Slave 0 SS input pin is asserted Low 1 SS input is not asserted High If SPI enabled as a Master this bit is not applicable Serial Peripheral Interface Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Z ZiLOG SPI Mode Register The SPI Mode register configures the character bit width and the direction and value of the SS pin Table 63 SPI Mode Register SPIMODE BITS 7 6 5 4 3 2 1 0 FIELD Reserved NUMBITS 2 0 SSIO SSV RESET 0 0 0 0 0 0 R W R R W R W R W R W R W ADDR F63H Reserved These bits are reserved and must be 0 NUMBITS 2 0 Number of Data Bits Per Character to Transfer This field contains the number of bits to shift for each character transfer Refer to the SPI Data Register description for information on valid bit positions when the character length is less than 8 bits 000 8 bits 001 1 bit 010 2 bits 011 3 bits 100 4 bits 101 5 bits 110 6 bits 111 2 7 bits SSIO Slave Select I O 0 SS pin configured as an input 1 SS pin configured as an output Master mode only SSV Slave Select Value If SSIO 1 and SPI configured as a Master 0 SS pin driven Low 0 1 SS pin driven High 1 This bit has no effect if SSIO 0 or SPI configured as a Slave PS017610 0404 Serial Peripheral Interface
225. rrupt Enable 0 does not generate any interrupts 1 DMA_ADC generates an interrupt after transferring data from the last ADC Analog Input specified by the ADC_IN field Reserved These bits are reserved and must be 0 ADC_IN ADC Analog Input Number These bits set the number of ADC Analog Inputs to be used in the continuous update data conversion followed by DMA data transfer The conversion always begins with ADC Analog Input 0 and then progresses sequentially through the other selected ADC Analog Inputs 0000 ADC Analog Input 0 updated 0001 ADC Analog Inputs 0 1 updated 0010 ADC Analog Inputs 0 2 updated 0011 ADC Analog Inputs 0 3 updated 0100 ADC Analog Inputs 0 4 updated 0101 ADC Analog Inputs 0 5 updated 0110 ADC Analog Inputs 0 6 updated 0111 ADC Analog Inputs 0 7 updated 1000 ADC Analog Inputs 0 8 updated 1001 ADC Analog Inputs 0 9 updated 1010 ADC Analog Inputs 0 10 updated 1011 ADC Analog Inputs 0 11 updated 1100 1111 Reserved PS017610 0404 Direct Memory Access Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore L 211 08 Status Register The DMA Status register indicates the DMA channel that generated the interrupt and the ADC Analog Input that is currently undergoing conversion Reads from this register reset the Interrupt Request Indicator bits IRQA IRQ1 and IRQO to 0 Therefore software interrupt service routines that
226. rs Addrs represents a number in the range of 0000H to FFFFH ER Extended Addressing Register Reg Reg represents a number in the range of 000H to FFFH IM Immediate Data Data Data is a number between 00H to FFH Ir Indirect Working Register Rn n 0 15 IR Indirect Register Reg Reg represents a number in the range of 00H to FFH Irr Indirect Working Register Pair RRp 0 2 4 6 8 10 12 14 IRR Indirect Register Pair Reg Reg represents an even number in the range 00H to FEH p Polarity p Polarity is a single bit binary value of either OB or 1B r Working Register Rn nz0 15 R Register Reg Reg represents a number in the range of 00H to FFH RA Relative Address X X represents an index in the range of 127 to 128 which is an offset relative to the address of the next instruction IT Working Register Pair RRp p 0 2 4 6 8 10 12 or 14 RR Register Pair Reg Reg represents an even number in the range of 00H to FEH Vector Vector Address Vector Vector represents a number in the range of 00H to FFH X Indexed Index The register or register pair to be indexed is offset by the signed Index value Index in a 127 to 128 range Table 116 contains additional symbols that are used throughout the Instruction Summary and Instruction Set Description sections 017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Table 116 Additional Symbols Symbol Definition dst Destination Operand
227. rupts Write to the Interrupt control registers to enable the UART Receiver interrupt and set the desired priority Clear the UART Receiver interrupt in the applicable Interrupt Request register Write to the UART Control 1 register to enable Multiprocessor 9 bit mode functions if desired UART 7 8 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Write to Control 0 register to Set the receive enable bit REN to enable the UART for data reception Enable parity if desired and select either even or odd parity Execute an EI instruction to enable interrupts The UART is now configured for interrupt driven data reception When the UART Receiver interrupt is detected the associated interrupt service routine ISR should per form the following 9 10 11 12 Check the UART Status 0 register to determine the source of the interrupt error break or received data If the interrupt was due to data available read the data from the UART Receive Data register If operating in Multiprocessor 9 bit mode first read the Multiprocessor Receive flag MPRX to determine if the data was directed to this UART before reading the data Clear the UART Receiver interrupt in the applicable Interrupt Request register Execute the IRET instruction to return from the interrupt service routine and await more data Receiving Data using the Direct Memory Access Controller DMA Th
228. ry sets all bytes to the value FFH With the Flash Controller unlocked writing the value 638 to the Flash Control register initiates the Mass Erase operation While the Flash Controller executes the Mass Erase operation the eZ8 CPU idles but the system clock and on chip peripherals continue to operate Typically the Flash Memory is Mass Erased using the On Chip Debugger Via the On Chip Debugger poll the Flash Status reg ister to determine when the Mass Erase operation is complete Although the Flash can be Mass Erased by user program code when the Mass Erase is complete the user program code is completely erased When the Mass Erase is complete the Flash Controller returns to its locked state Flash Controller Bypass The Flash Controller can be bypassed and the control signals for the Flash memory brought out to the GPIO pins Bypassing the Flash Controller allows faster Row Program ming algorithms by controlling the Flash programming signals directly Row programing is recommended for gang programming applications and large volume customers who do not require in circuit initial programming of the Flash memory Mass Erase and Page Erase operations are also supported when the Flash Controller is bypassed Please refer to the document entitled Third Party Flash Programming Support for Z8 Encore for more information on bypassing the Flash Controller This document is available for download at www zilog com PS017610 0404 Flash Memory
229. s No Yes Yes Programmable PE7 0 Io I N A Yes No Yes Yes Programmable x represents integer 0 1 to indicate multiple pins with symbol mnemonics that differ only by the integer PS017610 0404 Signal and Pin Descriptions Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 16 Table 3 Pin Characteristics of the Z8F640x family Active Low Internal Schmitt Symbol Reset or Tri State Pull upor Trigger Open Drain Mnemonic Direction Direction Active High Output Pull down Input Output PF 7 0 Io I N A Yes No Yes Yes Programmable PG 7 0 Io I N A Yes No Yes Yes Programmable PH 3 0 Io I N A Yes No Yes Yes Programmable RESET I I Low N A Pull up Yes N A VDD N A N A N A N A No No N A XIN I I N A N A No No N A XOUT Yes in No No No Stop mode x represents integer 0 1 to indicate multiple pins with symbol mnemonics that differ only by the integer 017610 0404 Signal and Pin Descriptions Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore ZiLOG Address Space Overview The eZ8 CPU can access three distinct address spaces The Register File contains addresses for the general purpose registers and the eZ8 CPU peripheral and general purpose I O port control registers Program Memory contains addresses for all memory locations having executable code and or data The Data Memory contains addresses for all memory locations that hold data only Th
230. scriptions 13 single assertion pulse interrupt sources 47 single shot conversion ADC 133 SIO 5 slave data transfer formats I2C 114 slave select 102 software trap 190 source operand 185 SP 185 SPI architecture 99 baud rate generator 105 baud rate high and low byte register 110 clock phase 102 configured as slave 100 control register 107 control register definitions 106 data register 106 error detection 105 interrupts 105 mode fault error 105 mode register 109 multi master operation 104 operation 100 overrun error 105 signals 101 single master multiple slave system 100 single master single slave system 99 status register 108 timing PHASE 0 103 timing PHASE 1 104 SPI controller signals 13 SPI mode SPIMODE 109 SPIBRH register 110 SPIBRL register 110 SPICTL register 107 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 211 08 SPIDATA register 106 SPIMODE register 109 SPISTAT register 108 SRA 191 src 185 SRL 191 SRP 189 SS SPI signal 101 stack pointer 185 status register I2C 118 STOP 189 stop mode 31 189 stop mode recovery sources 29 using a GPIO port pin transition 30 using watch dog timer time out 29 SUB 188 subtract 188 subtract extended addressing 188 subtract with carry 188 subtract with carry extended addressing 188 SUBX 188 SWAP 191 swap nibbles 191 symbols additional 185 system and short resets 26 T TCM 188 TCMX 188 technical support 213 test c
231. se 143 page select register 146 FPS register 146 FSTAT register 145 19 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore L z ZiLOG G gated mode 71 general purpose I O 33 GPIO 4 33 alternate functions 34 architecture 34 control register definitions 36 input data sample timing 176 interrupts 36 port A H address registers 37 port A H alternate function sub registers 39 port A H control registers 38 port A H data direction sub registers 39 port A H high drive enable sub registers 41 port A H input data registers 42 port A H output control sub registers 40 port A H output data registers 43 port A H stop mode recovery sub registers 41 port availability by device 33 port input timing 176 port output timing 177 H H 185 HALT 189 HALT mode 31 189 hexadecimal number prefix suffix 185 I Pc4 10 bit address read transaction 116 10 bit address transaction 114 10 bit addressed slave data transfer format 114 10 bit receive data format 116 7 bit address transaction 112 7 bit address reading a transaction 115 7 bit addressed slave data transfer format 113 7 bit receive data transfer format 115 baud high and low byte registers 121 C status register 118 control register definitions 118 PS017610 0404 Preliminary Index controller 111 controller signals 13 interrupts 112 operation 111 SDA and SCL signals 111 stop and start conditions 112 I2CBRH register 121 I2CBRL register 121 I2CCTL register 119 I2CDATA re
232. signal from the Master synchronizes the data transfer between the Master and Slave devices Slave devices ignore the SCK signal unless the SS pin is asserted PS017610 0404 Serial Peripheral Interface Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG The Master and Slave are each capable of exchanging a byte of data during a sequence of eight clock cycles In both Master and Slave SPI devices data is shifted on one edge of the SCK and is sampled on the opposite edge where data is stable Edge polarity is determined by the SPI phase and polarity control Slave Select The active Low Slave Select SS input signal is used to select a Slave SPI device SS must be Low prior to all data communication to and from the Slave device SS must stay Low for the full duration of each character transferred The SS signal may stay Low dur ing the transfer of multiple characters or may deassert between each character When the SPI on the Z8F640x family device is configured as the only Master in an SPI system the SS pin can be set as either an input or an output For communication between the Z8F640x family device SPI Master and external Slave devices the SS signal as an output can assert the SS input pin on one of the Slave devices Other GPIO output pins can also be employed to select external SPI Slave devices When the SPI on the Z8F640x family device is configured as one Master in a multi master SPI system the SS pin on the should
233. ster Empty This bit indicates that the UART Transmit Data register is empty and ready for additional data Writing to the UART Transmit Data register resets this bit 0 Do not write to the UART Transmit Data register 1 The UART Transmit Data register is ready to receive an additional byte to be transmit ted TXE Transmitter Empty This bit indicates that the transmit shift register is empty and character transmission is fin ished 0 Data is currently transmitting 1 Transmission is complete CTS CTS signal When this bit is read it returns the level of the CTS signal PS017610 0404 UART Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 89 ZiLOG Table 53 UARTx Status 1 Register UxSTAT1 BITS 7 6 5 4 3 2 1 0 FIELD Reserved MPRX RESET 0 0 0 0 0 0 0 0 R W R R R R R R R R ADDR F44H and FACH Reserved These bits are reserved and must be 0 MPRX Multiprocessor Receive This status bit is for the receiver and reflects the actual status of the last multiprocessor bit received Reading from the UART Data register resets this bit to 0 UARTx Control 0 and Control 1 Registers The UARTx Control 0 and Control 1 registers Tables 54 and 55 configure the properties of the UART s transmit and receive operations The UART Control registers must ben be written while the UART is enabled Table 54 UARTx Control 0 Register UxCTLO
234. t p r F6 3 3 lt Ir 3 4 BTJNZ bit src dst if src bit 1 r F6 3 3 lt Ir 3 ii Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS017610 0404 eZ8 CPU Instruction Set Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 193 ZiLoG Table 126 eZ8 CPU Instruction Summary Continued Assembly Opcode s ue Fetch Instr Mnemonic Symbolic Operation dst src Hex C Z S V D Cycles Cycles BTJZ bit src dst if src bit 0 r F6 CX 4E E lue 3 3 lt Ir 3 4 CALL dst SP lt SP 2 IRR D4 M 2 6 PC e dse DA ps C C EF KO umo we 1 2 CLR dst dst lt 00H R BO 2 2 2 IR Bl 2 3 COM dst dst lt dst R 60 2 2 IR 61 2 3 CP dst src dst src r r A2 ko 2 3 r Ir A3 2 4 R R A4 3 3 R IR A5 3 4 R IM A6 3 3 IR IM A7 3 4 CPC dst src dst src C r r 1F A2 LM E M 3 3 r Ir 1 3 4 R R IF A4 4 3 R IR 1 A5 4 4 R IM IF A6 4 3 IR IM 1F A7 4 4 CPCX dst src dst src C ER ER 1 A8 EE S 3 ER IM 1F A9 5 3 CPX dst src dst src ER ER A8 Wo ES GE ONU RS 4 3 ER IM 9 4 3 Flags Notation Value is a function of the result of the operation 0 Reset to 0 Unaffected 1 Set to 1 X Undefined PS017610 0404 eZ8 CP
235. t 514 WDT Oscillator cycles 16 System Clock cycles Short Reset Reset as applicable Reset 66 WDT Oscillator cycles 16 System Clock cycles Stop Mode Recovery Unaffected except Reset 514 WDT Oscillator cycles 16 System Clock cycles WDT_CTL register 017610 0404 Reset and Stop Mode Recovery Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 System and Short Resets During a System Reset the Z8F640x family device is held in Reset for 514 cycles of the Watch Dog Timer oscillator followed by 16 cycles of the system clock crystal oscillator A Short Reset differs from a System Reset only in the number of Watch Dog Timer oscil lator cycles required to exit Reset A Short Reset requires only 66 Watch Dog Timer oscil lator cycles Unless specifically stated otherwise System Reset and Short Reset are referred to collectively as Reset During Reset the eZ8 CPU and on chip peripherals are idle however the on chip crystal oscillator and Watch Dog Timer oscillator continue to run The system clock begins oper ating following the Watch Dog Timer oscillator cycle count The eZ8 CPU and on chip peripherals remain idle through the 16 cycles of the system clock Upon Reset control registers within the Register File that have a defined Reset value are loaded with their reset values Other control registers including the Stack Pointer Regis ter Pointer and Flags and general purpose RAM are undefined fo
236. t controller the cor responding bit in the IRQ1 register becomes 1 If interrupts are globally enabled vectored interrupts the interrupt controller passes an interrupt request to the eZ8 CPU If interrupts are globally disabled polled interrupts the eZ8 CPU can read the Interrupt Request 1 register to determine if any interrupt requests are pending Table 24 Interrupt Request 1 Register IRQ1 BITS 7 6 5 4 3 2 1 0 FIELD PAD7I PADGI PADSI PADAI PAD3I PAD2I PADII PADOI RESET 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W ADDR FC3H 017610 0404 PADxI Port A or Port D Pin x Interrupt Request 0 No interrupt request is pending for GPIO Port A or Port D pin x 1 An interrupt request from GPIO Port A or Port D pin x is awaiting service where x indicates the specific GPIO Port pin number 0 through 7 For each pin only 1 of either Port A or Port D can be enabled for interrupts at any one time Port selection A or D is determined by the values in the Interrupt Port Select Register Interrupt Controller Interrupt Request 2 Register Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 The Interrupt Request 2 IRQ2 register Table 25 stores interrupt requests for both vec tored and polled interrupts When a request is presented to the interrupt controller the cor responding bit in the IRQ2 register becomes 1 If interrupts are globally enabled ve
237. t from the host is the character 80H The character 80H has eight continuous bits Low one Start bit plus 7 data bits The Auto Baud Detector measures this period and sets the OCD Baud Rate Generator accordingly The Auto Baud Detector Generator is clocked by the Z8F640x family device system clock The minimum baud rate is the system clock frequency divided by 512 For optimal operation the maximum recommended baud rate is the system clock frequency divided by 8 The theoretical maximum baud rate is the system clock frequency divided by 4 This theoretical maximum is possible for low noise designs with clean signals Table 92 lists minimum and recommended maximum baud rates for sample crystal frequencies Table 92 OCD Baud Rate Limits System Clock Frequency Recommended Maximum Baud Rate Minimum Baud Rate MHz kbits s kbits s 20 0 2500 39 1 1 0 125 0 1 96 0 032768 32KHz 4 096 0 064 On Chip Debugger Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG If the OCD receives a Serial Break nine or more continuous bits Low the Auto Baud Detector Generator resets The Auto Baud Detector Generator can then be reconfigured by sending 80H OCD Serial Errors The On Chip Debugger can detect any of the following error conditions on the DBG pin e Serial Break a minimum of nine continuous bits Low Framing Error received Stop bit is Low e Transmit Collision OCD and host simultaneous transmission detecte
238. t pin number 0 through 7 Interrupt Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Zi ZiLOG Interrupt Control Register The Interrupt Control IRQCTL register Table 37 contains the master enable bit for all interrupts Table 37 Interrupt Control Register IRQCTL BITS 7 6 5 4 3 2 1 0 FIELD IRQE Reserved RESET 0 0 0 0 0 0 0 0 R W R W R R R R R R R ADDR FCFH IRQE Interrupt Request Enable This bit is set to 1 by execution of an EI Enable Interrupts or IRET Interrupt Return instruction or by a direct register write of a 1 to this bit It is reset to 0 by executing a DI instruction eZ8 CPU acknowledgement of an interrupt request or Reset 0 Interrupts are disabled 1 Interrupts are enabled Reserved These bits must be 0 PS017610 0404 Interrupt Controller Timers Overview Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 57 ZiLOG The Z8F640x family products contain three to four 16 bit reloadable timers that can be used for timing event counting or generation of pulse width modulated PWM signals The timers features include 16 bit reload counter Programmable prescaler with prescale values from 1 to 128 PWM output generation Capture and compare capability External input pin for timer input clock gating or capture signal External input pin signal frequency is limited to a maximum of one fourth the syst
239. t to 2 byte transfers the temporary holding register for the Timer Reload High Byte is not bypassed Table 40 Timer 0 3 Reload High Byte Register TxRH BITS 7 6 5 4 3 2 1 0 FIELD TRH RESET 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR F02H FOAH F12H FIAH Table 41 Timer 0 3 Reload Low Byte Register TxRL BITS 7 6 5 4 3 2 1 0 FIELD TRL RESET 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR F03H FOBH F13H FIBH TRH and TRL Timer Reload Register High and Low These two bytes form the 16 bit Reload value TRH 7 0 TRL 7 0 This value is used to set the maximum count value which initiates a timer reload to 0001H In Compare mode these two byte form the 16 bit Compare value PS017610 0404 Timers Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Timer 0 3 PWM High and Low Byte Registers The Timer 0 3 PWM High and Low Byte TXPWMH and TxPWML registers Tables 42 and 43 are used for Pulse Width Modulator PWM operations These registers also store the Capture values for the Capture and Capture Compare modes Table 42 Timer 0 3 PWM High Byte Register TxPWMH Z8 Encore Zi 211 08 BITS 7 6 5 4 3 0 FIELD PWMH RESET 0 0 0 0 0 0 R W R W R W R W R W R W R W ADDR F04H FOCH F14H F1CH Table 43 Timer 0 3
240. t value Caution The 24 bit WDT Reload Value must not be set to a value less than 000004H or unpredictable behavior may result Table 47 Watch Dog Timer Reload Upper Byte Register WDTU BITS 7 6 5 1 3 2 1 0 FIELD WDTU RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR FFIH R W Read returns the current WDT count value Write sets the desired Reload Value WDTU WDT Reload Upper Byte Most significant byte MSB Bits 23 16 of the 24 bit WDT reload value Table 48 Watch Dog Timer Reload High Byte Register WDTH BITS 7 6 5 4 3 2 1 0 FIELD WDTH RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR FF2H R W Read returns the current WDT count value Write sets the desired Reload Value WDTH WDT Reload High Byte PS017610 0404 Watch Dog Timer Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z 77 ZiLOG Middle byte Bits 15 8 of the 24 bit WDT reload value Table 49 Watch Dog Timer Reload Low Byte Register WDTL BITS 7 6 5 4 3 2 1 0 FIELD WDTL RESET 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W ADDR FF3H R W Read returns the current WDT count value Write sets the desired Reload Value WDTL WDT Reload Low Least significant byte LSB Bits 7 0 of the 24 bit WDT reload value PS017610 0404
241. t vector and executing code from the vector address After time out and interrupt generation the Watch Dog Timer counter rolls over to its maximum value of FFFFFH and continues counting The Watch Dog Timer counter is not automatically returned to its Reload Value WDT Interrupt in Stop Mode If configured to generate an interrupt when a time out occurs and the Z8F640x family device is in STOP mode the Watch Dog Timer automatically initiates a STOP Mode Recovery and generates an interrupt request Both the WDT status bit and the STOP bit in the Watch Dog Timer Control register are set to 1 following WDT time out in STOP PS017610 0404 Watch Dog Timer Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 mode Refer to the Reset and Stop Mode Recovery chapter for more information on STOP Mode Recovery If interrupts are enabled following completion of the Stop Mode Recovery the eZ8 CPU responds to the interrupt request by fetching the Watch Dog Timer interrupt vector and executing code from the vector address WDT Reset in Normal Operation If configured to generate a Reset when a time out occurs the Watch Dog Timer forces the Z8F640x family device into the Short Reset state The WDT status bit in the Watch Dog Timer Control register is set to 1 Refer to the Reset and Stop Mode Recovery chapter for more information on Short Reset WDT Reset in Stop Mode If configured to generate a Reset when a time out occurs and the
242. ta register After one bit of address is shifted out by the SDA signal the Transmit interrupt is asserted Software responds by writing the second byte of address into the contents of the re Data register The Controller shifts the rest of the first byte of address and write bit out by the SDA signal The slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL The Controller sets the bit in the Status register The Controller loads the contents of the Shift register with the contents of the PC Data register The Controller shifts the data out by the SDA signal After the first bit has been sent the Transmit interrupt is asserted Software responds by writing the data to be written out to the Control register The PC Controller shifts out the rest of the second byte of slave address by the SDA signal The PC slave sends an acknowledge by pulling the SDA signal low during the next high period of SCL The Controller sets the ACK bit in the IC Status register The PC Controller shifts the data out by the SDA signal After the first bit is sent the Transmit interrupt is asserted Software responds by asserting the STOP bit of the Control register The Controller completes transmission of the data on the SDA signal The I C Controller sends the STOP condition to the 12 bus Reading a Transaction with a 7 Bit Address Figure 81 i
243. te Function PxOC Output Control Open Drain PxHDE High Drive Enable PxSMRE STOP Mode Recovery Source Enable Port A H Address Registers The Port A H Address registers select the GPIO Port functionality accessible through the Port A H Control registers The Port A H Address and Control registers combine to pro vide access to all GPIO Port control Table 13 Table 13 Port A H GPIO Address Registers Px ADDR BITS 7 6 5 4 3 2 1 0 FIELD PADDR 7 0 RESET 00H R W R W ADDR FDOH FD4H FD8H FDCH FE4H FE8H FECH PS017610 0404 General Purpose I O Z8F640x Z8F480x Z8F320x Z8F240x Z8F 160x Z8 Encore Zi 211 08 PADDR 7 0 Port Address The Port Address selects one of the sub registers accessible through the Port Control reg ister PADDR 7 0 Port Control sub register accessible using the Port A H Control Registers 00H No function Provides some protection against accidental Port reconfiguration 01H Data Direction 02H Alternate Function 03H Output Control Open Drain 04H High Drive Enable 05H Stop Mode Recovery Source Enable 06H FFH No function Port A H Control Registers The Port A H Control registers set the GPIO port operation The value in the correspond ing Port A H Address register determines the control sub registers accessible using the Port A H Control register Table 14 Table 14 Port A H Control Registers
244. ter 128 DMA_ADC control register 130 DMA_ADC operation 123 end address low byte register 128 I O address register 125 operation 122 start current address low byte register 127 status register 131 STAT register 131 DMAACTL register 130 DMAXxCTL register 124 DMAXxEND register 128 DMAXH register 126 DMAXI O address DMAxIO 126 DMAXIO register 126 DMAXxSTART register 128 document number description 215 dst 185 E EI 189 electrical characteristics 167 ADC 174 flash memory and timing 173 GPIO input data sample timing 176 watch dog timer 174 enable interrupt 189 ER 184 Preliminary Index extended addressing register 184 external pin reset 29 eZ8 CPU features 3 eZ8 CPU instruction classes 187 eZ8 CPU instruction notation 183 eZ8 CPU instruction set 182 eZ8 CPU instruction summary 191 F FCTL register 144 features Z8 Encore first opcode map 204 FLAGS 185 flags register 185 flash controller 4 option bit address space 148 option bit configuration reset 148 program memory address 0000H 149 program memory address 0001H 150 flash memory 138 arrangement 139 byte programming 142 code protection 141 configurations 138 control register definitions 144 controller bypass 143 electrical characteristics and timing 173 flash control register 144 flash option bits 142 flash status register 145 flow chart 140 frequency high and low byte registers 147 mass erase 143 operation 139 operation timing 141 page era
245. ter is overwritten during the Write Memory Read Memory Write Register Read Register Read Memory CRC Step Instruction Stuff Instruction and Execute Instruction commands PS017610 0404 On Chip Debugger 017610 0404 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG DBG lt 03H DBG gt RuntimeCounter 15 8 DBG gt RuntimeCounter 7 0 Write OCD Control Register 04H The Write OCD Control Register command writes the data that follows to the OCDCTL register When the Read Protect Option Bit is enabled the DBGMODE bit OCDCTL 7 can only be set to 1 it cannot be cleared to 0 and the only method of putting the Z8F640x family device back into normal operating mode is to reset the device DBG 04H DBG OCDCTL 7 0 Read OCD Control Register 05H The Read OCD Control Register command reads the value of the OCDCTL register DBG 05H DBG OCDCTL 7 0 Write Program Counter 06H The Write Program Counter command writes the data that follows to the eZ8 CPU s Program Counter PC If the Z8F640x family device is not in Debug mode or if the Read Protect Option Bit is enabled the Program Counter PC values are discarded DBG 06H ProgramCounter 15 8 DBG ProgramCounter 7 0 Read Program Counter 07H The Read Program Counter command reads the value in the eZ8 CPU s Program Counter PC If the Z8F640x family device is not in Debug mode or if the Read Pr
246. ter the supply voltage again exceeds the Power On Reset voltage threshold the Z8F640x family device progresses through a full System Reset sequence as described in the Power On Reset section Following Power On Reset the POR status bit in the Watch Dog Timer Control WDTCTL register is set to 1 Figure 63 illustrates Voltage Brown Out operation Refer to the Electrical Characteristics chapter for the VBO and POR threshold voltages and Vpop Stop mode disables the Voltage Brown Out detector 1 VCC 3 3 VCC 3 3V hc rte prm QUE Voltage Execution Kn Brownout Execution S r WDT Clock Crystal Oscillator E E XOUT Internal RESET signal POR XTAL counter delay counter delay Figure 63 Voltage Brown Out Reset Operation not to scale Watch Dog Timer Reset If the device is in normal or Halt mode the Watch Dog Timer can initiate a System Reset at time out if the WDT RES Option Bit is set to 1 This is the default unprogrammed set ting of the WDT RES Option Bit The wDT status bit in the WDT Control register is set to signify that the reset was initiated by the Watch Dog Timer PS017610 0404 Reset and Stop Mode Recovery Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 29 ZiLOG External Pin Reset The RESET pin has a Schmitt triggered input and an internal pull up Once the RESET pi
247. the Controller to generate an interrupt except when the Controller is shifting in data during the reception of a byte or when shifting an address and the RD bit is set This bit and the interrupt are cleared by writing to the PCD register RDRF Receive Data Register Full This bit is set active high when the Controller is enabled and the C Controller has PS017609 0803 12C Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore received a byte of data When active this bit causes the PC Controller to generate an interrupt This bit is cleared by reading the PC Data register ACK Acknowledge This bit indicates the status of the Acknowledge for the last byte transmitted or received When set this bit indicates that an Acknowledge was received for the last byte transmitted or received 10B 10 Bit Address This bit indicates whether a 10 or 7 bit address is being transmitted After the START bit is set if the five most significant bits of the address are 11110B this bit is set When set it is reset once the first byte of the address has been sent RD Read This bit indicates the direction of transfer of the data It is active high during a read The status of this bit is determined by the least significant bit of the PC Shift register after the START bit is set TAS Transmit Address State This bit is active high while the address is being shifted out of the PC Shift register DSS Data Shift State
248. the LDC and LDCI instructions While the Flash Con troller programs the Flash memory the eZ8 CPU idles but the system clock and on chip peripherals continue to operate To exit programming mode and lock the Flash write any value to the Flash Control register except the Mass Erase or Page Erase commands PS017610 0404 Flash Memory Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 Caution The byte at each address of the Flash memory cannot be programmed any bits written to 0 more than twice before an erase cycle occurs Page Erase The Flash memory can be erased one page 512 bytes at a time Page Erasing the Flash memory sets all bytes in that page to the value FFH The Flash Page Select register identi fies the page to be erased With the Flash Controller unlocked writing the value 95H to the Flash Control register initiates the Page Erase operation While the Flash Controller exe cutes the Page Erase operation the eZ8 CPU idles but the system clock and on chip peripherals continue to operate The eZ8 CPU resumes operation after the Page Erase operation completes If the Page Erase operation is performed through the On Chip Debugger poll the Flash Status register to determine when the Page Erase operation is complete When the Page Erase is complete the Flash Controller returns to its locked state Mass Erase The Flash memory can also be Mass Erased using the Flash Controller Mass Erasing the Flash memo
249. tion places the Z8F640x family device into Halt mode In Halt mode the operating characteristics are e Primary crystal oscillator is enabled and continues to operate e System clock is enabled and continues to operate eZ8 CPU is idle Program counter PC stops incrementing Low Power Modes Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Watch Dog Timer s internal RC oscillator continues to operate If enabled the Watch Dog Timer continues to operate other on chip peripherals continue to operate The eZ8 CPU can be brought out of Halt mode by any of the following operations Interrupt Watch Dog Timer time out interrupt or reset Power on reset Voltage brown out reset External RESET pin assertion To minimize current in Halt mode all GPIO pins which are configured as inputs must be driven to one of the supply rails Vcc or GND 017610 0404 Low Power Modes Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 33 ZiLOG General Purpose I O Overview The Z8F640x family products support a maximum of seven 8 bit ports Ports A G and one 4 bit port Port H for general purpose input output I O operations Each port con tains control and data registers The GPIO control registers are used to determine data direction open drain output drive current and alternate pin functions Each port pin is individually programmable GPIO Port Availability By Device Not all Z8F640x f
250. ts or interrupts the Z8F640x family device when the WDT reaches its terminal count The Watch Dog Timer uses its own dedicated on chip RC oscillator as its clock source The Watch Dog Timer has only two modes of operation on and off Once enabled it always counts and must be refreshed to prevent a time out An enable can be performed by executing the WDT instruction or by setting the WDT AO Option Bit The WDT_AO bit enables the Watch Dog Timer to operate all the time even if a WDT instruction has not been executed The Watch Dog Timer is a 24 bit reloadable downcounter that uses three 8 bit registers in the eZ8 CPU register space to set the reload value The nominal WDT time out period is given by the following equation WDT Time out Period ms WOT Reload value Reload where reload value is the decimal value of the 24 bit value given by WDTU 7 0 WDTH 7 0 WDTL 7 0 and the typical Watch Dog Timer RC oscillator frequency is 50kHz The Watch Dog Timer cannot be refreshed once it reaches 0000021 The WDT Reload Value must not be set to values below 0000048 Table 45 provides PS017610 0404 Watch Dog Timer Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 information on approximate time out delays for the minimum and maximum WDT reload values Table 45 Watch Dog Timer Approximate Time Out Delays Approximate Time Out Delay WDT Reload Value WDT Reload Value with 50kHz typical WDT osci
251. tting IrDA Data 96 Receiving IrDA Data eee ee eee 97 98 Infrared Encoder Decoder Control Register Definitions 98 Serial Peripheral Interface 99 OVERVIEW FC EE 99 Atchit ct re coie reor REPE ET PR UM ETC ni p heroes 99 100 SPI Signals eee ea es Beet 101 SPI Clock Phase and Polarity Control 102 Multi Master Operation 104 Error Detection made ora aaa 105 SPLIntetr pts 2v ecc mE Re wih eed 105 SPI Baud Rate Generator 105 SPI Control Register Definitions 106 SPI Data Register 106 SPI Control Register rien tinia is 107 SPI Status Register eens 108 SPI Mode 2 shee oko DEE 109 SPI Baud Rate High and Low Byte Registers 110 IZC Controller ssc sessie 111 OVERVIEW A EDEN 111 hoch dM PLUR 111 SDA and SCL 51 2 111 re Interrupts OEE eRe Ree 112 Start and Stop Conditions 112 Writing a Transaction with a 7 Bit Address 112 Writing a Transaction with a 10 Bit Address
252. tware responds by setting the STOP bit of the PC Control register A STOP condition is sent to the 2 slave a Transaction with a 10 Bit Address Figure 82 illustrates the receive format for a 10 bit addressed slave The shaded regions indicate data transferred from the 12 Controller to slaves and unshaded regions indicate data transferred from the slaves to the Controller Slave Address W 0 A Slave address A S Slave Address R 1 A A Data A 1st 7 bits 2nd Byte 1st 7 bits Figure 82 Receive Data Format for a 10 Bit Addressed Slave The first seven bits transmitted in the first byte are 11110xXx The two bits are the two most significant bits of the 10 bit address The lowest bit of the first byte transferred is the write signal The data transfer format for a receive operation on a 10 bit addressed slave is as follows 1 2 3 017609 0803 Software writes an address 11110B followed by the two address bits and a 0 write Software asserts the START bit of the Control register The 12 Controller sends the Start condition 12C Controller 017609 0803 09 s gv 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG The Controller loads the Shift register with the contents of the PC Data register After the f
253. upt Control register globally enables and disables interrupts Interrupts are globally enabled by any of the following actions e Execution of an EI Enable Interrupt instruction Execution of an IRET Return from Interrupt instruction e Writing a 1 to the bit in the Interrupt Control register Interrupts are globally disabled by any of the following actions e Execution of a DI Disable Interrupt instruction e eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller e Writing aO to the bit in the Interrupt Control register Reset Interrupt Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Zi 211 08 Execution of a Trap instruction e Illegal instruction trap Interrupt Vectors and Priority The Z8F640x family device interrupt controller supports three levels of interrupt priority Level3 is the highest priority Level 2 is the second highest priority and Level 1 is the lowest priority If all of the interrupts were enabled with identical interrupt priority all as Level 2 interrupts for example then interrupt priority would be assigned from highest to lowest as specified in Table 22 Level 3 interrupts always have higher priority than Level 2 interrupts which in turn always have higher priority than Level 1 interrupts Within each interrupt priority level Level 1 Level 2 or Level 3 priority is assigned as specified in Table 22 Reset Watch Dog
254. us conversion The bit fields in the ADC Control register may be written simultaneously Write to ANAIN 3 0 to select one of the 12 analog input sources Analog to Digital Converter Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG Set CONT to 1 to select continuous conversion Write to VREF to enable or disable the internal voltage reference generator Set CEN to 1 to start the conversions 3 When the first conversion in continuous operation is complete after 5129 system clock cycles plus the 40 cycles for power up if necessary the ADC control logic performs the following operations CEN resets to 0 to indicate the first conversion is complete CEN remains 0 for all subsequent conversions in continuous operation Aninterrupt request is sent to the Interrupt Controller to indicate the first conversion is complete An interrupt request is not sent for subsequent conversions in continuous operation 4 Thereafter the ADC writes a new 10 bit data result to ADCD_H 7 0 ADCD L 7 6 every 256 system clock cycles 5 disable continuous conversion clear the CONT bit in the ADC Control register to 0 DMA Control of the ADC The Direct Memory Access DMA Controller can control operation of the ADC includ ing analog input selection and conversion enable For more information on the DMA and configuring for ADC operations refer to the Direct Memory Access Controller chapter ADC
255. uses 40 additional clock cycles to power up before beginning the 5129 cycle conversion When the conversion is complete the ADC control logic performs the following operations 10 bit data result written to ADCD H 7 0 ADCD_L 7 6 CEN resets to 0 to indicate the conversion is complete Aninterrupt request is sent to the Interrupt Controller If the ADC remains idle for 160 consecutive system clock cycles it is automatically powered down Continuous Conversion When configured for continuous conversion the ADC continuously performs an analog to digital conversion on the selected analog input Each new data value over writes the previous value stored in the ADC Data registers An interrupt is generated only at the end of the first conversion after enabling Caution In Continuous mode users must be aware that ADC updates are limited by the input signal bandwidth of the ADC and the latency of the ADC and its digital filter Step changes at the input are not seen at the next output from the ADC The response of the ADC in all modes is limited by the input signal bandwidth and the latency The steps for setting up the ADC and initiating continuous conversion are as follows 1 017610 0404 Enable the desired analog input by configuring the general purpose I O pins for alternate function This disables the digital input and output driver Write to the ADC Control register to configure the ADC for continuo
256. ved DMAx I O Address Register The DMAx I O Address register contains the low byte of the on chip peripheral address for data transfer The full 12 bit Register File address is given by FH DMAx_IO 7 0 PS017610 0404 Direct Memory Access Controller Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore 2 211 08 When DMA is configured for two byte word transfers the DMAx I O Address register must contain an even numbered address Table 72 DMAx I O Address Register DMAxIO BITS 7 6 5 4 3 2 1 0 FIELD IO RESET X X X X X X X X R W R W R W R W R W R W R W R W R W ADDR FB1H FB9H DMA_IO DMA on chip peripheral control register address This byte sets the low byte of the on chip peripheral control register address on Register File Page FH addresses to FFFH DMAx Address High Nibble Register The DMAx Address High register specifies the upper four bits of address for the Start Current and End Addresses of DMAx Table 73 DMAx Address High Nibble Register DMAxH BITS 7 6 5 4 3 2 1 0 FIELD DMA END H DMA START H RESET x x X X X X X X R W R W R W R W R W R W R W R W R W ADDR FB2H FHAH DMA END H DMAx End Address High Nibble These bits used with the DMAx End Address Low register form a 12 bit End Address The full 12 bit address is given by DMA END H 3 0 DMA_END 7 0 DMA START H DMAx
257. view The Analog to Digital Converter ADC converts an analog input signal to a 10 bit binary number The features of the sigma delta ADC include e 12 analog input sources are multiplexed with general purpose I O ports Interrupt upon conversion complete Internal voltage reference generator Direct Memory Access DMA controller can automatically initiate data conversion and transfer of the data from 1 to 12 of the analog inputs Architecture Figure 83 illustrates the three major functional blocks converter analog multiplexer and voltage reference generator of the ADC The ADC converts an analog input signal to its digital representation The 12 input analog multiplexer selects one of the 12 analog input sources The ADC requires an input reference voltage for the conversion The voltage ref erence for the conversion may be input through the external VREF pin or generated inter nally by the voltage reference generator PS017610 0404 Analog to Digital Converter Z8F640x Z8F480x Z8F320x Z8F240x Z8F160x Z8 Encore Z ZiLOG VREF Internal Voltage Reference Generator Analog Input Multiplexer _ lt 4 ANAO Td ANA1 Analog to Digital E Vids Converter d md ANA4 5 Reference Input ANA7 Lo ANA8 Analog Input __ 9 ANA10 Lo ANA11 Figure 83 Analog to Digital Converter Block Diagram Operation Automatic Power Down If the ADC is idle no conversions in p
258. xCTLO register 89 UxCTLI register 90 UxRXD register 87 UxSTATO register 87 UxSTATI register 89 UxTXD register 86 V vector 184 voltage brown out reset VBR 27 watch dog timer approximate time out delays 72 73 CNTL 28 control register 75 electrical characteristics and timing 174 interrupt in normal operation 73 interrupt in stop mode 73 operation 72 refresh 73 189 reload unlock sequence 74 reload upper high and low registers 76 reset 28 reset in normal operation 74 reset in stop mode 74 time out response 73 WDTCTL register 75 WDTH register 76 WDTL register 77 working register 184 working register pair 184 WTDU register 76 X X 184 XOR 190 XORX 190 Index Z8F640x Z8F480x Z8F320x Z8F240x Z8F 160x Z8 Encore Z 211 08 7 Z8 Encore block diagram 3 features 1 introduction 1 part selection guide 2 PS017610 0404 Preliminary Index

Z8 Encore!™ Microcontrollers with Flash Memory and 10

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Z8 Encore!&trade; Microcontrollers with Flash Memory and 10

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Z8 Encore!™ Microcontrollers with Flash Memory and 10