BlueVD4 Board
Contents
1. 2010 RivieraWaves Page 38 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 RivigraWaves W M J13 35 FPGA2_TEST66 FPGA2 AB2 C1 7 J13 36 FPGA2_TEST67 FPGA2 AB1 C Q1 J13 37 GND J13 38 GND J14 1 GND J14 2 GND J14 3 FPGA2_TEST68 FPGA2 AC14 D Q0 J14 4 FPGA2 TEST69 FPGA2 AC13 D3 7 J14 5 FPGA2 TEST70 FPGA2 AC12 D3 6 J14 6 FPGA2 TEST71 FPGA2 AC10 D3 5 J14 7 FPGA2 TEST72 FPGA2 AC8 D3 4 J14 8 FPGA2 TEST73 FPGA2 AC7 D3 3 J14 9 FPGA2 TEST74 FPGA2 AC5 D3 2 J14 10 FPGA2 TEST75 FPGA2 ACA D3 1 J14 11 FPGA2_TEST76 FPGA2 AC3 D3 0 J14 12 FPGA2 TEST77 FPGA2 AC2 D2 7 J14 13 FPGA2 TEST78 FPGA2 AD11 D2 6 J14 14 FPGA2 TEST79 FPGA2 AD9 D2 5 J14 15 FPGA2 TEST80 FPGA2 AD7 D2 4 J14 16 FPGA2 TEST81 FPGA2 AD6 D2 3 J14 17 FPGA2 TEST82 FPGA2 AD5 D2 2 J14 18 FPGA2 TEST83 FPGA2 AD4 D2 1 J14 19 FPGA2_TEST84 FPGA2 AD2 D2 0 J14 20 FPGA2_TEST85 FPGA2 AD1 D0 0 J14 21 FPGA2 TEST86 FPGA2 AE12 D0 1 J14 22 FPGA2 TEST87 FPGA2 AE11 D0 2 J14 23 FPGA2 TEST88 FPGA2 AE9 D0 3 J14 24 FPGA2 TEST89 FPGA2 AE8 D0 4 J14 25 FPGA2 TEST90 FPGA2 AE6 D0 5 J14 26 FPGA2 TEST91 FPGA2 AE4 D0 6 J14 27 FPGA2 TEST92 FPGA2 AE3 D0 7 J14 28 FPGA2 TEST93 FPGA2 AE2 D1 0 J14 29 FPGA2 TEST94 FPGA2 AE1 D1 1 J14 30 FPGA2 TEST95 FPGA2 AF11 D1 2 J14 31 FPGA2 TEST96 FPGA2 AF9 D12. 1 Overview 1 1 Document overview This document describes the connections and set up for the BlueVD4 board kit consisting of a BlueVD4 board a transformer an application daughter board and an optional RF daughter board for BlueJay TC1 1 2 System pictures The following picture shows the BlueVD4 board in standalone mode 5 n a a a Li L n a Figure 1 1 BlueVD4 board Page 7 of 41 Confidential 2010 RivieraWaves WM Niera Waves Title BlueVD4 Board Document type User Manual V Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 2 BlueVD4 board quick start On the following board diagram the useful connectors and switches are highlighted in order to quickly find them on the actual board The necessary connections are detailed below FPGA21V8 FPGA23V3 3V3 Q 5A daughter board daughter board idm E transformer 2 X BHEHBHH POWER FPGA2 clock test r7 Button l reset Een SRAM Configuration FPGA2 r LEDs SRAM n EB FPGA configuration FPGA2 test FPGA 1 CPLD FPGAI test CONFIG connector HW FLASH JTAG connector FPGAI clock test FLASH osc F u a D E Y H 100 Soft used GAL Digital i ARM UAR Tbe LH ETM7 i Ham FPGAI switch Multilce connector connectors Figure 2 1 BlueVD4 overview 2 1 Power up The power up of the BlueVD4 board is very simple
3. FlashProg interface Figure 3 1 External ARM7S JTAG Figure 3 2 Internal ARM7S JTAG Figure 3 3 Internal and external ARMTS sees Figure 5 1 System reset tenista nane ne verat NEEE Figure 7 1 Future daughter board sesseeeseeeneenneennn Figure 7 2 BlueVD4 Bluetooth System Figure 7 3 USB configuration uessss Figure 7 4 Siw RF module plugged on VDABTDB eeeeenn Figure 7 5 Xemics Semtech RF module plugged on VDABTDB Figure 7 6 Keypad and display mounted for full embedded applications Figure 7 7 BlueJay TC1 RF board mounted on VD4 mother board Figure 7 8 VD4 Bluetooth System esseseeeeeeeeeeennnen nene Figure 7 9 BlueVD4 Bluetooth System Figure 7 10 Aardvark Connector Description c ccsscccssscesssscesssecssseecserecsesecssaecesesaeecsusecsessesesueessseecaeessessesenaeesensaess Confidential 2010 RivieraWaves Page 5 of 41 tM RyigaWaves Title BlueVD4 Board Document type User Manual NX Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 List of Table Table 7 1 Configuration switches iinei a a aai aa aa a a e aa i ia a aaa a Table 7 2 Digital signal Storena a e a i aa a e a i a ii Table 7 3 Digital pin correspondence between BlueVD4 and VD4BT
4. RyigaWaves Title BlueVD4 Board Document type User Manual NX Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 5 System reset The CPLD handles the system reset of the BlueVD4 board The different reset sources are going to the CPLD and the CPLD transmits them to the main components on board Reset sources Y Voltage supervisor reset End of FPGA configuration signal Push Button Reset PCMCIA reset coming from Digital interface if Digital interface is used as PCMCIA NS S S Reset coming from the RF Eagle interface Component resets handled by CPLD Y FPGA1 Y FPGA2 Y HW Flash Y Radio board For the radio board the choice is offered between a reset coming directly from CPLD load R103 and remove R104 or a resent passing through FPGA load R104 and remove R103 Voltage Supervisor Push Button Reset PCMCIA Reset FPGA1 nRST FPGA2 nRST RF Eagle Board j N Multilce ESL ARM Processor SWF_nRST SW Flash Figure 5 1 System reset Confidential 2010 RivieraWaves Page 14 of 41 WM NIe Waves Title BlueVD4 Board Document type User Manual NX Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 6 Switches and LEDs 6 1 Switches An eight lines switch is connected to FPGA1 An ON position means that the line is connected to 3V3 through a 10K resistor An O
5. BlueVD4 Board User Manual BLUEVD4 BRD UM Version 1 01 2010 06 24 RivieraWaves http www rivierawaves com RivieraWaves confidential This document is copyrighted and released under CDA or NDA only Do not copy or distribute without written authorization from RivieraWaves Please check with RivieraWaves that this document is the latest release Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 RivigraWaves W WM Revision history Version Date Revision description Author 1 00 2010 04 01 Initial Release JPL 1 01 2010 06 24 Typos correction in switch explanation table JPL Changes between a version and the previous one is reflected by the addition of change bars like for the line below This line has been modified from previous version Confidential 2010 RivieraWaves Page 2 of 41 tM Niera Waves Title BlueVD4 Board Document type User Manual V Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 Table of contents AMETE Te e a a a aa E Aa AAO EAA sv due E a ASA AEEA S 2 ELET A E A E E A T 3 list of FiUl E si icissss ss ssss ssessesasdecsss assess sasiaiscncsacedsessassdsssssssisensesesdas se sessecsiessseses sacecsesacssdisis ESSE ERA EC SER ass sarase sasssaeaeseani see 5 LiSt OF Table ees
6. Table 7 11shows the power supply signals available in BlueVD4 s J20 connector BlueVD4 VD4 t VD4BJ1DB Digital Interface ve ici E Signal name Pin Vcc 3 3V J20 D19 Vec_2 5V J20 D20 Power Vcc 1 8V ARMS J20 B18 Vio 1 8V J20 819 Vcc 1 2V J20 B20 J20 B17 GND J20 A17 GND J20 A18 GND J20 A19 GND J20 A20 GND Ground GND J20 D17 J20 C17 GND J20 D18 GND J20 C18 GND J20 C19 GND J20 C20 GND TOTAL 16 Table 7 11 Digital power correspondence between BlueVD4 and VD4BJ1DB Confidential 2010 RivieraWaves Page 30 of 41 WM Niera Waves Title BlueVD4 Board Document type User Manual V Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 7 2 4 Partlist The following table summarizes the components used in the VD4BJ1DB Part Number RivieraWaves Stock Description CON MOLC_120 02 S Q LC TBD Male connector 80 pin BlueVD4 CON FW 30 04 LD 210 160 TBD Power supply board connectors CON 8x2 MALE ALTERNE TBD Logic analyzer connector CON 4x1 MALE TBD I Q board connector CON 24x2 MALE ALT 2mm TBD HissFPGA board connector CON 5x2 MALE ALTERNE TBD Aardvark SPI 0 100 2 54mm pitch IDC type connector LTC3543EDCB TBD DC DC converter MAX3392E TBD Level shifter NX2520DA TBD 52MHz quartz BOOST2RF QFN40 Y BlueJay TC1 DEA252450BT_7012D1 TBD Multilayer band pass filter 2
7. Power the board with the correct transformer 3V3 5A to supply the board Y Transformer part reference SB 035AOF 11 3V3 5A from Stontronics Y Jack connector inside outside IMPORTANT Never connect a transformer with higher voltage than 3V3 to supply the BlueVD4 board it will be severely damaged Once the board is powered the FPGA is loaded with the binary stored in the HW Flash At the end of loading the orange LED FPGA configuration becomes on and indicates that the FPGA is correctly configured and ready to start If the LED FPGA configuration is not ON at the power up of the board please refer to chapter 9 2 Confidential 2010 RivieraWaves Page 8 of 41 Title BlueVD4 Board Document type User Manual Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 2 2 Programming HW Flash The necessary tools to program the HW Flash on the board are A Y BLUE POD Small RivieraWaves HW box used to connect a PC to the board FlashProg RivieraWaves Software program running on the PC minimum version 4 6 The following list details how to connect the Blue POD to the BlueVD4 board Y Y Y Check in the BIOS of your computer that the parallel port is set in EPP mode before launching Windows Connect the BLUE POD to the serial link connector called CONFIG connector J7 on Figure 2 1 Connect the other side of the BLUE POD to the parallel port of the PC Please check that no other applicatio
8. WM RivieraWaves Title BlueVD4 Board Document type User Manual Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 3 3 Case of internal and external ARM7S In that case connect the JTAG data of the both ARM7S in serial mode as shown below ARMS Multilce LIII TDO ARM7S amet gi i e ABMS CHIP tno ARM7TDMIS FPGA1 Test Chip Figure 3 3 Internal and external ARM7S Confidential 2010 RivieraWaves Page 12 of 41 tM NIe Waves Title BlueVD4 Board Document type User Manual V Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 4 Xilinx JTAG chain 4 1 FPGA JTAG chain The Xilinx JTAG chain can be used for programming the binary and provides also read back capabilities if used with the correct ISE tool from Xilinx To see the FPGA JTAG chain connect your parallel PC cable and Xilinx box to the JTAG connector J18 on board see Figure 2 1 There is a FGPA JTAG chain only for the FPGA1 or both for FPGA1 and FPGA2 By default the FPGA JTAG chain of the board is configured only for FPGA1 R80 mounted and R81 not mounted To connect FPGA2 to the XILINX JTAG chain just reverse the two resistors R80 not mounted and R81 mounted R81 and R80 are zero Ohm resistors Important FPGA2 is not mounted on the BlueVD4 prototyping board With IMPACT software from Xilinx it is possible to lo
9. 32K HOP_STRB RM_RESET PCM Bus 4 PCM DOUT PCM CLK PCM DIN PCM FSYNC Switch 6 2 for radio selection 4 free Diagnostic 8 8 output ports for logic analyzer TOTAL 71 Table 7 2 Digital signal list Confidential 2010 RivieraWaves Page 21 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 RivigraWaves W A 7 1 2 1 Digital signal correspondence table The following table explains the relation between VD4BTDB and BlueVD4 signals stating the correspondence between signal names in the schematics connector pins and FPGA pins The connector J3 is used to plug VD4BTDB on top of the BlueVD4 motherboard The corresponding bus in the BlueVD4 schematic is FPGA1_DGHT VD4BTDB Digital Interface VD4BTDB Signal nameND4BTDB Connector BlueVD4 FPGA1_DGHT i FPGA1 Pin connector Pin Connector Pin PDIU RCV J1 A12 J3 A12 11 U17 L D1 PDIU OE J1 A13 J3 A13 12 U17 L E4 PDIU_SUSPEND J1 B14 J3 B14 38 U17 L K7 PDIU_USB_BUS USB Philips PDIU_VM J1 A14 J3 A14 13 U17 L E3 Transceiver PDIU VP J1 A15 J3 A15 14 U17 L F2 PDIU VMO J1 A16 J3 A16 15 U17 L F1 PDIU VPO J1 A17 J3 A17 16 U17 L F6 PDIU SPEED J1 A18 J3 A18 17 U17 L F5 FTDI D7 J1 C15 J3 C15 64 U17 P NA FTDI D6 J1 C16 J3 C16 65 U17 P N3 FTDI D5
10. BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 WM RivigraWaves W References Title PCC Extend 125HIB User s manual 1 Reference M200049 03 Version 1 Date December 2001 Source Sycard www sycard com Title FT245BM USB FIFO USB Parallel I C 2 Reference DS245B Version 1 6 Date 2005 Source Future Technology Devices Intl Ltd Title Aardvark I2C SPI Embedded Systems Interface 3 Reference Version V3 20 Date July 15 2005 Source Total Phase Confidential 2010 RivieraWaves Page 41 of 41
11. J1 D17 J3 D17 91 U17 P T9 FTDI DA J1 C17 J3 C17 66 U17 P N2 FTDI D3 J1 D18 J3 D18 92 U17 P T8 FTDI D2 J1 D19 J3 D19 93 U17 P T6 FTDI USB BUS USB FTDI TIR 11 D20 43 020 24 U17 P TS Transceiver FTDI_DO J1 D21 J3 D21 95 U17 P T4 FTDI_nRXF J1 D22 J3 D22 96 U17 P T3 FTDI_nTXE J1 C22 J3 C22 71 U17 P P6 FTDI_nRD J1 D23 J3 D23 97 U17 P T1 FTDILWR J1 C23 J3 C23 72 U17 P P5 FTDI nRESET J1 C24 J3 C24 73 U17 P P4 FTDI_nPWREN J1 C25 J3 C25 74 U17 P P2 KEY V3 J1 A6 J3 A6 5 U17 L B3 KEY_V2 J1 A7 J3 A7 6 U17 L C4 KEY_V1 J1 B8 J3 B8 32 U17 L I7 KEYPAD_BUS Bus for KEY_VO J1 A8 J3 A8 7 U17 L C3 external Keypad KEY_H3 J1 A9 J3 A9 8 U17 L C2 KEY_H2 J1 B10 J3 B10 34 U17 L I5 KEY_H1 J1 A10 J3 A10 9 U17 L D4 KEY_HO J1 A11 J3 A11 10 U17 L D2 LCD_DB7 J1 C1 J3 C1 50 U17 L M11 LCD DB6 J1 D2 J3 D2 76 U17 L R16 LCD DB5 J1 C2 J3 C2 51 U17 L M10 LCD DBA J1 D3 J3 D3 77 U17 L R14 TN LCD DB3 J1 C3 J3 C3 52 U17 L M8 Display LCD_DB2 J1 D4 J3 D4 78 U17 L R12 LCD_DB1 J1 C4 J3 C4 53 U17 L M7 LCD DBO J1 D5 J3 D5 79 U17 L R11 LCD E J1 C5 J3 C5 54 U17 L M6 LCD RW J1 D6 J3 D6 80 U17 L R9 LCD RS J1 D7 J3 D7 81 U17 L R8 HABI GTI BB CLK 1 J1 B5 J3 B5 29 U17 P H4 z ENABLE RM 2 J1 B6 J3 B6 30 U17 P H3 SPI_SS_N J1 B1 J3 B1 25 U17 L G2 RF BT1 2 SPI BUS SPI CLK J1 B2 J3 B2 26 U17 L G1 Confidential 2010 RivieraWaves Page 22 of 41 WM Ryiga
12. J12 29 FPGA2 TEST26 FPGA2 V4 A1 1 J12 30 FPGA2 TEST27 FPGA2 V3 A1 2 J12 31 FPGA2 TEST28 FPGA2 V2 A1 3 J12 32 FPGA2 TEST29 FPGA2 W12 A1 4 J12 33 FPGA2 TEST30 FPGA2 W10 A1 5 J12 34 FPGA2 TEST31 FPGA2 W9 A1 6 J12 35 FPGA2 TEST32 FPGA2 W7 A1 7 J12 36 FPGA2 TEST33 FPGA2 W6 A CLK1 J12 37 GND J12 38 GND J13 1 GND J13 2 GND J13 3 FPGA2 TEST34 FPGA2 W5 C CLK3 J13 4 FPGA2 TEST35 FPGA2 WA C3 7 J13 5 FPGA2_TEST36 FPGA2 W2 C3 6 J13 6 FPGA2_TEST37 FPGA2 W1 C3 5 J13 7 FPGA2 TEST38 FPGA2 Y13 C3 4 J13 8 FPGA2 TEST39 FPGA2 Y11 C3 3 J13 9 FPGA2_TEST40 FPGA2 Y9 C3 2 J13 10 FPGA2 TEST41 FPGA2 Y7 C3 1 J13 11 FPGA2 TEST42 FPGA2 Y6 C3 0 J13 12 FPGA2 TEST43 FPGA2 YA C2 7 J13 13 FPGA2_TEST44 FPGA2 Y3 C2 6 J13 14 FPGA2_TEST45 FPGA2 Y2 C2 5 J13 15 FPGA2 TEST46 FPGA2 Y1 C2 4 J13 16 FPGA2 TEST47 FPGA2 AA14 C2 3 J13 17 FPGA2_TEST48 FPGA2 AA13 C2 2 J13 18 FPGA2 TEST49 FPGA2 AA11 C2 1 J13 19 FPGA2 TEST50 FPGA2 AA10 C2 0 J13 20 FPGA2 TEST51 FPGA2 AA8 C0 0 J13 21 FPGA2 TEST52 FPGA2 AA6 C0 1 J13 22 FPGA2 TEST53 FPGA2 AA5 C0 2 J13 23 FPGA2 TEST54 FPGA2 AA4 C0 3 J13 24 FPGA2 TEST55 FPGA2 AA3 C0 4 J13 25 FPGA2 TEST56 FPGA2 AA1 C0 5 J13 26 FPGA2 TEST57 FPGA2 AB15 C0 6 J13 27 FPGA2 TEST58 FPGA2 AB13 C0 7 J13 28 FPGA2 TEST59 FPGA2 AB11 C1 0 J13 29 FPGA2 TEST60 FPGA2 AB10 C1 1 J13 30 FPGA2 TEST61 FPGA2 AB8 C1 2 J13 31 FPGA2 TEST62 FPGA2 AB7 C1 3 J13 32 FPGA2 TEST63 FPGA2 AB6 C1 4 J13 33 FPGA2_TEST64 FPGA2 AB5 C1 5 J13 34 FPGA2 TEST65 FPGA2 AB3 C1 6 Confidential
13. Reset coming from on board reset button Off Reset coming from BlueJay RF reset button this is the default value when BlueJay RF module is used Table 7 1 Configuration switches Important Switch to On means logical value 0 whereas switch to Off means logical value 1 7 1 1 8 Power supplies The 3V3 voltage present on the BlueVD4 is passed to the VD4BTDB through the daughter board connectors One pin per connector is dedicated to 3V3 voltage The 5V needed by the FT245BM USB chip is coming directly from the USB interface i e from the PC The 5V needed by the display is done with a Linear step up regulator LT1930ES5 from the 3V3 analog present on board Power sources available in BlueVD4 are listed in section 7 1 2 2 7 1 2 Digital signals The following table lists all the digital signals coming from BlueVDA It also explains how these signals are mapped on the connector interface between BlueVD4 and VD4BTDB Digital Interface Number of signal Signal list from FPGA USB Philips Transceiver 8 RCV OE SUSPEND VM VP VMO VPO SPEED USB FTDI 14 D 7 0 RD WR TXE RXF PWREN RESET KEYPAD 8 V 3 0 H 3 0 DISPLAY 11 DB 7 0 E RS RW SKY72313 XE1413 BTRF 2 SYS_CLK_OUT BB_CLK SYNC_FOUND ENABLE_RM SPI Bus for fallback 1 2 Radio 4 SPI_SMD SPI_MSD SPI_SS_N SPI_CLK Control Bus for fallback 1 2 Radio 6 CD_TXEN RX_TX_DATA TX_DATA_UNI BB_
14. Y Audio codec ROLC 130 02 S Q LC Y Male connector 120 pin ANTELEC BAR 15x2 BeTech Semtech board connector HE14 12x2 BeTech SiW board connector FCN 724P016 AU W BeTech LCD Connector HE14 8x1 BeTech KP Connector TOBY STX 3150 5N 577C Y Audio jack 3 5mm Microphone TOBY STX 3150 5N 701C Y Audio jack 3 5mm Speaker PDIUSBP11ADB Y Philips USB 1 1 PHY transceiver MOLEX CON USB TYPE B BeTech USB TYPE B connector FCN 724P016 AU W BeTech Logic Analyzer connector IKNO604000 BeTech Switches Table 7 5 VD4BTDB Part list 7 2 BlueVD4 BlueJay TC1 daughter board optional 7 2 1 Overview This section describes the Daughter Board that enables Confidential 2010 RivieraWaves Page 24 of 41 l RivieraWaves Title BlueVD4 Board Document type User Manual W Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 e The characterization of the Bluejay TC1 device e The BLUEVD4 development board adds Bluetooth RF link functionality by using Blue jay TC1 The code name of this board is VD4BJ1DB The two different roles played by this board are outlined below The Figure 7 7 shows such a daughter board connected to the BlueVD4 board on the right side of the picture s a s a a o a 2 G Figure 7 7 BlueJay TC1 RF board mounted on VD4 mother board 7 2 4 4 RF Device Characterization Board Figure 7 8 depicts the usage of VD4BJ1DB as an RF Characterization vehicle The board can
15. m m u FPGA 1 m L lil Ea ES mosmsamum ose FLASH e HW FLASH CPLD 000 ferot Q0000000 Figure 7 1 Future daughter board 7 1 BlueVD4 application daughter board This section describes the daughter board that enables the BlueVD4 development board to add complete Bluetooth functionality The code name of this board is VD4BTDB Figure 7 2 depicts the envisioned system Confidential 2010 RivieraWaves Page 16 of 41 l RivieraWaves Title BlueVD4 Board Document type User Manual V Relerence in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 BlueVD4 SIW1701 SKY72313 USB KEYPAD DISPLAY Ho PCM Figure 7 2 BlueVD4 Bluetooth System 7 1 1 Features description 7 1 1 1 HCI Support 7 1 1 1 1 FTDI An external FIFO to USB chip will be used to convey the Bluetooth HCI FT245BM Chip 2 from FTDI plus USB Series B connector female are used Integrating the USB chip directly on the VD4BTDB has the advantage to avoid adding another daughter board In this case just an external crystal and passive components are needed 7 1 1 1 2 Integrated USB Device To support the configuration in which a standard USB Device controller would be instantiated within BlueVD4 an USB Series B connector female and Philips Transceiver PDIUSBP11ADB are needed in the VD4BTDB USB standard version i
16. nennen nnne nnne nnn 24 7 2 1 DII MCC 24 7 2 1 1 RF Device Characterization Board 2cci saceiscsssscessessccaideassspaseeasneasacsssseastessacceejaneyeseaarsedsecassassanquaaenouessaaeee sneciecisanse 25 7 2 1 2 Bluetooth System Application Board erret rero eta csvesadsvsdeveganeccutesidaan aE cacao e ev ROT RET Ye E 25 Confidential 2010 RivieraWaves Page 3 of 41 RivieraWaves Title BlueVD4 Board Document type User Manual X Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 7 2 2 REGUIFEMOENKS ERROREM 26 7 2 2 1 BB Interface 26 7 2 2 2 Multiple BB Control Sources 7 2 2 2 1 Multiple BB Control Sources A 7 2 2 2 2 Multiple SPI Sources 527 7 2 2 3 Powering Sources 28 7 2 2 3 1 Characterization 28 7 2 2 3 2 Application BOSE rrt rote th RR bescesdicecesaeaezesesesanecsa ced A ET EXER VETRERE WERE ONERE ORARE EUER ESTE FO eo EY ed 28 7 2 2 4 Spare Arann ice 28 7 2 2 5 Bl eVD4 Requirernents icis nane iie tantae ee ehh ke x RR a YER KE Re EE REN YE FE ERA TIVE XE EEE VR REA RE GR RR A OCEAN ER EXER RAPERE nn 28 7 2 3 Digital sigtals iieri rro nnne iv ei eget ea e e Re Fer EF YER e dines ER ERES CHER Fe P eR PR FERRE EP PEE Ren 29 7 2 3 1 Digital signal corresponding table 29 7 2 3 2 VD4BJ1DB Power correspondence t
17. 10 10 FPGA1 TEST75 FPGA1 AL10 D3 1 Confidential 2010 RivieraWaves Page 36 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 WM RivigraWaves W J10 11 FPGA1_TEST76 FPGA1 AL9 D3 0 J10 12 FPGA1_TEST77 FPGA1 AL8 D2 7 J10 13 FPGA1_TEST78 FPGA1 AL6 D2 6 J10 14 FPGA1_TEST79 FPGA1 AL5 D2 5 J10 15 FPGA1_TEST80 FPGA1 AL4 D2 4 J10 16 FPGA1_TEST81 FPGA1 AL3 D2 3 J10 17 FPGA1_TEST82 FPGA1 AL1 D2 2 J10 18 FPGA1_TEST83 FPGA1 AM21 D2 1 J10 19 FPGA1_TEST84 FPGA1 AM20 D2 0 J10 20 FPGA1_TEST85 FPGA1 AM18 D0 0 J10 21 FPGA1 TEST86 FPGA1 AM17 DO 1 J10 22 FPGA1 TEST87 FPGA1 AM15 DO 2 J10 23 FPGA1_TEST88 FPGA1 AM13 D0 3 J10 24 FPGA1 TEST89 FPGA1 AM11 D0 4 J10 25 FPGA1 TEST90 FPGA1 AM10 D0 5 J10 26 FPGA1 TEST91 FPGA1 AM7 D0 6 J10 27 FPGA1 TEST92 FPGA1 AM6 DO 7 J10 28 FPGA1_TEST93 FPGA1 AM5 D1 0 J10 29 FPGA1_TEST94 FPGA1 AM3 D1 1 J10 30 FPGA1_TEST95 FPGA1 AM2 D1 2 J10 31 FPGA1_TEST96 FPGA1 AM1 D1 3 J10 32 FPGA1_TEST97 FPGA1 AN7 D1 4 J10 33 FPGA1_TEST98 FPGA1 AN5 D1 5 J10 34 FPGA1 TEST99 FPGA1 AN4 D1 6 J10 35 FPGA1_TEST100 FPGA1 AN3 D1 7 J10 36 FPGA1_TEST101 FPGA1 AN2 D CLK2 J10 37 GND J10 38 GND Table 8 2 FPGA1 test connectors 8 22 FPGA2 Connector type AMP 767054 1 Mictor Connector Schematic references J12 amp J13 amp J14 GND connected t
18. 13 J20 D13 60 U17 R AC14 iK J14 D1 J20 D1 48 U17 R AE8 RW J14 D3 J20 D3 50 U17 R AE9 em J14 D5 J20 D5 52 U17 R AC10 Bigejay TCI N SS J14 D7 120 D7 54 U17 R AD11 DATAE S J14 A1 J20 A1 0 U17 R W1 DATAIO 2 J14 A3 J20 A3 2 U17 R AA1 J14 A5 J20 AS 4 U17 R AD1 m J14 A7 J20 A7 6 U17 R AF1 Sai EET eee J14 C14 J20 C14 45 U17 R AAB i J14 D10 J20 D10 57 U17 R AB13 J14 D9 J20 D9 56 U17 R AA13 meet J14 A13 J20 A13 12 U17 R AC2 TRAE DD SP CREE J14 B13 J20 B13 28 U17 R ACA Confidential 2010 RivieraWaves Page 29 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 RivigraWaves W M SP_CTRL_5 J14 A12 J20 A12 11 U17 R AB2 SP CTRL 4 J14 B12 J20 B12 27 U17 R AA4 SP_CTRL_3 J14 A11 J20 A11 10 U17 R Y2 SP CTRL 2 J14 B11 J20 B11 26 U17 R Y4 SP CTRL 1 J14 A10 J20 A10 9 U17 R W2 SP_CTRL_O J14 B10 J20 B10 25 U17 R W4 TOTAL 23 Table 7 10 Digital pin relation between BlueVD4 and VD4BJ1DB Note that the choice of J20 allows for an eventual split of the entire BT System design by using FPGA2 if necessary this device is not mounted on BlueVD4 boards This option can be exercised without any change on VD4BJ1DB by simple modification of the pin assignments in FPGA1 and FPGA2 VD4BJ1DB will then be connected to FPGA2 through J22 connector 7 2 3 2 VD4BJ1DB Power correspondence table
19. 2010 06 24 gacgaqen IOF nux Figure 7 5 Xemics Semtech RF module plugged on VDABTDB 7 1 1 2 1 3 RivieraWaves Bluejay Bluetooth radio To be connected to BlueVD4 through a dedicated daughter board This requirement falls outside the scope of VD4BTDB but is captured here for reference purposes The interface with the Bluejay TC1 radio board is as follows e 14 digital control lines e Male connector MOLC_120_02_S_Q_LC 80 pin e The 32 768KHz clock is taken from the oscillator to be mounted on BlueVD4 7 1 1 3 MMI devices optional Keypad and LCD could be either e Mounted via a ribbon cable as side components e Screwed over the VD4BTDB Figure 7 6 Keypad and display mounted for full embedded applications Confidential 2010 RivieraWaves Page 19 of 41 WM NIe Waves Title BlueVD4 Board Document type User Manual V Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 7 1 1 4 Keypad optional Interface with Keypad is a simple 8x1 connector The 8x1 connector is defined to drive e 4 vertical lines e 4 horizontal lines Keypad features e Matrixed e 16 buttons 7 1 1 5 Display optional As for the keypad there is a display connector on the VD4BTDB to connect a display The display is already a mini board with a complete digital interface e 11 lines 8 data bits plus 3 control lines Select read write Should the option of mounting t
20. 28 J5 76 1018 FPGA1 AV28 J5 77 1039 FPGA1 AT34 J5 78 1019 FPGA1 AV35 J5 79 1040 FPGA1 AT35 J5 80 1020 FPGA1 AT28 J6 1 GND J6 2 GND J6 3 GND J6 4 nCCD2 CPLD N16 J6 5 GND J6 6 GND J6 7 CAD31_1058 FPGA1 AT33 J6 8 CAD30_1041 FPGA1 AW36 J6 9 GND J6 10 GND J6 11 CAD28_1059 FPGA1 AT38 J6 12 CSTSCHG_1042 FPGA1 AP31 J6 13 GND J6 14 GND J6 15 CAUDIO 1060 FPGA1 AN30 J6 16 nCCBE3_ 1043 FPGA1 AU38 Confidential 2010 RivieraWaves Page 33 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 RivigraWaves W tM J6 17 GND J6 18 GND J6 19 nCREQ lO61 FPGA1 AR39 J6 20 nCSERR lO44 FPGA1 AW35 J6 21 GND J6 22 GND J6 23 nCRST CPLD J16 J6 24 CVS2 CPLD L16 J6 25 GND J6 26 GND J6 27 CAD19 1062 FPGA1 AU37 J6 28 CAD17_1045 FPGA1 AU26 J6 29 GND J6 30 GND J6 31 nFRAME 1063 FPGA1 AT39 J6 32 nCTRDY IO46 FPGA1 AP27 J6 33 GND J6 34 GND J6 35 NC J6 36 3V3 J6 37 GND J6 38 GND J6 39 nCDEVSEL lO64 FPGA1 AR38 J6 40 nCSTOP IO47 FPGA1 AP26 J6 41 GND J6 42 GND J6 43 nCBLOCK lO65 FPGA1 AP32 J6 44 NC J6 45 GND J6 46 GND J6 47 CAD16 lO66 FPGA1 AR37 J6 48 CAD15_1048 FPGA1 AV34 J6 49 GND J6 50 GND J6 51 CAD13_1067 FPGA1 AV32 J6 52 CVS1 CPLD K16 J6 53 GN
21. 3 J14 32 FPGA2 TEST97 FPGA2 AF8 D1 4 J14 33 FPGA2 TEST98 FPGA2 AF6 D1 5 J14 34 FPGA2 TEST99 FPGA2 AF5 D1 6 J14 35 FPGA2 TEST100 FPGA2 AFA D1 7 J14 36 FPGA2 TEST101 FPGA2 AF3 D CLK2 J14 37 GND J14 38 GND Confidential 2010 RivieraWaves Table 8 3 FPGA2 test connectors Page 39 of 41 tM RyigaWaves Title BlueVD4 Board Document type User Manual NX Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 9 Problems on board 9 1 Nothing is running Verify you are using the appropriate power supply Y Transformer part reference SB 035AO0F 11 3V3 5A from Stontronics Y Jack connector inside outside Check the following green power LEDs on the upper right corner are ON v 3V3 v 2V5 Y 1V810 Y 1V8 ARM Y 1v2 9 2 FPGA problem Orange LED DONE or FPGA Configuration near CPLD is not ON after power up Y Check that all the power LEDs are ON Y Check that the following filters are presents back side of the board F1 F2 F3 F4 F7 and F8 Y Reload the FPGA binary inside HW FLASH with the BLUE POD and check that there are no errors during loading see Programming HW Flash chapter Y Reload the CPLD via CPLD JTAG chain with appropriate program see CPLD JTAG Chain chapter Y Check the programming oscillator clock is correctly running 8Mhz on test point CCLK near CPLD Confidential 2010 RivieraWaves Page 40 of 41 Title BlueVD4 Board Reference
22. 4 GHz from TDK LFL182G45TC1A108 TBD Low Pass Filter muRata HHM1711D1 TBD 100 50 TDK 2 4GHz Balun SST12LP15A TBD External PA SST 2 4 GHz Table 7 12 VD4BJ1DB Part list Confidential 2010 RivieraWaves Page 31 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 tM RivigraWaves W 8 Connector connections 8 1 Digital interface The following table summarizes the digital interface connections particularly on which pin number of FPGA1 it is connected Y Connector type AMP_104693 8 Y Schematics reference J5 amp J6 The pinout of these two connectors is forecast to be connected to the PCCextend 125A from Sycard to have a PCMCIA interface For more information of PCCextend 125A see 1 GND connected to board ground 3V3 connected to the 3 3V of the board NC not connected FPGA1 XCAVLX200 11FF1513C CPLD XC95288XL 6FG256C Connector pin number Signal name Board connection J5 1 GND J5 2 GND J5 3 NC J5 4 GND J5 5 GND J5 6 GND J5 7 CAD27_1021 FPGA1 AV37 J5 8 nCCLKRUN IOO FPGA1 AR32 J5 9 GND J5 10 GND J5 11 CAD25_1022 FPGA1 AU36 J5 12 CAD29 IO1 FPGA1 AT30 J5 13 GND J5 14 GND J5 15 CAD23 1023 FPGA1 AU33 J5 16 CAD26_102 FPGA1 AT26 J5 17 GND J5 18 GND J5 19 CAD21_1024 FPGA1 AU31 J5 20 CAD24
23. 6 1 IJI e audiant 7 1 1 Document OVerVIQW ciceeseeisi teen ttp en ba eda dacs ERR PER e ra Lea ba ela Ea dans PEE b ni ERR RR RR EE E PRA FREE RR R E GE FREE PERRA devs CER Ra dt 7 1 2 amp iir jenelleidu g c 7 2 BlueVD4 board quick start 2 1 Weg NEE 2 2 Programming HW Flash 3 ARMS chip UT ce M 11 3 4 Case OF External ARMS eror cosas vvsvancauaecncuusvssvan couaneavsievesssreseaecucedacesvansd er ER Pe P XR Pee se eee epa eb 11 32 Case of internalARM ZS sss isis ec core e svancs e Ure Fe CERT OR PETER REI Pu FE TE Re e eee eap eV eel ae door pee died douse E EE 11 3 3 Case of internal and external ARM7S cccsccssccsscccssscessseeeserecsssecscsaecssaeecseaeesesaeeesesaeceaeeseseeesesseseaesesseessaeeess 12 4 XilinxJTAG Chalhn E E so eee T aep kX VE EET Eua a eE LECT TEENS E E TVA C A BK TRY ERR IAREIR OG aneaus EON EERER TE FORTE RUSO 13 7 M EPG AIAG Cl Ali E 13 AD E eeN AE cre rp em 13 5 EIE M TDI ODIT LLL DLILOIIDOIDDDI LIU OEIL SUD 14 6 Switches and LEDS A 15 EL 3SWItCIIBSs cmreEpi t ivo ancatnat tor ederet D EID Pene NEM LU NEMUS LS Cqp LITE IT 15 G2 gt WEDS ELE E 15 7 Daughter Oars isisicssscsscsssssssssessssssiecessscscesssssssasesascecsscsncsesssssssssesseeteaces cisssssseses asessa ceases RIF TES SUR se sesdessceeescscsesss 16 7 1 BlueVD4 ap
24. 6 A3 5 J8 7 FPGA1 TESTA FPGA1 U5 A3 4 J8 8 FPGA1 TEST5 FPGA1 U3 A3 3 J8 9 FPGA1 TEST6 FPGA1 U2 A3 2 J8 10 FPGA1 TEST7 FPGA1 U1 A3 1 J8 11 FPGA1 TEST8 FPGA1 V13 A3 0 J8 12 FPGA1 TEST9 FPGA1 V12 A2 7 J8 13 FPGA1 TEST10 FPGA1 V10 A2 6 J8 14 FPGA1 TEST11 FPGA1 V9 A2 5 J8 15 FPGA1 TEST12 FPGA1 V7 A2 4 J8 16 FPGA1 TEST13 FPGA1 V5 A2 3 J8 17 FPGA1 TEST14 FPGA1 W12 A2 2 J8 18 FPGA1 TEST15 FPGA1 W10 A2 1 J8 19 FPGA1 TEST16 FPGA1 W9 A2 0 J8 20 FPGA1 TEST17 FPGA1 W7 A0 0 J8 21 FPGA1 TEST18 FPGA1 W6 A0 1 J8 22 FPGA1 TEST19 FPGA1 W5 A0 2 J8 23 FPGA1 TEST20 FPGA1 Y13 A0 3 J8 24 FPGA1 TEST21 FPGA1 Y11 A0 4 J8 25 FPGA1 TEST22 FPGA1 Y9 A0 5 J8 26 FPGA1 TEST23 FPGA1 AA11 A0 6 J8 27 FPGA1 TEST24 FPGA1 AA10 A0 7 J8 28 FPGA1 TEST25 FPGA1 AD17 A1 0 J8 29 FPGA1 TEST26 FPGA1 AE18 A1 1 Confidential 2010 RivieraWaves Page 35 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 RivigraWaves W M J8 30 FPGA1_TEST27 FPGA1 AE12 A1 2 J8 31 FPGA1_TEST28 FPGA1 AE11 A1 3 J8 32 FPGA1 TEST29 FPGA1 AF11 A1 4 J8 33 FPGA1 TEST30 FPGA1 AF9 A1 5 J8 34 FPGA1 TEST31 FPGA1 AF8 A1 6 J8 35 FPGA1 TEST32 FPGA1 AG17 A1 7 J8 36 FPGA1 TEST33 FPGA1 AF23 A CLK1 J8 37 GND J8 38 GND J9 1 GND J9 2 GND J
25. 9 3 FPGA1 TEST34 FPGA1 AG10 C CLK3 J9 4 FPGA1 TEST35 FPGA1 AG8 C3 7 J9 5 FPGA1 TEST36 FPGA1 AG7 C3 6 J9 6 FPGA1 TEST37 FPGA1 AG6 C3 5 J9 7 FPGA1 TEST38 FPGA1 AG5 C3 4 J9 8 FPGA1_TEST39 FPGA1 AH17 C3 3 J9 9 FPGA1_TEST40 FPGA1 AJ22 C3 2 J9 10 FPGA1 TEST41 FPGA1 AH13 C3 1 J9 11 FPGA1_TEST42 FPGA1 AH10 C3 0 J9 12 FPGA1_TEST43 FPGA1 AH9 C2 7 J9 13 FPGA1_TEST44 FPGA1 AH7 C2 6 J9 14 FPGA1_TEST45 FPGA1 AH5 C2 5 J9 15 FPGA1_TEST46 FPGA1 AH4 C2 4 J9 16 FPGA1_TEST47 FPGA1 AH3 C2 3 J9 17 FPGA1_TEST48 FPGA1 AH2 C2 2 J9 18 FPGA1_TEST49 FPGA1 AJ16 C2 1 J9 19 FPGA1_TEST50 FPGA1 AJ12 C2 0 J9 20 FPGA1 TEST51 FPGA1 AJ10 C0 0 J9 21 FPGA1 TEST52 FPGA1 AJ9 C0 1 J9 22 FPGA1 TEST53 FPGA1 AJ7 C0 2 J9 23 FPGA1 TEST54 FPGA1 AJ6 C0 3 J9 24 FPGA1 TEST55 FPGA1 AJ5 C0 4 J9 25 FPGA1 TEST56 FPGA1 AJA C0 5 J9 26 FPGA1 TEST57 FPGA1 AJ2 C0 6 J9 27 FPGA1 TEST58 FPGA1 AJ1 C0 7 J9 28 FPGA1 TEST59 FPGA1 AK17 C1 0 J9 29 FPGA1 TEST60 FPGA1 AK16 C1 1 J9 30 FPGA1 TEST61 FPGA1 AK11 C1 2 J9 31 FPGA1 TEST62 FPGA1 AK9 C1 3 J9 32 FPGA1 TEST63 FPGA1 AK8 C1 4 J9 33 FPGA1_TEST64 FPGA1 AK7 C1 5 J9 34 FPGA1 TEST65 FPGA1 AK6 C1 6 J9 35 FPGA1 TEST66 FPGA1 AK4 C1 7 J9 36 FPGA1_TEST67 FPGA1 AK3 C Q1 J9 37 GND J9 38 GND J10 1 GND J10 2 GND J10 3 FPGA1_TEST68 FPGA1 AK2 D Q0 J10 4 FPGA1 TEST69 FPGA1 AK1 D3 7 J10 5 FPGA1 TEST70 FPGA1 AL18 D3 6 J10 6 FPGA1 TEST71 FPGA1 AL16 D3 5 J10 7 FPGA1 TEST72 FPGA1 AL14 D3 4 J10 8 FPGA1 TEST73 FPGA1 AL13 D3 3 J10 9 FPGA1 TEST74 FPGA1 AL11 D3 2 J
26. D J6 54 GND J6 55 CAD10_1068 FPGA1 AW37 J6 56 CAD8_1049 FPGA1 AV25 J6 57 GND J6 58 GND J6 59 NC J6 60 CAD6 IO50 FPGA1 AW32 J6 61 GND J6 62 GND J6 63 CADA IO69 FPGA1 AP37 J6 64 CAD2_1051 FPGA1 AW27 J6 65 GND J6 66 GND J6 67 nCCD1 CPLD M16 J6 68 GND J6 69 1070 FPGA1 AN27 J6 70 1052 FPGA1 AT36 J6 71 1071 FPGA1 AN29 J6 72 1053 FPGA1 AT29 J6 73 1072 FPGA1 AP34 Confidential 2010 RivieraWaves Page 34 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 WM RivigraWaves W J6 74 1054 FPGA1 AN28 J6 75 1073 FPGA1 AP35 J6 76 1055 FPGA1 AR34 J6 77 1074 FPGA1 AW25 J6 78 1056 FPGA1 AR36 J6 79 1075 FPGA1 AW30 J6 80 1057 FPGA1 AU25 8 2 Test Connectors Table 8 1 Digital Port connections The following tables summarize the test connector connections particularly on which pin number of FPGA1 and FPGA2 it is connected 8 2 1 FPGA1 Connector type AMP 767054 1 Mictor Connector Schematic references J8 amp J9 amp J10 GND connected to board ground FPGA1 XCAVLX200 11FF1513C Connector pin number Signal name FPGA1 connection Mictor connection J8 1 GND J8 2 GND J8 3 FPGA1 TESTO FPGA1 U10 A CLKO J8 4 FPGA1 TEST1 FPGA1 U8 A3 7 J8 5 FPGA1 TEST2 FPGA1 U7 A3 6 J8 6 FPGA1 TEST3 FPGA1 U
27. DB cssssssscesssccssecesenseeeseseeseueecsseeesssesseaeessas Table 7 4 Digital power correspondence between BlueVD4 and VDABTDB Table 7 5 VDABTDB Part list eeeeeeee enne nen etn nnn etn Table 7 6 Bluejay TC1 Baseband Interface Table 7 7 Bluejay TC1 Power Lines Table 7 8 BIUEVD4 Require Ment a isacscececscacssavsaceescecvance csvsaceducvccencdcaecavedncvsvan EY HIER EST rd edi YE var eaae YR A ava ee Ee e PA EYE deed ovis Table 7 9 Digital Signal IE EREHETITCU EP Table 7 10 Digital pin relation between BlueVD4 and VD4BJ1DB ssssesesseeereeneeeen nennen enne nnne nnne Table 7 11 Digital power correspondence between BlueVD4 and VD4BJ1DB sessseeeneeennnenenen nenne 30 Table P3 PETI PPS IIR Tad E sacle 31 Table 8 1 Digital Port corinectioris uei screen tree ed PER ARE Uer tn CHE PAPUFATER E S ERU UE T seen E eEEY PA PU ATE EEFEE SEE PEE PY Y EYE ovis 35 Table 8 2 FPGA1 test connectors esesssesseeseeeeeeene entente enne nenne ennt te te tn sitne etes te sense trenes innen esent ennt nennen nene 37 Table 8 3 FPGA2 test COMMECtOIS cccceceeeseeeseceseeceeeeaeeseaeeaeeceessaecaeeseaeeneeceaeecsaeeeeeseaeeceseaceseaesaseaeeseaseaeeseaeeneeesneeseaeees 39 Confidential 2010 RivieraWaves Page 6 of 41 A Document type User Manual QW Title BlueVD4 Board Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24
28. FF position means that the line is connected to ground through a 10K resistor A second four line switch is present on board and the lines are distributed as following Y First two lines 1 amp 2 connected to CPLD Y Third line 3 connected to FPGA2 Y Fourth line 4 allows the choice between ON HW Flash loading with BLUE POD OFF CPLD JTAG chain An ON position on the second switch means directly connected to ground and an OFF position means connected to 3V3 through 10K resistor 6 2 LEDs Each FPGA has eight external LED connections FPGA1 has a first set of three different color LEDs red yellow green followed by five others red LEDs FPGA2 has eight red LEDs Confidential 2010 RivieraWaves Page 15 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 7 Daughter boards For future daughter boards there are five available connectors on the BlueVD4 board Y Two are connected to FPGA1 Y Three are connected to FPGA2 Both small connectors 64 pins are each connected to an entire bank of each FPGA That is to say that all the signals of the bank and consequently of the connector can have the same voltage standard which is on board configurable Four holes are available on the BlueVD4 board to attach the daughter board i BJJ OCG OM MAGS co m m
29. VD4 motherboard All the signals shall be routed to Bluejay TC1 in at least one operating mode as described in section 7 2 2 2 In order to ease logic analyzer captures of the baseband interface all the signals in Table 7 6 will be routed to a 16 pin debug connector 7 2 2 2 Multiple BB Control Sources 7 2 2 2 1 Multiple BB Control Sources A provision for an alternative routing to the BlueVD4 interface shall be provided for the following signals e ENABLE RM e N_RST e SET GAIN STS A control switch shall be provided in order to route both options accordingly Confidential 2010 RivieraWaves Page 26 of 41 RivieraWaves Title BlueVD4 Board Document type User Manual Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 7 2 2 2 2 Multiple SPI Sources The SPI interface of Bluejay TC1 shall be driven by either of the interfaces below A control switch shall be provided in order to route both options accordingly e The baseband interface see section 7 2 2 1 e The Aardvark bus see Figure 7 10 and reference 3 2 Hardware Specifications TOTAL PHASE Aardvark IC SPI Embedded Systems Interface 2 1 Pinouts Connector Specification The ribbon cable connector is a standard 0 100 2 54mm pitch IDC type connector This connector will mate with a standard keyed boxed header Alternatively a split cable is available which connects to the ribbon cable and provides individual
30. Waves Title BlueVD4 Board Document type User Manual NX Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 SPI MSD J1 B3 J3 B3 27 U17 L H7 SPI SMD J1 B4 J3 B4 28 U17 L H5 RM_RESET J1 C11 J3 C11 60 U17 L N10 HOP STRB J1 C12 J3 C12 61 U17 L N8 RF BT1 2 CTRL BUS TX DATA UNI J1 D13 J3 D13 87 U17 L T15 CD_TXEN J1 C13 J3 C13 62 U17 L N7 RX TX DATA J1 D14 J3 D14 88 U17 L T14 BB_32K J1 D15 J3 D15 89 U17 L T13 PCM CLK J1 A19 J3 A19 18 U17 L F4 PCM BUS Digital PCM PCM FSYNC J1 B20 J3 B20 44 U17 L L8 interface PCM DIN J1 A20 J3 A20 19 U17 L F3 PCM DOUT J1 B21 J3 B21 45 U17 L L6 SWITCH1 J1 C7 J3 C7 56 U17 P M3 SWITCH2 J1 D8 J3 D8 82 U17 P R6 SWITCH6 1 Switches for SWITCH3 J1 C8 J3 C8 57 U17 P M2 control SWITCH4 J1 D9 J3 D9 83 U17 P R4 SWITCH5 J1 C9 J3 C9 58 U17 P M1 SWITCH6 J1 D10 J3 D10 84 U17 P R3 DIAGO J1 A21 J3 A21 20 U17 P Y13 DIAG1 J1 B22 J3 B22 46 U17 P L5 DIAG2 J1 A22 J3 A22 21 U17 P Y11 DIAG7 0 Switches for DIAG3 J1 B23 J3 B23 47 U17 P L4 control DIAG4 J1 A23 J3 A23 22 U17 P Y9 DIAG5 J1 B24 J3 B24 48 U17 P L3 DIAG6 J1 A24 J3 A24 23 U17 P AA11 DIAG7 J1 B25 J3 B25 49 U17 P L1 TOTAL 71 Table 7 3 Digital pin correspondence between BlueVD4 and VDABTDB Notes 1 This signal carries the clock from the RF device to the baseband it is an input to BlueVD4 s FPGA1 Note that this clock may or may not be actually used to clock the entire system this decision is made insi
31. _103 FPGA1 AT24 J5 21 GND J5 22 GND J5 23 CAD18_1025 FPGA1 AU27 J5 24 CAD22_104 FPGA1 AU32 J5 25 GND J5 26 GND J5 27 nCIRDY IO26 FPGA1 AP25 J5 28 CAD20_105 FPGA1 AU30 J5 29 GND J5 30 GND J5 31 NC J5 32 nCCBE2 lIO6 FPGA1 AR27 J5 33 GND J5 34 GND J5 35 nCINT IO27 FPGA1 AP24 J5 36 CCLK 107 FPGA1 AH20 Global CLK J5 37 GND J5 38 GND J5 39 NCPERR 1O28 FPGA1 AW24 Confidential 2010 RivieraWaves Page 32 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 RivigraWaves W tM J5 40 3V3 J5 41 GND J5 42 GND J5 43 nCCBE1_1029 FPGA1 AR26 J5 44 nCGNT IO8 FPGA1 AR31 J5 45 GND J5 46 GND J5 47 CAD12 1030 FPGA1 AV30 J5 48 CPAR IO9 FPGA1 AR29 J5 49 GND J5 50 GND J5 51 CAD9_1031 FPGA1 AV27 J5 52 CAD14 1010 FPGA1 AV33 J5 53 GND J5 54 GND J5 55 CAD7 1032 FPGA1 AW34 J5 56 CAD11 lO11 FPGA1 AV29 J5 57 GND J5 58 GND J5 59 CAD3 1033 FPGA1 AW29 J5 60 nCCBEO_1012 FPGA1 AR24 J5 61 GND J5 62 GND J5 63 CADO_1034 FPGA1 AP36 J5 64 CAD5 IO13 FPGA1 AW31 J5 65 GND J5 66 GND J5 67 GND J5 68 CAD1_1014 FPGA1 AW26 J5 69 1035 FPGA1 AU35 J5 70 1015 FPGA1 AR33 J5 71 1036 FPGA1 AT25 J5 72 1016 FPGA1 AP29 J5 73 1037 FPGA1 AU28 J5 74 1017 FPGA1 AT31 J5 75 1038 FPGA1 AR
32. able c ccccscccssssccsseccesseeseneecceseessseecsseeecesseeeseseeecseeeeseeeeaeecseaeeeeseeseseeeseaaeees 30 y EE Cree 31 8 Connector CONNECTIONS 5 ocio a ea naa a e Fa sepas aac aaa sea n4 Fas 344 ch essee dansas adai sabbdaceacencsdes saani Eiaeiee canat acaceccectectases 32 8 1 Digital interface 32 8 2 est COMMECCOMS crre cel sins diewens t open recorre rea bdea disse e ungez sa E AEREA EEE a aa AEEA EEEE 35 8 2 1 FPGA1 8 2 2 FPGA2 9 Problems on DF ie aeeco ica oue ioa daas eed dpa de ga adr antec sion asas uid Usa era ca sed sea i ee daa ded dra da sau abaco dense RE RULES 40 9 1 Nothing is running 9 2 FPGA pFODIGEH rni tte RU EEERECD A REF PRA RAE A RATER EA PIREVRPRR EREASR FEM A EAR ERER ERER RENS References eoo eti eot nei nee nan exa aaa xa Fa cus du oaa aUa vea a Yu CR E NE E essa P CR aa e eE aa Na uyE Vana sa yu rk eH eaa VE Ne DA YN XR RR YeETa cpdas ds aia a PR NE NN HEUS 41 Confidential 2010 RivieraWaves Page 4 of 41 tM RyigaWaves Title BlueVD4 Board Document type User Manual NX Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 List of Figure Figure 1 1 Blu eVD4A DOA Gh uie eese taret e neo breton eee denn pe tne tem puni teedi ud Dente dant vetet ec dean tieacasaeantecenate Figure 2 1 BlueVD4 overview Figure 2 2 BlueVD4 board with BLUE POD Figure 2 3
33. ad the FPGAs directly with their programs without using the CPLD and the HW Flash Note that the bit file must be generated with the necessary option in Xilinx ISE Startup options gt FPGA Start Up Clock gt JTAG The main disadvantage of this kind of FPGA loading is that programs are lost once the power is removed and it is necessary to reload the program inside the FPGA with IMPACT software at each power up Note that the JTAG programming is very slow compared to programming through the CPLD 4 2 CPLD JTAG Chain The CPLD JTAG chain is separate from the FPGA JTAG chain due to different supply voltages 3V3 for CPLD and 2V5 for FPGA Access to the CPLD is done via IMPACT software from XILINX The same connector is used for both the HW Flash loading and CPLD configuration i e CONFIG connector J7 see Figure 2 1 To switch to the CPLD chain instead of HW Flash loading chain put switch 4 of INT1 OFF INT1 switch is called configuration switch on Figure 2 1 The CPLD is already loaded with the RivieraWaves program and has the following features Y Automatically loads program s from the HW Flash to the FPGA s at power up v Transfers the FPGA programs from the PC into the HW Flash component Y Handles system reset of the board For more information about system reset see chapter 5 Y PCMCIA configuration start when digital interface is used as PCMCIA CVS and CCD signals Confidential 2010 RivieraWaves Page 13 of 41 tM
34. be connected to external elements used to perform the characterization process control and data capture interfaces This interface to these elements will be described in section 7 2 2 VQ Capture Board Figure 7 8 VD4 Bluetooth System Power 7 2 1 2 Bluetooth System Application Board Figure 7 2 depicts the complete Bluetooth system that uses VD4BJ1DB as RF link In this case VD4BJ1DB is connected to the BlueVD4 motherboard which is completed with the VD4BTDB see 7 1 to supply the basic peripherals of a Bluetooth system Confidential 2010 RivieraWaves Page 25 of 41 l RivieraWaves Title BlueVD4 Board Document type User Manual W Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 BlueVD4 SIW1701 SKY72313 KEYPAD DISPLAY Figure 7 9 BlueVD4 Bluetooth System 7 2 2 Requirements 7 2 2 1 BB Interface VD4BJ1DB shall present an interface to the baseband section of the system as described in Table 7 6 below Signal Group Pins Description SPI I F 4 SCLK MISO MOSI N_SS Data I F 4 DATAIO 2 0 DATAIO_VAL Power 2 VDD3V3 GND Other Control 3 N_RST ENABLE_RM GAIN_SET_STS System Clock 1 BB_CLK Table 7 6 Bluejay TC1 Baseband Interface The baseband interface shall be routed to a 80 pin MOLC_120_02_S_Q_LC male connector see routing details in section 7 2 3 1 which will be plugged into connector J20 of the
35. de BlueVD4 s FPGA1 The signal names are a BB_CLK SiW b CNX_SYS_CLK_OUT Semtech 2 This signal carries different information depending on the destination RF device This signal is an output of BlueVD4 s FPGA1 where the selection of the actual signal source is carried out a ENABLE_RM SiW RF Power down indication from baseband b SYNC_DET Semtech Baseband signal telling RF device that packet synchronization has been achieved 7 1 2 2 Power correspondence table Table 7 4 shows the power supply signals available in BlueVD4 s J3 connector Confidential 2010 RivieraWaves Page 23 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 WM RivigraWaves W 7 1 3 Part list BlueVD4 VD4BTDB Digital Interface i ss 1 Signal name connector Pin J3 B27 Power Vcc 3 3V J3 D27 Vcc 3 3V J3 A1 GND J3 A2 GND J3 A3 GND J3 B26 GND J3 A26 GND J3 A27 Ground GND J3 D26 GND J3 C26 GND J3 C27 GND J3 C28 GND J3 C29 GND J3 C30 GND TOTAL 13 Table 7 4 Digital power correspondence between BlueVD4 and VD4BTDB The following table summarizes the components used in the VD4BTDB Part Number RivieraWaves Stock Description LT1930ES5 Y Step up regulator for LCD FT245BM BeTech FTDI UART 2 USB I F Chip MC145483DW
36. he LCD above VD4BTDB be retained the potentiometer used to tune it shall not be covered allowing easy access to the rotating wiper 7 1 1 6 PCM A PCM interface is available on the BCARDDB with a PCM codec and Jack connectors This interface allows a user to connect a headset PCM Codec MC145483 from Motorola Audio jacks two 3 5mm 3 PTS audio jacks green for speaker pink for microphone PC color convention To ensure structural solidity the audio jacks need to be mounted through the PCB not just surface soldered 7 1 1 7 Configuration capabilities The configuration switch INT1 allows e Selecting the radio interface e Selecting the way of connecting to the host system UART or FTDI e Selecting how is routed the PCM output from the FPGA e Selecting the source of the main reset The Table 7 1 describes the configurations available Confidential 2010 RivieraWaves Page 20 of 41 WM RyigaWaves Title BlueVD4 Board Document type User Manual NX Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 Switch Value Action 1 On Select UART to support HCI Off Select FTDI to support HCI this is the default value 2 On Select PCM routed to audio codec Off Select PCM routed to dedicated connector this is the default value 3 4 5 On On On RADIO_CONF Select the connected RF chip Off On On On On On SiW Off On On XE1314 On Off On BJ On Off On TC1 6 On
37. leads for each pin Orientation The ribbon cable pin order follows the standard convention The red line indicates the first position When looking at your Aardvark adapter in the upright position figure 5 pin 1 is in the top left corner and pin 10 is in the bottom right corner Figure 5 The Aardvark I2C SPI Host Adapter in the upright position Pin 1 is located in the upper left corner of the connector and Pin 10 is located in the lower right corner of the connector If you flip your Aardvark adapter over figure 6 such that the text on the serial number label is in the proper upright position the pin order is as shown in the following diagram Figure 6 The Aardvark I2C SPI Host Adapter in the upside down position Pin 1 is located in the lower left corner of the connector and Pin 10 is located in the upper right corner of the connector Order of Leads SCL GND SDA NC 5V MISO NC 5V SCLK MOSI SS GND O1 0 n Soe Or m Figure 7 10 Aardvark Connector Description Confidential 2010 RivieraWaves Page 27 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 7 2 2 3 Powering Sources The powering of VD4BJ1DB takes place in two different modes 7 2 2 3 1 Characterization The following supply lines of Bluejay TC1 shall be made available independently to provide power consumption test p
38. n is using the parallel port at the same time Place switch 4 of INT1 to ON INT1 switch is called configuration switch on Figure 2 1 rassinn 9 Figure 2 2 BlueVD4 board with BLUE POD The final step to program the HW Flash is to launch the FlashProg software Y NS S S NS Power up the board with the correct supply Launch FlashProg on the connected PC Minimum version of FlashProg must be 4 6 Select the FPGA1 tick box please refer to 1 on Figure 2 3 Select the correct Platform WiLDSYSFPGA see 2 on Figure 2 3 Going through select the corresponding HW binary bit file for FPGA1 Refer to 3 on Figure 2 3 FPGA2 field is useless for the BlueVD4 platform as FPGA2 is not mounted Click on the program button At the end of the programming the orange LED FPGA configuration must be on indicating that the FPGA is programmed with the new file stored inside the HW Flash Don t forget the necessary option in Xilinx ISE to generate the bit file Startup options gt FPGA Start Up Clock gt CCLK Confidential 2010 RivieraWaves Page 9 of 41 RivieraWaves Reference in Wireless Title BlueVD4 Board Document type User Manual Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 3 Selectthe 1 Select which oneor i orresponding bit both FPGAto program iieb ogra ga FlashProg 4 7 am Fies Newlogic Fisshf veis ST adi ee ee Prater nfo Flash ifo Fie i
39. nto Plato WidSy sFpoa gt Progam Ces 2 Selectthe correct platform Figure 2 3 FlashProg interface Confidential 2010 RivieraWaves Page 10 of 41 tM RyigaWaves Title BlueVD4 Board Document type User Manual NX Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 3 ARM7S chip JTAG The BlueVD4 features an ARM7TDMI processor directly mounted on the board external ARM7TDMI The user can also synthesize its own ARM7S processor and can integrate it directly in the FPGA internal ARM7S Whatever the type of processor used being internal or external the processor JTAG is accessible through a Multilce connector see Figure 2 1 This JTAG chain provides a serial line to the processor and eases the real time debugging 3 1 Case of external ARM7S To use the external ARM7S JTAG chip connect the ARMS CHIP TDO FPGA input to the ARMS TDO FPGA output ARMS Multilce ARM7TDMIS FPGA1 Test Chip Figure 3 1 External ARM7S JTAG 3 2 Case of internal ARM7S In case of internal ARM7S use only just connect the JTAG lines to the ARM7S block leave unconnected the ARMS CHIP TDO from the external ARM7S ARMS Multilce mammam ARM7S lt ABMS_CHIP TDO ARMZTDMIS FPGA1 Test Chip Figure 3 2 Internal ARM7S JTAG Confidential 2010 RivieraWaves Page 11 of 41
40. o board ground FPGA2 XCAVLX200 11FF1513C Connector pin number Signal name FPGA2 connection Mictor connection J12 1 GND J12 2 GND J12 3 FPGA2 TESTO FPGA2 R6 A CLKO J12 4 FPGA2 TEST1 FPGA2 R4 A3 7 J12 5 FPGA2_TEST2 FPGA2 R3 A3 6 J12 6 FPGA2 TEST3 FPGA2 R2 A3 5 J12 7 FPGA2 TESTA FPGA2 R1 A3 4 J12 8 FPGA2 TESTS FPGA2 T9 A3 3 J12 9 FPGA2 TEST6 FPGA2 T8 A3 2 J12 10 FPGA2 TEST7 FPGA2 T6 A3 1 J12 11 FPGA2 TEST8 FPGA2 T5 A3 0 J12 12 FPGA2 TEST9 FPGA2 T4 A2 7 J12 13 FPGA2_TEST10 FPGA2 T3 A2 6 J12 14 FPGA2 TEST11 FPGA2 T1 A2 5 J12 15 FPGA2 TEST12 FPGA2 U10 A2 4 Confidential 2010 RivieraWaves Page 37 of 41 Title BlueVD4 Board Reference BLUEVD4 BRD UM Document type User Manual Version 1 01 Release Date 2010 06 24 RivigraWaves W M J12 16 FPGA2_TEST13 FPGA2 U8 A2 3 J12 17 FPGA2 TEST14 FPGA2 U7 A2 2 J12 18 FPGA2 TEST15 FPGA2 U6 A2 1 J12 19 FPGA2 TEST16 FPGA2 U5 A2 0 J12 20 FPGA2 TEST17 FPGA2 U3 A0 0 J12 21 FPGA2 TEST18 FPGA2 U2 A0 1 J12 22 FPGA2 TEST19 FPGA2 U1 A0 2 J12 23 FPGA2 TEST20 FPGA2 V13 A0 3 J12 24 FPGA2 TEST21 FPGA2 V12 A0 4 J12 25 FPGA2 TEST22 FPGA2 V10 A0 5 J12 26 FPGA2 TEST23 FPGA2 V9 A0 6 J12 27 FPGA2 TEST24 FPGA2 V7 A0 7 J12 28 FPGA2 TEST25 FPGA2 V5 A1 0
41. oints TC1 Pin Symbol Function 2 AVDD IN PA TX driver voltage supply input 4 AVDD RXTX RX TX block voltage supply decoupling output 12 VDD 3V3 3 3 V supply for RF SW 28 VDD IN DIG Digital block voltage supply input 29 VDD DIG Digital block voltage supply decoupling output 31 AVDD IN REG Analog block voltage supply 2 input 32 AVDD ADDA RX ADC TX DAC voltage supply decoupling output 34 AVDD XO XO block voltage supply decoupling output 37 AVDD XX Optional pin TBD 38 AVDD PLL PLL block voltage supply decoupling output 39 AVDD VCO VCO block voltage supply decoupling output 40 VREF_RFPLL RFPLL reference decoupling Group the power per voltage levels Then decide how to obtain 1 5 1 2 from 3v3 and or 2v5 and or 1v8 also available in BlueVD4 Table 7 7 Bluejay TC1 Power Lines Then decide what method will be used to change from single source tomultiple source grouped tomultiple source pin by pin 7 2 2 3 2 All the power lines described in section 7 2 2 3 1 need to be supplied in this mode as a single interface connected to Application Board the power section of the baseband connector described in sections 7 2 2 1 7 2 3 1 7 2 2 4 Spare Area No spare area for mounting extra components is provided 7 2 2 5 BlueVD4 Requirements The requirements specific to BlueVD4 are detailed in Table 7 8 below Confidential 2010 RivieraWaves aL Rien a
42. plication daughter board sesessseseeeeee eene nnne nennen nnne nnne nnne nnns eere nnns nnns 16 7 1 1 Features 1o d er dolo RTL 17 7 1 1 1 ale SUP DOM e coeds 17 p s E FL ENS o eee 17 7 1 1 1 2 Integrated USB Device 7 1 1 2 Supported radio modules 7 1 1 2 1 Fallback BT1 2 aes 18 pA ei SAGEM 0 rn 18 7 1 1 2 1 2 Semtech XE1413 essent eee Un pne e coed aaedacsnayasapavdadensanayetuccquachvad eat sasha FER S EE EEES 18 7 1 1 2 1 3 RivieraWaves Bluejay Bluetooth radio E we 19 7 1 1 3 MMI devices optional T wi 19 7 1 1 4 Keypad optional ins 20 7 1 1 5 Display Optional x 22 5 1 e corri tnt nra er E N E AR FEV E YEVENEV SE ve BEER STR TUN TR erka viv Caesa vas 0g 20 7 1 1 6 de H M 20 7 1 1 7 Configuration capabilities 20 7 1 1 8 Power supplies dll 7 1 2 Digital signals ro m 2521 7 1 2 1 Digital signal Correspondence table 2 eicit inrita ri pa dann eade aya roba Ch C PAR Ra eR deed a Ea v Ee ERN YR Rega 22 7 1 2 2 Power correspondence tablg coercere teas eo ene sive EY PR E aeaa a TEER AE e YR OS TES ET ER vats REY V TS ERN TUE 23 7 1 3 Eje P A E 24 7 2 BlueVD4 BlueJay TC1 daughter board optional enne
43. s 1 1 In case of the FT245BM being integrated in the VDABTDB the interface to the USB connector should be routed either from the FTDI port or from the Philips transceiver configurable see Table 7 1 Philips Transceiver D amp D USB lines FTDI Transceiver Figure 7 3 USB configuration Confidential 2010 RivieraWaves Page 17 of 41 Title BlueVD4 Board Document type User Manual Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 7 1 1 2 Supported radio modules 7 1 1 2 1 Fallback BT1 2 7 1 1 2 1 1 SiW1701 Interface with the Silicon Wave radio board e 13 digital control lines e 2x12 Male connector kind HE14 e A 32 768KHz oscillator is to be mounted on BlueVD4 The goal is to replace the low power clock from Silicon Wave board not always present depends on the board version Low power clock selection between internal external source is to be performed inside BlueVD4 as per Silicon Wave board version D aaanaaaa OF NM tiu Figure 7 4 Siw RF module plugged on VDABTDB 7 1 1 2 1 2 Semtech XE1413 Interface with Semtech XE1413 e 11 digital control lines e 2x15 Female connector kind HE14 e The low power oscillator of the Semtech radio board is used The local BlueVD4 oscillator can be used as an alternative Confidential 2010 RivieraWaves Page 18 of 41 Title BlueVD4 Board Document type User Manual Reference BLUEVD4 BRD UM Version 1 01 Release Date
44. ves NU WM Niera Waves Title BlueVD4 Board Document type User Manual V Reference in Wireless Reference BLUEVD4 BRD UM Version 1 01 Release Date 2010 06 24 Item Description Connection to BlueVD4 VD4BJ1DB can be connected to either J20 FPGA1 or J22 FPGA2 Table 7 8 BlueVD4 Requirements 7 2 3 Digital signals The following table lists all the digital signals coming from BlueVDA It also explains how these signals are mapped on the connector interface between BlueVD4 and VD4BJ1DB Digital Interface Number of signal Signal list from BlueVD4 Bluejay TC1 15 N RST ENABLE RM BB CLK SCLK MISO MOSI N SS DATAIO 3 0 GAIN SET STS NRST OUT 101 100 Spare Control Lines 8 SP CTRL 7 0 TOTAL 23 Table 7 9 Digital signal list 7 2 3 1 Digital signal corresponding table The following table explains the relation between VD4BJ1DB and BlueVD4 signals stating the correspondence between signal names in the schematics connector pins and FPGA pins The connector J20 is used to plug VD4BJ1DB on top of the BlueVD4 motherboard The corresponding bus in the BlueVD4 schematic is FPGA1 1V8 DGHT FPGA1 1V8 FPGA1 VD4BJ1DB Digital Interface a Nurses lu 1 DGHT i 5 zig N_RST J14 C15 J20 C15 46 U17 R AB8 Recor J14 A15 J20 A15 14 U17 R AE2 ENABLE RM J14 C16 J20 C16 47 U17 R AC8 J14 D12 J20 D12 59 U17 R AA14 BREAK J14 D
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