Craignell User Manual Issue – 1.01
Contents
1. point d ASIC Design Craignell User Manual Issue 1 01 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 Kit Contents You should receive the following items with you Craignell development kit 1 Craignell CR28 CR32 CR36 CR40 Board Purchase Optional Extras The following or eguivalent are necessary to program a Craignell module 1 Prog2 Programming Cable 2 Craignell Programming Adaptor We also have ZIF based module to power a Craignell outside of a target board to allow programming Contact boardsales enterpoint co uk for more details on this item 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 Foreword PLEASE READ THIS ENTIRE MANUAL BEFORE PLUGGING IN OR POWERING UP YOUR CRAIGNELL BOARD PLEASE TAKE SPECIAL NOTE OF THE WARNINGS WITHIN THIS MANUAL Trademarks Coolrunner II Spartan ISE EDK Webpack Xilinx are the registered trademarks of Xilinx Inc San Jose California US Craignell is a trademark of Enterpoint Ltd 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 Introduction Welcome to your Craignell board Craignell is a low cost high performance Spartan M 3E FPGA based module This manual covers Issue2 and later of the Craignell modules If you need information on Issuel the schematics are available at http www enterpoint co uk component replacements craignell html The aim of this manual is to assist in usi2. G3 LOC A9 I IOSTANDARD LVTTL LOC C14 IOSTANDARD LVTTL IOSTANDARD LVTTL 109 IOSTANDARD LVTTL 108 IOSTANDARD LVTTL 107 IOSTANDARD LVTTL 106 IOSTANDARD LVTTL 105 IOSTANDARD LVTTL 104 IOSTANDARD LVTTL 100 IOSTANDARD LVTTL IO1 IOSTANDARD LVTTL 102 IOSTANDARD LVTTL 103 IOSTANDARD LVTTL 1035 I IOSTANDARD LVTTL 1036 IOSTANDARD LVTTL 1037 IOSTANDARD LVTTL 1034 IOSTANDARD LVTTL 1038 I IOSTANDARD LVTTL 1026 IOSTANDARD LVTTL 1033 IOSTANDARD LVTTL 1032 IOSTANDARD LVTTL 1031 IOSTANDARD LVTTL 1030 I IOSTANDARD LVTTL 1028 IOSTANDARD LVTTL 1027 IOSTANDARD LVTTL 1025 I IOSTANDARD LVTTL 1024 IOSTANDARD LVTTL 1023 I IOSTANDARD LVTTL 1020 IOSTANDARD LVTTL 1021 I IOSTANDARD LVTTL 1022 IOSTANDARD LVTTL 1016 IOSTANDARD LVTTL 1017 IOSTANDARD LVTTL 1018 IOSTANDARD LVTTL 1019 IOSTANDARD LVTTL 1015 I IOSTANDARD LVTTL 1014 IOSTANDARD LVTTL 1013 IOSTANDARD LVTTL 1012 IOSTANDARD LVTTL IO11 IOSTANDARD LVTTL 1010 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 CR36 Pinout Constraints NET CLK TNM NET CLK TIMESPEC TS_CLK PERIOD CLK 25 ns HIGH 50 OFFSET IN 3 ns BEFORE CLK OFFSET OUT 8 5 ns AFTER CLK NET CLK LOC M
3. 15 NET PIN31 LOC A13 IOSTANDARD LVTTL 41014 NET PIN32 LOC A10 IOSTANDARD LVTTL 1013 NET PIN33 LOC C9 IJOSTANDARD LVTTL 1012 NET PIN34 LOC G3 IIOSTANDARD LVTTL IO11 NET PIN35 LOC A9 IOSTANDARD LVTTL 1010 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 CR32 Pinout Constraints NET CLK TNM NET CLK TIMESPEC TS_CLK PERIOD CLK 25 ns HIGH 50 OFFSET IN 3 ns BEFORE CLK OFFSET OUT 8 5 ns AFTER CLK NET CLK NET LED_DRIVE NET PINI NET PIN2 NET PIN3 NET PIN4 NET PINS NET PIN6 NET PIN7 NET PIN8 NET PINO NET PIN10 NET PIN11 NET PIN12 NET PIN13 NET PIN14 NET PIN15 NET PIN17 NET PIN18 NET PIN19 NET PIN20 NET PIN21 NET PIN22 NET PIN23 NET PIN24 NET PIN25 NET PIN26 NET PIN27 NET PIN28 NET PIN29 NET PIN30 NET PIN31 LOC M6 IOSTANDARD LVTTL LOC B9 LOC A7 LOC B5 LOC C6 LOC C3 LOC C5 LOC B1 LOC G1 LOC F3 LOC A3 LOC H3 LOC J3 LOC H1 LOC F1 LOC M4 LOC H12 LOC J12 LOC G13 LOC J14 LOC K14 LOC C12 LOC F12 LOC F14 LOC F2 LOC G14 LOC A13 LOC A10 LOC C9 LOC G3 LOC A9 LOC C14 IOSTANDARD LVTTL IOSTANDARD LVTTL 109 IOSTANDARD LVTTL IO8 I IOSTANDARD LVTTL 107 IOSTANDARD LVTTL 106 I IOSTANDARD LVTTL 105 IOSTAND
4. 6 IOSTANDARD LVTTL NET LED DRIVE LOC C14 IOSTANDARD LVTTL NET PINI LOC B9 IOSTANDARD LVTTL 109 NET PIN2 LOC A7 IOSTANDARD LVTTL IO8 NET PIN3 LOC B5 IOSTANDARD LVTTL 107 NET PIN4 LOC C6 IOSTANDARD LVTTL 106 NET PINS LOC C3 IOSTANDARD LVTTL IO5 NET PIN6 LOC C5 IOSTANDARD LVTTL 104 NET PIN7 LOC B1 IOSTANDARD LVTTL 100 NET PIN8 LOC G1 IIOSTANDARD LVTTL IO1 NET PIN9 LOC F3 IOSTANDARD LVTTL 102 NET PIN10 LOC A3 IOSTANDARD LVTTL mO3 NET PIN11 LOC H3 IOSTANDARD LVTTL 1035 NET PIN12 LOC J3 IOSTANDARD LVTTL 1036 NET PIN13 LOC H1 IOSTANDARD LVTTL 1037 NET PIN14 LOC F1 IIOSTANDARD LVTTL 1034 NET PIN15 LOC M4 IOSTANDARD LVTTL 1038 NET PIN16 LOC L3 IOSTANDARD LVTTL 1026 NET PIN17 LOC P4 IOSTANDARD LVTTL 1033 NET PIN19 LOC L14 IOSTANDARD LVTTL 1027 NET PIN20 LOC N14 IOSTANDARD LVTTL 1025 NET PIN21 LOC H12 IOSTANDARD LVTTL 1024 NET PIN22 LOC J12 IOSTANDARD LVTTL 1023 NET PIN23 LOC G13 IOSTANDARD LVTTL sIO20 NET PIN24 LOC J14 IOSTANDARD LVTTL 1021 NET PIN25 LOC K14 IOSTANDARD LVTTL 1022 NET PIN26 LOC C12 IOSTANDARD LVTTL 1016 NET PIN27 LOC F12 IOSTANDARD LVTTL HIO17 NET PIN28 LOC F14 IOSTANDARD LVTTL 1018 NET PIN29 LOC F2 IOSTANDARD LVTTL 1019 NET PIN30 LOC G14 IOSTANDARD LVTTL 410
5. ARD LVTTL 104 IOSTANDARD LVTTL IOO IOSTANDARD LVTTL IO1 IOSTANDARD LVTTL 102 IOSTANDARD LVTTL 103 I IOSTANDARD LVTTL 1035 IOSTANDARD LVTTL 1036 IOSTANDARD LVTTL 1037 IOSTANDARD LVTTL 1034 IOSTANDARD LVTTL 1038 IOSTANDARD LVTTL 1024 IOSTANDARD LVTTL 1023 I IOSTANDARD LVTTL 1020 IOSTANDARD LVTTL 1021 IOSTANDARD LVTTL 1022 IOSTANDARD LVTTL IO16 I IOSTANDARD LVTTL sIO17 I IOSTANDARD LVTTL 1018 IOSTANDARD LVTTL I019 I IOSTANDARD LVTTL sIO15 IOSTANDARD LVTTL 1014 I IOSTANDARD LVTTL 1013 I IOSTANDARD LVTTL HIO12 I IOSTANDARD LVTTL IO11 IOSTANDARD LVTTL 1010 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 CR28 Pinout Constraints NET CLK TNM_NET CLK TIMESPEC TS_CLK PERIOD CLK 25 ns HIGH 50 OFFSET IN 5 ns BEFORE CLK OFFSET OUT 15 ns AFTER CLK NET CLK NET LED_DRIVE NET PIN2 NET PIN3 NET PIN4 NET PINS NET PIN6 NET PIN7 NET PIN8 NET PINO NET PIN10 NET PIN11 NET PIN12 NET PIN13 NET PIN15 NET PIN16 NET PIN17 NET PIN18 NET PIN19 NET PIN20 NET PIN21 NET PIN22 NET PIN23 NET PIN24 NET PIN25 NET PIN26 NET PIN27 LOC M6 IOSTANDARD LVTTL LOC A7 LOC B5 LOC C6 LOC C3 LOC C5 LOC B1 LOC G1 LOC F3 LOC A3 LOC H3 L
6. OC J3 LOC H1 LOC H12 LOC J12 LOC G13 LOC J14 LOC K14 LOC C12 LOC F12 LOC F14 LOC F2 LOC G14 LOC A13 LOC A10 LOC C9 LOC C14 I IOSTANDARD LVTTL IOSTANDARD LVTTL IOSTANDARD LVTTL IOSTANDARD LVTTL IOSTANDARD LVTTL IIOSTANDARD LVTTL IOSTANDARD LVTTL I IOSTANDARD LVTTL IO1 IOSTANDARD LVTTL 102 IOSTANDARD LVTTL 103 IOSTANDARD LVTTL I035 I IOSTANDARD LVTTL 1036 IOSTANDARD LVTTL 1037 108 107 106 105 104 100 IIOSTANDARD LVTTL 1023 IOSTANDARD LVTTL 1020 I IOSTANDARD LVTTL 1021 IOSTANDARD LVTTL 1022 I IOSTANDARD LVTTL 1016 IOSTANDARD LVTTL HIO17 I IOSTANDARD LVTTL 1018 I IOSTANDARD LVTTL 1019 IOSTANDARD LVTTL HIO15 I IOSTANDARD LVTTL 1014 I IOSTANDARD LVTTL 1013 I IOSTANDARD LVTTL I012 I IOSTANDARD LVTTL IO11 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 Medical and Safety Critical Use Craignell boards are not authorised for the use in or use in the design of medical or other safety critical systems without the express written person of the Board of Enterpoint If such use is allowed the said use will be entirely the responsibility of the user Enterpoint Ltd will accept no liability for any failure or defect of the Craignell board or its design when it is used in any medical or safety critical application Wa
7. e signals that connect to Serial Flash and additionally Prog_B When a Prog2 or suitable Xilinx cable is plugged in Prog_B is connected to DGND OV and the SpartanM 3E FPGA is placed into the pre configured state This avoids conflicts on the Serial Flash control and data lines with drive from the programming cable The pinout of the header also 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 allows ISE Impact tool serial flash mode to program the Serial Flash Please note to allow the FPGA to configure you must remove the programming cable from the Serial Flash Programming Header 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 FPGA Craignell supports Spartan M 3E devices in the CP CPG132 package Standard builds of Craignell use commercial grade devices but industrial grade parts can be fitted at extra cost subject to minimum order guantities and charges Currently we are supplying only the XC3S100E 4CPG132C and XC3S500E 4CPG132C FPGAs as standard options The XC3S250E 4CPG132C is also possible LEDS Supplied on Craignell there is I LED driven by the FPGA LEDI has a positive polarity i e 1 on LED2 and LED3 are negative polarity i e O on The LEDS are situated on FPGA IO pins as indicated below LED LED1 FPGA C14 PIN CLOCK Craignell comes fitted with a 40 MHz oscillator This is input on FPGA pin M6 FLASH MEMORY Supplied as standard on Craignell
8. is a 4Mbit ST Microelectronics M25P40 This device is used to configure the Spartan M 3E The remainder of flash memory is available for storing code for PicoBlaze MicroBlaze or other microprocessors A XC3S100E will use 581 344 bits of this memory for configuration The XC3S500E will use 2 270 208 bits for configuration General I O Craignell supports between twenty six and thirty eight 5V tolerant I O depending on which Craignell you purchase 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 CR40 Pinout Constraints NET CLK NET LED DRIVE NET PINI NET PIN2 NET PIN3 NET PIN4 NET PINS NET PIN6 NET PIN7 NET PIN8 NET PINO NET PIN10 NET PIN11 NET PIN12 NET PIN13 NET PIN14 NET PIN15 NET PIN16 NET PIN17 NET PIN18 NET PIN19 NET PIN21 NET PIN22 NET PIN23 NET PIN24 NET PIN25 NET PIN26 NET PIN27 NET PIN28 NET PIN29 NET PIN30 NET PIN31 NET PIN32 NET PIN33 NET PIN34 NET PIN35 NET PIN36 NET PIN37 NET PIN38 NET PIN39 LOC M6 LOC B9 LOC A7 LOC B5 LOC C6 LOC C3 LOC C5 LOC B1 LOC G1 LOC F3 LOC A3 LOC H3 LOC J3 LOC H1 LOC F1 LOC M4 LOC L3 LOC P4 LOC M5 LOC P6 LOC P7 LOC M12 LOC L14 LOC N14 LOC H12 LOC J12 LOC G13 LOC J14 LOC K14 LOC C12 LOC F12 LOC F14 LOC F2 LOC G14 LOC A13 LOC A10 LOC C9 LOC
9. ll For programming and building your design you will need to download a copy of ISE Webpack form Xilinx You can obtain it here http www xilinx com ise logic design prod webpack htm The programming of the FPGA and Serial Flash parts on Craignell are achieved using 2 separate interfaces Both of these interfaces are accessed through a single 2x6 1 27mm header Our Craignell Programming Adaptor which breaks out these interfaces into two standard 2x7 2mm headers for use with out Prog2 cable or Xilinx programming cables The picture below shows their interface locations Please take special note of the orientation and alignment of the Programming adaptor shown in the photograph below PIN1 SPI FLASH Gai MY ann aidd YE S EXA X X X Cr a1gnel 40 The first interface is a standard JTAG port which follows the standard layout for our Prog2 cable and for Xilinx Programming Cables IV and later The Xilinx ISE Impact tool can be used to control programming boundary scan mode ISE Webpack can be downloaded free from Xilinx on their website Direct JTAG programming is volatile and the FPGA will lose its configuration every time the board power is turned off on From sustained use of FPGA design programming the design into the Serial Flash memory is recommended Generation of suitable Serial Flash content files and control of the JTAG chain can be achieved using the ISE Impact The second interface contains th
10. ng the main features of Craignell Should this manual fail to explain a feature sufficiently then our support team can be reached by email on support enterpoint co uk 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 Finding Your Way Around 2 5V 1 2V REGULATORS XC3S 100E S00E FPGA 40MHZ OSCILLATOR PROGRAMMING M2540 SERIAL FLASH Er aa gr t 140 Getting Started Craignell is currently available in 4 pinout sizes 28 pins 32 pins 36 pins and 40 pins Your Craignell normally comes with our LED Flash Test build loaded This application will cause the LED to flash on and off and indicates power is applied the on board oscillator is running and the FPGA has configured from the on board SPI Flash Memory Pin1 of the module is on the back side of the module at the top left of the picture above CR40 Pins count counter clockwise from Pinl1 Some useful links and other information can be obtained from our website here http www enterpoint co uk techitips techitips html 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 Craignell Features Power Inputs and Power Supplies Craignell uses a notional SV input but can operate from 3 5V to 5 5V specification guaranteed but in practise can operate as low as 2 8V and as high as 6V if care in interfacing signal levels is taken An optimised version for 3 3V power supply operation will be available shortly Please contact sales if
11. rranty Craignell comes with a 90 return to base warranty Other specialised warranty programs can be offered to users of multiple Enterpoint products Please contact sales on boardsales enterpoint co uk if you are interested in these types of warranty Support Enterpoint offers support during normal United Kingdom working hours 9 00am to 5 00pm Please examine our Craignell FAO web page and the contents of this manual before raising a support guery We can be contacted as follows Telephone 44 0 1684 585262 Email support enterpoint co uk 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008
12. you are interested in this version or reguire more information The power is supplied to the module on the top right pin 5V facing from the front of the module and most components visible and the bottom left pin OV GND We can supply other variants of power pinning as special builds for component replacements with differing reguirements Input current reguirements will depend on the design loaded into the FPGA on the board the size of the FPGA and I O loading We would normally expect this would be in the range 100 500mA An onboard a Texas Instruments TPS70402 linear regulator produces 1 22V and 2 5V from the input supply voltage The 1 22V is used for the Spartan 3E core voltage and the 2 5V is used for all other devices and for the Vccaux Bank Voltages of Spartan M 3E WARNING THE REGULATORS CAN POTENTIALLY GET VERY HOT IN SOME UNUSUAL CIRCUMSTANCES ALONG WITH THE BOARDS THERMAL RELIEF PLEASE DO NOT TOUCH OR PLACE HIGHLY FLAMABLE MATERIALS NEAR THIS DEVICE WHILST THE CRAIGNELL BOARD IS IN OPERATION 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 Selecting the FPGA Bank VCCIOX voltages Craignell fixes the I O voltages all of FPGA banks to 2 5V However there are pull ups to all the VO pins on the Gull Wing Connectors to the input supply voltage allow the I O to achieve CMOS type levels were these are needed 2008 Enterpoint Ltd Craignell Manual Issue 1 01 25 01 2008 Programming Craigne
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