Wi.232DTS User`s Manual
Contents
1. 8 5 Transmit Wait Timeout regNVTXTO 0x05 reg TXTO 0x50 R W R W R W R W R W R W R W R W D7 D6 D5 D4 D3 D2 D1 DO 7 6 5 4 3 2 1 0 When a byte is received by the UART the module will start a timer that will countdown every millisecond The timer is restarted when each byte is received If the timer reaches zero before the next byte is received from the UART the module begin transmitting the data in the buffer Normally this timeout value should be greater than 0x01 and greater than one byte time at the current UART data rate If the timeout value is set to 0x00 the transmit wait timeout will not operate and a full buffer will be required for transmission When setup this way the data will be sent only when a full MTU has been received through the UART The default setting for this register is 0x10 16ms delay 8 6 Network Group regNVNETGRP 0x06 regNETGRP 0x51 R W RAN RAW RAW RAW RAW RAN RAW B7 B6 B5 B4 B3 B2 Bi BO 7 6 5 4 3 2 1 0 Modules can be grouped into networks Although only modules with the group ID will be able to talk to each other modules in different groups but on the same channel will still coordinate transmissions through the CDMA mechanism Valid values for this register are 0 to 127 The default group setting is 0 8 7 CRC Control regNVUSECRC 0x08 regUSECRC 0x33 R W R W R W R W R W R W R W 87 TB 8 sm 8 8 8 8 Set to 0x01 to enable CRC2. Table 7 Register Summary 9 Using Configuration Registers 9 1 CMD Pin The CMD pin is used to inform the module where incoming UART information should be routed When the CMD pin is high or left floating all incoming UART information is treated as payload data and transferred over the wireless interface If the CMD pin is low the incoming UART data is routed to the command parser for processing Since the module s processor looks at UART data one byte at a time the CMD line must be held low for the entire duration of the command plus a 20us margin for processing Leaving the CMD pin low for additional time for example until the ACK byte is received by your application will not adversely affect the module If RF Wi 232DTS 2003 2005 Radiotronix Inc 20 packets are received while the CMD line is active they are still processed and presented to the module s UART for transmission CMD HA A RxD 5 __ Command Header DxFF ee DIXDOA T Figure 10 Command and CMD Pin Timing 9 2 Command Formatting The Wi 232DTS module contains several volatile and non volatile registers that control its configuration and operation The volatile registers all have a non volatile mirror register that is used to determine the default configuration when power is applied to the module During normal operation the volatile registers are used to control the module Placing the module in the command mode allows these
3. a delay between characters set by regTXTO set in 1mSec increments These registers allow the designer to optimize performance of the module for fixed length and variable length data The module will support streaming data as well To optimize the module for streaming data regUARTMTU should be set to 128 and regTXTO should be set to a value equal to 1 byte time at the current UART data rate If the buffer is full or the timer set by regTXTO expires and the module is in the process of sending the previous packet over the RF link the module will assert CTS high indicating that the host should not send any more data Data sent by the host while CTS is high will be lost When the MAC layer has a packet to send it will use a carrier sense multiple access CSMA protocol to determine if another module is already transmitting If another module is transmitting the module will receive that data before attempting to transmit its data again If during this process the UART receive buffer gets full the CTS line will go high to prevent the host UART from over running the receive buffer The CSMA mechanism introduces a variable delay to the transmission channel This delay is the sum of a random period and a weighted period that is dependent on the number of times that the module has tried and failed to acquire the channel For applications that guarantee that only one module will be transmitting at any given time the CSMA mechanism can be turned off to
4. Wi 232DTS User s Manual U S 902 928MHz ISM Band Version Rev 1 4 1 UU de R A DIOTRONIX fe without aires 905 Messenger Lane Moore OK 73160 405 794 7730 2003 2005 Radiotronix Inc all rights reserved 1 Document Control Created By Engineering Review Marketing Review Approved Engineering Approved Marketing Revision 1 0 Author SJM Steve Montgomery 12 9 03 Date 12 9 2003 Description Document Created 1 2 TRM GWH 5 12 2004 Various corrections including register addresses 1 3 TRM 6 2 2004 Corrected programming omission regarding esc chars 1 3 1 TRM 6 3 2004 Corrected MAC OUI and NVSLPMODE register errors 1 4 0 TRM 6 27 2004 Corrected inconsistencies in register tables Altered encoding algorithm to return size and make resultant string null terminated Corrected error in Pin Description section Added defaults to NV register table Reorganized sections for better readability Added flash and command timing information 1 4 1 TRM 3 15 2005 Corrected error in register summary table regarding MAC address Renamed OUI2 0 MAC2 0 to MAC5 0 Updated sales information Wi 232DTS 2003 2005 Radiotronix Inc 2 Introduction 2 1 Module Overview TRANSMITTER amp ON ANTENNA SWITCH vco Vee NG ad d RECEIVER BASEB
5. 4 mile or more outdoors If the environment is open and the antennas are 8 to 10 feet off of the ground the range could be a mile Indoors this link budget should yield a range of several hundred feet This is a well balanced link budget More than 10dB of the budget is achieved through transmit power which will allow good performance indoors in the presence of multi path while keeping the overall operating current low making the module suitable for primary battery powered applications such as RFID and automated meter reading 8 Module Configuration 8 1 Channel settings reg NVTXCHAN 0x00 reg TXCHAN 0x4B R W RAN RAW RAW RAW RAW RAN RAW RES D6 D5 D4 D3 D2 D1 DO 7 6 5 4 3 2 1 0 reg NVRXCHAN 0x01 regRXCHAN 0x4C R W RAN RAW RAW RAW RAW RAN RAW RES D6 D5 D4 D3 D2 D1 DO 6 5 4 3 2 1 0 The Wi 232DTS supports 32 channels 0 31 in DTS mode and 84 channels 0 83 in low power mode Transmit and receive channels are set in regTXCHAN addr 0x4B and regRXCHAN addr 0x4C respectively Wi 232DTS 2003 2005 Radiotronix Inc 15 When the module is in DTS mode the channel registers are masked so that only the lower 6 bits determine the channel The following equations can be used to calculate transmit center frequency in LP and DTS modes Fc 902 34 chan 3MHz LP Fc 903 0 chan 75MHz DTS All modules in a network must be in the same mode L
6. RECEIVER HARDWARE IN VISE SOFTWARE IN VASE Figure 2 WiSE Block Diagram The Wi 232DTS module has a UART type serial interface and contains special application software to create a transparent UART to antenna wireless solution capable of direct wire replacement in most embedded RS 232 422 485 applications NOTE Although the module is capable of supporting the typical serial communications required by RS 232 RS 422 and RS 485 networks it is not compatible with the electrical interfaces for these types of networks The module has CMOS inputs and outputs and would require an appropriate converter for the particular type of network it is connected to Wi 232DTS 2003 2005 Radiotronix Inc Figure 3 Wi 232DTS Networking Concept The module is designed to interface directly to a host UART Three signals are used to transfer data between the module and the host UART TXD RXD and CTS TXD is the data output from the module RXD is the data input to the module CTS is an output that indicates the status of the module s data interface If CTS is low the module is ready to accept data If CTS is high the module is busy and the host UART should not send any further data Internally the module has a 192 byte buffer for incoming characters from the host UART The module can be programmed to automatically transmit when the buffer reaches a programmed limit set by regUARTMTU The module can also be programmed to transmit based on
7. 4 4 CTS0 MODI 222 CON SKTIX4 ADI 3 3 INDO WI232DTS 2 2 m RXDO GND GND VIN GND ANT CON HDRIX12 CON HDR1X12 GND GND GND C2CK GND Zz TG 66 ci C2 CA T47U6 01 CAPO803 4 TUF 33V I i e GND GND 1 O o o o o o o olo Jo Jo Lo LA Figure 9 Evaluation Module Circuit 7 5 Power Supply Although the Wi 232DTS module is very easy to use care must be given to the design of the power supply circuit lt is important for the power supply to be free of digital noise generated by other parts of the application circuit such as the RS 232 converter Figure 4 shows the schematic for our evaluation module circuit for the Wi 232DTS module It includes an on board power supply and antenna connector This evaluation circuit was used to measure the performance of the Wi 232DTS module and should be used as a reference for Wi 232DTS based designs If noise is a problem it can usually be eliminated by using a dedicated LDO regulator for the module and or by separating the grounds for the module and the other circuits 7 6 UART Interface The UART interface is very simple it is comprised of four CMOS compatible digital lines Wi 232DTS 2003 2005 Radiotronix Inc 13 Line Direction Description CTS Out Clear to send this pin indicates to the host micro when it is ok to send data When CTS is high the host micro should stop sending data to the module until CTS returns to the low state CMD In Com
8. 5 2 VDC Input RF Level 15 dBm Storage Temperature 40 85 C Table 12 Absolute Maximum Ratings 10 2 Detailed Electrical Specifications 10 2 1 AC Specifications RX Parameter Min Typ Max Units Notes Receive frequency US 902 2 927 8 MHz At antenna pin Channels DTS 32 Channels LP Mode 84 Channel spacing DTS Mode 750 kHz Channel spacing LP Mode 300 kHz Receiver sensitivity DTS MODE 100 dBm 152 34 kbit sec Receiver sensitivity DTS MODE 102 dBm 38 4 kbit sec Receiver sensitivity DTS MODE 104 dBm 9 6 kbit sec Receiver sensitivity LP MODE 104 dBm 38 4 kbit sec Receiver sensitivity LP MODE 105 dBm 9 6 kbit sec Input IP3 40 dBm Flo 1MHz and Flo 1 945MHz Input Impedance 50 Ohms No matching required LO Leakage 65 dBm 50 ohm termination at ANT Adjacent channel rejection 48 dBc Fc 650kHz dBc IF Bandwidth DTS Mode 600 KHz IF Bandwidth LP Mode 200 KHz Table 13 AC Specifications Rx Wi 232DTS 2003 2005 Radiotronix Inc 23 10 2 2 AC Specifications TX Parameter Min Typ Max Units Notes Transmit Frequency US 902 2 927 8 MHz Center frequency error 2 3 ppm 915 MHz 25 Frequency Deviation DTS Mode 235 kHz Frequency Deviation LP Mode 50 kHz Maximum Output Power LP 5 0 dBm 915 MHz Mode Into 50 ohm load Maximum Output Power DTS 11 14 dBm 915
9. NetWork MOGE rr aot EAE E RAA bee iaa 17 8 5 Transmit Walt TimeOut csr aaa Ga iden nE N GAYA NG AREA EE E ASE E ate 18 8 6 NetWork Group r o anidar tt ai ete di acta Men dead 18 8 75 GRC CONO hai fa tia ia aut tan ei Mn Oe te Re We aha ee ad 18 8 8 UART minimum transmission UNit oooccccnnnnnncnnnnnoncccnanonnnnnnnannnr nano nn nr nan ran rca 18 8 9 Verbose Mode sil ei enken bakkene cence 19 8 10 CSMA enable uvaner seere Ga Gagah sak a ak a aa a randen ates 19 8 11 Sleep control rasakake eel ei de NG aaa Ga babies Lett anse nih ahve center ede 19 8 12 MAG Address Halen keg lp 19 8 13 Register SUMMA ati tarda 20 9 Using Configuration RegisterS rrrrrrrnnnvnnnnnvnnnnvnnnnnvnnnnnnnnnnvnnnnvennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnr 20 Qos SMP PIN ee ped re en 20 9 2 Command Formatting rrernvrnnnnvnnonrvnnnvrvnnnrnnnnnnnrerrennnnrnnsnnnnrerressnrnesnnnnsenrenrsrresnnnnnsnnenennn 21 9 3 Writing To Registar S asaba ia Da ea A NG NA AAN EE DALE A aan E ANG Wa AH NG naa a BG KE NR 22 9 4 Reading From Registers cccccccccesesececeteeeeceeeseenceeeseeeceeesneeceeesneneeeesnenseeesenneseeesennaes 22 10 Electrical Specifications rnnnnvrnnnvrnnnnvnnnnnnnnnnvnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 23 10 1 Absolute Maximum Ratings sas sak angga ian pe Ka Kana AKATE RE MA KENKEN EKA KE KANA EKER AK NEH AKA KE KANEA KANAAN 23 10 2 Detailed Electrical Specifications sisane ane re
10. avoid this delay The MAC layer prefixes the data with a packet header and postfixes the data with a 16 bit CRC The 16 bit CRC error checking can be disabled to allow the application to do its own error Wi 232DTS 2003 2005 Radiotronix Inc 6 checking Data is encoded using a proprietary algorithm DirectSPREAD to spread the RF energy equally within the transmission bandwidth Modules can operate in groups Each module can be assigned an 8 bit group ID which is used to logically link it to other modules on the same channel All modules on a channel will interoperate regardless of their respective group Ids In other words the CSMA mechanism will prevent collisions of modules on the same channel but belonging to different groups Modules can also operate in two network modes Master Slave and Peer to Peer These modes define a set of communication rules that identifies which modules can talk to any given module In Master Slave mode masters can talk to slaves and other masters slaves can talk to masters but slaves cannot talk to other slaves This mode is sometimes required for applications that are replacing legacy RS 485 networks In peer to peer mode any module can hear any other module In both modes group integrity is enforced When a module transmits a packet all other modules on the same channel will receive the packet check the packet for errors and determine whether the received group ID matches the local group ID I
11. into sleep mode through the command mode In sleep mode the RF section is completely shutdown and the protocol processor is in an idle state Once the module has been placed in the sleep mode it can be awakened by either cycling power which will loose all volatile settings or by sending a power up sequence through the serial port The power up sequence is a combination of four OxFF bytes sent back to back at the data rate for which the module is configured Note When in sleep mode the module will not be able to receive data from other modules Any data sent to the module while it is in sleep mode will be lost If the current draw in sleep mode is too high for a particular application the designer can switch power to the module through a FET to turn off the module when it is not needed If this technique is used the volatile registers will reset to the values in their non volatile mirrors so any changes from the default will have to be reloaded The Wi 232DTS is a very flexible module because of all of the configurable parameters it supports However modules that are not configured in the same way will not be able to communicate reliably causing poor performance or outright failure of the wireless link All modules in a network must have the same mode configuration to ensure interoperability Every Wi 232 module has read only internal registers that contain factory programmed information that includes calibration data and a 48 bit MA
12. mode or 0x00 to disable CRC mode The default CRC mode setting is enabled 8 8 UART minimum transmission unit regNVUARTMTU 0x09 reguARTMTU 0x54 R W RAN RAW RAW RAW RAW RAN RAW B7 B6 B5 B4 B3 B2 B1 BO 7 6 5 4 3 2 1 0 This register determines the UART buffer level that will trigger the transmission of a packet The minimum value is 1 and the maximum value is 128 The default value for this register is 64 which provides a good mix of throughput and latency Wi 232DTS O 2003 2005 Radiotronix Inc 8 9 Verbose mode regNVSHOWVER 0x0A regSHOWVER 0x55 R W R W R W R W R W R W R W R W B7 B6 B5 B4 B3 B2 B1 BO 7 6 5 4 3 2 1 0 Setting this register to 0x00 will suppress the start up message including firmware version that is sent to the UART when the module is reset A value of 0x01 will cause the message to be displayed after reset By default the module start up message will be displayed 8 10 CSMA enable regNVCSMAMODE 0x0B regCSMAMODE 0x56 R W RAN RAW RAW RAW RAW RAN RAW B7 B6 B5 B4 B3 B2 B1 BO 7 6 5 4 3 2 1 0 Carrier sense multiple access CSMA is a best effort delivery system that listens to the channel before transmitting a message If another Wi 232 module is already transmitting when a message is queued the module will wait before sending its payload This helps to eliminate RF message corruption at the
13. registers to be programmed Byte values in excess of 127 0x80 or greater must be changed into a two byte escape sequence of the format OxFE value 128 For example the value 0x83 becomes OxFE 0x03 The following function will prepend a OxFF header and size specifier to a command sequence and create escape sequences as needed It is assumed that src is populated with either the register number to read one byte pass 1 into src len or the register number and value to write two bytes pass 2 into src len It is also assumed that the dest buffer has enough space for the two header characters plus the encoded command and the null terminator int EscapeString char src char src len char dest The following function copies and encodes the first src_len characters from src into dest This encoding is necessary for Wi 232 command formats The resulting string is null terminated The size of this string is the function return value char src idx dest idx Save space for the command header and size bytes dest idx 2 Loop through source string and copy encode _ for src_idx 0 src idx lt src_len src_idx if src src_idx gt 127 dest dest idx OxFE it dest dest idx src src idx amp 0x7F for Add null terminator mmm gt dest dest idx 0 Add command h
14. 3 2005 Radiotronix Inc 14 antenna is used If the transmitter operates under the spread spectrum rules however the transmit power can be increased up to 1W depending on the spread spectrum technique and antennas that are used Wireless Fact Frequency hopping spread spectrum does not effectively combat multipath in the 902 928 MHz band It does combat in channel interference but at the expense of bandwidth power consumption and latency Direct sequence spread spectrum like FHSS does not combat multipath It does do a better job than FHSS at combating in channel interference but at the expensive of occupied bandwidth and power consumption These spread spectrum techniques are generally chosen because the FCC will allow higher output power from a transmitter employing these techniques Recently the FCC rules changed to include a new type of spread spectrum device call digital transmission system DTS This method of spread spectrum has no processing gain but allows lower cost solutions like the Wi 232DTS to transmit with higher output power To calculate the link budget for a wireless link simply add the transmit power the antenna gains and the receiver sensitivity LB Ptx Gtxa SENSrx Grxa For example the link budget for a pair of Wi 232 modules in DTS mode at the maximum data rate and using 3dBi whips antennas would be 11dBm 3dB 100dBm 3dB 117dB A link budget of 117dB should easily yield a range of 1
15. AND DSP CONTROL DATA PROTOCOL CONTROLLER LEGEND HARDWARE IN WISE SOFTWARE IN WISE SERIAL INTERFACE WO INTERFACE Figure 1 Wi 232DTS Block Diagram 2 2 Features True UART to antenna solution 16 bit CRC error checking 152 34kbit sec maximum RF data rate 32 channels in DTS mode 84 channels in low power mode Small size 8 x 935 08 Low power standby and sleep modes PHY and MAC layer protocol built in CSMA medium access control 115dB link budget in DTS mode 2 3 Applications e Direct RS 232 422 485 wire replacement requires external RS 232 to 3V CMOS conversion circuitry e Asset Tracking e Automated Meter Reading Wi 232 APPLICATION WISE MAC WISE PACKET HAL 4 modes allow user to optimize power range Command mode for volatile and non volatile configuration 48 bit unique MAC address 5 volt tolerant I O Under 20 in production quantities 868MHz European version available Industrial Home Automation RFID Wireless Sensors Remote Data Logging Wi 232DTS 2003 2005 Radiotronix Inc 2 3 Table of Contents 1 Document Control 5 sco cits a aa a e a E a aa aa a EE a aa Ga aa a a agak 1 2 MUDA NGUDI eo kN KAE NANA NAE ARGA 2 217 Mod le OVENI We abaikan aba Nana gga SANA pa aaa daga baa A Apa aga Ngak anga bae ng e b aaa dakan aii 2 2 ROO aaa aia keen aii 2 23 SAPpplicalONS aka kesan sa en a AK aa aaa maate a
16. C address that can be used by the host application for higher level connection oriented protocols This MAC address can be read through the command interface 6 2 Operating States The primary active state is the IDLE state When the module is not actively transmitting or receiving data it is in this state While in this state the receiver is enabled and the module is continuously listening for incoming data If the module detects a pre amble and valid start code it will enter the RX_HEADER state ee o FF ER IDLE MODE y 3 TE ET RX HEADER E ax TMEO ER er e ot SG SA Roy pe BAG DAA aren cur er Ser me lt pr oe pa zo a Ag Ng A FE a CRC NN 4 NG a P z ME ji P a ce UART TX S Kar et Figure 4 RX State Machine If the module is in the IDLE state and a byte is received by the UART it will enter the TX WAIT state Wi 232DTS 2003 2005 Radiotronix Inc 8 Figure 5 TX State Machine 6 3 Resetting Module to Factory Defaults It may be necessary to reset the non volatile registers to their factory defaults To reset the module to factory defaults hold the command line low and cycle power to the module The command line must remain low for a minimum of 450ms after the resetting the module Once the command line is released the module s non volatile registers will be reset to factory defaults Wi 232DTS 2003 2005 Radiotronix Inc 9 7 Application Information 7 1 Pin out
17. Deviation 50kHz TX Current 24mA RX Current 20mA RX Bandwidth 200kHz Table 5 LP Mode Parameters 8 3 UART Data Rate reg NVDATARATE 0x03 regDATARATE 0x4E R W RAW R W R W R W R W R W R W RES RES RES RES RES BR2 BR1 BRO 7 6 5 4 3 2 1 0 By default the UART data rate is set to 2 4 kbit second at the factory This data rate can be changed by setting the regDATARATE register Valid settings are Baud Rate B 2400 9600 19200 38400 57600 a ojojojo y o o ololg o lo ol3g 115200 Table 6 Data Rate Register Settings If you lose track of the baud rate setting of the module it will be impossible to program the module You can either try every possible baud rate to discover the setting or force a power on reset with CMD held low to set the baud rate to its default 2 4kbit second 8 4 Network Mode regNVNETMODE 0x04 regNETMODE 0x4F R W RAN RAW RAW RAW RAW RAN RAW D7 D6 D5 D4 D3 D2 D1 DO 7 6 5 4 3 2 1 0 The module supports two networking modes Normal and Slave In normal mode the module can talk to any other module In slave mode the module can talk to normal mode modules but cannot transmit to or receive from other slaves Slave mode is selected by writing 0x00 to this register The default network mode is 0x01 Normal Mode Wi 232DTS O 2003 2005 Radiotronix Inc 17
18. Diagram Figure 6 Pin out diagram 7 2 Pin Description O De ejite Ground 2 No connect reserved 3 No connect reserved Command input active low UART receive input UART transmit output UART clear to send output active low 8 No connect reserved 9 No connect reserved Reserved ISP pin Reserved ISP pin Ground Antenna port 50 ohm Ground Ground Ground Ground Ground VCC 2 7 to 3 6 VDC Table 1 Module Pin Descriptions Legend Signals that are used in this implementation Signals used for in system programming Signals not used in this implementation do not connect Wi 232DTS 2003 2005 Radiotronix Inc 7 3 Mechanical Drawings j 0 93in PE 0 00in 0 46in 0 8in Mp 4 A I My R ig oo i fll M fl Figure 7 Module Mechanical Drawings Wi 232DTS 2003 2005 Radiotronix Inc 11 Copyright 2003 4 All rights reserved ALL DIMENSIONS IN MILS Wi 232DTS 730 170 Radiotronix Inc 260 me tt titi i 770 Figure 8 Wi 232DTS Suggested Footprint Wi 232DTS 2003 2005 Radiotronix Inc 7 4 Example Circuit R2 RESOGI3 IK jPi Im 2 12 Y T m GND A PDI 10 10 DTRI VCC JP3 PD a DES 9 DTRI 1 PD3 8 RTSI 2 PDS 7 7 TXDI 3 PDS 6 6 RXDI sH RSSI 3 3 RISO GND ADO
19. KEN Ag A Ka GAK Na ale 2 3 Table Of Content EE EE ee pean 3 4 Table of Figu Sarica aA ease daa 4 5 Index of Tables rrnsvnnnnnnnvnnnnnnnvennnnnnvnnennnnvnnnnnnnvnnennnnvnnennnnnnnnnnnnnnennnnnnnennnnnnennnnnnnnennnnnneennnnner 4 6 Theory of Operation sanega dawa Yapa aaa ae ines 5 bits General aaa uia araa a aiid ea al aa EN Ta Pa eee da evil 5 6 2 Operating Sales aaa a aa aa NGANGEN A 8 6 3 Resetting Module to Factory Defaulis aaa enan anana anaa aana aana anana a aana anana anaa anana 9 7 Application Information srernsannvnnnnnnnvennnnnnvennnnnnnennnnnnnnennnnnnnennnnnnnnnnnnnnnennnnnnnnnnnnnnennnnnnnnnn 10 fle PIQUE Diagrama o ih Sae NGABA a AA aetna dativ above lal anna els 10 fie Pin DESErptOnuasssvn virket dvd i AE A ee A el es 10 7 3 Mechanical Drawings nurseri aain A E cnn r nano AN de BNN AAK KAEN NA AN Wa EKA a an gi 11 45 Example Circuits asi een lene a med A ee 13 LD Power Supply ins nce ai deena ass eee ciate eae 13 7 6 WART tera ss arana aan a aaa IA AAA ee 13 fal NN 14 7 8 Link budget transmit power and range performance ococccnncccnnnnnnononcnancccnnncnnnnnanannncnnns 14 8 Module Configuration ss rraavnnnnvnnnnvnnnnnvnnnnnnnnnnvnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnr 15 8 1 Channel Settings cc aftenen 15 8 27 Pow r Moderna iii dir SS 16 8201 DTS MOG aa ea dd 16 8 22 Low power Mode aa nhk add ide 16 8 3 UART Data Rate Ais hester din 17 8 4
20. MHz Mode Into 50 ohm load Output Impedance 50 Ohms Carrier phase noise TBD dBc Into 50 ohm load Harmonic Output 50 dBc Into 50 ohm load Table 14 AC Specifications Tx 10 2 3 DC Specifications Parameter Min Typ Max Units Notes Operating Temperature 20 70 C Supply voltage 2 7 3 0 3 6 VDC Operating limits Receive current consumption 20 mA Continuous operation Vdd 3 3VDC Transmit current consumption Output into 50 ohm load LP Mode 5 dBm 28 mA Vdd 3 3VDC DTS Mode 1 dBm 32 mA DTS Mode 2 dBm 39 mA DTS Mode 11 dBm 57 mA Standby current consumption 850 uA Vdd 3 3VDC Sleep current consumption 35 uA Vdd 3 3VDC Vih Logic high level input 0 7 Vcc 5 2 VDC Vil Logic low level input 0 0 3 Vc VDC Voh Logic high level output 2 5 c VDC Vol Logic low level output 0 Vcc VDC A Table 15 DC Specifications Wi 232DTS 2003 2005 Radiotronix Inc 24 10 3 Flash Specifications Non Volatile Registers Parameter Min Typ Max Units Notes Flash Write Duration 16 21 ms Module stalled during write operation Flash Write Cycles 20k 100k Cycles Table 16 Flash Specifications Non Volatile Registers 11 Custom Applications For cost sensitive applications such as wireless sensors and AMR Radiotronix can embed the application software directly into the microcontroller built into the module For more information on this service please contact
21. P or DTS and must have the same transmit and receive channels programmed in order to communicate properly 8 2 Power Mode The transmission and reception modes of the module are determined by the settings of the regPWRMODE register It is important to note that a module configured to operate in LP mode cannot hear another module transmitting in DTS mode or vice versa However a module configured to operate in any of the three DTS modes can hear any other module transmitting in any of the DTS modes provided that they are within range of one another regNVPWRMODE 0x02 regPWRMODE 0x4D R W R W R W R W R W R W R W R W NA NA NA NA NA NA PMI PMO 7 6 5 4 3 2 1 0 PM1 PMO Mode o 10 LP Mode 5dBm power setting typical o 1 DTS Mode 1dBm power setting typical 1 O DTS Mode 2dBm power setting typical DTS Mode 11dBm power setting typical Table 3 Power Mode Register Settings 8 2 1 DTS Mode In DTS mode the module is configured as follows DTS Mode Parameters TX Power 1 2 or 11 dBm Deviation 235kHz TX Current 28 to 57mA RX Current 20mA RX Bandwidth 600kHz Table 4 DTS Mode Parameters 8 2 2 Low power Mode In low power mode the module is configured as follows Wi 232DTS 2003 2005 Radiotronix Inc 16 LP Mode Parameters TX Power 3 5dBm
22. Radiotronix 12 Ordering Information Wi 232DTS modules can be ordered on line 24 7 from Mouser Electronics at www mouser com radiotronix or Future Electronics at www futureelectronics com p n WI 232DTS 13 Contact Us 13 1 Technical Support Radiotronix has built a solid technical support infrastructure so that you can get answers to your questions when you need them Our primary technical support tools are the support forum and knowledge base found on our website We are continuously updating these tools To find the latest information about these technical support tools please visit http Avww radiotronix com support Our technical support engineers are available Mon Fri between 9 30 am and 4 30 pm central standard time The best way to reach a technical support engineer is to send an email by visiting the Support page at http www radiotronix com support E mail support requests are given priority because we can handle them more efficiently that phone support requests For customers that would prefer to talk directly to a support engineer we do offer phone support free of charge All support requests are placed in a queue and returned in the order that they are received 13 2 Sales Support Our sales department can be reached via e mail at sales radiotronix com or by phone at 405 794 7730 Our sales department is available Mon Fri between 8 30 am and 5 00 pm Our modules can be purchased through distribution at Fu
23. e 8 Write Register Command value to be written is less than 128 0KB80 1 0 ranerani 22 Table 9 Write Register Command value to be written is greater than or equal to 128 0x80 22 Table 10 Read Register Command erannvvnnnannvvvnnennvvrnnrrnvvnnrrnavnnnrsnnvnnnssnsnnnnssssnnnnssnsnnnnnssnsnnnneenn 22 Table 11 Read Register Module Response For A Valid Register rurannrrnnnnnnvrnnnnnnnrrnnnennrrnnrennr 22 Table 12 Absolute Maximum RAatiMQS ooooccccnnnnnccnnnnecccnnnocccnnoncnrc cnn nr cnn cnc 23 Table 13 AC Specifications RX ooonoocccnnonoccccnononcncnononcnnnnnonnnnnnnnnnnnnnnnn nn nn naar rn nn naar nr anane nn neen annen 23 Table 14 AC Specifications TX ooooonoccccnononccccononcnnnnnnnnnnnnnonnnnnnno nn nn canon nn eaaa nr n naar rn annn En nn rnnnannnnnns 24 Table 15 DG Specihicatons cai A Ai 24 Table 16 Flash Specifications Non Volatile Registers urrrrrannvnnonvrrnnnrrnnnnvnnnnrnnrrrrennnrnnnnnnener 25 Wi 232DTS O 2003 2005 Radiotronix Inc 4 6 Theory of Operation 6 1 General The Wi 232 module is one of a family of WiSE Wireless Serial Engine modules A WiSE module combines a state of the art DTS FSK data transceiver and a high performance protocol controller to create a complete embedded wireless communications link in a tiny IC style package Wireless Serial Engine WMSE TM TRANSMITTER CONO ANTENNA SWITCH COMBINER bd BASEBAND DSP PROTOCOL CONTROLLER
24. e Registers Name Address Description reg TXCHANNEL 0x4B Transmit channel setting reg RXCHANNEL 0x4C Receive channel setting regPWRMODE 0x4D Operating mode settings regDATARATE 0x4E UART data rate reg NETMODE Ox4F Network mode Normal or Slave reg XTO 0x50 Transmit wait timeout regNETGRP 0x51 Network group ID reguSECRC 0x53 Enable Disable CRC reg JARTMTU 0x54 Minimum transmission unit regSHOWVER 0x55 Enable disable start up message regCSMAMODE 0x56 Enable disable CSMA regSLPMODE 0x58 Power state of module Non volatile Read Only Registers Name Address Description regMAC5 0x22 These registers form the unique 48 bit MAC address regMAC4 0x23 regMAC3 0x24 regMAC2 0x25 regMAC1 0x26 regMACO 0x27 Non volatile Registers Name Address Description Default regNVTXCHANNEL 0x00 Transmit channel setting 16 reg NVRXCHANNEL 0x01 Receive channel setting 16 reg NVPWRMODE 0x02 Operating mode settings 1 dBm DTS mode reg NVDATARATE 0x03 UART data rate 2400bps regNVNETMODE 0x04 Network mode Normal Slave Normal regNVTXTO 0x05 Transmit wait timeout 16ms regNVNETGRP 0x06 Network group ID 0x00 regNVUSECRC 0x08 Enable Disable CRC Enabled regNVUARTMTU 0x09 Minimum transmission unit 64 bytes regNVSHOWVER Ox0A Enable Disable start up message Enabled regNVCSMAMODE 0x0B Enable Disable CSMA Enabled regNVSLPMODE 0x0D Power state of module Awake
25. e module will respond to this command with an ACK 0x06 If an ACK is not received the command should be resent If a write is attempted to a read only or invalid register the module will respond with a NAK 0x15 9 4 Reading From Registers A register read command is constructed by placing an escape character before the register number The following table shows the byte sequence for reading a register Byte 0 Byte 1 Byte 2 Byte 3 Header Size Escape Register 71615 4 3 2 1 0 7 6 5 4 3 2 1 07 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 OxFF 0x02 OxFE O Register Table 10 Read Register Command The module will respond to this command by sending an ACK 0x06 followed by the register number and register value The register value is sent unmodified For example if the register value is 0x83 0x83 is returned after the ACK 0x06 See table below for the format of the response If the register number is invalid it will respond with a NACK 0x15 Byte 0 Byte 1 Byte 2 ACK Register Value 7 6 15 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0x06 0 Register Value Table 11 Read Register Module Response For A Valid Register Wi 232DTS O 2003 2005 Radiotronix Inc 22 10 Electrical Specifications 10 1 Absolute Maximum Ratings Min Max Units Parameter VCC Power Supply 0 3 5 0 VDC Voltage on any pin 0 3
26. eader A nnn noe dest 0 OxFF dest 1 dest idx 2 Return escape string size Aji raina a a a return dest idx Wi 232DTS O 2003 2005 Radiotronix Inc 21 Figure 11 Command Conversion Code 9 3 Writing To Registers Writing to a volatile register is nearly instantaneous Writing to a non volatile register however takes typically 16 ms Because the packet size can vary based on the need for encoding there are two possible packet structures The following tables show the byte sequences for writing a register in each case WARNING Be sure that the module is properly powered and remains powered for the duration of the register write Loss of important configuration information could occur if the unit loses power during a non volatile write cycle Byte 0 Byte 1 Byte 2 Byte 3 Header Size Register Value 7 6 5 4 3 2 1 0 7 6 5 4 3 21110 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 OxFF 0x02 0 Register JO Value Table 8 Write Register Command value to be written is less than 128 0x80 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Header Size Register Escape Value z1615 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 GE Ai E _ Lower 7 bits OxFF 0x03 0 Register OxFE o of Value Table 9 Write Register Command value to be written is greater than or equal to 128 0x80 Th
27. ent As such we strongly encourage all of our customers to use off of the shelf antennas whenever possible 7 8 Link budget transmit power and range performance A link budget is the best figure of merit for comparing wireless solutions and determining how they will perform in the field In general the solution with the best link budget will deliver the best line of sight range performance Improving the link budget by increasing the receiver sensitivity will result in lower power consumption while improving the link budget by increasing the transmit power will result in more robust performance in the presence of an on channel interferer or multi path interference Wireless Fact You will never reduce the performance of a wireless link by increasing the sensitivity It has been proposed that less sensitive receivers will perform better in a noisy environment That simply is not true It is the equivalent of saying that someone who is hard of hearing can hear better in a noisy room than in a quiet room The real solution is to make the talker speak louder to get over the noise in the room The same is true for a wireless link In real world noisy environments increased output power is generally the best way to improve range performance The transmit power on unlicensed devices is regulated by the FCC For transmitters that are not spread spectrum the output power is limited to 0dBm 1mW when a standard 1 4 wave whip Wi 232DTS O 200
28. expense of additional latency Setting this register to 0x01 will enable CSMA Setting this register to 0x00 will disable CSMA By default CSMA is enabled 8 11 Sleep control regNVSLPMODE 0x0D reg SLPMODE 0x58 R W RAN RAW RAW RAW RAW RAN RAW B7 B6 B5 B4 B3 B2 B1 BO 7 6 5 4 3 2 1 0 Setting this register to 0x01 will place the module into sleep mode 0x02 will place the module in standby mode Sleep mode places the module in the lowest power inactive state 35uA and requires approximately 7 8ms to resume transmission or reception once awakened Standby draws 850uA and requires approximately 1 2ms to awaken To wake up the module send four OxFF bytes to the UART in a row or perform a hard reset If four OxFF bytes are used to wake the module the fifth character sent to the UART will be transmitted over the RF link Upon awakening the module will clear the volatile register to 0x00 The default value for this register is 0x00 awake 8 12 MAC Address regMAC5 regMACO 0x22 0x27 N A R R R R R R R R D7 D6 D5 D4 D3 D2 D1 DO 7 6 5 4 3 2 1 0 These registers make a unique 48 bit MAC address These values are factory preset and cannot be altered These address bytes are not used by the module They are provided for customer applications as a unique address Wi 232DTS 2003 2005 Radiotronix Inc 8 13 Register Summary Volatile Read Writ
29. f the packet is error free and the group Ids match the module will decrypt the data if necessary and send the error free data to its host UART for processing The modules only implement the ISO reference network stack up to the MAC layer so they are transparent to link layer addressing schemes Therefore the modules can work with any link layer and higher protocols in existing today Certain features of the module are controlled through programmable registers Registers are access by bringing CMD low When CMD is low all data transfers from the host UART are considered to be register access commands When CMD is high all data transfers from the host UART are considered to be raw data that needs to be transparently transmitted across the wireless link The module maintains two copies of each register one in flash and one in RAM On reset the module loads the RAM registers from the values in the flash registers The module is operated out of the RAM registers Applications that need to change parameters of the module often would simply modify the RAM register By putting default settings in the flash registers the module will always come up in a preconfigured state which is useful for applications that do not have external microcontrollers such as RS 232 adapters The UART interface is capable of operating in full duplex at baud rates from 2 4 to 115 2 kbps The module has six power modes High DTS Medium DTS Low DTS low power standby and
30. mand the host micro will bring this pin low to put the module in command mode Command mode is used to set and read the internal registers that control the operation of the module When CMD is high the module will transparently transfer data to and from other modules on the same channel NOTE If this pin is low when the module comes out of reset the registers will be reset to their factory programmed defaults It is important to ensure that CMD is held high during power up under normal conditions RXD In Receive data input TXD Out Transmit data output Table 2 Wi 232DTS UART Interface Lines 7 7 Antenna The module is designed to work with any 50 ohm antenna including PCB trace antennas We are often asked What is the best antenna to use with your module Actually the selection of an antenna is based on a particular application not the module used As a rule a 1 4 wave whip antenna with a good solid ground plane is the best choice However many embedded applications cannot support an externally mounted antenna If this is the case a PCB antenna must be used The designer can either use an off of the shelf PCB antenna such as the Splatch from Linx Technologies or design a trace antenna There are several good antenna tutorials and references on the Internet and we encourage the designer to use these resources Note Antenna design is difficult and can be impossible without the proper test equipm
31. n 8 Figure 5 TX State Machinerieen iaai a iia iaai dai aidi 9 Figure 7 Pin out diagram E A naea KAT EETA AEE KANG KN AN 10 Figure 8 Module Mechanical Drawings rrernrrnnnnrrnnnnvnnrnvnnnnrrrnnnnvnnrnnennrrrennnrnnnnnnnnennresnnnnnnnnnnnennee 11 Figure 9 Wi 232DTS Suggested Footprint aaa eaaa eaaa eaaa aana eaaa aa aana aana anana nana anana 12 Figure 10 Evaluation Module Circuit aaaeaan eaaa eaaa eaaa ea aaa aana aana nana anana anana naen 13 Figure 11 Command and CMD Pin Timing eaaa een an anane a anaa anaa anaa anaa aana anana aana ran 21 Figure 12 Command Conversion Code sasana anaa e anana aa eaaa eaaa aaa anaa anaa anana ranma 22 5 Index of Tables Table 1 Module Pin Descriptions kk oka ye aa a ab a ek Ngan ba a maag adana ena aa AA Ga ai Ng pana megana Kn 10 Table 2 Wi 232DTS UART Interface Lines aaseaaa sanan nean nana n anan aana anana anana nana aana anaa 14 Table 3 Power Mode Register Settings aaaaaaeaa anana nana anana anana anana anana anaa n aana anana 16 Table 4 DTS Mode Parameters saosna a sa ea eaaa a aana aana aana aana aana aa aana aana an cnn 16 Table 5 LP M de Parameters isvrisnmtigg nn dada 17 Table 6 Data Rate Register Settings saanane aae arana cece eeeeaeeeeeeeecaeeeeaaeseeeeeseeeesaeeseeeseeaeees 17 Table 7 Register Summary syai ana kangg aa AG Nana iin a AG a di tle ea tle dai 20 Tabl
32. nn nrrnnnnnnnnnn narr ann nrcrnrrcr nr 23 10 2 1 AC Specifications RX rerannvenenrrrnnnrnnnnnvnnenrennnrnnnnnvnnnnnrennnrnnannnnnnnvenerrrnsnnnntnnnnesenn 23 10 2 2 AC Specifications TX sasarane rana a nana nana nana nana aana aaa anana nana naen aana anaa n aana 24 10 2 3 DE SpeciticatlONS isaka anaa A ov ANANG aa a a Aga Ng a EN KAN EN NA AGA Ag aa E aa KANG 24 10 2 4 Flash Specifications Non Volatile Registers aa an aranana aana nana aee 25 11 Custom ApplicatiOnS r nnnnnnnnnnvvnnnnvnnnnnvnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnenn 25 12 Ordering InformatiOn ss rnannvnnnnvnnnnvnnnnnvnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 25 13 GontactUs u uuunseu lesertur lia alada 25 13 15 TGGANIGALSUPPOK anaa Ag a TA aab aa aaa NGE eee Ge tana 25 13 25 Sales SUpport anan aaa aa a aga agan a aa an a ce a a Aa nah an an a ga Agi a aa a aaa adan 25 Wi 232DTS O 2003 2005 Radiotronix Inc 3 4 Table of Figures Figure 1 Wi 232DTS Block Diagram sasae eaaa eaaa naen anaa anaa ana anaa aaa aa aan nan aana anana nenen 2 Figure 2 WISE Block Diagram sasae ea aee ae eaaa aaa ana ana ana anana aaa an anana nancs 5 Figure 3 Wi 232DTS Networking Concept anaa anaa aana aana aa aa aaa aaa nana rra 6 Figure 4 RX State Machine asa osse ea ae eran eaaa anana anaa ANANA ANANA ANANA ANAN Nana anana ne
33. sleep The Wi 232DTS module is the first module in the world to take advantage of the digital spread spectrum provision in FCC part 15 rules Under this provision transmitters can operate at a higher output power if the transmission bandwidth is at least 500kHz Through an encoding technique we call DirectSPREAD the Wi 232DTS module is able to operate at 11dBm and meet the requirements of this provision In DTS mode the module s channel bandwidth is set to 600kHz and the transmit power is set to 11dBm In this mode the module can operate on 32 channels and support a maximum RF data rate of 152 34kbit second The receiver sensitivity at the max data rate is 100dBm typical yielding a link budget of 111dB This mode is an excellent alternative to frequency hopping spread spectrum It has very fast synchronization allowing it to operate in a duty cycle mode for extended battery life In low power mode the module s channel bandwidth is set to 200kHz In this mode the module can operate on 84 channels and support a maximum data rate of 38 4 kbit second The receiver sensitivity at the maximum data rate is 105 typical yielding a link budget of 105dB This mode reduces transmit current consumption allowing use with batteries that cannot supply the pulse Wi 232DTS 2003 2005 Radiotronix Inc 7 currents required for DTS mode The range in this mode will be a little more than half of the range in DTS mode The module can be placed
34. ture Electronics www futureelectronics com or Mouser Electronics www mouser com Wi 232DTS 2003 2005 Radiotronix Inc 25 Radiotronix Inc 905 Messenger Lane Moore OK 73160 405 794 7730 405 794 7477 Fax www radiotronix com sales radiotronix com Wi 232DTS 2003 2005 Radiotronix Inc 26
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