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1. EmbeddedDNA Eurolech THE COMPLETE EMBEDDED PC SOLUTION CPU 1232 TFT Digital Interface Rev 1 0 Sep 2003 COPYRIGHT 1994 2003 Eurotech S p A All Rights Reserved Application Note ABOUT THIS MANUAL This application note contains information about the TFT Digital Interface installed on the CPU 1232 Eurolech THE COMPLETE EMBEDDED PC SOLUTION Via J Linussio 1 33020 AMARO UD ITALY Phone 39 0433 485 411 Fax 39 0433 485 499 web _ http www eurotech it e mail mailto sales eurotech it NOTICE Although all the information contained herein has been carefully verified Eurotech S p A assumes no responsibility for errors that might appear in this document or for damage to property or persons resulting from an improper use of this manual and of the related software Eurotech S p A reserves the right to change the contents and form of this document as well as the features and specifications of its products at any time without notice Trademarks and registered trademarks appearing in this document are the property of their respective owners EuroTecH Application Note Conventions The following table lists conventions used throughout this guide Icon Notice Type Description Important features or Information note instructions potential damage to a program system or device or potential personal injury Warning Information to alert you to EuroTecH This page is intenti2. TFT LCD datasheet to which you want to connect Sometimes when running CRT and TFT video at the same time the image shown on the CRT could appear rescaled and shifted This happens because the parameters inserted for the TFT interface also modifies the CRT visualization Defining CPU 1232 BIOS Parameters As previously mentioned to enter the proper parameters into the Flat Panel BIOS settings the user should refer to the TFT LCD datasheet In Table 6 is shown an example of a timing table referring to a 640x480 TFT LCD EuroTecH Application Note A EI EI o e a0 Ji o e ara 2 COM CS ujete ENE II 1 E HE 8 os ae eee Display period ay period Te eo E gt hasi NON de E a o aw oeme o ICI e fae e CLK Hsyne timing Hsync CLK timing Vsyne Hsyne timing spp Maca Display period ay period 460 T Fixed timing mode Fe Fixed timing mode aromas felel pe gt rea pap aoee CO E rem EC O O CT Table 6 Timing Characteristic Example for a TFT LCD Front porch i 12 T Back porch 13 The following instructions are an example on how to define the values to enter in the Setup relating to timing characteristics shown in Table 6 EuroTecH 14 Application Note BIOS Field BIOS Value Notes Type Custom We would enter custom parameters Resolution 640x480 Obtained from the TFT LCD datasheet this is a characteristic Dot Clock MHz 25 Referring Table 6 CLK 1 T
3. aneous Refresh Rate Colours Hz 8bpp 256 colours 60 16bpp 64K colours 60 8bpp 256 colours 60 16bpp 64K colours 60 8bpp 256 colours 60 16bpp 64K colours 60 LCD TFT video resolutions This list is not meant to be a complete list of all the possible supported TFT video For further info about other new LCD TFT flat panels supported please contact the Eurotech Customer Support Service Application Note J19 TFT Digital Interface Connector The TFT digital interface is accessible via the J19 connector which is a 20x2 pitch 1 25mm SMT connector aa i i see 3888 Zom 00 628888888 NS Geode E CS5530A A J19 I O LCD TFT Companion NS Geode Gx1 Process Figure 1 Connectors layout The following table shows the J19 connector type and its matching models Connector Reference Connector Type J19 Used Connector Hirose DF 13 40DP 1 25V J19 Corresponding connector Hirose DF13 40DS 1 25C Table 2 J19 mating connectors For fur
4. ationships should be ensured Horizontal Sync Period th Display Period thd Front Porch thf Pulse Width thp Back Porch thb Vertical Sync Period tv Display Period tvd Front Porch tvf Pulse Width tvp Back Porch tvb Practically referring to Table 6 and to Table 7 the results are Horizontal Sync 800 640 16 96 48 Vertical Sync 525 480 12 31 2 EuroTecH 16 Application Note Chapter 3 Connecting the TFT LCD to the CPU 1232 This section contains a brief checklist of the actions to perform before connecting a TFT LCD display to the CPU 1232 a First of all download all information about the TFT LCD module and its inverter selected a Verify that the resolution of the TFT panel is compatible with and supported by the resolution shown in Table 1 of this application note a Read carefully the TFT LCD datasheet in particular the Electrical Characteristics that must be compatible with the electrical interface of the CPU 1232 TFT LCD interface referred to in Table 4 a Consulting the TFT LCD datasheet and the Table 3 CPU 1232 connector pin out write a table with the connections between the J19 CPU 1232 connector and the TFT LCD selected this may be useful when building the connection cable a Consulting the TFT LCD inverter datasheet and Table 3 CPU 1232 connector pin out make the proper cable a Refer to the TFT LCD input signal timing datasheet section to detect the paramete
5. c Typical value The reported value 25 1 5MHz is approximated to 25Mhz Referring Table 6 HSync Front Porch thf Typical value The HSync FP 2 reported value 16CLK So the value you ve to enter the BIOS is 2 to obtain 16 2x8 Referring Table 6 HSync Pulse width thp Typical value The HSync AT 12 reported value 96CLK The value you ve to enter the BIOS is 12 to obtain 96 12 x8 Referring Table 6 HSync Pulse Back porch thb Typical value HSync BP 6 The reported value 48CLK The value you ve to enter the BIOS is 6 to obtain 48 6x8 Referring Table 6 VSync Front Porch tvf Typical value The reported value 12CLK VSync AT Referring Table 6 VSync Pulse width tvp Typical value The reported value 2 H Referring Table 6 VSync Back Porch thb Typical value The reported value 31CLK VSync FP 12 VSync BP 31 Table 7 Flat Panel BIOS parameters Timings Diagrams The followings images show a graphical mode to represent timing data The information is not represented in the same graphical order shown into the Flat Panel BIOS setup but the contents are the same lt Horizontal gt Display period Note Figure 3 Timing Diagram Horizontal Mode EuroTecH Application Note 15 lt Wertical gt Wsyne A Display period a Figure 4 Timing Diagram Vertical Mode The previous Figures may be useful to verify graphically if the entered BIOS parameters match the TFT timing diagram Regarding the timing the following rel
6. lock Dot Clock is the pixel dot clock output It clocks the pixel data Flat Panel Horizontal Sync Flat Panel Horizontal Sync establishes the line rate and horizontal Retrace interval for a TFT display Flat Panel Vertical Sync Flat Panel Vertical Sync establishes the screen refresh rate and vertical retrace interval for a TFT display Display Enable Display Enable indicates the active display portion of a scan line This is a data valid signal This is a useful signal which allow you to control the switching on off of the lamps Graphics Red Pixel Data Bus This bus drives graphics pixel data synchronous to the Dot Clock output Graphics Green Pixel Data Bus This bus drives graphics pixel data synchronous to the Dot Clock output Graphics Blue Pixel Data Bus This bus drives graphics pixel data synchronous to the Dot Clock output Application Note Electrical Characteristics TTL 8mA VHMAX 3 3V TTL 8mA Vumax 3 3V TTL 8mA VHMAX 3 3V TTL 8mA Vinmax 3 3V TTL 8mA VHMAX 3 3V TTL 8MA Vumax 3 3V TTL 8mA Vumax 3 3V TTL 8mA Vumax 3 3V TTL 8mA Vinmax 3 3V TTL 8mA Vumax 3 3V Power Supply 5V 5 Ground Ground Table 4 Signal Description Electrical Characteristics EuroTecH Application Note 11 Chapter 2 BIOS Setup To enable the TFT Digital Interface functionality the user sbould properly configure the BIOS settings This section will show which BIOS settings to modify to prope
7. onally left blank Table of Contents CONV GMM OMS sorrise nanea a a sendeeeesuehconacennsebucts cn Su a asatuchas a 3 Table OF GONG MIMS oosina a a a Ea aaa 5 Chapter CPU 1232 TFT Digital Interface o 7 TFT Digital Interface OW CPV iG W series etonse trees n S 7 JIS TFT Digital Interface Connector ai doi 8 J19 TFT Digital Interface Pl Dita A E A A 9 J19 TFT Digital Interface Signal DescriptiON cccooocccccocnoccccoconcoconnncncannnnnnnanononannnnononnnnonnnnnnononannnnnnnns 10 Ghapterz BIOS Secu ui occ pico 11 CPUFIZ32 BIOS Mena AO oca 11 CPU 1232 BIOS Flat Panel Parameters 000 A A A a 12 Defining CPU 1232 BIOS Parameters ccccccccssscecceeseeeceenseecseucecsseeeecsaueeecseaeeeessaseeessageeessageeeessaseeseas 12 TANS Bigga asa A sanan 14 Chapter 3 Connecting the TFT LCD to the CPU 1232 cc cteccccsssseeeeeeeeeeeeeeeeeseeseeesseeneseeeneeeseaeneesenenes 16 This page is intentionally left blank Chapter 1 CPU 1232 TFT Digital Interface This brief application note contains information about using the CPU 1232 TFT digital interface to help users connect TFT LCD panels to the CPU 1232 module TFT Digital Interface Overview The CPU 1232 allows users to connect various models of LCD TFT flat panel displays via its J19 connector The following table shows the supported LCD TFT video resolutions Resolution 640x480 640x480 800x600 800x600 1024x768 1024x768 Table 1 Simult
8. rly control the LCD TFT For further information on how to set the BIOS please refer to the CPU 1232 user manual CPU 1232 BIOS Menu After entering BIOS setup pressing the F2 key during the boot time select the Flat Panel page using the cursor arrows The following image will appear on the screen General Custom Devices communications 640x480 ATAPI Units 25 Advanced Flat Panel PCI Legacy EF PCI Advanced Power Management Error Handling Quit Figure 2 BIOS setup Flat Panel section EuroTecH CPU 1232 BIOS Flat Panel parameters Application Note This is a brief description of the fields that can be modified in the BIOS Setup their default value Field Type Resolution Dot Clock MHz HSync FP HSync AT HSync BP VSync FP VSync AT VSync BP Description Disabled Disabled Custom Custom parameters Hitachi 800x600 38MHz LG 800x600 38MHz NEC 800x600 38MHz Sharp 800x600 40MHz Select the proper graphical z resolution 1024x768 Dot Clock Frequency in MHz Front Porch Horizontal Sync This Value must be recognized from the TFT Display Data Sheet Active Time Horizontal Sync Back Porch Horizontal Sync Front Porch Vertical Sync Active Time Vertical Sync Back Porch Vertical Sync Table 5 BIOS Flat Panel Options Default Value Disabled 640x480 a O E O A To insert the correct parameters the user should refer to the information contained into the
9. rs to insert into the CPU 1232 BIOS Flat Panel section and calculate it as described in the Chapter 2 BIOS Setup a To connect the system first carefully verify the connections cable the BIOS settings and all the information to prevent erroneous damages to the system a After verifying the information power up the system verifying all information is properly displayed on the TFT LCD module Try some graphical test programs to detect the functionality of the images EuroTecH
10. ther information about connectors electrical mechanical please refer to the Hirose website http www hirose com referring to the DF13 connector family Eurolechi Application Note J19 TFT Digital Interface Pin Out The following table describes the J19 TFT Digital Interface connector signals Pin Number 2 A 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Table 3 Function Reserved GND NC GND GREENS MSB GREEN4 GREEN3 GREEN2 GND GREEN1 GREENO LSB BLUE5 MSB BLUE4 GND BLUES BLUE2 BLUE1 BLUEO LSB GND Dot Clock Pin Number Function GND GND VDD VDD FP HSYNC GND FP_VSYNC VDD VDD Data Enable GND RED5 MSB RED4 RED3 VDD Enable BackLight Enable RED2 RED1 REDO LSB GND J19 TFT Digital Interface connector pinout For physical correspondence with the J19 connector pins please refer to Figure 1 The purpose of the information shown herein is to help the user properly build the cable for connecting the digital interface of the CPU 1232 with a TFT LCD Panel Reducing the cable length will reduce interferences to the TFT LCD digital signals EuroTecH 10 J19 TFT Digital Interface Signal Description The digital TFT interface signals are described in the following table SIGNAL NAME Dot Clock FP_HSYNC FP_VSYNC ENA _DISP VDD ENABLE DATA ENABLE BACKLIGHT ENABLE REDI5 0 GREEN 5 0 BLUE 5 0 VDD GND Description Pixel Port C
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