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Nexus Technology Company Confidential

1. 16 Figure 5 Read Data Latency CAS Latency CAS Additive Latency RDIMM 54041 6 cid C Dc 69 Figure 6 Write Data Latency CAS Write Latency 5 1 6 cycles 70 Figure 7 Locating Minimum Valid NEX DDR3INTR HS Read Data Window 71 Figure 8 Measuring NEX DDR3INTR HS Data Hi Lo Read Data Setup amp Hold 72 Figure 9 Measuring NEX DDR3INTR HS Data Hi Lo Read Data Setup amp Hold 73 Figure 10 NEX DDR3INTR HS Setup Window esee 74 Figure 11 NEX DDR3INTR HS Setup Window rennen 74 Figure 12 NEX DDR3INTR HS Read Data Capture Point Window 75 Figure 13 Locating Minimum Valid NEX DDR3INTR HS Write Data Window 76 Figure 14 Measuring NEX DDR3INTR HS A Data Hi Lo Write Data Setup amp Hold 76 Figure 15 Measuring NEX DDR3INTR HS Data Hi Lo Write Data Setup amp Hold 77 Figure 16 NEX DDR3INTR HS Write Data Capture Point Window 78 Figure 17 Viewing Individual 8 bit Read Data Groups see 79 Figure 18 TLA V5 6 or later Setting Individual Setup amp Hold Values for the 8 bit Read Data esiste erattu eed 79 Figure 19 NEX DDR3INTR HS Listing Display
2. 100 TABLE TABLES Table 1 NEX DDR3INTR HS Support Software Requirements 9 Table 2 B DDR3D 2D lt 1333MT s Read and Write Storage and Trigger Grouping 17 Table 3 B DDR3D 4D lt 1866MT s Read and Write Storage and Trigger Grouping 23 Table 4 DDR3D lt 1333MT s Read and Write Storage and Trigger Grouping 35 Table 5 R DDR3D 2 lt 1866MT s Read and Write Storage and Trigger Grouping 39 Table 6 B DDR3D 2D lt 1333MT s Read and Write MagniVu Channel Grouping 52 Table 7 BLDDR3D_4A lt 1866MT s Read and Write MagniVu Channel Groupins 55 Table 8 DDR3D lt 1333MT s Read and Write MagniVu Channel Groupins 60 Table 9 DDR3D 2 lt 1866MT s Read and Write MagniVu Channel Grouping 63 Table 10 NEX DDR3INTR HS Mnemonics Definition 84 Table 11 NEX DDR3INTR HS Control Symbol Table 86 1 0 OVERVIEW 1 1 General Information The DDR3 Interposer Products are designed for ease of use Interposers add extra signal trace length and an extra connector that might affect the quality of the system operation in some systems This Product is designed for capture of DDR3 data rates of 1866MT s or slower and may only be used with
3. 84 6 4 Viewing Timing Data on the TLA 84 HINES amp TIPS ho gos tend 86 7 1 Symbolic Triggering on a Command using NEX DDR3INTR HS Supports 86 7 2 DDR3D 2D R_DDR3D_1A Capturing MRS Mode Register Set Cycles 87 7 3 DDR3D 4A R DDR3D 2 Power Triggers 88 7 4 DDR3D 4A R DDR3D 24A Capturing MRS Mode Register Set Cycles 93 7 5 Address Errors When Decoding MRS Cycles 95 7 6 MRS Decode Errors for Ranks other than 95 Jh Thresholds eroinin cick 95 APPENDIX How DDR Data is Clocked u 96 AGT TRACK Sr OU uuo a hip S Qa 96 A2 DDR Aoquisitioti 96 A 3 B_DDR3D_2D R_DDR3D_1A a teo eet 97 4 B_DDR3D_4A R_DDR3D_2A Acduisition 97 APPENDIX B Setting Sample Capture Points in TLA V5 6 xXX 99 uides 101 NEX DDR3INTR HS Bus Loading 101 2 DIMM connector
4. 114784 TLATBB4A TLA7BAA Slots 1 2 Slots 3 4 Slots 5 6 Slots 7 8 Slots 9 10 Slots 11 12 Slave 2 Master Slave 1 Slave 3 Figure 1 7Bx4 Merged Module Configuration The logic analyzer modules should be connected to the DDR3 DIMM Interposer as follows using 1 Tek P6960HCD probe and three 3 Tek P6962HCD probes TLA Master Connect the P6960HCD probe head to the DDR3 Interposer s LEASH soldered on coax cable that is attached to the P153 163 Coax cables on the Interposer Plug the TLA connector from the probe into the E3210 input of the Logic Analyzer module and then plug the B TLA connector from the probe into the C3210 input of the module TLA Slave 1 Connect the P6962HCD probe head to the DDR3 Interposer s LEASH soldered on coax cable that is attached to 152 162 Coax Cable on the Interposer Plug the probe s TLA connectors into the Slave 1 acquisition module as follows B2 connector into the E3210 input A connector into the AD32 input A2 connector into the AD10 input Bl connector into the C3210 input B DDR3HS MN XXX ll Doc Rev 1 40 Nexus Technology Company Confidential Slave 2 Connect the P6962HCD probe head to DDR3 Interposer s LEASH soldered on coax cable that is attached to 154 164 Coax Cable on the Interposer Plug the probe s TLA connectors into the Slave 2 acquisition module as follows B2 connector into the E3210 i
5. For Help press F1 Figure 7 Locating Minimum Valid NEX DDR3INTR HS Read Data Window B_DDR3HS MN XXX 71 Doc Rev 1 40 Nexus Technology Company Confidential RD File Edit view Data System Tools Window Help 4 Sample Point Import Tool wm Protocol Designer iverify AutoDeskew il setup IA Trigger 1 waveform Listing Tek Idle 0 amp view a9 Magnivu Activity OF value Q QQ Time Div 500 lt v D Search v pil amp og Cursor 2 v 1 09ns Vu KEO Vu RASH CASH Eb yVu Strobes 1FF 1 B yVu Data AAAABABA AAAABAAA 00000000 00000000 00000000 B niu Data EFAFBAFF EFABBAFF 00000000 FFFFFFFF 00000000 00000000 EP Vu DataByte7 00 00 lt For Help press F1 Figure 8 Measuring NEX DDR3INTR HS A Data Hi Lo Read Data Setup amp Hold Zoom in further to determine the Setup and Hold sample point necessary to acquire valid data at that point Figure 8 and use the cursors to measure the time from the clock edge to the start of valid Read data In this example the delay from edge to data is approximately 1 05ns after the clock edge meaning that a suitable Setup amp Hold value for the A Data Hi capture group would be 1 055ns 1 289ns Note that the A Data Lo group is valid somewhat later than the Data Hi group with its valid time starting at approximatel
6. Figure 9 Measuring NEX DDR3INTR HS Data Hi Lo Read Data Setup amp Hold Now the sample point positions must be set for the A Data Hi Lo and B Data Hi Lo capture groups in the Setup window Each 32 bit data group will require its own value programmed from the measurements noted in the MagniVu window IMPORTANT for the B DDR3D 4A and DDR3D 2 supports the values used for the data groups must also be used for the data groups and the values used for the data groups must also be used for the D data groups The capture points are set in the Setup window within the B DDR3D XX R DDR3D XX tab see Figure 10 In the lower right portion of the window is a scroll field Scroll down until grayed out groups are visible then select the group in which the sample points are to be selected Figure 11 Clicking on the Rising Falling Edge icon red arrow will bring up the window shown in Figure 12 Set the Ts value for the Setup time derived from the analysis of the MagniVu data This should automatically set the appropriate Hold time for the group As mentioned above when using the DDR3D 4A and DDR3D IA supports the values used for the Read Data Hi Lo capture groups must also be used for the Read Data Hi Lo capture groups and the values used for the Read Data Hi Lo capture groups must also be used for the Read D Data Hi Lo capture groups B DDR3HS MN XXX
7. nah qis ans 7 12 Customer Product bet iue 7 1 3 Software Package descnplloIt co dece opel il Ge de 7 n Mea SS A ASS aS SA 8 KS C GC TOUTE L us bonis AM SS Ente uw ana 8 20 SOFTWARE INS TALIA TION 9 2 1 General Support Software Information enne enne enne 9 2 2 Loading the Support Into the TLA 9 3 0 CONNECTING to the NEX DDR3INTR HS INTERPOSER eere 10 3 1 General c ECCO 10 32 BzXDDR3SD 2D SUpDOEti c eee Saeed re ee od irs uite 10 3 3 B aQ a aqa 10 3 4 R_DDR3D_1A Support Reduced Module Count support 12 3 5 R_DDR3D_2A Support Reduced Module Count support 13 3 6 Short LIONSELDIODES 14 3 6 1 HCD connector the LEASH probe 15 3 6 2 LEASH probe to the various logic analyzer probes 15 3 7 Interposer location in the Target Ou NO datu uvas catu aU Eee tud 16 3 8 Display Groups not in Tables 2 3 4 or O Gio 46 AO CLOCK SELECTION utn Quid d 47 4 1 B DDRSD 2D Clo
8. lt 1333MT s Read and Write MagniVu Channel Grouping Group Signal TLA Group Signal TLA Name Name Input Name Name Input DataByte7 DQ63 DataByte3 DQ62 2061 2060 2059 2058 2057 2056 DataByte6 DQ55 DataByte2 DQ54 DQ53 DQ52 051 2050 2049 2048 DataByte5 DQ47 DataBytel DQ46 DQ45 DQ44 DQ43 DQ42 2041 2040 DataByte4 DQ39 DataByte0 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 Table 8 DDR3D lt 1333MT s Read and Write MagniVu Channel Grouping 4 Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin Input Name Name Pin Input Control CKEI Address BA2 SYM BAI S3 BAO S2 15 1 14 0 A13 BA2 12 BAI All BA0 15 9 14 8 13 AT A12 BC A6 5 RAS A4 CAS A3 WE A2 Strobes Al HEX A0 DM8 ERR_OUT RESET TEST ODTO ODTI PAR IN Table 8 DDR3D 1333MT s Read and Write Storage and Trigger Grouping cont d Notes 1 denotes low true signal Notes 1 Group Name Data_Hi_M Signal Name TLA Input Group Name Data_Lo_M Signal Name DQ31_M DQ30_M DQ29_M DQ28_M DQ27_M DQ26_M DQ25_M DQ24_M DQ23_M DQ22_M DQ21_M DQ20_M DQ19_M DQ18_M DQ17_M DQ16_M DQ15_M DQ14_M DQ13_M DQ12_M DQ11_M DQ10_M DQ9_M DQ8_M DQ7_M DQ6 M DQ5 M DQ4 M DQ3 M DQ2 M DQI M DQ0 M TLA Input D2 6 D2 3 M E2 0 M E2 1 M D2 4 M D2 M_E2 2 M_E2 3 M_E2 4 M_E2 5 M_E3 2
9. 0 11_0 A10 AP_0 Control 0 SYM DDR3 TLA Input Control 1 SYM Address 17 Hex Signal Name CKEI 1 CKEO 1 53 1 52 1 51 1 0 _1 BA2_1 _1 _1 15_1 Al4_1 A13 1 12 1 A10 AP 1 RAS 1 1 WE 1 BA2 1 BAI 1 BAO 1 A15 1 A14 1 A13 1 12 1 11_1 A10 AP_1 DDR3 TLA Pin 52 190 71 171 172 196 174 55 70 175 177 56 178 58 59 180 61 181 188 Input A32 A3 1 1 M_C2 541 C3 0 1 M C3 4 1 M C3 3 1 M A3 0 1 M_C3 741 CI1 6 1 CKO 1 A2 5 1 M_CK3 1 2 471 M_C1 341 _ 3 6 1 C3 5 1 M_C1 741 M A3 0 1 C3 7 1 M CI 6 1 CKO 1 2 571 _ 1 2 471 A2 6 1 M_C1 341 M_A2 141 M_A2 041 2 371 0 2 1 2 271 0 571 0 1 M 1 M_C1 141 1 571 Table 5 DDR3D 2A lt 1866MT s Read and Write Storage and Trigger Grouping cont d Notes 1 denotes a low true signal These signals are required for accurate acquisition and post processing of acquired data The M in front of TLA channel denotes the Master card of the merged pair The 75 in front of a TLA channel denotes the Slave card of the merged pair Signals in these groups are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value Signal DDR3 TLA Group Signal DDR3 TLA Name Pin Input Name Name Pin Input Ungrouped PAR_IN_O 68
10. A3 APPENDIX Data Flow Through the Probes coax cable to channel Coax wire Coax P153 163 Coax P152 162 Coax P154 164 Coax P151 161 PIN Channel Channel Channel Channel 1 6960 PRB2X P6962HCD PRB2X P6962HCD PRB2X P6962HCD APPENDIX D Data Flow Through the Probes coax cable to channel Cont d Coax wire Coax P153 163 Coax P152 162 Coax P154 164 Coax P151 161 PIN Channel Channel Channel Channel 1 6960 PRBIX P6960HCD PRBIX P6960HCD PRB1X P6960HCD APPENDIX B DDR3D 2D Support Pinout TLA Channel 15 RESET CKEI CKEO BA2 ERR OUT All 14 A12 BC PRB2X Probe Connection for B_DDR3D_2D software Coax P152 162 TLA DDR3 Channel Signal PRB1X Probe Connection for B_DDR3D_2D software Coax P153 163 APPENDIX B DDR3D 2D Support Pinout Cont d TLA DDR3 TLA DDR3 Channel Signal i Channel Signal PRB2X Probe Connection for PRB2X Probe Connection for B DDR3D 2D software B DDR3D 2D software Coax P154 164 Coax P151 161 APPENDIX B DDR3D 4A Support Pinout TLA DDR3 TLA DDR3 Channel Signal Channel Signal CB1 CB3 CB7 CB6 CB2 2058 DM8 CB5 CB4 DQ31 CB0 DQ27 DQ30 DM3 DQ26 DQS3 15 TEST RESET 1 CKE0 BA2 ERR_OUT All 14 A12 BC P6962HCD 2X Probe Connection for P6960HCD 1X Probe Connection for B_DDR3D_4A software B_DDR3D_4A software Coax P152 162 Coax P153 163 AP
11. DQ26 DQ26 DQ3I DQ3I DQ42 DQ42 DQ47 DQ47 2027 0027 VSS VSS DQ43 DQ43 VSS VSS VSS VSS NC CB4 VSS VSS DQ52 DQ52 NC CBO NC 5 DQ48 DQ48 2053 2053 VSS DQ49 DQ49 VSS VSS APPENDIX D 240 pin DDR3 DIMM Pinout cont d Front Side left 1 60 X64 Non Parity X72 ECC VSS Back Side right 121 180 X64 Non Parity DM8 DQS17 X72 ECC DM8 DQS17 Front Side left 61 120 Pin SS X72 ii Parity Fee Back Side right 181 240 X64 Non Parity DM6 DQS15 Pin X72 ECC DM6 DQS15 DQS8 DQS17 0517 DQS15 0515 2058 VSS VSS VSS VSS VSS NC CB6 DQ54 DQ54 NC CB2 NC CB7 DQ55 DQ55 NC CB3 VSS VSS VSS VSS VSS Test DQ60 DQ60 Free Free Free DQ61 DQ61 KEY VSS VSS RESET RESET CKEI DM7 DQS16 DM7 00516 CKEO CKEO VDD 20 16 DQS16 VDD VDD 15 VSS VSS BA2 BA2 14 0062 0062 ERR OUT NC ERR OUT VDD DQ63 DQ63 VDD VDD A12 VSS VSS All All A9 VDDSPD VDDSPD A7 A7 VDD SAI SA1 VDD VDD A8 SDA SDA A5 A5 A6 VSS VSS A4 A4 VTT VTT
12. 80 Figure 20 Disassembly Properties apa 81 Figure 21 NEX DDR3INTR HS Listing Display Control Flow 83 Figure 22 NEX DDR3INTR HS MagniVu Display on TLA 85 Figure 23 B_DDR3D_2D MRS Trigger 87 Figure 24 MRS Cycle Acquisition Disassembly eese 88 Figure 25 B DDR3D 4A R DDR3D 24A Read Command Trigger 90 Figure 26 B DDR3D 4A DDR3D 2 Read Command Trigger Detail 90 Figure 27 B DDR3D 4A DDR3D 2 Read Address and Data Trigger BL 4 Odd WALETICIES ea xx Late cur 91 Figure 28 B DDR3D 4A R DDR3D 2 Read Address and Data Trigger BL 4 Even 92 Figure 29 B DDR3D 4A DDR3D 2A MRS TTIg8g8er 93 Figure 30 B DDR3D 4A DDR3D 2 MRS Trigger Detall 94 Figure 31 MRS Cycle Acquisition Disassembly eene enne 94 Figure 32 B DDR3D 2D Setup Window TLA V5 6 or later see 99 Figure 33 B DDRD 2D Setup Window TLA V5 6 or later 100 Figure 34 B DDR3D 2D Capture Point Window TLA V5 6 or later
13. CAS VDD VDD DQS1 DOQS1 NC DQS10 NC DQS10 VDD VDD ODTO ODTO DQSI DQSI VSS VSS 51 51 13 13 VSS VSS DQ14 DQ14 RSVD ODTI RSVD ODTI VDD VDD DQIO DQIO DQI5 DQI5 VDD VDD Free Free VSS VSS RSVD SPD RSVD Spd3 VSS VSS VSS VSS DQ20 DQ20 VSS VSS DQ36 DQ36 DQI6 DQI6 DQ21 DQ21 DQ32 DQ32 DQ37 DQ37 DQI7 0017 VSS VSS DQ33 DQ33 VSS VSS VSS VSS DML2 20511 DML2 DQS11 VSS VSS DM4 DQS13 DM4 DQS13 DQS2 DQS2 DQS11 DQS11 DQS4 DQS4 DQS13 DQS13 DQS2 DQS2 VSS VSS DQS4 DQS4 VSS VSS VSS VSS DQ22 DQ22 VSS VSS DQ38 DQ38 DQI8 2018 2023 2023 2034 0039 0039 DQI9 2019 VSS VSS DQ35 DQ35 VSS VSS VSS VSS DQ28 DQ28 VSS VSS DQ44 DQ44 DQ24 DQ24 DQ29 DQ29 DQ40 DQ40 DQ45 DQ45 DQ25 DQ25 VSS VSS VSS VSS VSS VSS DM3 DQS12 DM3 DQS12 VSS VSS DM5 DQS14 DM5 DQS14 DQS3 DQS3 DQS12 DQS12 DQSS DQS5 DQS14 DQS14 DQS3 DQS3 VSS VSS DQS5 DQS5 VSS VSS VSS VSS DQ30 DQ30 VSS VSS DQ46 DQ46
14. Connect NEX PRBIXL probe head to the DDR3 Interposer s LEASH that is attached to the P151 161 Coax cable on the Interposer Match the label end of the NEX PRB1XL probes with the labels the front of the Tektronix Logic Analyzer Master module and connect See Figure 2 for connections Table 4 shows the Channel Grouping Wiring for use with the R_DDR3D_1A support 3 5 R DDR3D 2A Support Reduced Module Count support To acquire DDR3 Read and Write data at speeds at up to 1866MT s requires two merged TLA7BB4 136 channel logic analyzer modules each having the 1 4GHz state speed option and the R DDR3D 2A support software The Master card will be in the lower numbered of the two cards and the Slave card is in the adjacent high numbered slots The logic analyzer modules should be connected to the DDR3 DIMM Interposer as follows using 4 Tek P6960HCD probes TLA Master Slave Connect the P6960HCD probe head to the DDR3 Interposer s LEASH soldered on coax cable that is attached to the P151 161 Coax cables on the Interposer Plug the A TLA connector from the probe into the E3210 input of the Master Logic Analyzer module and then plug the TLA connector from the probe into the E3210 input of the Slave module Connect the P6960HCD probe head to the DDR3 Interposer s LEASH soldered on coax cable that is attached to the P152 162 Coax cables on the Interposer Plug the A TLA connec
15. DQ5 RD A DQ4 RD DQ3 RD A DQ2 RD A DQI RD A DDR3 TLA Pin 4 Input Table 3 DDR3D 4D lt 1866MT s Read and Write Storage and Trigger Grouping 1 All signals on this page are required for accurate post processing of acquired data The M in front of TLA channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set The S2 in front of a TLA channel denotes Slave card 2 of the merged set The 3 in front of a TLA channel denotes Slave card 3 of the merged set poe 19 Group Name RdBDatHi Hex Signal Name RD_B_DQ63 RD_B_DQ62 RD_B_DQ61 RD_B_DQ60 RD_B_DQ59 RD_B_DQ58 RD_B_DQ57 RD_B_DQ56 RD_B_DQ55 RD_B_DQ54 RD_B_DQ53 RD_B_DQ52 RD_B_DQ51 RD_B_DQ50 RD_B_DQ49 RD_B_DQ48 RD_B_DQ47 RD_B_DQ46 RD_B_DQ45 RD_B_DQ44 RD_B_DQ43 RD_B_DQ42 RD_B_DQ41 RD_B_DQ40 RD_B_DQ39 RD_B_DQ38 RD_B_DQ37 RD_B_DQ36 RD_B_DQ35 RD_B_DQ34 RD_B_DQ33 RD_B_DQ32 DDR3 TLA Input Group Name RdBDatLo Hex Pin Signal Name RD_B_DQ31 RD_B_DQ30 RD_B_DQ29 RD_B_DQ28 RD_B_DQ27 RD_B_DQ26 RD_B_DQ25 RD_B_DQ24 RD_B_DQ23 RD_B_DQ22 RD B DQ I RD B DQ20 RD B DQI9 RD B DQI8 RD B RD B DQl6 RD B DQI5 RD 014 RD B 013 RD B DQI2 RD B RD B RD B DQ9 RD B DQ8 RD B DQ7 RD B DQ6 RD B DQS5 RD B DQ4 RD B DQ3 RD B DQ2 RD B RD B DDR3 TLA Pin 156 155 150 149 37 36 31 30 147
16. Notes 1 denotes low true signal 2 These signals are required for accurate acquisition and post processing of acquired data 3 The M in front of a TLA channel denotes the Master card of the merged pair 4 The S in front of a TLA channel denotes the Slave card of the merged pair 5 3 Adjusting Input Thresholds for Proper Data Acquisition 5 3 1 Thresholds for NEX PRB1XL PRB2XL Probes The Interposer DDR3 support was designed to work with the new Nexus Low Profile Distributed probes To maximize the electrical characteristics of the acquired waveforms the probe input resistors values were placed at 510 ohms This value results in a divide by ten of the signals to the logic analyzer when using the NEX PRB1X T and NEX PRB2X T probes The logic analyzer expects a divide by 20 Since the divide value is different than the standard Tektronix probe the voltage swing and offset will be higher than expected and the thresholds will be different Instead of the expected 0 75 threshold of approximately 1 9V threshold will be required Use of the logic analyzer output to a scope will be required to determine the exact threshold for the system under test Note that the Nexus SPA tool will fine adjust this threshold setting 5 3 2 Thresholds for Tektronix P696xHCD Probes Double probing the DDR3 data signals needed for 1866 MT s acquisitions yet reducing the load to that of a single probe resulted in a threshold setting on the logic analyze
17. wR Q36 E2 3 BAD C AIS 0 140 A13 0 0 2 C MM 3 0 80 70 460 AS 0 40 E22 wr Q32 1 033 1 WR Q36 2 0 10 460 LsB E23 aa URGE ontr E1 E17 d E1 6 dien a 1 0 0 534 0 524 0 518 0 504 2 term tere Eg a0 lao 9 3 0 5 0 3 0 2 SU E R 0 Eo 4 A3 7 Axe AM 8303 al A3 2 a 1 A3 0 Am 7 1 1 4 ES 0 ore Listing E ES El All B Explorer Setup Al Trigger 11 waveform 101 Sample Point Import Tool 191 Define ompare ba Ug Capture Protocol Designer SE S H Analysis NEX DDR PROTOCOL iverify Ww Fitters 11 Suppress Analysis Asynchronous Synchronous Storage 1285 Samples per Signal 32MS Options Max Clock Rate 1 4 GHz Normal Blocks 7 S H 128K El Samples 504 Every Rising Edge SDRAM DDR CLKO Clocking Search Range Custom Manual Ops H Accuracy Ops Deskew Group Participation In Other Activity amp Threshold a Clock
18. denotes low true signal 2 Signals in these groups are acquired using the 7Bx4 s demux capability and will not have a MagniVu display value Group Name ADataMsks BIN lt lt lt lt lt Q Q O BDataMsks BIN Signal Name DDR3 TLA Pin Input Group Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin Input Name Name Pin Input Control CKEI Address BA2 SYM CKEO Hex BAI S3 BAO S2 Al5 SHE 14 SO A13 BA2 A12 BC BAI All BAO 15 9 14 8 13 7 A12 BC A10 AP AS RAS A4 CAS A3 WE A2 Ungrouped DMS8 Al ERR_OUT A0 RESET TEST ODTO ODTI PAR IN Table 4 DDR3D 1333MT s Read and Write Storage and Trigger Grouping cont d Notes 1 denotes low true signal 2 These signals are required for accurate acquisition and post processing of acquired data 3 Signals in these groups are acquired using the 7Bx4 s demux capability and will not have a MagniVu display value Group Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin Input Name Name Pin Input ADatHi A_DQ63 ADatLo Hex 062 Hex DQ30 DQ6I DQ29 A DQ60 DQ28 DQ59 DQ27 DQS8 DQ26 DQ57 A DQ25 DQ56 DQ24 055 A DQ23 A DQs4 DQ22 A DQ53 DQ2I A DQ52 A DQ20 5 A_DQI9 50 A_DQI8 A_DQ49 A_DQI7 A_DQ48 A_DQI6 A_DQ47 DQIS A DQ46 A_DQI4 A DQ45
19. 2 Ungrouped RESET 0 M_A3 6 PAR_IN_1 68 2 1 RESET _1 A3 6 1 ERR_OUT _0 53 M_A2 7 ODT1_0 M_C3 1 ERR_OUT 3_1 53 M_A2 741 ODT1_1 M_C3 141 TEST 0 167 M A3 7 ODTO 0 M C3 2 TEST 1 167 A3 7 1 ODTO 1 M _ 3 2 1 DDRCLK M_C1 4 2058 M 3 2 Table 5 R_DDR3D_2A lt 1866 Read and Write Storage and Trigger Grouping cont d Notes 1 2 3 4 denotes low true signal The M in front of a TLA channel denotes the Master of the merged pair The 75 in front of a TLA channel denotes Slave card 1 of the merged pair Signals with 1 suffix are stored in 7Bx4 s Prime memory and will not have a MagniVu display value 3 S Display Groups not in Tables 2 3 4 5 There are several groups in the List window that are not documented in the tables as these groups are used only by the post processing display software To ensure correct data display these groups must not be modified These groups are DataHi DataLo ChekBits DataMasks MRS Addr 4 0 CLOCK SELECTION 41 B DDR3D 2D Clocking Selections There are two clocking option fields available when using the DDR3D 2D support package These select fields permit the user to setup the TLA acquisition as follows SDRAM Clocking Permits selecting the Clocking Mode to be used to acquire DDR3 data It is important to note that the selection chosen will force unused Chip Selects and into inactive states The field choic
20. DQ53 WR DQ52 WR WR DQ50 WR DQ49 WR DQ48 WR DQ47 WR DQ46 WR DQ45 WR DQ44 WR DQ43 WR DQ42 WR_A_DQ41 WR_A_DQ40 WR_A_DQ39 WR_A_DQ38 WR_A_DQ37 WR_A_DQ36 WR_A_DQ35 WR_A_DQ34 WR_A_DQ33 WR_A_DQ32 DDR3 TLA Input Pin Group Name WrA_DatLo Hex Signal Name WR_A_DQ31 WR_A_DQ30 WR_A_DQ29 WR_A_DQ28 WR_A_DQ27 WR_A_DQ26 WR_A_DQ25 WR_A_DQ24 WR_A_DQ23 WR_A_DQ22 WR_A_DQ21 WR_A_DQ20 WR_A_DQ19 WR_A_DQ18 WR DQI7 WR DQI6 WR DQI5 WR DQI4 WR DQI13 WR DQI2 WR A WR DQIO WR DQ9 WR DQ8 WR DQ7 WR DQ6 WR DQ5 WR DQ4 WR WR DQ2 WR DQI WR DDR3 TLA Pin 4 Input signals on this page are required for accurate post processing of acquired data 2 The M in front of a TLA channel denotes the Master card of the merged pair WrB_DatHi Hex Signal Name WR_B_DQ63 WR_B_DQ62 WR_B_DQ61 WR_B_DQ60 WR_B_DQ59 WR_B_DQ58 WR_B_DQ57 WR_B_DQ56 WR_B_DQ55 WR DQ54 WR DQ53 WR B DQ352 WR WR DQ50 WR DQ49 WR 48 WR B DQ47 WR DQ46 WR DQ45 WR B DQ44 WR B DQ43 WR B DQ42 WR_B_DQ41 WR_B_DQ40 WR_B_DQ39 WR_B_DQ38 WR_B_DQ37 WR_B_DQ36 WR_B_DQ35 WR_B_DQ34 WR_B_DQ32 WR_B_DQ33 DDR3 TLA Pin Input 5 D2 0 1 S D2 1 1 5 D2 5 1 5 QI I S D2 2 1 S D2 3 1 S D2 7 1 5 D3 0 1 S D3 2 1 S D3 3 1 S D3 7 1 S DI 5 1 S D3 1 1
21. DQI3 DQ44 012 A_DQ43 DQ42 A DQIO A_DQ41 A_DQ9 A DQ40 A_DQ39 A_DQ7 A_DQ38 A_DQ6 A_DQ37 A_DQ5 A_DQ36 A_DQ4 A_DQ35 A_DQ3 A_DQ34 A_DQ2 A_DQ33 A_DQ32 A_DQO Table 5 _2 lt 1866MT s Read and Write Storage and Trigger Grouping Notes 1 All signals on this page are required for accurate post processing of acquired data 2 The M in front of a TLA channel denotes the Master card of the merged pair Group Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin Input Name Name Pin Input BDatHi DQ63 BDatLo Hex B_DQ62 Hex B_DQ61 B_DQ60 B DQs9 B 058 B DQ57 B DQ56 B 055 B DQ54 B 053 B DQ52 B DQ51 B DQ50 B DQ49 B DQ48 B DQ47 B DQ46 B DQ45 B DQ44 B DQ43 B DQ42 B_DQ41 B DQ40 B DQ39 B DQ38 B DQ37 B DQ36 B DQ35 B DQ34 B DQ33 B DQ22 Table 5 DDR3D 2 lt 1866MT s Read and Write Storage and Trigger Grouping cont d Notes 1 All signals this page are required for accurate post processing of acquired data 2 The S in front of a TLA channel denotes the Slave card of the merged pair 3 Signals in these groups are acquired using the 7Bx4 s demux capability and will not have a MagniVu display value Group Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin Input Name Name Pin Input CDatHi C_DQ63 0 071 CDatLo C DQ3I D2 6 1 Hex C DQ62 0 171 Hex C DQ30 M_D2 341 C_DQ61 0 571 C DQ
22. 146 141 140 28 27 22 21 Input S_D2 6 S_D2 3 S3_D0 0 S3_D0 1 S_D2 4 S_D2 1 S3_D0 2 S3_D0 3 S3_D0 4 S3_D0 5 S3_D1 2 53 DI 3 S3 D0 6 S3 D0 7 53 DI 1 S3 DI 4 S3 DI 6 53 DI 7 S3 D3 4 53 D3 1 53 DI 5 S3 D3 7 S3 D3 3 S3 D32 S3 D3 0 S3 D2 7 S3 D2 3 S3 D22 S3 QI S3 D2 5 53 2 1 S3 D2 0 Table3 B DDR3D 4 lt 1866MT s Read and Write Storage and Trigger Grouping cont d Notes 1 DR All signals on this page are required for accurate post processing of acquired data The M in front of a TLA channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set The S2 in front of a TLA channel denotes Slave card 2 of the merged set The S3 in front of a TLA channel denotes Slave card 3 of the merged set Signals in these groups are acquired using the 7Bx4 s demux capability and will not have a MagniVu display value RdCDatHi Hex Notes 1 SA Du qe un Signal Name RD_C_DQ63 RD_C_DQ62 DQ6I DQ60 059 RD 058 RD DQS57 RD DQ56 RD DQS5 RD C DQ 54 DQ53 052 RD RD DQ50 RD C DQ49 DQ48 RD_C_DQ47 RD_C_DQ46 RD_C_DQ45 RD_C_DQ44 RD_C_DQ43 RD_C_DQ42 RD_C_DQ41 RD_C_DQ40 RD_C_DQ39 RD_C_DQ38 RD_C_DQ37 RD_C_DQ36 RD_C_DQ35 RD_C_DQ34 RD_C_DQ33 RD_C_DQ32 DDR3 TLA Pin Input 52 A0 0 1 52 0 171 52 A0 5 1 S2
23. 3 1 1 l as 0 m 9 9 m m mni R 31 30 R29 R 28 R 27 R26 R25 R24 ER UT amp 11 Ald 2 A7 8 R 23 R 22 R 21 R 20 Rood a 15 Redd R d3 Red2 Redi Red0 RQ 21 7 1 21 6 4 Maza Jazo 07 R QE R QE ROE R Qz R Q1 ROU Figure 33 B DDRD 2D Setup Window TLA V5 6 or later Set the Ts value for the Setup time derived from the analysis of the MagniVu data performed in Section 5 This should automatically set the appropriate Hold time for the group Signal Sampling Group Sampler Definition Open Thresholds Support Defaults Close Redo Undo Figure 34 B DDR3D 2D Capture Point Window TLA V5 6 or later B_DDR3HS MN XXX 100 Doc Rev 1 40 Nexus Technology Company Confidential APPENDIX C Considerations 1 NEX DDR3INTR HS Bus Loading It must be noted that the NEX DDR3INTR HS Interposer is designed to minimal effect on the user s circuit The acquired signals are sampled at top edge connector and then passed through isolation resistors to the probe There will be an effective 600 ohm load on all probed signals C 2 DIMM connector location for best quality signal capture An inter
24. 52 0 2 1 52 A0 3 1 52 0 771 2_ 1 0 1 2_ 1 2 1 52 1 371 52 1 771 52 A3 5 1 52 1 171 S2 1 471 52 3 771 52 A3 6 1 52 A3 4 1 52 3 171 52 2 771 52 A2 6 1 52 3 371 52 A32 l 52 2 571 52 2 471 52 2 371 52 A2 2 1 2 171 2 471 52 2 171 52 A2 0 1 _ 2 6 1 M_C2 741 RdCDatLo Hex Signal Name RD_C_DQ31 RD_C_DQ30 RD_C_DQ29 RD_C_DQ28 RD_C_DQ27 RD_C_DQ26 RD_C_DQ25 RD_C_DQ24 RD_C_DQ23 RD_C_DQ22 RD_C_DQ 21 RD_C_DQ20 RD_C_DQ19 RD_C_DQ18 RD DQI7 RD C RD DQI5 RD C DQI4 RD DQI3 RD DQI2 RD C RD DQIO RD C DQ9 RD C DQS8 RD C DQ7 RD DQ6 RD DQS5 RD DQ4 RD C DQ3 RD C DQ2 RD C DQI RD C DQO DDR3 Pin 4 TLA Input _ 2 6 1 _ 2 3 1 53 A0 0 1 53 0 171 _ 2 4 1 _ 2 1 1 3_ 0 2 1 S3_A0 341 53 0 471 53 0 571 53 1 2 1 53 1 371 53 A0 6 1 S3 0 771 53 1 171 53 1 471 53 1 671 53 1 771 53 471 53 171 53 1 571 53 771 S3 3 371 3_ 2 1 S3 A3 0 1 3_ 2 7 1 53 2 371 53 2 2 1 S3_CKO 1 3_ 2 5 1 53 2 171 53 2 071 Table 3 B_DDR3D_4D lt 1866MT s Read Write Storage and Trigger Grouping 4 All signals on this page are required for accurate post processing of acquired data The M in front of TLA channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set The S2 in fr
25. DDR3D 4A Fie System Tools Window Help 5 p m T Ed Bil Explorer l setup trigger gt BY waveform iii Listing Status Jide 74 Sample Point Import Tool Protocol Designer 5 S H Analysis NEX DoR PROTOCOL iverify D by storage Force Main Prefil Trigger Pos J Magnu 20ps_ MagniVu Trigger Pos mum Overview Figure 28 B_LDDR3D_4A R_DDR3D_2A Read Address and Data Trigger BL 4 B_DDR3HS MN XXX Jag Trigger on Read from specific address and data with even latency 8 is example used Burst Length 4 Group Control_0 ACT 508 BANK ACTIVATE And Group Address_0 OOo Reset Counter 1 And Go To 2 Group Control_1 508 BANK ACTIVATE And Group Address_1 Reset Counter 1 And Go To 2 Wait for Read Command Group Control_0 RD 508 READ And Group Address_0 9999 Inc Counter 1 And Go To 3 Group Control 1 RD 508 READ And Group Address 1 OOO GoTo4 Group Control 0 ACT 508 BANK ACTIVATE Group Address_0 1 Group Control_1 ACT 508 BANK ACTIVATE And Group Address_1 000 1 when Read Command was in first clock cycle Count Latency 2 1 Look for Read Data in either clock cycle Counter 1 lt 3 Inc Counter 1
26. DESL IGNORE COMMAND DESL IGNORE COMMAND DESL IGNORE COMMAND DESL IGNORE COMMAND DESL IGNORE COMMAND PRE PRECHARGE BANK DESL IGNORE COMMAND DESL IGNORE COMMAND DESL IGNORE COMMAND DESL IGNORE COMMAND DESL IGNORE COMMAND DESL IGNORE COMMAND Figure 19 NEX DDR3INTR HS Listing Display B_DDR3HS MN XXX 80 Nexus Technology Company Confidential OOF FOO00 OOF FOOOO 00FF0000 FFFFOOFF FFFFFFOO 00000000 OOFFFFOO OOF FFFFF OOFFOOFF FFFFFFFF 000000FF FFOOOOFF FFOOOOFF 0000FF00 OOF FOOFF FFOOOOFF 00FF0000 FF000000 OOOOFFFF FFFFFFFF FF000000 000000 0000 00 00000000 NNNNNNNNNNNNNNN N N N N Doc Rev 1 40 To change the display it is necessary to bring up the window s Properties window perform right mouse click in the State display window and select the Disassembly tab This will bring up the configuration window shown in Figure 20 Properties B_DDR3D _2D About Data Listing Window Column Marks Disassembly Module B_DDR3D_2D Show Hardware v C Disassemble Across Gaps Hardware Highlight Software DDR3D 2D Controls Control Flow Burst Length Subroutine CAS Latency CAS Additive Latency CAS Write Latency Registered lo DM Signal Use write Masks Figure 20 Disassembly Properties There are several select fields available in this window some of which must be set correctly for
27. HEX AO MISCI Placeholder MISCO Placeholder DDRCKO 184 M CI 4 Ungrouped 2058 DM8 ERR_OUT RESET TEST ODTO ODTI PAR_IN Table 2 B DDR3D 2D lt 1333MT s Read and Write Storage and Trigger Grouping cont d Notes 1 denotes a low true signal These signals are required for accurate acquisition and post processing of acquired data The M in front of TLA channel denotes the Master card of the merged pair The 75 in front of a TLA channel denotes the Slave card of the merged pair Signals in these groups are acquired using the 7Bx4 s demux capability and will not have a MagniVu display value gw up Notes Group Name RdADatHi Hex Signal Name RD_A_DQ63 RD_A_DQ62 RD_A_DQ6l RD_A_DQ60 RD_A_DQS59 RD_A_DQS58 RD A DQ57 A DQ56 RD DQ55 A DQ54 RD DQ53 A DQ52 RD A DQ50 RD A DQ49 RD DQ48 RD DQ47 RD A DQ46 RD DQ45 RD A DQ44 RD A DQ43 RD DQ42 RD_A_DQ41 RD_A_DQ40 RD_A_DQ39 RD_A_DQ38 RD_A_DQ37 RD_A_DQ36 RD_A_DQ35 RD_A_DQ34 RD_A_DQ33 RD_A_DQ32 DDR3 TLA Pin Input Group Name RdADatLo Hex Signal Name RD DQ3I RD DQ30 RD DQ29 RD DQ28 RD DQ27 RD DQ26 RD DQ25 RD A DQ24 RD DQ23 RD A DQ22 RD A DQ I RD DQ20 RD A DQI9 RD A DQI18 RD A DQI7 RD A DQI6 RD DQIS5 RD A DQI4 RD DQ13 RD A DQI2 RD A RD A DQIO RD DQ9 RD A DQ8 RD A DQ7 RD A DQ6 RD
28. OOFFOOFF FFFFOOOO OOOOFFOO FFFFOOOO Figure 21 NEX DDR3INTR HS Listing Display Control Flow Changing the Show field setting in the display of Figure 19 from Hardware to Control Flow results in the display of Figure 21 where only Row and Column Address commands and valid data are displayed Note that the timestamp is updated to reflect the time between displayed cycles 6 2 Viewing Raw DDR3 Data using NEX DDR3INTR HS XX Supports In order to make the display of DDR3 data more user friendly the raw data from the Address all Data and other groups is suppressed in the software support s Listing display Instead the post processing display software formats and reorders the data to tag and display valid DDR3 Address Commands and Data Data is reordered chronologically in the display with the oldest data being shown on the line above the newer data B_DDR3HS MN XXX 83 Doc Rev 1 40 Nexus Technology Company Confidential To see the raw data using the Interposer support package perform right mouse click in the Listing window select Add Column then click on the group to be added Refer to the TLA User s Manual or online help for further information on added or deleting data groups 6 3 NEX DDR3INTR HS Mnemonics Description Table 10 gives a brief description of each of the text lines displayed in the software support s post processing software display Mnemonic Description ACT BANK ACTIVATE Sx Bank Active com
29. RDd_CB2 S D3 3 1 WRd CB2 _ 1 3 1 5 121 WRd 5 02 1 5 2 571 WRd_CBO _ 0 5 1 Table 3 B DDR3D 4D lt 1866MT s Read and Write Storage and Trigger Grouping cont d Notes 1 denotes a low true signal 2 The S in front of a TLA channel denotes Slave card 1 of the merged set 3 Signals in these groups are acquired using the TLA s demux capability and will not have a MagniVu display value 4 Signals in these groups are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value Notes 1 9919 D Group Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin Input Name Name Pin Input ADatMsks a_DM8 BDatMsks b_DM8 BIN DM7 BIN a DM6 a DM5 a 4 a DM3 a DM2 a DMI a DMO CDatMsks DM8 S C3 1 1 DDatMsks _ 1 1 1 BIN c_DM7 52 E2 4 1 BIN S2 E0 4 1 c DM6 52 E3 6 1 52 1 671 DM5 52 C3 0 1 S2 CI 0 1 c_DM4 2 071 0 071 S 2 271 S 0 271 c_DM2 3_Q341 S3 271 c DMI 53 C3 5 1 E 53 571 c_DMO S3 C2 6 1 53 C0 6 1 Z 000060 Table 3 B_DDR3D_4D lt 1866MT s Read Write Storage and Trigger Grouping 4 The M in front of a TLA channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set The 2 in front of a TLA channel denotes Slave card 2 of the merge
30. 73 Doc Rev 1 40 Nexus Technology Company Confidential view System Tools Window Help lg eB m N Explorer setup H Trigger MY waveform fa Listing Status Idle Tek Sample Point Import Tool Protocol Designer 8 S H Analysis NEX DDR PROTOCOL 171 Define Compare Dy Ly Sy Ls Blicapure Writers F Suppress Analysis B_DDR3D_4A Asynchronous Synchronous Storage Samples per Signal Options 1 Max Clock Rate 1 4 GHz 1289 sete x 3 126K S Samples 8 Normal Blocks S H SDRAM OR CKD Caching _ Deskew Search Range Accuracy custom manual gt 9 m l E HUE Group 771 Activity amp 1 Signal Participation In Other Threshold Type Qual Probe 7 5k 4 3 Clock Qual 7 ll EsG EX2 EX 0 930 7 6 5 4 3 2 1 isa 930 7 6 5 qe 4 qeu je Mes 1 West 1 9310 93 0 E2 WR Q32 WR Q33 4 2 5 WR 935 1 WR Q37 DM4 21 wr Q32 wR Q33 I 5
31. A_DQ43 A DQII A DQ42 A DQIO A DQA4I A DQ9 A_DQ40 A_DQ8 A_DQ39 A DQ7 A DQ38 A DQ6 A DQ37 DQ36 DQ4 A DQ35 A DQ3 A DQ34 A DQ2 A DQ33 A A DQ32 A DQO Table 4 DDR3D 14A lt 1333MT s Read and Write Storage and Trigger Grouping Notes 1 All signals this page are required for accurate post processing of acquired data Group Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin Input Name Name Pin Input BDataHi 0 0 1 BDataLo D2 6 1 Hex 0 1 1 D2 3 1 0 5 1 E2 041 E2 141 A0 2 1 D2 4 1 0 3 1 D2 1 1 0 7 1 2 2 1 1 0 1 E2 3A1 A1 2A1 E2 4A1 1 3 1 E2 5 1 1 7 1 E3 2 1 D1 541 E3 3 1 1 1 1 E2 6 1 1 4 1 E2 741 D1 741 E3 141 01 6 1 E3 441 D1 441 E3 6 1 D1 141 E3 7 1 D0 7 1 1 4 1 D0 6 1 E1 141 D1 341 E3 5 1 1 2 1 E1 741 0 5 1 1 3 1 D0 4 1 E1 241 D0 3 1 E1 041 D0 2 1 E0 7 1 C2 141 0 371 C2 441 E0 2 1 00 1 1 Q2 1 D0 0 1 E0 5 1 C2 6 1 E0 1 1 C2 7 1 E0 0 1 Table 4 DDR3D lt 1333MT s Read and Write Storage and Trigger Grouping cont d Notes 1 Allsignals this page are required for accurate post processing of acquired data 2 Allsignals on this page are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value DDR3 TLA Pin Input Group Name AChkBits OFF Signal Name BChkBits OFF Table R_DDR3D_1A lt 1333MT s Read and Write Storage and Trigger Grouping cont d Notes 1
32. Data Hi RD DQ63 S2 A0 0 RD Data Lo RD 5 A2 6 RD DQ62 RD DQ30 5 A23 RD RD DQ29 S3 0 0 RD DQ60 RD DQ28 S3 0 1 RD DQ59 RD DQ27 S A24 RD DQ58 RD 0026 S A231 RD DQS57 RD DQ25 53 A02 RD DQ56 RD DQ24 S3 0 3 RD DQ55 RD DQ23 S3 04 RD DQs4 RD DQ22 53 0 5 RD DQ53 RD 0021 853 AI2 RD 52 RD DQ20 S3 1 3 RD RD DQI9 53 A0 6 RD DQ50 RD DQI8 53 0 7 RD DQ49 RD DQI7 S3 RD DQ48 RD DQI6 S3_A1 4 RD DQ47 RD DQI5 53 6 RD DQ46 0014 S3 1 7 RD_DQ45 RD DQI3 S3_A3 4 RD DQ44 RD DQI2 53 A31 RD DQ43 RD_DQ11 S3 AIL 5 RD DQ42 RD DQIO 53 A3 7 RD DQ41 RD DQ9 S3 A3 3 RD 40 RD DQ8 53 A32 RD DQ39 RD DQ7 53 A3 0 RD DQ38 RD 53 27 RD_DQ37 RD DQ5 S3_A2 3 RD DQ36 RD DQ4 S3 A22 RD DQ35 RD DQ3 S3_CKO RD_DQ34 002 53 2 5 RD_DQ33 RD_DQI S3_A2 1 RD_DQ32 RD 53 2 0 Table 7 B DDR3D 4A lt 1866MT s Read Write MagniVu Channel Grouping The M in front of TLA channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set The S2 in front of a TLA channel denotes Slave card 2 of the merged set The S3 in front of a TLA channel denotes Slave 3 of the merged set Signal TLA Signal TLA Name Input Name Input RD_DataByte7 RD_DQ63 RD_DataByte3 RD_DQ31 S_A2 6 RD_DQ62 RD_DQ30 S_A2 3 RD_DQ61 RD DQ29 S3_A0 0 RD DQ60 RD DQ28 53 A01 RD DQ59 RD DQ27 S_A2 4 RD_DQ58 RD_DQ26 S_A2 1 RD_DQ57 RD DQ25 S
33. Group Rd_ADataHi 33332222 And Group Rd_ADataLo 11110000 Trigger All Modules Group Rid BDataHi 33332222 And Group Rd_BDataLo 11110000 Trigger All Modules Group Rd_CDataHi 33332222 And Group Ad_CDataLo 11110000 Trigger All Modules Group Rd_DDataHi 33332222 And Group 4 DDataLo 11110000 Trigger All Modules Anything Reset Counter 1 And Go To 2 When Read Command was in second clock cycle Count Latency 2 1 look for Read Data in second clock cycle only transactions 1 amp 2 Counter 1 lt 3 Inc Counter 1 Group Rd_CDataHi 33332222 And Group Rd_CDataLo 11110000 Trigger All Modules Group Rd_DDataHi 33332222 And Group 4 DDataLo 11110000 Trigger All Modules Anything 5 Look for Read Data in first clock cycle only transactions 3 4 Group Rd_ADataHi 33332222 And Group Rd_ADataLo 11110000 Trigger All Modules Group Rd BDataHi 33332222 And Group BDataLo 11110000 Trigger All Modules Anything GoTo2 Tektronix 92 Nexus Technology Company Confidential n Latencies Doc Rev 1 40 7 4 B DDR3D 4A R DDR3D 2A Capturing MRS Mode Register Set Cycles If the characteristics of the DDR target latency burst length are not known it is possible to acquire this information using the so that the acquisition and post processing settings can be properly set T
34. Individual Setup amp Hold Values for the 8 bit Read Data Groups B DDR3HS MN XXX Nexus Technology Company Confidential 79 Doc Rev 1 40 6 0 VIEWING DATA 6 1 Viewing NEX DDR3INTR HS Data When using the NEX DDR3INTR HS support packages the raw Address and Data groups are suppressed and are replaced with post processed data in new groups This data 1 displayed in new groups that have the support package name preceding it 1 BLDDR3D_XX or R_DDR3D_XX Address B DDR3D 2D or _4D DataHi etc The raw data groups are suppressed so that the display of data can be done in a more user friendly fashion The Command group is suppressed because its function is replaced with a column labeled X DDR3D XX Mnemonics The Interposer support software includes post processing code that permits masking out all invalid Read Write and non Command data providing the user a much better overview of bus activity Figure 19 shows the default X DDR3D XX display where all DDR3 data is displayed DDR3 List mn gt m ES Yu 4 1 Activity Cursor 1 w tog Cursor 2v Sns Delta Time 5ns OE DESL IGNORE COMMAND IGNORE COMMAND 0000FF00 OOFFFFOO OOOOF FOO 00000000 000000FF 00000000 FF000000 FFOOOOFF FFFFFFOO FFFFOOFF PRE PRECHARGE BANK 6 7000000 OOFFFFOO OOOOF FFF FF000000 PRE PRECHARGE BANK 1 FF000000 FFFFOOFF 00000000 FFFFFFOO FFOOOOFF FF000000 OOFFFFOO FFFFFFFF 0000FF00 OOFFFFFF
35. M_E3 3 M_E2 6 M_E2 7 M_E3 1 M_E3 4 M_E3 6 M_E3 7 M_E1 4 M El 1 5 7 M_E1 3 M_E1 2 0 0 7 3 0 2 02 E0 5 E0 1 E0 0 Table 9 R DDR3D_2A lt 1866MT s Read and Write MagniVu Channel Grouping The M in front of TLA channel denotes the Master card of the merged pair Group Signal TLA Group Signal TLA Name Name Input Name Name Input Data_Hi_S Data_Lo_S Table 9 DDR3D 2 lt 1333MT s Read and Write MagniVu Channel Grouping cont d Notes 1 The S in front of a TLA channel denotes the Slave card of the merged pair Group Signal TLA Group Signal TLA Name Name Input Name Name Input DataByte7_M DataByte3_M DQ31_M DQ30_M DQ29_M DQ28 M DQ27 M DQ26 M DQ25 M DQ24 M DataByte M DataByte2 M DQ23 M DQ22 M DQ21 M DQ20 M DQI9 M DQI8 17 M 16 M DataByte5 M DataBytel M DQI5 M DQ14 M DQI3 M DQI2 M DQ11_M M 9 M M DataByte4_M DataByte0_M Table 9 R_DDR3D_2A lt 1333MT s Read and Write MagniVu Channel Grouping cont d Notes 1 The in front of a TLA channel denotes the Master card of the merged pair Group Signal TLA Group Signal TLA Name Name Input Name Name Input DataByte7_S DQ63_S DataByte3_S DQ31_S DQ62_S DQ30_S DQ61_S DQ29_S DQ60_S DQ28_S DQ59_S DQ27_S DQ58_S DQ26_S DQ57_S DQ25_S DQ56_S DQ24 S DataByte6 S DQ55_S DataByte2_S DQ23_S DQ54_S DQ22_S DQ53
36. S D3 4 1 S DI 7 1 S DI 6 1 S_D1 441 S_D1 141 S_D0 741 S_D0 641 S_D1 341 S DI 2 1 S_D0 541 S_D0 441 S_D0 341 5 D0 2 1 M 0 171 M C0 4 1 5 D0O 1 1 S_D0 041 C0 6 1 M C0 7 1 WrB_DatLo Hex Signal Name WR B DQ3I WR DQ30 WR B DQ29 WR DQ28 WR DQ27 WR B DQ26 WR B DQ25 WR B DQ24 WR DQ23 WR DQ22 WR DQ21 WR DQ20 WR DQI9 WR B DQI8 WR DQI7 WR DQI6 WR DQI5 WR B DQI4 WR DQI3 WR DQI2 WR B DQII WR DQIO WR DQ9 WR DQ8 WR WR_B_DQ6 WR WR B DQ4 WR B DQ3 WR B DQ2 WR B DQI WR DDR3 TLA Pin Input M DO0 6 1 M_D0 341 _ 0 0 1 _ 0 1 1 M_D0 441 _ 0 1 1 _ 0 2 1 _ 0 3 1 _ 0 4 1 _ 0 5 1 _ 1 2 1 _ 1 3 1 _ 0 6 1 _ 0 7 1 S_C1 141 _ 1 4 1 _ 1 6 1 _ 1 7 1 S_E1 441 S_E1 141 _ 1 5 1 S_E1 741 S_E1 341 S_E1 241 5 EL 0 1 5 E0 7 1 S E0 3 1 S_E0 241 S_CK241 5 E0 5 1 S_E0 141 5 E0 0 1 Table 2 B DDR3D 2D lt 1333MT s Read and Write Storage and Trigger Grouping cont d Notes 1 2 3 4 All signals on this page are required accurate post processing of acquired data The M in front of TLA channel denotes the Master card of the merged pair The 75 in front of a TLA channel denotes the Slave card of the merged pair All signals on this page are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value Signal DDR3 TLA Signal Nam
37. S2 C3 4 1 WR 15 S3 E3 6 1 WR C DQ46 S2 C3 1 1 WR C DQI4 53 E3 7 1 WR C 45 S2 C2 7 1 WR C DQI3 S3 C3 4 1 WR C DQ44 52 C2 6 l WR C DQI2 S3 C3 1 1 WR C DQ43 S2 C3 3 1 WR C DQII1 S3 E3 5 1 WR C DQ42 S2 C32 1 WR C DQIO 53 C377 1 WR_C_DQ41 2_C2 541 WR_C_DQ9 3_ 3 3 1 WR_C_DQ40 S2 C2 4 1 WR C 8 S3 C32 1 WR C DQ39 S2 C2 3 1 WR C DQ7 S3 C3 0 1 WR C DQ38 52 2 271 WR C DQ6 S3 C277 1 WR C DQ37 M E2 1 l WR C DQ5 3_ 2 3 1 WR_C_DQ36 M_E2 441 WR_C_DQ4 3_C2 241 WR_C_DQ35 S2 C2 1 l WR C DQ3 3_ 1 WR_C_DQ34 2_C2 041 WR_C_DQ2 3_C2 541 WR_C_DQ33 M_E2 641 WR C DQI 53 C2 1 1 WR C DQ32 M E2 7 1 WR C DQO S3 CZ 0 1 Table 3 B DDR3D 4 lt 1866MT s Read and Write Storage and Trigger Grouping cont d Notes l QUIS 19 signals on this page are required for accurate post processing of acquired data The in front of a TLA channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set The S2 in front of a TLA channel denotes Slave card 2 of the merged set The S3 in front of a TLA channel denotes Slave card 3 of the merged set All signals on this page are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value Signal DDR3 TLA Signal DDR3 TLA Name Pin Input Name Pin Input Wr_DDatHi WR_D_DQ63 S2 E0 0 1 Wr_DDatLo WR D S D2 6 1 Hex WR D DQ62 S2 0 171 Hex WR D DQ30 S D2 3 1 WR D DQ6I S2 E0 5 1 WR D
38. WR DQII WR DQIO WR B DQ9 WR B DQS WR DQ7 WR WR WR_B_DQ4 WR_B_DQ3 WR_B_DQ2 WR DQI WR B DQO DDR3 TLA Pin Input 1 All signals on this page are required for accurate post processing of acquired data The M in front of TLA channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set The S2 in front of a TLA channel denotes Slave card 2 of the merged set The S3 in front of a TLA channel denotes Slave 3 of the merged set Signals in these groups are acquired using the 7Bx4 s demux capability and will not have a MagniVu display value Ow eo m Signal TLA Signal DDR3 TLA Name Input Name Pin Input Wr_CDatHi WR_C_DQ63 2_ 2 0 1 Wr CDatLo 5 A2 6 1 Hex WR C DQ62 S2 E2 1 l Hex WR C DQ30 S_A2 341 WR_C_DQ61 2_ 2 5 1 WR_C_DQ29 3_ 2 0 1 WR_C_DQ60 2_03 1 WR_C_DQ28 53 2 171 WR DQ59 S2 2 271 WR C DQ27 5 A2 4 1 WR C DQ58 S2 2 371 WR C DQ26 S_A2 141 WR_C_DQ57 2_ 2 7 1 WR_C_DQ25 S3_E2 2A1 WR_C_DQ56 2_ 3 0 1 WR_C_DQ24 3_ 2 3 1 WR_C_DQ55 S2 E3 2 1 WR C DQ23 53 2 471 WR C DQ54 S2 E3 3 1 WR C DQ22 53 2 571 WR_C_DQ53 2_E3 741 WR C DQ21 53 E3 2 1 WR C DQ52 S2 C3 5 1 WR C DQ20 S3 3 371 WR C DQS5I S2 171 WR C DQI9 3_ 2 6 1 WR C DQ50 S2 E3 4 1 WR DQI8 3_E2 741 WR_C_DQ49 2_C3 741 WR_C_DQ17 53 171 WR C DQ48 52 C3 6 1 WR C DQI6 S3 E3 4 1 WR C DQ47
39. Write Latency plus the additional one cycle delay for RDIMM memory File Edit view Data System Tools Window Help 9 Sample Point Import Tool protocol Designer SE autoDeskew setup trigger M waveform 5 Listing Idle 0 amp 44 View Magnivu activity OF value Q d Time Div 4 5ns v D Search At 2 1505 Waveform 50015 3ns 1 500 Ops 1 500ns 3ns 4 500ns 6ns 7 50015 ns 10 500ns 1205 13 500ns 1615 16 500ns 1815 19 500ns 21ns 22 500ns j 4 668 ns H 23 633 ns Vu Sampi 2 B Vu Address 00000 40058 00000 KED Vu SOF DDRAK Vu CAS Sample Pt 1 Sample Pt 2 HANE pro Write Data Preamble B yVu Data Hi 55555555 B miu Data 55555555 By W Databyte7 ss lt gt For F1 Figure 6 Write Data Latency CAS Write Latency RDIMM 5 1 6 cycles As with acquiring Read data the B_LDDR3D_2D R_DDR3D_1A supports sample Write data twice based on each rising edge of the DDR3 clock and stores data every clock cycle So to acquire both pieces of data the Write A Data Hi Lo capture data groups must have their sample point set to that shown by Sample Pt 1 in Figure 6 and the Write Data Hi Lo capture groups must have their sample point set to that shown by Sample Pt 2 The B_DDR3D_4A R_DDR3D_2A supports sample Write data
40. _ 2 6 1 RD_B_DQ50 S_A3 4A1 RD_B_DQ18 S_C2 7A1 RD_B_DQ49 _ 1 7 1 RD_B_DQ17 S_C3 1 1 RD_B_DQ48 S_A1 6 1 RD_B_DQ16 S_C3 4 1 RD_B_DQ47 S_A1 4 1 RD_B_DQ15 S_C3 6 1 RD_B_DQ46 S_A1 141 RD_B_DQ14 S _C3 741 RD_B_DQ45 S_A0 741 RD_B_DQ13 S_E3 441 RD_B_DQ44 5 A0 6 1 RD B DQI2 S E3 1 1 RD B DQ43 S 1 371 RD B S C3 5 1 RD B DQ42 S 1 271 RD B DQIO S E3 7 1 RD B DQ4I1 _ 0 5 1 RD_B_DQ9 S_E3 341 RD_B_DQ40 5 _ 0 4 1 RD B S E32 1 RD B DQ39 5 0 371 RD B DQ7 S E3 0 1 RD B DQ38 5 A0 2 1 RD B DQ6 S E2 7 1 RD B DQ37 M_C2 141 RD B DQ5 S E2 3 1 RD B DQ36 _ 2 4 1 RD B DQ4 S E2 2 1 RD B DQ35 5 A0 1 1 RD B DQ3 5 0371 RD B DQ34 5 0 071 RD B DQ2 S E2 5 1 RD B DQ33 CZ 6 1 RD B DQI S E2 1 1 RD B DQ32 M_C2 741 RD_B_DQO S_E2 041 Table 2 B DDR3D 2D lt 1333MT s Read and Write Storage and Trigger Grouping cont d Notes 1 2 3 All signals on this page are required for accurate post processing of acquired data The S in front of a TLA channel denotes the Slave card of the merged pair All signals on this page are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value Table 2 B_DDR3D_2D lt 1333MT s Read and Write Storage and Trigger Grouping 4 Notes 1 3 The 5 in front of a TLA channel denotes the Slave card of the merged pair WrA_DatHi Hex Signal Name WR_A_DQ63 WR_A_DQ62 WR_A_DQ61 WR_A_DQ60 WR_A_DQ59 WR_A_DQ58 WR_A_DQ57 WR_A_DQ56 WR_A_DQ55 WR_A_DQ54 WR
41. and will not have a MagniVu display value Group Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin Input Name Name Pin Input AChkBits CChkBits C_CB7 M D3 5 1 OFF OFF C_CB6 M D3 4 1 C CB5 D3 0 1 CB4 M D2 7 1 CB3 D3 6 1 C CB2 M_D3 341 C M Q0O 1 C D2 5 1 BChkBits DChkBits D CB7 5 D3 5 1 OFF OFF D_CB6 S_D3 441 D CB5 5 D3 0 1 D CB4 S D2 7 1 D CB3 S D3 6 1 D CB2 S D3 3 1 D CBI 5 0071 D_CB0 S_D2 541 ADatMsks BDatMsks b_DM8 BIN BIN b_DM7 b_DM6 b DM5 b_DM4 b_DM3 b_DM2 b DMI b DMO CDatMsks 161 D3 1 1 DDatMsks E d DMS S_D3 141 BIN 230 0 571 BIN d DM7 5 0 571 221 1 671 d_DM6 S_A1 641 212 DI 0 1 d DM5 S_D1 041 203 M_C2 041 d_DM4 S_C2 041 152 D2 2 1 d DM3 S D2 2 1 143 0371 d_DM2 5 0371 134 1 571 DMI 5 1 571 125 E0 6 d_DMO S_E0 6 Table 5 R_DDR3D_2A lt 1866 Read and Write Storage and Trigger Grouping cont d Notes 1 The M in front of a TLA channel denotes the Master card of the merged pair 2 The S in front of a TLA channel denotes the Slave card of the merged pair 3 Signals in these groups are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value Signal Name 1_0 CKE0_0 S3 0 S2 0 S1 _0 50 0 2 0 BAI 0 BAO 0 15 0 Al4 0 A13 0 12 0 A10 AP_0 RAS _0 CAS _0 WE _0 Address 0 BA2 0 Hex BAI 0 BAO 0 15 0 14 0 A13 0 12
42. channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set Signals in these groups are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value m Signal DDR3 TLA Name Pin Input Ungrouped PAR_IN_O 68 M_C1 2 PAR_IN_1 68 CI 2 1 ERR 0 53 5 A0 7 ERR 1 53 S_A0 741 TEST 0 167 5 7 TEST 1 167 _ 1 7 1 Group Name Ungrouped Signal Name RESET _0 RESET _1 ODT1_0 ODTI 1 ODTO 0 ODTO 1 DDR3 TLA Pin Input 168 S_A1 6 168 _ 1 6 1 77 C31 77 M _ 3 1 1 195 M_C3 2 195 M_C3 241 Table 3 B DDR3D 4D lt 1866MT s Read and Write Storage and Trigger Grouping cont d Notes 1 2 3 4 denotes low true signal The M in front of a TLA channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set Signals with a 1 suffix are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value Group Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin Input Name Name Pin Input ADataHi A_DQ63 A_DQ31 Hex A_DQ62 A_DQ30 DQ29 DQ60 A_DQ28 A_DQ59 A_DQ27 A_DQ58 A_DQ26 A_DQ57 A_DQ25 DQ56 A DQ24 A DQS5 A DQ23 DQS54 A DQ22 A DQS53 DQ2I A DQ52 DQ20 5 A_DQI9 A_DQ50 A_DQ18 A_DQ49 A DQI7 DQ48 A DQI6 DQ47 A_DQIS A_DQ46 A_DQI4 A_DQ45 A_DQ13 A_DQ44 012
43. different data group areas and what they mean 5 2 MagniVu Signals Because of the design of the Tektronix TLA7Bx4 acquisition cards different data groups need to be defined for use within MagniVu Table 6 shows the MagniVu group definitions in the B DDR3D 2D support Table 7 shows the MagniVu group definitions in the B DDR3D 4A support Table 8 the DDR3D IA support definitions Table 9 those for the DDR3D 2A support Group Signal TLA Group Signal TLA Name Name Input Name Name Input Data Hi DQ63 Data Lo DQ62 DQ30 2061 2029 2060 2028 2059 2027 2058 2026 2057 2025 2056 2024 2055 2023 2054 2022 2053 2021 2052 2020 2019 2050 2018 2049 2017 2048 2016 2047 2015 2046 2014 2045 5 2013 2044 2012 2043 2042 2041 DQ9 DQ40 208 2039 207 2038 DQ6 DQ37 DQ5 DQ36 DQ4 DQ35 DQ3 DQ34 DQ2 DQ33 2032 Table 6 B DDR3D 2D lt 1333MT s Read and Write MagniVu Channel Grouping Notes 1 The in front of a TLA channel denotes the Master card of the merged pair 2 The S in front of a TLA channel denotes the Slave card of the merged pair Group Signal TLA Group Signal TLA Name Name Input Name Name Input DataByte7 DQ63 DataByte3 DQ31 DQ62 DQ30 2061 0029 2060 2028 2059 2027 2058 2026 2057 0025 2056 2024 DataByte6 2055 DataByte2 DQ23 2054 2022 2053 2021 2052 2020 2051 2019 2050 2018 2049 2017 2048 2016 DataByte5 DQ47 DataBytel DQI5 DQ46 DQ14 DQ45 2013 2044 0012 2043 DQ11 DQ42 DQ1
44. location for best quality signal capture 101 APPENDIX D 240 pin DDR3 DIMM Pinout nnne nennen 102 APPENDIX E Data Flow Through the Probes coax cable to channel 104 APPENDIX F B_DDR3D_2D Support Prnout nein ania niece ead tides 106 APPENDIX G B_DDR3D_4A Support 108 APPENDIX H R_DDR3D_2A Support Pinout 110 APPENDIX I R_DDR3D_1A Support Pinout a asss 112 APPENDIX J Data Group Data Byte Strobe Cross Reference 114 APPENDIX K NEX DDR3INTR HS Silkscreen 115 APPENDIX L K ep out 116 APPENDIX M Simulation Modx l 117 APPENDIX References 118 usu eod 119 TABLE OF FIGURES Figure 1 7Bx4 Merged Module Configuration 11 Figure 2 Drawing of Interposer with probes attached 14 Figure 3 HCD connector on the LEASH probe aedis e Les 15 Figure 4 LEASH probe to HCD Probe
45. on a Command using NEX DDR3INTR HS Supports A Symbol Table has been included for the Control data groups defined in each of the support packages The Symbol Table for the X_DDR3D_XX supports is shown in Table 11 The use of Symbol Tables when triggering makes it easier for the user to define a given cycle to be triggered on Rather than trying to remember what signals make up the Control group the Symbol Table has the appropriate bits already set for the given cycle It is important to note that changing the channel definition of the Control group can result in incorrect symbol information being displayed Symbol Definition cc ssss x1 1110 for SO ssss 1 1101 for S1 cc ssss x1 1011 for S24 ssss 1 0111 for S3 x in Definition Don t Care MRS Sx MODE REGISTER SET REF Sx REFRESH PRE Sx SINGLE BANK PRECHARGE PREA Sx PRECHARGE ALL BANKS ACT ACTIVATE BANK WR Sx WRITE WRA Sx WRITE WITH AUTO PRECHARGE RD Sx READ RDA Sx READ WITH AUTO PRECHARGE 5 NO OPERATION DES DEVICE DESELECT ZQCL Sx ZQ CALIBRATION LONG ZQCS Sx ZO CALIBRATION SHORT CC SSSS XXX xxx xx000 CC SSSS xxx xx001 CC ssss xxx x0010 CC ssss xxx xxx x1010 5555 xxx 011 5555 x0100 5555 x1100 8888 xxx 0101 88885 xxx xxx 1101 8888 xx111 CC SSSS XXX XXXXX CC ssss xxx x
46. process To determine the Write Data group sample points first make an appropriate acquisition of Write data by triggering on a Write Command Then as above create a timing window display of MagniVu data and display the Data Hi Lo 32 bit data groups the individual Command group signals and the DDR3 clock that was used for the data acquisition DDRCKO NOTE As mentioned earlier it is important to note that because of the design of the TLA acquisition card inputs and the Strobe activity prior to Write data being placed on the data bus it will appear as if the Strobes indicate valid Write data earlier than the data is actually there see the circle indicated as Write Data Preamble in Figure 6 These Write Preamble Strobe edges should NOT be used to determine where valid Write data is on the data bus A sample waveform display of MagniVu Write data is shown in Figure 13 To determine the sample point locate the smallest window of valid Write data during the acquired burst see Figure 13 Note that in this instance the first piece of valid data happens before the rising edge it is associated with This shift must be taken into account or data will not be aligned properly in the Listing display window Note that and B data corresponding to A Data Hi Lo and Data Hi Lo data groups have been indicated Refer to section 5 6 for important information on properly determining the Write data sample points B DDR3HS MN XXX
47. set for any of the 8 bit data groups or for individual data bits Clock 1 1 1 Read i 4 RdA S amp H i RdB S amp H Write lt gt WrA S amp H lt WrB S amp H A 4 B DDR3D 4A R DDR3D 2A Acquisition The DDR3D 4A support requires four 4 merged TLA7Bx4 136 channel 1 4GHz TLA7BB4 acquisition cards used in a TLA7XX logic analyzer chassis and the R DDR3D 24A supports requires two 2 merged TLA7Bx4 136 channel 1 4GHz TLA7BB4 acquisition cards Data is captured using the rising edge of the DDR clock with data being stored every two DDR clocks Internal capabilities of the 7BB4 acquisition card are used to capture 4 samples of Read data two per DDR clock and 4 samples of Write data again two per DDR clock and then store that information in acquisition card memory RO Clock Read RdC S amp H RdA S amp H gt 1 RdB S amp H RdD S amp H The and sample points will be the same as will and D sample points APPENDIX B Setting Sample Capture Points in TLA V5 6 xxx Beginning with V5 6 of the TLA Application drastic changes were made in the User Interface One of the more important ones when it comes to Nexus DDR Memory Supports is where and how the sample points for the Read and or Write data groups are set For TLA Application versions V5 6 and later the sample points are set in the Setup window
48. the Tektronix TLA7BB4 acquisition modules While the Interposer specification is 1866 for UDIMMs the RDIMMs support have only been specified and validated to 1600 Contact Nexus for updates to this RDIMM specification Various Nexus and Tektronix probes interface between the Interposer and the Logic Analyzer Refer to the section below to match your needs This Interposer has been designed to provide a quick and easy connection between Tektronix TLA7BB4 Logic Analyzer acquisition cards and a 240 pin DDR3 Double Data Rate 3 bus Contact NEXUS Technology for other available DDR3 Products The Nexus Technology web site www NexusTechnology com contains information on the latest software release 1 2 Customer Product Acceptance Nexus Technology has designed this interposer to have a minimal effect in your target As with any interposer solution approximately one inch of trace length will be added between your target and the target DIMM Depending on the target layout memory controller DIMM type and DIMM socket being probed an interposer may affect the performance of your system All users are given 30 days to qualify the interposer in their system Should performance issues arise it is important to know that alternate solutions are available Nexus Technology offers NEXVu VDIMMs which provide both optimal probe points at the memory components and no added trace length or interposer effects Also available are memory component products which a
49. twice based on each rising edge of the DDR3 clock but data is stored every two clock cycles So to acquire both pieces of data the Write A Data Hi Lo and Write Data Hi Lo capture groups must have their sample point set to that shown by Sample Pt 1 in Figure 6 and the Write Data Hi Lo and Write D Data Hi Lo capture groups must have their sample point set to that shown in the Figure by Sample Pt 2 NOTE Because of the design of the TLA acquisition card inputs and the Strobe activity prior to Write data being placed on the data bus it will appear as if the Strobes indicate valid Write data earlier than the data is actually there see the circle indicated as Write Data Preamble in B_DDR3HS MN XXX 70 Doc Rev 1 40 Nexus Technology Company Confidential Figure 6 These Write Preamble Strobe edges should be used to determine where valid Write data is on the data bus 5 7 NEX DDR3INTR HS Support Setup Using any of the NEX DDR3INTR HS supports it is possible to acquire both Read and Write data by setting the sample point of the data groups appropriately The following explanation will permit a user to analyze acquired DDR3 data and determine what values to use in setting the Read data sample points To adjust the Read Data group sample points first make an appropriate acquisition of Read data by triggering on a Read command Then create a timing window display of MagniVu data and display the Data Hi and Data Lo
50. 0 DQ41 DQ9 DQ40 DQ8 DataByte4 DQ39 DataByteO DQ7 DQ38 DQ6 DQ37 DQ5 DQ36 DQ4 DQ35 DQ3 DQ34 DQ2 DQ33 201 2032 Table 6 B DDR3D 2D lt 1333MT s Read and Write MagniVu Channel Grouping cont d Notes 1 The in front of a TLA channel denotes the Master card of the merged pair 2 The S in front of a TLA channel denotes the Slave card of the merged pair Group Signal TLA Group Signal Name Name Input Name Name CheckBits DataMasks DM7 Strobes Address BA2 M A3 0 BAI C3 7 BAO 6 15 M_CKO Al4 M_A2 5 A13 12 A2 4 All M_A2 6 A10 AP M_C1 3 Control CKEI A9 M A2 1 CKEO 8 2 0 53 7 2 3 52 6 C0 2 Sl A5 22 SO A4 C0 5 BA2 A3 0 BAI A2 M 01 BAO Al Al5 AO M CI 5 14 Orphans PAR_IN M_C1 2 A13 ERR_OUT S_A0 7 A12 BC TEST S_A1 7 A10 AP RESET S_A1 6 RAS ODT1 M_C3 1 CAS ODTO M C32 WE Placeholder MISCO Placeholder DDRCKO 4 Table 6 B DDR3D 2D lt 1333MT s Read Write MagniVu Channel Grouping cont d Notes 1 denotes low true signal 2 The M in front of a TLA channel denotes the Master card of the merged pair 3 The S in front of a TLA channel denotes the Slave card of the merged pair 4 MISCI and MISCO are placeholders only and will not have interesting data on them Notes 1 2 3 4 Group Signal TLA Group Name Name Input Name RD
51. 1110 CC ssss xxx x0110 Table 11 NEX DDR3INTR HS Control Symbol Table Signals left to right CKE1 S3 52 51 S0 BA2 BAI BAO 15 A14 A13 A12 BC AIO AP RAS CAS WE 72 B DDR3D 2D R 1 Capturing MRS Mode Register Set Cycles If the characteristics of the DDR target latency burst length are not known it is possible to acquire this information using the TLA so that the post processing Control settings can be properly set This information is programmed into the DDR memory upon system boot by use of the MRS Mode Register Set command and is required when using the NEX DDR3INTR HS supports for the post processing software to properly decode the acquisitions The TLA trigger shown in Figure 23 can be used to acquire the MRS cycles when using either of these supports Note that because there is no Trigger event defined in this example that it will be necessary to Stop the TLA acquisition manually to display the MRS data A trigger could certainly be added in either or both of the Trigger events but the method shown ensures that the last valid MRS cycles will be acquired regardless of the memory depth setting of the acquisition card E off line Trigger DDR3D 2D I Ele Edit wew System Tools Window Help Fe ES E EE Explorer isetup I trigger MY Waveform i Listing Idle 54 Sample Point Import Tool E Protocol Designer 5 5 Analysis NEX DDR PROTOCOL iver
52. 29 E2 0 1 C DQ60 M_CK1 1 C_DQ28 M_E2 141 C_DQ59 M A0 2 1 C DQ27 D2 4 1 C DQ58 0 371 C_DQ26 D2 1 1 C 2057 M A0 7 1 C DQ25 E2 22 C DQ56 1 071 C_DQ24 M_E2 341 C_DQ55 2 1 C_DQ23 2 471 1 371 C_DQ22 M E2 5 1 C DQ53 1 771 C_DQ 21 M_E3 241 C_DQ52 C_DQ20 M E3 3 1 C DQ5I AL 1 1 C DQI9 E2 6 1 C 2050 1 471 C DQI8 E2 7 1 C DQ49 DI 7 1 C DQI7 M E3 1 1 C DQ48 M DI 6 1 C DQI6 M E3 4 1 C DQ47 DE 4 1 C DQI5 E3 6 1 C DQ46 M_D1 141 C DQI4 M E3 7 1 C DQ45 M D0 7 1 C DQI13 4 1 C DQ44 M D0 6 1 C DQI2 M_E1 141 C_DQ43 M_D1 341 C E3 5 1 C DQ42 M_D1 241 C DQIO _ 1 7 1 C_DQ41 M_D0 5 1 C_DQ9 _ 1 3 1 C_DQ40 M D0 4 1 C 8 _ 1 2 1 C_DQ39 M D0 3 1 C DQ7 C DQ38 M D0 2 1 C DQ6 M E0 7 1 C DQ37 M C2 1 1 C 0 371 C_DQ36 M_C2 4 1 C_DQ4 _ 0 2 1 C_DQ35 D0O 1 1 C DQ3 0271 C_DQ34 M D0 0 1 C DQ2 0 571 C_DQ33 M C2 6 1 C DQI E0 1 1 C DQ32 M_C2 741 C DQO M E0 0 1 Table 5 DDR3D 2 lt 1866MT s Read and Write Storage and Trigger Grouping cont d Notes 1 Allsignals this page are required for accurate post processing of acquired data 2 The M in front of a TLA channel denotes the Master card of the merged pair 3 signals on this page are stored in the 7Bx4 s Prime memory and will not have MagniVu display value Group Signal DDR3 TLA Group Signal DDR3 TLA Name Name Pin
53. 32 bit data groups the individual Command group signals and the DDR3 clock that was used for the data acquisition DDRCKO A sample waveform display of MagniVu Read data is shown in Figure 7 To determine the sample point locate the smallest window of valid Read data during the acquired burst see Figure 7 Note that in this instance the first piece of valid data happens significantly after the rising edge it is associated with In fact the initial valid data appears at the DDR Clock falling edge This delay must be taken into account or data will not be aligned properly in the Listing display window Note that A and B data corresponding to A and B data groups have been indicated A RD File Edit view Data System Tools Window Help 74 Sample Point Import Tool protocol Designer SE autoDeskew A il setup trigger M waveform Listing Idle 0 view a Magnivu activity OF Q Time Div 1 v n9 Search v amp v 9 f Cursor 2 14 96ns Waveform 3ns 4 500ns Ops 1 500ns 4 500ns 6ns 7 500ns 10 500 5 12ns 13 500ns 1515 16 500ns 18ns 19 500ns 21ns 22 500ns 24 4 003 ns H 24 297 ns 2 B Vu Address 00000 40006 00000 Latency expires Minimum lt Read Command _ Valid Read S amp H Data Begins Ep pivu Strobes 000 65b B pivu Data Hi 00000000 B miu Data 00000000 i B Iu Databyte7 o0 lt
54. 3_A0 2 RD DQ56 RD DQ24 S3 A033 RD DataByte6 RD DQ55 RD DataByte2 RD DQ23 RD DQ54 RD DQ22 RD DQ53 RD DQ21 RD DQ52 RD DQ20 RD RD DQI9 RD DQ50 RD DQI8 RD DQ49 RD DQI7 RD DQ48 RD DQI6 RD DataByte5 RD DQ47 RD DataBytel RD DQI5 RD DQ46 RD_DQ14 RD DQ45 RD DQI3 RD DQ44 RD DQI2 RD DQ43 RD DQII RD DQ42 RD DQIO RD DQ41 RD DQ9 RD DQ40 RD DataByte4 RD DQ39 DataByteO RD DQ38 RD DQ37 RD DQ36 RD DQ35 RD DQ34 RD DQ33 RD DQ32 Table 7 B DDR3D lt 1866MT s Read and Write MagniVu Channel Grouping cont d Notes 1 The M in front of a TLA channel denotes the Master card of the merged set 2 The S in front of a TLA channel denotes Slave card 1 of the merged set 3 The 52 in front of a TLA channel denotes Slave card 2 of the merged set 4 The S3 in front of a TLA channel denotes Slave 3 of the merged set Signal TLA Group Signal TLA Name Input Name Name Input WR Data WR DQ63 52 E2 0 WR Data Lo WR_DQ31 WR DQ62 WR DQ30 WR DQ6I WR DQ29 WR DQ60 WR DQ28 WR DQS9 WR DQ 7 WR 058 WR DQ26 WR DQS7 WR DQ25 WR DQS6 WR DQ24 WR DQS5 WR 023 WR DQS54 WR DQ22 WR DQS3 WR 021 WR DQ52 WR DQ20 WR DQS5I WR DQI9 WR DQS0 WR DQI8 WR DQ49 WR DQI7 WR DQ48 WR DQI6 WR DQ47 WR DQI5 WR DQ46 WR DQI4 WR DQ45 WR DQI13 WR DQ44 WR DQI2 WR DQ43 WR WR DQ42 WR DQIO WR DQ4I WR DQ9 WR DQ40 WR WR DQ39 WR DQ7 WR DQ38 WR WR DQ37 WR DQ5 WR DQ36 WR DQ4 WR DQ35 WR DQ3 WR D
55. DQ29 S3 0 071 WR D DQ60 52 271 WR_D_DQ28 S3 0 171 WR D DQS9 52 E0 2 1 WR D DQ27 S D2 4 1 WR D DQS 8 52 E0 3 1 WR D DQ26 S D2 1 l WR D 57 52 E0 7 1 WR D DQ25 S3 E0 2 1 WR D DQ56 52 1 071 WR_D_DQ24 S3 E0 3 1 WR D DQS 5 52 1 271 WR_D_DQ23 S3_E0 4A1 WR_D_DQ54 S2_E1 3A1 WR_D_DQ22 S3 0 571 WR D DQ 3 52 1 771 WR_D_DQ21 S3_E1 2A1 WR_D_DQ52 2_ 1 5 1 WR_D_DQ20 53 1 371 S2 1 121 WR_D_DQ19 S3 E0 6 1 WR D DQ50 52 1 471 WR_D_DQ18 S3 E0 7 1 WR D DQ49 2_ 1 7 1 WR D DQI7 3_E1 141 WR_D_DQ48 52 CI 6 1 WR D DQI6 S3_E1 4A1 WR_D_DQ47 S2_C1 4 1 WR D DQI5 S3 1 671 WR D DQ46 2_C1 141 WR_D_DQ14 53 1 771 WR_D_DQ45 52 0 771 WR_D_DQ13 3_ 1 4 1 WR_D_DQ44 52 0 671 WR_D_DQ12 S3_C1 1 1 WR_D_DQ43 2_ 1 3 1 S3 EL 5 1 WR D DQ42 52 CLI 2 1 WR DQIO 3_ 1 7 1 WR_D_DQ41 52 0 571 WR_D_DQ9 3_ 1 3 1 WR_D_DQ40 S2_C0 4A1 WR_D_DQ8 S3_C1 2A1 WR_D_DQ39 2_ 0 3 1 WR_D_DQ7 3_ 1 0 1 WR_D_DQ38 2_ 0 2 1 WR_D_DQ6 3_ 0 7 1 WR_D_DQ37 0 171 WR_D_DQ5 3_ 0 3 1 WR_D_DQ36 0 471 WR_D_DQ4 3_ 0 2 1 WR_D_DQ35 2_ 0 1 1 WR_D_DQ3 53 0271 WR_D_DQ34 2_ 0 0 1 WR_D_DQ2 53 0 571 WR_D_DQ32 E0 6 1 WR D 3_ 0 1 1 WR_D_DQ33 0 771 WR_D_DQ0 3_ 0 0 1 Table 3 B DDR3D 4D lt 1866MT s Read and Write Storage and Trigger Grouping cont d Notes 1 All signals on this page are required for accurate post processing of acquired data The M in front of TLA channel denotes th
56. DQSO 17 6 5 4 3 2 1 0 NEX DDR3INTR HS Groups Bytes Strobes Cross Reference APPENDIX NEX DDR3INTR HS Silkscreen Ewe o 00 0 33 LIN I T T nit 3 i Rights Reserved 7 Sepyriqhy C 2009 Made in U S 0 LL LL om GHz ERU Ie i 5 P Nexus Technology 1 S DORSINTR BB FHIN AOZ WWW NexusTechrology co a Front Silk screen APPENDIX L Keep out area CABLE EGRESS OUT OF TOP oF o9 es 4 8 46 44 0 g 8 e D N 430 110 92 1 2 973 75 51 2x 2463 62 56 2X 1 024 S 824 B 20 92 307 17 8 000 0 MOTHERBOARS Mae SURFACE o o ea 85 g2 35 e 3 Eg es RS Ne ss 1 ALL DIMS INCHES MM 2 CONNECTOR w OPEN LATCH OUTLINE NEXUS DDR3 INTERPOSER KEEPOUT VOLUME fae e SLIM VERSION STANDARD INTERPOSED DIMM CARD 116 Doc Rev 1 40 Nexus Technology Company Confidential B_DDR3HS MN XXX APPENDIX Simulation Model Double this if two Interposers are being used on the same memory channel DDR Straddle Connector 30 mOhm 3 18 nH Customer DDRDIMM DEM CE Cm td 96 96 ps td 175 68 ps 20 45 footprint 75 ohm impedance td 175 ps td 2100 ps td 288 ps 20 75 20 75 DDR3 signal
57. DR3HS MN XXX 76 Doc Rev 1 40 Nexus Technology Company Confidential Now the sample point for the Write Data Hi and Data Lo groups must be determined see Figure 15 The next valid Write data after the cycle measured above occurs approximately 500ps after the rising edge of DDRCKO so a suitable Setup amp Hold value for the Data Hi capture group would be 508ps 742ps As with the data the Data Lo group is somewhat later than the Data Hi group Data Lo valid time starts at approximately 800ps so suitable Setup amp Hold value for the Data Lo capture group would be 801ps 1 035ns e File Edit view Data System Tools Window Help 74 Sample Point Import Tool Protocol Designer iverify 143 AutoDeskew Setup trigger E Waveform 55 Listing ES Te Idle D amp x ia Magnivu I OF value Q Q Time Div 5005 w e He Search ay lI Cursor 1 tog Cursor 2 v 490ps Waveform P60ns 13 260ns 14 260ns 16 260ns 17 260ns 20 260ns 21 260ns Sai BP pvu Aggress 2 55555555 00000000 55555555 00000000 FFFFFFFF 55555515 55555555 00000000 55555555 00000000 FFFFFFFF 00 55 00 55 00 For Help press F1 11 Figure 15 Measuring NEX DDR3INTR HS B Data Hi Lo Write Data Setup amp Hold Now the sample point positions must be set for the A Data Hi Lo Data Hi Lo
58. Input Name Name Pin Input DDatHi D_DQ63 5 A0 0 1 DDatLo D DQ31 5 D2 6 1 Hex D DQ62 5 0 171 Hex D_DQ30 S D2 3 1 D_DQ61 S_A0 541 D_DQ29 5 E2 0 1 D DQ60 S D DQ28 S E2 1 1 D DQ59 5 A0 2 1 D DQ27 S D2 4 1 D DQ58 5 A0 3 1 D DQ26 S D2 1 1 D DQ57 5 A0 7 1 D DQ25 S E2 22 1 D DQ56 S_A1 041 D_DQ24 S_E2 341 D_DQ55 S_A1 241 D_DQ23 S_E2 441 D DQ54 _ 1 3 1 D_DQ22 S_E2 541 D DQ53 S_A1 741 D_DQ 21 S E32 1 D DQ52 5 _ 1 5 1 D_DQ20 S_E3 341 S_A1 141 D_DQ19 S 2 671 D DQ50 S_A1 441 D DQI8 S E2 7 1 D DQ49 S_D1 7 1 D_DQ17 S E3 1 1 D DQ48 S 1 6 1 D DQI16 S E3 4 1 D DQ47 S 1 471 D DQI5 S E3 6 1 D DQ46 S _ 1 1 1 D S E3 7 1 D DQ45 5 DO 7 1 D DQI3 S_E1 441 D_DQ44 5 D0 6 1 D DQI2 S_E1 141 D_DQ43 S DI 3 1 D S E3 5 D DQ42 S DI 2 1 D S EL7 1 D_DQ41 S_D0 541 D_DQ9 S_E1 341 D_DQ40 S_D0 441 D_DQ8 S_E1 241 D_DQ39 S _D0 341 D DQ7 S EL 0 1 D DQ38 5 _ 0 2 1 D DQ6 5 E0 7 1 D DQ37 _ 2 1 1 D_DQ5 S E0 3 1 D DQ36 _ 2 4 1 D_DQ4 S E0 2 1 D DQ35 S_D0 141 D_DQ3 5 0271 D DQ34 5 DO 0 1 D DQ2 _ 0 5 1 D_DQ33 5 2 61 D S_E0 141 D_DQ32 _ 2 7 1 D_DQ0 S E0 0 1 Table 5 DDR3D 2 lt 1866MT s Read and Write Storage and Trigger Grouping cont d Notes 1 All signals this page are required for accurate post processing of acquired data 2 The S in front of a TLA channel denotes the Slave card of the merged pair 3 Signals in these groups are acquired using the 7Bx4s s demux capability
59. MRSO decode error bit A15 or similar error may be displayed This happens when the offending Address bit is not in the state specified by JEDEC for MRS cycles Usually this error happens when A15 or another Address bit is acquired as being high during the MRS cycle rather than being low as the specification requires If this should happen the easiest temporary fix is to flip the polarity bit of the bad address bit in the Setup window so that the decode can proceed Don t forget to flip the polarity bit back to normal before continuing with the debug 7 6 MRS Decode Errors for Ranks other than 0 Some multi rank DDR3 DIMMs have some Address bits to their odd numbered ranks of memory chips swizzled In other words A3 from the target may be taken to A5 on the components etc Because of this the MRS decode for the odd ranks on such DIMMs will be incorrect But since all ranks of a DIMM will have the same Latencies Burst Lengths etc all of the necessary information for proper display decode can be gleaned from the SO MRS cycles 7 7 Thresholds Analog waveforms and their associated thresholds viewed using the Tektronix Analog Mux will display amplitudes and thresholds that are not an exact representation of the actual analog waveform The Nexus passive probes used on DDR3 NEX Vu and Interposer products are designed to supply maximum voltage swing to the Logic analyzer to insure correct digital signal swing capture at the high DDR3 rates Wh
60. NEXUS TECHNOLOGY NEX DDR3INTR HS DDR3 800 1866MT s Interposer For use with the TLA7Bx4 Logic Analyzer Modules Including these Software Support packages B DDR3D 4A DDR3D 2D DDR3D 2 Reduced Module Count support DDR3D Reduced Module Count support DDR3SPA Copyright 2010 Nexus Technology Inc All rights reserved Contents of this publication may not be reproduced in any form without the written permission of Nexus Technology Inc Brand and product names used throughout this manual are the trademarks of their respective holders B DDR3HS MN XXX 1 Doc Rev 1 40 Nexus Technology Company Confidential Warranty Terms and License Agreement For warranty terms refer to the Terms and Conditions of Sale document that was included in the product shipment The Software License Agreement is displayed during installation A hardcopy of that agreement may be obtained from Nexus Technology All Nexus Technology products to which this manual refers are subject to the Terms and Conditions of Sale document and the Software License Agreement as appropriate Compliance with WEEE and RoHS Directives This product is subject to European Union regulations on Waste Electrical and Electronics Equipment Return to Nexus Technology for recycle at end of life Costs associated with the return to Nexus Technology are the responsibility of the sender TABLE CONTENTS OVERVIEW lasa aoa 7 1 1 General
61. PENDIX B DDR3D 4A Support Pinout cont d TLA DDR3 TLA DDR3 Channel Signal Channel Signal P6962HCD 2X Probe Connection P6962HCD 2X Probe Connection for B_DDR3D_4A software for B DDR3D 4A software Coax P154 164 Coax P151 161 APPENDIX H R DDR3D 2 Support Pinout TLA Channel CB7 CB6 CB2 2058 DM8 CB5 CB4 DQ31 CBO DQ27 DQ30 DM3 DQ26 DQS3 15 TEST RESET CKE1 CKEO BA2 ERR_OUT All Al4 A12 BC 7 5 9 A8 P6960HCD 1X Probe Connection for R_DDR3D_2A software Coax P152 162 TLA Channel P6960HCD 1X Probe Connection for R_DDR3D_2A software Coax P153 163 APPENDIX H R_DDR3D_2A Support Pinout 4 TLA DDR3 TLA DDR3 Channel Signal Channel Signal P6960HCD 1X Probe Connection P6960HCD 1X Probe Connection for R_DDR3D_2A software for DDR3D 2 software Coax P154 164 Coax P151 161 APPENDIX I R_DDR3D_1A Support Pinout TLA DDR3 TLA DDR3 Channel Signal Channel Signal CB3 CB7 CB6 CB2 2058 DM8 CB5 CB4 DQ31 CBO DQ27 DQ30 DM3 DQ26 DQS3 15 TEST RESET 1 CKE0 BA2 ERR_OUT All 14 A12 BC NEX PRB1XL Probe Connection for NEX PRBIXL 1X Probe Connection for DDR3D 1 software DDR3D software Coax P152 162 Coax P153 163 APPENDIX I R_DDR3D_1A Support Pinout cont d TLA DDR3 TLA DDR3 Channel Signal Channel Signal NEX PRBIXL 1X Probe Connection NEX PRBIXL 1X Probe Connection
62. Q34 WR DQ2 WR DQ33 WR DQI WR DQ32 WR DQO Table 7 B DDR3D 4A 1866MT s Read and Write MagniVu Channel Grouping cont d Notes 1 The M in front of a TLA channel denotes the Master card of the merged set 2 The S in front of a TLA channel denotes Slave card 1 of the merged set 3 The 2 in front of a TLA channel denotes Slave 2 of the merged set 4 The S3 in front of a TLA channel denotes Slave 3 of the merged set Signal TLA Signal TLA Name Input Name Input WR_DataByte7 WR_DQ63 WR_DataByte3 WR_DQ31 S_C2 6 WR_DQ62 WR DQ30 S C23 WR DQ6I WR DQ29 53 E20 WR DQ60 WR DQ28 S3 21 WR DQS9 WR 5 C24 WR 058 WR DQ26 S C21 WR DQS7 WR DQ25 S3 E22 WR 056 WR DQ24 53 E23 WR DataByte6 WR DQS5 WR_DataByte2 WR_DQ23 WR 054 WR DQ22 WR DQS3 WR DQ 21 WR 052 WR DQ20 WR DQSI WR DQI9 WR 050 WR DQI8 WR DQ49 WR DQI7 WR DQ48 WR DQI6 WR DataByte5 WR DQ47 WR DataBytel WR DQI5 WR DQ46 WR DQI4 WR DQ45 WR DQI13 WR DQ44 WR DQI2 WR DQ43 WR WR DQ42 WR DQIO WR DQ4I WR DQ9 WR 40 WR WR DataByte4 WR DQ39 WR DataByteO WR DQ38 WR DQ37 WR DQ236 WR DQ35 WR DQ34 WR DQ33 WR DQ32 Table 7 B DDR3D 4A 1866MT s Read and Write MagniVu Channel Grouping cont d Notes 1 The M in front of a TLA channel denotes the Master card of the merged set 2 The S in front of a TLA channel denotes Slave card 1 of the merged set 3 The 52 in front of a TLA channel denotes
63. Q41 RD_A_DQ40 RD_A_DQ39 RD_A_DQ38 RD_A_DQ37 RD_A_DQ36 RD_A_DQ35 RD_A_DQ34 RD_A_DQ33 RD_A_DQ32 DDR3 TLA Input Pin Group Name RdA_DatLo Hex Signal Name RD A DQ3I RD DQ30 RD DQ29 RD DQ28 RD A DQ27 RD DQ26 RD DQ25 RD A DQ24 RD DQ23 RD A DQ22 RD A 021 RD DQ20 RD A DQI9 RD A DQI18 RD A DQI7 RD A DQI6 RD DQIS5 RD A DQI4 RD A DQI13 RD A DQI2 RD A RD A DQIO RD A DQ9 RD A DQ8 RD A DQ7 RD A DQ6 RD A DQ5 RD A DQ4 RD DQ3 RD A DQ2 RD A DQI RD A DQO DDR3 TLA Pin Input Table 2 B DDR3D 2D lt 1333MT s Read and Write Storage and Trigger Grouping signals on this page are required for accurate post processing of acquired data 2 The S in front of a TLA channel denotes the Slave card of the merged pair Signal DDR3 TLA Group Signal DDR3 TLA Name Pin Input Name Name Pin Input RdB_DatHi RD_B_DQ63 _ 2 0 1 RdB DatLo RD M 0 671 Hex RD B DQ62 _ 2 1 1 Hex RD B DQ30 0 371 RD_B_DQ61 5 2 571 RD B DQ29 _ 2 0 1 RD_B_DQ60 S_CK041 RD_B_DQ28 _ 2 1 1 RD_B_DQ59 S_A2 2A1 RD_B_DQ27 0 471 RD B DQ58 5 2 371 RD B DQ26 0 171 RD B DQ57 _ 2 7 1 RD_B_DQ25 _ 2 2 1 RD B DQ56 5 A3 0 1 RD B DQ24 _ 2 3 1 RD B DQ55 5 A3 2 1 RD B DQ23 _ 2 4 1 RD_B_DQ54 S_A3 3A1 RD_B_DQ22 _ 2 5 1 RD_B_DQ53 S_A3 741 RD B DQ21 5 C32 l RD B DQ52 S 1 571 RD B DQ20 S_C3 341 RD B DQS5I S A3 1 1 RD B DQI9
64. R DQ7 WR DQ6 WR DQ5 WR DQ4 WR DQ3 WR DQ2 WR DQI WR DQO DDR3 TLA Pin Input Table 3 B DDR3D 4 lt 1866MT s Read and Write Storage and Trigger Grouping cont d Notes l uc soto signals on this page are required for accurate post processing of acquired data The M in front of a TLA channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set The S2 in front of a TLA channel denotes Slave card 2 of the merged set The S3 in front of a TLA channel denotes Slave card 3 of the merged set Table 3 B DDR3D 4D lt 1866MT s Read and Write Storage and Trigger Grouping cont d Notes Wr_BDatHi Hex Signal Name WR_B_DQ63 WR_B_DQ62 WR_B_DQ61 WR_B_DQ60 WR_B_DQ59 WR_B_DQ58 WR_B_DQ57 WR_B_DQ55 WR DQ54 WR DQ53 WR B DQ3532 WR 5 WR DQ50 WR B DQ49 WR DQA48 WR DQ47 WR DQ46 WR DQ45 WR DQ44 WR B DQ43 WR DQ42 WR_B_DQ41 WR_B_DQ40 WR_B_DQ39 WR_B_DQ38 WR_B_DQ37 WR_B_DQ36 WR_B_DQ35 WR_B_DQ34 WR_B_DQ32 WR_B_DQ33 DDR3 TLA Input Pin Group Name Wr_BDatLo Hex Signal Name WR WR DQ30 WR DQ29 WR B DQ28 WR B DQ27 WR DQ26 WR DQ25 WR B WR DQ23 WR DQ22 WR B DQ21 WR DQ20 WR DQI9 WR DQIS8 WR B DQI7 WR DQI6 WR DQI5 WR B DQI4 WR DQI3 WR B DQI2
65. R3D 2A Even Write Addr Data BLA Trigger Designed to trigger on specific Write data written to a specific SO Write address for even latencies with a Burst Length of 4 B DDR3D 4A R DDR3D 2A Even Write Addr Data BLS Trigger Designed to trigger on specific Write data written to a specific SO Write address for even latencies with a Burst Length of 8 B DDR3D 4A R DDR3D 2A MRS Cycle Store Trigger Designed to acquire and store all SO and 51 MRS cycles Does not trigger the TLA it must be stopped manually B DDR3D 4A R DDR3D 2 Odd Read Addr Data BLA Trigger Designed to trigger on specific Read data from a specific SO Read address for odd latencies with a Burst Length of 4 B DDR3D 4A R DDR3D 2A Odd Read Addr Data BLS Trigger Designed to trigger on specific Read data from a specific 50 Read address for odd latencies with a Burst Length of 8 B DDR3D 4A R DDR3D 2 Odd Write Addr Data BLA Trigger Designed to trigger on specific Write data written to a specific SO Write address for odd latencies with a Burst Length of 4 DDR3D 4A R DDR3D 2 Odd Write Addr Data BL8 Trigger Designed to trigger on specific Write data written to a specific SO Write address for odd latencies with a Burst Length of 8 B DDR3D 4A R DDR3D 2A Read Command Trigger Designed to trigger on any 50 or S14 Read Command B DDR3D 4A R DDR3D 2A Write Command Trigger Designed to trigger on any SO or S1 Write Command So to tri
66. RDD RDD RDD RDD RDD RDD RDD RDD RDD RDD RDD RDD RDD RDD RDD RDD RDD Table 3 B DDR3D 4D lt 1866MT s Read and Write Storage and Trigger Grouping cont d Notes 1 Allsignals this page are required for accurate post processing of acquired data The in front of a TLA channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set The S2 in front of a TLA channel denotes Slave card 2 of the merged set The S3 in front of a TLA channel denotes Slave 3 of the merged set All signals on this page are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value D U es Wr_ADatHi Hex Signal Name WR_A_DQ63 WR_A_DQ62 WR_A_DQ61 WR_A_DQ60 WR_A_DQ59 WR_A_DQ58 WR_A_DQ57 WR_A_DQ56 WR_A_DQ55 WR DQ54 WR DQ53 WR DQ52 WR WR DQ50 WR DQ49 WR DQ48 WR DQ47 WR DQ46 WR DQ45 WR DQ44 WR DQ43 WR DQ42 WR_A_DQ41 WR_A_DQ40 WR_A_DQ39 WR_A_DQ38 WR_A_DQ37 WR_A_DQ36 WR_A_DQ35 WR_A_DQ34 WR_A_DQ33 WR_A_DQ32 DDR3 TLA Wr ADatLo Hex Signal Name WR_A_DQ31 WR_A_DQ30 WR_A_DQ29 WR_A_DQ28 WR_A_DQ27 WR_A_DQ26 WR_A_DQ25 WR_A_DQ24 WR_A_DQ23 WR_A_DQ22 WR DQ21 WR DQ20 WR DQI19 WR DQI8 WR DQ1I7 WR DQ16 WR DQI5 WR DQI4 WR DQI3 WR DQI2 WR WR DQIO WR DQ9 WR DQ8 W
67. Signal Type Cl 2 Qual 3 z s 4 Clock Qual E3 7 E3 6 5 4 E3 3 2 E3 1 E3 0 930 930 7 E 5 E 4 y 3 2 4 2 5 WR Q36 E2 3 E2 2 5 WR Q36 1 9 E21 3 21 2 1 WR Q36 1 WR Q32 1 WR Q36 1 ma l WR WR WR WR 037 Qu 9 0 a DM4 b pM4 c DM4 d DM4 gt nda 93 0 9210 1 P E1 5 E1 7 E1 4 E16 E1 2 E1 1 E1 0 7 Je e ae 5 4 Jee 2 1 1 o Et 0 0 5 0 3 0 2 E01 5 ED 3 ED 2 Rec Rec A3 6 6 al A3 5 4 ax 3 Ax 2 a A3 0 1 6 B_DDR3HS MN XXX I As 5 az 3 2 AS 0 as 1 Figure 11 NEX DDR3INTR HS Setup Window 74 Doc Rev 1 40 Nexus Technology Company Confidential Signal Sampling Group Sampler Definition Thresholds El 5 Support Defaults Close Figure 12 NEX DDR3INTR HS Read Data Capture Point Window Setting the Setup amp Hold values for acquiring Write data is a similar
68. Slave card 2 of the merged set 4 The S3 in front of a TLA channel denotes Slave 3 of the merged set Signal Name Name CheckBits DataMasks DM8 DM7 DM6 DM5 DM4 DM3 DM2 DM1 Strobes DMO Address BA2 BAI BAO 15 14 A13 12 11 Control CKEI 10 CKEO 9 S3 A8 S2 7 Sl SO 5 BA2 A4 BAI A3 BAO A2 Al5 Al Al4 AO A13 Orphans TEST 12 ERR_OUT A10 AP PAR_IN RAS RESET CAS ODTI WE ODTO DDRCKO M 4 Table 7 B DDR3D 4A 1866MT s Read and Write MagniVu Channel Grouping cont d Notes 1 denotes low true signal These signals are required for accurate determination of sample points The M in front of TLA channel denotes the Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set The S2 in front of a TLA channel denotes Slave card 2 of the merged set The S3 in front of a TLA channel denotes Slave 3 of the merged set Tuto Group Signal TLA Group Signal TLA Name Name Input Name Name Input Data_Hi DQ63 Data_Lo DQ31 DQ62 DQ30 DQ61 DQ29 DQ60 DQ28 DQ59 DQ27 0058 2026 2057 0025 0056 2024 0055 2023 2054 2022 0053 2021 2052 2020 0051 2019 0050 2018 2049 2017 2048 2016 2047 2015 2046 2014 2045 2013 2044 2012 2043 2011 2042 2010 2041 209 2040 208 2039 207 0038 DQ6 DQ37 DQ5 DQ36 DQ4 DQ35 DQ3 DQ34 DQ2 DQ33 DQI DQ32 DQO Table 8 R DDR3D
69. The X clock cycle value is determined by adding the maximum Burst Length of 8 clock cycles to the selected maximum Read Latency So for selected Total Latency of lt 5 cycles the support software will store a total of 13 clock cycles worth of data after the Read or Write Command appears on the bus Refresh Cycles Permits choosing whether Refresh Cycles will be stored or not The field choices are Acquire default Refresh Cycles will be stored Do Not Acquire This mode will reduce the number of Refresh cycles stored by the acquisition card to provide optimum use of the acquisition memory NOTE This mode is disabled when the SDRAM Clocking choice is set to a Every Rising Edge selection 4 2 B_DDR3D_4A Clocking Selections There is one clocking option field available when using the BLDDR3D_4A support package These select fields permit the user to setup the TLA acquisition as follows SDRAM DDR CLKO Clocking Permits selecting the Clocking Mode to be used to acquire DDR3 data It is important to note that the selection chosen will force unused Chip Selects and CKEI into inactive states The field choices are S0 Every Rising Edge default Clocks data using every rising edge of DDR Clock 0 Forces low and S1 3 high No Idle Cycle filtering is done 50 amp S1 Every Rising Edge Clocks data using every rising edge of DDR Clock 0 Forces S2 3 high No Idle Cycle filtering is done S0 3 Ever
70. _S DQ21 S DQ52_S DQ20_S DQS51_S DQ19_S DQ50_S DQ18_S DQ49_S DQ17_S DQ48 S 16 S DataByte5 S DQ47 S DataBytel S DQI5 S DQ46 S DQI4 S DQ45 S DQI3 S DQ44 S DQI2 S DQ43 S S DQ42 S DQIO S DQ41_S DQ9_S DQ40_S DQ8_S DataByte4_S DQ39_S DataByte0_S DQ38_S DQ37_S DQ36_S DQ35_S DQ34_S DQ33_S DQ32_S Table 9 R_DDR3D_2A lt 1333MT s Read and Write MagniVu Channel Grouping cont d Notes 1 The S in front of a TLA channel denotes the Slave card of the merged pair Signal DDR3 TLA Signal DDR3 TLA Name Pin Input Name Pin Input Control BA2 CKEO BAI 53 S2 15 51 14 0 13 BA2 A12 BC BAI All BAO A10 AP Al5 9 14 A8 A13 7 A12 BC A10 AP A5 RAS CAS A3 WE CheckBits_M DataMasks M E 161 D3 1 230 A0 5 221 AI 6 212 M DI 0 203 C2 0 152 M D2 2 143 Q3 134 5 125 M_E0 6 161 S_D3 1 230 S_A0 5 221 S_A1 6 212 S_D1 0 203 S_C2 0 152 S_D2 2 143 S_Q3 134 S_E1 5 125 S E0 6 ODT ODTI 77 M_C3 1 ODTO 195 M_C3 2 Orphans TEST 167 M_A3 7 ERR_OUT 53 A2 7 PAR IN 58 M CI 2 RESET 49 M_A3 6 lt ON lt CheckBits_S D D DM DM DM DM DM DM 5 4 3 2 1 0 DataMasks S Strobes lt lt lt lt z lt lt lt NU Q lu ka lt n Table 9 R_DDR3D_2A lt 1866MT s Read and Write Storage and Trigger Grouping cont d
71. a 3 at the edge connector of the DIMM CLK 80 Diff Control Address CMD 45 DM DQ 60 gt DOS diff 87 5 Replace 75 ohm resistor with Tektronix input load model B DDR3HS MN XXX 117 Nexus Technology Company Confidential 1 06 mM board to be added Samtec td 10500 ps Connector 20 75 Pair 34 AXG Coax B 75 Ohm1 Logic AnNyZer load connector Pair i 3A AWG coax Doc Rev 1 40 APPENDIX References JEDEC PC3 6400 PC3 8500 10660 DDR3 SDRAM Unbuffered DIMM Design Specification Revision 0 1 March 20 2006 Tektronix TLA7000 Series Installation Manual Tek part number 071 1747 03 Tektronix TLA7000 Series Technical Reference Manual Tektronix part number 071 1764 00 Nexus Low Profile Distributed Probe Manual Part number LowProfileProbes MN X XX JEDEC DDR3 SDRAM Standard JESD79 3 June 2007 PPENDIX Support About Nexus Technolosy Inc NEXUS TECHNOLOGY Established in 1991 Nexus Technology Inc is dedicated to developing marketing and supporting Bus Analysis applications for Tektronix Logic Analyzers We can be reached at Nexus Technology Inc 78 Northeastern Blvd 2 Nashua NH 03062 TEL 877 595 8116 FAX 877 595 8118 Web site http www nexustechnology com Support Contact Information Technical Support techsupport nexustechnology com General Information support nexustechnology com Quote Requests quotes nexustech
72. ad to the DDR3 Interposer s LEASH soldered on coax cable that is attached to the P153 163 Coax cable on the Interposer Connect the NEX PRB2XL 2 amp A1 0 probe head to the DDR3 Interposer s LEASH that is attached to the P152 162 Coax cable on the Interposer Match the label on the end of the NEX PRB1XL 2XL probes with the labels on the front of the Tektronix Logic Analyzer Master module and connect TLA Slave Connect the NEX PRB2XL 2 amp 1 0 probe head to the DDR3 Interposer s LEASH soldered on coax cable that is attached to the P154 164 Coax cable on the Interposer Connect the NEX PRB2XL 3 2 amp E3 2 probe head to the DDR3 Interposer s LEASH that is attached to the P151 161 Coax cable on the Interposer See Figure 2 for connections Table 2 shows the Channel Grouping Wiring for use with the B DDR3D 2D support 3 3 B DDR3D 4A Support To acquire DDR3 Read and Write data at speeds up to 1866MT s requires four merged TLA7BB4 136 channel logic analyzer modules each having the 1 4GHz state speed option Referring to Figure 1 the Master TLA7BB4 card is in the second to lowest numbered slot second from the left of the four modules Slave Module 1 will be in the adjacent high numbered slots Slave Module 2 is in the lowest numbered slots and Slave Module 3 is in the highest numbered slots System Configuration Signals Merge Modules i
73. addition to these Disassembly Properties selections changing the settings in the Show field results display changes as well Hardware default displays all acquired cycles Software suppresses all idle or wait cycles Control Flow shows Address Command and valid Read Write data cycles Subroutine shows valid Read Write data cycles only DDR3 List mu che ES Xe Si activity 1 90 9 Search Ot Cursor 1 Mii Cursor 2v 9ns C1 0 2 C2 2 Delta Time DDR3UA3A DDR3UA3A DDR3UA3A DDR3UA3A DDR3UA3A DDR3UA3A DDR3UASA S see Address Mnemonics DataHi Datalo DataMasks c3 YNN____________ vb o 5 9 8 Ss 5ASES OOOOFFOO ooFFOODO OOFFFFOO 00FF0000 OOOOFFOO 00FF0000 00000000 FFFF00FF OOOOOOFF FFFFFFOO 00000000 00000000 FF000000 00FFFF00 FFOOOOFF OOFFFFFF FFFFFFOO OOFFOOFF FFFFOOFF FFFFFFFF FF000000 000000FF OOFFFFOO FFOOOOFF OOOOFFFF FFOOOOFF FF000000 OOOOFFOO FF000000 OOFFOOFF FFFFOOFF FFOOOOFF 00000000 00FF0000 FFFFFF00 FF000000 FFOOOOFF OOOOFFFF FFOOOOOO FFFFFFFF OOFFFFOO FF000000 FFFFFFFF 000000FF OOOOFFOO 0000FF00 OOFFFFFF 00000000 FFFFOOFF 00000000 FF000000 FF000000 FFFFFFOO FFFF0000 OOFFFFOO OOFFOOFF OOFFOOFF FFOOFFOO FFFFOOOO FFFFOOOO OOFFFFFF FF000000 FFFFFFOO OOFFOOOO OOOOOOFF FFFFFFOO 00000000 00000000 FFOOFFFF FFFF0000 FFFFOOOO OOFFFFFF FFFFOOOO 00FF0000
74. alue to the CAS Latency value and adding one if Registered memory RDIMMs are being used resulting in the total number of clock cycles from the Read Command to the first valid Read Data If these values are not known the technique described in Section 7 3 can be used to determine the necessary values with the exception of whether or not the memory is RDIMM or UDIMM In Figure 5 the total Read latency is 6 cycles The B_DDR3D_2D and R DDR3D 14A supports sample Read data at two separate times based on each rising edge of the DDR3 clock and stores data every clock cycle So to acquire both pieces of data the Read A Data Hi Lo capture groups must have their sample point set to that shown by Sample Pt 1 in Figure 5 and the Read Data Hi Lo capture groups must have their sample point set to that shown by Sample Pt 2 The B_DDR3D_4A and R_DDR3D_2A supports sample Read data on each rising edge of the DDR3 clock but data is stored every two clock cycles So to acquire both pieces of data the Read Data Hi Lo and Read Data Hi Lo capture groups must have their sample point set to that shown by Sample Pt 1 in Figure 5 and the Read Data Hi Lo and Read D Data Hi Lo capture groups must have their sample point set to that shown in the Figure by Sample Pt 2 RD El File Edit View Data System Tools Window Help 74 Sample Point Import Tool B Protocol Designer iverify SW autoDeskew ZX Setup trigge
75. capture groups in the Setup window Each 32 bit data group will require its own value programmed from the measurements noted in the MagniVu window Note that if the Upper Strobes are being used as Data Masks then the WrtMasks group should have a Setup amp Hold value that matches that of the Write Data groups The sample point positions must now be set for the capture groups in the Setup window Note that if the Upper Strobes are being used as Data Masks then the WrtMasks group should have a Setup amp Hold value that matches that of the Write Data groups B_DDR3HS MN XXX 77 Doc Rev 1 40 Nexus Technology Company Confidential Signal Sampling Group Sampler Definition Open Thresholds 5 Support Defaults Close Redo Figure 16 NEX DDR3INTR HS Write Data Capture Point Window Because of the speeds of DDR3 data it may be necessary to program Setup amp Hold values for each of the 8 bit groups that are associated with a given Strobe This could be required if there is significant skew between the DDR Strobes Figure 17 shows some of these additional data groups DataByte7 0 added to the same Waveform display shown in Figure 17 Note that it is now possible to determine the skew between data groups and place these values into the Setup amp Hold Window settings in the TLA Setup window see Figure 18 Refer to Appendix F Data Group Byte Strobe Cross Reference for detai
76. ckmg Selections civics veh ta den pun I sett edet rite ode pete pede 47 4 2 B_DDR3D_4A Clocking Selections 48 43 DDR3D 1A Clocking Selections eet t terti esee 48 44 R_DDR3D Clocking Selections 49 5 0 CONFIGURING FOR READ WRITE DATA ACQUISITION 51 5 1 A Note About the Different Data 51 52 5 3 Adjusting Input Thresholds for Proper Data Acquisition 68 5 3 1 Thresholds for NEX PRB1XL PRB2XL Probes 68 5 3 2 Thresholds for Tektronix 9 eorr ede he ee 68 DDR3 and DDR SSPA 68 5 5 Selecting NEX DDR3INTR HS Read Data Sample Points 68 5 6 Selecting NEX DDR3INTR HS Write Data Sample Points 70 5 7 NEX DDR3INTR HS Support 71 6 0 VIEWING DA TA 80 6 1 Viewing NEX DDRSINTR HS RG eas 80 6 2 Viewing Raw DDR3 Data using NEX DDR3INTR HS XX Supports 83 6 3 NEX DDR3INTR HS Mnemonics Description
77. ct Nexus for any updates Figure 2 below shows the location on the Interposer of the LEASH probe connections Location of HCD connectors right under metal compression plate and probe tip board P151 161 PRIMARY SIDE VIEW Figure 2 Drawing of Interposer with probes attached The four 4 each 1 foot long LEASH probes that are soldered onto the Interposer are in turn connected to a variety of probes listed in Sections 3 1 3 6 These probes in turn connect to the input of the logic analyzer modules The connection between the LEASH Probes and the logic Analyzer is an HCD connector with a pinout as shown below on the LEASH probe The strain relief on the LEASH to probe interface while designed for bench handling can be damaged by twisting the coax cables Bends of over 45 degrees in this area should be avoided The coax connection points are not to be bent under any circumstances 3 6 1 HCD connector on the LEASH probe pins GND J15 2 GND J15 5 GND J15 8 GND 15 11 GND J15 14 GND J15 17 GND 2 GND J15 4 GND 15 7 GND 15 10 GND J15 13 GND 15 16 GND VTT GND E1 GND J15 3 GND J15 6 GND J15 9 GND J15 12 GND J15 15 GND J15 18 GND D1 GND J16 18 GND J16 15 GND J16 12 GND J16 9 GND J16 6 GND J16 3 GND GND VTT GND J16 16 GND J16 13 GND J16 10 GND J16 7 GND J16 4 GND C1 GND J16 17 GND J16 14 GND J16 11 GND J16 8 GND J16 5 GND J16 2 GND B1 A1 Figure 3 HCD connector on the LEASH probe Each LEASH probe connec
78. d set The S3 in front of a TLA channel denotes Slave 3 of the merged set Signals in these groups are acquired using the TLA s demux capability and will not have a MagniVu display value Signals in these groups are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value Group Signal DDR3 TLA Signal DDR3 TLA Name Name Pin Input Name Pin Input Control 0 CKEI 0 Control 1 1 S AL2 1 SYM CKEO 0 SYM CKEO 1 S_A1 141 S3 _0 S3 _1 M C2 5 1 2 0 52 1 M C3 0 1 51 0 1 1 M 3 4 1 50 0 50 1 M 3 3 1 BA2_0 BA2_1 S_A1 041 BAI 0 BAI 1 M C3 7 1 BAO 0 BAO 1 M CI 6 1 A15 0 A15 1 S 14 0 A14 1 S A0 5 1 A13 0 A13 1 CK 1 A12 BC 0 A12 BC _1 5 A0 4 1 A10 AP 0 A10 AP_1 M_C1 341 RAS _0 RAS _1 M C3 6 1 CAS t 0 CAS 1 M C3 5 1 WE 0 WE 1 M CI 7 1 Address 0 BA2_0 Address 17 BA2 1 5 AL O 1 Hex BAI 0 Hex 1 M 3 7 1 BAO 0 BAO 1 M CI 6 1 A15 0 A15 1 S CKI I 14 0 A14 1 5 A0 5 1 A13 0 A13 1 M_CK3 1 A12 BC _0 A12 BC _1 5 A0 4 1 A11 0 111 5 A0 6 1 A10 AP 0 A10 AP_1 M_C1 341 S_A0 141 5 A0 0 1 5 A0 3 1 M C0 2 1 5 0 271 _ 0 5 1 _ 1 0 1 0171 M_C1 141 571 Table 3 B DDR3D 4 lt 1866MT s Read Write Storage and Trigger Grouping 4 Notes 1 denotes low true signal These signals are required for accurate acquisition and post processing of acquired data The in front of a TLA
79. e Master card of the merged set The S in front of a TLA channel denotes Slave card 1 of the merged set The S2 in front of a TLA channel denotes Slave card 2 of the merged set The S3 in front of a TLA channel denotes Slave card 3 of the merged set All signals on this page are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value DNS p Signal DDR3 TLA Signal DDR3 TLA Name Pin Input Name Pin Input Rd_AChkBits RDa_CB7 Wr_AChkBits WRa_CB7 OFF RDa_CB6 OFF WRa_CB6 5 WRa CB5 RDa CB4 WRa 4 RDa_CB3 WRa_CB3 RDa_CB2 WRa_CB2 RDa_CB1 WRa_CB1 RDa_CBO WRa CBO Rd BChkBits RDb CB7 5 D3 5 Wr BChkBits WRb S CL5 OFF RDb CB6 S D3 4 OFF WRb CB6 S CL4 RDb 5 S D3 0 WRb 5 5 0 RDb CB4 S D2 7 WRb CB4 5 C0 7 RDb CB3 S D3 6 WRb CB3 5 6 RDb_CB2 S_D3 3 WRb_CB2 S_C1 3 RDb_CB1 5 QI WRb 5 Q2 RDb CBO S D2 5 WRb_CBO _ 0 5 Rd_CChkBits RDc_CB7 5 A3 5 Wr_CChkBits WRc_CB7 S C3 5 1 OFF RDc CB6 5 A3 4 l OFF WRc 6 5 C3 4 1 RDc CB5 5 A3 0 1 WRc CB5 5 C3 0 1 RDc CB4 _ 2 7 1 WRc_CB4 _ 2 7 1 RDc_CB3 _ 6 1 WRc_CB3 _ 3 6 1 RDc_CB2 S_A3 3A1 WRc_CB2 _ 3 3 1 S_CK041 WRc_CB1 S_CK341 RDc_CB0 _ 2 5 1 WRc_CB0 _ 2 5 1 Rd_DChkBits RDd_CB7 S D3 5 Wr_DChkBits WRd 7 S 1 5 1 OFF RDd CB6 S D3 4 OFF WRd CB6 _ 1 4 1 RDd CB5 S D3 0 1 WRd 5 _ 1 0 1 RDd_CB4 _02 7 1 WRd_CB4 _ 0 7 1 RDd_CB3 S D3 6 1 WRd CB3 _ 1 6 1
80. e Pin Input Name RdAChkBits RD_A_CB7 WrACHhkBits WR_A_CB7 OFF RD_A_CB6 OFF WR_A_CB6 RD A CB5 WR 5 RD A 4 WR 4 CB3 WR RD A CB2 WR A CB2 RD A CBI WR A RD A WR RdBChkBits 4 RD B CB7 _ 1 5 1 WrBChkBits 4 WR B CB7 M_D1 541 OFF RD B CB6 M OFF WR B CB6 M_D1 4 1 RD B CB5 M AL 0 1 WR B CB5 M DI 0 1 RD B CB4 M 0 771 WR B CB4 D0 7 1 RD B CB3 1 671 WR_B_CB3 DI 6 1 RD B CB2 1 371 WR_B_CB2 M_D1 341 RD_B_CB1 WR M _00 1 RD_B_CBO _ 0 5 1 WR_B_CB0 0 571 ADatMsks BDatMsks BIN BIN S_A2 4A1 S_A3 641 S_A1 041 M_C2 041 A0 2 1 _ 1 S_E3 541 5 2 671 SESEL LSR LSLS UJ w Ud w w C0 x Table 2 B_DDR3D_2D lt 1333MT s Read and Write Storage and Trigger Grouping 4 Notes 1 denotes low true signal 2 The M in front of a TLA channel denotes the Master card of the merged pair 3 The S in front of a TLA channel denotes the Slave card of the merged set 4 Signals in these groups are acquired using the 7Bx4 s demux capability and will not have a MagniVu display value Group Signal DDR3 TLA Group Signal Name Name Pin Input Name Name Control CKEI M A32 Address BA2 SYM CKEO BAI S34 BAO 2 15 51 14 0 A13 BA2 A12 BC BAI All BAO 15 9 14 8 13 7 A12 BC A6 A10 AP AS RAS A4 CAS A3 WE A2 Strobes Al
81. e folder of the support to be installed DDR3D 2D B_DDR3D_4A R_DDR3D_1A or DDR3D 24A and then run the MSI file within the folder The selected software will be installed on the TLA s hard disk To load the support into the TLA first select the desired Logic Analyzer module different supports require different module counts in the Setup window select Load Support Package from the File pull down then choose the name of the software package you want to load and click on Okay Note that the TLA acquisition cards must be properly configured for the selected support package to load properly 3 0 CONNECTING to the NEX DDR3INTR HS INTERPOSER 3 1 General Care should be taken to support the weight of the acquisition probes so that the Logic Analyzer Interposer board and or target DIMM socket are not damaged For NEX PRBIXL 2XL probe labeling please refer to the Low Profile Probes manual LowProfileProbes MN XXX from Nexus 3 2 B DDR3D 2D Support To acquire DDR3 Read and Write data at speeds up to 1333MT s requires two merged TLA7BB4 136 channel 750MHz or 1 4GHz acquisition cards and the DDR3D 2D support software The Master card will be in the lower numbered of the two cards and the Slave card is in the adjacent high numbered slots The logic analyzer modules should be connected to the DDR3 DIMM Interposer as follows using 1 NEX PRB1XL probes and three 3 NEX PRB2XL probes TLA Master Connect the NEX PRBIXL probe he
82. e stored in the A3 A3B prime channels D3 and D3B sections A very useful side benefit of using demux is that since only one set of TLA data channels has to be connected only one probe load is added to the target even though data is stored in two or four different locations of the acquisition card A 2 DDR Acquisition General All of the above is background necessary to understand how the TLA is able to acquire data at rates that initially look too fast The speeds of DDR3 1066 MT s require different setups to enable proper data acquisition In addition instead of trying to use the 8 Data Strobes to acquire data our solution uses CLKO of the DDR SDRAM Clocks and all data acquisition is adjusted in relation to the clock edges The 8 Data Strobes cannot be easily used to acquire data as some TLA configurations only support 4 Clock Inputs Also the Strobes cannot be used to acquire Address and Command information B DDR3D _2D R_DDR3D_1A Acquisition The B_DDR3D_2A support requires two 2 merged TLA7Bx4 136 channel 750MHz or 1 4GHz TLA7BB4 acquisition cards used in a TLA7XX logic analyzer and the R DDR3D 1A support requires a single TLA7Bx4 136 channel 750MHz 1 4GHz acquisition card Data is acquired using the rising edge of the DDR clock A_Data information is earlier older data than the information stored in B_Data Different Sample Points must be set for each of the four 32 bit Data groups and if necessary sample points can be
83. ecific Read data the trigger in Figure 277 could be used when dealing with odd latency values B DDR3HS MN XXX 90 Doc Rev 1 40 Nexus Technology Company Confidential TLA off line Trigger B_DDR3D_4A JE Fie view System Tools Window Help BES 9 E epore MS waveform Status ide 7 Sample Point Import Tool Si Protocol Designer 5 S H Analysis 171 Def Dy Ley X B Storage Force Main Prefil Trigger Pos Magnu 20ps Magnu Trigger Pos J 44 Trigger on Read from specific address and data with odd latency 5 is example used Burst Length 4 Group Control_O ACT SOH BANK ACTIVATE And Group Address_0 Reset Counter 1 And Go To 2 Else If Group Control 1 ACT 508 BANK ACTIVATE And Group Address_1 Then Reset Counter 1 And Go To 2 Wait for Read Command Group Control 0 RD 508 READ And Group Address_0 OO Inc Counter 1 And Go To 4 Group Control 1 RD 508 READ And Group Address 1 BoTo3 Group Control 0 ACT 508 BANK ACTIVATE And Group Address 01 BoTo1 Group Control 1 ACT 508 BANK ACTIVATE And Group Address 1 OX 1 State 3 when Read Command was in second clock cycle Count Latency 1 2 Look for Read Data i
84. es are S0 Every Rising Edge default Clocks data using every rising edge of DDR Clock 0 Forces low and S1 3 high No Idle Cycle filtering is done S0 amp S1 Every Rising Edge Clocks data using every rising edge of DDR Clock 0 Forces S2 3 high No Idle Cycle filtering is done S0 3 Every Rising Edge Clocks data using every rising edge of DDR Clock 0 No Idle Cycle filtering is done S0 Total L lt 5 utilizes Selective Clocking to reduce acquisition of Idle bus states Forces 1 low and 1 3 high S0 amp S1 Total lt 5 utilizes Selective Clocking to reduce acquisition of Idle bus states Forces S2 3 high S0 3 Total L lt 5 utilizes Selective Clocking to reduce acquisition of Idle bus states 0 Total L lt 6 S0 amp 814 Total L lt 6 0 3 Total L lt 6 0 Total L lt 25 50 amp S12 Total L lt 25 0 3 Total L lt 25 The above selections reduce the number of Idle cycles stored by the acquisition card to provide optimum use of the acquisition memory Data is stored whenever RAS or CAS is asserted low along with a valid Chip Select After every assertion of CAS paired with a valid Chip Select samples are taken during the next X DDR Clock cycles to ensure that all valid memory cycles have been acquired The acquisition then pauses and waits for the next Command If CAS and a Chip Select are asserted during these X clock cycles the count is reset
85. for R_DDR3D_1A software for R DDR3D 14 software Coax P154 164 Coax P151 161 APPENDIX J Data Group Data Byte Strobe Cross Reference 32 bit Data Group 8 bit Data Group Strobe Data Bits RdADatHi RdADatB7 DQS7 63 62 61 60 59 58 57 56 RdADatB6 DQS6 55 54 53 52 51 50 49 48 RdADatB5 DQS5 47 46 45 44 43 42 41 40 RdADatB4 DQS4 39 38 37 36 35 34 33 32 RdADatLo RdADatB3 DQS3 31 30 29 28 27 26 25 24 RdADatB2 2052 23 222 21 20 19 18 17 16 RdADatB1 DQS1 15 14 13 12 11 10 9 8 RdADatBO DQSO 17 6 5 4 3 2 1 0 WrADatHi WrADatB7 DQS7 63 62 61 60 59 58 57 56 WrADatB6 DQS6 55 54 53 52 51 50 49 48 WrADatB5 DQS5 47 46 45 44 43 42 41 40 WrADatB4 DQS4 39 38 37 36 35 34 33 32 WrADatLo WrADatB3 DQS3 31 30 29 28 27 26 25 24 WrADatB2 2052 2322 21 20 19 18 17 16 WrADatBl DQS1 15 14 13 12 11 10 9 8 WrADatBO DQSO 17 6 5 4 3 2 1 0 RdBDatHi RdBDatB7 DQS7 63 62 61 60 59 58 57 56 RdBDatB6 DQS6 55 54 53 52 51 50 49 48 RdBDatB5 DQS5 47 46 45 44 43 42 41 40 RdBDatB4 DQS4 39 38 37 36 35 34 33 32 RdBDatLo RdBDatB3 DQS3 31 30 29 28 27 26 25 24 RdBDatB2 2052 23 22 21 20 19 18 17 16 RdBDatB1 DQS1 15 14 13 12 11 10 9 8 RdBDatBO DQSO 17 6 5 4 3 2 1 0 WrBDatHi WrBDatB7 DQS7 63 62 61 60 59 58 57 56 WrBDatB6 DQS6 55 54 53 52 51 50 49 48 WrBDatB5 DQS5 47 46 45 44 43 42 41 40 WrBDatB4 DQS4 39 38 37 36 35 34 33 32 WrBDatLo WrBDatB3 DQS3 31 30 29 28 27 26 25 24 WrBDatB2 DQS2 23 22 21 20 19 18 17 16 WrBDatB1 DQS1 15 14 13 12 11 10 9 8 WrBDatBO
86. ga 2 921 21 0 1 0 53 52 51 50 2 1 MSB E2 7 E2 6 2 5 E2 4 A Ez 21 7 6 21 5 Ez 4 Nene Ez 2 l 21 1 6 9 5 4 ol 3 1 I E1 7 103 PES E1 1 020 920 0 7 0 6 0 5 Eo 200 0 2 1 CKE0 S34 S24 S14 50 2 BAL BAO AIS 14 AS Ai ALAF RASH CASH I A 9 Wewa sak WE LsB al A15 RD_A_DQ63 RD_A_DQ62 RD_A_DQ61 RD_A_DQ60 RD_ Qz EQ 7 E0 4 Heng G 4 9 3 RESET 43 5 Ax4 Max A3 7 I 0 IA 1 2 7 Haag Haag 1 4 Harga 1 2 Nara 0 Figure 32 B DDR3D 2D Setup Window TLA V5 6 or later In the lower right portion of the window is a scroll field Scroll down until grayed out groups are visible then select the group in which the sample points are to be selected see Figure 33 Clicking on the Rising Falling Edge icon red arrow will bring up the window shown in Figure 34 B DDR3HS MN XXX 99 Doc Rev 1 40 Nexus Technology Company Confidential APPENDIX B Setting Sample Capture Points in TLA V5 6 xxx cont d 1 off line Setup B_DDR3D 201 File Edit View System Tools window Ba ARSE A B Explorer jid Trig
87. ger MY waveform fois Listing Status Idle 74 Sample Point Import Tool 8 Protocol Designer 9 S H Analysis MBP NEX DDR PROTOCOL iverify 171 Define Compare nad D Sy Ls Bg iCapture Filters 48 Suppress Analysis B_DDR3D_2D Asynchronous Synchronous Storage Samples per Signal Options 1285 64 5 Clock Rate 149 Samples Samples 63 Sample Blocks SDRAM DDR CLK0 Clocking S0 Every Rising Edge x Refresh Cycles Acquire Search Range Accuracy 7 Custom 7 Manual Group lt Activity amp Signal Participation In Other Threshold Clock Probe 7 s s 4 2 1 pm Clock Qual E3 7 E3 6 EX E3 3 E3 2 E3 1 E3 0 930 930 E3 7 E3 6 E3 5 E3 4 E3 3 E3 2 1 E3 0 9310 910 1 2 7 2 6 2 5 m N I E2 4 E2 3 E2 2 E2 1 E2 0 8 E2 7 E2 6 1 1 E1 7 E1 6 PES E1 4 E1 3 E1 2 E1 1 E1 0 am 920 1 E2 s 4 E21 4 E21 3 E21 2 E21 1 E21 0 7 Er 6 E11 5 4 E1 3 E11 2 E11 1 0 9210 970 E0 7 E0 6 P 0 5 0 4 i E0 3 0 2 0 1 0 0 I E01 7 01 6 Eo s Eo 4 l Eo 3 E01 2 E01 1 E01 0 TEST RESET 5 d AX 4 4 AX AX2 m fas 6 A3 7 A3 6 A3
88. gger on a Read command to SO or S1 the trigger program would be as shown in Figure 25 E TLA off line Trigger B_DDR3D_4A DEAR JE File Edit view System Tools Window Help 54 sample Point Import Tool Protocol Designer S H Analysis MP NEX DDR PROTOCOL iverify 2 Define Explorer setup If trigger Dy Ly Sy Se then Storage All x Force Main Prefil Trigger MagniVu 20ps EV MagniVu Trigger Pos 2 44 EasyTrigger PowerTrigger State 1 Trigger on any Read Command If Group Control 0 SD READ Or Group Control_0 RDA 508 READ WITH AUTO PRECHARGE Group Control_1 RD 50 Then Trigger All Modules Else If Group Control 0 RD 1 READ Or Group Control 0 ADA 518 READ WITH AUTO PRECHARGE Group Control 1 RD 1 Then Trigger All Modules Figure 25 B DDR3D 4A R DDR3D 2A Read Command Trigger Clause Definition B_DDR3D_4A State 1 1 Cono 0 RD SOR READ v Conto 0 v S0 READ v Conto 1 v RD SO READ SD READ Group Radix Trigger All Modules Symbolic Symbol File Symbol File c pr b_ddr3d_4a_ctrl tsf_v Event Name optional Figure 26 B DDR3D 4A DDR3D 2 Read Command Trigger Detail To trigger on a Read command to a given address followed by sp
89. his information is programmed into the DDR memory upon system boot by use of the MRS Mode Register Set commands and is required when using the DDR3D 4 or DDR3D 2 supports for the post processing software to properly decode the acquisitions The TLA trigger shown in Figure 29 can be used to acquire the MRS cycles when using this support Note that because there is no Trigger event defined in this example that it will be necessary to Stop the TLA acquisition manually to display the MRS data A trigger could certainly be added in either or both of the Trigger events but the method shown ensures that the last valid MRS cycles will be acquired regardless of the memory depth setting of the acquisition card EB off line Trigger 2SBidfx File Edit View System Tools Window Help gal e BRS Explorer fli setup trigger 1 waveform Listing Idle 00 Le S4 E Ali X Hume Noe Bn E fl Tigger Pos 2 EasyTrigger PowerTrigaer State 1 Cycle Store If Group Control_0 MRS 508 MODE REGISTER SET Or Group Control 0 MRS 518 MODE REGISTER SET Or Group Cont Then Store Sample Else If Group Control 1 MRS 508 MODE REGISTER SET Or Group Control_1 MRS 518 MODE REGISTER SET Or Group Cont Then Store Sample For Help press F1 Figure 29 B_DDR3D_4A R_DDR3D_2A MRS Trigger B_DDR3HS MN XXX 93 Doc Rev 1 40 Nexus Technology Compan
90. ify Dy Ly 1 EL X Ha Storage None v EI Trigger Pos 3 2 MagniVu 20ps Magnu Trigger Pos J E State 1 Store MRS cycles to 508 and S1 If Group Control MRS 508 MODE REGISTER SET Or Group Control MRS 518 MODE REGISTER SET Then Store Sample For Help press F1 Figure 23 B_DDR3D_2D MRS Trigger In the trigger example a Storage condition has been created so that only MRS cycles will be stored In testing multiple MRS cycles were seen during the boot process and the example triggers shown will ensure that all of the MRS cycles will be acquired an example of which is shown in Figure 24 The last acquired MRS cycle will reflect the settings used in the DDR target in this case a CAS latency of 2 cycles with a Burst length of 8 B_DDR3HS MN XXX 87 Doc Rev 1 40 7 al 7 A INEXUS y Company Conj idential EE DDR2M 3A MRS D x c2 po E Delta Time 1 29743 a Lock Delta Time DDR2M 34 297 414 375 us 357 826 750 us E Figure 24 MRS Cycle Acquisition Disassembly 7 3 B DDR3D 4A R DDR3D 2A Power Triggers Because of the way data is captured and stored when using the B DDR3D 4 and R DDR3D 2A supports see Appendix A triggering on a Command or other DDR3 event has become more complicated Since two clock cycles of data are stored in the 7BB4 card t
91. ile the Tektronix active P69xx and P68xx series of probe being general purpose probes divide the input voltage swing by 20 the passive probes from Nexus divide the signals by approximately 7 5 Since the divide value is different than the standard Tektronix probe the voltage swing and offset will be higher than expected and the thresholds will be different Instead of the expected 0 75 threshold of approximately 1 9V threshold will be required This was designed specifically for DDR3 signals to allow the best possible capture of the digital representation of these signals Viewing the output of the Logic Analyzer analog mux should be used as a tool to provide fine adjustment of the logic analyzer signal Vref The threshold value determined in this manner should be used as the threshold setting for the Nexus DDR3 product Please note Only the vertical resolution is affected by the Nexus passive probes APPENDIX DDR Data is Clocked A 1 Background Demultiplexing means that the TLA s Logic Analyzer card can have one data probe connected to the target yet store incoming data in two or four separate data sections of the card For instance the A3 data section 8 bits can be connected to the target and data can be stored in the A3 section and the D3 section Using the equivalent of 4X demux by utilizing both the cross point switch and prime memory capabilities of the acquisition card connections made to the channels permit data to b
92. ing Individual 8 bit Read Data Groups off line Setup B_DDR3D_4A lig Fie Edit View System Tools Window Help DoR B_DDR3D_4A Asynchronous Synchronous 54 Sample Point Import Tool 4 Protocol Designer 2 S H Analysis Will NEX DDR PROTOCOL iVerify 121 Define Dy La Sy ts iCapture Filters Suppress Analysis Storage Wi Explorer il Setup SDRAM DDR CLKO Clocking Max Clock Rate 50 Every Rising Edge Samples per Signal 1285 64 5 E Samples Options 8 Norm Search Range custom Manual Group Participation lt lt In Other Activity amp Threshold at Signal Type Clock Qual Probe E3 E EX I6 s5 E3 6 5 4 1 5 4 3 2 1 Ex3 3 0 Clock Qual 930 Groups undo gt Redo Be 930 RdADatB7 Fa DQ63 lt DQ62 cRDa DQ51 cRD 6 c E1 5 E1 4 A3 71 E1 7 l Et ed 5 4 A3 61 A3 51 2 1 A3 31 A3 21 A3 11 A3 01 Ck0 DQ47 cRDa DQ46 cRDa DQ45 c Figure 18 TLA V5 6 or later Setting
93. is higher VCC voltage level 2 0 SOFTWARE INSTALLATION 2 1 General Support Software Information One CD containing all of the relevant support software and documentation has been included with the NEX DDR3INTR HS product The particular support needed depends on the speed of the DDR3 bus being probed and the TLA configuration Please note that hardware requirements differ depending on the speed of the DDR3 bus For more information on the hardware requirements and setup please see Section 3 0 Support 1400 or slower Read AND Wirite Data 1400 5 or slower Read AND Write Data 1866MT s or slower Read AND Wirite Data 1866MT s or slower Read AND Wirite Data S W Support B DDR3D 2D DDR3D 1A Reduced Module Count Support See Section 1 3 B DDR3D 4A DDR3D 2A Reduced Module Count Support See Section 1 3 of acq cards 2 TLA7BB4 750 1 4GHz state speed 1 TLA7BB4 750MHz 1 4GHz state speed 4 TLA7BB4 1 4GHz state speed 2 TLA7BBA 1 4GHz state speed of probes 1 PRBIXL and 3 PRB2XL 4 PRBIXL 1 P6960HCD and 3 P6962HCD 4 P6960HCD Table 1 NEX DDR3INTR HS Support Software Requirements 2 2 Loading the Support into the TLA The NEX DDR3INTR HS software is installed using the same method as other Windows programs Place the NEX DDR3INTR HS Install CD in the CD drive of the TLA Using Windows Explorer select the CD move to the support_software folder select th
94. le dual or quad rank DDR3 DIMM running 1866MT s or slower This support requires 4ea Tektronix P6960HCD probes and two merged Tektronix TLA7BB4 acquisition cards each with the 1 4GHz state speed option The limitations and cautions when using this support are Selective clocking is not available When using a QR DIMM if one or more Ranks are powered down data may be acquired erratically Note that this manual uses some terms generically For instance references to the TLA700 7000 apply to all suitable TLA7XXX Logic Analyzers or PCs being used to control the TLA NEX DDR3INTR HS and X DDR3D XX refers to any of the B DDR3D 2D 4A or DDR3D 1A 2 software support packages This manual assumes that the user is familiar with the DDR3 SDRAM Specification and the Tektronix TLA Logic Analyzers It is also expected that the user is familiar with the Windows environment used with the TLA 1 4 Eye size required The Eye size stable data required at the input resistor to the Nexus passive probes NEX PRBIXL and NEX PRB2XL is 330ps and 0 2V The eye size for the Tektronix probes is 240ps and 0 2V Capture accuracy may be affected if a stable eye cannot meet this requirement The eye is a perfectly shaped diamond with each side equal distant from the center 1 5 1866MT s VCC required 1866MT s capture by the logic analyzer requires VCC voltage of 1 65V The user needs to ensure that their system under test can provide and withstand th
95. ls on which 8 bit groups make up a 32 bit group When setting the individual Setup amp Hold values it is suggested that the settings for the associated 32 bit group be reset to Support Package Default This will prevent the TLA from displaying warnings that conflicting values have been set for the data bits The Support Package Default Setup amp Hold values are the same as the TLA default values 117ps 117ps It will also be necessary to program the Setup amp Hold values for all of the 8 bit groups in the affected 32 bit group If conflicting Setup amp Hold points are programmed then the values will have exclamation marks beside them to denote the conflict B_DDR3HS MN XXX 78 Doc Rev 1 40 Nexus Technology Company Confidential TLA off line WR MVu Edit Data System Tools Window SE Autodeskew setup trigger waveform ED Tek sta Sample Point Import Tool rotocol Designer 8 Ga activty OF value Q Time Div 500ps At v Cursor 2 80025 v D Seach 2 case pivu Strobes 13 1601 14 160ns 15 1605 16 160 17 160 20 1605 21 180ns 00000 For Help press F1 Figure 17 View
96. lso provide optimal probe points extremely small added trace lengths and extremely small interposer effects 1 3 Software Package description The NEX DDR3INTR HS support includes the following software packages which require TLA Application software V5 6 703 or later B_DDR3D_2D allows the user to acquire Read AND Write data from a single dual or quad rank DDR3 DIMM running 1333MT s or slower This support requires lea NEX PRBIXL 3ea NEX PRB2XL Low Profile Distributed probes and two merged Tektronix TLA7BB4 750MHz or 1 4GHz acquisition cards This support can use Selective Clocking to reduce the number of Idle states acquired by the logic analyzer B DDR3D 4A allows the user to acquire Read AND Write data from a single dual or quad rank DDR3 DIMM running 1866MT s or slower This support requires lea Tektronix P6960HCD and 3ea Tektronix P6962HCD probes and four merged Tektronix TLA7BB4 acquisition cards each with the 1 4GHz state speed option DDR3D 1 Reduced Module Count Support allows the user to acquire Read AND Write data from a single dual or quad rank DDR3 DIMM running 1333MT s or slower This support requires 4ea NEX PRBIXL Low Profile Distributed probes and one Tektronix TLA7BB4 750MHz or 1 4GHz acquisition card There are a few limitations or cautions when using this support Selective clocking is not available R DDR3D 2A Reduced Module Count Support allows the user to acquire Read AND Write data from a sing
97. mand activate a row in a bank for subsequent access Chip Select 0 3 Bank x DESL IGNORE COMMAND Deselect function no new command E MRS EXTENDED MODE Mode Register Set command registers 0 3 REGISTER SET x Sx Chip Select 0 3 NOP NO OPERATION Sx No Operation command Chip Select 0 3 PRE SINGLE BANK PRECHARGE Sx Precharge command Chip Select 0 3 Bank x Bank PREA PRECHARGE ALL BANK Sx Precharge All command Chip Select 0 3 RDA READ W AUTO PRECHARGE Read command with auto precharge Chip Select 0 3 Bank x Sx Bank RD READ Sx Bank Read command initiates a burst read access to active row Chip Select 0 3 Bank x READ DATA Valid Read data on the bus REF REFRESH Sx Self Refresh command Chip Select 0 3 WRA WRITE W AUTO PRECHARGE Write command with auto precharge Chip Select 0 3 Bank x Sx Bank WR WRITE Sx Bank Write command initiates a burst write access to active row Chip Select 0 3 Bank x WRITE DATA Valid Write data on the bus ZQCL ZQ CALIBRATION LONG Sx ZQ Calibration Long Chip Select 0 3 ZQCS ZQ CALIBRATION SHORT Sx 70 Calibration Short Chip Select 0 3 Table 10 NEX DDR3INTR HS Mnemonics Definition 6 4 Viewing Timing Data on the TLA By default the TLA will display an acquisition in the Listing State mode However the same data can be displayed in Timing form by adding a Waveform Display window This is done by clicking o
98. n either clock cycle Counter 1 lt 1 Inc Counter 1 Group Rd_ADataHi 33332222 And Group Rd_ADataLo 11110000 Trigger All Modules Group Rd BDataHi 33332222 And Group Rd_BDataLo 11110000 Trigger All Modules Group Rd CDataHi 33332222 And Group Rd CDataLo 11110000 Trigger All Modules Group Rd DDataHi 33332222 And Group DDataLo 11110000 Trigger All Modules Anything Reset Counter 1 And Go To 2 when Read Command was in second clock cycle Count Latency 1 2 Look for Read Data in second clock cycle only transactions 1 amp 2 Counter 1 lt 1 Inc Counter 1 Group Rd CDataHi 33332222 And Group Rd CDataLo 11110000 Trigger All Modules Group Rd DDataHi 33332222 And Group Rd DDataLo 11110000 Trigger All Modules Anything BoTo5 State 5 Look for Read Data t clock cycle only transactions 3 amp 4 Group Rd ADataHi 33332222 And Group Rd ADataLo 11110000 Trigger All Modules Group Rd BDataHi 33332222 And Group Rd BDataLo 11110000 Trigger All Modules Anything Reset Counter 1 And Go To 2 Figure 27 B_LDDR3D_4A R_DDR3D_2A Read Address and Data Trigger BL 4 Odd Latencies B_DDR3HS MN XXX 91 Doc Rev 1 40 Nexus Technology Company Confidential To trigger on Read Address followed by Read Data the trigger in Figure 28 would be used for even latency values off line Trigger B
99. n the Window pull down selecting New Data Window clicking on Waveform Window Type then choosing the Data Source Two valid choices are presented X DDR3D XX and X DDR3D XX MagniVu The first will show the exact same data same acquisition mode as that shown in the Listing window except in Waveform format The second selection will show all of the channels in 20GHz MagniVu mode so that edge relationships can be examined around the MagniVu trigger point MagniVu is very useful and in some cases necessary to see resolve DDR3 data With either selection all channels can be viewed by scrolling down the window Refer to the TLA System User s Manual for additional information on formatting the Waveform display E off line WR MVu Edit view Data System Tools Window Help 7 4 Sample Point Import Tool Protocol Designer E iverify 23 autoDeskew A Jl setup IP trigger 1 waveform We Listing Run 1 1 x 9 x amp Magnvu Activity OF value Q Time Div je By Search ns 10 500 5 12ns 13 500ns 15ns 16 500 18ns 19 500ns 21ns 21 054 ns Soo te Kas qun kes r l L For press F1 Figure 22 NEX DDR3INTR HS MagniVu Display TLA B_DDR3HS MN XXX 85 Doc Rev 1 40 Nexus Technology Company Confidential 7 0 HINTS amp TIPS 7 1 Symbolic Triggering
100. nology com We will try to respond within one business day If Problems Are Found Document the problem and e mail the information to us If at all possible please forward a Saved System Setup with acquired data that shows the problem Please do not send a text listing alone as that does not contain enough data for analysis To prevent corruption during the mailing process it is strongly suggested that the Setup be zipped before transmission B_DDR3HS MN XXX 119 Doc Rev 1 40 Nexus Technology Company Confidential
101. nput A connector into AD32 input A2 connector into the AD10 input B1 connector into the C3210 input TLA Slave 3 Connect the P6962HCD probe head to DDR3 Interposer s LEASH soldered on coax cable that is attached to P151 161 position on the Interposer Plug the probe s TLA connectors into the Slave 3 acquisition module as follows B2 connector into the E3210 input A connector into AD32 input A2 connector into the AD10 input connector into the C3210 input See Figure 2 for connection information Table 3 shows the Channel Grouping Wiring for use with the B_DDR3D_4A support 3 4 R_DDR3D_1A Support Reduced Module Count support To acquire DDR3 Read and Write data at speeds up to 1333MT s requires one TLA7BB4 136 channel 750 2 or 1 4GHz acquisition card and the DDR3D support software logic analyzer modules should be connected to the DDR3 DIMM Interposer as follows using 4 NEX PRB1XL probes TLA Module Connect the NEX PRBIXL probe head to the DDR3 Interposer s LEASH soldered on coax cable that is attached to the 153 163 Coax cable on the Interposer Connect the NEX PRBIXL AD3 2 probe head to the DDR3 Interposer s LEASH that is attached to the P152 162 Coax cable on the Interposer Connect the NEX PRBIXL 1 0 probe head to the DDR3 Interposer s LEASH soldered on coax cable that is attached to the 154 164 Coax cable on the Interposer
102. off line WR MVu File Edit view Data System Tools Window Help Sample Point Import Tool Protocol Designer iverify Z AutoDeskew Setup Trigger MY Waveform fw Listing MIL c Tek k Idle gt 0 A X Be view Magnivu activity OF value Q Q Time Div 1 5ns v pn Search 1 2 Waveform 5600 5 3ns 1 500ns Ops 1 500ns 4 500ns 7 50015 10 500ns 1215 13 500ns 15ns 16 500ns 1815 19 500ns 21ns 22 500ns 24 668 H 23 633 ns B miu Address 00000 40098 00000 4 gniVu CXED Latency expires LI LI L ELI L1 Write Command Wie baa Data 55555555 QU en cc 2COCOOC Measurements Trigger For press F1 11 Figure 13 Locating Minimum Valid NEX DDR3INTR HS Write Data Window Zoom in further to determine the Setup and Hold sample point necessary to acquire valid data at that point Figure 14 and use the cursors to measure the time from the clock edge to the start of valid Write data In this example the data leads the clock edge by approximately 740ps meaning that a suitable Setup amp Hold value for the A Data Hi capture group would be 742ps 508ps Note that the A Data Lo group is valid somewhat later
103. ont of a TLA channel denotes Slave card 2 of the merged set The S3 in front of a TLA channel denotes Slave card 3 of the merged set All signals on this page are stored in the 7Bx4 s Prime memory and will not have a MagniVu display value Signal DDR3 TLA Signal DDR3 TLA Name Pin Input Name Pin Input RdDDatHi _D_ 52 0 071 RdDDatLo RD_D_DQ31 156 S_D2 6 1 Hex _D_ 2_00 1 1 Hex RD_D_DQ30 155 S_D2 3A1 2_D0 541 RD_D_DQ29 150 53 0 071 52 0071 RD_D_DQ28 149 3_00 1 1 S2 D0 2 1 RD D DQ27 37 S D2 4 1 S2 D0 3 1 RD D DQ26 36 S D2 1 1 2_00 7 1 RD_D_DQ25 31 S3_D0 2A1 2_01 0 1 RD_D_DQ24 30 3_00 3 1 2_01 2 1 RD_D_DQ23 147 3_00 4 1 2_01 3 1 RD_D_DQ22 146 3_00 5 1 2_D1 741 RD D DQ21 141 3_01 2 1 2_D3 541 RD_D_DQ20 140 3_01 3 1 2_D1 141 RD D DQI9 28 S3 D0 6 1l 2_D1 441 RD_D_DQ18 27 3_00 7 1 2_D3 741 RD_D_DQ17 22 3_D1 141 S2 D3 6 1 RD D 16 21 53 DL 4 1 S2 D3 4 1 RD D DQI5 S3 DI 6 1 S2 D3 1 l RD D DQI4 3_01 7 1 2_D2 741 RD_D_DQ13 S3 D3 4 1 S2 D2 6 1 RD D DQI2 53 D3 1 l S2 D3 3 1 RD D 53 DL 5 1 52 D3 2 1 RD D DQIO 53 D3 7 1 2_D2 541 RD_D_DQ9 S3 D3 3 1 S2 2 471 RD D 3_03 2 1 2_D2 341 RD D DQ7 S3 D3 0 1 52 D2 2 1 RD D DQ6 S3 2 771 0 171 RD_D_DQ5 3_02 3 1 _ 0 4 1 RD_D_DQ4 S3_D2 2A1 2_D2 141 RD_D_DQ3 3_01 1 2_02 0 1 RD_D_DQ2 3_02 5 1 M C0 6 1 RD D DQI 53 D2 1 l M 0 771 RD D DQO 53 2 081 g g Q Nn RD_D_ RDD RDD RDD RDD RDD RDD RDD RDD RDD RDD
104. poser is subject to reflected noise and the quality of the acquisitions should improve if the Interposer is in the furthest slot away from the memory controller If the memory channel contains two DIMM slots and only one will be used the slot used must be the furthest away from the memory controller APPENDIX D 240 pin DDR3 DIMM Pinout Front Side left 1 60 Front Side left 61 120 Back Side right 181 240 Back Side right 121 180 X64 Non Parity VREF Pin X72 ECC VREF X64 Non Parity VSS X72 ECC VSS X64 Pin Non Parity A2 X72 ECC A2 Pin X64 Non Parity Al X72 ECC Al VSS VSS DQ4 DQ4 VDD VDD VDD VDD DQO DQO DQS DQS 1 VDD VDD DQI DQ1 VSS VSS 1 CKO CKO VSS VSS DMO DQS9 DMO DQS9 VDD VDD CKO CKO DQSO DQSO NC DQS9 NC DQS9 VDD VDD VDD VDD DQS0 DQS0 VSS VSS VREF VREF EVENT NC EVENT NC VSS VSS DQ6 DQ6 NC Par_In NC Par_In A0 A0 DQ2 DQ2 DQ7 DQ7 VDD VDD VDD VDD DQ3 DQ3 VSS VSS A10 AP BAI BAI VSS VSS 0012 0012 BAO BAO VDD VDD DQ8 DQ8 DQ13 DQ13 VDD VDD RAS RAS DQ9 DQ9 VSS VSS WE WE SO 50 VSS VSS DMI DQS10 DMI 005810 CAS
105. r 5 waveform Listing gt Tek Idle D BS 23 view Magnivu activity OF Value Q Time Div 1 5 Search Qt 2 v 14369 Waveform 6ns 4 500ns 3ns 1 50015 0 1 500ns 3ns 4 500ns 6ns 7 500ns Ons 10 500ns 12ns 13 500ns 1515 16 500ns 18ns 19 500ns 21ns 2 J 76 328 ns H 21 446 ns 5 x B 2242 Aggress 00000 40006 00000 CKED Vu SOF DDRCLKC RASH 1 Sample Pt 2 2278 Sample Pt 1 B zniVu Strobes 000 B yVu Data 00000000 Bp 2270 Data 10 00000000 B iu DatsByte7 o0 lt For Help press F1 Figure 5 Read Data Latency CAS Latency CAS Additive Latency RDIMM 5 0 1 6 cycles B_DDR3HS MN XXX 69 Doc Rev 1 40 Nexus Technology Company Confidential 5 6 Selecting NEX DDR3INTR HS Write Data Sample Points Unlike valid DDR Read data valid Write data is bisected by the Strobes Since valid DDR3 Write data is bisected by the Strobes see Figure 5 the Setup amp Hold sample point must set for the valid data that occurs closest to the clock edge The appropriate clock edge for Writes is determined by counting the number of clock cycles specified by the Write Latency MRS value from the Write Command to the first valid Write Data If these values are not known the technique described in Section 7 3 can be used to determine them In Figure 6 the total Write latency is 6 cycles
106. r that the user would not expect The threshold setting when using these probes with this product is defaulted to 3 7V This can be verified by viewing the signals via the Mux signal output in the front of the logic analyzer module Note that the Nexus SPA tool will fine adjust this threshold setting 54 DDR3 and DDR3SPA It is strongly recommended that Nexus DDR3SPA DDR3 Sample Point Analyzer be used to determine the proper sample point setting necessary for accurate Read and Write data acquisition Given the correct DDR bus parameters Latency Burst Length etc SPA will analyze any Read and or Write bus transactions in MagniVu memory and return suggested sample points Refer to the DDR SPA documentation for more specific information on using this software If for whatever reason DDR3SPA doesn t appear to provide good sample point setting information the following sections describe how to evaluate acquired DDR3 data to determine the proper sample points manually 5 5 Selecting NEX DDR3INTR HS Read Data Sample Points For the DDR3 Read data to be properly acquired it is necessary to choose the proper sample points to ensure that data is acquired at the proper point in the transaction Since valid DDR3 Read data is straddled by the Strobes see Figure 5 the Setup amp Hold sample point must be set for the valid data that occurs closest to the clock edge The appropriate clock edge for Reads is determined by adding the Additive Latency v
107. rst Length Permits setting the length of data Bursts The field choices are BL8 default Assumes a Burst Length of 8 data transactions BLA Assumes a Burst Length of 4 5 0 CONFIGURING FOR READ WRITE DATA ACQUISITION Prior to configuring your NEX DDR3INTR HS support package it 1 strongly recommended that Appendix A How DDR Data is Clocked section 5 4 Selecting DDR Read Sample Points and section 5 5 Selecting DDR Write Sample Points be read This background information is very helpful and facilitates proper support configuration 5 1 Note About the Different Data Groups The NEX DDR3INTR HS support software have three different areas where signal groups are defined to provide specific functionality There are the MagniVu data groups see Tables 6 7 8 and 9 are the groups that contain raw MagniVu data Storage data groups see Tables 2 3 4 and 5 can be seen in the acquisition card Setup window and contain the data stored in Main Memory which is used for the Listing display Capture data groups not defined in this manual are the groups seen in the TLA s Setup amp Hold dialog box and are the groups used to capture data during each DDR clock cycle The MagniVu and Capture data groups will be referred to in the following explanation on determining and setting the correct sample points to acquire Read and Write data Please contact your local Tektronix representative for a detailed explanation of the
108. than the Data Hi group with its valid time starting at approximately 430ps prior to the clock edge so the Setup amp Hold sample point for the A Data Lo capture group would be set to 430ps 195ps R im File Edit view Data System Tools Window Help 54 sample Point Import Tool Protocol Designer iverify Bautodeskew 5 GR trigger waveform 3 Listing GE gt Tek Idle S EST X Ba d Magnivu activity OF value Q d Time Div 500ps ven Search ay Cursor 1 v tog Cursor 2 740ps 2 J Waveform Ons 13 260ns 14260ns 15 260ns 16260ns 17 260 18 260ns 19 260ns 20 260ns 21 260 2 265 ns 21 699 ns 5 URNA ALLANT Eb Vu Address 00000 CKED M lt CASH i i A B B piu Strobes 1FF 000 1FF 1FF 000 OFF 000 B Data Hi 55555555 00000000 55555555 00000000 B miu Data o 55555515 AAAAAAAA 55555555 00000000 55555555 00000000 FFFFFFFF i B Vu Databyte7 14 00 55 oo 55 oo FF 3 gt EN For Help press F1 Tektronix Figure 14 Measuring NEX DDR3INTR HS Data Hi Lo Write Data Setup amp Hold B_D
109. the post processing software to work properly These fields and their selections are Burst Length permits setting the burst length for Read and Write data Valid choices are 4 the default 8 and 4 8 On the Fly This value must be set properly for all valid Read and Write data to be displayed CAS Latency CL sets the delay in clock cycles from the Read command until the first piece of valid Read data is available This value must be set properly for all valid Read Data to be displayed Valid choices are 5 default 6 7 8 9 or 10 cycles CAS Additive Latency additional latency for data cycles This value must also be set properly for valid Read Data to be displayed Valid choices are 0 default CL 1 or CL 2 cycles CAS Write Latency number of clock cycles from Write command to the first Write Data This value must be set properly for all valid Write Data to be displayed Valid choices are 5 default 6 7 or 8 cycles Registered must be set to reflect whether or not Registered DDR memory is used Default is No When set to Yes an additional clock cycle delay is added to CAS Latency and to valid Read and Write Data tagging B_DDR3HS MN XXX 81 Doc Rev 1 40 Nexus Technology Company Confidential DM Signal Use permits setting Data Mask functionality to Write Masks default Strobes When set to Write Mask the DM signals will be used to mask Write Data to show which data bytes were valid in the cycle In
110. tor from the probe into the AD32 input of the Master Logic Analyzer module and then plug the TLA connector from the probe into the AD32 input of the Slave module Connect the P6960HCD probe head to the DDR3 Interposer s LEASH soldered on coax cable that is attached to the P153 163 Coax cables on the Interposer Plug the A TLA connector from the probe into the C3210 input of the Master Logic Analyzer module and then plug the TLA connector from the probe into the C3210 input of the Slave module Connect the P6960HCD probe head to the DDR3 Interposer s LEASH soldered on coax cable that is attached to the P154 164 Coax cables on the Interposer Plug the A TLA connector from the probe into the AD10 input of the Master Logic Analyzer module and then plug the TLA connector from the probe into the AD10 input of the Slave module See Figure 2 for connections Table 5 shows the Channel Grouping Wiring for use with the R_DDR3D_2A support 3 6 Short LEASH probes The standard product includes 4 LEASH probes connected to this Interposer product These short probes are soldered directly onto the interposer and interface the Interposer to the Passive probes that connect to the logic analyzer These LEASH probes are to allow the user to easily install and remove the Interposer product in their system with out the added weight of the passive probe attached There may be other probing options in the future Conta
111. ts to the various probes using four screws two plates and a HCD connector These parts are supplied 3 6 2 LEASH probe to the various logic analyzer probes To connect the leash to the various probes that connect to the logic analyzer follow the below diagram Care must be taken to not brush the HCD pins sideways gray part in drawing below The Top plate will have recessed screw holes for the screw heads and the bottom plate will have threaded screw holes Align screw holes and guide pin holes Tighten each screw a small amount while going to each screw in turn to maintain even force with each screw Take care not to damage the screw heads There is no force or torque specification for the HCDs Reasonably tighten the screws down tip the various probes Top iw Four each Screws Hold each a LEASH robe HCD Interposer here _ connector top plate and back Transition board or the LEASH plate Cable end Figure 4 LEASH probe to HCD Probe connection 3 7 Interposer location in the Target The Interposer must be installed in the furthest slot from the memory controller Notes 1 RdA_DatHi Hex Signal Name RD_A_DQ63 RD_A_DQ62 RD DQ61 RD DQ60 RD DQ59 RD DQ58 RD DQ57 RD DQ56 RD DQ55 RD DQ54 RD DQ53 RD DQ52 RD DQ51 RD DQ50 RD DQ49 RD DQ48 RD DQ47 RD DQ46 RD DQ45 RD A DQ44 RD DQ43 RD A DQ42 RD_A_D
112. urst Length of 4 Monitors the state of the A12 BC at the time of the Command cycle to determine whether the burst length will be 4 or 8 transactions 4 4 R DDR3D 2A Clocking Selections There are two clocking option fields available when using the DDR3D 24A support package These select fields permit the user to setup the TLA acquisition as follows Active Chip Selects Write Latencies Allows the user to set the number of active ranks Chip Selects that the target DIMM will be using and the Write Latency for the data bus The field choices are 0 1r WLS default Single Rank DIMM S0 only active with a Write Latency of 5 cycles 10 2r WLS Dual Rank DIMM 50 and S1 active with a Write Latency of 5 cycles 3210 WLS5 Quad Rank DIMM 50 34 active with a Write Latency of 5 cycles 0 WL6 Single Rank DIMM 0 only active with a Write Latency of 6 cycles 3210 WL12 Quad Rank DIMM 50 3 active with a Write Latency of 12 cycles Clocking Mode Permits choosing whether to acquire data based on the state of the two CKE signals The field choices are CKE Enabled Clocking 1r only default Minimizes acquired data when both CKE signals are low inactive and a Single Rank clocking choice see Active Chip Selects Write Latencies description above is selected Every rising clock edge Acquires data on every DDRCLKO rising edge regardless of the state of the CKE signals Bu
113. within the support package tab see Figure 32 using the Nexus B DDR3D 2D DDR3 DIMM Interposer support as an example E off line Setup DDR3D 2D DER File Edit View System Tools window Help a explorer isetup trigger M waveform 25 Listing Status Idle 74 Sample Point Import Tool Protocol Designer S S H Analysis MMP NEX DDR PROTOCOL 19 De Ly Spy ts E iCapture Filters 121 Suppress Analysis synchronous Synchronous Storage Samples per Signal Options 1285 64 5 Max Clock Rate 1 4 GHz v 2 g 128 Samples Samples 63 Sample Samples v Blocks SDRAM DDR CLKO Clocking 50 Every Rising Edge x Refresh Cycles Acquire Search Range Accuracy Custom eskew Participation In Other Threshold Type Clock Qual Probe 7 6 5 4 3 1 0 Clock Qual Groups Q3 1 BA0 415 414 413 412 BC A1LA10 AP AIAS A D Group lt lt Activity amp 4 Signal E3 7 Ex amp 5 4 3 Ex 2 Ex 1 0 930 MSB 31 3 9310 90 BAL BAO A15 14 A13 Al E3 7 48 6 je 5 4 3 2 E3 1 E3 0 E2 2 E2 1 q AS AF AG 5 4 A2 Al 80 LSB Control E11 7 11 6 5 11 4 Hen
114. wo tests must be made to determine whether or not an event occurred The storage trigger groups that have an 0 suffix to their names are groups whose data is associated with the first clock cycle that is acquired groups with an _1 suffix are associated with the second clock cycle that is acquired IMPORTANT NOTE The Power Triggers should be loaded into the TLA ONLY through the Load Trigger function in the Trigger window If they are loaded as Module Setups any user entered settings such as sample points and threshold values will be lost Several Power Triggers have been created and included with the DDR3D 44A and DDR3D 2A supports They be found in the C My Document B_DDR3D_4A_ Triggers Document R DDR3D 24A Triggers folder and can be loaded into the module using the Load Trigger icon or menu pull down The Triggers have names that try to indicate what they were designed to do and there are also short descriptions shown for each trigger when it is clicked on from within the Load Trigger menu The triggers and brief descriptions of each follows B DDR3D 4A R DDR3D 2A Even Read Addr Data BLA Trigger Designed to trigger on specific Read data from a specific SO Read address for even latencies with a Burst Length of 4 B DDR3D 4A R DDR3D 2A Even Read Addr Data Trigger Designed to trigger on specific Read data from a specific SO Read address for even latencies with a Burst Length of 8 B DDR3D 4A R DD
115. y 1 23ns after the clock edge so the Setup amp Hold sample point for the Data Lo capture group would be set to 1 23ns 1 465ns Now the sample point for the B Data Hi and Lo groups must be determined see Figure 9 The next valid Read data after the cycle measured above occurs approximately 2 37ns after the rising edge of DDRCKO so a suitable Setup amp Hold value for the B Data Hi capture group would be 2 383ns 2 617ns As with the A data the B Data Lo group is somewhat later than the Data Hi group The Data Lo valid time starts at approximately 2 52ns so a suitable Setup amp Hold value for the B Data Lo capture group would be 2 52ns 2 754ns B DDR3HS MN XXX 72 Doc Rev 1 40 Nexus Technology Company Confidential RD File Edit view Data System Tools Window Help 4 Sample Point Import Tool wm Protocol Designer iverify AutoDeskew il setup IA trigger 1 Waveform Tek Status 0 amp view a9 Magnivu activity OF value Q Q Time Div 500ps v D Search amp og Cursor 2 2 37ns Waveform 10ns 14 410ns 15 410ns iyu Sa B miu Actress Vu CKED Vu RASH CASH Eb yVu Strobes 000 1FF B yVu Data Hi AAAABAAA 00000000 00000000 i 00000000 B miu Data ip EFAFBAFF EFABBAFF 00000000 FFFFFFFF 00000000 00000000 B Vu DataByte7 00 00 d 00 lt For press F1
116. y Confidential Clause Definition B_DDR3E_2SBidfx State 1 1 Group Control_0 MRS SOHMOD v Group 0 Or Group Control_o MRS 528 MOD Or 0 v MRS 538 MOD v Group Radix Store Sample Symbolic Symbol File Symbol File b_ddr3e_2sbidfx_ctrl tsf Event Name optional Figure 30 B DDR3D 4A DDR3D 2A MRS Trigger Detail In the trigger example a Storage condition has been created so that MRS cycles for any Chip Select 0 1 2 or 3 will be stored In testing multiple MRS cycles were seen during the boot process and the example triggers shown will ensure that all of the MRS cycles will be acquired an example of which is shown in Figure 31 The last acquired MRS cycle will reflect the settings used in the DDR3 target in this case a CAS latency of 4 cycles with a Burst length of 4 EE DDR2M 3A MRS joj ma Epp 6184 2 4 084 coc E Delta Time 11 2375 Lock Delta Time DDR2M 3A DDR2M 3A DDR2M 3A DDR2M 3 DDR2M 3A DDR2M 3 Address Mnemonics DataHi DataLo ChekBits DataMasks Timestamp Figure 31 MRS Cycle Acquisition Disassembly Shown for reference only B DDR3HS MN XXX 94 Doc Rev 1 40 Nexus Technology Company Confidential 7 5 Address Errors When Decoding MRS Cycles It may happen when decoding MRS cycles that an error message such as
117. y Rising Edge Clocks data using every rising edge of DDR Clock 0 No Idle Cycle filtering is done 43 DDR3D Clocking Selections There are three clocking option fields available when using the DDR3D support package These select fields permit the user to setup the TLA acquisition as follows Active Chip Selects Write Latencies Allows the user to set the number of active ranks Chip Selects that the target DIMM will be using and the Write Latency for the data bus The field choices are 0 1r WLS default Single Rank DIMM 50 only active with a Write Latency of 5 cycles 10 2r WLS Dual Rank DIMM 50 and S1 active with a Write Latency of 5 cycles 3210 WLS5 Quad Rank DIMM 50 34 active with a Write Latency of 5 cycles 0 WL6 Single Rank DIMM 0 only active with a Write Latency of 6 cycles 3210 WL12 Quad Rank DIMM 50 3 active with a Write Latency of 12 cycles Clocking Mode Permits choosing whether to acquire data based on the state of the two CKE signals The field choices are CKE Enabled Clocking default Minimizes acquired data when both CKE signals are low inactive Every rising clock edge Acquires data on every DDRCLKO rising edge regardless of the state of the CKE signals Burst Length Permits setting the length of data Bursts The field choices are default Assumes a Burst Length of 8 data transactions BLA Assumes a B

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