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1. Channel Mask 0x5 V1VG Fig 3 10 Zero Suppression based on the amplitude NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 31 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 3 4 1 3 Zero Length Encoding ZLE NPO Zero Length Encoding allows to transfer the event in compressed mode discarding either the data under the threshold set by the User positive logic or the data over the threshold set by the User negative logic With Zero length encoding it is also possible to set LOOK BACK the number of data to be stored before the signal crosses the threshold and or Ni wo LOOK FORWARD the number of data to be stored after the signal crosses the threshold see 4 3 In this case the event of each channel has a particular format which allows the construction of the acquired time interval Total size of the event total number of transferred data Control word stored valid data if control word is Control word stored valid data if control word is The total size is the number of 32 bit data that compose the event including the size itself The control word has the following format Bit Function r O 0 skip 30 2 20 0 stored skipped words If the contr
2. 30 3 4 1 2 Full Suppression based on the amplitude of the 30 1 5 Zero Lena th Encodine ZDE uuu Lu uu _ ____ 32 3 4 2 SUP PTOSSION 34 2 TRIGGER MANAGEMENT resperator reene 38 Boo 38 322 38 D 38 Idade Treo oc 39 3 5 4 40 ID ER 41 5 ANALOG MONITOR 42 Jud Trigger Majority Mode Monitor Mode 0 42 3 7 2 Test Mode 43 3 7 3 Analog Monitor Inspection Mode Monitor Mode 2 43 3 7 3 1 Procedure to enable Analog Monitor mode 44 DP 44 3 7 4 Buffer Occupancy Mode Monitor Mode 3 45 5 7 Voltage Level Mode Monitor Mode 4 45 CEBSLPATIBRNOGENERA TOR 46 3 9 RESET CLEAR AND DEFAULT CONFIGURATION L 46 3 9 1 FG CAS 46 3 9 2 us 46 3 9 3 O NNI mm 46 3 10 VNIEDUOUSINITERPE ACE uu a a 46 3 10 1 Addressing capa
3. S Pep 52 3 14 4 0 22 l I _4___6_____ 53 3120 CAENVME Mulli Wrile ____6_6___ __ __ 6_ 6____ 53 3 14 7 53 3 14 8 54 3 14 9 MBLTReadCycle eese eene eene 54 3 14 10 CAENVME FIFOMBLTReadCycle 55 3 14 11 CAENVMB 4 55 3 14 12 CAENVME 0 55 3 14 13 IROD Sable 56 3 14 14 CAENVME THE 56 a lt xu uu x 57 dle REGRLIFRSADDRESS MAP RON 57 4 2 CONFIGURATION OXFOOO OXFO84 nnne nennen 58 43 CHANNELNZS XIN248 RAW u a EX 59 44 CHANNEL 75 5 0 28 2 00 00 00000 000000000006 senes se ene esae sensere 60 4 5 CHANNEL THRESHOLD 1 90 20 0 2 20 0 2 0000000000000000 60 4 6 CHANNEL
4. as ee HR 21 3 2 6 OCS 22 222 Direct Drive pin E S SSS 22 3 2 8 Fe RE CT 22 3 2 9 ER 23 UI RR ERIS 25 Jis PRC QUES TU SOD rcc 25 222 2 Gate and Sample mode uu uu uu ionisering EE E E etd pau dd 25 2221 Pe oT 25 222 WO uu sQ 26 3 3 4 Acquisition Triggering Samples and 26 3541 SIZE CV CIS RRRRRR EE 27 3 30 28 Filename Number of pages Page 2 V1724_REV19 DOC 74 CAEN Q far Discoveri Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 DENEN L xu 28 MEE MCN TS 28 2393 5 28 3 3 6 Memory FULL management 30 IAs ZERO SUPPRESSION 30 3 4 1 LEIO uu u ______ __ 30 3 4 1 1 Full Suppression based on the integral of the 1
5. 20 FIG 3 4 CAENPLLCONFIG MAIN MENU 000000000000000000000000000500 22 nere essen annees 22 FIG 3 3 SAMPLING CLOCK PHASE SHIFT cain SU ocu NUES GU UIS US Urea UC Saa ERU 23 FIG 3 6 DATA STORAGE IN GATE 25 FIG 3 7 DATA STORAGE IN SAMPLE MODE cccccssscccceseccenssecccesccesanecceeesecesaeeecesaeccesusecesaeeecesuaeceesaecessaeeceeaes 26 gre 27 J os 29 FIG 3 10 ZERO SUPPRESSION BASED ON THE 31 FIG 3 11 ZERO LENGTH ENCODING SAMPLES STORAGE 33 FIG 3 12 ZERO SUPPRESSION 34 FIG 3 13 EXAMPLE WITH POSITIVE LOGIC AND NON OVERLAPPING Ni 34 FIG 3 14 EXAMPLE WITH NEGATIVE LOGIC AND NON OVERLAPPING Ni Nppwp eee 35 3 15 EXAMPLE WITH POSITIVE LOGIC AND NON OVERLAPPING NY pk 36 FIG 3 16 EXAMPLE WITH POSITIVE LOGIC AND OVERLAPPING BK 37 FIG 3 17 BLOCK DIAGRAM OF TRIGGER MANAGEMENT ccsssccccessccecsecceessececaeccecuseecesasececsesecesueeceesaeecesaaeceeaes 38 FIG 3 18 LOCAL TRIGGER GENE
6. MAGNIFY 0 x1 OFFSET 0 2048 1 f CHO CHI CH2 CH3 CH4 CH5 CHE CHT MAGNIFY 1 2 OFFSET 0 1792 0875 CHO CHI CH2 CH3 CH4 CH5 CHE CHT MAGNIFY 3 x8 OFFSET 0 880 896 1536 0750 1280 0 525 1024 05 768 0375 digital 912 0 250 displacement dac above ground displacement 437 5 mV 896 steps 256 0125 0 0 Time Fig 3 24 Example of Magnify and Offset parameters use on single channel The assumption is an input signal on CHO using th whole dynamics and all channels participating to Analog Monitor The ADC on the mezzanine produces data in the 0 16383 range 14 bit All channels have 0 offset and therefore the ADC converted value is 8192 The triangular waveform is shown as example The FRGA AMC of channel 0 sends the 8 MSB to FPGA ROC with 25 Mhz rate one sample out of four If no output is added and MAGNIFY factor 1x the DAC produces a copy of the signal on channel 0 with 125 mV dynamics 1 8 of DAC dynamics and 500 mV average value If a larger dynamics is desired it is necessary to modify OFFSET and MAGNIFY factor in order to avoid saturation it is necessary to subtract to the channel sum a value equal to the minimum of the channel sum displacement 3 7 4 Buffer Occupancy Mode Monitor Mode 3 In this mode MON out provides a voltage value proportional to the number of buffers filled with events step 1 bu
7. tv ain Oo uS 51 LIST OF TABLES UE ie MOD S T 1 ISIL 5 9 TABLE 2 1 MODEL V 1724 POWER REQUIREMENTS 11 TABLE 2 2 FRONT PANEL ___________ _ ___ 6 6_______ 15 TABLE 2 3 MOD VI 724 TECHNICAL SPECIFICATIONS 18 TABLE 3 1 BUFFER ORGANIZATION __________________ 26 TABLE 3 2 FRONT PANEL VOS DEFAULT 42 TABLE 4 1 ADDRESS MAP FOR THE MODEL V1724 57 TABLE 4 2 ROM ADDRESS MAP FOR THE MODEL V1724 59 TABLE 4 3 OUTPUT BUFFER MEMORY BLOCK DIVISION eese nnne nennen 62 NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 8 CAEN Q Document Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 1 General description 1 1 Overview The Mod V1724 is a 1 unit wide VME 6U module housing a 8 Channel 14 bit 100 MS s Flash ADC Waveform Digitizer with threshold Auto Trigger capabilities The board is available with different input range memory and connector config
8. MINS TION PUPPI Ire eim IRE IUE Des ON 52 JPOWER 22 ilis ARE UPGRADE N 5 3 1 VIT24 Upgrade Jiles 4 LIST OF FIGURES FIG 1 1 V1724 BLOCK DIAGRAM NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 6 CAEN for Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 2 1 NIOD V1724 FRONT u oes eoe yea ___________________ 12 Qe 2 MOA CONNECTOR uuu DRE 13 FIG 2 3 AMP DIFFERENTIAL CONNECTOR ccccsssccccesscceeesecccessecccseccesaneceesesececsueccesaeeceesaeeceeeesecesueecessueeceeaueeeeeaes 13 3 ANPCLEINOLLTCONNICIORZ uu awa 14 FIG 2 5 PROGRAMMABLE IN OUT CONNECTOR 14 FIG 2 0 LC OPTICAL CONNECTOR uuu 15 FIG 2 7 ROTARY AND DIP SWITCHES 17 FIG 3 1 SINGLE ENDED INPUT _ _______ 19 FIG 3 2 DIFFERENTIAL INPUT DIAGRAM ccccccsssccccsssccecesececeesecccaeecceseeececseececaeeccesaeeccesuecessasecessecessusecesaueceeaes 19 FIG 3 3 CLOCK DISTRIBUTION
9. DOW Fig 3 25 A24 addressing 0x00000000 OxFFFF0000 A32 mode 31 24 23 1615 0 _ l I SW2 SW SUE 28 Fig 3 26 A32 addressing The Base Address of the module is selected through four rotary switches see 2 6 then it is validated only with either a Power ON cycle or a System Reset see 3 8 3 10 1 2 CR CSR address GEO address is picked up from relevant backplane lines and written onto bit 23 19 of CR CSR space indicating the slot number in the crate the recognised Address Modifier for this cycle is 2F This feature is implemented only on versions with 160pin connectors 31 24123 19 18 16 15 0 OFFSET Fig 3 27 CR CSR addressing q eu 3 10 1 3 Address relocation Relocation Address register see 4 41 allows to set via software the board Base Address valid values 0 Such register allows to overwrite the rotary switches settings its setting is enabled via VME Control Register see 4 32 The used addresses are 31 24 23 1615 0 a FSET eo li ADERL location 31 2423 1615 0 OFFSET software ADER L relocation Fig 3 28 Software relocation of base address A24 NPO Filena
10. 2 eooo x x _ purrerrres 00000000 eo o x x _ cusromsze x x _ ANALOG MONITORPOLARITY AND SHIFT rea ox Rw x x _ hcousmowcowmo 00 p x x _ housmowsmms eos pec TRIGGER SOURCE ENABLE MASK oeme Rw x x _ FRONTPANEL TRIGGER OUTENABLE MASK x x x posrreiccersernnc 00000000 ere pum p x x _ pronreaneL vonata 00000000 ere ox x x _ boeno laum x x _ Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 57 Ix far Driscoveri Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 REGISTER NAME _ ASE mone H ress CHANNELeNABLEMASK oso ox Rw x x _ ROCEPGAFIRMWAREREVISION eme pownsaweeracror 00000000 ens ox X x _ EewsrmD 00000000 penc x x x sermonrroroac oes p x x 0 5 jew p 00000000 pe x x _ everrsze ox x x x hwocwowoR 00000000 pem o x x _
11. p x wesmus ea opo x x _ MULTICAST ADDRESS CONTROL nec ox mw x ReLocanonavoress 00000000 x Inrerruerstausio om x Inrernuereventnumacr ox x x _ pureventuuwacr xeric p x x _ soraren _ ero om Rw x x _ sur swo jum __ penc x x _ conricurarion eons conricurarionrom ___________ lose _ 4 2 Configuration ROM OxF000 0xF084 r The following registers contain some module s information 032 accessible read only OUI manufacturer identifier IEEE OUI Version purchased version Board ID Board identifier Revision hardware revision identifier Serial MSB serial number MSB Serial LSB serial number LSB NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 58 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 Table 4 2 ROM Address Map for the Model V1724 Address Content OxF000_ 4 checksum length2 OxFO04 0x00 constant OxF014 Ox84 constantO OxF018 OxF01C OxF020 0 024 0
12. 12 22 ___________ _______ 13 2 4 1 ANALOG INPUT ________ ________ _ 13 2 4 2 13 2 4 3 ADC REFERENCE CLOCK connectors 14 2 4 4 Digital 14 2 4 5 Optical LINK COnnector 15 2 5 OTHER FRONT PANEL COMPONENTS ccccccssccssccscccsccesscesscesccenccesseescceccessseesscecceesseesscesccessseesscesccencs 15 u aa 15 4 COMPONEN 4 5 55 4 16 2 7 TECHNICAL SPECIFICATIONS TABLE 19 3 FUNCTIONAL DESCRIPTION 19 21 Lu __ _____ gt 19 3 1 1 ______ 19 3 1 2 nca UI 19 22 CLOCK DISTRIBUTION E 20 34 d Direct Drive 9 ARRIERE 20 2 2 u gt i gt uuu 21 3 2 3 21 3 2 4 Qu C RE 21 3 2 3 PODS OVC AI u
13. Bit 31 0 Reserved 4 12 Channel Configuration 0x8000 r w Allows to select Zero Suppression algorithm 0000 no zero suppression default 19 16 0001 full suppression based on the integral ZS INT 0010 zero length encoding ZLE 0011 full suppression based on the amplitude ZS AMP 15 8 reserved 0 Analog monitor disabled 1 Analog monitor enabled 0 Trigger Output on Input Over Threshold 1 Trigger Output on Input Under Threshold allows to generate local trigger either on channel over or under threshold see S 4 3 and S 4 6 5 0 Memory Random Access 1 Memory Sequential Access 3 0 Test Pattern Generation Disabled 1 5 Test Pattern Generation Enabled 2 0 Trigger Overlapping Not Enabled 1 1 Trigger Overlapping Enabled Allows to handle trigger overlap see 3 3 4 0 Window Gate 1 Single Shot Gate Allows to handle samples validation see 3 3 1 This register allows to perform settings which apply to all channels NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 61 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 It is possible to perform selective set clear of the Channel Configuration register bits writing to 1 the corresponding set and clear bit at address 0x8004 set or 0 8008 clear see the following 4 13 and 4
14. Base 0 0000 OxOFFC the first board starts to transfer its data driving DTACK properly once the transfer is completed the token is passed to the second board via the IACKIN IACKOUT lines of the crate and so on until the last board which completes the data transfer and asserts BERR which has to be enabled the Master then ends the cycle and the slave boards are rearmed for a new acquisition If the size of the BLT cycle is smaller than the events size the board which has the token waits for another BLT cycle to begin from the point where the previous cycle has ended 3 12 2 Random readout to be implemented Events can be readout partially not necessarily starting from the first available and are not erased from the memories unless a command is performed In order to perform the random readout it is necessary to execute an Event Block Request via VME Indicating the event to be read page number 12 bit datum the offset of the first word to be read inside the event 12 bit datum and the number of words to be read size 10 Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 49 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 bit datum At this point the data space can be read starting from the header which reports the required size not the actual one of the event the Trigger Time Tag the
15. 0 Channel 6 trigger disabled 1 Channel 6 trigger enabled 0 Channel 5 trigger disabled 1 Channel 5 trigger enabled 0 Channel 4 trigger disabled 1 Channel 4 trigger enabled 0 Channel 3 trigger disabled 1 Channel 3 trigger enabled 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 0 Channel 1 trigger disabled 1 Channel 1 trigger enabled EN 0 Channel 0 trigger disabled 1 5 Channel 0 trigger enabled This register 7 enable the channels to generate OUT front panel signal as the digitised signal exceeds the Vth threshold see S 3 5 3 enables to generate the TRG OUT bit1 enables Chi to generate the TRG OUT and so on EXTERNAL TRIGGER ENABLE bit30 enables the board to generate the TRG OUT SW TRIGGER ENABLE bit 31 enables the board to generate TRG OUT see 8 4 21 4 25 Post Trigger Setting 0x8114 r w 31 0 Post trigger value The register value sets the number of post trigger samples The number of post trigger samples is Npost PostTriggerValue 2 ConstantLatency where Npost number of post trigger samples PostTriggerValue Content of this register ConstantLatency constant number of samples added due to the latency associated to the trigger processing logic in the ROC FPGA This value is constant but the exact value may change between different firmware revisions NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 D
16. 028 0 02 0 01 0 43 0 52 0x00 0x40 V1724LC 0x10 V1724 VX1724 0x11 1724 VX1724B 0x40 vers OxFO30 V1724C VX1724C 0x12 V1724D VX1724D 0x41 1724 VX1724E 0x42 V1724F VX1724F 0x43 V1724 0x00 1724 0x01 0 038 OxF040 OxF044 OxF048 4 OxF080 OxF084 These data are written into one Flash page at Power ON the Flash content is loaded into the Configuration RAM where it is available for readout 4 3 Channel ZS_THRES 0x1n24 r w Bit Functin J 31 0 Positive Logic 1 Negative Logic Threshold Weight used in Full Suppression based on the integral 30 only 0 Fine threshold step Threshold 25 THRES 29 0 1 5 Coarse threshold step Threshold 25 THRES 29 0 64 represent the value to be compared with each sample of the event and see if it is over unedr threshold depending on the used logic With Zero Length Encoding the 14 LSB represent the value to be compared with each sample of the event and see if it is good or skip type see 8 3 4 and 8 4 12 With Full Suppression based on the integral the 30 LSB value represents the value depending on bit 30 to be compared with sum of the samples which compose the event and see if it is over under threshold depending on the used logic 29 0 With Full Suppression based on the amplitude the 14 LSB NPO Filena
17. Full Suppression based on the signal amplitude allows to discard data from one channel if the signal does not exceed the programmed threshold for Ns subsequent data at least Ns is programmable see S 4 4 It is also possible to configure the algorithm with negative logic in this case the data from that channel are discarded if the signal does not remain under the programmed threshold for Ns subsequent data at least see S 4 4 The following figure shows an example of Full Suppression based on the amplitude of the signal the algorithm has positive logic are enabled for acquisition therefore Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 30 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 the Channel Mask field in the Header allows to acknowledge which channel the data are coming from see also 8 3 3 5 for data format details Channel Configuration bits 19 16 0x3 25 AMP mode CH Enable Mask OxF Trigger Source Enable Mask bits 31 16 0x4000 Trigger Source Enable Mask bits 15 0 0x0 Channel n 25 THRES bit 31 2 0 Channel n 25 THRES bits 13 0 Threshold Channel n 5 NSAMP bits 31 0 Ns Threshold OUTPUT DATA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15114113 121110 9 8 7 6 5 4 3 2 110
18. THRESHOLD CH1 IN MAJORITY Fig 3 21 Majority logic 2 channels over threshold bit 6 of Ch Config Register 0 In this mode the MON output provides a signal whose amplitude is proportional to the number of channels over the trigger threshold The amplitude step 7 1 channel over threshold is 125mV 3 7 2 Test Mode Monitor Mode 1 In this mode the MON output provides a sawtooth signal with 1 V amplitude and 24 41kHz frequency 3 7 3 Analog Monitor Inspection Mode Monitor Mode 2 In this mode the MON output provides a signal whose amplitude is proportional to the sum of the board channels The following diagram shows the way the channels data are processed Hz DATA Vref 1 V H5 DATA 8 DATA 8 11 E CH3DATA 8 gt ua t MONE CH2 DATA 8 gt 11 DATA 8 HO DATA 8 CHT cHe cs cnt 1 bit D is x1 x2 x4 8 Analog Monitor Register Analog Monitor Register Analog Monitor Register Analog Monitor Register EHABLE field field OFFSET field field Fig 3 22 Inspection Mode diagram Data converted by channel ADC are brought to the FPGA via a 2 bit BUS Data transfer timing is provided by TRG CLK the available bandwidth is 200 Mb s NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 43 CAEN Q 14 rene Dri Wve Document type Title Revision date Revision User s Manual MUT Mod V1724 8 C
19. 3 3 5 3 Event format examples The event format is shown in the following figure case of 8 channels enabled with Zero Length Encoding disabled and enabled respectively see 8 3 3 5 1 and S 0 NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 28 Tools for Discovery Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 ZERO LENGHT ENCODING disabled 31 30 29 28 27 26 25 24 23 22 21120 19 18 1716151413 121110 9 8 7 6 5 4 3 2 1 0 00 SAMPLE 1 CH 0 00 SAMPLE 0 CH 0 0 0 SAMPLE 3 00 SAMPLE 2 CH 0 gt o 00 SAMPLE 1 0 00 SAMPLE 2 0 00 SAMPLE 1 00 SAMPLE 0 7 00 SAMPLE 3 0 0 SAMPLE 2 CH 7 gt a 00 SAMPLE N 1 0 0 SAMPLE N 2 CH 7 ZERO LENGHT ENCODING enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211109876543210 SIZE CONTROL
20. AD9510 programming CAEN has developed a software tool which allows to handle easily the clock parameters CAENPLLConfig is a software tool which allows the PLL management whenever the module is controlled through a CAEN VME Controller see http www caen it nuclear function1 php fun vmecnt The tool is developed through open source classes wxWidgets v 2 6 3 see http www wxwidgets org and requires the CAENVMETool API s to be installed they be downloaded at http www caen it nuclear lista sw php modzV 1718 with the SW package for CAEN VME Bridges amp Slave Boards CAENPLLConfig is available at http www caen it nuclear lista sw php mod V1 724 And must be simply run on the PC connected to the used CAEN VME Controller The User has to select the board type and base address in the ADC BOARD field then the used mode PLL or Direct Feed BYPASS in the INPUT field see figure below Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 21 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 B CAEN PLL Config BO Make output Write to Flash About foals Jor Discovery ADC BOARD Type Base address Hex OUTPUT Clock modality Sampling clock S PLL BYPASS Divide ratio Input clock MHz 10 gt 100 0000 MHz Output clock Input clock divider Enable
21. Fwp N words with samples over threshold Skip Ns Good 4 words with samples over threshold 3 If the algorithm works in positive logic and Niek 0 Ns lt lt then the readout event is 3 control words 1 size Skip N4 Good N 2 N N 2 words with samples over threshold Skip Ns 4 If the algorithm works in positive logic and NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 36 CAEN 15 for Discover Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 N lt lt 0 Fig 3 16 Example with positive logic and overlapping then the readout event is N 4 4 control words 1 size Skip Good N words with samples over threshold Good N words with samples over threshold Skip 5 N B In this case there are two subsequent GOOD intervals 5 If the algorithm works in positive logic and 0 lt Nirwo lt Nirwo gt then the readout event is 4 control words 1 size Skip Good Niek N words with samples over threshold Good Ns Niewo N 4 words wi
22. MULTI BOARD SYNC MODE Used only for Multiboard synchronisation Acquisition Status 0x8104 r Bit Function Board ready for acquisition PLL and ADCs are synchronised correctly 0 not ready 1 ready This bit should be checked after software reset to ensure that the board will enter immediatly run mode after RUN mode setting otherwise a latency between RUN mode setting and Acquisition start might occur PLL Status Flag see S 2 5 1 0 PLL loss of lock 1 PLL loss of lock NOTE flag can be restored to 1 via read access to Status Register see S 4 38 PLL Bypass mode see S 2 5 1 0 No bypass mode 1 5 Bypass mode Er Clock source see 8 2 6 5 0 7 Internal 1 5 External EVENT FULL itis set to 1 as the maximum nr of events to be read is reached EVENT READY it is set to 1 as atleast one event is available to readout 0 RUN off 1 RUN on 0 reserved Software Trigger 0x8108 w 31 0 A write access to this location generates a trigger via software Trigger Source Enable Mask 0 810 r w 0 Software Trigger Disabled 1 Software Trigger Enabled 0 External Trigger Disabled Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 64 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 x x 1 External Trigger Enabled x 29 27 reserved 1 Channel trigger ena
23. OxEF18 r w INTERRUPT EVENT NUMBER If interrupts are enabled the module generates a request whenever it has stored in memory a Number of events INTERRUPT EVENT NUMBER 4 44 BLT Event Number OxEF1C This register contains the number of complete events which has to 7 0 be transferred via BLT CBLT see 8 3 12 1 2 4 45 Scratch OxEF20 r w 31 0 Scratch to be used to write read words for VME test purposes 4 46 Software Reset OxEF24 w Bit Function 31 0 A write access to this location allows to perform a software reset 4 47 Software Clear OxEF28 w 31 0 A write access to this location clears all the memories 4 48 Flash Enable OxEF2C r w 0 Flash write ENABLED 1 Flash write DISABLED This register is handled by the Firmware upgrade tool 4 49 Flash Data OxEF30 r w 7 0 Data to be serialized towards the SPI On board Flash This register is handled by the Firmware upgrade tool 4 50 Configuration Reload OxEF34 w Bt Funtin 0 A write access to this register causes a software reset see S 3 8 a reload of Configuration ROM parameters and a PLL reconfiguration NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 71 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 5 Installation Mod V1724 fits into all
24. Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 out count The number of bytes transferred Returns An error code about the execution of the function Description The function performs a VME block transfer read cycle It can be used to perform MBLT transfers using 64 bit data width CAENVME_API CAENVME_BLTReadCycle long Handle unsigned long Address unsigned char Buffer int Size CVAddressModifier AM CVDataWidth DW int count 3 14 8 CAENVME_FIFOBLTReadCycle Parameters Handle The handle that identifies the device Address The VME bus address out Buffer The data read from the VME bus in Size The size of the transfer in bytes in AM The address modifier in DW The data width out count The number of bytes transferred Returns An error code about the execution of the function Description The function performs a VME block transfer read cycle It can be used to perform MBLT transfers using 64 bit data width The Address is not incremented on the VMEBus during the cycle CAENVME API CAENVME FIFOBLTReadaCycle int32 t Handle uint32 t Address void Buffer int Size CVAddressModifier AM CVDataWidth DW int count 3 14 9 CAENVME_MBLTReadCycle Parameters in Handle The handle that identifies the device Address The VME bus address out Buffer The data read from the VME bus in Size The size of the
25. threshold and remains under or over threshold for Nth quartets of samples at least local trigger is delayed of Nth quartets with respect to input signal This register allows to set Nth see also S 3 5 3 Channel n Status 0x1n88 r Bit 5 Buffer free error 1 7 trying to free a number of buffers too large 1 enabled CHn enabled Channel n DAC see 6 4 10 Busy 2 1 Busy 0 DC offset updated Memory empty 0 Memory full Channel n AMC FPGA Firmware 0x1n8C r Bt 0 0 15 8 Firmware Revision X 7 0 Firmware Revision Y Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 60 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format Example revision 1 3 of 12 June 2007 is 0 760 0103 4 9 Channel n Buffer Occupancy 0 11194 r Bit 10 0 Occupied buffers 0 1024 4 10 Channel n DAC 0x1n98 r w Bit DAC Data Bits 15 0 allow to define a DC offset to be added the input signal in the 1 125V 1 125V range low range or in the 1V 8V range high range see also 3 1 1 When Channel n Status bit 2 is set to 0 DC offset is updated see S 4 7 4 11 Channel ADC Configuration 0x1n9C
26. Event Counter and the part of the event required on the channel addressed in the Event Block Request After data readout in order to perform a new random readout it is necessary a new Event Block Request otherwise Bus Error is signalled In order to empty the buffers it is necessary a write access to the Buffer Free register see 4 16 the datum written is the number of buffers in sequence to be emptied BUFFERS SELECT THE BUFFER NUMBER J SELECT THE STARTING OFFSET a ADUT DATA 1 e i n i E SELECT THE BLOCKLENGHT BERR Fig 3 30 Example of random readout 3 12 3 Event Polling 3 13 NPO A read access to Event Size register see S 4 35 allows polling the number of 32 bit words composing the next event to be read this permits to perform a properly sized according to the Event Size information BLT readout from the Memory Event Buffer Optical Link The board houses a daisy chainable Optical Link able to transfer data at 80 MB s therefore it is possible to connect up to eight V1724 to a single Optical Link Controller a standard PC equipped with the PCI card CAEN Mod A2818 The A2818 is a 32 bit 33 MHz PCI card the communication path uses optical fiber cables as physical transmission line Mod AY2705 AY2720 12705 AI2720 AY2705 and AY2720 have a duplex connector on the A2818 side and two simplex connec
27. Event Ready Board ID 0 8 Bit GEO VME64X versions this register can be accessed in read mode only and contains the GEO address of the module picked from the backplane connectors when CBLT is performed the GEO address will be contained in the EVENT HEADER Board ID field see 5 3 3 5 Other versions this register can be accessed both in read and write mode it allows to write the correct GEO address default setting 0 of the module before CBLT operation GEO address will be contained in the EVENT HEADER Board ID field MCST Base Address and Control OXEFOC r w Allows to set up the board for daisy chaining 00 7 disabled board 01 last board 10 first board 11 7 intermediate These bits contain the most significant bits of the MCST CBLT address of the module set via VME i e the address used in MCST CBLT operations These bits contains the A31 A16 bits of the address of the module 15 0 it can be set VME for a relocation of the Base Address of the module Interrupt Status ID OxEF14 r w Bit 31 0 This register contains the STATUS ID that the module places on the VME data bus during the Interrupt Acknowledge cycle Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 70 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 4 43 Interrupt Event Number
28. Link daisy chain N B Optical Link is not available on the Mod V1724LC 3 14 CAENVMELIib library The Optical Link can be operated through the CAENVMELib library a set of ANSI C functions which permits an user program the use and the configuration of the modules The present description refers to CAENVMELib available in the following formats Win32 DLL CAEN provides the CAENVMELib lib stub for Microsoft Visual C 6 0 Linux dynamic library CAENVMELib is logically located between an application like the samples provided and the device driver 3 14 1 CAENVME Init Parameters BdType The model of the board V2718 in Link The index of the A2818 see figure above in BdNum The board number in the link see figure above out Handle The handle that identifies the device Returns An error code about the execution of the function Description The function generates an opaque handle to identify the module NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 51 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 attached to the PC It must be specified only the module index BdNum because the link is PCI CAENVME_API CAENVME_Init CVBoardTypes BdType short Link short BdNum long Handle 3 14 2 CAENVME_End Parameters in Handle The handle that identifies the module
29. NIM TTL 2 500 e SYNC SAMPLE START Sample front panel input NIM TTL 2410 5500 2 DAC output 1Vpp on Rt 500 not available on Mod V1724LC Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 13 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 Mechanical specifications 00 type LEMO connectors 2 4 3 ADC REFERENCE CLOCK connectors Fig 2 4 AMP CLK IN OUT Connector Function CLK IN External clock Reference input AC coupled diff LVDS ECL PECL LVPECL CML Zdiff 1100 Mechanical specifications AMP 3 102203 4 connector Function CLOCK OUT Clock output DC coupled diff LVDS Zdiff 1100 Mechanical specifications AMP 3 102203 4 AMP MODUII 2 4 4 Digital l O connectors 9 9 9 9 Fig 2 5 Programmable IN OUT Connector NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 14 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 Function N 16 programmable differential LVDS I O signals Zdiff_in 110 Ohm Four Indipendent signal group 0 3 4 7 8 11 12 15 In Out direction control see also 0 Mechanical specifications 3M 7634 5002 34 pin He
30. OVER UNDER THRESHOLD 1384 60 dl 60 4 8 CHANNEL AMC FPGA FIRMWARE OXIN8C 20 60 4 9 CHANNEL BUFFER OCCUPANCY 0 1 94 61 4 10 CHANNEL N DAC 0 1 95 50 u u u aU RE So aE duda ___ __ ______ 6___6 61 4 11 CHANNEL N ADC CONFIGURATION 9 R W 61 4 12 CHANNEL CONFIGURATION 0X8000 0 2 0 00000 0 rese en serene rns 61 4 13 CHANNEL CONFIGURATION BIT SET 0 9004 0 1 200000000 0 62 4 14 CHANNEL CONFIGURATION BIT CLEAR 0X8008 62 4 15 BUFFER ORGANIZATION 0 900 ese sese rises 62 4 16 BUFFER FREE 0X8010 252555 2 4 62 4 17 CUSTOM SIZE 0X6020 R W J 62 4 19 ANALOG MONITOR POLARITY AND SHIFT 0 902 63 4 19 ACQUISITION CONTROL OX8 1003 63 4 20 ACQUISITION STATUS 0 5104 scnssssascvrstrnsansinnnsiewnasyedonudonauinantianavnsinsesicoansesacsuwioananabbi
31. Returns An error code about the execution of the function Description Notifies the library about the end of work and free the allocated resources CAENVME_API CAENVME_End long Handle 3 14 3 CAENVME_ReadCycle Parameters in Handle The handle that identifies the device Address VME bus address out Data The data read from the VME bus in AM The address modifier in DW The data width Returns An error code about the execution of the function Description The function performs a single VME read cycle CAENVME_API CAENVME_ReadCycle long Handle unsigned long Address void Data CVAddressModifier AM CVDataWidth DW 3 14 4 CAENVME_WriteCycle Parameters in Handle The handle that identifies the device Address The VME bus address in Data The data written to the VME bus in AM The address modifier in DW The data width Returns An error code about the execution of the function 3 The Board base address set via rotary switches see 2 6 NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 22 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 Description The function performs a single VME write cycle CAENVME_API CAENVME_WriteCycle long Handle unsigned long Address void Data CVAddressModifier AM CVDataWidth DW 3 14 5 C
32. Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 jsampes 24 This register must not be written while acquisition is running 4 18 Analog Monitor Polarity and Shift 0x802A This field allows to shift the signal in order to obtain the 8 bit of the Chx DATA field see 3 7 3 out of the 14 bit converted sample Default value is 6 in this case Chx DATA represents the 8 MSB of the 14 bit converted sample If this field is 0 Chx DATA represents the 8 LSB of the 14 bit converted sample If the 8 selected bits are all 0 the transferred Chx DATA is OxFF 0 signal not inverted default value 1 signal inverted 4 19 Acquisition Control 0x8100 r w 0 Normal Mode default board becomes full whenever all buffers are full see S 4 15 1 5 Always keep one buffer free board becomes full whenever N 1buffers are full nr of blocks see 4 15 DOWNSAMPLE DISABLED 4 1 DOWNSAMPLE ENABLED allows to enable disable downsampling whose factor is set via Downsample Factor register see 4 30 0 COUNT ACCEPTED TRIGGERS 3 1 COUNT ALL TRIGGERS allows to reject overlapping triggers see 3 3 4 0 Acquisition STOP 2 1 Acquisition RUN allows to RUN STOP Acquisition 00 REGISTER CONTROLLED RUN MODE 01 S IN CONTROLLED RUN MODE m 10 S IN GATE MODE 11 MULTI BOARD SYNC MODE Bit 2 allows to Run and Stop data acquisition when such bit i
33. dip switches location NPO Filename Number of pages Page 00103 05 1724 19 V1724_REV19 DOC 74 17 Is for Discovem Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 2 7 Technical specifications table Table 2 3 Mod V1724 technical specifications 1 unit wide VME 6U module 8 channels single ended or differential depending on version 2 25Vpp 10Vpp Single ended on request input range positive or negative 40MHz Bandwidth Programmable DAC for Offset Adjust on each channel Single ended versions only Analog Input Resolution 14 bit sampling rate 10 MS s to 100 MS s simultaneously on each channel Digital Conversion Multi board synchronisation one board can act as clock master External Gate Clock capability NIM TTL by S IN input connector for burst or single sampling mode The V1724 sampling clock generation supports three operating modes PLL mode internal reference 50 MHz local oscillator ADC Sampling PLL mode external reference on CLK IN Frequency 50MHz 100ppm Other reference Clock generation frequency values are available in 10 100MHz range PLL Bypass mode External clock on CLK IN drives directly ADC clocks External clock Frequency from 10 to 100MHz CLK IN AC coupled differential input clock LVDS ECL PECL LVPECL CML CLK OUT DC coupled differential LVDS output clock locked to ADC samplin
34. lt Niek lt ONSE Fig 3 14 Example with negative logic and non overlapping Nurwp then the readout event Is N s 5 control words 1 size Good Ni N4 words with samples under threshold Skip Good Niek N words with samples under threshold Skip Good N T N5 N s words with samples under threshold In some cases the number of data to be discarded can be smaller than gk and 1 If the algorithm works in positive logic and Ni S lt 0 Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 35 CAEN Q Tools for Discover Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100 5 8 Digitizer 25 09 2009 19 22 Fig 3 15 Example with positive logic and non overlapping then the readout event is N gt 5 control words 1 size Good N N words with samples over threshold Skip Ns Good N 4 N 4 words with samples over threshold Skip N5 2 If the algorithm works in positive logic and 0 lt lt then the readout event is N N 5 control words 1 size Skip N4 Good N2
35. output single channel amplified on 0 1 V dynamics DAC MON I gt dec voltage V Analog Monitor ENABLE 0x01 gt MON Output CHO CHO Full Scale signal MAGNIFY 0 x1 OFFSET 0 2048 1 CHO Full Scale signal MAGNIFY 1 x2 OFFSET 0 CHO Full Scale signal MAGNIFY 2 x4 OFFSET 0 41792 4 75 E CHO Full Scale signal MAGNIFY 3 x8 OFFSET 0 1536 0 750 1280 0 625 1024 0 500 8 0 375 512 0 250 256 0 1 Fig 3 23 Example of Magnify parameter use on single channel The assumption is an input signal on CHO using the whole dynamics Only such channel is enabled for Analog Monitor the triangular waveform is just as example FPGA AMC of CHO sends 8MSB to FPGA ROC with 25 Mhz rate one sample out of four If no output is added and MAGNIFY factor 1x the DAC produces a copy of the signal on channel 0 with 07125 mV dynamics 1 8 of DAC dynamics If a larger dynamics is desired it is necessary increase MAGNIFY factor with MAGNIFY 8x one channel covers all the DAC available dynamics Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 44 CAEN Q Ix far Driscoveri Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 Channel sum with maximum dynamics DAC Analog Monitor ENABLE gt MON Output deci voltage CHO CH1 CH2 CHS CHS CHS CHE CH7 14 24 34 44 54 6
36. timeout expires CAENVME API CAENVME_IRQWait long dev unsigned long Mask unsigned long Timeout NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 56 Ix far Driscoveri Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 4 VME Interface The following sections will describe in detail the board s VME accessible registers content 4 1 Registers address map Table 4 1 Address Map for the Model V1724 REGISTER NAME ADDRESS ase H ress 000000 X x x Cranmera zs mres pee ox x x _ zs nsame x x x _ ox x x _ Channel n OVERIUNDER THRESHOLD x x x rammetnstarus p x x _ Cranen FPGA FIRMWARE REWSION ramet BUFFER Occupancy pene x x x x_ Gramenos ____________ _ p x x _ Chameln CONFIGURATION ox x x _ CHANNEL 0400 ox x x _ CHANNEL ox w x x _ CHANNEL CONFIGURATION CLEAR axe p x x _
37. value sampled after the S IN signal leading edge is stored data storage takes place by couples of samples two 32 bit long words per time For this purpose it is necessary to Set bits 1 0 of Acquisition Control register to S IN GATE MODE Set bit 0 of Channel Configuration Register see 5 4 12 to 1 Note that if the S IN signal is not synchronised with the sampling clock then a 1 clock period jitter occurs between the S IN leading edge and the actual sampling time S40 544 548 832 rm 816 528 50 2 520 524 e ADCDATA DO Di 02 03 X D4 05 X 06 X D11 X 012 SAMPLING CLOCK S IN D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D5 D5 D5 D5 D5 D5 D5 D5 MEMORY D9 D9 09 D9 BUFFER Fig 3 7 Data storage in Sample Mode 3 3 4 Acquisition Triggering Samples and Events When the acquisition is running a trigger signal allows to storea Trigger Time Tag TTT the value of a 32 bit counter which steps on with the sampling clock and represents a time reference increment the EVENT COUNTER see S 4 31 fil the active buffer with the pre post trigger samples whose number is programmable via Post Trigger Setting register see S 4 25 the Acquisition window width is determined via Buffer Organization register setting see S 4 15 then the buffer is f
38. with EXT CLK and in accordance with the setup time related to its leading edge In fact if EXT TRG is not correlated with EXT CLK a board might sense the trigger in a certain period of the clock while another might sense it in the subsequent Therefore an uncertainty of 1 EXT CLK period would occur and then 1 SAMP CLK hit on the position of the acquired stored buffer with respect to the trigger arrival time The distribution of trigger can be simplified through the use of a daisy chain the external trigger signal is sent to the first board in the chain and this in coincidence with the TRG IN received gets triggered and generates a TRG OUT which is in turn fed to the NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 23 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 NPO adjacent board TRG IN and so on There is a fixed latency of few clock hits between TRG IN and TRG OUT the value of this latency depends on the loaded firmware version this latency which spreads from board to board can be easily rejected by acting on the value of the Post Trigger see 3 3 in order to have acquisition windows of all modules perfectly aligned If the external trigger entering the first board is asynchronous then a one sample uncertainty occurs as described above when this uncertainty is resolved on the first board all the o
39. 14 Default value is 0x10 4 13 Channel Configuration Bit Set 0x8004 w Bit fFuncin J JJ J Bits set to 1 means that the corresponding bits in the Channel 7 0 Configuration register are set to 1 4 14 Channel Configuration Bit Clear 0x8008 w precio JJ Bits set to 1 means that the corresponding bits in the Channel 7 0 Configuration register are set to 0 4 15 Buffer Organization 0x800C r w Bit 3 0 BUFFER CODE The BUFFER CODE allows to divide the available Output Buffer Memory into a certain number of blocks according to the following table Table 4 3 Output Buffer Memory block division CODE Nr ofblocks Locations max Samples block max 0000 262144 1024K 512K 0001 131072 512K 256 0010 65536 256 128 0011 8 32768 128 0100 16384 A write access to this register causes a Software Clear see 6 3 9 This register must not be written while acquisition is running The number of Memory Locations depends on Custom size register setting see 4 17 4 16 Buffer Free 0x8010 r w 11 0 Frees the first N Output Buffer Memory Blocks see S 4 15 4 17 Custom Size 0x8020 r w Bit Function O Custom Size disabled 0 Number of memory locations per event 1 location 2 31 0 NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 62 CAEN Document type Title
40. 4 34 MONITOR 0 8144 R W ccscsccseccssceccscesscecscensscessceuscenssensscescenssenseceussencsenssseuscenssenesceuss 4 35 ip 1423 D Pt 4 36 ANALOG MONITOR 0X8150 4 37 NME uuu 4 38 NME SIAIESIOXIT 4 39 BOARD 4 40 MCST BASE ADDRESS AND CONTROL OXEFOC R NW 4 41 RELOCATION ADDRESS 000 4 42 INTERRUPT STATUS O i uu u _____ __ __ 4 43 INTERRUPT EVENT NUMBER OXEEF 18 2 1 4 44 BLT EVENT NUMBER 0 1 4 45 4 46 SOBIWARERESET OUXBE24 W u uu uu l u aaa _______6 6_ ___ _ 6 4 47 CLEAR I 4 48 FLASH ENABLE OXEF ZC 9 4 49 FLASH DATA OXEF30 4 50 CONFIGURATION RELOAD 4 W
41. A 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1413 121110 9 8 7 6 5 4 3 2 10 Channel Mask 0x5 1 Fig 3 11 Zero Length Encoding samples storage NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724 REV19 DOC 74 33 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 3 4 2 Zero Suppression Examples If the input signal is the following Fig 3 12 Zero Suppression example If the algorithm works in positive logic and lt Nirwp lt lt Fig 3 13 Example with positive logic and non overlapping Nurwp then the readout event is 5 control words 1 size Skip Good N 2 words with samples over threshold Skip Ns Ni pk Good Na Ni rwp N 4 words with samples over threshold Skip Ns NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724 REV19 DOC 74 34 CAEN Q Tools for Discover Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 NPO If the algorithm works in negative logic and Niek
42. AENVME_MultiRead Parameters in Handle The handle that identifies the device Address array of VME bus addresses out Data An array of data read from the VME bus in AM An array of address modifiers in DW An array of data widths Returns An array of error codes about the execution of the function Description The function performs a sequence of VME read cycles CAENVME API CAENVME MultiRead long Handle unsigned long Address void Data CVAddressModifier AM CVDataWidth DW 3 14 6 CAENVME MultiWrite Parameters in Handle The handle that identifies the device Address An array of VME bus addresses in Data An array of data written to the VME bus in AM An array of address modifiers DW An array of data widths Returns An array of error codes about the execution of the function Description The function performs a sequence of VME write cycles CAENVME API CAENVME ReadCycle long Handle unsigned long Address void Data CVAddressModifier AM CVDataWidth DW 3 14 7 CAENVME_BLTReadCycle Parameters in Handle The handle that identifies the device Address The VME bus address out Buffer The data read from the VME bus in Size The size of the transfer in bytes in The address modifier in DW The data width NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 53 CAEN Document type Title
43. GU VME crates 1724 versions require VME64X compliant crates the crate OFF before board insertion removal Remove all cables connected to the front panel before board insertion removal CABLES MUST BE REMOVED FROM THE FRONT PANEL BEFORE EXTRACTING THE BOARD FROM THE CRATE 5 1 Power ON sequence To power ON the board follow this procedure 1 insert the V1724 board into the crate 2 power up the crate 5 2 Power ON status At power ON the module is in the following status e the Output Buffer is cleared e registers are set to their default configuration see S 4 5 3 Firmware upgrade The board can store two firmware versions called STD and BKP respectively at Power On a microcontroller reads the Flash Memory and programs the module with the firmware version selected via the JP2 jumper see S 2 6 which can be placed either on the STD position left or in the BKP position right It is possible to upgrade the board firmware via VME by writing the Flash for this purpose download the software package available at http www caen it nuclear product php mod V1 724 The package includes the new firmware release file v1724 revX Y W Z rbf and the V1724 firmware upgrade tool e CVUpgrade exe CVUpgrade exe windows executable e CVUpgrade tool source code and VC project For upgrading the firmware utilizing CVUpgrade exe open a DOS shell then launch NPO Filename Nu
44. OC 74 66 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 4 26 Front Panel I O Data 0x8118 Bit Allows to Readout the logic level of LVDS and set the logic level of LVDS Outputs 4 27 Front Panel Control 0x811C 0 I O Normal operations TRG OUT signals outside trigger presence trigger are generated according to Front Panel Trigger Out Enable Mask setting see 4 24 1 I O Test Mode TRG OUT is a logic level set bit 14 00 General Purpose I O 01 Programmed 10 Pattern mode LVDS signals are input and their value is written into header PATTERN field see 3 3 5 0 LVDS I O 15 12 are inputs 1 LVDS 15 12 are outputs 0 LVDS I O 11 8 are inputs 1 LVDS I O 11 8 are outputs 3 0 LVDS 1 0 7 4 are inputs 1 LVDS I O 7 4 are outputs 2 0 LVDS 1 0 3 0 are inputs 1 LVDS I O 3 0 are outputs O panel output signals TRG OUT CLKOUT enabled 1 1 panel output signals TRG OUT CLKOUT enabled in high impedance 0 TRG CLK are NIM Levels 1 TRG CLK are TTL I O Levels Bits 5 2 are meaningful for General Purpose I O use only 4 28 Channel Enable Mask 0 8120 r w Bit 7 Channel 7 disabled 1 5 Channel 7 enabled 0 Channel 6 disabled 1 5 Channel 6 enabled 5 0 Channel 5 disabled 1 5 Channel 5 enabled 0 Channel 4 disabled I 4 Channel ena
45. Page 00103 05 V1724x MUTx 19 V1724 REV19 DOC 74 20 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 NPO 3 2 2 PLL Mode The AD9510 features an internal Phase Detector which allows to couple REF CLK with VCXO 1 GHz frequency for this purpose it is necessary that REF CLK is a submultiple of 1 GHz AD9510 default setting foresees the board internal clock 50 2 as clock source of REF CLK This configuration leads to Ndiv 100 5 thus obtaining 10MHz at the Phase Detector input and CLK INT 1GHz The required 100 MHz Sampling Clock is obtained by processing CLK INT through Sdiv dividers When an external clock source is used if it has 50MHz frequency then AD9510 programming is not necessary otherwise Ndiv and Rdiv have to be modified in order to achieve PLL lock A REF CLK frequency stability better than 100ppm is mandatory 3 2 3 Trigger Clock TRG CLK signal has a frequency equal to 72 of SAMP CLK therefore a 2 samples uncertainty occurs over the acquisition window 3 2 4 Output Clock Front panel Clock Output is User programmable Odiv and Odel parameters allows to obtain a signal with the desired frequency and phase shift in order to recover cable line delay and therefore to synchronise daisy chained boards CLK OUT default setting is OFF it is necessary to enable the AD9510 output buffer to enable it 3 2 5
46. RATION ssccccsssccecssecccceseccccesecccaeccesesecceseseceseeeccesueecceeuecesaeeeceseucessaneceeuaeceeaes 39 FIG 3 19 LOCAL TRIGGER RELATIONSHIP WITH COINCIDENCE 40 FIG 3 20 TRIGGER INTEGRATION ccccsescccossscccssvencescecesescecevsscsccescesesescecessscsecessenenescenesescecessseseaessenesescecesssenees 41 FIG 3 21 MAJORITY LOGIC 2 CHANNELS OVER THRESHOLD BIT 6 OF CH CONFIG REGISTER 0 43 FIG 3 22 INSPECTION MODE DIAGRAM ssccccsssccceeecceceececessececaueccessnecccssnecesaeeecesueeccesuaecessaecesaaecessuaecesaueecesees 43 FIG 3 23 EXAMPLE OF MAGNIFY PARAMETER USE ON SINGLE 2 0 0 nan 44 FIG 3 24 EXAMPLE OF MAGNIFY AND OFFSET PARAMETERS USE ON SINGLE CHANNEL 45 47 FIG 5 20 A32 ADDRESSING uu 47 PIG ADDRESS ING aiai 47 FIG 3 28 SOFTWARE RELOCATION OF BASE 565 47 OF BLT ico Ime M 49 Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 7 CAEN for Discover Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 FIG 3 30 EXAMPLE OF RANDOM READOUT 4 1200 0 0000000000000000000 50
47. RS LOCAL BUS TRIGGERS amp SYNC VME ROC FPGA Readout control VME interface control Optical link control Trigger control External interface control CPC Fig 1 1 Mod V1724 Block Diagram The function of each block will be explained in detail in the subsequent sections NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 10 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 2 Technical specifications 2 1 Packaging and Compliancy 2 1 1 Supported VME Crates The module is housed in a 6U high 1U wide VME unit The board hosts the VME P1 and P2 connectors and fits into both VME VME64 standard and V430 backplanes VX1724 versions fit VME64X compliant crates 2 1 2 Stand Alone operation When accessed through Optical Link see S 3 13 the board can be operated outside the VME Crate It is up to the User to provide the required power supplies see S 2 2 and adequate cooling ventilation 2 2 Power requirements The power requirements of the module are as follows Table 2 1 Model V1724 power requirements NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 11 CAEN Tooli for Discover Document type Title Revision date Revis
48. Technical Information Manual Revision n 19 25 September 2009 MOD V1724 8 CHANNEL 14 BIT 100 MS S DIGITIZER MANUAL REV 19 NPO 00103 05 V1724x MUTx 19 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products CAEN Is foi 00103 05 V1724x MUTx 19 Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 TABLE OF CONTENTS 1 GENERAL DESCRIPTION 9 9 2 S089 94 PIECE 10 2 JIECHNICALSPECIFICATIONS ERES 11 21 JACKAGINGAND 11 2 11 2 62 AVON Operat RETE 11 22 POWER CIR 11 235 RNIN ore
49. Trigger Enabled 0 External Trigger Disabled 1 External Trigger Enabled 0 Channel 7 trigger disabled 1 Channel 7 trigger enabled 0 Channel 6 trigger disabled 1 Channel 6 trigger enabled 5 0 Channel 5 trigger disabled 1 5 Channel 5 trigger enabled 0 Channel 4 trigger disabled 1 5 Channel 4 trigger enabled 0 Channel 3 trigger disabled 1 5 Channel 3 trigger enabled 0 Channel 2 trigger disabled 1 5 Channel 2 trigger enabled 0 Channel 1 trigger disabled 1 5 Channel 1 trigger enabled 0 Channel 0 trigger disabled 1 5 Channel 0 trigger enabled NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 65 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 This register bits 0 7 enable the channels to generate a local trigger as the digitised signal exceeds the Vth threshold see 3 5 3 enables to generate the trigger bit enables Ch1 to generate the trigger and so on EXTERNAL TRIGGER ENABLE bit30 enables the board to sense TRG IN signals SW TRIGGER ENABLE bit 31 enables the board to sense software trigger see S 4 21 4 24 Front Panel Trigger Out Enable Mask 0x8110 r w Bit 31 0 Software Trigger Disabled 1 Software Trigger Enabled 0 External Trigger Disabled 1 External Trigger Enabled 0 Channel 7 trigger disabled 1 Channel 7 trigger enabled
50. WORD 00 SAMPLE 1 00 SAMPLE 0 CH 1 z O0 0 CONTROL WORD 0 0 SAMPLE N 1 CH 1 00 SAMPLE N 2 CH 1 SIZE CONTROL WORD 00 SAMPLE 1 00 SAMPLE 0 7 CONTROL WORD 00 SAMPLE N 1 0 0 SAMPLE N 2 CH 7 Fig 3 9 Event Organization NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 29 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 3 3 6 Memory FULL management 3 4 Bits of Acquisition Control register see 4 17 allows to select Memory FULL management mode In Normal Mode the board becomes full whenever all buffers are full see S 4 15 otherwise Always one buffer free mode it is possible to always keep one buffer free board becomes full whenever N 1buffers are full with N nr of blocks see 5 4 15 In Normal Mode the board waits until one buffer is filled since FULL status is exited whether the trigger is overlapped or not The board exits FULL status at the moment which the last datum from the last channel participating to the event is read In Always one buffer free mode one buffer cannot be used therefore it is NOT POSSIBLE with this mode to set Buffer Code to 0000 see 4 15 but this allows to eliminate dead time when FULL status is exited Zero suppression The board implements three algo
51. ader Connector 2 4 5 Optical LINK connector LINK TX red wrap RX black wrap Fig 2 6 LC Optical Connector Mechanical specifications LC type connector to be used with Multimode 62 5 125um cable with LC connectors both sides not featured on Mod V1724LC Electrical specifications Optical link for data readout and slow control with transfer rate up to 80MB s daisy chainable 2 5 Other front panel components 2 9 1 Displays The front panel hosts the following LEDs Table 2 2 Front panel LEDs Name Funcion SSS O Nim 7 Standard selection for CLK V1724LC Rev 0 TRG OUT TRG IN SIN LINK green yellow Network present Data transfer activity PLL LOCK The PLL is locked to the reference clock PLL BYPS green The reference clock drives directly ADC clocks the PLL circuit is switched off and the PLL LOCK LED is turned off RUN green RUNbit set see 4 20 Trigger accepted DRDY green Event data depending on acquisition mode are present in the Output Buffer BUSY All the buffers are full OUT LVDS Signal group OUT direction enabled NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 15 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 2 6 Internal components SW2 4 5 6 Base Addr 31 16 Type 4 rotary switches Function Se
52. asia 250 0000 MHz Mie 1000 0000 MHz Fig 3 4 CAENPLLConfig Main menu 3 2 6 PLL programming In PLL mode the User has to enter the divider for input clock frequency input clock divider field in CAENPLL Config Main menu since the VCXO frequency is 1GHz in order to use for example a 50MHz ExtClk the divider to be entered is 20 Then it is necessary to set the parameters for sampling clock and CLK OUT enable divide ratio and phase shift delay in Output Clock field of CAENPLLConfig Main menu the tool refuses wrong settings for such parameters 3 2 7 Direct Drive programming In Direct Drive BYPASS mode the User can directly set the input frequency Input Clock field real values are allowed Given an input frequency it is possible to set the parameters in order to provide the required signals 3 2 8 Configuration file Once all parameters are set the tool allows to save the configuration file which includes all the AD9510 device settings SAVE button in the upper toolbar of CAENPLL Config Main menu It is also possible to browse and load into the AD9510 device a pre existing configuration file OPEN button in the upper toolbar of CAENPLL Config Main menu For this purpose it is not necessary the board power cycle NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 22 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 C
53. bilifies ___________ 46 3 10 1 1 Base mia taa sa 46 3 10 1 2 47 3 10 1 3 ________________ 47 3 11 DATA TRANSFER CAPABILITIES cccccccccsccsceucsuscuccccecccecusseuseuscsscescessessesseusesscescescessusseuseusceccescessuecs 48 3 12 BI 48 Llad 26016010 0 a 48 31211 vele 48 3 12 1 2 BLOCK TRANSFER 032 064 2 2 000 ua ESEE 48 3 12 1 3 CHAINED BLOCK TRANSFER D32 D64 49 3 12 2 Random readout to 49 NPO Filename Number of pages Page 00103 05 1724 19 1724 REV19 DOC 74 4 CAEN Q Ix for Disi ver Document type Title User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer Revision date Revision 25 09 2009 19 DP PANES p ETC CPC ERU 50 3 13 B uude LINA 50 3 14 BAL BILAN 51 A UP TL NIRE 51 SAEZ u A 52 3 14 5 _
54. bled 3 0 Channel 3 disabled 1 Channel 3 enabled 2 0 Channel 2 disabled 1 Channel 2 enabled 1 0 Channel 1 disabled 1 Channel 1 enabled EN 0 Channel 0 disabled 1 Channel 0 enabled Enabled channels provide the samples which are stored into the events and not erased The mask cannot be changed while acquisition is running NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 67 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 4 29 ROC FPGA Firmware Revision 0x8124 r 91 16 Revision date in Y M DD format Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format 4 30 Downsample Factor 0x8128 r w This register allows to set N sampling frequency will be divided by Downsampling is enabled Acquisition Control register see 8 4 17 4 31 Event Stored 0x812C r Bit This register contains the number of events currently stored in the 31 0 Output Buffer This register value cannot exceed the maximum number of available buffers according to setting of buffer size register 4 32 Set Monitor DAC 0x8138 r w 11 0 This register allows to set the DAC value 12bit This register allows to set the DAC value in Voltage level mode see 2 7 LSB 0 244 mV te
55. bled 0 Channel 6 trigger disabled 1 Channel 6 trigger enabled 0 Channel 5 trigger disabled 1 Channel 5 trigger enabled 0 Channel 4 trigger disabled 1 Channel 4 trigger enabled 0 Channel 3 trigger disabled 1 Channel 3 trigger enabled 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 0 Channel 1 trigger disabled 1 Channel 1 trigger enabled 0 Channel 0 trigger disabled 1 Channel 0 trigger enabled This register bits 0 7 enable the channels to generate a local trigger as the digitised signal exceeds the Vth threshold see 3 5 3 enables to generate the trigger enables Ch1 to generate the trigger and so on Bits 26 24 allows to set minimum number of channels that must be over threshold beyond the triggering channel in order to actually generate the local trigger signal for example if bit 7 0 FF all channels enabled and Local trigger coincidence level 1 whenever one channel exceeds the threshold the trigger will be generated only if at least another channel is over threshold at that moment Local trigger coincidence level must be smaller than the number of channels enabled via bit 7 0 mask EXTERNAL TRIGGER ENABLE bit30 enables the board to sense TRG IN signals SW TRIGGER ENABLE bit 31 enables the board to sense software trigger see S 4 21 5 3 2 1 4 23 Trigger Source Enable Mask 0x810C r w Bit 0 Software Trigger Disabled 1 Software
56. eader of the subsequent event is readout It is not possible to readout an event partially see also S 3 3 5 3 12 1 1 SINGLE D32 This mode allows to readout a word per time from the header actually 4 words of the first available event followed by all the words until the end of the event then the second event is transferred The exact sequence of the transferred words is shown in 8 3 3 5 We suggest after the 1 word is transferred to check the Event Size information and then do as many D32 cycles as necessary actually Event Size 1 in order to read completely the event 3 12 1 2 BLOCK TRANSFER D32 D64 2eVME BLT32 allows via a single channel access to read N events in sequence N is set via the BLT Event Number register see 4 44 The event size depends on the Buffer Size Register setting 4 15 namely Event Size 8 Block Size 16 bytes Smaller event size can be achieved via Custom Size setting see 3 3 4 1 and 4 17 Then it is necessary to perform as many cycles as required in order to readout the programmed number of events We suggest to enable BERR signal during BLT32 cycles in order to end the cycle avoiding filler readout The last BLT32 cycle will not be completed it will be ended by BERR after the N event in memory is transferred see example in the figure below Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 48 CAEN Document type Title Revisio
57. ffer 0 976 mV This mode allows to test the readout efficiency in fact if the average event readout throughput is as fast as trigger rate then MON out value remains constant otherwise if MON out value grows in time this means that readout rate is slower than trigger rate 3 7 5 Voltage Level Mode Monitor Mode 4 In this mode MON out provides a voltage value programmable via the N parameter written in the SET MONITOR DAC register with Vmon 1 4096 N Volt NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 45 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 3 8 Test pattern generator The FPGA AMC can emulate the ADC and write into memory a ramp 0 1 2 3 3FFF 3FFE 0 for test purposes It can be enabled via Channel Configuration register see 4 12 3 9 Reset Clear and Default Configuration 3 9 f Global Reset Global Reset is performed at Power ON of the module or via a VME RESET SYS RES see S 4 46 It allows to clear the data off the Output Buffer the event counter and performs a FPGAs global reset which restores the FPGAs to the default configuration It initialises all counters to their initial state and clears all detected error conditions 3 9 2 Memory Reset The Memory Reset clears the data off the Output Buffer The Memory Reset can be forwarded via either a wr
58. ft In order to keep all dividers outputs aligned the AD9510 is provided with a SYNCB input see S 3 2 all dividers are put in phase on a SYNCB edge This is done automatically within a board at any board reset therefore it is guaranteed that one board has the same sampling clock for all channels However if it is necessary to synchronize sampling clock on more V1724s then SYNCB signals have to be synchronized in their turn as well On modules with printed board Rev 2 or greater synchronization is achieved by piloting SYNCB through a D Edge Triggered Flip Flop receiving EXT as clock input In this way it is ensured that the SYNCBs of all modules have the same phase On modules with printed board Rev 1 however the synchronization SYNCB can be obtained through the S IN signal In fact on S IN leading edge when the board is properly programmed see 3 3 1 the ROC FPGA sends a pulse on SYNCB In order to avoid uncertainty it is necessary that S IN is sent to all the modules in phase with EXT CLK this will allow all V1724s to receive it with the same clock period After the synchronization of sampling clock signals the modules will be also in phase with each other and all samples will be written into memory all at the same time However in order to ensure that the windows of acquisition related to the external trigger signal are also perfectly aligned it is also necessary that the TRG IN signal is sent to all modules synchronously
59. g clock Frequency values in 10 100MHz range are available 512K sample ch or 4M sample ch see 1 1 Multi Event Buffer with independent read and write access Programmable event size and pre post trigger Divisible into 1 1024 buffers Common External TRGIN NIM or TTL and VME Command Trigger Individual channel autotrigger time over under threshold TRGOUT NIM or TTL for the trigger propagation to other V1724 boards Trigger Time Stamp 32bit 10ns 43s range Sync input for Time Stamp alignment AMC FPGA One Altera Cyclone 1 4 or EP1C20 per channel Data readout and slow control with transfer rate up to 80 MB s to be used instead of VME bus Daisy chainable one A2818 PCI card can control and read eight V1724 boards in a chain not available on Mod V1724LC VME64X compliant D32 BLT32 MBLT64 CBLT32 64 2eVME 2eSST Multi Cast Cycles Transfer rate 60 MBLT64 100MB s 2eVME 160MB s 2eSST Sequential and random access to the data of the Multi Event Buffer The Chained readout allows to read one event from all the boards in a VME crate with a BLT access Upgrade V1724 firmware can be upgraded via VME General purpose C Libraries and Demo Programs CAENScope 12bit 100MHz DAC controlled by ROC FPGA supports five operating modes Waveform Generator 1 Vpp ramp generator Majority MON 2 output signal is proportional to the number of ch under over threshold 1 step 125mV Analog Inspection data st
60. g the pre trigger of the event is not reached yet this happens typically as the trigger occurs too early either with respect to the RUN ACQUISITION command see S 3 3 1 or with respect to a buffer emptying after a MEMORY FULL status the trigger overlaps the previous one and the board is not enabled for accepting overlapped triggers As a trigger is refused the current buffer is not frozen and the acquisition continues writing on it The Event Counter can be programmed in order to be either incremented or not If this function is enabled the Event Counter value identifies the number of the triggers sent but the event number sequence is lost if the function is not enabled the Event Counter value coincides with the sequence of buffers saved and readout 3 3 4 1 Custom size events It is possible to make events with a number of Memory locations which depends on Buffer Organization register setting see S 4 15 smaller than the default value One memory location contains two ADC samples and the maximum number of memory locations is therefore half the maximum number of samples per block NS 512K Nblocks Smaller values can be achieved by writing the number of locations into the Custom Size register see S 4 17 NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 27 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Di
61. ger Source Enable Mask see 5 4 22 bits 7 0 FF all channels enabled and Local trigger coincidence level 1 bits 26 24 whenever an enabled channel exceeds the threshold the trigger will be generated only if at least another channel is over threshold at that moment Local trigger coincidence level must be smaller than the number of channels enabled via bit 7 0 mask The following figure shows examples with Local trigger coincidence level 1 and 0 NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 39 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 CHO THRESHOLD CHO IN CH1 THRESHOLD CH1 IN LOCAL TRG 0 LOCAL TRG 1 TRIGGER Coinc lev 1 TRIGGER Coinc lev 0 Fig 3 19 Local trigger relationship with Coincidence level 3 5 4 Trigger distribution The OR of all the enabled trigger sources after being synchronised with the internal clock becomes the global trigger of the board and is fed in parallel to all the channels which store an event A Trigger Out is also generated on the relevant front panel TRG OUT connector NIM or TTL and allows to extend the trigger signal to other boards For example in order to start the acquisition on all the channels in the crate as one of the channels ramps over threshold the Local Trigger must be enabled as Trigger Out the Trigger Out must the
62. gitizer 25 09 2009 19 0 means default size events i e the number of memory locations is the maximum allowed 1 with the constraint lt 1 lt means that one event will be made of 2 1 samples 3 3 5 Event structure An event is structured as follows Header 4 32 bit words Data variable size and format The event can be readout either via VME or Optical Link data format is 32 bit long word therefore each long word contains 2 samples 3 3 5 1 Header It is composed by four words namely Size of the event number of 32 bit long words Board ID GEO Bit24 data format 02 normal format 17 Zero Length Encoding data compression method enabled see S 3 4 16 bit pattern latched on the LVDS see 3 6 as one trigger arrives see 4 27 Channel Mask 5 1 channels participating to event ex CHS and CH7 participating Ch Mask this information must be used by the software to acknowledge which channel the samples are coming from Event Counter It is the trigger counter it can count either accepted triggers only or all triggers see S 4 17 Trigger Time Tag It is a 32 bit counter 31 bit count 1 overflow bit which is reset either as acquisition starts or via front panel Reset signal see S 3 8 and is incremented at each sampling clock hit It is the trigger time reference Event structure 3 3 5 2 Samples Stored samples data from masked channels are not read
63. hannel 14bit 100MS s Digitizer 25 09 2009 19 NPO The FPGA ROC handles 8 bit data Data rate is 74 of TRG CLK Chx DATA represents 8 bit of the converted sample selected via the Analog Monitor Polarity amp Shift register see 4 18 on modules with Piggy Back revision older than 0 B Chx DATA represents the 8 MSB of the converted sample Data from 8 channels are summed each channel can be enabled see Analog Monitor Register at 4 36 to participate or not to the sum The sum value is provided on 11 bit bit 31 of Analog Monitor register see 4 36 allows to invert the sum a positive negative offset also encoded on 11bit can be added to the sum there is a sign bit in the Analog Monitor Register to select offset polarity The sum value can be multiplied by a fixed factor MAGNIFY x1 x2 x4 x8 The final result 11 bit dynamics allows to drive the DAC The DAC output has 1V dynamics and drives 50 Ohm 3 7 3 1 Procedure to enable Analog Monitor mode In order to enable Analog Monitor mode is necessary to enable the channels to send data to FPGA ROC by setting to 1 bit 7 of Channel Configuration register see 4 12 If this bit is set the datum sent is always 0 Configure the Analog Monitor register with the desired settings Enable Analog Monitor mode set to 2 the Monitor Mode register 3 7 3 2 Applications examples These examples show the effect of the channel offset magnify parameters over MON
64. hannel 14bit 100MS s Digitizer 25 09 2009 19 3 2 9 Multiboard synchronisation In order to allow several V1724s to work synchronously same sampling clock for all channels it is necessary to use the external clock For such purpose two solutions are possible daisy chain where the clock is propagated from one board to another with the first board used as a clock master whose source could be either the internal clock or an external reference managed by the User tree structure with an equalized clock distributor fan out unit with low skew outputs and constant cables length In both cases the goal is to have all REF CLK signals with the same phase Since the PLL aligns the phase of VCXO output signal to REF CLK the result of synchronization is that all V1724s have the 1GHz VCXO output signals perfectly aligned in phase However despite the V1724s having all the same 1GHz reference it is not guaranteed that the sampling clock is in its turn aligned In fact the use of clock dividers to produce the sampling clock may lead such signals to have different phases as shown in the following picture where two 250MHz divider 4 see 6 3 2 5 are obtained from a 1GHz VCXO output Out S CLK 1 S CLK 2 Fig 3 5 Sampling clock phase shi
65. houses a 12bit 100MHz DAC with 0 1 V dynamics on a 50 Ohm load see Fig 1 1 whose input is controlled by the ROC FPGA and the signal output driving 50 Ohm is available on the MON 2 output connector MON output of more boards can be summed by an external Linear Fan In This output is delivered by a 12 bit DAC The DAC control logic implements five operating modes Trigger Majority Mode Monitor Mode 0 Test Mode Monitor Mode 1 Analog Monitor Inspection Mode Monitor Mode 2 Buffer Occupancy Mode Monitor Mode 3 Voltage Level Mode Monitor Mode 4 Operating mode is selected via Monitor Mode register see S 4 34 N B this feature is not available on the Mod V1724LC 3 7 1 Trigger Majority Mode Monitor Mode z 0 It is possible to generate a Majority signal with the DAC a voltage signal whose amplitude is proportional to the number of channels under over see 8 4 12 threshold 1 step 125mV this allows via an external discriminator to produce a global trigger signal as the number of triggering channels has exceeded a particular threshold NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 42 CAEN Q Is for Discove Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 Nth 4samples wawawa Nth 4samples lt THRESHOLD IN Nth 4samples 4samples
66. ic Range 1 Vpp Positive Unipolar 2 25 DAC FSR 1 125 FPGA 0 1 125 2 25 V MCX Input WV Negative Unipolar 0 Bipolar DAC FSR 2 Fig 3 1 Single ended input diagram 3 1 2 Differential input Input dynamics is 1 125V Zin 50 Q The input bandwidth ranges from DC to 40 MHz with 2nd order linear phase anti aliasing low pass filter Differential Mode MODUII Fig 3 2 Differential input diagram NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 19 Tools F Dis C Ter Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 3 2 Clock Distribution 1GHz VCXO CLK CLK Source 17777777777777777777777777777 VCXO Feedback loo EXT INT EXT CLK MEZZANINES x4 Charge Detector Pump only for PCB E SAMP CLKO 2 or higher 2 2 SAMP CLK1__ SAMP CLK2 Acquisition SvhcB 8 andas Control TRIGGER TRG IN I Trigger amp Sy
67. ion User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 2 3 Front Panel Mod V1724 CLOCK IN INTERNAL CLOCK OUT TRG OUT LOCAL TRIGGER OUT EXTERNAL TRIGGER IN SYNC SAMPLE START ANALOG INPUT ANALOG MONITOR OUTPUT DIGITAL I O s 8 CH 14 BIT 100 5 5 DIGITIZER Fig 2 1 Mod V1724 front panel NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 12 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 2 4 NPO External connectors 2 4 1 ANALOG INPUT connectors CHO Fig 2 2 MCX connector Single ended version see options in 1 1 Function Analog input single ended input dynamics 2 25Vpp Zin 50Q on request 10Vpp Zin 1KQ Mechanical specifications MCX connector CS 85MCX 50 0 16 SUHNER CHO Fig 2 3 AMP Differential connector Differential version see options in S 1 1 Function Analog input differential input dynamics 2 25Vpp Zin 100Q or 10Vpp Zin 1KQ Mechanical specifications AMP 3 102203 4 AMP MODUII N B absolute max analog input voltage 6Vpp with Vrail max to 6V or 6V for any DAC offset value 2 4 2 CONTROL connectors Function e TRG OUT Local trigger output NIM TTL on Rt 500 e TRG IN External trigger input
68. ite access to Software Clear Register see S 4 47 or with a pulse sent to the front panel Memory Clear input see S 0 3 9 3 Timer Reset The Timer Reset allows to initialize the timer which allows to tag an event The Timer Reset can be forwarded with a pulse sent to Trigger Time Tag Reset input see S O 3 10 VMEBus interface The module is provided with a fully compliant 4 64 interface see 1 1 whose main features are EUROCARD 90 Format J1 P1 and J2 P2 with either 160 pins 5 rows or 96 3 rows connectors 24 A32 and CR CSR address modes 032 BLT MBLT 2eVME 2eSST data modes write capability CBLT data transfers interrupter Configuration ROM 3 10 1 Addressing capabilities 3 10 1 1 Base address The module works in A24 A32 mode The Base Address of the module can be fixed through four rotary switches see S 2 6 and is written into a word of 24 or 32 bit The Base Address can be selected in the range NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 46 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 0x000000 OxFF0000 A24 mode 31 24 23 1615 0 OFFSET DX DRY DAA DR RR DOE DROW DR NNNNNNSS DR DR RRR DIAL
69. mber of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 72 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 NPO CVUpgrade FileName BaseAdd image fast nover where FileName is the RBF file BaseAdd is the Base Address Hex 32 bit of the V1724 image is standard default or backup fast enables fast programming MultiRead Write with CAEN Bridge nover disables programming check N B it is strongly suggested to upgrade ONLY one of the stored firmware revisions generally the STD one if both revision are simultaneously updated and a failure occurs it will not be possible to upload the firmware via VME again IMPORTANT NOTE all modules featuring PCB Rev 0 do not support firmware release v1724 revX1 2 0 4 rbf and later PCB revision Revision Field can be read at Configuration ROM see 4 2 Contact support nuclear caen it in order to upgrade firmware of modules featuring PCB 0 5 9 1 V1724 Upgrade files description The board hosts one FPGA on the mainboard and one FPGA for each of the eight channels The channel FPGAs firmware is identical A unique file is provided that will updated all the FPGA at the same time ROC FPGA MAINBOARD FPGA Readout Controller VME interface There is one FPGA Altera Cyclone EP1C20 AMC FPGA CHANNEL FPGA ADC readout Memory Controller There is one FPGA Al
70. me Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 47 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 3 11 Data transfer capabilities 3 12 The board supports 032 single data readout Block Transfer BLT32 and MBLT64 2eVME and 2eSST cycles Sustained readout rate is up to 60 MB s with MBLT64 up to 100 MB s with 2eVME and up to 160 MB s with 2eSST Events readout 3 12 1 Sequential readout NPO The events once written in the SRAMs Memory Event Buffers become available for readout via VME During the memory readout the board can continue to store more events independently from the readout on the free buffers The acquisition process is therefore deadtimeless until the memory becomes full Although the memories are SRAMs VMEBus does not handle directly the addresses but takes them from a FIFO Therefore data are read from the memories sequentially according to the selected Readout Logic from a memory space mapped on 4Kbytes 0x0000 0x0FFC The events are readout sequentially and completely starting from the Header of the first available event followed by the Trigger Time Tag the Event Counter and all the samples of the channels from 0 to 7 Once an event is completed the relevant memory buffer becomes free and ready to be written again old data are lost After the last word in an event the first word H
71. me Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 59 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 4 4 Channel n Z8 NSAMP 0x1n28 r w 4 5 4 6 4 7 4 8 NPO With Full Suppression based on the amplitude 25 AMP bits 20 0 allow to set the number Ns of subsequent samples which must be found over under threshold depending on the used logic necessary to validate the event if this field is set to O it is considered 1 With Zero length encoding ZLE bit 31 16 allows to set read Ni the number of data to be stored before the signal crosses the threshold bit 15 0 allows to set read Ni wp the number of data to be stored after the signal crosses the threshold see 3 4 and 8 4 12 Channel n Threshold 0x1n80 r w Bt 1111 Funcin Threshold Value for Trigger Generation Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold and remains under or over threshold for Nth couples of samples at least local trigger is delayed of Nth quartets of samples with respect to input signal This register allows to set Vth LSB input range 14bit see also S 3 5 3 Channel n Over Under Threshold 0x1n84 r w Bit 11 0 Number of Data under over Threshold Each channel can generate a local trigger as the digitised signal exceeds the Vth
72. n be fed to a Fan Out unit the obtained signal has to be fed to the External Trigger Input of all the boards in the crate including the board which generated the Trigger Out signal NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 40 CAEN Toody ror DI overt Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 CLOCK REF CLOCK DISTRIB IN TRIGGER External of generated Progr Phase shit Simultaneous start of run Common ta all and time re erence channels by a master board OPTICAL LINK Readout and or control B MB s up to 8 boards TRIGGER LOGIC V1485 um ANALOG OUTPUT 11 Linear Sum Majority TRIGGER BUS Trigger Tagging Digital Majority Over Threshold Coincidence matrix ADCs data stream Fig 3 20 Trigger integration 3 6 Front Panel I Os The V1724 is provided with 16 programmable general purpose LVDS 1 signals Signals can be programmed via VME see 4 26 and 4 27 Default configuration is Number of pages Page NPO Filename 4 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 Table 3 2 Front Panel I Os default setting Ch 6 Trigger Request 3 7 Analog Monitor The board
73. n date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 NPO READOUT DATA BUFFERS Block size 1024 bytes BERR enabled BLT size 16384 bytes N 4 Fig 3 29 Example of BLT readout Since some 64 bit CPU s cut off the last 32 bit word of a transferred block if the number of words composing such block is odd it is necessary to add a dummy word which has then to be removed via software in order to avoid data loss This can be achieved by setting the ALIGNGA bit in the VME Control register see 4 32 MBLT64 cycle is similar to the BLT32 cycle except that the address and data lines are multiplexed to form 64 bit address and data buses The 2eVME allows to achieve higher transfer rates thanks to the requirement of only two edges of the two control signals DS and DTACK to complete a data cycle 3 12 1 3 CHAINED BLOCK TRANSFER D32 D64 The V1724 allows to readout events from more daisy chained boards Chained Block Transfer mode The technique which handles the CBLT is based on the passing of a token between the boards it is necessary toverify that the used VME crate supports such cycles Several contiguous boards in order to be daisy chained must be configured as first intermediate or last via MCST Base Address and Control Register see 8 4 40 A common Base Address is then defined via the same register when a BLT cycle is executed at the address
74. name Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 74
75. nc TRG OUT 5 S IN 0 LOCAL BUS 2 Fig 3 3 Clock distribution diagram The module clock distribution takes place on two domains OSC CLK and REF CLK the former is a fixed 50MHz clock provided by an on board oscillator the latter provides the ADC sampling clock OSC CLK handles both VME and Local Bus communication between motherboard and mezzanine boards see red traces in the figure above REF CLK handles ADC sampling trigger logic acquisition logic samples storage into RAM buffer freezing on trigger through a clock chain Such domain can use either an external via front panel signal or an internal via local oscillator source selection is performed via dip switch SW1 see 2 6 in the latter case OSC CLK and REF CLK will be synchronous the operation mode remains the same anyway REF CLK is processed by AD9510 device which delivers 6 clock out signals 4 signals are sent to ADCs one to the trigger logic and one to drive CLK OUT output refer to AD9510 data sheet for more details http www analog com UploadedFiles Data Sheets AD9510 pdf two operating modes are foreseen Direct Drive Mode and PLL Mode 3 2 1 Direct Drive Mode The aim of this mode is to drive externally the ADCs Sampling Clock generally this is necessary when the required sampling frequency is not a VCXO frequency submultiple The only requirement over the SAMP CLK is to remain within the ADCs range NPO Filename Number of pages
76. nenosoncasenenevnreen 64 4 21 SOFTWARE TRIGGER OX8 1083 64 4 22 TRIGGER SOURCE ENABLE MASK OX8 LOC 48044 64 NPO Filename 00103 05 V1724x MUTx 19 V1724_REV19 DOC Number of pages Page 74 5 CAEN Q ix for Driscovi Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 4 23 TRIGGER SOURCE ENABLE MASK 0X810C 4 24 FRONT PANEL TRIGGER OUT ENABLE MASK 0X81 10 RAW 4 25 POST TRIGGER SETTING 0X 81 14 4 26 FRONTPANBL DOJDATATOXSTTS R W 5 4 27 FRONT PANEL I O CONTROL 0X81 1C R W 4 28 CHANNEL ENABLE MASK 0X8120 0 0 0 0 0 ne nene rese rh ener en rennen nen 4 29 ROC FPGA FIRMWARE REVISION 0 9124 0000 0 00 rr nennt nnns 4 30 DOWNSAMPLE FACTOR 0 5128 4 3 A enne urs EDD gt 4 32 SET MONITOR DAC 0 8138 4 33 BOARD INFO 0 8140 R ccccccsseccsssscesssccuveccnseccesssceussceeseccesecenseserersceuecensecessesssusscensecensscensescees
77. nnel can generate a local trigger as the digitised signal exceeds the Vth threshold ramping up or down depending on VME settings and remains under or over threshold for Nth quartets of samples at least Nth is programmable via VME The Vth digital threshold the edge type and the minimum number Nth of couples of samples are programmable via VME register accesses see 4 3 and 4 6 actually local trigger is delayed of Nth quartets of samples with respect to the input signal NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724 REV19 DOC 74 38 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 N B the local trigger signal does not start directly the event acquisition on the relevant channel such signal is propagated to the central logic which produces the global trigger which is distributed to all channels see 3 5 4 Nth 4samples Nth Nth 4samples 4samples 8 x THRESHOLD CHO IN Local Trigger CH0 Channel Configuration register lt 6 gt 0 Local Trigger CH0 Channel Configuration register lt 6 gt 1 Fig 3 18 Local trigger generation 3 5 3 1 Trigger coincidence level It is possible to set the minimum number of channels that must be over threshold beyond the triggering channel in order to actually generate the local trigger signal If for example Trig
78. ol set to 01 3 3 2 Gate and Sample mode acquisition It is possible to use the S IN signal see S 2 4 2 as gate to enable samples storage The samples produced by the 100 MHz ADC are stored in memory only if they are validated by the S IN signal otherwise they are rejected data storage takes place by couples of samples two 32 bit long words per time Two operating modes are foreseen as decrbed in the following 3 3 2 1 Gate mode In Gate mode all the values sampled as the S IN signal is active high are stored for this purpose it is necessary to Set bits 1 0 of Acquisition Control register to S IN GATE MODE Set bit 0 of Channel Configuration Register see S 4 12 to 0 All the values sampled as the S IN signal is active high are stored S40 S44 536 _ 548 5 58 852 S4 _ 5 207 I _ 516 yd 50 520 524 f ADCDATA DO X D1 X 02 D3 DS lt D7 X D10 X X D12 SAMPLING CLOCK mE S IN MEMORY BUFFER Fig 3 6 Data Storage in Gate mode Underscored stored NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 25 L A PRELIMINARY Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 3 3 3 Sample mode In Sample mode only the first
79. ol word type is good then it will be followed by as many data as those indicated in the stored skipped words field if the control word type is skip then it will be followed by a good control world unless the end of event is reached IMPORTANT NOTE the maximum allowed number of control words is 62 14 for piggy back release 0 6 and earlier therefore the ZLE is active within the event until the 14 transition between a good and a skip zone or between a skip and a good zone All the subsequent samples are considered good and stored The following figure shows an example of Zero Length Encoding the algorithm has positive logic CHO CH3 are enabled for acquisition therefore the Channel Mask field in the Header allows to acknowledge which channel the data are coming from see also 3 3 5 for data format details Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 32 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 Settings CH Enable Mask OxF Channel Configuration bits 19 16 0x2 ZLE mode Trigger Source Enable Mask bits 31 16 0x4000 Trigger Source Enable Mask bits 15 0 0x0 Channel n Z8 THRES bit 31 0 Channel n Z8 THRES bits 13 0 5 Threshold Channel n 25 NSAMP bits 31 16 Nlfwd Channel n Z8 NSAMP bits 15 0 NIbk Threshold OUTPUT DAT
80. on of the function Description The function returns a bit mask indicating the active IRQ lines CAENVME_API CAENVME IRQCheck long Handle byte Mask 3 14 12 CAENVME IRQEnable Parameters Handle The handle that identifies the device in Mask A bit mask indicating the IRQ lines Returns An error code about the execution of the function Description The function enables the IRQ lines specified by Mask Actually only bit 0 in the mask is meaningful NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 55 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 CAENVME_API CAENVME_IRQEnable long dev unsigned long Mask 3 14 13 CAENVME IRQDisable Parameters Handle The handle that identifies the device Mask A bit mask indicating the IRQ lines Returns An error code about the execution of the function Description The function disables the IRQ lines specified by Mask CAENVME API CAENVME_IRQDisable long dev unsigned long Mask 3 14 14 IRQWait Parameters Handle The handle that identifies the device Mask A bit mask indicating the IRQ lines in Timeout Timeout in milliseconds Returns An error code about the execution of the function Description The function waits the IRQ lines specified by Mask until one of them raise or
81. ream from one channel ADC drives directly the DAC input producing the channel input signal 1 Vpp Memory Buffer Optical Link VME interface Analog Monitor not available in V1724LC Buffer Occupancy MON 2 output signal is proportional to the Multi Event Buffer Occupancy 1 buffer 1mV Voltage level MON 2 output signal is a programmable voltage level 16 general purpose LVDS controlled by the FPGA Busy Data Ready Memory full Individual Trig Out and other function can be programmed An Input Pattern from the LVDS I O can be associated to each trigger as an event marker LVDS I O NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 18 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 3 Functional description 3 1 Analog Input The module is available either with single ended on MCX connector or on request differential on Tyco MODU 1 3 pin connector input channels 3 T 1 Single ended input Input dynamic is 2 25Vpp Zin 50 10Vpp Zin 1K dynamic is available on request A 16bit DAC allow to add up to 1 125V 5V with high range input DC offset in order to preserve the full dynamic range also with unipolar positive or negative input signals The input bandwidth ranges from DC to 40 MHz with 2nd order linear phase anti aliasing low pass filter Input Dynam
82. rithms of Zero Suppression and Data Reduction Full Suppression based on the integral of the signal ZS_INT Full Suppression based on the signal amplitude ZS_AMP Zero Length Encoding ZLE The algorithm to be used is selected via Configuration register see 4 12 and its configuration takes place via two more registers CHANNEL n 25 THRES and CHANNEL n ZS NSAMP When using 25 and 25 algorithms it must be noticed that that one datum 32 bit long word contains 2 samples therefore depending also on trigger polarity settings of bit31 of Channel n 25 THRES register threshold is crossed if Positive Logic one datum is considered OVER threshold if at least one sample is higher or equal to threshold Negative Logic one datum is considered UNDER threshold if at least one sample is lower than threshold 3 4 1 Zero Suppression Algorithm NPO 3 4 1 1 Full Suppression based on the integral of the signal Full Suppression based on the integral of the signal allows to discard data from one channel if the sum of all the samples from this channel is smaller than the threshold set by the User see 4 3 It is also possible to configure the algorithm with negative logic in this case the data from that channel are discarded if the sum of all the samples from that channel is higher than the threshold set by the User see S 4 3 3 4 1 2 Full Suppression based on the amplitude of the signal
83. rminated on 50 Ohm 4 33 Board Info 0x8140 Bt 15 8 Memory size Mbyte channel Board Type 7 0 0 V1724 4 34 Monitor Mode 0x8144 r w This register allows to encode the Analog Monitor see 3 7 operation 000 Trigger Majority Mode 001 Test Mode 010 Analog Monitor Inspection Mode 011 Buffer Occupancy Mode 100 Voltage Level Mode NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 68 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 4 35 Event Size 0x814C r 31 0 Nr of 32 bit words in the next event 4 36 Analog Monitor 0x8150 r w Analog Inspection inverter 31 0 1 1 1 Magnify factor 00 1x 21 20 01 2x 10 4x 11 8x 19 18 8 7 0 Channel 7 disabled 1 5 Channel 7 enabled 0 Channel 6 disabled 1 5 Channel 6 enabled 0 Channel 5 disabled 1 Channel 5 enabled 4 0 Channel 4 disabled 1 Channel 4 enabled 3 Channel 3 disabled 1 Channel 3 enabled 2 0 Channel 2 disabled 1 Channel 2 enabled 0 Channel 1 disabled 1 5 Channel 1 enabled EN 0 Channel 0 disabled 1 5 Channel 0 enabled 4 37 Control r w 5 0 Release On Register Access Interrupt mode default 1 Release On AcKnowledge ROAK Inter
84. rozen for readout purposes while acquisition continues on another buffer Table 3 1 Buffer Organization REGISTER BUFFER NUMBER SIZE of one BUFFER samples __ SKM 2 OM 8 Underscored stored NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 26 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 An event is therefore composed by the trigger time tag pre and post trigger samples and the event counter Overlap between acquisition windows may occur a new trigger occurs while the board is still storing the samples related to the previous trigger this overlap can be either rejected or accepted programmable via VME If the board is programmed to accept the overlapped triggers as the overlapping trigger arrives the current active buffer is filled up then the samples storage continues on the subsequent one In this case events will not have all the same size see figure below EVENT n EVENT n 1 EVENT n 2 Recorded Not Recorded TRIGGER PRE POST ACQUISITION WINDOW Overlapping Triggers Fig 3 8 Trigger Overlap A trigger can be refused for the following causes acquisition is not active memory is FULL and therefore there are no available buffers the required number of samples for buildin
85. rupt mode 0 RELOC Disabled BA is selected via Rotary Switch see 8 2 6 1 RELOC Enabled is selected RELOC register see S 4 41 0 ALIGN64 Disabled 1 ALIGN64 Enabled see S 3 12 1 2 0 BERR Not Enabled the module sends a DTACK signal until the CPU inquires the module 4 1 5 BERR Enabled the module is enabled either to generate a Bus error to finish a block transfer or during the empty buffer read out in D32 0 Optical Link interrupt disabled 1 5 Optical Link interrupt enabled Bit 7 this setting is valid only for interrupts broadcasted on VMEbus interrupts broadcasted on optical link feature RORA mode only n RORA mode interrupt status can be removed by accessing VME Control register see 4 37 and disabling the active interrupt level 7 NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 69 CAEN Q Document type User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 4 38 4 39 4 40 4 41 4 42 NPO Title Revision date Revision In ROAK mode interrupt status is automatically removed via an interrupt acknowledge cycle Interrupt generation is restored by setting an Interrupt level gt 0 via VME Control register VME Status OxEFO04 0 BERR FLAG no Bus Error has occurred 1 BERR FLAG a Bus Error has occurred this bit is re set after a status register read out Reserved 0 No Data Ready 1
86. s set to 1 the board enters Run mode and a Memory Reset see 3 9 2 is automatically performed When bit 2 is reset to 0 the stored data are kept available for readout In Stop Mode all triggers are neglected Bits 1 0 descritpion 00 REGISTER CONTROLLED RUN MODE multiboard synchronisation via S_IN front panel signal control start stop set clear of bit 2 GATE always active Continuous Gate Mode or Downsample Mode Continuous Gate Mode can be used only if Channel gate mode see 4 12 is set in Window Mode Downsample Mode can be used prior DOWNSAMPLE FACTOR register see 8 4 30 valid setting 40 01 S IN CONTROLLED RUN MODE Multiboard synchronisation via S IN front panel signal NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 63 CAEN Q Document type User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 4 20 4 21 4 22 NPO Title Revision date Revision S IN works both as SYNC and RUN START command GATE always active Continuous Gate Mode or Downsample mode Continuous Gate Mode Gate always active to be used only if Channel Gate Mode CHANNEL Configuration Register is set to Window Mode AJ Downsample Mode it is set via DOWNSAMPLE ENABLE and a value 0 at DOWNSAMPLE FACTOR register 10 S IN GATE MODE Multiboard synchronisation is disabled S IN works as Gate signal set clear of RUN STOP bit 11
87. t the VME base address of the module SW3 CLOCK SOURCE Type Dip Switch Function Select clock source External or Internal SW1 FW Type Dip Switch Function it allows to select whether the Standard STD or the Back up BKP firmware must be loaded at power on default position STD NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 16 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 7 Pa GND 115 f ne u u 5 x em 0 115079 1 aks ray a B Meee II ss 222005 T P gg 8 TD Rx ET pieta RI L L 00 00 B Ba 88 3 ae 0 ES b SU 90 T p qr Ex T pH m 4 all d sl i us 8188 81 pe n 8171 EN 25 21 1 1 10 183 E nmm rere C FEMA WEE mapp lezie he L T Fig 2 7 Rotary and
88. tera Cyclone EP1C4 EP1C20 in V1724E VX1724E V1724F VX1724F version All FPGAs can be upgraded via VMEBUS CVUpgrade utility program must be used for this purpose The programming file has the extension RBF and its name follows this general scheme v1724 revX Y W Z RBF where e X Y is the major minor revision number of the mainboard FPGA e W Z is major minor revision number of the channel FPGA WARNING you can restore the previous FW revision in case there is a failure when you run the upgrading program There is a jumper on the mainboard that allows to select the backup copy of the firmware You must upgrade all the FPGAs and keep the revisions aligned it is not guaranteed that the latest revision of one FPGA is compatible with an older revision Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 73 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 Upgrade examples 1 Upgrade to Rev 1 0 main FPGA Rev 0 2 channel FPGA of the standard page of the V1724 CVUpgrade v1724 1 0 0 2 0 32100000 standard 2 Upgrade to Rev 1 0 main FPGA Rev 0 2 channel FPGA of the backup page of the V1724 CVUpgrade v1724 1 0 0 2 rbf 32100000 backup 3 Upgrade to Rev 1 0 main FPGA Rev 1 1 channel FPGA of the standard page of the V1724 CVUpgrade 1724 1 0 1 1 rbf 32100000 standard NPO File
89. th samples over threshold Skip Ns N B In this case there are two subsequent GOOD intervals These examples are reported with positive logic the compression algorithm is the same also working in negative logic NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 37 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 3 5 Trigger management All the channels in a board share the same trigger this means that all the channels store an event at the same time and in the same way same number of samples and same position with respect to the trigger several trigger sources are available Mother Board Mezzanines Memory Buffers TRG OUT TRG IN TRIGGER sition M Enable Mask VME Local Bus Interface Interface Fig 3 17 Block diagram of Trigger management 3 9 1 External trigger External trigger can be NIM TTL signal on LEMO front panel connector 50 Ohm impedance The external trigger is synchronised with the internal clock see S 3 2 3 if External trigger is not synchronised with the internal clock a one clock period jitter Occurs 3 5 2 Software trigger Software trigger are generated via VME bus write access in the relevant register see 4 21 3 5 3 Local channel auto trigger Each cha
90. ther ones will be aligned to it If a precise temporal relationship between trigger and samples is required such as repeated acquisitions where a jitter on the position of the signal in the acquisition window is a major issue it is suggested to use one input channel among all the V1724s in the chain to sample the trigger signal itself this will allow to reconstruct off line the trigger edge position in the acquisition window with a resolution smaller than the sampling period through interpolation Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 24 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 3 3 Acquisition Modes 3 3 1 Acquisition run stop The acquisition can be started in two ways according to Acquisition Control register Bits 1 0 setting see 4 17 setting the RUN STOP bit bit 2 in the Acquisition Control register bits 1 0 of Acquisition Control must be set to REGISTER CONTROLLED RUN MODE or S IN CONTROLLED RUN MODE driving S IN signal high bits 1 0 of Acquisition Control must be set to 01 Subsequentially acquisition is stopped either resetting the RUN STOP bit bit 2 in the Acquisition Control register bits 1 0 of Acquisition Control must be set to REGISTER CONTROLLED RUN MODE or S IN CONTROLLED RUN MODE A driving S IN signal low bits 1 0 of Acquisition Contr
91. tors on the board side the simplex connector with the black wrap is for the RX line lower and the one with the red wrap is for the TX higher see also S 2 4 5 The Optical Link allows to perform VME read Single data transfer and Block transfers and write Single data transfer operations See also the web page http www caen it nuclear product php mod A2818 The parameters for read write accesses via optical link are the same used by VME cycles Address Modifier Base Address data Width etc wrong parameter settings cause Bus Error VME Control Register bit 3 see S 4 36 allows to enable the module to broadcast an interrupt request on the Optical Link an 8 bit mask see S 3 14 12 and S 3 14 13 allows to enable the corresponding A2818 s to propagate the interrupt on the PCI bus as a request from the Optical Link is sensed Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 50 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 VME and Optical Link accesses take place on independent paths and are handled by board internal controller with VME having higher priority anyway it is better to avoid accessing the board via VME and Optical Link simultaneously The following diagram shows how to connect V1724 modules to the Optical Link Link PC side crate side BdNum T 0 ES V17XX 0 RX 0 1 1 N Fig 3 31 Optical
92. transfer in bytes in AM The address modifier out count The number of bytes transferred Returns An error code about the execution of the function Description The function performs a VME multiplexed block transfer read cycle CAENVME API NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 54 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 CAENVME MBLTReadCycle long Handle unsigned long Address unsigned char Buffer int Size CVAddressModifier AM int count 3 14 10 CAENVME FIFOMBL TReadCycle Parameters Handle The handle that identifies the device Address The VME bus address out Buffer The data read from the VME bus in Size The size of the transfer in bytes in AM The address modifier out count The number of bytes transferred Returns An error code about the execution of the function Description The function performs a VME multiplexed block transfer read cycle The Address is not incremented on the VMEBus during the cycle CAENVME API CAENVME FIFOMBLTReadCycle int32 t Handle uint32 t Address void Buffer int Size CVAddressModifier AM int count 3 14 11 CAENVME_IRQCheck Parameters in Handle The handle that identifies the device out Mask A bit mask indicating the active IRQ lines Returns An error code about the executi
93. uration as summarised by the following table Table 1 1 Mod V1724 versions Model Inputtype Memory Optical link AMC FPGA Form factor MAPME Single ended_ 4 Msamples ch_ Yes EPIGU 6U VME64 V1724F 4 EP1C20 6U VME64 ira Single ended 512 Ksamples ch ves GU MEG4X 17248 Singleended 4Msamples ch EP1C4 6U VME64x VX1724C Differential _ 512 Ksamples ch 1 4 6U VME64x VX1724D Differential _ 4Msamples ch EP1C4 6U VME64X 4 Msamples ch AMC ADC e Memory controller FPGA Models available ALTERA Cyclone 1 4 4000 Logic elements or ALTERA Cyclone EP1C20 20000 Logic elements Single ended input versions optionally are available with 10 Vpp dynamic range default range 2 25 Vpp The DC offset of the signal can be adjusted channel per channel by means of a programmable 16bit DAC The board features a front panel clock reference In Out and a PLL for clock synthesis from internal external references This allows multi board phase synchronisations to an external clock source or to a V1724 clock master board The data stream is continuously written in a circular memory buffer when the trigger occurs the FPGA writes further N samples for the post trigger and freezes the buffer that then can be read either via VME or via Optical Link the acquisition can continue without dead time in a ne
94. w buffer Each channel has a SRAM memory divided in buffers of programmable size The trigger signal can be provided via the front panel input as well as via the VMEbus but it can also be generated internally as soon as a programmable voltage threshold is reached The individual Auto Trigger of one channel can be propagated to the other channels and onto the front panel Trigger Output The VME interface is VME64X compliant and the data readout can be performed in NPO Filename Number of pages Page 00103 05 V1724x MUTx 19 V1724_REV19 DOC 74 9 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 25 09 2009 19 Single Data Transfer D32 32 64 bit Block Transfer BLT MBLT 2eVME 2eSST and 32 64 bit Chained Block Transfer CBLT The board houses a daisy chainable Optical Link able to transfer data at 80 MB s thus it is possible to connect up to eight V1724 64 ADC channels to a single Optical Link Controller Mod A2818 see Accessories Controller The V1724 can be controlled and readout through the Optical Link in parallel to the VME interface The Mod V1724LC is also available a simplified version of the Mod V1724 without Optical Link and Analog Monitor features 1 2 Block Diagram FRONT PANEL x8 channels fim gt ____ AMC FPGA ADC 8 ke CONTROLLER BUFFE

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