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VEEK-MT User Manual - Mouser Electronics

1. Video and Embedded Evaluation Kit Multi touch User Manual P e D f ETaASIC www terasic com Copyright O 2003 2011 Terasic Technologies Inc All Rights Reserved CONTENTS ESSE CHAPTER 1 INTRODUCTION OF THE VEEK MT nina nnnnnnnnnnnnnnn nenen 1 DU POO NG Ka 5 1 2 Setup License for Terasic Multi touch IP 6 Ac ee na 1 CHAPTER 2 ARE PO aa ati 8 ZN Layout AGC ompole A E E E AE E EE EE ES E AE E aeons 8 2 2 Block Diagram ot the V BEK NT M hoon sense katun sana sos nenas mai 9 CHAPTER 3 USING VEIT acerca aa na aa 10 5 Omnis Grime the Cyclone IY B ERA css ccoo cocineta ios EINTE i 10 AA MPAA mE 13 2 9 Using the 7 LCD Capacitive TOUCH Screen eene sooo o rape o Eb sanusebededscudesannseebesnaedoeaunecbebbddvedesensactesadesederass 14 24 Using gt megapixel Disital Image SENSOR mba san sd ban asem Ba esa ana sasa 16 33 Using tbe Dia Accelerometer Te 17 3 6 Using the Ambient Light SENSOT ssscsssaiaancecanacesscosedasssnnsannataiaancececacnes sada 0 0 89 49 060 592298 6 00000950 08900 949 0060 1080 17 STE sao Terasic Moe IP EE OT TETUER 18 CHAPTER 4 VEEK MI DEMONSTRATIONS woo oie quaa ta ecce aos ua Re Pork at ceu u Dua ona s 20 ANS rod Ke An Aa TNT 20 AA TAC tOry AAA e ET DOO T 20 2 3 Pater Ae MAO MSU Oon aon oem aon PPP A aa O nenas kam Das Ema e ede 21 AA UCU ee E 25 4 5 Video and Image BOSS Ua nanas adu s
2. Mersion _ Change Log V1 0 Initial Version Preliminary 6 2 Copyright Statement Copyright 2011 Terasic Technologies All rights reserved Tiasic Terasic VEEK MT User Manual 45 www terasic com
3. file together by executing the instructions below e Copy both the Selector sof and Selector elf files into a common directory relying on your choice This directory is where you will convert the files e On your host PC launch a Nios II Command Shell from Start gt Programs gt Altera gt Nios II version 5 EDS gt Nios II Command Shell e From the command shell navigate to where your SOF file is located and create your hardware binary file using the following command commands listed below Terasic VEEK MT User Manual 42 www terasic com rasic com Convert Selector sof file into Selector_HW flash file sof2flash epcs input Selector sof output Selector HW flash Convert flash file into bin file nios2 elf objcopy I srec O binary Selector_HW flash Selector_HW bin From the command shell navigate to where your ELF file is located and create your software bin image using the following command commands listed below Convert Selector elf into Selector SW flash elf2flash epcs after Selector_HW flash input Selector elf output Selector SW flash Convert Selector SW flash into Selector _SW bin nios2 elf objcopy I srec O binary Selector_SW flash Selector_SW bin Combine Selector_HW bin and Selector_SW bin using the following command cat Selector HW bin Selector_SW bin gt Selector bin The generated Selector bin is our target binary file Restoring the original binary file To restore the original contents
4. section 3 7 Using Terasic Multi Touch IP in this document Terasic VEEK MT User Manual 21 www terasic com www teresic com L id Jv s a zn T Js hi Avalon Interconnect Fabric y gt MXO gt gt o gt AAAAAAxxAA gt gt gt gt gt gt gt gt gt gt gt HHXXk gt gt Avalon Memory Mapped Bus Avalon Streaming Bus Figure 4 2 Block Diagram of the Painter Demonstration Demonstration Source Code Project directory Painter Bit stream used Painter sof Nios II Workspace Painter Software B Demonstration Batch File Demo Batch File Folder Painter Memo batch The demo batch file includes the following files Batch File test bat test bashrc FPGA Configuration File Painter sof Nios II Program Painter elf Demonstration Setup Make sure Ouartus II and Nios II are installed on your PC Power on the DE2 115 board Connect USB Blaster to the DE2 115 board and install USB Blaster driver if necessary Execute the demo batch file test bat under the batch file folder Painter Nemo batch After Nios II program is downloaded and executed successtully you will see a painter GUI in the LCD Figure 4 3 shows the GUI of the Painter Demo e The GUI is classified into three areas Palette Canvas and Gesture Users can select pen color from the color palette and start painting in the Canvas area If gesture is detected the associated gesture symbol is shown in the gesture area To clear canvas content press the Clear
5. 13 www terasic com www terasic com 3 3 Using the 7 LCD Capacitive Touch Screen The VEEK MT features a 7 inch capacitive amorphous TFI LCD panel The LCD touch screen offers resolution of 800x480 to provide users the best display guality for developing applications The LCD panel supports 24 bit parallel RGB data interface The VEEK MT is also equipped with a Touch controller which can read the coordinates of the touch points through a serial port interface To display images on the LCD panel correctly the RGB color data along with the data enable and clock signals must act according to the timing specification of the LCD touch panel as shown in Table 3 1 Table 3 2 gives the pin assignment information of the LCD touch panel Table 3 1 LCD timing specifications ITEM SYMBOL MIN TYP MAX UNIT NOTE Dot Clock 1 tCLK 33 MHZ DCLK DCLK pulse duty Tcwh 40 50 60 Setup time Tesu ns Hold time Tehd ns Horizontal period tH 1056 tCLK Horizontal Valid tHA 800 tCLK Horizontal Blank tHB 256 tCLK Vertical Period tV 525 tH Vertical Valid tVA 480 tH DE Vertical Blank tVB 45 tH SYNC HSYNC setup time Thst 8 ns HSYNC hold time Thhd 8 ns VSYNC Setup Time Tvst 8 ns VSYNC Hold Time Tvhd 8 ns Horizontal Period th 1056 tCLK Horizontal Pulse Width thpw 30 tCLK thb thpw 46DCLK Horizontal Back Porch thb 16 tCLK is fixed Horizontal Front Porch thfp 210 tCLK Horizontal Valid thd 800 tCLK Vertical Period tv 525 th Vertical Pulse Width tvpw 13 th tv
6. Interrupt 1 output 2 5V GSENSOR INT2 G28 Interrupt 2 output 2 5V GSENSOR CS n F28 Chip Select 2 5V GSENSOR ALT ADDR K27 I2C Address Select 2 5V GSENSOR SDA SDI SDIO K28 Serial Data 2 5V GSENSOR SCL SCLK M27 Serial Communications Clock 2 5V 3 6 Using the Ambient Light Sensor The APDS 9300 is a low voltage digital ambient light sensor that converts light intensity to digital signal output capable of direct I2C communication Each device consists of one broadband photodiode visible plus infrared and one infrared photodiode Two integrating ADCs convert the photodiode currents to a digital output that represents the irradiance measured on each channel This digital output can be input to a microprocessor where illuminance ambient light level in lux is derived using an empirical formula to approximate the human eye response For more detailed information of better using this chip please refer to its datasheet which is available on manufacturer s website or under the datasheet folder of the system CD Table 3 5 Pin names and Descriptions of Ambient Light Sensor Module Signal Name FPGA Pin No Description VO Standard LSENSOR_ADDR_SEL J25 Chip select 2 5V LSENSOR_INT L28 Interrupt output 2 5V LSENSOR_SCL J26 Serial Communications Clock 2 5V LSENSOR_SDA L27 Serial Data 2 5V Terasic VEEK MT User Manual 17 www terasic com rasic com 3 7 Using Terasic Multi Touch IP Terasic Multi Touch IP is provided for developers to retrieve user inputs
7. of the Application Selector perform the following steps e Copy Selector project into a local directory of your choice The Selector project is placed in Demonstrations Selector Power on the VEEK MT with the USB cable connected to the USB Blaster port Download the Selector sof to the board by using either JTAG or AS programming Run the Nios II and choose Selector Software as the workspace Choose Tools gt Flash Programmer to open the flash programmer Choose Program a file into memory choose your Selector bin file See Figure 5 2 Click Program Flash to start program Selector bin to EPCS in the board When the programming finishes power on again O You can also use Selector_batch to generate selector bin and restore the original binary file by executing the Selector bat under the Factory Recovery Selector batch folder Terasic VEEK MT User Manual 43 www terasic com rasic com Flash Programmer Program project to flash memory on target board Program flash with Selector bin using script D CD Demonstrations Selector Software Selector Debug flash programmer sh zu flash programmer type filter text TS E Main W gs Flash Programmer arget Hardware D ACDDenonstrationsiSelectorWDE2_115_SOPC ptf v E E epcs flash controller Y E Figure 5 2 Programming Flash settings TagasiC Terasic VEEK MT User Manual 44 www terasic com www teresic com Chapter 6 Appendix 6 1 Revision History
8. stream file with the pof filename extension e Once the programming operation is finished set the RUN PROG slide switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCS64 device to be loaded into the FPGA chip Terasic VEEK MT User Manual 12 www terasic com rasic com NOTE RA USB Blaster Circuit Quartus II FRONSISUN AS Mode Auto Power on NRhre BYA Programmer MAX Il Config Config an EPM 240 Q ai QUARTUS II PROG Figure 3 5 The AS Configuration Scheme 3 2 Bus Controller The VEEK MT comes with a bus controller using the Max II EPM240 that allows user to access the touch screen module through the HSMC connector This section describes its structure in block diagram form and its capabilities B Bus Controller Introduction The bus controller provides level shifting functionality from 2 5V HSMC to 3 3V domains B Block Diagram of the Bus Controller Figure 3 6 gives the block diagram of the connection setup from the HSMC connector to the bus controller on the Max II EPM240 to the touch screen module To provide maximum flexibility for the user all connections are established through the HSMC connector Thus the user can configure the Cyclone IV E FPGA on the VEEK MT to implement any system design LCD ouch 5 5V 3 3 TUN n 2 5V 3 3V EPM240 Terasic VEEK MT User Manual
9. Bayer pattern Shutter type Global reset release GRR Maximum data rate master clock 96Mp s at 96MHz Framerate Full resolution Programmable up to 15 fps VGA mode Programmable up to 70 fps ADC resolution 12 bit Responsivity 1 4V lux sec 550nm Terasic VEEK MT User Manual 4 www terasic com rasic com Pixel dynamic range SNRMAX Power Supply Voltage pply g O B Digital Accelerometer e Upto 13 bit resolution at 16g e SPI 3 and 4 wire digital interface e Flexible interrupts modes B Ambient Light Sensor Approximates human eye response 50 60 Hz lighting ripple rejection 70 1dB 38 1dB 3 3V 1 7V 3 1V Precise luminance measurement under diverse lighting conditions Programmable interrupt function with user defined upper and lower threshold settings 16 bit digital output with IC fast mode at 400 kHz Programmable analog gain and integration time O for more detailed information of the LCD touch panel and CMOS sensor module please refer to their datasheets respectively 1 1 About the Kit The kit includes everything users need to run the demonstrations and develop custom designs as shown in Figure 1 2 The system CD contains technical documents of the VEEK MT which includes component datasheets demonstrations schematic and user manual Terasic VEEK MT User Manual rasic com www terasic com Video and Embedded Evaluation Kit Multi touch VEEK MT Type A B USB Cable Pow
10. Configuring the FPGA in JTAG Mode Figure 3 3 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone IV E FPGA perform the following steps e Ensure that power is applied to the VEEK MT e Configure the JTAG programming circuit by setting the RUN PROG slide switch SW19 to the RUN position See Figure 3 4 e Connect the supplied USB cable to the USB Blaster port on the VEEK MT e The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename extension Terasic VEEK MT User Manual 11 www terasic com www terasic com USB Blaster Circuit PROG RUN Quartus II amp Programmer MAX II JTAG UART MNOTSRYA s Q EPM 240 EAE EEEE QUART S II 1 are Signals Cyclone IV RUN Figure 3 3 JTAG Chain Configuration Scheme SW19 Figure 3 4 The RUN PROG Switch SW19 Set to JTAG Mode B Configuring the EPCS64 in AS Mode Figure 3 5 illustrates the AS configuration set up To download a configuration bit stream into the EPCS64 serial configuration device perform the following steps e Ensure that power is applied to the VEEK MT e Connect the supplied USB cable to the USB Blaster port on the VEEK MT e Configure the JTAG programming circuit by setting the RUN PROG slide switch SW19 to the PROG position e The EPCS64 chip can now be programmed by using the Quartus II Programmer module to select a configuration bit
11. EK MT User Manual 7 www terasic com www teresic com Chapter 2 Architecture This chapter describes the architecture of the Video and Embedded Evaluation Kit Multi touch VEEK MT including block diagram and components 2 1 Layout and Components The picture of the VEEK MT is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the locations of the connectors and key components 5 Megapixel Digital Camera Ambient Light Sensor 7 LCD Touch Panel ferasIC Figure 2 1 VEEK MT PCB and Component Diagram Top Terasic VEEK MT User Manual 8 www terasic com www teresic com TV Decoder NTSC PAL Ethemet Audio 28MHZ 10 100 1000M CODEC Port1 USB Oscillator USB Device Ethernet Blaster Fort USB Mic LineLine Video VGA 10 100 1000M RS 232 Host In In Out In Out Porto Part yo 0 Ba 12V DC Power Supply Connector M om m ie Power ON OFF Switch ume c s EN E d NL Es J 3 T ds MI 9 ia Altera USB Blaster Controller chipset es al c em i E AA ET dm 3 x YA USB Host Slave Controller Altera EPCS64 Configuration Device LCD 16x2 Module T segment Displays Programming Mode Switch 18 Slide Switches 18 Red LEDs 4Push buttons 8 i n LEDs Figure 2 2 VEEK MT PCB and Component Diagram Bottom 2 2 Block Diagram of the VEEK MT PS 2 Port Triple 8 bit VGA DAC Digital Accelerometer Gigabit Ethernet PHY Expansion Header with Protection Diodes Alte
12. KEY 0 after toggle SW 17 Q Note execute the test bat under Camera demo_batch will automatically download the sof file Table 4 2 summarizes the functional keys of the digital camera Figure 4 13 gives a run time photograph of the demonstration Table 4 2 The functional keys of the digital camera demonstration Component Function Description KEY 0 Reset circuit KEY 1 Set the new exposure time use with SW 0 KEY 2 Trigger the Image Capture take a shot KEY 3 Switch to Free Run mode SWI O Off Extend the exposure time Terasic VEEK MT User Manual 32 www terasic com rasic com NOTE RA On Shorten the exposure time SW 17 Mirror mode HEX 7 0 Frame counter Display ONLY Figure 4 13 Screen Shot of the Camera Demonstration 4 7 Video and Image Processing for Camera The Video and Image Processing VIP for Camera Example Design demonstrates dynamic scaling and clipping of a standard definition video stream in RGB format and picture in picture mixing with a background layer The video stream 1s output in high resolution 800x480 on LCD touch panel The example design demonstrates a framework for rapid development of video and image processing systems using the parameterizable MegaCore functions that are available in the Video and Image Processing Suite Available functions are listed in Table 4 2 This demonstration needs the Quartus II license file includes the VIP suite feature These fu
13. Period Suppression Host ID Type MIC ID Colors Host ID Value 0018f3ca7326 Wait for floating licenses Fonts Figure 1 3 License Setup The second way is to add license content to the existing license file The procedures are listed below Use Notepad or other text editing software to open the file license multi touch dat 1 The license contains the FEATURE lines required to license the IP Cores as shown in Figure 1 4 Terasic VEEK MT User Manual 6 www terasic com www terasic com license multi touch dat 10 2l 30 40 SU 6 0 0 1 FEATURE 535 0018 alterad 9999 12 12 jan 9999 uncounted 3F150Z2F111E 4 VENDOR STRIHG I14zczkz9 gj hoTVOtLcnySBti hPsnSaeyvATvaocaV50sL3wvQOdqoclDdcIz HOSTID ANY TS OK SIGN 1177 8185 SDAS 4068 5033 BEST 2139 77DS c55 3B4B 6582 721C 9B62 CD64 1358 0519 40Cz2 1508 B6C8 CASE 1 zZ 3 4 5 E549 C994 C296 DGFD E937 SADE 5505 5952 EDCF 0843 Figure 1 4 Content of license_multi_touch dat 2 Open your Quartus II license dat file in a text editor 3 Copy everything under license_multi_touch dat and paste it at the end of your Quartus II license file Note Do not delete any FEATURE lines from the Quartus II license file Doing so will result in an unusable license file 4 Save the Quartus II license file 1 3 Getting Help Here is information of how to get help if you encounter any problem e Terasic Technologies Tel 886 3 550 8800 e Email support terasic com Terasic VE
14. SD card socket of VEEK MT Switch on the power SW18 1 Scroll to select the demonstration to load using the side bar Tap on the Load button to load and run a demonstration 2 Q Note 1 If the board is already powered the application selector will boot from EPCS and a splash screen will appear while the application selector searches for applications on the SD card 2 The application will begin loading and a window will be displayed showing the progress Loading will take between 2 and 30 seconds depending on the size of the application 5 3 Application Selector Details This section describes some details about the operation of the application selector utility SD Card The Application Selector uses an SD card for storing applications The SD card must be formatted with the FAT 16 file system and can be any capacity up to 2GB Long file names are supported The Nios II CPU access the SD card through an SD card SPI controller Application Files Each loadable application consists of two binary files all stored on the SD card The first binary file represents the software portion of the example and must be derived from an ELF file as described in the section of this document titled Creating Your Own Loadable Applications This binary file can be named anything supported by the FAT16 file system the only restriction being that the name must end with SW bin The second binary file represents the hardware portion of the example a
15. Y axis or from 10 to 80 and from 80 to 10 in Y axis the image will invert Figure 4 17 shows the demonstration in action YadasiC Terasic VEEK MT User Manual 37 www terasic com Figure 4 17 Digital Accelerometer Demonstration Q Note Execute G sensor demo_batch test bat to download sof and elf files Terasic VEEK MT User Manual 38 www terasic com www terasic com Chapter 5 Application Selector The application selector utility is the default code that powers on the FPGA and offers a graphical interface on the LCD allowing users to select and run different demonstrations that reside on an SD card 5 1 Ready to Run SD Card Demos You can find several ready to run SD card demos in your SD card root directory as well as in the System CD under Factory_Recovery Application_Selector folder Figure 5 1 shows the photograph of the application selector main interface Figure 5 1 Application selector main interface Also you can easily convert your own applications to be loadable by the application selector For more information see Creating Your Own Loadable Applications in section 5 3 If you have lost the contained files in the SD card you could find them on the VEEK MT System CD under the Factory_Recovery folder Terasic VEEK MT User Manual 39 www terasic com www terasic com 5 2 Running the Application Selector Connect power to the VEEK MT Insert the SD card with applications into the
16. ames into external RAM This core supports double or triple buffering with a range of options for frame dropping and repeating 2D Median Filter Provides a way to apply 3 x 3 5 x 5 or 7 x 7 pixel median filters to video images Gamma Corrector Allows video streams to be corrected for the physical properties of display devices Clocked Video These two cores convert the industry standard clocked video format BT 656 to Input Output Avalon ST video and vice versa These functions allow you to fully integrate common video functions with video interfaces processors and external memory controllers The example design uses an Altera Cyclone IV E EP4CE115F29 featured VEEK MT Terasic VEEK MT User Manual 27 www terasic com rasic com A video source is input through an analog composite port on VEEK MT which generates a digital output in ITU BT656 format A number of common video functions are performed on this input stream in the FPGA These functions include clipping chroma resampling motion adaptive deinterlacing color space conversion picture in picture mixing and polyphase scaling The input and output video interfaces on the VEEK MT are configured and initialized by software running on a Nios II processor Nios II software demonstrates how to control the clocked video input clocked video output and mixer functions at run time is also provided The video system is implemented using the SOPC Builder system level design tool This abst
17. and outputs it as a stream Control Synchronizes the changes made to the video stream in real time between two Synchronizer functions Switch Allows video streams to be switched in real time Color Space Converts image data between a variety of different color spaces such as RGB to Converter YCrCb Chroma Resampler Changes the sampling rate of the chroma data for image frames for example from 4 2 2 to 4 4 4 or 4 2 2 to 4 2 0 2D FIR Filter Implements a 3 x 3 5 x 5 or 7 x 7 finite impulse response FIR filter on an image data stream to smooth or sharpen images Alpha Blending Mixes and blends multiple image streams useful for implementing text overlay Mixer and picture in picture mixing Scaler A sophisticated polyphase scaler that allows custom scaling and real time updates of both the image sizes and the scaling coefficients Deinterlacer Converts interlaced video formats to progressive video format using a motion adaptive deinterlacing algorithm Also supports bob and weave algorithms Test Pattern Generates a video stream that contains still color bars for use as a test pattern Generator Clipper Provides a way to clip video streams and can be configured at compile time or at run time Color Plane Changes how color plane samples are transmitted across the Avalon ST Sequencer interface This function can be used to split and join video streams giving control over the routing of color plane samples Frame Buffer Buffers video fr
18. button pae LEE Terasic VEEK MT User Manual 22 www terasic com www terasic com JAN DTE R A Figure 4 4 shows the photo when users paint in the canvas area Figure 4 5 shows the phone when counter clockwise rotation gesture is detected Figure 4 6 shows the photo when zoom in gesture is detected Figure 4 3 GUI of Painter Demo Terasic Multi Touch Figure 4 4 Single Touch Painting Terasic VEEK MT User Manual 23 www terasic com rasic com Figure 4 5 Counter clockwise Rotation Gesture Figure 4 6 Zoom in Gesture Q Note execute the test bat under Picture ViewerMemo batch will automatically download the sof and elf file Terasic VEEK MT User Manual 24 www terasic com rasic com 4 4 Picture Viewer This demonstration shows a simple picture viewer implementation using Nios Il based SOPC system It reads JPEG images stored on the SD card and displays them on the LCD The Nios II CPU decodes the images and fills the raw result data into frame buffers in SDRAM The VEEK MT will show the image the buffer being displayed points to When users touch the LCD touch panel it will proceed to display the next buffered image or last buffered image Figure 4 7 shows the block diagram of this demonstration The Nios II CPU here takes a key role in the demonstration It is responsible of decoding the JPEG images and coordinates the works of all the peripherals The touch panel handling program uses the timer as a re
19. ch IP Pin Name Direction Description iCLK Input Connect to 50MHz Clock iRSTN Input Connect to system reset signal TRIG Input Connect to Interrupt Pin of Touch IC oREADY Output Rising Trigger when following six output data is valid oREG X1 Output 10 bits X coordinate of first touch point oREG Y1 Output 9 bits Y coordinate of first touch point oREG X2 Output 10 bits X coordinate of second touch point Terasic VEEK MT User Manual 18 www terasic com rasic com oREG Y2 Output 9 bits Y coordinate of second touch point oREG TOUCH COUNT Output 2 bits touch count Valid value is 0 1 or 2 oREG GESTURE Output 8 bits gesture ID See Table 3 7 I2C SCLK Output Connect to I2C Clock Pin of Touch IC l2C SDAT Inout Connect to I2C Data Pin of Touch IC The supported gestures and IDs are shown in Table 3 7 Table 3 7 Gestures Gesture ID hex One Point Gesture North 0x10 North East 0x12 East 0x14 South East 0x16 South 0x18 South West 0x1A West 0x1C North West Ox1E Rotate Clockwise 0x28 Rotate Anti clockwise 0x29 Click 0x20 Double Click 0x22 Two Point Gesture North 0x30 North East 0x32 East 0x34 South East 0x36 South 0x38 South West 0x3A West 0x3C North West 0x3E Click 0x40 Zoom In 0x48 Zoom Out 0x49 Note The Terasic Multi Touch IP can also be found under the MP folder in the system CD as well as the MP folder in the reference designs Terasic VEEK MT User Manual 19 www terasic com rasic com Chapter 4 VEEK MI D
20. configuration as long as power is applied to the board the configuration information will be lost when the power is turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera EPCS64 serial configuration device It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the VEEK MT is turned off When the board s power is turned on the configuration data in the EPCS64 device is automatically loaded into the Cyclone IV E FPGA W JTAG Chain on VEEK MT To use the JTAG interface for configuring FPGA device the JTAG chain on the VEEK MT must form a closed loop that allows Quartus II programmer to detect the FPGA device Figure 3 1 illustrates the JTAG chain on the VEEK MT Shorting pinl and pin2 on JP3 can disable the JTAG signals on the HSMC connector that will form a close JTAG loopback on DE2 115 See Figure 3 2 Thus only the on board FPGA device Cyclone IV E will be detected by Quartus I programmer By default a jumper is placed on pin and pin2 of JP3 To prevent any changes to the bus controller Max II EPM240 described in later sections users should not adjust the jumper on JP3 Terasic VEEK MT User Manual 10 www terasic com rasic com ANU S RYAN USB Embedded Blaster Connector L TDI iaj USB TDO Figure 31 JTAG Chain JP3 Figure 3 2 JTAG Chain Configuration Header B
21. configures the FPGA with your selection For more comprehensive information of the application selector factory configuration please refer to chapter 5 Terasic VEEK MT User Manual 20 www terasic com rasic com Altera DE2 115 Application Selector E Pic_View y a 2 DE2_115_TV dam 3 DE2 115 SD Card Audio t 4 4 DE2 115 PIO EN 5 DE2 115 LED A O A AA Figure 4 1 Application Selector Interface Q Note Please insert the supplied SD card from this demonstration 4 3 Painter Demonstration This chapter shows how to control LCD and touch controller to establish a paint demo based on SOPC Builder and Altera VIP Suite The demonstration shows how multi touch gestures and single touch coordinates operate Figure 4 2 shows the hardware system block diagram of this demonstration For LCD display processing the reference design is developed based on the Altera Video and Image Processing Suite VIP The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is filled by NIOS II processor according to users input For multi touch processing a Terasic Memory Mapped IP is used to retrieve the user input including multi touch gesture and single touch coordinates Note the IP is encrypted so the license should be installed before compiling the Quartus II project For IP usage details please refer to the
22. el data bit 2 C27 Pixel data bit 3 F26 Pixel data bit 4 E26 Pixel data bit 5 G25 Pixel data bit 6 G26 Pixel data bit 7 H25 Pixel data bit 8 H26 Pixel data bit 9 K25 Pixel data bit 10 K26 Pixel data bit 11 E27 Snapshot strobe D28 Line valid D27 Frame valid F27 Image sensor reset AE26 Serial clock E28 Snapshot trigger AE27 Serial data G23 External input clock Terasic VEEK MT User Manual 16 rasic com O Standard 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V www terasic com 3 5 Using the Digital Accelerometer The VEEK MT is equipped with a digital accelerometer sensor module The ADXL345 is a small thin ultralow power assumption 3 axis accelerometer with high resolution measurement Digitalized output is formatted as 16 bit twos complement and can be accessed either using SPI interface or I2C interface This chip uses the 3 3V CMOS signaling standard Main applications include medical instrumentation industrial instrumentation personal electronic aid and hard disk drive protection etc Some of the key features of this device are listed below For more detailed information of better using this chip please refer to its datasheet which is available on manufacturer s website or under the datasheet folder of the system CD Table 3 4 Pin Names and Descriptions of the GSENSOR Module Signal Name FPGA Pin No Description VO Standard GSENSOR_INT1 G27
23. emonstrations This chapter gives detailed description of the provided bundles of exclusive demonstrations implemented on VEEK MT These demonstrations are particularly designed or ported for VEEK MT with the goal of showing the potential capabilities of the kit and showcase the unigue benefits of FPGA based SOPC systems such as reducing BOM costs by integrating powerful graphics and video processing circuits within the FPGA 4 1 System Requirements To run and recompile the demonstrations you should Install Altera Quartus II 11 0 and NIOS II EDS 11 0 or later edition on the host computer Install the USB Blaster driver software You can find instructions in the tutorial Getting Started with Altera s DE2 115 Board tut initialDE2 115 pdf which is available on the DE2 115 system CD e Copy the entire demonstrations folder from the VEEK MT system CD to your host computer 4 2 Factory Configuration The VEEK MT development kit comes preconfigured with a default utility that boots up on power on and allows users to quickly select load and run different Ready to Run demonstrations stored on an SD card using the VEEK MT touch panel Figure 4 1 gives a snapshot of the default application selector interface Note Every demonstration consists of an FPGA hardware image and an application software image When you select a demonstration the application selector copies the hardware image to EPCS device and software image to flash memory and re
24. er Supply MTLC Quick Start Guide E O Altera Complete Design Suite DVD for Windows Q VEEK MT System CD SN Remote Controller or 2GB SD Card 11 Two Wire Strips black and red Es USB to SD Card Adapter Two 1 pin Headers Figure 1 2 VEEK MT kit package contents 1 2 Setup License for Terasic Multi Touch IP To utilize the multi touch panel in a Quartus II project the Terasic Multi Touch IP is required for operation Error messages will be displayed 1f the license file for the Multi Touch IP is not added before compiling projects The license file is located at VEEK MT System CDNLicenseMicense multi touch dat There are two ways to install the license The first one is to add the license file license multi touch dat to the License file listed in Quartus II as shown in Figure 1 3 In order to reach this window please navigate through to Quartus II gt Tools gt License Setup amp Options General License Setup EDA Tool Options Fonts L file 168 1 58 C dues muli torch Headers amp Footers Settings ea ee 118002192 168 1 56 Crlaltera111 0Vicense multi touch dat Internet Connectivity C Use LM LICENSE FILE variable Libraries EL SEGEUID Current license Preferred Text Editor Web License Update H Processing License Type Full Version Tooltip Settings e STELLE GI Messages Subscription Expiration 2012 01 Begin 30 day Grace
25. f the VEEK MT to a VGA monitor both LCD and CRT type of monitors should work Load the bit stream into FPGA note Run the Nios II IDE and choose VIP Software as the workspace Click on the Run button note e Press the screen of the VEEK MT and drag the video frame box will result in scaling the playing window to any size as shown in Figure 4 10 Q Note 1 Executing VIP demo_batch VIP bat will download sof and elf files 2 You may need additional Altera VIP suite Megacore license features to recompile the project Figure 4 11 illustrates the setup for this demonstration Terasic VEEK MT User Manual 29 www terasic com rasic com 12 02 53 uL Figure 4 10 VIP Demonstration Video In CVBS Output AW imp mar Vo E 3 d DVD Player PLATE ERA HAHA JAQ0DD0000 Figure 4 11 Setup for the VIP Demonstration 4 6 Camera Application This demonstration shows a digital camera reference design using the 5 megapixel CMOS sensor and 7 inch LCD modules on the VEEK MT The CMOS sensor module sends the raw image data to FPGA on the DE2 115 board the FPGA on the board handles image processing part and converts the data to RGB format to display on the LCD module The I2C Sensor Configuration module is used to configure the CMOS sensor module Figure 4 12 shows the block diagram of the demonstration Terasic VEEK MT User Manual 30 www terasic com www teresic com NOTE RA As soon as the configurat
26. ge Processing Suite functions using the Avalon ST Video protocol which facilitates building run time controllable systems and error recovery For the objective of a better visual effect the CMOS sensor is configured to enable the left right mirror mode User could disable this functionality by modifying the related register value being written to CMOS controller chip Figure 4 14 shows the Video and Image Processing block diagram SOPC y N A gt _LOMS Cameras ab Frame Butter Nios Il processor E s EM SDRAM 91184 YSJIMS sng wasis IqeJ yams sng wajs s Alpha Blending Mixer Figure 4 14 VIP Camera Example SOPC Block Diagram Key Components Terasic VEEK MT User Manual 34 www terasic com www terasic com Demonstration Source Code Project directory VIP Camera Bit stream used VIP Camera sof Nios II Workspace VIP Camera Software B Demonstration Batch File Demo Batch File Folder VIP CameraMemo batch The demo batch file includes the following files e Batch File VIP Camera bat VIP Camera bashrc FPGA Configuration File VIP Camera sof Nios II Program VIP Camera elf B Demonstration Setup e Connect the VGA output of the VEEK MT to a VGA monitor both LCD and CRT type of monitors should work e Load the bit stream into FPGA note e Run the Nios II and choose VIP Camera WSoftware as the workspace Click on the Run button note e The sys
27. gular interrupter and periodically updates the sampled coordinates FPG D 50MHz Socket 91 q8 4 j2euuooJeju uiejes s Figure 4 7 Block Diagram of the Picture Viewer Demonstration Demonstration Source Code Project directory Picture Viewer Bit stream used Picture Viewer sof Nios II Workspace Picture ViewerNSoftware B Demonstration Batch File Demo Batch File Folder Picture Viewerdemo batch The demo batch file includes the following files Batch File Picture Viewer bat Picture Viewer bashrc FPGA Configuration File Picture Viewer sof e Nios II Program Picture Viewer elf Terasic VEEK MT User Manual 25 www terasic com www terasic com Mn E S NOTE RA Demonstration Setup Format your SD card into FAT16 format Place the jpg image files to the jpg subdirectory of the SD card For best display result the image should have a resolution of 800x480 or the multiple of that Insert the SD card to the SD card slot on the VEEK MT Load the bit stream into the FPGA on the VEEK MT Run the Nios II Software under the workspace Picture_Viewer Software Note After loading the application you will see a slide show of pictures on the SD card The next image will be displayed after the delay period You can control the slide show as follows Press Forward 6j to advance Reverse 3 to go back to previous image Play Stop deh to play the slide or stop it On the top corner you will see the delay
28. i an otot e On hasasncacaenon csacenstooosgiedy 27 AO Camera Ap Dl a O ea E E E E 30 4 7 Video ana Image Processing for Camieta oo o oo mo o moms kaan aa kans aan 33 4 8 Digital Accelerometer DemonsttatiOn4 oo oo ooo o o mooomoooosbmusma nenen ana tema 36 CHAPTER 5 AFFLICA TION SELECT OR aa na ai 39 del Ready to Rum SD AE DEMOS mu m TU 39 32 Runing the Application Se lec OE ms aman ama ma bhn maha Kakan aan ANA 40 Terasic VEEK MT User Manual 1 www terasic com rasic com IN DTE RYN 3 Apphication Selector Details A A 40 sie o om bob EEA E E E E E E 42 CHAPTER 6 AFF ENDA OCC PA 45 Os ING VS TO ISCO ooo y PPP o oo net as asah 45 Oy lt ae aa A 45 Terasic VEEK MT User Manual 2 www terasic com www terasic com Chapter 1 Introduction The Video and Embedded Evaluation Kit Multi touch VEEK MT is a comprehensive design environment with everything embedded developers need to create processing based systems VEEK MT delivers an integrated platform that includes hardware design tools intellectual property IP and reference designs for developing embedded software and hardware platform in a wide range of applications The fully integrated kit allows developers to rapidly customize their processor and IP to best suit their specific application The VEEK MT features the DE2 115 development board targeting the Cyclone IV E FPGA as well as a capacitive LCD multimedia color touch panel which natively supports multi touch ge
29. including multi touch gestures and single touch The file name of this IP is i2c_touch_config and it is encrypted To compile projects with the IP users need to install the IP license first For license installation please refer to section 1 2 Setup License for Terasic Multi Touch IP in this document The license file is located at VEEK MT System CD License license_multi_touch dat The IP decodes I2C information and outputs coordinate and gesture information The IP interface is shown below module isc touch config Host Side iCLK LRSTH iTRIG OREG TOUCH COUNT oREG GESTURE 120 Side I2C SCLK 120 SDAT I The signal purpose of the IP is described in Table 3 6 The IP requires a 50MHz signal as a reference clock to the iCLK pin and system reset signal to IRSTN iTRIG I2C SCLK and IC2 SDAT pins should be connected of the TOUCH_INT_n TOUCH_I2C_SCL and TOUCH_I2C_SDA signals in the 2x20 GPIO header respectively When oREADY rises it means there is touch activity and associated information is given in the OREG_X1 OREG_Y1 OREG_X2 oREG Y2 oREG TOUCH COUNT and oREG GESTURE pins For the control application when touch activity occurs it should check whether the value of oREG GESTURE matched a pre defined gesture ID defined in Table 3 7 If it is not a gesture it means a single touch has occurred and the relative X Y coordinates can be derived from oREG X1 and oREG Yl Table 3 6 Interface Definitions of Terasic Multi tou
30. ion code is downloaded into the FPGA the I2C Sensor Configuration block will initial the CMOS sensor via I2C interface The CMOS sensor is configured as follow Row and Column Size 800 480 Exposure time Adjustable Pix clock MCLK 2 25 2 50MHz Readout modes Binning Mirror mode Line mirrored According to the settings we can calculate the CMOS sensor output frame rate is about 44 4 fps After the configuration The CMOS sensor starts to capture and output image data streams the CMOS sensor Capture block extracts the valid pix data streams based on the synchronous signals from the CMOS sensor The data streams are generated in Bayer Color Pattern format So it s then converted to RGB data streams by the RAW2RGB block After that the Multi Port SDRAM Controller acquires and writes the RGB data streams to the SDRAM which performs as a frame buffer The Multi Port SDRAM Controller has two write ports and read ports also with 16 bit data width each The writing clock is the same as CMOS sensor pix clock and the reading clock 1s provided by the LCD Controller which is 33MHz Finally the LCD controller fetches the RGB data from the buffer and displays it on the LCD panel continuously Because the resolution and timing of the LCD is compatible with WVGA 800 480 the LCD controller generates the same timing and the frame rate can achieve about 25 fps For the objective of a better visual effect the CMOS sensor is configured to enable
31. ll as hardware binary files of applications which are being loaded The Application Selector binary file is permanently stored in EPCS device at offset 0x0 Hardware binary files for the applications being loaded get written to EPCS at load time to an offset 0x400000 Creating Your Own Loadable Applications It is easy to convert your own Nios II design into an application which is loadable by the Application Selector utility All you need is a hardware image a SOF file and a software image which runs on that hardware a Nios II ELF file The only restrictions are e The hardware designs must contain a CFI Flash controller 1 e If the SOF file contains a Nios II CPU then its reset address should be set to CFI Flash at offset 0x0 e Before compiling the software make sure you have set your software s program memory text section in Flash memory under the System Library Properties Nios II IDE page or through BSP Editor Nios II SBT for Eclipse utility 2 Once you have your working SOF and ELF file pair perform the following steps to convert them to a loadable application selector compatible application e Copy both the SOF and ELF files into a common directory relying on your choice This directory is where you will convert the files e On your host PC launch a Nios II Command Shell from Start gt Programs gt Altera gt Nios II lt version 5 EDS gt Nios II Command Shell e From the command shell navigate to whe
32. n Film Transistor Liquid Crystal Display module e Module composed of LED backlight e Supports 24 bit parallel RGB interface e Converting the X Y touch coordinates to corresponding digital data via Touch controller Table 1 1 shows the general physical specifications of the touch screen Note Terasic VEEK MT User Manual 3 www terasic com rasic com Table 1 1 General Physical Specifications of the LCD Item Specification Unit LCD size T inch Diagonal Resolution 800 x3 RGB x 480 dot Dot pitch 0 1926 H x0 1790 V mm Active area 154 08 H x 85 92 V mm Module size 164 9 H x 100 0 V x 5 7 D mm Surface treatment Glare Color arrangement RGB stripe Interface Digital B 5 Megapixel Digital Image Sensor Superior low light performance High frame rate Low dark current Global reset release which starts the exposure of all rows simultaneously Bulb exposure mode for arbitrary exposure times Snapshot mode to take frames on demand Horizontal and vertical mirror image Column and row skip modes to reduce image size without reducing field of view Column and row binning modes to improve image quality when resizing Simple two wire serial interface Programmable controls gain frame rate frame size exposure Table 1 2 shows the key parameters of the CMOS sensor Note Table 1 2 Key Performance Parameters of the CMOS sensor Parameter Value Active Pixels 2592Hx1944V Pixel size 2 2umx2 2um Color filter array RGB
33. nctions allow you to fully integrate common video functions with video interfaces processors and external memory controllers The example design uses an Altera Cyclone IV E EP4CE115F29 featured on the VEEK MT A video source 1s input through the CMOS sensor on VEEK MT which generates a digital output in RGB format A number of common video functions are performed on this input stream in the FPGA These functions include clipping chroma resampling motion adaptive deinterlacing color space conversion picture in picture mixing and polyphase scaling The input and output video interfaces on the VEEK MT are configured and initialized by software Terasic VEEK MT User Manual 33 www terasic com rasic com running on a Nios II processor Nios II software demonstrates how to control the clocked video input clocked video output and mixer functions at run time is also provided The video system is implemented using the SOPC Builder system level design tool This abstracted design tool provides an easy path to system integration of the video processing data path with a NTSC or PAL video input VGA output Nios II processor for configuration and control The Video and Image Processing Suite MegaCore functions have common open Avalon ST data interfaces and Avalon Memory Mapped Avalon MM control interfaces to facilitate connection of a chain of video functions and video system modeling In addition video data is transmitted between the Video and Ima
34. nd must be derived from a SOF file as described in the section of this document titled Creating Your Own Loadable Applications This file can be named anything supported by the FAT 16 file system the only restriction being that the name must end with _HW bin SD Card Directory Structure All loadable applications on the SD card must be located in a top level directory named Application Selector Under the Application Selector directory each application is located in its own subdirectory The name of that subdirectory is important because the application selector utility uses that name as the title of the application when displaying it in the main menu The subdirectory names can be anything so long as they adhere to the FAT file system long file name rules Spaces are permitted Terasic VEEK MT User Manual 40 www terasic com rasic com CFI Flash CFI flash is used to store the software binary files of applications All software binary files used by the application selector contain a boot copier which is pre ended by the Nios2 elf objcopy utility during file conversion process described in the Creating Your Own Loadable Applications section The boot copier copies the software code to program memory before running it The Application software binary file is stored in flash at load time to an offset 0x0 EPCS Device EPCS is used to store both the binary file of the Application Selector both hardware and software image itself as we
35. or SDRAM as the program memory you may need to perform two steps to convert your elf file into bin file to make the software properly run on VEEK MT The commands seem to look like this elf2flash basezflash base address end flash end address _ resetzflash base address Input lt your software name gt elf output lt your software name gt flash boot SOPC_KIT_NIOS2 components altera_nios2 boot_loader_cfi srec nios2 elf objcopy I srec O binary your software name gt flash your software name gt _SW bin 3 You may pad a compress option for saving binary image space because the Cyclone IV E series support the decompress feature while loading hardware image from EPCS device 4 The command will use the default HAL boot loader and link it to the text section 5 You can also use the tool bin demo batch to convert your sof and elf to bin Copy your example sof and Your example elf to the bin demo batch folder rename them to test sof test elf execute the test bat then the final test HW bin and test SW bin are your target files 5 4 Restoring the Factory Image This section describes some details about the operation of restoring the Application Selector factory image Combining factory recovery binary files In the factory settings you need to program Application Selector binary files to EPCS Before programming you should combine application selector software binary file and hardware binary
36. period seconds You can increase or decrease the delay period by touching the 8 or E993 buttons The max delay is 120 seconds the min delay is 1 second and the default delay is 10 seconds You can hide the control buttons by clicking on the Hide button located at the top left corner of the touch screen Touch anywhere on the screen to resume and to return to menu Figure 4 8 Picture Viewer Demonstration Q Note execute the Picture Viewer bat under Picture ViewerMemo batch will automatically download the sof and elf file Terasic VEEK MT User Manual 26 www terasic com www terasic com 4 5 Video and Image Processing The Video and Image Processing VIP Example Design demonstrates dynamic scaling and clipping of a standard definition video stream in either National Television System Committee NTSC or Phase Alternation Line PAL format and picture in picture mixing with a background layer The video stream is output in high resolution 800x480 LCD touch panel The example design demonstrates a framework for rapid development of video and image processing systems using the parameterizable MegaCore functions that are available in the Video and Image Processing Suite Available functions are listed in Table 4 1 This demonstration needs the Ouartus II license file includes the VIP suite feature Table 4 1 VIP IP Cores Functions IP MegaCore D ee escription Function Frame Reader Reads video from external memory
37. pw tvb 23th Vertical Back Porch tvb 10 th is fixed Vertical Front Porch tvfp 22 th Terasic VEEK MT User Manual 14 www terasic com Vertical Valid tvd 480 th Setup time Tdsu 8 ns DATA Hold time Tdsu 8 ns Table 3 2 Pin assignment of the LCD touch panel Signal Name ie ii Description O Standard LCD BO P28 LCD blue data bus bit 0 2 5V LCD B1 P27 LCD blue data bus bit 1 2 5V LCD B2 J24 LCD blue data bus bit 2 2 5V LCD B3 J23 LCD blue data bus bit 3 2 5V LCD B4 T26 LCD blue data bus bit 4 2 5V LCD B5 T25 LCD blue data bus bit 5 2 5V LCD_B6 R26 LCD blue data bus bit 6 2 5V LCD_B7 R25 LCD blue data bus bit 7 2 5V LCD_DCLK V24 LCD Clock 2 5V LCD_DE H23 Data Enable signal 2 5V LCD_DIM P21 LCD backlight enable 2 5V LCD_DITH L23 Dithering setting 2 5V LCD GO P26 LCD green data bus bit 0 2 5V LCD G1 P25 LCD green data bus bit 1 2 5V LCD G2 N26 LCD green data bus bit 2 2 5V LCD G3 N25 LCD green data bus bit 3 2 5V LCD G4 L22 LCD green data bus bit 4 2 5V LCD G5 L21 LCD green data bus bit 5 2 5V LCD G6 U26 LCD green data bus bit 6 2 5V LCD G7 U25 LCD green data bus bit 7 2 5V LCD HSD U22 Horizontal sync input 2 5V LCD MODE L24 DE SYNC mode select 2 5V LCD POWER CTL M25 LCD power control 2 5V LCD RO V28 LCD red data bus bit 0 2 5V LCD R1 V27 LCD red data bus bit 1 2 5V LCD R2 U28 LCD red data bus bit 2 2 5V LCD R3 U27 LCD red data bus bit 3 2 5V LCD R4 R28 LCD red data bus bit 4 2 5V LCD R5 R27 LCD red data bus bit 5 2 5V LCD R6 V26 LCD red da
38. ra 60 nm Cyclone IV E FPGA with 115K LES SOMHz Oscillator 64MB SDRAM x MB SRAM BMB FLASH SMA Ext Clock Out SMA Ext Clock In IR Receiver Figure 2 3 gives the block diagram of the VEEK MT board To provide maximum flexibility for the user all connections are made through the Cyclone IV E FPGA device Thus the user can configure the FPGA to implement any system design HSMC DE2 115 LTC Figure 2 3 Block Diagram of VEEK MT Terasic VEEK MT User Manual 9 www terasic com www terasic com Chapter 3 Using VEEK MT This section describes the detailed information of the components connectors and pin assignments of the VEEK MT 3 1 Configuring the Cyclone IV E FPGA The Video and Embedded Evaluation Kit VEEK MT contains a serial configuration device that stores configuration data for the Cyclone IV E FPGA This configuration data is automatically loaded from the configuration device into the FPGA every time while power is applied to the board Using the Quartus II software it is possible to reconfigure the FPGA at any time and it is also possible to change the non volatile data that is stored in the serial configuration device Both types of programming methods are described below 1 JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone IV E FPGA The FPGA will retain this
39. racted design tool provides an easy path to system integration of the video processing data path with a NTSC or PAL video input VGA output Nios II processor for configuration and control The Video and Image Processing Suite MegaCore functions have common open Avalon ST data interfaces and Avalon Memory Mapped Avalon MM control interfaces to facilitate connection of a chain of video functions and video system modeling In addition video data is transmitted between the Video and Image Processing Suite functions using the Avalon ST Video protocol which facilitates building run time controllable systems and error recovery Figure 4 9 shows the Video and Image Processing block diagram SOPC auge YO MS sng wasis 2GP yamg sng WajsAs La Figure 4 9 VIP Example SOPC Block Diagram Key Components Terasic VEEK MT User Manual 28 www terasic com www terasic com B Demonstration Source Code e Project directory VIP e Bitstream used VIP sof e Nios II Workspace VIP Software B Demonstration Batch File Demo Batch File Folder VIP demo_ batch The demo batch file includes the following files e Batch File VIP bat VIP_bashrc e FPGA Configuration File VIP sof e Nios II Program VIP elf B Demonstration Setup e Connect a DVD player s composite video output yellow plug to the Video IN RCA jack J12 of the VEEK MT The DVD player has to be configured to provide NTSC output or PAL output e Connect the VGA output o
40. re your SOF file is located and create your hardware binary file using the following commands Convert sof file into flash file sof2flash epcs input your example sof output your example_HW flash 3 Convert flash file into binary file nios2 elf objcopy I srec O binary your example_HW flash your example HW bin From the command shell navigate to where your ELF file is located and create your software binary file using the following command Terasic VEEK MT User Manual 41 www terasic com rasic com nios2 elf objcopy O binary your example elf your example SW bin 4 5 Create a new subdirectory and name it what you would like the title of your application to be shown as in the application selector e Using an SD card reader copy the directory onto an SD card into a directory named Application Selector The directory structure on the SD card should look like this Application_Selector lt Name of Application gt lt elf_name gt _SW bin lt sof_name gt _HW bin e Place the SD card in the VEEK MT and switch on the power The Application Selector will start up and you will now see your application appear as one of the selections Q 1 You may not need a CFI Flash controller when your design does not contain a Nios II processor or you store your software code within the on chip memory and use the hex initialization file 2 If you would like to use other memories such as SRAM
41. sensor Figure 4 16 shows the hardware system block diagram of this demonstration The system is clocked by an external 50MHz oscillator Through the internal PLL module the generated 150MHz clock is used for Nios II processor and other components and there is also 1OMHz for low speed peripherals Terasic VEEK MT User Manual 36 www terasic com rasic com va F il T 7 Y P E Ru i olige4 Peuuodlaju uejes S ADXL345 gt LCD APDS 9300 Figure 4 16 Block Diagram of the Digital Accelerometer Demonstration Demonstration Source Code Project directory G sensor Bit stream used G sensor sof Nios II Workspace G sensor Software B Demonstration Batch File Demo Batch File Folder G sensordemo batch The demo batch file includes the following files e Batch File G sensor bat test bashrc e FPGA Configuration File G sensor sof e Nios II Program G sensor elf B Demonstration Setup e Load the bit stream into the FPGA on the VEEK MT e Run the Nios II software under the workspace G sensorNSoftware Note e After the Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal its ADXL345 s ID e5 e Tilt the VEEK MT to all directions and you will find that the angle of the accelerometer and value of light sensor will change When turning the board from 80 to 10 and from 10 to 80 in
42. stures A 5 megapixel digital image sensor ambient light sensor and 3 axis accelerometer make up the rich feature set The VEEK MT is preconfigured with an FPGA hardware reference design including several ready to run demonstration applications stored on the provided SD card Software developers can use these reference designs as their platform to quickly architect develop and build complex embedded systems By simply scrolling through the demos of your choice on the LCD touch panel you can evaluate numerous processor system designs The all in one embedded solution offered on the VEEK MT in combination of the LCD touch panel and digital image module provides embedded developers the ideal platform for multimedia applications with unparalleled processing performance Developers can benefit from the use of FPGA based embedded processing system such as mitigating design risk and obsolescence design reuse reducing bill of material BOM costs by integrating powerful graphics engines within the FPGA and lower cost Figure 1 1 shows a photograph of VEEK MT Terasic VEEK MT User Manual I www terasic com rasic com Figure 1 1 Video and Embedded Development Kit Multi touch The key features of the board are listed below B DE2 115 Development Board Cyclone IV EP4CE115 FPGA o 114 480 LEs o 432 M9K memory blocks o 3 888 Kb embedded memory o 4 PLLs Configuration o On board USB Blaster circuitry o JTAG and AS mode configuration
43. supported o EPCS64 serial configuration device Memory Devices o 128MB SDRAM o 2MB SRAM o 8MB Flash with 8 bit mode o 32Kb EEPROM Switches and Indicators o 18 switches and 4 push buttons o 18 red and 9 green LEDs o Eight 7 segment displays Audio o 24 bit encoder decoder CODEC o 3 5mm line in line out and microphone in jacks Terasic VEEK MT User Manual 2 www terasic com rasic com e Character Display o 16x2 LCD module e On board Clocking Circuitry o Three 50MHz oscillator clock inputs o SMA connectors external clock input output e SD Card Socket o Provides SPI and 4 bit SD mode for SD Card access e Two Gigabit Ethernet Ports o Integrated 10 100 1000 Ethernet e High Speed Mezzanine Card HSMC o Configurable I O standards voltage levels 3 3 2 5 1 8 1 5V e USB Type A and B o Provides host and device controller compliant with USB 2 0 o Supports data transfer at full speed and low speed o PC driver available e 40 pin Expansion Port o Configurable I O standards voltage levels 3 3 2 5 1 8 1 5V e VGA out Connector o VGA DAC high speed triple DACS e DB9 Serial Connector o RS232 port with flow control e PS 2 Connector o PS 2 connector for connecting a PS2 mouse or keyboard e TV in Connector o TV decoder NTSC PAL SECAM e Remote Control o Infrared receiver module e Power o 12V DC input o Switching and step down regulators LM3150MH B Capacitive LCD Touch Screen e Equipped with an 7 inch amorphous TFT LCD Thi
44. ta bus bit 6 2 5V LCD R7 V25 LCD red data bus bit 7 2 5V LCD RSTB K22 Global reset pin 2 5V LCD SHLR H24 Left or Right Display Control 2 5V Terasic VEEK MT User Manual 15 www terasic com rasic com LCD UPDN K21 LCD VSD V22 TOUCH I2C SCL T22 TOUCH I2C SDA 721 TOUCH INT n R23 3 4 Using 5 Megapixel Digital Image Sensor Up Down Display Control Vertical sync input touch I2C clock touch I2C data touch interrupt 2 5V 2 5V 2 5V 2 5V 2 5V The VEEK MT is equipped with a 5 megapixel digital image sensor that provides an active imaging array of 2 592H x 1 944V It features low noise CMOS imaging technology that achieves CCD image quality In addition it incorporates sophisticated camera functions on chip such as windowing column and row skip mode and snapshot mode The sensor can be operated in its default mode or programmed by the user through a simple two wire serial interface for frame size exposure gain settings and other parameters Table 3 3 contains the pin names and descriptions of the image sensor module Table 3 3 Pin Assignment of the CMOS Sensor Signal Name CAMERA PIXCLK CAMERA DO CAMERA D1 CAMERA D2 CAMERA D3 CAMERA D4 CAMERA D5 CAMERA D6 CAMERA D7 CAMERA D8 CAMERA D9 CAMERA D10 CAMERA D11 CAMERA STROBE CAMERA LVAL CAMERA FVAL CAMERA RESET n CAMERA SCLK CAMERA TRIGGER CAMERA SDATA CAMERA XCLKIN FPGA Pin No Description J27 Pixel clock F24 Pixel data bit O F25 Pixel data bit 1 D26 Pix
45. tem enters the FREE RUN mode automatically Press KEY 0 on the DE2 115 board to reset the circuit e Press KEY 2 to stop run you can press KEY 3 again to switch back to FREE RUN mode and you should be able to see whatever the camera captures on the VGA display e User can use SW 17 to mirror image of the line However remember to press KEY 0 after toggle SW 17 e Press and drag the video frame box will result in scaling the playing window to any size as shown in Figure 4 10 Q Note 1 Execute VIP CameraMemo batclhNVIP CameraA bat will download sof and elf files 2 You may need additional Altera VIP suite Megacore license features to recompile the project Figure 4 15 illustrates the setup for this demonstration Terasic VEEK MT User Manual 35 www terasic com rasic com VGA Out VGA LCD CRT Monitor dc Figure 4 15 Setup for the VIP Camera demonstration 4 8 Digital Accelerometer Demonstration This demonstration shows a bubble level implementation based on a digital accelerometer We use LC protocol to control the ADXL345 digital accelerometer and the APDS 9300 Miniature Ambient Light Photo Sensor The LCD displays the interface When tilting the VEEK MT the ADXL345 measures the static acceleration of gravity In the Nios II software the change of angle in the x axis and y axis is computed and shown as angle data in the LCD display The value of light sensor will change as the brightness changes around the light
46. the left right mirror mode User could disable this functionality by modifying the related register value being written to CMOS controller chip DAT FVAL LVAL CMOS N RAW2RGB Capture y LCD Controller PCL CMOS MCLK Sensor pio Configuration Mult Port SDRAM MTLC Figure 4 12 Block Diagram of the Digital Camera Design Terasic VEEK MT User Manual 31 www terasic com www terasic com Demonstration Source Code Project directory Camera Bit stream used Camera sof Demonstration Batch File Demo Batch File Folder CameraNdemo batch The demo batch file includes the following files Batch File test bat FPGA Configuration File Camera sof Demonstration Setup Load the bit stream into FPGA by executing the batch file test bat under CameraMemo batch folder The system enters the FREE RUN mode automatically Press KEY 0 on the DE2 115 board to reset the circuit Press KEY 2 to take a shot of the photo you can press KEY 3 again to switch back to FREE RUN mode and you should be able to see whatever the camera captures on the LCD display User can use the SW 0 and KEY 1 to set the exposure time for brightness adjustment of the image captured When SW 0 is set to Off the brightness of image will be increased as KEYT 1 is pressed longer If SW 0 is set to On the brightness of image will be decreased as KEYT 1 is pressed shorter User can use SW 17 to mirror image of the line However remember to press

VEEK-MT User Manual - Mouser Electronics

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