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1. aeg 8 3 Functional Description 1 rare Inseln 9 SNO NI A 9 3 1 1 Switch DeflnitlO 1S ia e EE alici Alb ei b ad inia 9 31 2 LED Definition ea 10 3 2 Platform Interface 10 2 ia e ae ee pe 10 3 2 2IMBIST IDEE 11 mue 11 3 24 MRS I 11 3 25 EM 11 3 2 0 MPRESEN TE dece ean 11 32 1 JTAG Interface 11 3 2 7 1 JTAG Voltage nc Ret meinen 12 3 92 G DOKS LA Sc ri tA a E 12 SiS We B dE 12 3 3 2 20 ii ii a ee ee nie 13 3 3 3 PCle Reference Clock PCIEREFCLK 13 3 3 4 Secondary Reference Clock 2 2 13 3 9 9 REECGLICT25M itc P m HR E M epis eb M les 13 31910 GELK M2C i ia tates 14 i LEOTE AN PL op 14 3 4 Flash ia in A ee aet etate A a MIROR 14 exerum 15 3 5 1 Power Up 15 eR Marr inserieren 16 3 6 1 Automatic Temperature Monitoring e 16 3 75 Local Bus tn ne Getestet abel a e tide 17 3 9 Target FPGA ey les a este eet Ba b Gad o
2. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Alpha Data Table A 3 Connector P4 ADM XRC 6TL User Manual Version 1 0 24 Appendix B Front Connector Pinouts Appendix B Front XRM Connector Pinouts The XRM interface consists of two connectors CN1 and J3 is a 180 way Samtec QSH in 3 fields It is for general purpose signals power and module control J3 is a 28 wav Samtec QSE DP for high speed serial MGT links Kev General Purpose Clocks 1 XRM Connector Field 1 Alpha Data Signal FPGA Samtec Samtec FPGA Signal DA NO N39 1 2 M39 DA 1 DA PO N38 3 4 M38 DA 1 DA N2 T36 5 6 40 DA P3 DA P2 U36 7 8 41 DA N3 DA 4 140 9 10 L42 DA_N5 DA_P4 L39 11 12 L41 DA_P5 DA_N6 T35 13 14 R42 DA_N7 DA_P6 T34 15 16 P42 DA_P7 DA_P8 R39 17 18 M41 DA_P9 DA_N8 P38 19 20 M42 DA_N9 DA_N10 P37 21 22 T40 DA_N11 DA_P10 N36 23 24 R40 DA_P11 DA_N12 R38 25 26 N40 DA_P13 DA_P12 T39 27 28 N41 DA_N13 DA_N14 M37 29 30 T41 DA P15 DA P14 M36 31 32 T42 DA N15 DB NO V37 33 34 V36 DB 1 DB PO W37 35 36 W36 DB 1 SA 0 N35 37 38 P36 DA CC P16 39 40 P35 DA CC N16 41 42
3. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Table B 1 Connector Field 1 ADM XRC 6TL User Manual Version 1 0 Appendix B Front Connector Pinouts Page 25 2 XRM Connector Field 2 Signal FPGA Samtec Samtec FPGA Signal DB N2 V39 61 62 U34 DB N3 DB P2 U39 63 64 V34 DB P3 DB N4 U38 65 66 V35 DB N5 DB P4 U37 67 68 W35 DB P5 DB N6 U33 69 70 W38 DB N7 DB P6 U32 71 72 V38 DB P7 DB N8 U41 73 74 V40 DB P9 DB P8 U42 75 76 W40 DB N9 DB P10 V33 77 78 WA1 DB N11 DB N10 W33 79 80 VAI DB_P11 DB_N12 Y39 81 82 W42 DB_P13 DB_P12 Y40 83 84 Y42 DB_N13 DB_N14 Y35 85 86 AA39 DB N15 DB P14 AA35 87 88 Y38 DB_P15 DB_CC_P16 W32 89 90 AA34 SB_1 DB_CC_N16 Y33 91 92 AC38 SC 0 SA 1 R35 93 94 AD36 SC 1 SB 0 AA36 95 96 AG38 SD 0 DC CC P16 AD32 97 98 AB38 DC N1 DC CC N16 AE32 99 100 AB37 DC P1 DC NO AB36 101 102 AH34 DD CC P16 DC PO AC36 103 104 AJ35 DD CC N16 SD 1 AG36 105 106 AH35 SD 3 SD 2 AJ36 107 108 AF30 GCLK M2C N MGTCLK M2C P G10 109 110 AE30 GCLK M2C P MGTCLK M2C N G9 111 112 SDA MGTCLK C2M N 113 114 SCL MGTCLK C2M P 115 116 ALERT N K3 117 118 Ja Alpha Data Table B 2 XRM Connector Field 2 ADM XRC 6TL User Manual Version 1 0 26 Appendix Front Connector Pinouts B 3 XRM Connector
4. Field 3 Signal FPGA Samtec Samtec FPGA Signal DC P2 ACA1 121 122 AA42 DC P3 DC N2 AD41 123 124 42 DC N3 DC 4 AC33 125 126 AB39 DC 5 DC P4 AC34 127 128 40 DC 5 DC P6 AD42 129 130 AC40 DC_P7 DC_N6 AE42 131 132 AD40 DC N7 DC N8 AD33 133 134 41 DC 9 _ 8 135 136 41 DC P9 DC 10 AF42 137 138 AD38 DC N11 DC N10 AF41 139 140 AE38 DC P11 DC P12 AB32 141 142 AD37 DC N13 DC N12 AB33 143 144 AE37 DC P13 DC N14 AE39 145 146 AL42 DD P1 DC P14 40 147 148 42 DD DD PO AK38 149 150 5 DC N15 DD NO AJ38 151 152 AE34 DC P15 DD P2 AJ42 153 154 41 DD N3 DD N2 AK42 155 156 AL41 DD_P3 DD_N4 AG37 157 158 AG41 DD 5 DD P4 AF37 159 160 40 DD 5 DD 6 40 161 162 AL39 DD N7 DD 6 AL40 163 164 AK39 DD_P7 DD N8 AF36 165 166 AHA1 DD N9 DD P8 AF35 167 168 42 DD 9 DD 10 AJ40 169 170 AJ41 DD N11 DD P10 AH39 171 172 40 DD 11 DD N12 AF34 173 174 AG39 DD N13 DD 12 AG34 175 176 AF39 DD P13 DD N14 AG33 177 178 AK37 DD N15 DD P14 AF32 179 180 AJ37 DD_P15 Alpha Data Table Connector CN1 Field 3 ADM XRC 6TL User Manual Version 1 0 Appendix B Front Connector Pinouts Page 27 4 XRM Connector J3 Samtec Pin Samtec Pin JFPGA 1 2 H7 3 4 H8 5 6 G5 7 8 G6 9 10 P
5. Local Link REFCLK200M reserved pins 37 36 27 26 25 1 5 DRAM Banks0 amp 1 13 12 23 32 22 1 5 DRAM Banks 2 8 3 14 15 16 17 XRM VIO XRM Interface variable voltage 21 28 38 1 5V reserved Table 3 12 Target FPGA IO Banks 3 8 2 GTX Mappings There are a total of 24 MGT links connected to the Target FPGA 4tothe Bridge FPGA or PCle 3 0 4to PCle 7 4 the XRM Interface 8tothe secondary connector The connections of these links and their associated reference clocks are shown in Figure 5 below Alpha Data ADM XRC 6TL User Manual Version 1 0 18 3 Functional Description REFCLK 125M MGTCLK M2C XRM 7 0 XRM Target FPGA PCle Bridge Lu 221 3 0 FPGA PCle 3 0 CIKO 115 XMC P5 Y gt P5PCIeRefCIk 1 114 6 7 0 XMC P6 P6RefCIk 125MHz Osc Figure 5 MGT Links amp Clocking Note o 1 The numbering in the Target FPGA refers to the GTX Quad number Each Quad contains a grouping of four GTXE1 Multi Gigabit Transceivers and two dedicated reference clock pairs 2 Reference clocks can be routed internally from one Quad to other Quads directly above and below In the diagram clocks shown with a dashed line are available for use by the Quad using this internal routing
6. 1 24 Table B 2 Connector Field 2 nenn nenn nennen 25 Table B 3 Connector Field 3 26 Tabe B4 XRM Gonnector JB sid ertet ri edente ebrei haj i tak g an baka 27 Table C 1 XRM 1O146 Pinout pins 1 38 nnne nnns 28 Table C 2 XRM 1O146 Pinout pins 39 76 29 Table XRM 1O146 Pinout pins 77 114 29 Table C 4 XRM 1O146 Pinout pins 115 152 iii 30 Alpha Data ADM XRC 6TL User Manual Version 1 0 6 1 Introduction This page intentionallv left blank Alpha Data ADM XRC 6TL User Manual Version 1 0 1 Introduction Page 7 1 Introduction The ADM XRC 6TL is a high performance for applications using Virtex 6 FPGAs from Xilinx This card supports all Virtex 6 LXT and SXT devices available in the FF G 1759 package The card includes separate FPGA with a PCle bridge developed by Alpha Data Using a separate device allows high performance operation without the need to integrate proprietary cores in the user target FPGA The ADM XRC 6TL is available in air cooled and conduction cooled configurations 1 1 Key Features Single width compliant to VITA Standard 42 0 and 42 3 Dedicated 4 lane PCI Express interface with high performance DMA controllers e Virtex 6 FPGA FF G 1759 package independent banks of DD
7. 9 Figure 2 JTAG Header 22 orli Lilia 11 Figure 3 JTAG Boundary Scan 12 Figure 4 Flash Memory 15 Foure S Links amp a LA Sta ta PR keg 18 Figur 6 DRAM Ban ks 4 2 2 3042220 Han He esse 19 Table of Tables T bl 1 1 References anne ee tuta 7 Table 3 1 Switch 10 T ble 3 2 LED Definitions E a s 10 T ble 3 3 ECLK Connection i eee do aii Fe eres 12 Table 3 4 REFCLK200M ConnectionS 13 Fable 3 5 PCIEREFCLK R Connections sais coria ins ice 13 Tabie 3 6 POREFGLK Connections tires resi ir 13 Table 3 7 REFCLK125M Connections 14 Table 3 8 GCLK M2C 14 Table 3 9 MGTCLK M2C Connections 14 Table 3 10 Voltage and Temperature MONItOrs i 16 Table 3 11 Temperature Limits 16 Table 3 12 Target FPGA IO Banks 17 T ble 3 13 XRM GPIO ps aaa 20 T 3bl amp A 1 XMG Connector aan 21 Table Ai2 XMG Connector Poran eee ri te Do tre ii eden 22 Table PMC Connector 4 2 0000 000011 23 Table B 1 XRM Connector Field
8. GND GND GND GND REFCLK 1 REFCLK 1 ROOT1 Notes Table A 2 XMC Connector P6 1 PCle Channel 1 Lanes 7 0 are connected to the Target FPGA Other protocols can be used on these links subject to carrier support 2 GPIO signals are single ended and 3 3V compatible Alpha Data ADM XRC 6TL User Manual Version 1 0 Rear Connector Pinouts Page 23 A 3 Connector 4 The Connector 4 is fitted as standard but can be omitted if required 32 GPIO signals are connected between P4 and the target FPGA via FET bus switches Bv limiting the signal voltage at 2 5V these allow the use of 3 3V or 2 5V signalling levels to be used at P4 Signals mav be used in single ended or as differential pairs Signal FPGA Pin P4 Pin P4 Pin FPGA Pin Signal PN4 P1 N33 1 2 T30 PN4 P2 PN4 N1 P33 3 4 R30 PN4 N2 PN4 P3 R32 5 6 W30 4 4 PN4 N3 T32 7 8 V30 4 4 PN4 P5 V31 9 10 AN14 PN4 P6 PN4 N5 W31 11 12 AN13 PN4 6 4 P7 Y30 13 14 AA31 PN4 P8 PN4 7 AA30 15 16 AB31 PN4 8 4 9 AG32 17 18 AH30 PN4 P10 PN4 9 AF31 19 20 AJ30 PN4 N10 PN4 P11 AH31 21 22 AK33 PN4 P12 PN4 N11 AG31 23 24 AJ32 PN4 N12 PN4 P13 AV13 25 26 AW12 PN4 P14 PN4 N13 AV14 27 28 AW13 PN4 N14 PN4 P15 BA16 29 30 BB13 PN4 P16 PN4 N15 BA17 31 32 BB14 PN4 N16 33 34
9. PEROp3 PEROn3 VPWR 9 GND GND GA2 GND GND MSDA PEROp4 PEROn4 PEROp5 PEROn5 VPWR GND GND MVMRO GND GND MSCL PEROp6 PEROn6 PEROp7 PEROn7 GND GND GND GND REFCLK 0 REFCLK 0 WAKE ROOTO Table A 1 XMC Connector P5 PCle Channel 0 Lanes 3 0 are connected to the Bridge FPGA by default but can be routed to the target FPGA PCle Channel 0 Lanes 7 4 are only connected to the Target FPGA This may be used as a second 4 lane channel if supported by the carrier card although this configuration is non standard JTAG is unused XMC_TDI is connected to XMC_TDO 3 3V AUX is unused VPWR can be either 5V or 12V Alpha Data ADM XRC 6TL User Manual Version 1 0 22 Appendix Rear Connector Pinouts A 2 Secondarv XMC Connector P6 100 PET1nO GPIO 00 1 1 1 1 GPIO 12 GND GND GPIO 01 GND GND GPIO 13 102 1 2 GPIO 02 PET103 PET1n3 GPIO 14 GND GND GPIO 03 GND GND GPIO 15 PET104 PET1n4 GPIO 04 PET105 PET1n5 GPIO 16 GND GND GPIO 05 GND GND GPIO 17 PET 106 PET1n6 GPIO 06 1 7 PET1n7 GPIO 18 GND GND GPIO 07 GND GND GPIO 19 GPIO 08 GPIO 20 GND GND GPIO 09 GND GND GPIO 21 PER100 PER1nO GPIO 10 PER101 PER1n1 GPIO 22 GND GND GPIO 11 GND GND GPIO 23 PER102 PER1n2 PER103 PER1n3 GND GND GND GND PER104 PER1n4 PER105 PER1n5 GND GND GND GND PER106 PER1n6 PER107 PER1n7
10. 0MH2 gt 146 bit P5 PCle x4 gt Virtex5 FX70T MPTL Control 4 0 FFG665 Front MGT Front IO 8 XRM I F PCle x4 Gen2 capable MGT x8 or app specific protocol P6 Rear GPIO 24 bit P4 Rear GPIO 32 bit GTP 5Gbls x4 User FPGA Virtex 6 LXT SXT FFG1759 720 VO 25 GTX m System Monitor JTAG Battery for AES keys DDR3 SDRAM 256MB DDR3 SDRAM 256MB DDR3 SDRAM 256MB DDR3 SDRAM 256MB Figure 1 ADM XRC 6TL Top Level Block Diagram 3 1 1 Switch Definitions There is a set of eight DIP switches placed on the rear of the board Their functions are described in Table 3 1 below the OFF position for normal operation Note All switches are OFF by default All Factory Test and Reserved switches must be in Alpha Data ADM XRC 6TL User Manual Version 1 0 10 3 Functional Description Switch Ref Function ON State Off State SW1 1 Bridge Bridge FPGA is bypassed PCIe lanes Bridge FPGA is used PCle lanes 3 0 Bypass 3 0 are connected directly to the user are connected to the bridge FPGA SW1 2 Factory Test Factory Test Mode Normal Operation SW1 3 Reserved B SW1 4 Reserved 5 SW1 5 One time Target FPGA is cleared then configured Target FPGA is cleared then configured Configurat
11. 3 9 Memory Interfaces The ADM XRC 6TL has four independent banks of DDR3 SDRAM Each bank consists of two 16 bit wide memory devices in parallel to provide a 32 bit datapath capable of running up to 400MHz DDR 800 1Gb devices Micron MT41J64M16 187E are fitted as standard to provide 256MB per bank 2Gb devices giving 512MB per bank are available as an ordering option The memory banks are arranged for compatibility with the Xilinx Memory Interface Generator MIG Figure 6 Shows the component references and FPGA banks used Full details of the interface signalling standards and an example design are provided in the SDK Note DRAM Banks 0 amp 1 must use a common write clock due to restrictions in CLKPERF routing in the FPGA Alpha Data ADM XRC 6TL User Manual Version 1 0 3 Functional Description Page 19 DRAM Bank 0 DRAM Bank 1 011 amp 025 014 amp 022 Adr Ctl 36 37 27 Adr Ctl 26 25 00 37 37 36 36 00 25 25 26 27 Virtex 6 013 Adr Ctl 32 22 23 12 Adr Ctl 23 DQ 22 22 32 32 DQ 12 12 13 13 DRAM Bank 3 DRAM Bank 2 U12 8 026 015 8 023 Figure 6 DRAM Banks 3 10 Interface and Front Panel I O The XRM interface provides a high performance and flexible front panel interface through a range of interchangeable XRM modules Further details of the XRM modules can be found on the Alpha Data website The interface consi
12. 36338805 Figure 2 JTAG Header J2 The scan chain is shown in Figure 3 Alpha Data ADM XRC 6TL User Manual Version 1 0 12 3 Functional Description Bridge FPGA Control CPLD Target FPGA XC5VEX70T XC2C64A XCEVLXxxxT rFEGGG5 CP56 FFG1759 TDI Level Shift HDR TDO 2 5V VIO DET XRM XRM En M e VREF 2 5V I PRESENT Figure 3 JTAG Boundary Scan Chain 3 2 7 1 JTAG Voltage The Vcc supply provided on J2 to the JTAG cable is 2 5V and is protected by a poly fuse rated at 350mA The JTAG scan chain uses 2 5V CMOS levels at J2 3 3V signals must not be used The JTAG signals at the interface use the adjustable voltage XRM VIO 3 3 Clocks The ADM XRC 6TL provides a wide variety of clocking options The programmable and fixed reference clocks on the board can be combined with the PLLs in the FPGA to suit the target application The on board clocks are detailed below Note Clock Termination The LVDS clocks do not have termination resistors on the circuit board On die terminations in the FPGA must be enabled by setting the attribute DIFF TERM TRUE This can either be set in the source code when instantiating the buffer or in the User Constraints File UCF See the Xilinx Virtex 6 Libraries Guide
13. 4 REFCLK200M Connections 3 3 3 Reference Clock PCIEREFCLK The 100MHz PCI Express reference clock is provided by the carrier card through the Primary XMC connector P5 at pins A19 and B19 This is multiplied to 250MHz and distributed to both the Bridge and Target FPGAs On the Target FPGA it is connected to GTX Quad 113 and 114 to allow its use as a reference for all the MGT links to the XMC connectors See Figure 5 on page 18 for details of the MGT links and reference clocks PCIEREFCLK 1 MGTREFCLK1 113 LVDS 25 AD8 AD7 PCIEREFCLK 2 MGTREFCLKO 114 LVDS 25 AB8 AB7 Table 3 5 PCIEREFCLK Connections 3 3 4 Secondary Reference Clock The carrier can provide a reference clock through the Secondary connector P6 at pins 19 8 B19 This PEREFCLE is connected directly to the target FPGA P6REFCLK MGTREFCLKO_113 carrier dependent AF8 AF7 Table 3 6 P6REFCLK Connections 3 3 5 REFCLK125M The fixed 125 0MHz reference clock REFCLK125M is a differential clock signal using LVDS The clock is buffered and connected to three MGTREFCLKO inputs on the Target FPGA at GTX Quad 112 115 and 116 See Figure 5 Alpha Data ADM XRC 6TL User Manual Version 1 0 14 3 Functional Description REFCLK125M 3 MGTREFCLKO 112 LVDS 25 AK8 AK7 REFCLK125M 2 MGTREFCLKO 115 LVDS 25 V8 V7 REFCLK125M 1 MGTREFCLKO 116 LVDS 25 M8 M7 Table 3 7 REF
14. 7 11 12 P8 13 14 N5 15 16 N6 17 18 F7 19 20 F8 21 22 E5 23 24 E6 25 26 L5 27 28 L6 Alpha Data Table B 4 XRM Connector J3 ADM XRC 6TL User Manual Version 1 0 28 Appendix XRM IO146 Pinout XRM IO146 Pinout The following tables detail the pin out of the Mictor connector on the XRM IO146 when fitted to an ADM XRC 6TL Signal FPGA Samtec Mictor Mictor Samtec FPGA Signal DA_PO N38 3 1 2 40 DA P3 DA NO N39 1 3 4 41 DA N3 DA P2 U36 7 5 6 4 M38 DA 1 DA N2 T36 5 7 8 2 M39 DA N1 DA P4 L39 11 9 10 12 L41 DA_P5 DA_N4 L40 9 11 12 10 L42 DA_N5 DA_P6 T34 15 13 14 16 P42 DA_P7 DA_N6 T35 13 15 16 14 R42 DA_N7 DA_P8 R39 17 17 18 18 M41 DA_P9 DA_N8 P38 19 19 20 20 M42 DA_N9 DA_P10 N36 23 21 22 24 R40 DA_P11 DA_N10 P37 21 23 24 22 T40 DA_N11 DA_P12 T39 27 25 26 26 N40 DA_P13 DA_N12 R38 25 27 28 28 N41 DA N13 DA P14 M36 31 29 30 30 T41 DA_P15 DA_N14 M37 29 31 32 32 T42 DA N15 SA 0 N35 37 33 34 38 P36 DA 16 SA 1 R35 93 35 36 40 P35 DA CC N16 5V 37 38 go 4 SB 1 Table C 1 XRM 10146 Pinout pins 1 38 Alpha Data ADM XRC 6TL User Manual Version 1 0 Appendix XRM IO146 Pinout Pa
15. ADM XRC 6TL XMC Mezzanine Card User Guide Version 1 0 9 DATA 2 Copyright 2010 Alpha Data Parallel Systems Ltd All rights reserved This publication is protected by Copyright Law with all rights reserved No part of this publication mav be reproduced in anv shape or form without prior written consent from Alpha Data Parallel Systems Limited Alpha Data Alpha Data 4 West Silvermills Lane 2570 North First Street Suite 440 Edinburgh EH3 5BD San Jose CA 95131 UK USA Phone 44 0 131 558 2600 Phone 408 467 5076 Fax 44 0 131 558 2700 Fax 866 820 9956 Email support alphadata co uk Email support alpha data com Alpha Data ADM XRC 6TL User Manual Version 1 0 3 Revision Historv 09 01 10 0 First Draft 0 12 01 10 Second Draft Alpha Data ADM XRC 6TL User Manual Version 1 0 4 Table of Contents rear EMS Haie 7 Lele Key Eeatutes it in Ut te e 7 1 2 References amp 7 2 Installation ttt tet m em a mc e t eet 8 2 1 Software Installation 8 2 2 Hardware Installation 5 2 eat eon Roo ER RE RS ERAS 8 2 2 1 Handling Instructions u see ene eaae nera RR 8 2 2 2 Motherboard Carrier 2 8 2 2 3 Goolng
16. CC P16 SC 1 AD36 94 111 112 99 AE32 DC CC N16 5V 113 114 5V Table C 3 XRM 10146 Pinout pins 77 114 Alpha Data ADM XRC 6TL User Manual Version 1 0 30 Appendix XRM IO146 Pinout Signal FPGA Samtec Mictor Samtec JFPGA Signal DD PO AK38 149 115 116 146 142 DD P1 DD NO AJ38 151 117 118 148 42 DD 1 DD P2 AJ42 153 119 120 156 ALA1 DD P3 DD N2 AK42 155 121 122 154 AM41 DD N3 DD P4 AF37 159 123 124 160 AF40 DD P5 DD N4 AG37 157 125 126 158 AG41 DD N5 DD P6 AK40 161 127 128 164 AK39 DD P7 DD N6 AL40 163 129 130 162 AL39 DD N7 DD P8 AF35 167 131 132 168 AG42 DD P9 DD N8 AF36 165 133 134 166 41 DD 9 DD 10 AH39 171 135 136 172 40 DD P11 DD N10 40 169 137 138 170 AJ41 DD_N11 DD_P12 AG34 175 139 140 176 AF39 DD_P13 DD_N12 AF34 173 141 142 174 AG39 DD_N13 DD_P14 AF32 179 143 144 180 AJ37 DD_P15 DD_N14 AG33 177 145 146 178 AK37 DD_N15 SD_0 AG38 96 147 148 102 AH34 DD_CC_P16 SD_3 AH35 106 149 150 104 AJ35 DD CC N16 5V 151 152 5V Table C 4 XRM IO146 Pinout pins 115 152 Alpha Data ADM XRC 6TL User Manual Version 1 0
17. CLK125M Connections 3 3 6 GCLK M2C The clock GCLK_M2C is a differential clock signal using LVDS It is provided by an XRM module through the XRM connector CN1 at pins 110 amp 108 Itis connected to a Global Clock input on the Target FPGA GCLK M2C IO LO GC 24 LVDS 25 AE30 AF30 Table 3 8 GCLK M2C Connections 3 3 7 MGTCLK M2C The reference clock MGTCLK M2C is a differential clock signal using LVDS The clock is provided by an XRM module through the XRM connector CN1 at pins 109 amp 111 It is connected to GTX Quad 117 on the Target FPGA for application specific frequencies line rates MGTCLK M2C MGTREFCLKO 117 LVDS 25 G10 G9 Table 3 9 MGTCLK M2C Connections 3 4 Flash Memory 512Mb Flash Memory Intel Numonyx PC48F4400PO0VBOO is used to store board Vital Product Data VPD programmable clock parameters and configuration bitstreams for the Bridge and Target FPGAs The flash memory cannot be accessed by the target FPGA Host access is only possible through the FLCTL FLPAGE and FLDATA registers in the bridge FPGA Utilities for erasing programming and verification of the flash memory are provided in the ADM XRC SDK Write Protect The Flash Write Protect WP pin is connected to an inverted version of the MVMRO signal at the XMC interface When the MVMRO signal is active High all writes to the flash will be inhibited This state will be indicated by the Amber LED D7 Alpha Data A
18. DM XRC 6TL User Manual Version 1 0 3 Functional Description Page 15 Alternate Bridge FPGA Bitstream Default Bridge FPGA Bitstream Vital Product Data VPD LCLK Word 15 0 LCLK Word 31 16 reserved BO Length 7 0 Boot Flag 0 Bitstream 0 Length 23 8 reserved Default Target FPGA Bitstream Target Bitstream 0 B1 Length 7 0 Boot Flag 1 Bitstream 1 Length 23 8 reserved Alaternate Target FPGA Bitstream Target Bitstream 1 0 0000 0000 0x007F_FFFI 0 0080 0000 OxOOFF FFFI 0 0100 000 0 0100 03FE 0 0100 0400 0 0100 0402 0 0120 0000 0 0120 0002 0 0122 0000 0x028F FFFE 0x0290 0000 0x0290 0002 0x0292 0000 OxO3FF FFFE Figure 4 Flash Memory Map 3 5 Configuration 3 5 1 Power Up Sequence If valid data is stored in the flash memory the bridge will automatically set the programmable clock generator and configure the Target FPGA at power up This sequence can be inhibited by turning the Flash Boot Inhibit FBI switch SW 1 6 to ON See Table 3 1 Note If an over temperature alert is detected from the System Monitor the target will be cleared by pulsing its PROG signal See Section 3 6 1 Alpha Data ADM XRC 6TL User Manual Version 1 0 16 3 Functional Description 3 6 Health Monitoring The ADM XRC 6TL has
19. R3 800 SDRAM 256MB bank 1GB total 2GB option Front panel XRM interface with adjustable voltage 146 free I O signals and 8 MGT links to user FPGA Rear panel interface with 24 GPIO signals 8 8 GTP links between user FPGA and P6 4 additional GTP links between user FPGA and P5 Rear panel PMC interface with 32 GPIO signals between user FPGA and P4 optional e Voltage and temperature monitoring 1 2 References amp Specifications ANSI VITA 42 0 XMC Standard December 2008 VITA ISBN 1 885731 49 3 ANSI VITA 42 3 XMC Express Protocol Layer Standard June 2006 VITA ISBN 1 885731 43 4 ANSI IEEE 1386 2001 IEEE Standard for a Common Mezzanine Card CMC Family October 2001 IEEE ISBN 0 7381 2829 5 ANSI IEEE 1386 1 2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC October 2001 IEEE ISBN 0 7381 2831 7 ANSI VITA 20 2001 R2005 Conduction Cooled PMC February 2005 VITA ISBN 1 885731 26 4 Table 1 1 References Alpha Data ADM XRC 6TL User Manual Version 1 0 8 2 Installation 2 Installation 2 1 Software Installation Please refer to the Software Development Kit SDK installation CD The SDK contains drivers examples for host control and FPGA design and comprehensive help on application interfacing 2 2 Hardware Installation 2 2 1 Handling Instructions The components on this board can damaged e
20. XRC 6TL User Manual Version 1 0 3 Functional Description Page 11 3 2 2 MBIST Built In Self Test This output signal is driven active low until the FPGA with PCle interface is configured In normal operation this is the bridge FPGA In Bridge Bvpass mode it is the target FPGA 3 2 3 MVMRO Write Prohibit This signal is an input from the carrier When asserted high all writes to non volatile memories are inhibited This is indicated bv the Amber LED D7 This signal cannot be internally driven or over ridden A buffered version of the signal is connected to the target FPGA at pin AD30 3 2 4 MRSTIH XMC Reset In This signal is an active low input from the carrier When asserted the bridge FPGA will be reset At the end of the reset the target FPGA configuration sequence will start See Section 3 5 on page 15 The MRSTI signal is translated to 2 5V levels and connected to the target FPGA at pin AC30 3 2 5 MRSTO XMC Reset Out This optional output signal is unused and undriven 3 2 6 MPRESENT Module Present This output signal is connected directiv to OV 3 2 7 JTAG Interface The JTAG interface on the XMC connector is unused TDI is connected directly to XMC TDO A JTAG boundarv scan chain is connected to header J2 This allows the connection of the Xilinx JTAG cable for FPGA debug using the Xilinx ChipScope tools The JTAG Header pinout is shown in Figure 1 below lt 4a E
21. and Constraints Guide for further details 3 3 4 LCLK The programmable clock is a single ended clock with L CMOS25 levels connected to a Global Clock input on the Target FPGA at pin AY14 It is generated from a 100MHz reference by a DOM within the bridge FPGA LCLK may be set between 32MHz and 140MHz Signal Target FPGA Input IO Standard P pin N pin LCLK IO LOP GC 34 LVCMOS25 AY14 n a Table 3 3 LCLK Connection The frequency is set by writing DCM multiply and divide values to the LCLOCK register in the bridge FPGA The default rate is 40MHz and is set at power up An alternative default rate can be stored in flash memory FlashAdr 0x0100 0400 DCM Multiplier Value 1 FlashAdr 0x0100 0402 DCM Divider Value 1 Note If the target FPGA design includes a DCM driven by LCLK the clock frequency should be set prior to Target FPGA configuration Alpha Data ADM XRC 6TL User Manual Version 1 0 3 Functional Description Page 13 3 3 2 REFCLK200M The fixed 200MHz reference clock REFCLK200M is a differential clock signal using LVDS It is connected to a Global Clock input on the Target FPGA at pins AP11 and AP12 This clock can be used to generate application specific clock frequencies using the PLLs within the Virtex 6 FPGA It is also suitable as the reference clock for the IO delay control block IDELAYCTRL REFCLK200M IO L1 GC 34 LVDS 25 AP11 AP12 Table 3
22. emperature limits are shown in Table 3 11 below Target FPGA Board LM87 Min Max Min Max Commercial 0 85 0 70 Industrial 40 100 40 85 Table 3 11 Temperature Limits Important If any temperature limit is exceeded the Target FPGA is automatically cleared This is indicated by Green LED D13 Target DONE switching off and Red LED D14 Fault switching on Alpha Data ADM XRC 6TL User Manual Version 1 0 3 Functional Description Page 17 The purpose of this mechanism is to protect the card from damage due to over temperature It is possible that it will cause the user application and possibly the host computer to hang 3 7 Local Bus A Multiplexed Packet Transport Link MPTL connects the Bridge and Target FPGAs It is capable of transferring data at up to 1GB s simultaneously in each direction The MPTL replaces the parallel local bus used in previous generations of the ADM XRC series Details of the link and example designs are given in the Software Development Kit SDK 3 8 Target FPGA 3 8 1 Bank Voltages The Target FPGA IO is arranged in banks each with their own supply pins The bank numbers their voltage and function are shown in Table 3 12 Full details of the IOSTANDARD required for each signal are given in the SDK IO Banks Voltage Purpose 0 24 2 5V Configuration JTAG Pn4 33 34 35 2 5V Pn4
23. ge 29 Signal FPGA Samtec Mictor Samtec FPGA Signal DB PO W37 35 39 40 36 W36 DB P1 DB NO Y37 33 41 42 34 36 DB N1 DB P2 U39 63 43 44 64 34 DB P3 DB N2 V39 61 45 46 62 U34 DB N3 DB P4 U37 67 47 48 68 W35 DB P5 DB N4 U38 65 49 50 66 V35 DB N5 DB P6 U32 71 51 52 72 38 _ 7 DB N6 U33 69 53 54 70 W38 DB N7 DB P8 042 75 55 56 74 V40 DB P9 DB N8 041 73 57 58 76 W40 DB N9 DB 10 V33 77 59 60 80 VAI DB_P11 DB_N10 W33 79 61 62 78 W41 DB N11 DB P12 Y40 83 63 64 82 W42 DB_P13 DB_N12 Y39 81 65 66 84 Y42 DB_N13 DB_P14 AA35 87 67 68 88 Y38 DB_P15 DB_N14 Y35 85 69 70 86 AA39 DB_N15 SD 1 AG36 105 71 72 89 W32 DB CC P16 SD 2 AJ36 107 73 74 91 Y33 DB CC N16 5V 75 76 95 AA36 SB 0 Table C 2 XRM IO146 Pinout pins 39 76 Signal FPGA Samtec Mictor Samtec JFPGA Signal DC PO AC36 103 77 78 100 AB37 DC_P1 DC_NO AB36 101 79 80 98 AB38 DC_N1 DC_P2 41 121 81 82 122 42 DC P3 DC N2 ADA1 123 83 84 124 42 DC N3 DC P4 AC34 127 85 86 126 AB39 DC P5 DC AC33 125 87 88 128 40 DC 5 DC P6 AD42 129 89 90 130 40 DC P7 DC 6 42 131 91 92 132 AD40 DC_N7 DC_P8 AE33 135 93 94 136 41 _ 9 DC N8 AD33 133 95 96 134 41 DC 9 DC 10 AF42 137 97 98 140 AE38 DC_P11 DC_N10 AF41 139 99 100 138 AD38 DC_N11 DC_P12 AB32 141 101 102 144 AE37 DC_P13 DC_N12 AB33 143 103 104 142 AD37 DC N13 DC P14 40 147 105 106 152 4 DC 15 DC N14 AE39 145 107 108 150 AE35 DC N15 SC 0 AC38 92 109 110 97 AD32 DC
24. ion from Flash at power up only from flash at power up and after every board reset MRSTIH SW1 6 Flash Boot Target FPGA is not configured from on Target FPGA is configured from on board Inhibit board flash memory flash memory SW1 7 Reserved SW1 8 Reserved 3 1 2 LED Definitions Table 3 1 Switch Definitions There are six LEDs placed on the rear of the board to indicate the current status Comp Ref Function ON State Off State D7 Amber MVMRO Inhibit writes to non volatile memories Enable writes to non volatile memories D8 Amber Bridge Bridge FPGA is bypassed PCle lanes Bridge FPGA is used PCle lanes 3 0 Bypass 3 0 are connected directly to the user are connected to the bridge FPGA 011 Green Power Good 2 5V 1 8V and 1 5V power supplies are 2 5V 1 8V and 1 5V power supplies are on not all on or at their correct levels 012 Green Bridge Done Bridge FPGA is configured Bridge FPGA is unconfigured D13 Green Target Done Target FPGA is configured Target FPGA is unconfigured D14 Red Fault Voltage or Temperature Fault Detected No fault detected Table 3 2 LED Definitions 3 2 XMC Platform Interface 3 2 1 IPMI A 2 kbit EEPROM type M24C02 is connected to the IPMI This memory contains board information tvpe voltage requirements etc as defined in the the XMC based specification Alpha Data ADM
25. lectrostatic discharge ESD To prevent damage observe SSD precautions Always wear a wrist strap when handling the card Hold the board by the edges Avoid touching any components Store in ESD safe bag 2 2 2 Motherboard Carrier Requirements The ADM XRC 6TL is a single width XMC 3 mezzanine with optional P6 and P4 connectors The motherboard carrier must comply with the XMC 3 VITA 42 3 specification for the Primary XMC connector J5 The Secondary XMC connector J6 should also be compatible with the XMC 3 pinout Note Connector P6 on the card is not compatible with the XMC 10 GPIO Standard In particular USB VCC must not be applied on this connector The ADM XRC 6TL is compatible with either 5V or 12V on the VPWR power The power dissipation of the board is highly dependent on the Target FPGA application A power estimator spreadsheet is available on request from Alpha Data This should be used in conjunction with Xilinx power estimation tools to determine the exact current requirements for each power rail 2 2 3 Cooling Requirements t b d Alpha Data ADM XRC 6TL User Manual Version 1 0 3 Functional Description Page 9 3 Functional Description 3 1 Overview PWR oe Power Boot Ctl IPMI Pu ba 3V3 Conversion CPLD EPROM 64MB 200MHz BRG BVPASS XRM Bus Bridge Control FPGA LCLK 32 10
26. nded GPIO Group B 16 XRM DB 15 0 16 diff Pairs 32 single ended XRM DB CC 16 Regional Clock GPIO pair 2 single ended SB 1 0 2 single ended GPIO Group C 15 XRM DC 15 0 16 diff Pairs 32 single ended XRM DC CC 16 Regional Clock GPIO pair 2 single ended SC 1 0 2 single ended GPIO Group D 14 XRM DD 15 0 16 diff Pairs 32 single ended XRM DD CC 16 Regional Clock GPIO pair 2 single ended SD 3 0 4 single ended GPIO Table 3 13 XRM GPIO Groups 3 10 4 I F High speed Serial Links Eight MGT links are routed between the Target FPGA and the XRM interface Lanes 6 0 are routed through the Samtec QSE DP connector J3 Lane 7 is routed through the Samtec QSH connector CN1 Alpha Data ADM XRC 6TL User Manual Version 1 0 Appendix A Rear Connector Pinouts Page 21 Appendix A Rear Connector Pinouts A 1 Primary XMC Connector P5 Notes 1 2 3 4 5 PETOpO PETOnO 3 3V PETOp1 PETOn1 VPWR 9 GND GND XMC TRSTH GND GND MRSTIH PETOp2 PETOn2 3 37 PETOp3 VPWR GND GND XMC TCK GND GND MRSTOH PETOp4 4 3 3V 5 PETOn5 VPWR 9 GND GND XMC TMS GND GND 12V PETOp6 PETOn6 3 3V PETOp7 PETOn7 VPWR 9 GND GND XMC_TDI GND GND 12V x VPWR GND GND XMC GND GND GAO PEROpO PEROnO MBISTH PEROp1 PEROn1 VPWR GND GND GA1 GND GND MPRESENT PEROp2 PEROn2
27. sos ok 17 3 9 Bank Voltage Secere is 17 3 8 2 ee thence 17 3 9 Memory Interfaces pra bia ER 18 3 10 XRM Interface and Front Panel I O 19 3 10 1 XRM Connectors eu na 19 3 10 2 XRM eye acd druknet kaken snutt 19 3 10 3 tro M toe apre ta tet e eir ree reete Ede esto rte 19 3 10 4 XRM High speed Serial LinkS 20 Appendix Rear Connector Pinouts 21 A 1 Primary Connector 5 lt lt 21 2 Secondary Connector 22 22 Connector P i iii EET dakka a 23 Alpha Data ADM XRC 6TL User Manual Version 1 0 Appendix B Front XRM Connector PiNOUtSs i 24 B 1 XRM Gonnector GN1 Field ee a i a A 24 B 2XxRM ConnectorGN1 Field 2 2 25 B 3 XRM Connector Field 26 B 4 XRM Gonn ctor DB i e 27 Appendix C XRM IO146 Pinout nn 28 Table of Figures Figure 1 ADM XRC 6TL Top Level Block
28. sts of two samtec connectors 1 and J3 3 10 1 XRM Connector CN1 Connector CNI is for general purpose signals power and module control The connector is a 180 Samtec connector with 3 fields The part fitted to the ADM XRC 6TL is Samtec QSH 090 01 F D A K Full pinout information for this connector is listed in Appendix B 1 3 10 2 XRM Connector J3 Connector J3 is for the high speed serial MGT links The part fitted to the ADM XRC 6TL is Samtec QSE 014 01 F D DP A K Full pinout information for this connector is listed in Appendix B 4 3 10 3 XRM I F GPIO The general purpose IO GPIO signals are connected in 4 groups to the Target FPGA group consists of 16 standard I O pairs a Regional Clock Capable pair and either 2 or 4 single ended signals There are no on board terminations on the pairs and any can be used in single ended modes To allow fast data transfer all of the GPIO signals within a group are delay matched to within 100ps All the XRM GPIO signals and FPGA IO banks share a common voltage XRM VIO that van be either 2 5V 1 8V or 1 5V The required voltage is stored within the platform management PROM on the XRM Alpha Data ADM XRC 6TL User Manual Version 1 0 20 3 Functional Description Group 17 XRM DA 15 0 16 diff 32 single ended XRM DA CC 16 Regional Clock GPIO pair 2 single ended SA 1 0 2 single e
29. the ability to monitor temperature and voltage to maintain a check on the operation of the board The monitoring is implemented using a National Semiconductor LM87 connected to control logic in the bridge FPGA using EC The control logic scans the LM87 when instructed bv host software and stores the current measurements in a blockram This allows the values to be read without the need to communicate directiv with the LM87 The following voltage rails and temperatures are monitored Monitor Purpose 1 0V FPGA Core Supply VccINT 1 5V DDR3 SDRAM Target FPGA memory I O 1 8V Flash Memorv DC DC converters for GTX Supplies 2 5V FPGA Auxilliarv Supplv VccAUX XRM VIO XRM Front Panel I O voltage 3 3V Board Input Supply 5 0V Internally generated 5V supply VPWR Board Input Supply either 5 0V or 12 0V Temp1 Target FPGA on die temperature Temp2 LM87 on die temperature Table 3 10 Voltage and Temperature Monitors An example application that reads the system monitor svsmon is available on request 3 6 1 Automatic Temperature Monitoring At power up the control logic sets temperature limits and enables the over temperature interrupt in the LM87 If the One Time Configuration OTC function is disabled using SW1 5 see Table 3 1 the limits and interrupt will be re set after a board reset MRSTI If OTC is enabled the limits and interrupt will only be set once at power up The t

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