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MVME167 Single Board Computer User`s Manual

1. Printer ACK Interrupt Control Register FFF42030 BIT 31 30 29 28 27 26 25 24 NAME PLTY INT IEN ICLR IL2 IL1 ILO Printer FAULT Interrupt Control Register FFF42031 BIT 23 22 21 20 19 18 17 16 NAME PLTY INT IEN ICLR IL2 IL1 ILO Printer SEL Interrupt Control Register FFF42032 BIT 15 14 13 12 11 10 9 8 NAME PLTY INT IEN ICLR IL2 IL1 ILO Printer PE Interrupt Control Register FFF42033 BIT 7 6 5 4 3 2 1 0 NAME PLTY INT IEN ICLR IL2 IL1 ILO Printer Interrupt Control Register FFF42034 BIT 31 30 29 28 27 26 25 24 NAME PLTY INT IEN ICLR IL2 IL1 ILO Printer Input Status Register FFF42036 BIT 15 14 13 12 11 10 9 8 NAME PLTY ACK FLT SEL PE BSY Printer Port Control Register FFF42037 BIT 7 6 5 4 3 2 1 0 NAME DOEN INP STB FAST MAN Printer Data Register 16 bits FFF4203A BIT 15 0 NAME PD15 PDO 3 16 167 Single Board Computer User s Manual Memorv Maps Table 3 6 040 Internal Register Memorv Map 2nd Ist Data Bits 40 40 D31 D30 D29 D28 D27 D26 D25 D24 FFF43100 FFF43000 CID7 5 CID4 CID3 CID2 CIDI CIDO FFF43104 FFF43004 REV7 REV6 REVS REV4 REV3 REV2 REVI REVO FFF431
2. D15 D8 D7 DO CPU MSTR FAST DRO 040 BRAM VECTOR BASE REGISTER EN COMPARE REGISTER COUNTER REGISTER COMPARE REGISTER COUNTER REGISTER OVERFLOW EE OVERFLOW COUNTER 2 b 2 5 COUNTER 1 h TIC2 TIC2 TIC2 2 TIC TIMER 1 INT IEN IRQ LEVEL INT IRQ LEVEL eee ae SCC TRANSMIT scc scc a i pus SCC RECEIVE IRQ AVEC IRQ LEVEL 801 500 Ra ten avec IRQ LEVEL SCC MODEM PIACK SCC RECEIVE PIACK re LAN LAN LAN LAN INT LAN LAN u LAN ERR INT IRQ LEVEL Sei SCO ER IRQ LEVEL scsi scsi SCSI INT IRQ IEN IRQ LEVEL PRTR ER PRTR PE SEL SEL SEL SEL SEL IRG EVE PE PE PE PE PE IRQ LEVEL PLIV INT IEN INT JEN ICLR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR PRTR ANY ACK FLT SEL PE BSY DAT INP FAST MAN INT ENBL ASTB STB PRINTER DATA INTERRUPT INTERRUPT IPL LEVEL MASK LEVEL 1362 9403 This sheet begins on facing page MVME167 D3 3 15 Operating Instructions Table 3 5 Printer Memorv Map
3. P4 P5 J4 J5 SHEET 8 SHEET7 SHEET 6 ys BBRAM AND TOD SHEET 23 MEZZANINE SERIAL PORT SERIAL SHEETS 24 26 PCCCHIP2 SHEET 21 MC68040 MPU SHEET 27 EEDEN PRINTER SHEET 22 SCSI INTERFACE SCSI SHEET 18 IPL COMBINER SHEET 28 LANCE SIA LAN SHEET 19 SHEET 20 VMECHIP2 VME BUFFERS CLOCKS VME GENERATOR SHEET 12 SHEETS 13 15 BI J3 SHEET 10 SHEET 5 SHEET 20 SRAMS AND BATTERY BACKUP EPROMS SWITCHES SHEETS 16 17 REMOTE SHEETS RESET ABORT LEDS 1473 9405 Figure 4 1 MVME167 Main Module Block Diagram 4 10 MVME167 Single Board Computer User s Manual 167 Functional Description CONNECTOR SHEET 5 CONNECTORS SHEET 4 1 ADDRESS BUS DATA BUS ADDRESS MUX SHEET 7 DATA MUX SHEET 13 14 1 TIMING CONTROL SHEET 6 Y ACKNOWLEDGE CONTROL SHEET 15 MULTIPLEXED ADDRESS RDA BUS RDB BUS RDC BUS RDD BUS PARITY DATA DRAM STROBES MEMORY ARRAY BANKA SHEET 8 MEMORY ARRAY BANK B SHEET 9 MEMORY ARRAY BANK C SHEET 10 MEMORY ARRAY BANK D SHEET 11 PARITY MEMORY SHEET 12 10887 00 9401 Figure 4 2 Parity DRAM Mezzanine Module Block Diagram MVME167 D3 4 11 Functional Description 1076 0058801 viel 133HS 52078 WVHQ
4. 9 A 2 xiii xiv GENERAL INFORMATION Introduction This manual provides general information preparation for use and installation instructions operating instructions and functional description for the MVME167 series of Single Board Computers referred to as MVME167 throughout this manual Model Designations The 167 is available in several models which are listed in Table 1 1 MVME167 Model Designations on page 1 1 Table 1 1 MVME167 Model Designations Model Number Speed Major Differences MVME 67 001B was MVME167 01 or 001A 25MHz 4MB Onboard Parity DRAM MVME 167 002B was MVME167 02 or 002A 25MHz 8MB Onboard Parity DRAM MVME167 003B was MVME167 03 or 003A 25MHz 16MB Onboard Parity DRAM MVME167 004B was MVME167 04 or 004A 25MHz 32MB Onboard Parity DRAM MVME 67 031B was 167 31 or 031A 33 MHz 4MB Onboard ECC DRAM MVME167 032B was MVME167 32 or 032A 33 MHz 8MB Onboard ECC DRAM MVME167 033B was MVME167 33 or 033A 33 MHz 16MB Onboard ECC DRAM MVME167 034B was MVME167 34 or 034A 33 MHz 32MB Onboard ECC DRAM MVME167 035B was MVME167 035A 33 MHz 64MB Onboard ECC DRAM MVME167 036B was MVME167 036A 33 MHz 128MB Onboard ECC DRAM MVME167 D31 1 General Information Features Features of the 167 are listed below U U L B tl LLD DI MC68040 Microprocessor at 25 M
5. 412V CONNECTOR 1508 r TO 22 L _ TERMINAL CTS eccL 5 OPTIONAL DER 6 5 HARDWARE DCD 5 TRANSPARENT y GEE SIG GND 5 isdie CHASSIS GND RXC e LS08 GND ENDE UT 12V EA RD SIG GND zy 7777 222 sed ba 1 7 7 4700 NC lt 1 DTR 20 6850 EE TXD 2 TXD RXD 3 m CONNECTOR 12v L MODEM Bic RTS OR gt X 4506 SVSTEM 12V u E s Cd 39ko WV 42V AA F Oo _ DCD DCD A 6 9 TXC 12V MODULE cb181 9210 4 MVME167 Single Board Computer User s Manual Levels of Implementation A Figure A 2 shows a wav of wiring an EIA 232 D connector to enable a computer to connect to a basic terminal with only three lines This is feasible because most terminals have a DTR signal that is ON and which can be used to pull up the CTS DOD and DSR signals Two of these connectors wired back to back can be used In this implementation however diagnostic messages that might otherwise be generated do not occur because all the handshaking is bvpassed In addition the TX and RX lines have to be crossed since TX from a terminal is outgoing but the TX lineon modem is an incoming signal EIA 232 D CONNECTOR GND 1 2 RxD 3 5 4 CTS 5 DSR 6 GND 7 DCD 8 DTR 20 Figure A 2 Minimum EIA 232 D Connection MVME167 D3 A 5 A EIA 232 D Interconnections
6. se ee ee Re AA eene nnne nennen nennen en 3 1 ABORT Switch 81 ena ae RI enne te ir bleed 3 1 RESET Switch 92 edente eee eet 3 1 Front Panel Indicators DS1 054 00442222 0 3 2 Memory Maps tee p eat SE Ete eet 3 3 Local Bus Memory 3 3 vii Normal Address Range 3 3 Detailed VO Memory Maps 3 6 BBRAM TOD Clock Memory eene enne 3 26 Interrupt Acknowledge 3 28 VMEbus Memory 3 29 VMEbus Accesses to the Local Bus 3 29 VMEbus Short I O Memory ee ee 3 29 Software Initialization AE un ete EE OE OE 3 30 Multi MPU Programming Considerations eene 3 30 Local Reset Operation oii e EE tpe 3 30 4 FUNCTIONAL DESCRIPTION Introduction aot id ttt toten ten eee ENT 4 1 MVME167 Functional 4 1 Data wee ses er je pe OE Pe Ge 4 1 MC68040 MPU EE RE EE OE OE RA 4 2 EPROM SE Sa OE e ES N ER REUS 4 2 ORA A i a ta A EO RUE 4 2 Onboard eere S a es 4 3 Battery Backed Up RAM and Clock nee nn sen Re nee 4 4 MMEDUS Interface
7. 4 4 I O Interfaces 4 5 Serial Port Interface ku un aec ec e S hamunay 4 5 Parallel Port seen u RS 4 6 Ethernet Interface diee ec rer Rees 4 6 SCSI Interface EROPd eee pied aet iae 4 7 SEST Termination dette ees 4 7 Resources in e ne Ran REA RD ERR 4 7 Programmable Tick Timers 5 sesse terree s ee ene EU Cg 4 7 Watchdog Timer eee ete Si a ae 4 8 Software Programmable Hardware Interrupts esee 4 8 Local Bus Timeout isse e ea er EA a GR EE GEE ER EG De ee a ee ee ende 4 8 Timing Performance A 4 8 Local Bus to DRAM Cycle Times eese 4 8 ROM Cycle Times serene ee fede dro 4 0 SCSI Transfers eee Rn EO EO EO ed SQ 4 9 LAN DMA Transfers Ee RU E eor ERES 4 9 Remote Status and Control a 4 10 viii APPENDIXA EIA 232 D INTERCONNECTIONS Inttodu tioni 1 Levels of Implementation A 3 Signal Adaptations A 3 Sample Configurations A 4 Proper Grounding A eg s A 6 List of Figures Figure 2 1 MVME167 Switches Headers Connectors Fuses and LEDs 2 3 Figure 4 1 MVME167 Main Module Block Diagram eee 4 11 Figure 4 2 Parity DRA
8. ZFILL RWCKB 0 0 0 24 SCRUB CONTROL RACODE RADATA HITDIS SCRB SCRBEN 0 SBEIEN IDIS 28 SCRUB PERIOD SBPD15 SBPD14 SBPD13 8 12 SBPDII SBPD10 SBPD9 SBPDS 2C SCRUB PERIOD SBPD7 SBPD6 SBPD5 SBPD4 SBPD3 SBPD2 SBPDI SBPDO 30 CHIP PRESCALE CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPSO 34 SCRUB TIME ON OFF SRDIS 0 STON2 STONI STONO STOFF2 STOFFI STOFFO 38 SCRUB PRESCALE 0 0 SPS21 SPS20 SPS19 SPS18 SPS17 SPS16 3C SCRUB PRESCALE SPSI5 SPS14 SPSI3 5 512 SPS11 5 510 5 59 5 58 540 SCRUB PRESCALE SPS7 SPS6 5 55 5 54 SPS3 SPS2 SPSI SPSO 44 SCRUB TIMER STI5 ST14 ST3 ST12 STII STIO 519 ST8 48 SCRUB TIMER ST7 ST6 ST5 STA ST3 ST2 STI STO SCRUB ADDR CNTR 0 0 0 0 0 SAC26 SAC25 SAC24 50 SCRUB ADDR CNTR SAC23 SAC22 SAC21 SAC20 SACI9 SACI8 SACI7 SACI6 54 SCRUB ADDR CNTR SACIS SACIA SACI2 SACII SACIO SAC9 SAC8 58 SCRUB ADDR CNTR SAC7 SAC6 5 0 0 0 0 5C ERROR LOGGER ERRLOG ERD ESCRB ERA EALT 0 MBE SBE 60 ERROR ADDRESS EA31 EA30E EA29 EA28 EA27 EA26 EA25 EA24 64 ERROR ADDRESS EA23 EA22 EA21 EA20 EA19 EA18 EA17 16 68 ERROR ADDRESS 15 14 EA13 EA12 10 9 8 6C ERROR ADDRESS EA7 EA6 EAS5 EA4 0 0 0 0 70 ERROR SYNDROME S7 S6 S5 54 53 52 51 50 74 DEFAULTSI WRHDIS STATCOL FSTRD SELII SELIO RSIZ2 RSIZI RSIZO 78 DEFAULTS2 XY FLIP REFDIS NOCACHE RESST2 RESSTI RESSTO 3 18
9. operating instructions 3 1 operating svstems l 6 P P2 adapter board l 5 2 7 2 8 parallel port interface 4 6 parallel printer port 4 6 paritv DRAM mezzanine module block diagram 4 12 PCCchip2 1 5 PCCchip2 memorv map 3 14 printer interface 4 6 printer memorv map 3 16 printer port 4 6 programmable hardware interrupts 4 8 programmable tick timers 4 7 proper grounding A 6 R registers 3 30 default values 3 30 related documentation l 7 remote status and control J3 4 10 RESET switch S2 3 1 3 30 RF emissions l 5 RFI 2 7 times 4 9 Receive Transmit Clock 4 2 4 5 S1 3 1 52 3 1 3 30 sample configurations A 4 SCC Serial Controller Chip see CD2401 4 5 SCSI Controller see 53C710 4 7 SCSI FIFO buffer 4 9 SCSI ID see local SCSI ID 3 28 SCSI interface 4 7 SCSI specification 1 8 SCSI termination 4 7 SCSI terminator power 2 8 SCSI transfers 4 9 Serial Controller Chip SCC see CD2401 4 5 serial port 4 2 4 serial port 4 clock configuration select headers J6 and J7 2 4 serial port interface 4 5 MVME167 Single Board Computer User s Manual shielded cables see also cables 1 4 2 7 signal adaptations A 3 signal ground A 6 signal levels A 1 signals transfer type 3 3 software initialization 3 30 software programmable hardware inter rupts 4 8 specifications l 3 SRAM static RAM 4 2 SRAM backup power source select head er J8 2 5 SRAM batterv backu
10. 2 6 3 1 3 30 53C710 see SCSI Controller 4 7 53C710 SCSI memorv map 3 24 82596CA see Ethernet and LAN 4 6 82596CA Ethernet LAN memorv map 3 23 ABORT switch interrupter 3 1 ABORT switch 51 3 1 adapter board see P2 adapter board 1 5 2 7 ambient air temperature l 3 assembler disassembler 1 6 assertion l 9 B Batterv Backed Up RAM BBRAM and Clock see MKA8TOS NVRAM 4 4 batterv backup 4 2 batterv handling and disposal 4 3 batterv lifetime 4 3 BBRAM see Batterv Backed Up RAM MK48T08 and NVRAM 3 26 4 4 BBRAM configuration area memory map 8 25 BBRAM TOD Clock memorv map 3 26 BG bus grant 2 7 big endian mode 3 24 binarv number 1 9 block diagram ECC DRAM mezzanine module 4 13 MVME167 main module 4 11 paritv DRAM mezzanine module 4 12 board ID 3 27 board serial number 3 27 board speed 3 28 bus error 3 30 bus grant BG 2 7 byte 1 9 C cables see also shielded cables 2 7 CD2401 see SCC and Serial Controller Chip 4 5 CFM cubic feet per minute 1 3 chassis ground A 6 checksum 3 28 Cirrus Logic CD2401 serial port memory map 3 19 conductive chassis rails 1 4 configuration area 3 26 controls and indicators 3 1 cooling requirements 1 3 CR2430 4 2 cubic feet per minute CFM 1 3 cycle times 4 8 localbus to DRAM 4 8 ROM 4 9 MVME167 D3IN 1 xm z Index D data bus structure 4 1 data circuit terminating DCE A 1 data terminal equipment DTE A 1 D
11. 2C GCSR GROUP SELECT BOARD SELECT a Ed E i 31 30 29 25 24 23 22 21 20 19 18 17 16 WAIT ROM DMA TB SRAM 30 RMW ZERO SNP MODE SPEED 34 38 DMA CONTROLLER 3C DMA CONTROLLER 40 DMA CONTROLLER 44 DMA CONTROLLER TICK TICK CLR IRQ VMEBUS 48 gt 2 1 p IRQ STAT INTERRUPT VMEBUS INTERRUPT VECTOR LEVEL This sheet continues on facing page gt 3 8 167 Single Board Computer User s Manual Memorv Maps 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2 SLAVE ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 ADDER SNP WP SUP usr BEK PRGM DATA 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MASTER STARTING ADDRESS 1 MASTER STARTING ADDRESS 2 MASTER STARTING ADDRESS 3 MASTER STARTING ADDRESS 4 MASTER ADDRESS TRANSLATION SELECT 4 MAST MAST MAST MAST D16 WP MASTER AM 2 016 WP MASTER AM 1 EN EN EN EN io2 102 i2 02 101 0 ROM ROM BANK B ROM BANK EN WP SU PD EN Die WP SU SIZE SPEED SPEED EN EN EN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAST MAST MST MST MASTER DMA DMA DMA DMA DM DMA ROBN DHB DWB FAIR RWD VMEBUS HALT EN TBL FAR RELM VMEBUS DMA DMA LB DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA TBL IN
12. 3 Receive RTXC4 Receive TRXC4 Factorv Configurations J6 J7 1 1 3 3 Drive RTXC4 Drive 4 2 4 MVME167 Single Board Computer User s Manual Hardware Preparation SRAM Backup Power Source Select Header J8 Header J8 is an optional header that is used to select the power source used to back up the SRAM on the MVME167 if the optional battery and circuitrv is present J8 J8 J8 4 4 4 HE SI 3 2 1 3 2 1 3 2 1 Backup Power Disabled VMEbus 5V STBY Optional Battery Factory Configuration when Optional Battery Is Present i Do not remove all jumpers from J8 This mav disable the Caution SRAM If vour board contains the optional header J8 but the optional battery is removed jumpers must installed on 8 between pins 2 and 4 as shown in the Backup Power Disabled drawing above MVME167 D3 2 5 Hardware Preparation and Installation Installation Instructions The following sections discuss installation of the MVME167 into VME chassis and svstem considerations Ensure that EPROM devices are installed as needed Factorv configuration is with two EPROMs installed for the MVME167Bug debug monitor in sockets XU1 and XU2 Ensure that all header jumpers are configured as desired MVME167 Module Installation Now t
13. 8 167 Single Board Computer User s Manual OPERATING INSTRUCTIONS Introduction This chapter provides necessarv information to use the MVME167 module in a svstem configuration This includes controls and indicators memorv maps and software initialization of the module Controls and Indicators The MVME167 module has ABORT and RESET switches and FAIL STAT RUN SCON LAN 12V LAN power SCSI and VME indicators all located on the front panel of the module ABORT Switch S1 When enabled by software the front panel ABORT switch generates an interrupt at a user programmable level It is normally used to abort program execution and return to the 167Bug debugger firmware located in the MVME167 EPROMs The ABORT switch interrupter in the VMEchip2 is an edge sensitive interrupter connected to the ABORT switch This interrupter is filtered to remove switch bounce RESET Switch S2 The front panel RESET switch resets all onboard devices and drives SYSRESET if the board is svstem controller The RESET switch mav be disabled bv software The VMEchip2 includes both a global and a local reset driver When the chip operates as the VMEbus svstem controller the reset driver provides a global svstem reset bv asserting the VMEbus signal SYSRESET A SYSRESET be generated the RESET switch a power up reset a watchdog timeout or a control bit in the LCSR SYSRESET remains asserted for at least 200 msec as req
14. MVME167 Single Board Computer User s Manual Memorv Maps Table 3 8 Cirrus Logic CD2401 Serial Port Memorv Map Base Address 5 45000 Register Description Offsets Size Access Global Registers Global Firmware Revision Code Register GFRCR 81 B R Channel Access Register CAR EE R W Option Registers Channel Mode Register CMR 1B B R W Channel Option Register 1 CORI 10 B R W Channel Option Register 2 COR2 17 B R W Channel Option Register 3 COR3 16 B R W Channel Option Register 4 15 B R W Channel Option Register 5 5 14 R W Channel Option Register 6 COR6 18 B R W Channel Option Register 7 COR7 07 B R W Special Character Register 1 SCHRI IF B R W Asvnc Special Character Register 2 SCHR2 IE B R W Asvnc Special Character Register 3 SCHR3 ID B R W Asvnc Special Character Register 4 SCHR4 IC B R W Asvnc Special Character Range low SCRI 23 B R W Asvnc Special Character Range high SCRh 22 B R W Asvnc LNext Character LNXT 2E B R W Asvnc Bit Rate and Clock Option Registers Receive Frame Address Registerl RFARI IF B R W Sync Receive Frame Address Register2 RFAR2 IE B R W Svnc Receive Frame Address Register3 RFAR3 ID B R W Sync Receive Frame Address Register4 RFAR4 IC B R W Svnc CRC Polvnomial Select Register CPSR D6 B R W Svnc Baud Rate Period Register RBPR CB B R W Receive Clock Option Regis
15. areas are defined bv software while the sixth area the time of dav TOD clock is defined bv the chip hardware The first area is reserved for user data The second area is used bv Motorola networking software The third area is used bv the SYSTEM V 68 operating system The fourth area is used by the MVME 167 board debugger MVME167Bug The fifth area detailed in Table 3 12 BBRAM Configuration Area Memory Map on page 3 25 is the configuration area The sixth area the TOD clock detailed in Table 3 13 TOD Clock Memory Map on page 3 26 is defined by the chip hardware The data structure of the configuration bytes starts at SFFFCIEFS and is as follows struct brdi cnfg char version 4 char serial 12 char id 16 char 16 char speed 4 char ethernet adr 6 char 1411121 char lscsiidIi2 char sysid 8 char pwb 8 char brdl serial 8 3 26 167 Single Board Computer User s Manual Memorv Maps char brd2 pwb 8 char brd2 serial 8 char reserved 153 char cksum 1 The fields are defined as follows 1 Four bytes are reserved for the revision or version of this structure This revision is stored in ASCII format with the first two bytes being the major version numbers and the last two bytes being the minor version numbers For example if the version of this structure is 1 0 this field contains 0100 Twelve bytes are reserved for the serial number
16. is available to the transceiver interface The green SCSI LED part of DS4 lights when the SCSI chip is local bus master The green VME LED part of DS4 lights when the board is using the VMEbus VMEbus AS is asserted by the VMEchip2 or when the board is accessed by the VMEbus VMEchip2 is the local bus master 167 Single Board Computer User s Manual Memorv Maps Memorv Maps There are two points of view for memory maps 1 the mapping of all resources as viewed by local bus masters local bus memory map and 2 the mapping of onboard resources as viewed bv VMEbus Masters VMEbus memorv map Local Bus Memorv Map The local bus memorv map is split into different address spaces bv the transfer tvpe TT signals The local resources respond to the normal access and interrupt acknowledge codes Normal Address Range The memory map of devices that respond to the normal address range is shown in the following tables The normal address range is defined bv the Transfer Tvpe TT signals on the local bus On the 167 Transfer Types 0 1 and 2 define the normal address range Table 3 1 Local Bus Memory is the entire map from 00000000 to FFFFFFFF Many areas of the map user programmable and suggested uses are shown in the table The cache inhibit function is programmable in the MMUs onboard VO space must be marked cache inhibit and serialized in its page table Table 3 2 Local VO Devi
17. is contrarv to specifications A 2 MVME167 Single Board Computer User s Manual Levels of Implementation A 2 The EIA 232 D interface is intended to connect a terminal to a modem When computers are connected without modems one must be configured as a modem and the other as a terminal Levels of Implementation There are several levels of conformance that mav be appropriate for tvpical EIA 232 D interconnections The bare minimum requirement is the two data lines and a ground The full implementation of EIA 232 D requires 12 lines it accommodates automatic dialing automatic answering and svnchronous transmission A middle of the road approach is illustrated in Figure A 1 Signal Adaptations One set of handshaking signals freguently implemented are RTS and CTS CTS is used svstems to inhibit transmission until the signal is high In the modem application RTS is turned around and returned as CTS after 150 microseconds RTS is programmable in some svstems to work with the older tvpe 202 modem half duplex CTS is used in some svstems to provide flow control to avoid buffer overflow This is not possible if modems are used It is usually necessary to make CTS high by connecting it to RTS or to some source of 12 volts such as the resistors shown in Figure A 1 CTS is also frequently jumpered to an MC1488 gate which has its inputs grounded the gate is provided for this purpose Another signal used in many system
18. of the board in ASCII format For example this field could contain 000000470476 Sixteen bytes are reserved for the board ID in ASCII format For example for a 16 MB 25 MHz MVME167 board this field contains MVME167 003B The 12 characters are followed by four blanks Sixteen bytes are reserved for the printed wiring assembly PWA number assigned to this board in ASCII format This includes the 01 w prefix This is for the main logic board if more than one board is required for a set Additional boards in a set are defined by a structure for that set For example for a 16 MB 25 MHz MVMEI67 board at revision A the PWA field contains 01 W3899B03A The 12 characters are followed by four blanks Four bytes contain the speed of the board in MHz The first two bytes are the whole number of MHz and the second two bytes are fractions of MHz For example for a 25 00 MHz board this field contains 2500 Six bytes are reserved for the Ethernet address The address is stored in hexadecimal format Refer to the detailed description in Chapter 4 If the board does not support Ethernet this field is filled with zeros These two bytes are reserved Two bytes are reserved for the local SCSI ID The SCSI ID is stored in ASCII format Eight bytes are reserved for the systems serial ID for boards lused a system MVME167 D3 Operating Instructions 10 Eight bytes are reserved for the printed wiring board PWB num
19. timer is enabled the access times out and is terminated by a TEA signal Detailed VO Memory Maps Tables 3 3 through 3 13 give the detailed memory maps for 3 3 VMEchip2 3 9 82596CA Ethernet chip 3 4 PCCchip2 3 10 53 710 SCSI chip 3 5 Printer 3 11 8 8 BBRAM TOD clock 3 6 040 memory controller chip 3 12 BBRAM configuration area 3 7 MCECC memory controller chip 3 13 TOD clock 3 8 CD2401 serial chip Note Manufacturers errata sheets for the various chips are available by contacting your local Motorola sales representative A non disclosure agreement may be required 3 6 167 Single Board Computer User s Manual Memorv Maps This page intentionally left blank MVME167 D3 3 7 Operating Instructions Table 3 3 VMEchip2 Memory Map Sheet 1 of 3 VMEchip2 LCSR Base Address FFF40000 OFFSET i 0 SLAVE ENDING ADDRESS 1 4 SLAVE ENDING ADDRESS 2 8 SLAVE ADDRESS TRANSLATION ADDRESS 1 SLAVE ADDRESS TRANSLATION ADDRESS 2 ADDER SNP WP SUP usr 2 24 PRGM DATA 10 PY seisi TA 2 5 5 2 2 2 2 2 2 s 14 MASTER ENDING ADDRESS 1 18 MASTER ENDING ADDRESS 2 1C MASTER ENDING ADDRESS 3 20 MASTER ENDING ADDRESS 4 24 MASTER ADDRESS TRANSLATION ADDRESS 4 MAST MAST MAST MAST 28 016 WP MASTER 4 D16 WP MASTER AM 3 EN EN EN EN GCSR MAST MAST MAST MAST
20. 08 FFF43008 FSTRD EXTPEN WPB MSIZ2 MSIZ1 MSIZO FFF4310C FFF4300C STS7 STS6 STS5 STS4 STS3 STS2 STSI STSO SFFF43110 FFF43010 OUT7 0076 OUTS OUTA OUT3 our OUTI OUTO SFFF43114 FFF43014 BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 SFFF43118 FFF43018 BAD23 BAD22 DMCTL SWAIT WWP PARINT PAREN RAMEN FFF4311C FFF4301C BCK7 BCK6 BCK5 BCK3 BCK2 BCKI BCKO Table 3 7 MCECC Internal Register Memory Map MCECC Base Address FFF43000 1st FFF43100 2nd Register Register Register Bit Names Offset Name D31 D30 027 D26 025 D24 00 CID7 CIDS CID5 CID4 CIDO 04 CHIP REVISION REV7 REV6 REVS 4 REV3 2 REVI REVO 08 MEMORY CONFIG 0 0 FSTRD 1 0 MSIZ2 MSIZI 5170 0C DUMMY 0 0 0 0 0 0 0 0 0 10 DUMMY 1 0 0 0 0 0 0 0 0 14 BASE ADDRESS BAD31 BAD30 29 BAD28 BAD27 BAD26 BAD25 BAD24 18 DRAM CONTROL BADO3 BAD22 RWBS SWAIT RWB3 NCEIEN NCEBEN RAMEN IC BCLKFREQUENCY BCK7 BCK6 5 BCK4 BCK3 BCK2 BCKO MVME167 D3 3 17 Operating Instructions Table 3 7 MCECC Internal Register Memorv Map Continued Base Address FFF43000 1st 43100 2nd Register Register Register Bit Names Offset Name D31 D30 po 028 027 26 025 D24 20 DATA CONTROL 0 0 DERC
21. 1 to the pin labeled RTS at connector P2 Likewise RTS from the CD2401 is tied to DTR on P2 Therefore when programming the CD2401 assert DTR when you want RTS and RTS when you want DTR The interface provided by the PCCchip2 allows the 16 bit CD2401 to appear at contiguous addresses however accesses to the CD2401 must be 8 or 16 bits 32 bit accesses are not permitted Refer to the CD2401 data sheet and to the PCCchip2 in the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide for detailed programming information The CD2401 supports DMA operations to local memory Because the CD2401 does not support a retry operation necessary to break VMEbus lockup conditions the CD2401 DMA controllers should not be programmed to access the VMEbus The hardware does not restrict the CD2401 to onboard DRAM Parallel Port Interface The PCCchip2 provides an 8 bit bidirectional parallel port eight bits of the port must be either inputs or outputs no individual selection In addition to the 8 bits of data there are two control pins and five status pins Each of the status pins can generate an interrupt to the MPU in any of the following programmable conditions high level low level high to low transition or low to high transition This port may be used as a Centronics compatible parallel printer port or as a general parallel I O port When used as a parallel printer port the five status pins function as Printer Acknow
22. 3 131 198X Revision 10c Global Engineering Documents P O Box 19539 Irvine CA 92714 CL CD2400 2401 Four Channel Multi Protocol Communications Controller Data Sheet order number 542400 003 Cirrus Logic Inc 3100 West Warren Ave Fremont CA 94538 82596 Local Area Network Coprocessor Data Sheet order number 290218 and 82596 User s Manual order number 296853 Intel Corporation Literature Sales P O Box 58130 Santa Clara CA 95052 8130 NCR 53C710 SCSI I O Processor Data Manual order number NCR53C710DM and NCR 53 710 SCSI Processor Programmer s Guide order number NCR53C710PG Corporation Microelectronics Products Division Colorado Springs CO MKASTOS B Timekeeper TM 8 8 Zeropower TM RAM data sheet in Static RAMs Databook order number DBSRAM71 SGS THOMPSON Microelectronics Group North amp South American Marketing Headquarters 1000 East Bell Road Phoenix AZ 85022 2699 Support Information The SIMVME 167 manual contains the connector interconnect signal information parts lists and the schematics for the MVME167 This manual may be obtained free of charge by contacting your local Motorola sales office l 8 MVME167 Single Board Computer User s Manual Manual Terminologv Manual Terminology Throughout this manual a convention is used which precedes data and address parameters by a character identifying the numeric format as follows dollar specifies a hexadecimal chara
23. 40 28 1 6 XU4 2 SKT 39 29 40 28 9 SKT 6 18 7 17 39 29 40 28 MEZZANINE BOARD 2 xu2 4 6 18 J8 21 29 OPTIONAL 2 J1 16 J4 J5 1 15 59 S1 52 20 2 19 J3 A DS4 PRIMARV SIDE COMPONENTS ARE REMOVED FOR CLARITY MVME 167 FAIL HALT RUN SCON SCSI VME LAN 12V MOTOROLA 1379 9404 2 3 Figure 2 1 MVME167 Switches Headers Connectors Fuses and LEDs MVME167 D3 Hardware Preparation and Installation Serial Port 4 Clock Configuration Select Headers J6 and J7 Serial port 4 can be configured to use clock signals provided by the and TRXCA signal lines Headers J and J7 on the 167 configure serial port 4 to drive or receive RTXC4 and TRXCA respectively Factory configuration is with port 4 set to receive both signals The remaining configuration of the clock lines is accomplished using the Serial Port 4 Clock Configuration Select header on the MVME712M transition module Refer to the 712 Transition Module and MVME147P2 Adapter Board User s Manual for configuration of that header J6 J7 1 1 3
24. 5 BBRAM TOD Clock 3 26 Cirrus Logic CD2401 serial port 3 19 detailed I O 3 6 interrupt acknowledge 3 28 local bus 3 3 local I O devices 3 5 MCECC internal register 3 17 040 internal register 3 17 8 8 TOD Clock 3 25 PCCchip2 3 14 printer 3 16 TOD clock 3 26 VMEbus 3 29 VMEbus short I O 3 29 VMEchip2 3 8 mezzanine module ECC DRAM 4 13 paritv DRAM 4 12 middle of the road EIA 232 D configu ration A 4 minimum EIA 232 D connection A 5 MK48T08 see Battery Backed Up RAM BBRAM and NVRAM 4 4 MKA8TO8 BBRAM TOD Clock memory map 3 25 model designations 1 1 modem s A 1 MVME167 D3 IN 3 xm z Index multi MPU programming consider ations 3 30 MVME167 functional description 4 1 MVME167 main module block diagram 4 11 MVME167 model designations 1 1 MVME167 module installation 2 6 MVME167 specifications 1 4 MVME167 switches headers connec tors fuses and LEDs 2 3 MVME167Bug see 167Bug and debug monitor 1 6 2 2 2 6 3 1 3 30 MVME167Bug debug monitor 1 6 MVME167Bug debugging package 1 7 MVME712 12 1 5 MVME712 13 1 5 MVME712A 1 5 MVME712AM 1 5 MVME712B 1 5 MVME712M 1 5 2 6 2 8 MVMEZ12X 1 6 2 6 4 5 N negation 1 9 Non Volatile RAM NVRAM see Bat tery Backed Up RAM BBRAM and 48708 3 26 4 4 normal address range 3 3 NVRAM Non Volatile RAM see Bat terv Backed Up RAM BBRAM and 48708 3 26 4 4 onboard DRAM 4 3
25. 5 24 23 22 21 20 19 18 17 16 70 CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR 74 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 78 AC FAIL ABORT SVS FAIL MST WP ERROR IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL VME IACK DMA SIG 3 SIG 2 7C IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 80 SW7 SW6 SW5 SW4 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 84 SPARE VME IRQ 7 VME IRQ 6 VME IRQ 5 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 88 VECTOR BASE VECTOR BASE ae A ABORT GPIOEN REGISTER 0 REGISTER 1 EN LEVEL LEVEL LEVEL 8C This sheet continues on facing page 3 10 167 Single Board Computer User s Manual Memorv Maps 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOCAL WD ACCESS BUS TIME OUT PRESCALER TIMER TIMER SELECT CLOCK ADJUST COMPARE REGISTER COUNTER COPARE REGISTER COUNTER OVERFLOW Ja le OVERFLOW ed IE ee COUNTER 2 5 2 COUNTER 1 j i i SCALER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SW7 swe sws sw4 swa Swe Swi swo sPARE IRQ IRQ IRQ IRQ IRQ IRQ IRQ7 IRQ6 IRQS maa mas IRQ2 Rat EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN IRQ IRQ IRQ IRQ IRQ IRQ IRQ
26. 87 Single Board Computers Programmer s Reference Guide for detailed programming information Software Programmable Hardware Interrupts Eight software programmable hardware interrupts are provided by the VMEchip2 These interrupts allow software to create a hardware interrupt Refer to the VMEchip2 in the MVME166 MVME167 MVME187 Single2 ngl 5 e ruptstc upts 6 6 tcnrT O 2 960 05 MVME167 D3 4 7 Functional Description bound cycles VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer Refer to the VMEchip2 in the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide for detailed programming information Timing Performance This section provides the performance information for the MVME167 Various MVME167s are designed to operate at 25 MHz or 33 MHz Local Bus to DRAM Cvcle Times The PCCchip2 and VMEchip2 have the same local bus interface timing as the MC68040 therefore the following cycle times also apply to the PCCchip2 and the VMEchip2 Read accesses to onboard DRAM require 4 bus clock cycles with parity checking off With parity checking on and the bus error reported in the current cycle 5 bus clock cycles are required Write accesses to onboard DRAM require 2 bus clock cycles Burst read accesses require 7 4 1 1 1 bus clock cycles with parity check off With parity checking on and the bus error reported in the current cycle 8 5 1 1 1 bus clock cycles are
27. C INC Di AM AM AM AM AM AM INT VME LB BLK 5 4 3 2 1 0 LOCAL BUS ADDRESS COUNTER VMEBUS ADDRESS COUNTER BYTE COUNTER TABLE ADDRESS COUNTER ER MPU MPU MPU MPU MPU DMA DMA DMA DMA DMA CLR LBE LPE LOB LTO LBE LPE LOB LTO DONE INTERRUPT COUNT STAT ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR 1360 9403 lt This sheet begins on facing page MVME167 D3 Operating Instructions Table 3 3 VMEchip2 Memorv Map Sheet 2 of 3 VMEchip2 LCSR Base Address FFF40000 OFFSET 31 30 29 28 27 26 25 24 28 22 21 20 19 18 17 16 ARB VME DMA DMA BGTO 4C EN TIME OFF TIME ON MER 50 TICK TIMER 1 54 TICK TIMER 1 58 TICK TIMER 2 5C TICK TIMER 2 SCON SYS BRD PURS BRD RST SYS WD WD WD TO WD WD WD 60 FAIL FAIL STAT PURS FAIL sw RST CLR CLR TO BF SRST RST STAT STAT OUT EN TO CNT STAT EN LRST EN EN 64 PRE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AG AB SYS MWP 2 VME DMA SIG3 SIG2 SIG1 SIGO LM1 LMO 68 FAIL IRQ FAIL BERR IRQ IRQ IRQ IRQ IACK IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN 6C IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 31 30 29 28 27 26 2
28. CE data circuit terminating equip ment A 1 debug monitor see 167Bug and MVME167Bug 2 2 2 6 3 1 3 30 debugging package 1 7 3 30 decimal number 1 9 default values registers 3 30 detailed I O memorv maps 3 6 diagnostics 1 6 DMA 4 5 4 6 DRAM dvnamic RAM 4 3 DRAM base address 2 7 DS1 DS4 3 2 DS1210S 4 2 DTE data terminal equipment A 1 dynamic RAM DRAM 4 3 E ECC error checking and correction DRAM mezzanine module block diagram 4 13 EIA 232 D 4 5 EIA 232 D interconnections A 1 A 2 EIA 232 D standard A 1 EPROM sockets 1 6 EPROM s 2 6 3 4 3 30 4 2 equipment required 1 6 errata sheets chip 3 6 Ethernet see 82596CA and LAN 2 8 4 6 Ethernet address 3 27 3 28 Ethernet interface 4 6 Ethernet station address 4 6 Ethernet transceiver interface 4 6 extended addressing 2 7 equipment F factorv jumper settings 2 2 FCC compliance l 4 features l 2 forced air cooling l 3 front panel 3 1 front panel indicators DS1 054 3 2 functional description 4 1 fuse F1 2 8 fuse F2 2 8 G GCSR Global Control and Status Regis ters see VMEchip2 GCSR 2 8 3 30 GCSR board control register 3 30 general description l 5 general information l 1 general purpose readable jumpers on header J1 2 2 global bus timeout 2 8 Global Control and Status Registers GC SR see VMEchip2 GCSR 2 8 3 30 grounding A 6 H half duplex A 3 handshaking A 1 A 3 hardware interrupts soft
29. End Of Interrupt Register TEOIR 85 B w 3 20 MVME167 Single Board Computer User s Manual Memorv Maps Table 3 8 Cirrus Logic CD2401 Serial Port Memorv Map Continued Base Address FFF45000 Register Description Offsets Size Access Modem Interrupt Registers Modem Priority Interrupt Level Register MPILR E3 B R W Modem Interrupt Register MIR EF B R Modem Timer Interrupt Status Register MISR 8B B R Modem End Of Interrupt Register MEOIR 86 B w DMA Registers DMA Mode Register write only DMR F6 B w Bus Error Retry Count BERCNT 8E B R W DMA Buffer Status DMABSTS 19 B R DMA Receive Registers A Receive Buffer Address Lower ARBADRL 42 w R W A Receive Buffer Address Upper ARBADRU 40 w R W B Receive Buffer Address Lower BRBADRL 46 w R W B Receive Buffer Address Upper BRBADRU 44 w R W A Receive Buffer Byte Count ARBCNT 4A w R W B Receive Buffer Byte Count BRBCNT 48 w R W A Receive Buffer Status ARBSTS 4F B R W B Receive Buffer Status BRBSTS 4E B R W Receive Current Buffer Address Lower RCBADRL 3E w R Receive Current Buffer Address Upper RCBADRU 3C w R DMA Transmit Registers A Transmit Buffer Address Lower ATBADRL 52 w R W A Transmit Buffer Address Upper ATBADRU 50 w R W B Transmit Buffer Address Lower BTBADRL 56 w R W B Transmit Buffer Address Upper BTBADRU 54 w R W A Transmit Buffer Byte Count ATBCNT 5A w R W B T
30. F reserved 128 5 SFFFCFFFF MK48T08 BBRAM TOD Clock D32 D8 64KB 1 SFFFD0000 SFFFDFFFF reserved 64KB FFFE0000 SFFFEFFFF reserved 64KB 2 NOTES 1 For a complete description of the register bits refer to the data sheet for the specific chip For a more detailed memorv map refer to the following detailed peripheral device memorv maps 2 On the 167 this area does not return acknowledge signal If the local bus timer is enabled the access times out and is terminated bv a TEA signal MVME167 D3 3 5 Operating Instructions Bvte reads should be used to read the interrupt vector These locations do not respond when an interrupt is not pending If the local bus timer is enabled the access times out and is terminated bv a TEA signal Writes to the LCSR in the VMEchip2 must be 32 bits LCSR writes of 8 or 16 bits terminate with a TEA signal Writes to the GCSR may be 8 16 or 32 bits Reads to the LCSR and GCSR may be 8 16 32 bits This area does not return an acknowledge signal If the local bus timer is enabled the access times out and is terminated bv a TEA signal This area does return an acknowledge signal Size is approximate Port commands to the 82596 must be written as two 16 bit writes upper word first and lower word second The CD2401 appears repeatedly from FFF45200 to FFF45FFF on the 167 If the local bus
31. Haddn Haddn THLNO Haav 8 144HS v1va Haddn XniN 5 JOHLINOO 9 133HS Srinvdaa ZL LL 133HS 390 18 AVHUV H3MOT1 i qq IHLNO 4 133HS XNW SSaHaaav JOHLNOO ONIJIL THLNO oro 1 IHLNO HQQV 0 0 sna 1 201 0 0 S y 133HS SHOLOANNOO Figure 4 3 ECC DRAM Mezzanine Module Block Diagram 167 Single Board Computer User s Manual 4 12 EIA 232 D INTERCONNECTIONS Introduction The EIA 232 D standard is the most widelv used terminal computer and terminal modem interface and vet it is not fullv understood This mav be because not all the lines are clearly defined and many users do not see the need to follow the standard in their applications Many times designers think only of their own equipment but the state of the art is computer to computer or computer to modem operation A svstem should easilv connect to anv other EIA 232 D standard was originally developed by the Bell System to connect terminals via modems Several handshaking lines were included for that purpose Although handshaking is unnecessarv in manv applications the lines themselves remain part of many designs because they facilitate troubleshooting Table A 1 lists th
32. Hz 00X models or 33 MHz 03X models 4 8 16 32 64MB of 32 bit DRAM with parity protection or 4 8 16 32 64 128 256MB of DRAM with ECC protection Four 44 pin PLCC ROM sockets organized as two banks of 32 bits 128KB SRAM with optional battery backup Status LEDs for FAIL STAT RUN SCON LAN 12V LAN power SCSI and VME 8K by 8 RAM and time of day clock with battery backup RESET and ABORT switches Four 32 bit tick timers for periodic interrupts Watchdog timer Eight software interrupts SCSI Bus interface with DMA Four serial ports with EIA 232 D buffers with DMA Centronics printer port Ethernet transceiver interface with DMA VMEbus interface VMEbus system controller functions VMEbus interface to local bus A24 A32 D8 D16 D32 D8 D16 D32 D64BLT BLT Block Transfer Local bus to VMEbus interface A16 A24 A32 D8 D16 D32 VMEbus interrupter VMEbus interrupt handler Global CSR for interprocessor communications for fast local memory VMEbus transfers A16 A24 A32 D16 D32 D16 D32 D64BLT MVME167 Single Board Computer User s Manual Specifications Specifications General specifications for the MVME167 are listed in Table 1 2 167 Specifications on page l 4 The following sections detail cooling requirements and FCC compliance Cooling Requirements The Motorola MVME167 VMEmodule is specified designed and tested to operate r
33. IRQ IRQ IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET SET SET SET SET SET IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 CLR CLR CLR CLR CLR CLR CLR IRQ IRQ IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 P ERROR IRQIE TIC TIMER 2 TIC TIMER 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL SIG 1 SIG 0 LM 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL Sw3 SW2 SW1 swo IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL VME IRQ 4 VMEB IRQ 3 VME IRQ 2 VME IRQ 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL GPIOO GPIOI GP REV DIS DIS DIS EN DIS EN SRAM MST gas BSYT INT BGN 1361 9403 4 This sheet begins on facing page MVME167 D3 3 11 Operating Instructions This page intentionally left blank 3 12 MVME167 Single Board Computer User s Manual Memorv Maps Table 3 3 VMEchip2 Memorv Map Sheet 3 of 3 VMEchip2 GCSR Base Address FFF40100 Offsets VME Local 15 14 13 12 11 10 9 8 7 6 5 4 3 211 0 0 0 CHIP REVISION CHIP ID 2 4 LM3 LM2 LM1 LMO SIG3 SIG2 5161 SIGO RST ISF SCON SYSFL X X X 4 8 GENERAL PURPOSE CONTROL AND STATUS REGISTER 0 6 GENERAL PURPOSE CONTROL AND STATUS REGISTER 1 8 10 GENERAL PURPOSE CONTROL AND STATUS REGISTER 2 A 14 GENERAL PURPOSE CONTROL AND S
34. M Mezzanine Module Block Diagram 4 12 Figure 4 3 ECC DRAM Mezzanine Module Block Diagram 4 13 Figure 1 Middle of the Road EIA 232 D Configuration sess A 4 Figure A 2 Minimum EIA 232 D Connection xi xii List of Tables Table 1 1 MVME167 Model Designations as l 1 Table 1 2 MVME167 1 4 Table 3 1 Local Bus Memory 222 022 1 0 0010000000000000015900002 3 4 Table 3 2 Local VO Devices Memory eee 3 5 Table 3 3 VMEchip2 Memory Map Sheet 1 of 3 3 8 Table 3 4 PCCchip2 Memory 3 14 Table 3 5 Printer Memory 3 16 Table 3 6 MEMCO40 Internal Register Memory Map eee 3 17 Table 3 7 MCECC Internal Register Memory 3 17 Table 3 8 Cirrus Logic CD2401 Serial Port Memory 3 19 Table 3 9 82596CA Ethernet LAN Memory 00000 3 23 Table 3 10 53C710 SCSI Memory 3 24 Table 3 11 MK48T08 BBRAM TOD Clock Memory 3 25 Table 3 12 BBRAM Configuration Area Memory 3 25 Table 3 13 TOD Clock Memory 00 224220200000 000 3 26 Table A 1 EIA 232 D
35. MVME167 Single Board Computer User s Manual Contents CHAPTER1 GENERAL INFORMATION Introduction oou g askai de 1 1 cri i 1 1 eto neget iu EO e EE etu 1 2 Specifications ea edic eU 1 3 Cooling Requirement 1 3 So 1 4 General Description as sa n Aa 1 5 Equmpiment ER RUP UR eque reete has ee 1 6 Related Documentation 1 7 Support Information tee peii 1 8 Manual 1 9 CHAPTER2 HARDWARE PREPARATION AND INSTALLATION Introduction e gne tepore e Re P RE EE OE 2 1 Unpacking Instrucfi nS 2 2 1 Hardware Preparation err A er nas W 2 1 General Purpose Readable Jumpers on Header Jl 2 2 System Controller Header 2 2 Serial Port 4 Clock Configuration Select Headers 16 and J7 2 4 SRAM Backup Power Source Select Header JB 2 5 Installation 9 2 6 MVME167 Module Installation eese 2 6 System Re Se ee ee ee ee ee tn 2 7 CHAPTER3 OPERATING INSTRUCTIONS Introduction saec rr 3 1 Controls and Indicators
36. Proper Grounding Another subject to consider is the use of ground pins There two pins labeled GND Pin 7is the SIGNAL GROUND and must be connected to the distant device to complete the circuit Pin 1 is the CHASSIS GROUND but it must be used with care The chassis is connected to the power ground through the green wire in the power cord and must be connected to the chassis to be in compliance with the electrical code The problem is that when units are connected to different electrical outlets there mav be several volts of difference in ground potential If pin 1 of each device is interconnected with the others via cable several amperes of current could result This condition not only be dangerous for the small wires in a typical cable but may also produce electrical noise that causes errors in data transmission That is whv Figure A 1 shows no connection for pin 1 Normally pin 7 should only be connected to the CHASSIS GROUND at one point if several terminals are used with one computer the logical place for that point is at the computer The terminals should not have connection between the logic ground return and the chassis A 6 MVME167 Single Board Computer User s Manual Index When using this index keep in mind that a page number indicates only where referenced material begins It mav extend to the page or pages following the page referenced Numerics 167Bug see debug monitor and MVME167Bug l 6 2 2
37. Reference Guide Multi MPU Programming Considerations Good programming practice dictates that only one MPU at a time have control of the 167 control registers Of particular note are registers that modify the address map registers that require two cycles to access and VMEbus interrupt request registers Local Reset Operation Local reset LRST is a subset of system reset SRST Local reset can be generated five ways expiration of the watchdog timer pressing the front panel RESET switch if the system controller function is disabled by asserting a bit in the board control register in GCSR by SYSRESET or by powerup reset N ote The GCSR allows a VMEbus master to reset the local bus This feature is verv dangerous and should be used with caution The local reset feature is a partial svstem reset not a complete system reset such as powerup reset SYSRESET When the local bus reset signal is asserted a local bus cycle be aborted The VMEchip2 is connected to both the local bus and the VMEbus and if the aborted cycle is bound for the VMEbus erratic operation may result Communications between the local processor and a VMEbus master should use interrupts or mailbox locations reset should not be used in normal communications Reset should be used only when the local processor is halted or the local bus is hung and reset is the last resort Any VMEbus access to the MVME167 while it is in the reset
38. TATUS REGISTER 3 C 18 GENERAL PURPOSE CONTROL AND STATUS REGISTER 4 E 1C GENERAL PURPOSE CONTROL AND STATUS REGISTER 5 MVME167 D3 3 13 Operating Instructions Table 3 4 PCCchip2 Memorv Map PCCchip2 Base Address FFF42000 OFFSET D31 D24 D23 D16 00 CHIP ID CHIP REVISION 04 1 08 TIC TIMER 1 0C TIC TIMER 2 10 TIC TIMER 2 14 PRESCALER COUNT REGISTER PRESCALER CLOCK ADJUST GPI GPI GPI GPI GPI GPI GPOE GPO 18 PLTY INT IEN IRQ LEVEL scc scc scc scc scc Scc scc scc 1C RTRY PAR EXT LTO SCLR MDM MDM MDM p M ERR ERR ERR ERR ERR IEN AVEC 20 24 SCC TRANSMIT PIACK LAN LAN LAN T LAN 28 PAR EXT LTO SCLR ERR ERR ERR SCSI scsi scsi scsi 2C PAR EXT LTO SCLR ERR ERR ERR PRTR PRTR PRTR PRTR PRTR PRTR ACK PRTR PRTR PRTR PRTR PRTR PRTR FAULT 30 ACK ACK ACK ACK ACK IRQ LEVEL FLT FLT FLT FLT FLT IRQ LEVEL PLTY E L INT IEN ICLR INT IEN ICLR PRTR PRTR PRTR PRTR PRTR 34 BSY BSY BSY BSY BSY BEE PLTY INT IEN ICLR 38 CHIP SPEED 3C SCC PROVIDES ITS OWN VECTORS This sheet continues on facing page 3 14 167 Single Board Computer User s Manual Memorv Maps
39. VMEchip2 in the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide The boards include 128KB of 32 bit wide static RAM that supports 8 16 and 32 bit wide accesses The SRAM allows the debugger to operate and limited diagnostics to be executed without the DRAM mezzanine The SRAM is controlled by the VMEchip2 and the access time is programmable Refer to the VMEchip2 in the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide for more detail The boards are populated with 100 ns SRAMs SRAM battery backup is optionally available on the MVME167 The battery backup function is provided by a Dallas DS1210S Only one backup power source is supported on the MVMEI67 Each time the 167 is powered 0512105 checks power source and if the voltage of the backup source is less than two volts the second memory cycle is blocked This allows software to provide an early warning to avoid data loss Because the DS1210S may block the second access the software should do at least two accesses before relying on the data Optionally the MVME167 provides jumpers that allow the power source of the DS1210S to be connected to the VMEbus 45 V STDBY pin or the onboard battery The optional power source SRAM is a socketed Sanyo CR2430 battery A small capacitor is provided to allow the battery to be quickly replaced without data loss The lifetime of the battery is very dependent on the ambient temperatu
40. actory jumper settings Settings can be made for General purpose readable register J1 MVME167 D32 1 Hardware Preparation and Installation 0 System controller select 72 Serial port 4 clock configuration select 76 J7 SRAM backup power source select 78 optional General Purpose Readable Jumpers on Header J1 Each MVME167 may be configured with readable jumpers These jumpers can be read as a register at FFF40088 in the VMEchip2 LCSR The bit values are read as a one when the jumper is off and as a zero when the jumper is on J1 2 16 1 15 GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 Zeros Factory Configuration System Controller Header J2 The 167 can be VMEbus system controller The system controller function is enabled disabled by jumpers on header J2 When the MVME 167 is system controller the SCON LED is turned on The VMEchip2 may be configured as a system controller as follows J2 J2 2 2 1 l 1 Svstem Controller Not Svstem Controller Factorv Configuration 2 2 MVME167 Single Board Computer User s Manual Hardware Preparation P1 P2 A32 A32 B1 B32 ol Fa ho B1 B32 ss C32 2 J6 J7 como 5 39 29
41. air mover which determine the actual volume and speed of air flowing over a module MVME167 D3 1 3 General Information Table 1 2 MVME167 Specifications Characteristics Specifications Power requirements with all four EPROM sockets populated and excluding external LAN transceiver 5 x 5 3 5 A typical 4 5 max at 25 MHz with 32MB paritv DRAM 5 0 A tvpical 6 5 A max at 33 MHz with 128MB ECC DRAM 12 5 100 mA max 1 0 A max with offboard LAN transceiver 12 Vdc 5 100 mA max Operating temperature refer to Cooling Requirements section 0 to 557 C at point of entry of forced air approximatelv 490 LEM Storage temperature 40 to 85 C Relative humidity 5 to 90 non condensing Physical dimensions Double high VMEboard PC board with mezzanine module only Height 9 187 inches 233 35 mm Depth 6 299 inches 160 00 mm Thickness 0 662 inches 16 77 mm PC boards with connectors and front panel Height 10 309 inches 261 85 mm Depth 7 4 inches 188 mm Thickness 0 80 inches 20 32 mm FCC Compliance The MVME167 was tested in an FCC compliant chassis and meets the requirements for Class A equipment FCC compliance was achieved under the following conditions 1 Shielded cables on all external I O ports 2 Cable shields connected to earth ground via metal shell connectors bonded to a conductive m
42. and normal DRAM initialization However software should insure a minimum of 10 initialization cycles are performed to each bank of RAM Battery Backed Up RAM and Clock The MK48T08 RAM and clock chip is used on the MVME167 This chip provides a time of day clock oscillator crystal power fail detection memory write protection 8KB of RAM and a battery in one 28 pin package The clock provides seconds minutes hours day date month and year in BCD 24 hour format Corrections for 28 29 leap year and 30 day months are automatically made No interrupts are generated by the clock The 48708 is an 8 bit device however the interface provided by the PCCchip2 supports 8 16 and 32 bit accesses to the 48708 Refer to the PCCchip2 in the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide and to the 48708 data sheet for detailed programming information VMEbus Interface The local bus to VMEbus interface the VMEbus to local bus interface and the local VMEbus DMA controller functions on the 167 are provided by the VMEchip2 The VMEchip2 can also provide the VMEbus system controller functions Refer to the VMEchip2 in the 166 167 187 Single Board Computers Programmer 5 Reference Guide for detailed programming information VO Interfaces The 167 provides onboard I O for many system applications The I O functions include serial ports printer port Ethernet trans
43. at the specified level This does not do so on the 167 Refer to the PCCchip2 information in the MVME166 MVME167 MVME187 Single Board Computers Programmer 5 Reference Guide for information on reading the current interrupt level and setting the interrupt mask VMEbus Memory Map This section describes the mapping of local resources as viewed by VMEbus masters VMEbus Accesses to the Local Bus The VMEchip2 includes a user programmable map decoder for the VMEbus to local bus interface The map decoder allows you to program the starting and ending address and the modifiers the MVME 167 responds to 167 Single Board Computer User s Manual Memorv Maps VMEbus Short VO Memory The VMEchip2 includes a user programmable map decoder for GCSR The GCSR map decoder allows you to program the starting address of the GCSR in the VMEbus short I O space MVME167 D3 3 29 Operating Instructions Software Initialization Most functions that have been done with switches or jumpers on other modules are done by setting control registers on MVME167 At powerup or reset the EPROMs that contain the 167Bug debugging package set up the default values of many of these registers Specific programming details may be determined by study of the MC68040 Microprocessor User s Manual Then check the details of all the MVME167 onboard registers as given in the MVME166 MVME167 MVME187 Single Board Computers Programmer s
44. ber assigned to the first mezzanine board in ASCII format This does not include the 01 w prefix For example for a 16MB parity mezzanine at revision E the PWB field contains 3690B03E 11 Eight bytes are reserved for the serial number assigned to the first mezzanine board in ASCII format 12 Eight bytes are reserved for the printed wiring board PWB number assigned to the optional second mezzanine board in ASCII format 13 Eight bytes are reserved for the serial number assigned to the optional second mezzanine board in ASCII format 14 Growth space 153 bytes is reserved This pads the structure to an even 256 bytes System specific items such as size of system side and systems side version may go here 15 The final one byte of the area is reserved for a checksum as defined in the 1 7 Debugging Package User s Manual and the Debugging Package for Motorola 68K CISC CPUs User s Manual for security and data integrity of the configuration area of the NVRAM This data is stored in hexadecimal format Interrupt Acknowledge Map The local bus distinguishes interrupt acknowledge cycles from other cycles by placing the binary value 9011 on 1 It also specifies the level that is being acknowledged using TM2 TMO The interrupt handler selects which device within that level is being acknowledged On the MVME187 a read anywhere from location FFFE0004 through FFFE001C causes an interrupt acknowledge cycle
45. ceiver interface and SCSI mass storage interface Serial Port Interface The CD2401 serial controller chip SCC is used to implement the four serial ports The serial ports support the standard baud rates 110 to 38 4K baud The four serial ports are different functionally because of the limited number of pins on the P2 I O connector Serial port 1 is a minimum function asynchronous port It uses RXD CTS TXD and RTS Serial ports 2 and 3 are full function asynchronous ports They use RXD CTS DCD TXD RTS and DTR Serial port 4 is a full function asynchronous 4 4 167 Single Board Computer User s Manual 167 Functional Description or svnchronous port It can operate at synchronous bit rates up to 64 k bits per second It uses RXD CTS DCD TXD RTS It also interfaces to the synchronous clock signal lines Refer to the MVME166 MVME167 MVME1687 Single Board Computers Programmer s Reference Guide for drawings of the serial port interface connections four serial ports use EIA 232 D drivers and receivers located on the main board and all the signal lines are routed to the I O connector The configuration headers located on the main board and the MVME712X transition board An external I O transition board such as the MVME712X should be used to convert the I O connector pinout to industry standard connectors N ote The MVME167 board hardware ties the DTR signal from the lote CD240
46. ces Memory Map on page 3 5 further defines the map for the local VO devices MVME167 D3 3 3 Operating Instructions Table 3 1 Local Bus Memorv Map Software Address Range Devices Accessed Port Size Size Cache Notes Inhibit 00000000 DRAMSIZE User Programmable D32 DRAMSIZE 1 2 Onboard DRAM DRAMSIZE FF7FFFFF User Programmable D32 D16 3GB 3 4 VMEbus FF800000 SFFBFFFFF ROM D32 4MB N 1 FFC00000 SFFDFFFFF reserved 2MB 5 FFE00000 1 SRAM D32 128KB N FFE20000 SFFEFFFFF SRAM repeated D32 896KB N 00000 FFFEFFFF Local VO Devices D32 D8 IMB Y 3 Refer to next table FFFF0000 FFFFFFFF User Programmable D32 D16 64KB 7 2 4 VMEbus 16 NOTES 1 Onboard EPROM appears at 00000000 003FFFFF following a local bus reset The EPROM appears at 0 until the bit is cleared the VMEchip2 The ROMO bit is located at address FFF40030 bit 20 The EPROM must be disabled at 0 before the DRAM is enabled The VMEchip2 and DRAM map decoders are disabled by a local bus reset This area is user programmable The suggested use is shown in the table The DRAM decoder is programmed in the MEMC040 or MCECC chip and the local to VMEbus decoders are programmed in the VMEchip2 Size is approximate Cache inhibit depends on devices in area mapped This area is not decoded If these locations are accessed and the local b
47. cter 90 percent specifies a binarv number amp ampersand specifies a decimal number Unless otherwise specified all address references are in hexadecimal An asterisk following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation an negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent Data and address sizes are defined as follows A byte is eight bits numbered 0 through 7 with bit 0 being the least significant H A word is 16 bits numbered 0 through 15 with bit 0 being the least significant H Alongword is 32 bits numbered 0 through 31 with bit 0 being the least significant MVME167 D3 1 9 General Information l 10 MVME167 Single Board Computer User s Manual HARDWARE PREPARATION AND INSTALLATION Introduction This chapter provides unpacking instructions hardware preparation and installation instructions for the MVME167 The MVME712X transition module hardware preparation is provided in separate manual
48. ddition the six bytes including the Ethernet address are stored in the configuration area of the BBRAM That is 08003 2 is stored in the BBRAM At an address of FFFC1F2C the upper four bytes 08003E2X can be read At an address of FFFC1F30 the lower two bytes XX XX can be read Refer to the BBRAM TOD Clock memory map description in Chapter 3 The MVMEI67 debugger has the capability to retrieve or set the Ethernet address If the data in the BBRAM is lost the user should use the number on the VMEbus P2 connector label to restore it The Ethernet transceiver interface is located on the MVME167 main module and the industry standard connector is located on the MVME712X transition module Support functions for the 82596CA are provided by the PCCchip2 Refer to the 82596CA user s guide and to the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide for detailed programming information SCSI Interface The MVME167 provides for mass storage subsystems through the industry standard SCSI bus These subsystems may include hard and floppy disk drives streaming tape drives and other mass storage devices The SCSI interface is implemented using the 53C710 SCSI VO controller 4 6 167 Single Board Computer User s Manual 167 Functional Description Support functions for the 53C710 are provided bv the PCCchip2 Refer to the 53C710 user s guide and to the MVME166 MVME167 MVME187 Si
49. e load and disk bootstrap load commands as well as a full set of onboard diagnostics and a one line assembler disassembler 167Bug includes a user interface which accepts commands from the system console terminal 167Bug can also operate in a System Mode which includes choices from a service menu Refer to the MVME167Bug Debugging Package User s Manual and the Debugging Package for Motorola 68K CISC CPUs User s Manual for details The MVME712X series of transition modules provide the interface between the MVME167 module and peripheral devices They connect the MVME167 to EIA 232 D serial devices Centronics compatible parallel devices SCSI devices and Ethernet devices The MVME712X series work with cables and a P2 adapter Software available for the MVME167 includes SYSTEM V 68 and real time operating systems programming languages and other tools and applications Contact your local Motorola sales office for more details MVME167 Single Board Computer User s Manual Related Documentation Related Documentation The following publications are applicable to the 167 and may provide additional helpful information If not shipped with this product thev mav be purchased bv contacting vour local Motorola sales office Non Motorola documents mav be purchased from the sources listed Motorola Document Title Publication Number MVME167 Single Board Computer Support Information SIMVME167 Refer to Support Inf
50. e standard EIA 232 D interconnections To interpret this information correctly remember that EIA 232 D was intended to connect a terminal to a modem When computers are connected to each other without modems one of them must be configured as a terminal data terminal equipment DTE and the other as modem data circuit terminating equipment DCE Since computers are normallv configured to work with terminals thev are said to be configured as a modem in most cases Signal levels must lie between 3 and 15 volts for a high level and between 3 and 15 volts for low level Connecting units in parallel may produce out of range voltages and is contrarv to EIA 232 D specifications MVME167 D3A 1 A EIA 232 D Interconnections Table A 1 EIA 232 D Interconnections Pin Number Signal Mnemonic Signal Name and Description 01 02 03 04 05 06 07 18 19 20 21 22 23 24 25 TxD RxD RTS CTS DSR SIG GND DCD TXC RxC DIR RI 5 Not used TRANSMIT DATA Data to be transmitted input to the modem from the terminal RECEIVE DATA Data which is demodulated from the receive line output from the modem to the terminal REQUEST TO SEND Input to the modem from the terminal when required to transmit a message With RTS off the modem carrier remains off When RTS is turned on the modem immediatelv turns on the carrier CLEAR TO SEND Out
51. e with DMA controller The LAN DMA controller uses FIFO buffer to interface the serial LAN bus to the 32 bit local bus The FIFO buffer allows the LAN DMA controller to efficientiv transfer data to the local bus 82596CA does not execute MC68040 compatible burst cycles therefore the LAN DMA controller does not use burst transfers Paritv DRAM write cvcles require 3 clock cycles and read cycles require 5 clock cycles with paritv off and 6 clock cycles with paritv on The transfer rate of the LAN DMA controller is 20 MB sec at 25 with paritv off Assuming a continuous transfer rate of 1 MB sec on the LAN bus 5 of the local bus bandwidth is used transfers from the LAN bus Remote Status and Control The remote status and control connector J3 is a 20 connector located behind the front panel of the MVME167 It provides system designers the flexibilitv to access critical indicator and reset functions This allows system designer to construct a RESET LED panel that can be located remotely from the MVME167 In addition to the LED and RESET switch access this connector also includes two general purpose TTL level I O pins and one general purpose interrupt pin which can also function as a trigger input This interrupt pin is level programmable MVME167 D3 4 9 Functional Description
52. eliably with an incoming air temperature range from 0 to 55 C 32 to 131 F with forced air cooling at a velocity typically achievable by using a 100 CFM axial fan Temperature qualification is performed in a standard Motorola VMESystem chassis Twenty five watt load boards are inserted in two card slots one on each side adjacent to the board under test to simulate a high power density system configuration An assembly of three axial fans rated at 100 CFM per fan is placed directly under the VME card cage The incoming air temperature is measured between the fan assembly and the card cage where the incoming airstream first encounters the module under test Test software is executed as the module is subjected to ambient temperature variations Case temperatures of critical high power density integrated circuits are monitored to ensure component vendors specifications are not exceeded While the exact amount of airflow required for cooling depends on the ambient air temperature and the type number and location of boards and other heat sources adequate cooling can usually be achieved with 10 CFM and 490 LFM flowing over the module Less airflow is required to cool the module in environments having lower maximum ambients Under more favorable thermal conditions it may be possible to operate the module reliably at higher than 55 C with increased airflow It is important to note that there are several factors in addition to the rated CFM of the
53. erent models or new and old batteries together Do not charge D LLULIL O L Always check proper polarity To remove the battery from the module carefully pull the battery from the socket Onboard DRAM The MVME167 onboard DRAM is located on a mezzanine board The mezzanine boards are available in different sizes and with parity protection or ECC protection Mezzanine board sizes are 4 8 16 or 32MB paritv or 4 8 16 32 64 or 128MB ECC two mezzanine boards mav be stacked to provide 256MB of onboard RAM The main board and a single mezzanine board together take one slot The stacked configuration requires two VMEboard slots Motorola software does support mixed paritv and ECC memorv boards on the same main board The DRAM is four wav interleaved to efficiently support cache burst cycles The paritv mezzanines are only supported on 25 MHZ main boards MVME167 D3 4 3 Functional Description DRAM map decoder can be programmed to accommodate different base address es and sizes of mezzanine boards The onboard DRAM is disabled by a local bus reset and must be programmed before the DRAM can be accessed Refer to the MEMCO40 or the MCECC in the MVME166 MVME167 MVME187 Single Board Computers Programmer 5 Reference Guide for detailed programming information Most DRAM devices require some number of access cycles before the DRAMs are fully operational Normally this requirement is met by the onboard refresh circuitry
54. for the upper 16 bits of data for 32 bit transfers and for the upper 8 address lines for extended addressing mode The MVME167 may not operate properly without its main board connected to P1 and P2 of the VMEbus backplane Whether the MVME167 operates as VMEbus master or as a VMEbus slave it is configured for 32 bits of address and for 32 bits of data A32 D32 However it handles A16 or A24 devices in the address ranges indicated in Chapter 3 D8 and or D16 devices in the system must be handled by the MC68040 software Refer to the memory maps in Chapter 3 The MVME167 contains shared onboard DRAM whose base address is software selectable Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address 00000000 as programmed by the MVME167Bug firmware This may be changed by software to any other base address Refer to the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide for details If the MVME167 tries to access offboard resources in a nonexistent location and is not system controller and if the system does not have a global bus timeout the MVME167 waits forever for the VMEbus cycle to complete This would cause the system to hang up There is only one situation in which the system might lack this global bus timeout the MVME167 is not the system controller and there is no global bus timeout elsewhere in the system MVME167 D3 2 7 Hardware Preparation and Installa
55. hat is based on the MC68040 bus and supports burst transfers and snooping The various local bus master and slave devices use the local bus to communicate The local bus is arbitrated by priority type arbiter and the priority of the local bus masters from highest to lowest is 82596CA LAN CD2401 serial through the PCCchip2 53C710 SCSI VMEbus and MPU In the general case any master can access any slave however not all combinations pass the common sense test Refer to the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide and to the user s guide for each device to determine its port size data bus connection and any restrictions that apply when accessing the device MVME167 D34 1 Functional Description MC68040 MPU The MC68040 processor is used on the MVME167 The MC68040 has on chip instruction and data caches and a floating point processor Refer to the MC68040 user s manual for more information EPROM SRAM There are four 44 PLCC CLCC EPROM sockets for 27C102JK or 27C202JK type EPROMS They are organized as two 32 bit wide banks that support 8 16 and 32 bit read accesses The EPROMs are mapped to local bus address 0 following a local bus reset This allows the MC68040 to access the stack pointer and execution address following a reset The EPROMs are controlled by the VMEchip2 The map decoder access time and when they appear at address 0 is programmable For more detail refer to the
56. hat the MVME167 module is ready for installation proceed as follows 1 Turn all equipment power OFF and disconnect power cable from ac power source C aution Inserting or removing modules while power is applied could A WARNING result in damage to module components wARNING DANGEROUS VOLTAGES CAPABLE OF CAUSING DEATH ARE PRESENT IN THIS EQUIPMENT USE EXTREME CAUTION WHEN HANDLING TESTING AND ADJUSTING Remove chassis cover as instructed in the equipment user s manual Remove the filler panel s from the appropriate card slot s at the front and rear of the chassis if the chassis has a rear card cage The 167 module requires power from both P1 and P2 It may be installed in any double height unused card slot if it is not configured as system controller If the 167 is configured as system controller it must be installed in the leftmost card slot slot 1 to correctly initiate the bus grant daisy chain and to have proper operation of the IACK daisy chain driver The MVME167 is to be installed in the front of the chassis and the MVME712X is to be installed in the front or the rear of the chassis Other modules in the system may have to be moved to allow space for the MVME712M which has a double wide front panel Carefully slide the MVME167 module into the card slot Be sure the module is seated properly into the P1 and P2 connectors on the backplane Do not damage or bend connector pins Fasten the module in
57. industry standard connectors for the I O devices The VMEbus interface is provided by an ASIC called the VMEchip2 The VMEchip2 includes two tick timers a watchdog timer programmable map decoders for the master and slave interfaces and a VMEbus to from local bus DMA controller a VMEbus to from local bus non DMA programmed access interface a VMEbus interrupter a VMEbus system controller a VMEbus interrupt handler and a VMEbus requester Processor to VMEbus transfers can be D8 D16 or D32 VMEchip2 DMA transfers to the VMEbus however can be 016 032 D16 BLT D32 BLT or D64 MBLT The PCCchip2 ASIC provides two tick timers and the interface to the LAN chip SCSI chip serial port chip printer port and BBRAM The MEMC040 memory controller ASIC provides the programmable interface for the parity protected DRAM mezzanine board The MCECC memory controller ASIC provides the programmable interface for the ECC protected DRAM mezzanine board MVME167 D3 1 5 General Information Equipment Required The following equipment is required to make a complete system using the MVME 167 Terminal Disk drives and controllers 1 Transition module MVME712 12 MVME712 13 MVME712M MVME712A MVME712AM or MVME712B and connecting cables and P2 adapter Li Operating system The MVME167Bug debug monitor firmware 167Bug is provided in two of the four EPROM sockets on the MVME167 main module It provides over 50 debug up downlin
58. ion Size Bytes FFFC1EF8 FFFC1EFB Version 4 FFFCIEFC FFFCIF07 Serial Number 12 FFFCIFO08 FFFC1F17 Board ID 16 FFFCIFI8 FFFC1F27 PWA 16 FFFC1F28 FFFC1F2B Speed 4 FFFCIF2C FFFC1F31 Ethernet Address 6 FFFCIF32 FFFC1F33 Reserved 2 4 FFFC1F35 SCSI ID 2 FFFC1F36 FFFC1F3D System ID 8 FFFC1F45 Mezz Board 1 PWB 8 FFFC1F46 FFFC1F4D Mezz Board 1 Serial Number 8 FFFCIF4E FFFC1F55 Mezz Board 2 PWB 8 FFFC1F56 FFFC1F5D Mezz Board 2 Serial Number 8 FFFC1FSE FFFCIFF6 Reserved 153 FFFCIFF7 Checksum 1 MVME167 D3 3 25 Operating Instructions Table 3 13 TOD Clock Memorv Map Data Bits Address D7 D6 D5 D4 D3 D2 D1 Function FFFC1FF8 w R S JCONTROL 00 9 ST SECONDS 00 FFFC1FFA x MINUTES 00 FFFCIFFB x x HOUR 00 FFFCIFFC x FT x x x 01 x x DATE 01 FFFCIFFE x x x MONTH 01 FFFC 1 FFF 00 NOTES W Write Bit R Read Bit S Signbit ST Stop Bit FT Frequency Test x Unused BBRAM TOD Clock Memory Map The MK48T08 BBRAM also called Non Volatile RAM or NVRAM is divided into six areas as shown in Table 3 11 MK45T05 BBRAM TOD Clock Memory on page 3 25 The first five
59. ledge ACK Printer Fault FAULT Printer Busy BSY Printer Select SELECT and Printer Paper Error PE while the control pins act as Printer Strobe STROBE and Input Prime INP MVME167 D3 4 5 Functional Description The PCCchip2 provides an auto strobe feature similar to that of the MVME147 PCC In auto strobe mode after a write to the Printer Data Register the PCCchip2 automatically asserts the STROBE pin for a selected time specified by the Printer Fast Strobe control bit In manual mode the Printer Strobe control bit directly controls the state of the STROBE pin Refer to the MVME166 MVME167 MVME187 Single Board Computers Programmer 5 Reference Guide for drawings of the printer port interface connections Ethernet Interface The 82596CA is used to implement the Ethernet transceiver interface The 82596CA accesses local RAM using DMA operations to perform its normal functions Because the 82596CA has small internal buffers and the VMEbus has an undefined latency period buffer overrun may occur if the DMA is programmed to access the VMEbus Therefore the 82596CA should not be programmed to access the VMEbus Every MVMEI67 is assigned an Ethernet Station Address The address is 08003E2XXXXX where XXXXX is the unique 5 nibble number assigned to the board i e every MVME167 has a different value for XXXXX Each module has an Ethernet Station Address displayed on a label attached to the VMEbus P2 connector In a
60. ngle Board Computers Programmer 5 Reference Guide for detailed programming information SCSI Termination The svstem configurer must ensure that the SCSI bus is properlv terminated at both ends On the MVME167 sockets are provided for the terminators on the P2 transition board If the SCSI bus ends at the P2 transition board then termination resistors must 4 be installed on the P2 transition board 45V power to the SCSI bus TERM power line and termination resistors is provided through a fuse located on the P2 transition board Local Resources The MVME167 includes many resources for the local processor These include tick timers software programmable hardware interrupts watchdog timer and local bus timeout Programmable Tick Timers Four 32 bit programmable tick timers with 1 us resolution are provided two in the VMEchip2 and two in the PCCchip2 The tick timers can be programmed to generate periodic interrupts to the processor Refer to the VMEchip2 and PCCchip2 in the MVME166 MVME167 MVME187 Single Board Computers Programmer 5 Reference Guide for detailed programming information Watchdog Timer A watchdog timer function is provided in the VMEchip2 When the watchdog timer is enabled it must be reset bv software within the programmed time or it times out The watchdog timer can be programmed to generate SYSRESET signal local reset signal or board fail signal if it times out Refer to the VMEchip2 in the MVME166 MVME167 MVME1
61. odule front panel 3 Conductive chassis rails connected to earth ground This provides the path for connecting shields to earth ground 4 Front panel screws properly tightened 1 4 167 Single Board Computer User s Manual General Description For minimum RF emissions it is essential that the conditions above be implemented failure to do so could compromise the FCC compliance of the equipment containing the module General Description The MVME 167 is a double high VMEmodule based on the MC68040 microprocessor 167 has 4 8 16 32 64 MB of parity protected DRAM or 4 8 16 32 64 128 256 MB of ECC protected DRAM 8KB of static RAM and time of dav clock with batterv backup Ethernet transceiver interface four serial ports with EIA 232 D interface four tick timers watchdog timer four sockets SCSI bus interface with DMA Centronics printer port A16 A24 A32 D8 D16 D32 D64 VMEbus master slave interface 128KB of static RAM with optional battery backup and VMEbus system controller The I O on the MVME 167 is connected to the VMEbus P2 connector The main board is connected through a P2 transition board and cables to the transition boards The 167 supports the transition boards MVME712 12 MVME712 13 MVME712M MVME712A MVME712AM and MVME712B referred to in this manual as MVME712X unless separately specified The MVME712X transition boards provide configuration headers and provide
62. ormation on page l 8 MVME167Bug Debugging Package User s Manual MVME167BUG Debugging Package for Motorola 68K CISC CPUs User s Manual 68KBUG Single Board Computers SCSI Software User s Manual SBCSCSI MVME166 MVME167 MVME187 Single Board Computers MVME187PG Programmer s Reference Guide MVMET712M Transition Module and P2 Adapter Board User s MVME712M Manual MVME712 12 MVME712 13 MVME712A MVME712AM and MVME712A MVMET712B Transition Module LCP2 Adapter Board User s Manual M68040 Microprocessor User s Manual M68040UM N ote Although not shown in the above list each Motorola Computer lote Group manual publication number is suffixed with characters which represent the revision level of the document such as D2 the second revision of a manual a supplement bears the same number as manual but has a suffix such as D2A1 the first supplement to the second edition of the manual MVME167 D3 1 7 General Information The following publications are available from the sources indicated Versatile Backplane Bus VMEbus ANSI IEEE Std 1014 1987 The Institute of Electrical and Electronics Engineers Inc 345 East 47th Street New Xork NX 10017 VMEbus Specification This is also available as Microprocessor system bus for 1 to 4 byte data IEC 821 BUS Bureau Central de la Commission Electrotechnigue Internationale 3 rue de Varemb Geneva Switzerland ANSI Small Computer System Interface 2 SCSI 2 Draft Document X
63. p 4 2 SRST svstem reset 3 1 3 30 static RAM SRAM 4 2 support information l 8 SYSRESET see system reset 3 1 3 30 svstem considerations 2 7 system console terminal l 6 svstem controller 2 2 svstem controller function 2 2 3 30 svstem controller header J2 2 2 svstem mode l 6 system reset SRST 3 30 system reset SRST see SYSRESET 3 1 SYSTEM 68 1 6 systems serial ID 3 28 T terminal s A 1 terminology 1 9 tick timers 4 7 timeout 4 8 global bus 2 8 local bus 4 8 timers 4 7 timing performance 4 8 TOD clock memorv map 3 26 transfer tvpe TT signals 3 3 transition modules 1 5 4 5 transparent mode A 4 TRXCA Transmit Receive Clock 4 2 4 TT transfer tvpe signals 3 3 U unpacking instructions 2 1 MEbus 3 29 MEbus accesses to the local bus 3 29 MEbus interface 4 4 MEbus memorv map 3 29 MEbus short I O memorv map 3 29 MEbus specification 1 8 MEchip2 1 5 MEchip2 GCSR Global Control and Status Registers 2 8 MEchip2 LCSR Local Control and Sta tus Registers 2 2 MEchip2 memory map 3 8 lt lt lt lt lt lt lt lt lt lt warnings 4 3 watchdog timer 3 30 4 8 word 1 9 MVME167 D3 IN 5 gt ITIO Z Index IN 6 167 Single Board Computer User s Manual
64. put from the modem to the terminal to indicate that message transmission can begin When a modem is used CTS follows the off to on transition of RTS after a time delav DATA SET READY Output from the modem to the terminal to indicate that the modem is to transmit data SIGNAL GROUND Common return line for all signals at the modem interface DATA CARRIER DETECT Output from the modem to the terminal to indicate that a valid carrier is being received Not used TRANSMIT CLOCK DCE Output from the modem to the terminal clocks data from the terminal to the modem Not used RECEIVE CLOCK Output from the modem to the terminal clocks data from the modem to the terminal Not used DATA TERMINAL READY Input to the modem from the terminal indicates that the terminal is readv to send or receive data Not used RING INDICATOR Output from the modem to the terminal indicates to the terminal that an incoming call is present The terminal causes the modem to answer the phone carrving DTR true while RI is active Not used TRANSMIT CLOCK DTE Input to modem from terminal same function as on pin 15 BUSY Input to modem from terminal A positive EIA signal applied to this pin causes the modem to go off hook and make the associated phone busv NOTES 1 A high EIA 232 D signal level is 3 to 15 volts A low level is 3 to 15 volts Connecting units in parallel mav produce out of range voltages and
65. ransmit Buffer Byte Count BTBCNT 58 w R W A Transmit Buffer Status ATBSTS 5 R W B Transmit Buffer Status BTBSTS SE B R W Transmit Current Buffer Address Lower TCBADRL 3A w R Transmit Current Buffer Address Upper TCBADRU 38 w R MVME167 D3 3 21 Operating Instructions Table 3 8 Cirrus Logic CD2401 Serial Port Memorv Map Continued Base Address FFF45000 Register Description Offsets Size Access Timer Registers Timer Period Register TPR DA B R W Receive Time out Period Register RTPR 24 w R W Async Receive Time out Period Regis low RTPRI 25 B R W Async Receive Time out Period Register high RTPRh 24 B R W Async General Timer 1 GTI 2 w R Sync General Timer 1 low GTII 2B B R Svnc General Timer 1 high GTIh 2 R Svnc General Timer 2 GT2 29 B R Sync Transmit Timer Register TTR 29 B R Async NOTE This is a 16 bit register 3 22 167 Single Board Computer User s Manual Memorv Maps Table 3 9 82596CA Ethernet LAN Memorv Map 82596CA Ethernet LAN Directly Accessible Registers Data Bits Address D31 D16 D15 FFF46000 Upper Command Word Lower Command Word FFF46004 MPU Channel Attention CA NOTES 1 Refer to the MPU Port and MPU Channel Attention registers in the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide After resetting vou must write the Svstem Configu
66. ration Pointer to the command registers before writing to the MPU Channel Attention register Writes to the Svstem Configuration Pointer must be upper word first lower word second MVME167 D3 3 23 Operating Instructions Table 3 10 53C710 SCSI Memorv Map 53C710 Register Address Map Base Address is 47000 SCRIPTs Big Endian Mode and Mode Little Endian Mode 00 SIEN SDID SCNTLI SCNTLO 00 04 SOCL SODL SXFER SCID 04 08 SBCL SBDL SIDL SFBR 08 0C SSTAT2 SSTATI SSTATO DSTAT 0C 10 DSA 10 14 CTEST3 CTEST2 CTESTI CTESTO 14 18 CTEST7 CTEST6 CTEST5 CTEST4 18 IC TEMP IC 20 LCRC CTESTS ISTAT DFIFO 20 24 DCMD DBC 24 28 DNAD 28 2C DSP 2C 30 DSPS 30 34 SCRATCH 34 38 DCNTL DWT DIEN DMODE 38 3C ADDER 3C NOTE Accesses may be 8 bit or 32 bit but not 16 bit 3 24 MVME167 Single Board Computer User s Manual Memorv Maps Table 3 11 MK48T08 BBRAM TOD Clock Memorv Map Address Range Description Size Bvtes FFFC0000 FFFC0FFF User Area 40 EFFC1000 FFFC10FF Networking Area 256 FFFC1100 FFFC16F7 Operating System Area 1528 FFFC16F8 FFFC1EF7 Debugger Area 2048 FFFC1EF8 FFFC1FF7 Configuration Area 256 FFFCIFF8 FFFCIFFF TOD Clock 8 Table 3 12 BBRAM Configuration Area Memory Map Address Range Descript
67. re of the board and the power on duty cycle The FB1225 and CR2430 lithium batteries should provide at least two years of backup time with the board powered off and the board at 4 2 167 Single Board Computer User s Manual 167 Functional Description 409 C If the power on dutv cvcle is 5090 the board is powered on half of the time the batterv lifetime is four vears At lower ambient temperatures the backup time is greatly extended and approach the shelf life of the battery When a board is stored if the battery is present it should be disconnected to prolong batterv life This is especiallv important at high ambient temperatures MVME167 boards with batterv backup are shipped with the batteries disconnected The power leads from the batterv are exposed on the solder side of the board therefore the board should not be placed on a conductive surface or stored in a conductive bag unless the batterv is removed A Lithium batteries incorporate inflammable materials such as WARNING lithium and organic solvents If lithium batteries are mistreated or handled incorrectiv thev mav burst open and ignite possiblv resulting in injurv and or fire When dealing with lithium batteries carefully follow the precautions listed below in order to prevent accidents Do not short circuit Do not disassemble deform or applv excessive pressure Do not heat or incinerate Do not applv solder directiv Do not use diff
68. required Burst write cycles require 5 2 1 1 1 bus clock cycles The parity DRAM is organized as four banks this requires the use of 256K by 4 chips for the data portion of the RAM and 256K by 4 chips with the write per bit option for the parity bits The use of four banks allows X 1 1 1 bursts with parity on ROM Cycle Times The ROM cycle time is programmable from 4 to 11 bus clock cycles The data transfers are 32 bits wide Refer to the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide SCSI Transfers The 167 includes a SCSI mass storage bus interface with DMA controller The SCSI DMA controller uses a FIFO buffer to interface the 8 bit SCSI bus to the 32 bit local bus The FIFO buffer allows the SCSI DMA controller to efficiently transfer data to the local bus in four longword bursts This reduces local bus usage by the SCSI device The first longword transfer of a burst with snooping disabled takes four bus clocks with parity off and five bus clocks with parity on Each of the remaining three transfers requires one bus clock The transfer rate of the DMA controller is 44 MB sec at 25 MHz with parity off Assuming a continuous transfer rate of 5 MB sec on the SCSI bus 12 of the local bus bandwidth is used by transfers from the SCSI bus 4 8 167 Single Board Computer User s Manual 167 Functional Description LAN DMA Transfers The 167 includes a LAN interfac
69. s Refer to Related Documentation in Chapter 1 Unpacking Instructions N ote If the shipping carton is damaged upon receipt request carrier s lote agent be present during unpacking and inspection of equipment Unpack equipment from shipping carton Refer to packing list and verifv that all items are present Save packing material for storing and reshipping of equipment C i Avoid touching areas of integrated circuitrv static discharge aution mu can damage circuits Hardware Preparation To select the desired configuration and ensure proper operation of the MVMEI67 certain option modifications may be necessary before installation The MVMEI67 provides software control for most of these options Some options can not be done in software so are done by jumpers on headers Most other modifications are done by setting bits in control registers after the 167 has been installed in a system The 167 registers are described in Chapter 4 and or in the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide as listed in Related Documentation in Chapter 1 The location of the switches jumper headers connectors and LED indicators on the MVMEI167 is illustrated in Figure 2 1 The MVME167 has been factory tested and is shipped with the factory jumper settings described in the following sections The 167 operates with its required and factory installed Debug Monitor MVME167Bug 167Bug with these f
70. s is DCD The original purpose of this signal was to tell the system that the carrier tone from the distant modem was being received This signal is frequently used by the software to display a message like CARRIER NOT PRESENT to help the user to diagnose failure to communicate Obviously if the system is designed properly to use this signal and is not connected to a modem the signal must be provided by a pullup resistor or gate as described above see Figure A 1 Many modems expect a DTR high signal and issue a DSR These signals are used by software to help prompt the operator about possible causes of trouble The DTR signal is sometimes used to disconnect the phone circuit in preparation for another automatic call It is necessary to provide these signals in order to talk to all possible modems see Figure A 1 MVME167 D3 A 3 A EIA 232 D Interconnections Sample Configurations Figure A 1 is a good minimum configuration that almost always works If the CTS and DOD signals are not received from the modem the jumpers can be moved to artificiallv provide the needed signal Figure A 1 Middle of the Road EIA 232 D Configuration 6850 TXD j RXD REN gt 3 TXD RXD gt 2 39kQ 12V NC 1 RISsl
71. state is ignored If a global bus timer is enabled a bus error is generated 3 30 167 Single Board Computer User s Manual FUNCTIONAL DESCRIPTION Introduction This chapter provides a block diagram level description for the MVME167 module The functional description provides an overview of the module followed bv a detailed description of several blocks of the module The block diagram of the MVME167 is shown in Figure 4 1 MVME 167 Main Module Block Diagram on page 4 10 The block diagram of the paritv DRAM mezzanine module of the MVME167 is shown as Figure 4 2 Paritv DRAM Mezzanine Module Block Diagram on page 4 11 The block diagram of the ECC DRAM mezzanine module of the 167 is shown as Figure 4 2 Paritv DRAM Mezzanine Module Block Diagram on page 4 11 Descriptions of the other blocks of the MVME 167 including programmable registers in ASICs and peripheral chips are given in the MVME166 MVME167 MVME187 Single Board Computers Programmer s Reference Guide Refer to it for the rest of the functional description of the MVME167 module 167 Functional Description The 167 is a high functionality VMEbus single board computer designed around the MC68040 chip It has 4 8 16 32 64 128 256MB of dynamic RAM a SCSI mass storage interface four serial ports a printer port and an Ethernet transceiver interface Data Bus Structure The local data bus on the MV ME167 is a 32 bit synchronous bus t
72. ter RCOR C8 B R W Transmit Baud Rate Period Register TBPR C3 B R W Transmit Clock Option Register TCOR CO B R W MVMEI67 D3 3 19 Operating Instructions Table 3 8 Cirrus Logic CD2401 Serial Port Memorv Map Continued Base Address FFF45000 Register Description S sed Offsets Size Access Channel Command and Status Registers Channel Command Register CCR 13 B R W Special Transmit Command Register STCR 12 B R W Channel Status Register CSR IA B R Modem Signal Value Registers MSVR RTS DE B R W MSVR DTR DF B R W Interrupt Registers Local Interrupt Vector Register LIVR 09 B R W Interrupt Enable Register IER 11 B R W Local Interrupting Channel Register LICR 26 B R W Stack Register STK E2 B R Receive Interrupt Registers Receive Priority Interrupt Level Register RPILR El B R W Receive Interrupt Register RIR ED B R Receive Interrupt Status Register RISR 88 w R W NOTE Receive Interrupt Status Register low RISRI 89 B R Receive Interrupt Status Register high RISRh 88 B R Receive FIFO Output Count RFOC 30 B R Receive Data Register RDR F8 B R Receive End Of Interrupt Register REOIR 84 B w Transmit Interrupt Registers Transmit Prioritv Interrupt Level Register TPILR 0 R W Transmit Interrupt Register TIR EC B R Transmit Interrupt Status Register TISR 8A B R Transmit FIFO Transfer Count TFTC 80 B R Transmit Data Register TDR F8 B w Transmit
73. the chassis with screws provided making good contact with the transverse mounting rails to minimize RFI emissions Remove IACK and BG jumpers from the header on the chassis backplane for the card slot the 167 is installed in 2 6 167 Single Board Computer User s Manual Installation Instructions 6 Connect P2 Adapter Board and specified cable s to the MVME167 at P2 the backplane at the MVME 167 slot to mate with optional terminals or other peripherals at the EIA 232 D serial ports parallel port SCSI ports and LAN Ethernet port Refer to the manuals listed in Related Documentation in Chapter 1 for information on installing the P2 Adapter Board and the MVME712X transition module s Some connection diagrams in the MVME166 MVME167 MVME187 Single Board Computers Programmer 5 Reference Guide Some cable s are not provided with the MVME712X module s and therefore are made or provided the user Motorola recommends using shielded cables for all connections to peripherals to minimize radiation Connect the peripherals to the cable s Detailed information on the EIA 232 D signals supported is found Appendix 7 Install any other required VMEmodules in the system 8 Replace the chassis cover 9 Connect power cable to ac power source and turn equipment power ON System Considerations The MVMEIL067 needs to draw power from both P1 and P2 of the VMEbus backplane P2 is also used
74. tion Multiple MVME167 modules mav be configured into a single VME card cage In general hardware multiprocessor features are supported Other MPUs on the VMEbus can interrupt disable communicate with and determine the operational status of the processor s One register of the GCSR set includes four bits which function as location monitors to allow one MVME167 processor to broadcast a signal to other MVME167 processors if any eight registers are accessible from local processor as well as from the VMEbus 167 provides 12 power to the Ethernet LAN transceiver interface through 1 amp fuse F2 located on the MVME167 module The 12V LED lights when 12 is available The fuse is socketed and located near diode If the Ethernet transceiver fails to operate check the fuse When using the MVME712M module the yellow LED 051 on the MVME712M front panel lights when LAN power is available indicating that the fuse is good The 167 provides SCSI terminator power through a 1 amp fuse FI located on the P2 Adapter Board The fuse is socketed If the fuse is blown the SCSI devices may not operate or may function erratically When the P2 Adapter Board is used with an MVME712M and the SCSI bus is connected to the MVME712M the green LED 052 on the MVME712M front panel lights when there is SCSI terminator power If the LED flickers during SCSI bus operation the fuse should be checked 2
75. uired by VMEbus specification Similarly the VMEchip2 provides an input signal and a control bit to initiate a local reset operation By setting a control bit software can maintain a board in a reset state disabling a faulty board from participating in normal system operation The local reset driver is enabled even when the VMEchip2 is not the system controller A local reset may be generated by the RESET switch a power up reset a watchdog timeout a VMEbus SYSRESET or a control bit in the GCSR Front Panel Indicators DS1 DS4 There are eight LEDs on the MVME167 front panel FAIL STAT RUN SCON LAN 12V LAN power SCSI and VME MVME167 D33 1 Operating Instructions The red FAIL LED part of DS1 lights when the BRDFAIL signal line is active The MC68040 status lines are decoded on the MV ME167 to drive the yellow STAT status LED part of DS1 In this case a halt condition from the processor lights the LED The green RUN LED part of DS2 lights when the local bus TIP signal line is low This indicates one of the local bus masters is executing a local bus cycle The green SCON LED part of 052 lights when the VMEchip2 in the 167 is the VMEbus system controller The green LAN LED part of DS3 lights when the LAN chip is local bus master The 167 supplies 12V power to the Ethernet transceiver interface through a fuse The green 12V LAN power LED part of DS3 lights when power
76. us timer is enabled the cycle times out and is terminated by a TEA signal 3 4 MVME167 Single Board Computer User s Manual Memorv Maps The following table focuses on the Local I O Devices portion of the local bus Main Memorv Map 9 Table 3 2 Local Devices Map Address Range Devices Accessed Port Size Size Notes SFFF00000 FFF3FFFF reserved 256 5 FFF40000 FFF400FF VMEchip2 LCSR D32 256B 14 FFF40100 FFF401FF VMEchip2 GCSR D32 D8 256B 14 FFF40200 FFF40FFF reserved 3 5KB 5 7 FFF41000 SFFF41FFF reserved 4KB 5 FFF42000 FFF42FFF PCCchip2 D32 D8 4KB 1 FFF43000 FFF430FF MEMC040 MCECC 1 D8 256B 1 FFF43100 SFFF431FF MEMCOAO MCECC 2 D8 256B 1 FFF43200 FFF43FFF MEMC040s MCECCs repeated 3 5KB 1 7 FFF44000 FFF44FFF reserved 4 5 FFF45000 FFF451FF CD2401 Serial Comm Cont DI6 D8 512B 1 9 FFF45200 FFF45DFF reserved 3KB 7 9 FFF45E00 EFFASFFF reserved 512B 1 9 FFF46000 FFF46FFF 82596CA LAN D32 4KB 1 8 FFF47000 FFF47FFF 53C710 SCSI D32 D8 4KB 1 FFF48000 SFFFAFFFF reserved 32KB 5 SFFF50000 FFF6FFFF reserved 128 5 FFF70000 SFFF76FFF reserved 28 6 FFF77000 SEFF77FFF reserved 4KB 2 SFFF78000 FFF7EFFF reserved 28 6 SFFF7F000 FFF7FFFF reserved 4 2 SFFF80000 FFFOFFFF reserved 128 6 FFFA0000 SFFFBFFF
77. ware programmable 4 8 hardware preparation 2 1 hardware preparation and installation 2 1 hexadecimal character 1 9 I O interfaces 4 5 interrupt acknowledge 2 7 installation instructions 2 6 interrupt acknowledge 2 7 interrupt acknowledge map 3 28 167 Single Board Computer User s Manual interrupts 4 8 introduction 1 1 2 1 3 1 4 1 1 J 2 2 722 2 73 4 10 16 2 4 J7 2 4 18 2 5 jumpers 2 1 L LAN see 82596CA and Ethernet 4 6 LAN DMA transfers 4 9 LAN FIFO buffer 4 9 LAN transceiver 2 8 LCSR Local Control and Status Regis ters see VMEchip2 LCSR 2 2 LEDs 3 2 levels of implementation A 3 LEM linear feet per minute l 3 linear feet per minute LFM 1 3 little endian mode 3 24 Local Area Network see LAN 4 6 local bus 4 8 local bus access 4 8 local bus memorv map 3 3 3 4 local bus timeout 4 8 local bus to DRAM cycle times 4 8 Local Control and Status Registers LCSR see VMEchip2 LCSR 2 2 local I O devices memorv map 3 5 local reset LRST 3 1 3 30 local reset operation 3 30 local resources 4 7 local SCSI ID 3 28 location monitors 2 8 longword l 9 LRST local reset 3 1 3 30 manual terminology 1 9 map decoders 3 29 MC68040 MPU 4 2 MCECC 1 5 MCECC internal register memory map 3 17 MEMC040 1 5 MEMC040 internal register memory map 3 17 memory maps 3 3 53C710 SCSI 3 24 82596CA Ethernet LAN 3 23 BBRAM configuration area 3 2

MVME167 Single Board Computer User`s Manual

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