4x5 Carrier Boards Overview-v17
Contents
1. A TE0701 02 REV2 FTUSB 1 has to be selected as port this is Channel B of the on board FTDI USB to JTAG interface Copyright 2014 Trenz Electronic GmbH Page 14 of 50 http www trenz electronic de n e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 Create a new Project from a Scan i n Create a new Blank Project Open an existing Programmer Project C Lattice diamond 2 2 x64 bin nt64 TE0701 TE0701 xcf v Browse v Import file to current implementation C Lattice diamond 2 2 x64 bin nt64 TE0701 TE0701 xcf x IL oe jJ Note On port 0 Channel A of the FTDI USB to JTAG interface the JTAG port of the e g Xilinx Zynq FPGA see F gure 3 on the carried module is accessible e TE0701 03 REV3 FTUSB 0 has to be selected as port this is Channel A of the on board FTDI USB to JTAG interface ei Programmer Ge Select an Action Q Create a new Project from a Scan cate ERE nes DER Create a new Blank Project Open an existing Programmer Project C Lattice diamond 2 2_x64 bin nt64 TE0701 TE0701 xcf v Browse v Import file to current implementation C Lattice diamond 2 2 x64 bin nt64 TE0701 TE0701 xcf a J oe jJ 6 After the scan has been completed successfully the following GUI should be visible wherein the LCMXO2 1200HC CPLD device must be selected manually Copyright 2012. 21 SD Card Connector Zynq SDIOO Bootable SD port see TE0701 Carrier Board User Manual Configuring Boot Mode RJ45 GbE Connector Pmod Connector J1 3 3V mapped to 8 Zynq PS MIOO pins MIOO MIO9 to MIO15 when using TE0720 same mapping as on Zedboard 6 pins MIO10 to MIO15 are additionally connected to TE0701 CPLD Carrier Controller ARM JTAG Connector DS 5 D Stream see TE0701 Carrier Board User Manual ARM JTAG Bus PJTAG to EMIO multiplexing needed VITA 57 1 compliant FMC LPC Connector with digitally programmable FMC VADJ Power Supply see TEO0701 Carrier Board User Manual Configuring Power Supply High Performance Enpirion DC DC Converters EN2340Q for 5 0V and 3 3V Power Supplies Barrel jack for 12V Power Supply Note The local power supplies 5 0V and 3 3V are generated by high performance Enpirion DC DC converters EN2340Q from the 12V power supply Carrier Controller CPLD Lattice LCMXO2 1200HC 1 200 Macrocell CPLD with Block RAM Flash and PLL 8 User LEDs and 2 User Pushbuttons mappable to different functions VID and EN Control for FMC VADJ DC DC Regulator see TEO701 Carrier Board User Manual Lattice CPLD Programming USB JTAG and UART Interface FTDI FT2232H compatible with Xilinx Tools also with many other tools Channel A can toggle Zyng SoC Module PS Reset Channel B can be used as USB UART TE0701 CPLD can reroute RXD TXD signals Pmod Connector J2
3. Open Xilinx iMPACT available with free Vivado ISE WebPack License 4 Create a new Xilinx iMPACT project Copyright 2014 Trenz Electronic GmbH Page 17 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 I want to load most recent project auto_project ipf Browse Load most recent project file when iMPACT starts create a new project ipf default ipf SS Please select an action from the list below E Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain e Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File When manually choosing Xilinx Impact 14 7 Cable Communication Setup then select Digilent USB JTAG Cable Note The port name TEO701 02 ID is read from FTDI User EEPROM Copyright 2014 Trenz Electronic GmbH Page 18 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 Advanced USB Cable Setup Port TCK Speed Baud Rate aS Cable Location E Local Remote Cable Plug in Open Cable Plug in Select or enter a Plug in from the list below pic platformush PORT USB21 FREQUENCY 6000000 L as IL cem j me jJ 6 After successful identification the following graphical view of the TE0720 JTAG chai
4. linked to this document or the materials or information contained at any or all such documents If your use of the materials or information from this document results in the need for servicing repair or correction of equipment or data you assume all costs thereof Copyright Notice No part of this manual may be reproduced in any form or by any means including electronic storage and retrieval or translation into a foreign language without prior agreement and written consent from Trenz Electronic Technology Licenses The hardware firmware software described in this document are furnished under a license and may be used modified copied only in accordance with the terms of such license Environmental protection To confront directly with the responsibility toward the environment the global community and eventually also oneself Such a resolution should be integral part not only of everybody s life Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space That is why Trenz Electronic invests in the protection of our Environment Copyright 2014 Trenz Electronic GmbH Page 49 of 50 http www trenz electronic de n e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 REACH Registration Evaluation Authorisation and Restriction of Chemicals compliance statement Trenz Electronic is a manufacturer and a distributor of electronic products
5. lt Strg gt lt Pos1 gt to return back to this overview Control and Data Flow on TE0701 and TE0720 The TE0701 Carrier Board comprises several components that can be accessed by the TE0720 Zynq SoC Module The corresponding control and data flow paths are visualized in the following figure Figure 4a Control and Data Flow on the TEO701 REV2 and the TE0720 REV1 FMC Connector not shown Copyright 2014 Trenz Electronic GmbH Page 22 of 50 http www trenz electronic de n e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 Figure 4b Control and Data Flow on the TE0701 REV3 FMC Connector not shown Power On Reset POR On the TE0701 the 5 0V and 3 3V power supply rails are generated by high performance DC DC Enpirion converters EN2340Q from the external 12V supply While the 3 3V plane supplies several on board components e g Lattice CPLD and FTDI Dual USB UART FIFO IC the 5V plane is mainly provided for power supply of the module to be carried e g TE0720 Zynq SoC module For the latter however special considerations must be taken see TE0720 Power Supply Therefore the on module system controller SC must be provided with information about the power on reset POR process namely the following control signals EN1 RESIN and NOSEQ And the SC provides in turn the status signal PGOOD down to the on board CPLD Signal Description EN1 This CPLD output active high signal is a p
6. 0 Inout clk lt 100000000 gt 12C Clk 400000 E In linux command line interface check that device with address 0x22 is visible zynq i2cdetect y r 0 0 1 2 3 4 5 6 7 8 9 a b c d e f 00 10 20 22 30 38 39 3e 3e 3f 40 50 60 70 and set bit 7 by write command zyng IZcset y 0 0x22 0x80 Copyright 2014 Trenz Electronic GmbH Page 32 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 TE0701 REV2 Known Issues First batch of TEO701 shipped did not have proper inrush current slew rate limiting circuitry required by the Enpirion newest datasheet rev C This can cause damage to the 3 3V and or 5V DCDC converters if power is applied by pushing in power plug This will cause the 12V input at Enpirion VIN terminals to rise in about 40uS what is 50x times more than allowed in datasheet This slew rate absolute maximum rating violation MAY cause damage to the Enpirion DC DC converters on TE0701 This has never happened in the lab or in factory testing where we use different power supplies and stress the boards However failures have been reported at customer sites If your TE0701 does not boot up properly and both red and green led stay lit then this may be caused by a damaged 5V regulator Moving the jumper on J16 to different position usually allows the board to be used with 3 3V supplied to module VIN C112 E
7. Cable USB II Digilent USB JTAG Cable HW Server Advanced USB Cable Setup Port TCK Speed Baud Rate aS O m Cable Location 9 Local Host Name Remote Cable Plug in F Open Cable Plug in Select or enter a Plug in from the list below xiinx_platformusb PORT USB21 FREQUENCY 6000000 oe JL ew j e TODO 6 After successful identification the following graphical view of the TE0720 JTAG chain will appear which comprises the Processing System PS and the Programmable Logic PL that are now ready to be programmed please see related Xilinx documentation Zyng 7000 All Programmable SoC Operations in iMPACT for more details Copyright 2014 Trenz Electronic GmbH Page 43 of 50 http www trenz electronic de n e trenz Revision 0 1 e electronic Cort 4x5 Carrier Boards Overview 1 ISE iMPACT P 20131013 Boundary Scan Help D X sa ss D s sl Boundary Scan 8 SystemACE E Create PROM File PROM File 2 WebTalk Data ynq7000_arm_da xc7z020 O zynq7000 arm bypass Identify Succeeded IE Boundary Scan PROGRESS END End Operation Elapsed time 0 sec BATCH CMD identifyMPM xn Configuration JTAG ONB4 10000000 Most iMPACT Boundary Scan operations performed on a Zynq 7000 AP SoC device are performed on the PL block For more information about configu
8. It is therefore a so called downstream user in the sense of REACH The products we supply to you are solely non chemical products goods Moreover and under normal and reasonably foreseeable circumstances of application the goods supplied to you shall not release any substance For that Trenz Electronic is obliged to neither register nor to provide safety data sheet According to present knowledge and to best of our knowledge no SVHC Substances of Very High Concern on the Candidate List are contained in our products Furthermore we will immediately and unsolicited inform our customers in compliance with REACH Article 33 if any substance present in our goods above a concentration of 0 1 96 weight by weight will be classified as SVHC by the European Chemicals Agency ECHA RoHS Restriction of Hazardous Substances compliance statement Trenz Electronic GmbH herewith declares that all its products are developed manufactured and distributed RoHS compliant WEEE Waste Electrical and Electronic Equipment Information for users within the European Union in accordance with Directive 2002 96 EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment WEEE Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment se
9. MODE 3 MIO 2 PJTAG R 0 and ndevendent JTAG BOOT MODE 3 MIO 2 PJTAG R 1 In Cascaded JTAG mode i e single chain mode one JTAG cable connected to the FTDI USB to JTAG interface see 19 in Figure 1 of TE0701 Carrier Board for TEO7xx Series User Manual can be used to have access both to Zynq PS and PL features concurrently To debug ARM software and the PL design simultaneously with separate cables the independent JTAG mode must be chosen Note Please see section JTAG Programming Guide ARM JTAG Bus for more details User Push Buttons PBs and LEDs On the TE0701 REV2 and REV3 Carrier Board two push buttons 81 and S2 and eight LEDs L1 to L8 are available to the user The default PB mapping is as follows Name Default Mapping S1 If S1 is pushed the active low RESet IN RESIN signal will be asserted Note This reset can also be forced by the FTDI USB to JTAG interface S2 If S2 is pushed the active high Power ON PON signal that is internally pulled up will be deasserted which can be considered as a RESTART button to switch o f push button and o7 release button all on module power supplies except 3 3VIN Note The capability to be enabled the first time will become active shortly after Power on Reset POR The active high PON signal is directly mapped to the active high EN1 signal which is routed to the SC e g on the TE0720 and directly used after deglitching as a mandatory active high enab
10. TE0701 REV2 Known Issues Ethernet RJ45 Pmod Slots PMOD J5 PMOD J6 TEO0703 Carrier Board User Manual 11 11 11 12 12 13 17 20 22 22 23 24 25 26 26 30 30 30 30 30 30 31 31 31 31 31 33 34 35 35 35 36 Copyright 2014 Trenz Electronic GmbH Page 2 of 50 http www trenz electronic de Wl e trenz electronic e 4x5 Carrier Boards Overview Revision 0 1 Overview TE0703 Carrier Board 36 Features 36 Document Change History ed TE0703 Jumper Configurations 38 Jumper Configurations 38 Intelligent Carried Controller iCC Update Mode 38 Configuring B34 Bank Supply of the TE0720 Zynq SoC Module 39 Backup Battery Supply VBAT connector 39 TE0703 JTAG Programming Guide 40 JTAG Programming Guide 40 Lattice CPLD Programming 40 Xilinx Zyng TE0720 Zynq SoC module Programming 41 TE0703 Control and Data Flow with TE0720 45 Control and Data Flow on TE0703 and TE0720 45 Intelligent Carrier Controller iCC 46 Features 46 User LEDs 46 Push Button 46 DIP Switch 46 LEDs 47 Module FPGA User LED s 47 System LED s 47 12C 48 Legal Notices 49 Document Warranty 49 Limitation of Liability 49 Copyright Notice 49 Technology Licenses 49 Environmental protection 49 REACH Registration Evaluation Authorisation and Restriction of Chemicals compliance statement _ 50 RoHS Restriction of Hazardous Substances
11. maximum current of 2A per pin on the board to board SAMTEC LSHM Series Connector J16 is not available on the TE0720 03 REV3 Carrier Board anymore Instead the modules power supply is now fixed to 5V power supply Additionally the VCCIO33 and VCCIO34 supply voltages of the Zynq FPGA on bank 33 and bank 34 respectively can be selected either to be 3 3V J17 1 2 3 or 2 5V J17 1 2 3 The latter is the default setting Le VCCIO33 VCCIO34 2 5V Furthermore the VCCIO13 supply voltage bank 13 can be selected to be either identical to bank 33 34 J21 1 2 3 or to be FMC VADJ J21 1 2 3 Again the latter is the default setting i e VOCIO132FMC VADJ Note The differential signals FMC_LA17 to FMC_LA33 next to PBO to PB3 as well as YO to Y5 are routed to bank 13 of the Zynq FPGA hence the VCCIO13 supply voltage is chosen correspondingly by default The FMC power supply on the TE0701 Carrier Board e FMC_VADJ is user programmable via 12C Please consult Carrier Boards for TE0720 Configuring FMC Power Supply Voltage on TEO701 via I2C for more details Configuring 12V Power Supply Pin on the Camera Link Connector Finally a 12V power supply can be connected to pin 26 of the camera link by closing J18 However this option is disabled by default J18 OPEN Copyright 2014 Trenz Electronic GmbH Page 11 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revisi
12. 1 of TE0701 Carrier Board User Manual that is connected to a USB to multi purpose UART FIFO IC from FTDI FT2232HQ and provides a USB to JTAG interface between a host PC and the TE0701 carrier board and the TE0720 Zynq module respectively Because it acts as a USB function device no power switch is required and only a ESD protection must be provided in this case Copyright 2014 Trenz Electronic GmbH Page 10 of 50 http www trenz electronic de n e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 Configuring CPLD JTAG Mode The JTAG port of the CPLD is enabled by setting J22 on TEO701 02 REV2 or by setting DIP switch S3 on TE0701 03 REV3 A e TE0701 02 REV2 Jumper J22 labeled CPLD JTAG EN see Figure 2 has to be REMOVED to enable CPLD JTAG mode because only if the corresponding CPLD input pin JTAGENB is configured high the I O pins TDI TDO TMS and TCK will function as JTAG pins see Lattice DS135 p 4 1 Note Setting J22 CLOSED will tie JTAGENB to ground Le TDI TDO TMS and TCK will function as general purpose UO pins TE0701 03 REV3 DIP switch S3 labeled ENJTAG must be moved to OFF position Configuring Power Supply of the TE0720 Zynq SoC Module The TE7020 GigaZee board can be powered either by 3 3V J16 1 2 3 or 5 0V J16 1 2 3 The latter is the default setting e VIN 5 0V to maximize the power that can be provided to the TE0720 Gigazee board considering the
13. 2B Connector pins and are directly controlled by the module Push Button Push button S1 is connected to intelligent Carrier Controller iCC and can be used as module reset button Other usage possible actual function depend on the code loaded into iCC DIP Switch 4 bit DIP switch has following functions enable disable update of the intelligent Carrier Controller MIOO readable signal by iCC and Module e 2 Mode bits Copyright 2014 Trenz Electronic GmbH Page 46 of 50 http www trenz electronic de n e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 LEDs Module FPGA User LED s Two LED s those closer to mini USB Connector are connected to the 4x5 B2B Connector pins Those LEDs can be controlled by FPGA Module LED NetName Color B2B Module BSP Name TE0720 TE0710 TEO0712 TEO0741 D3 FLED1 Red JM2 89 TE0703_LEDS 0 U7 U8 J16 U21 D4 FLED2 Green JM2 100 TE0703 LEDS 1 R7 K6 M17 Y20 A The bank where LED s are is not powered when TE0703 is used in standalone mode VCCIO for this bank must be supplied back to the TE0703 connectors TEO703 header Pin J2 B1 must have some valid UO voltage or the LED s will not be lit System LED s Two LED s close to the microSD Card are controlled by the Control CPLD their function depends on the CPLD Version and operational mode Copyright 2014 Trenz Electronic GmbH Page 47 of 50 http www trenz electronic de e trenz electron
14. 3 3V 6 pins PXO to PX7 can be multiplexed by Texas Instruments TXS02612RTWR SDIO Port Expander to SD Card pins MIO1 bank when using TE0720 2 pins connected to TE0701 CPLD Carrier Controller PX6 and PX7 Mini CameraLink Connector Trenz 4x5 Module Socket 3x Samtec LSHM Series Connectors ADV7511 HDMI Transmitter HDMI Connector 1 4 HEAC Support Micro USB Connector Device Host or OTG Modes 2x Pmods for Zynq PL 4 differential FPGA I O Pins each User Push Button S2 RESTART see TE0701 Carrier Board User Manual User Push Buttons PBs and LEDs User Push Button S1 RESET see TE0701 Carrier Board User Manual User Push Buttons PBs and LEDs Mini USB Connector USB JTAG and UART Interface see TE0701 Carrier Board User Manual JTAG Programming Guide or TEO701 Carrier Board User Manual Connecting FTDI USB to UART FIFO Interface User LEDs function mapping depends on TE0701 CPLD Carrier Controller see TEO701 Carrier Board User Manual User Push Buttons PBs and LEDs User 4 bit DIP Switch TE0701 03 only see TEO701 Carrier Board User Manual User Push Buttons PBs and LEDs Copyright 2014 Trenz Electronic GmbH Page 7 of 50 http www trenz electronic de n e trenz e electronic Cort 4x5 Carrier Boards Overview Document Change History date revision authors description 2014 02 18 0 2 Sven Ole Voigt TE0701 03 REV3 updated 2014 01 05 0 1 Sven Ole Voigt Initial release All Sven Ole Voi
15. 4 Trenz Electronic GmbH Page 15 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 E Lattice Dame E0701xcf File Edit View Process Tools Window Help rB Ha m Sah m8mmSadae i PS 2 ZAGESHECHEG AS CQRSBS FERS 9 Hierarchy 8 x StatPage E fa Reports O Programmer TE0701 xcf 3 ER Unit File Se aie Enable Status Device Family Device Operation File Name File Date Time Checksum USERCODE Cable Settings ig Machxo2 MXO2i2994C FLASH Erase Program ent Por Custom Port HEX YO Settings Q Use Default yO Settings C Use Custom YO Settings INITN Pin Connected DONE Pin Connected TRST Pin Connected 8 set TRST High Set TRST Low Cable and 1 0 settings PROGRAMN Pin Connected ispEN Pin Connected 8 Set ispEN High Set ispEN Low ELLA D File Process Hierar Output Starting prj src add exclude C Lattice diamond 2 2 x64 bin nt64 TE0701 TE0701 xcf n Programmer device database loaded Scanning USB2 Port FTUSB 1 Starting pgr project save C Lattice diamond 2 2 x64 bin nt64 TE0701 TE0701 xcf Scan completed successfully Cannot identify detected device on row 1 Please manually select the correct device Starting prj src enable C Lattice diamond 2 2 x64 bin nt64 TE0701 TE0701 xcf i Td Console output Error Warning Ready Me
16. 5 Pin Module B2B 1 JM2 22 2 JM2 24 3 JM2 21 4 JM2 23 7 JM2 26 8 JM2 28 9 JM2 25 10 JM2 27 PMOD J6 Pin Module B2B 1 JM2 2 JM2 3 JM2 4 JM2 7 JM2 8 JM2 9 JM2 10 JM2 BSP Name TE0701 J5 GPIO 0 TE0701 J5 GPIO 1 TE0701 J5 GPIO 2 TE0701 J5 GPIO 3 TE0701 J5 GPIO 4 TE0701 J5 GPIO 5 TE0701 J5 GPIO 6 TE0701 J5 GPIO 7 BSP Name TE0701 J6 GPIO 0 TE0701 Je GPIO 1 TE0701_J6_GPIO 2 TE0701_J6_GPIO 3 TE0701 J6 GPIO 4 TE0701_J6_GPIO 5 TE0701_J6_GPIO 6 TE0701 J6 GPIO 7 TE0720 TE0710 TEO0712 TEO0741 W17 W18 Y19 AA19 W16 Y16 Y18 AA18 TE0720 TE0710 TEO0712 TEO0741 Copyright 2014 Trenz Electronic GmbH Page 35 of 50 http www trenz electronic de e trenz electronic eu 4x5 Carrier Boards Overview Revision 0 1 TE0703 Carrier Board User Manual Overview TE0703 Carrier Board 1a Co N OOS Figure 1 TE0703 REV 01 Features 1 VG96 Connector Mounting Holes and Solder Pads 2 Carrier Controller CPLD Lattice LCMXO2 1200HO 1 200 Macrocell CPLD with Block RAM Flash and PLL 4 User LEDs and 1 User Pushbutton mappable to different functions see TE0703 Carrier Board User Manual Lattice CPLD Programming 3 SDIO Port Expander with Voltage Level Translation Texas Instruments TXS02612 4 Micro SD Card Connector Zynq SDIOO Bootable SD port 5 User LEDs function mapping depends on TE0703 CPLD Carrier Controller see TE0703 Carrier Board User M
17. ACIEM R34 CG y R36 u B C110 i 18 mCill IN 299 R42 10uf TE0701 PCB with the slew rate patch applied 2 capacitors 10uF each are added in parallel to existing resistors R36 and R42 on PCB also remove C110 and C111 This fix will not repair the DCDC converter should it be already damaged Copyright 2014 Trenz Electronic GmbH Page 33 of 50 http www trenz electronic de es e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 Ethernet RJ45 TE0701 has a RJ45 MAGJACK with two LED s PHY LED s are not connected directly to the module B2B connectors as the 4x5 modules have no dedicated PHY LED pins assigned PHY LED s are connected on the TE0701 to the carrier controller that can route those LED s to some module I O Pins In that case the Module has to map the PHY LEDs to corresponding pins With initial Carrier Controller design one RJ45 LED the right one is connected to module NOSEQ pin that functions as PHY LED output on TE0720 with default settings The other LED is connected to DC GPIO Extender and can be controlled from TE0720 if desired This LED will not have PHY LED function on TEO0701 with System Controller version 0 x Copyright 2014 Trenz Electronic GmbH Page 34 of 50 http www trenz electronic de n e trenz e electronic Pmod Slots 4x5 Carrier Boards Overview Revision 0 1 J5 and J6 Pmod signal routing is done as differential pairs for pins 1 2 3 4 7 8 9 10 PMOD J
18. Copyright 2014 Trenz Electronic GmbH Page 27 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 USB Serial Converter B Einstellungen Einschalten dieses Attributes hat Vorrang vor der Gerateeinstellung IMPORTANT NOTE on Using FTDI Tools The FTDI Tool FT Prog can only be used to display the FTDI device name and to check if it is correct 9 When using FTDI USB Tools DO NOT WRITE the on board FTDI EEPROM on TE0701 All FTDI tools overwrite the user EEPROM area on each EEPROM write without any warning Erased user EEPROM will disable Xilinx tools support for the on board USB JTAG This is how on board USB JTAG should look in FT Prog Copyright 2014 Trenz Electronic GmbH Page 28 of 50 http www trenz electronic de N e trenz e electronic e 4x5 Carrier Boards Overview Revision 0 1 File Devices Help OSNa D zm Device 0 Loc ID 0x0 gt FT EEPROM 8 Chip Details Product Description zb USB Device Descriptor t USB Config Descriptor BEE sch USB String Descriptors Serial Number Enabled Auto Generate Serial No sch Hardware Specific Serial Number 777 _ or Pref 25 USB String Descriptors Allows the user to alter the manufacturer product description and serial number strings Itis not possible to use FTDI FT Prog to restore EEPROM Should the EEPROM be
19. Spreadsheet view SS 1 EDO E C ge GB EB G fa DE Package View omg o Hierarchy 8 X stata Device View Unit File TEO701 P Netlist View ax Design Sum E NCD View 4 7 Proje BF IPexpress Br TE0701 Synthesis lee 4 Proce Reveal Inserter 7E0701 Strategy Name Strategy M Mma Reveal Analyzer pus D RE Floorplan View 1CMXO2 12008C 416100C Device Family MachXo2 D Sic B Physical View LCMXO2 12008C Package Type TQFP100 Det pee con 4 S Analy Timing Analysis View TEO701 1pf D M gj Power Calculator TE0701 150701 IEO701 prf D Pid 2 ECO Editor 2 2 0 101 Patch Version D va leese DW en partition Manager Bui D Ru fl HDL Diagram DP es Synplify Pro for Lattice Active HDL Lattice Edition bin nt64 TEO701 bin nt64 TEO701 1df fB Run Manager 2 Simulation Wizard Clear Tool Memory Options i D File Process erer Output ax Starting prj project new name TE0701 impl TE0701 dev LCMXO2 1200HC 4TG100C INFO VHDL 1504 The default vhdl library search path is now C Lattice diamond 2 2 x64 cae library vhdl packages vdbs Design load finished with 0 errors ani d 0 warnings Starting prj syn set lse Starting prj project save Td Console Output Error Warning Opens Programmer View Mem Usage 133 520 K 5 Select in the Programmer Getting Started dialog the following settings
20. TB J21 1 2 3 Please note that for the first default option the FMC power supply must be manually switched on by the e g Zynq FPGA on the TE0720 for more details on configuring the FMC power supply please refer to Carrier Boards for TE0720 Configuring FMC Power Supply Voltage on TEO701 via 12C 4 bit DIP Switch TE0701 03 only Additionally on the TE0701 03 REV 3 Carrier Board a 4 bit DIP switch S3 see 21 in Figure 1 of TE0701 Carrier Board for TE07xx Series User Manual is available The default S3 mapping is as follows Name Default Mapping S3 1 CM1 Mode pin 1 routed to Carrier Controller S3 2 CMO Mode pin 0 routed to Carrier Controller S3 3 JTAGEN Set to ON for normal operation Must be moved to OFF position to enable JTAG programming mode see E0701 Carrier Board User Manual Lattice CPLD Programming for more details S3 4 MIOO Readable signal by Carrier Controller and TEO7xx Module All Connecting FTDI USB to UART FIFO Interface On TE0701 02 REV2 and TE0701 03 REV3 the UART of the FPGA e g Xilinx Zynq on the carried module can be connected to the host PC via channel B of the on board FTDI Dual USB UART FIFO IC FTDI FT2232H which is routed to the mini USB connector see 19 in Figure 1 of TEO701 Carrier Board for TE07xx Series User Manual A There is by default no USB communication when connecting the micro USB connector to the host PC see 15 in Figure 1 of TEO701 Carrier Board for
21. TEO7xx Series User Manual On a Windows 7 host PC the FTDI FT2232H USB to UART JTAG interface should be shown in the device manager as two serial converters channel A and channel B and a one virtual USB COM port Copyright 2014 Trenz Electronic GmbH Page 26 of 50 http www trenz electronic de e trenz e electronic e 4x5 Carrier Boards Overview Datei git RS P y Andere Ger te a di Anschl sse COM amp LPT Pod Kommunikationsanschluss COM1 P vad Audio Video und Gamecontroller gt JE Computer gt gf DVD CD ROM Laufwerke P 5 Eingabeger te Human Interface Devices p M Grafikkarte gt qq IDE ATA ATAPI Controller p EI Jungo gt yey Laufwerke b D M use und andere Zeigegerate Ai Monitore gt E Netzwerkadapter p D Prozessoren gt AR Systemgerate gt cm Tastaturen b KR Tragbare Ger te T USB Controller 8 Generic USB Hub 8 Generic USB Hub L Intel R 7 Series C216 Chipset Family USB Enhanced Host Controller 1E26 Intel R 7 Series C216 Chipset Family USB Enhanced Host Controller 1E2D L Intel R USB 3 0 eXtensible Hostcontroller Intel R USB 3 0 Root Hub Iw USB Serial Converter A g USB Serial Converter B USB Massenspeichergerat 8 USB Root Hub 8 USB Root Hub A USB Verbundgerat USB Verbundgerat Revision 0 1 f VCP Loading for USB Serial Converter B is enabled Note Converter A VCP Loading should be disabled
22. anual User LEDs 6 Mini USB Connector USB JTAG and UART Interface see TE0703 Carrier Board User Manual JTAG Programming Guide 7 User Push Button RESET see TE0703 Carrier Board User Manual Push Button 8 RJ45 GbE Connector 9 USB Host Connector 10 Barrel jack for 5V Power Supply 11 4A High Efficiency Power SoC DC DC Step Down Converter with Integrated Inductor Enpirion EN6347 for 3 3V Power Supply Copyright 2014 Trenz Electronic GmbH Page 36 of 50 http www trenz electronic de n e trenz e electronic Cort 4x5 Carrier Boards Overview Revision 0 1 12 Trenz 4x5 Module Socket 8x Samtec LSHM Series Conneciors 13 USB JTAG and UART Interface FTDI FT2232H compatible with Xilinx Tools also with many other tools Channel A can toggle Zynq SoC Module PS Reset Channel B can be used as USB UART TE0703 CPLD can reroute RXD TXD signals 14 User DIP Switch E Note Contrary to our TEO701 Carrier Board the TE0703 is powered by a 5V power supply Document Change History date revision authors description 2014 02 12 0 1 Antti Lukats Sven Ole Voigt Work in progress All Antti Lukats Sven Ole Voigt Copyright 2014 Trenz Electronic GmbH Page 37 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 TE0703 Jumper Configurations Jumper Configurations Intelligent Carried Controller iCC Update Mode Configuring B34 Bank Supply of th
23. articularly Xilinx IMPACT 1 Plug in 5V power supply 2 Plug a standard USB A Male to Mini B cable into the USB port of the Host PC and into the mini USB connector see 6 in Figure 1 of TE0703 Carrier Board for TEO7xx Series User Manual on the TE0703 Carrier Board 3 Open Xilinx iMPACT available with free Vivado ISE WebPack License 4 Create a new Xilinx iMPACT project Iwant to e load most recent project auto_project ipf x Browse Load most recent project file when iMPACT starts create a new project ipf default ipf 5 Select to Configure devices using Boundary Scan JTAG and choose option Auto Copyright 2014 Trenz Electronic GmbH Page 41 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 Please select an action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain M Prepare a PROM File Prepare a System ACE File Prepare a Boundary Scan File Copyright 2014 Trenz Electronic GmbH Page 42 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 When manually choosing Xilinx Impact 14 7 Cable Communication Setup then select Digilent USB JTAG Cable Note The port name TE0703 01 ID is read from FTDI User EEPROM Platform
24. compliance statement WEEE Waste Electrical and Electronic Equipment 50 50 Copyright 2014 Trenz Electronic GmbH Page 3 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 TEO0701 Carrier Board for TEOQ7xx Figure 1 TE0701 REV 01 only a limited number is released a slightly modified REV 02 is shipped to customers Copyright 2014 Trenz Electronic GmbH Page 4 of 50 http www trenz electronic de n e trenz e electronic eu 4x5 Carrier Boards Overview Revision 0 1 TE0703 Carrier Board for TEOQ7xx Figure 2 TE0703 REV 01 Document Change History date revision authors description 2014 01 05 0 1 Sven Ole Voigt Work in progress All Sven Ole Voigt Copyright 2014 Trenz Electronic GmbH Page 5 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 TE0701 Carrier Board User Manual Overview TE0701 Carrier Board U N gt N OU A Figure 1a TE0701 01 REV 01 only a limited number is released a slightly modificated REV 02 is shipped to customers N A OO N gt ou 16 Te 18 20a 19 20b 21 Figure 1b TE0701 03 REV 03 Copyright 2014 Trenz Electronic GmbH Page 6 of 50 http www trenz electronic de UIN e trenz electronic 4x5 Carrier Boards Overview Revision 0 1 Features 11 12 13 14 15 16 17 20
25. e 30 of 50 http www trenz electronic de n e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 FMC Interface FMC VADJ Control To enable FMV VADJ on TE0701 bit 7 of IC register 0x22 should be set Requirements In FPGA PS project some Zynq EC controller should be enabled and connected to EMIO For example we use l C controller 0 In FPGA PL project this controller signals should be connected to pins W20 signal HDMI SCL on TE0701 and W21 signal HDMI SDA on TEO701 Enabling FMV VADJ from U Boot In u boot configuration enable selected C bus Controller 0 in our example itdef CONFIG ZYNQ 2C define CONFIG CMD Ic define CONF G HARD 2C 7 define CONFIG SYS 2C SPEED 100000 define CONF G SYS ZC SLAVE 7 define CONF G ZYNQ C CTLR 0 Zon In u boot command line interface check that device with address 0x22 is visible zynq uboot 2c probe Valid chip addresses 22 38 39 3C 3E SF and set bit 7 by write command zyng uboot gt ZC mw 0x22 0x80 1 Enabling FMV VADJ from Linux In linux device tree selected PC controller should be enabled and configured Zo IZc 0e0004000 compatible xInx 0S7 12C 1 00 a reg lt OxE0004000 0x1000 gt interrupts 0 25 4 gt Interrupt parent amp gic Copyright 2014 Trenz Electronic GmbH Page 31 of 50 http www trenz electronic de n e trenz e electronic Cort 4x5 Carrier Boards Overview Revision 0 1 bus d
26. e TE0720 Zynq SoC Module Backup Battery Supply VBAT connector Press lt Strg gt lt Pos1 gt to return back to this overview N Jumper Configurations On the TE0703 carrier board REV1 different hardware software configurations can be chosen by the following one jumper J5 and a 4 bit DIP switch J5 default open J7 VBAT connector S2 Figure 2 TE0703 REV1 Jumper Configurations Intelligent Carried Controller iCC Update Mode Carrier Controller JTAG port is enabled by setting switch 3 on DIP switch S2 on TE0703 01 REV1 to OFF position This setting is only useful when updating Carrier Controller firmware A Switch 3 on DIP switch S2 must be moved to ON position for normal operation Otherwise the JTAG on the module would not be accessible at all Copyright 2014 Trenz Electronic GmbH Page 38 of 50 http www trenz electronic de n e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 Configuring B34 Bank Supply of the TE0720 Zynq SoC Module J5 Jumper can be used to power TE0720 bank 34 from TE0720 3 3V output rail If J5 is installed TEO720 will boot also in the case bank 34 supply is not delivered from the VG96 Pin headers If TE0720 bank supply of 3 3V is required it is recommended to insert the jumper Optionally 3 3V or any other valid IO voltage can be supplied from the TE0703 pins Backup Battery Supply VBAT connector J7 provides two pins to s
27. e d gt trenz electronic Bud 4x5 Carrier Boards Overview Date 26 6 Se ep 2014 10 35 N e trenz e electronic Bud 4x5 Carrier Boards Overview Revision 0 1 Table of Contents TEO0701 Carrier Board for TEO7xx TEO0703 Carrier Board for TEO7xx Document Change History TEO0701 Carrier Board User Manual Overview TE0701 Carrier Board Features Document Change History TE0701 Jumper Configurations c co JO Oo Om OO A Jumper Configurations c Configuring Power Supply of the Micro USB Connector Device Host or OTG Modes Configuring CPLD JTAG Mode Configuring Power Supply of the TE0720 Zynq SoC Module Configuring 12V Power Supply Pin on the Camera Link Connector TE0701 JTAG Programming Guide JTAG Programming Guide Lattice CPLD Programming Xilinx Zyng TE0720 Zynq SoC module Programming ARM JTAG Bus TE0701 Control and Data Flow with TE0720 Control and Data Flow on TE0701 and TE0720 Power On Reset POR Configuring Boot Mode User Push Buttons PBs and LEDs 4 bit DIP Switch TE0701 03 only All Connecting FTDI USB to UART FIFO Interface Intelligent Carrier Controller Function Multiplexing Interactive mode Commands Erase all Identify Info FMC Interface FMC VADJ Control Requirements Enabling FMV VADJ from U Boot Enabling FMV VADJ from Linux
28. esis E EE 7 a n d l 4 Ab Die SSES Enable Status Device Family Device Operation File Name File Date Time Checksum USERCODE Cable Settings 2 Map Trace V PASS MachXO2 LCMXO2 1200HC FLASH Erase Program Verify _ TE0701 TEO701_TEO701 jed uJ 12 09 13 20 40 55 0x060F 0x00000000 SSES E amp Verilog Simulation File f E VHDL Simulation File Cable ss sl 4 T Place amp Route Design Port EES E amp Place amp Route Trace custom Port HEX E VO Timing Analysis 4 2 Export Files VO Settings eRe Neds Use Default VO Settings 7 amp Verilog Simulation File E amp VHDL Simulation File e uil VIS JEDEC File 7 amp Bitstream File WW D p S E S E 3 a H Debug Mode pe Process Hierarchy Post Map Resour L _ Output ax Check configuration setup Successful Devicel LCMXO2 1200HC FLASH Erase Program Verify Operation Done No errors Elapsed time 00 min 14 sec Operation successful Td Console output Error Waring Mem Usage 210 112 K Ready Xilinx Zynq TE0720 Zynq SoC module Programming The Xilinx Zynq FPGA on the TE0720 Zynq SoC module can be configured by Xi inx Design Tools particularly Xilinx iMPACT 1 Plug in 12V power supply 2 Plug a standard USB A Male to Mini B cable into the USB port of the Host PC and into the mini USB connector see 19 in Figure 1 of TEO701 Carrier Board for TEO7xx Series User Manual on the TEO701 Carrier Board 3
29. gt Copyright 2014 Trenz Electronic GmbH Page 8 of 50 Revision 0 1 http www trenz electronic de n e trenz e electronic Cort 4x5 Carrier Boards Overview Revision 0 1 TE0701 Jumper Configurations Jumper Configurations Configuring Power Supply of the Micro USB Connector Device Host or OTG Modes Configuring CPLD JTAG Mode e Configuring Power Supply of the TE0720 Zynq SoC Module Configuring 12V Power Supply Pin on the Camera Link Connector Press lt Strg gt lt Pos1 gt to return back to this overview Jumper Configurations On the TEO0701 carrier board REV2 different hardware software configurations can be chosen by the following 8 TE0701 03 6 jumpers and 4 bit DIP switch TEO701 03 only J22 default closed J16 default 2 3 J18 default open J17 default 2 3 J20 default closed J9 default 1 2 J19 default closed J21 default 2 3 Figure 2a TE0701 02 REV2 Jumper Configurations Copyright 2014 Trenz Electronic GmbH Page 9 of 50 http www trenz electronic de n e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 J18 default open LL LL d PORT 1 EPR a e D 0 E S i4 3SN 009031 03 LON 0 102031 J17 default 2 3 J20 default closed J9 default 1 2 S3 4 bit DIP Switch J19 default closed J21 default 2 3 Figure 2b TE0701 03 REV3 Jumper Configurations Configuring Powe
30. he 3 3V power supply is turned on after the 1 0V and 1 8V supplies have stabilized see TE0720 Power Supply The latter is the default mode i e for the NOSEQ pin of the SC the internal pull down is activated After booting the NOSEQ pin can be used as general purpose UO pin For example the SC REV 0 02 maps the Ethernet PHY LEDO to NOSEQ by default However this mapping can be changed by software after boot PGOOD This active high signal with internal pull up is a status input to the CPLD about the current status of the power supply rails on the carried module e g TE0720 It is routed to user LED3 which is switched on when the on module power supply rails are not ok 9 For more information on the preceding signals please consult the corresponding Wiki documentation of the TE0720 System Management Controller Configuring Boot Mode The Zynq 7000 generally supports several boot modes that can be selected by five boot mode pins BOOT MODE 4 0 where BOOT MODE 4 MIO 6 enables the PLLs The other boot mode pins select the boot source in the following way see Xilinx Zyng 7000 AP SoC Technical Reference Manual UG585 v1 6 1 Table 6 2 on page 147 The TE0720 Zynq SoC Module on the TE0701 Carrier Boards supports two different boot modes QSPI and SD Card booting BOOT MODE 0 BOOT MODE 2 BOOT MODE 1 BOOT MODE 3 MIO 5 MIO 4 MIO 3 MIO 2 Cascaded JTAG 0 Independent JTAG 1 JTAG 0 0 0 0 Quad SPI 1 0 0 SD Card 1 1 0 Tab
31. ic l 8 Cort 4x5 Carrier Boards Overview Revision 0 1 Net B2B Module TE0720 1E0710 01 TEO0712 TE0741 SCL JM1 95 M13 SDA JM1 93 L18 Copyright 2014 Trenz Electronic GmbH Page 48 of 50 http www trenz electronic de n e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 Legal Notices Document Warranty The material contained in this document is provided as is and is subject to being changed at any time without notice Trenz Electronic does not warrant the accuracy and completeness of the materials in this document Further to the maximum extent permitted by applicable law Trenz Electronic disclaims all warranties either express or implied with regard to this document and any information contained herein including but not limited to the implied warranties of merchantability fitness for a particular purpose or non infringement of intellectual property Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing use or performance of this document or of any information contained herein Limitation of Liability In no event will Trenz Electronic its suppliers or other third parties mentioned in this document be liable for any damages whatsoever including without limitation those resulting from lost profits lost data or business interruption arising out of the use inability to use or the results of use of this document any documents
32. le 1 Zynq 7000 AP SoC Boot Mode MIO Pins Extract As it can be seen in Table 1 the only difference between Quaa SP and SD Cara boot mode is BOOT MODE 2 MIO 4 This is exactly the only signal which is controlled by the MODE output of the on board CPLD The BOOT MODE 0 MIO 5 and BOOT MODE 1 MIO 3 input pins are tightend correspondingly e g on the TE0720 Zynq SoC Module to pull up i e SPI DQ3 M3 PS MIOS 1 and pull down e SPI DQ1 M1 PS MIOS 0 resistors Booting from SD Card Copyright 2014 Trenz Electronic GmbH Page 24 of 50 http www trenz electronic de es e trenz e electronic Cort 4x5 Carrier Boards Overview Revision 0 1 The Quad SPI boot mode is the default option However when a SD card has been inserted into the TEO701 Carrier Board SD Card Connector see 1 in Figure 1 of TE0701 Carrier Board for TEO7xx Series User Manual the SD Card boot mode is automatically chosen by the on board CPLD because the active low SD DETECT input signal is directly mapped to the MODE output signal see Figure 4 before booting the Zynq on the carried board more precisely the BOOT MODE signals are sampled 50 PS CLK ticks after the Low to High transition of the PS POR B reset pin Moreover the LED labeled L4 on the TEO701 is switched on when a SD card is inserted Choosing between Cascaded and Independent JTAG Two different JTAG modes can be selected by the dedicated on module PJTAG R signal Cascaded JTAG BOOT
33. le signal to the power FET switch 3 3VIN gt 3 3V as well as the three Enpirion DC DC converters VIN gt 1 0V 1 5V 1 8V All LEDs are red colored and connected to the on board Lattice CPLD The default LED mapping is summarized in the following Note LED5 to LED8 have not been assigned yet Name Default Mapping LED L1 NOSEQ This active high signal switches the LED on when the power sequencing mode is disabled LED2 L2 NOT POK FMO The active high signal POK_FMC is turned on when the FMC power supply FMC VADJ is present Note FMC VADJ may be enabled when FMC is present FMC_PRSNT 1 and disabled FMC_PRSNT 0 otherwise LED3 L3 NOT PGOOD The active high signal PGOOD switches on the LED when the on module power supply is not ok LED4 L4 NOT SD DETECT SD DETECT is active low i e the LED is turned on when a SD card has been inserted Table 2 On board LEDs on TE0701 REV2 and REV3 Copyright 2014 Trenz Electronic GmbH Page 25 of 50 http www trenz electronic de n e trenz e electronic Cort 4x5 Carrier Boards Overview Revision 0 1 A LEDS L5 to LED8 L8 are operating only when the corresponding power supply VIOTB i e bank 1 of the on board CPLD is switched on This can be accomplished on the one hand by connecting the FMC power supply FMC VADJ to VIOTB J21 1 2 3 which is the default option or on the other hand by connecting either 2 5V J17 1 2 3 or 3 3V J17 1 2 3 to VIO
34. m Usage 155 240 K 7 Now the previously generated JEDEC file can be selected 1 startpage 3 D Reports 7 mmm E P Programmer Te0701 xcf s AA g S Enable Status Device Family Device Operation File Name File Date Time Checksum USERCODE Wis PASS MachXO2 LCMXO2 1200HC FLASH Erase Program Verify Um 8 and the CPLD can be flashed by pushing on the program button 2 VH Start Page O 2 CS Reports ES TE0701 lpf Programmer TE0701 xcf D e eco Enable Status Device Family Device Operation File Name File Date Time Checksum USERCODE Wis PASS MachXO2 LCMXO2 1200HC FLASH Erase Program Verify TE0701 T E0701 TEO701 jed 12 09 13 20 40 55 0x060F 0x00000000 9 Finally the successful CPLD Flash configuration operation will be confirmed in the output window Copyright 2014 Trenz Electronic GmbH Page 16 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 LC Lattice Diamond Programmer 0701xcf file Edit View Project Design Process Tools Window Help Aav raas Pax hh GERAAI AAM a E VACEBSHSCHREGASGORSODS Ip o Process S X 5 statPage O Reports O Jf TEo701 Ipf O 1 Programmer TEO701 xcf 3 sx 4 SC Synthesize Design e eco o amp Lattice Synth
35. n will appear which comprises the Processing System PS and the Programmable Logic PL that are now ready to be programmed please see related Xilinx documentation Zyng 7000 All Programmable SoC Operations in iMPACT for more details Copyright 2014 Trenz Electronic GmbH Page 19 of 50 http www trenz electronic de UIN e trenz electronic D Cort 4x5 Carrier Boards Overview Revision 0 1 L ISE iMPACT P 20131013 Boundary Scan mes We File Edit View Operations Output Debug Window Help Jels SE ACIS UE KH K ORK A iMPACT Flows enpnax 8 Boundary Scan ih ae 8 SystemACE E Create PROM File PROM File TU E WebTalk Data ynq7000 arm da xc7z020 O zynq7000 arm bypass iMPACT Processes ensx Available Operations are Identify Succeeded IE Boundary Scan Console SE enex PROGRESS END End Operation n Elapsed time 0 sec BATCH CMD identifyMPM zu r Console Configuration JTAG ONB4 10000000 Most iMPACT Boundary Scan operations performed on a Zynq 7000 AP SoC device are performed on the PL block For more information about configuring the TEO720 Zynq SoC module please consult the corresponding Trenz Electronic Wiki documentation ARM JTAG Bus To debug ARM software the user can route the ARM DAP signals PJTAG through the MIO or through the EMIO a
36. nd to PL SelectlO pins as shown in the following figure see Xilinx Zyng 7000 AP SoC Technical Reference Manual UG585 v1 6 1 Figure 27 1 on page 653 Copyright 2014 Trenz Electronic GmbH Page 20 of 50 http www trenz electronic de n e trenz e electronic Cort 4x5 Carrier Boards Overview Revision 0 1 PS Domain PL Domain Hard Logic Hard Logic ARM DAP Debug Access Port a 4 bit instructions Xilinx PL TAP ARM CPU Debug 6 bit instructions PS AXI Master Dedicated Pins in PL Domain Xilinx Platform Cable TDI TCK TMS Configurable PL SelectlO MIO Pins UGS585 c27 01 011713 Figure 27 1 JTAG System Block Diagram All dedicated signals of the ARM Debug Access Port DAP are routed to the Pmod Connector J1 see 3 in Figure 1 of TE0701 Carrier Board for TEO7xx Series User Manual and if routed through the Xilinx Zynq EMIO interface to the ARM JTAG Connector see 4 in Figure 1 of TE0701 Carrier Board for TEO7xx Series User Manual on the TEO701 Carrier Board Copyright 2014 Trenz Electronic GmbH Page 21 of 50 http www trenz electronic de n e trenz e electronic Cort 4x5 Carrier Boards Overview Revision 0 1 TE0701 Control and Data Flow with TE0720 e Control and Data Flow on TE0701 and TE0720 Power On Reset POR Configuring Boot Mode User Push Buttons PBs and LEDs 4 bit DIP Switch TE0701 03 only All Connecting FTDI USB to UART FIFO Interface Press
37. on 0 1 TE0701 JTAG Programming Guide JTAG Programming Guide Lattice CPLD Programming Xilinx Zynq TE0720 Zynq SoC module Programming ARM JTAG Bus Press lt Strg gt lt Pos1 gt to return back to this overview JTAG Programming Guide The Lattice CPLD on TE0701 carrier board as well as the Xilinx Zyng FPGA on the TE0720 GigaZee board can be programmed via JTAG In the following figures the dedicated JTAG chains are illustrated Figure 3a TE0701 REV2 and TE0720 REV1 JTAG Chains Copyright 2014 Trenz Electronic GmbH Page 12 of 50 http www trenz electronic de n e trenz e electronic Cort 4x5 Carrier Boards Overview Revision 0 1 Figure 3b TE0701 REV3 JTAG Chains As it can be seen the most convenient way to configure both devices mentioned above will be via the FTDI USB to JTAG interface that is supported by both the Lattice Diamond Design Software and the Xilinx ISE Design Suite as described in the following sections Lattice CPLD Programming EI Normally the Carrier Controller Lattice CPLD is not required to be reprogrammed However if the user would like to configure the CPLD with an own bitfile or we recommend an important firmware update in the following it is described in detail how to do so The Lattice LCMXO2 1200HC CPLD device contains two types of memory SRAM and Flash While the SRAM contains the active configuration the Flash memory provides an internal storage space fo
38. overwritten special tools are required Copyright 2014 Trenz Electronic GmbH Page 29 of 50 http www trenz electronic de n e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 Intelligent Carrier Controller Starting from rev 1 0 the Carrier Controller includes an Softcore Processor that can configure the hardware on TE0701 and implement many additional functions Function Multiplexing TODO Interactive mode In interactive mode ICC accepts simple commands over serial port UART settings 8N1 115200 baud As default when all ICC nonvolatile memory is erased TE0701 on board USB IC FTDI FT2232H channel B is used for communications If FTDI Channel B is selected as communication channel for ICC then it is disconnected from other sources Commands Erase all This command will perform a bulk erase of user flash memory of the ICC All settings and user programs stored will be lost and factory default settings for the ICC will apply Identify Info This command will display Identification and other Information about the ICC and the Carrier Board Command code i Example BAS IC gt i ID 012BA043 FMC 0 SD 1W 1 ICC returns its own JTAG IDCODE identifies the IC as Lattice XO2 1200HC FMC Card Detect 0 no card detected SD Card Detect Card detected not write protected note if no card is inserted Write Protect swith would read 1 eg not locked Copyright 2014 Trenz Electronic GmbH Pag
39. ower on PON signal that is usually HIGH weak pull up except the user push button S2 is pressed which forces the related signal to be LOW ground ENT enables EN1 1 and disables EN1 0 the supplies on the carried module respectively RESIN This signal is controlled by the user push button S1 on the TE0701 and is forwarded directly to the SC where it is latched together with the EN1 signal as well as the all power rails OK signal 1 0V and 1 8V for core 1 5V and VTT for RAM and 3 3V The 3 3V power supply rail can be switched on EN_3V3 1 or off EN_3V3 0 by a load switch TPS27082L and is continuously checked by a voltage detector TPS3805H33 Note The 3 3VIN power supply from which the 3 3V power plane is sourced is supplied by the TEO701 Carrier Board and is kept always on Copyright 2014 Trenz Electronic GmbH Page 23 of 50 http www trenz electronic de es e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 Signal Description When RESIN alias user push button S1 is not pushed and simultaneously the EN1 signal is asserted EN 1 and all power rails are ok the active high Zynq power on reset signal PS POR is asserted NOSEQ This CPLD signal can be used to enable or disable the power sequencing mode If the active high NOSEQ signal is set to HIGH NOSEQ 1 then the 1 0V and 1 8V power supplies on the carried module will be forced to be enabled In norma mode NOSEQ 0 t
40. parately By the 13 August 2005 Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge Member States shall ensure the availability and accessibility of the necessary collection facilities Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health The symbol consisting of the crossed out wheeled bin indicates separate collection for waste electrical and electronic equipment Trenz Electronic is registered under WEEE Reg Nr DE97922676 Copyright 2014 Trenz Electronic GmbH Page 50 of 50 http www trenz electronic de
41. r Supply of the Micro USB Connector Device Host or OTG Modes The TEO0701 carrier board can be configured as a USB host Hence it must provide from 5 25V to 4 75V to the board side of the downstream connection micro USB port on J12 13 To provide sufficient power a TPS2051 power distribution switch is located on the carrier board in between the 5V power supply and the Vbus signal of the USB downstream port interface If the output load exceeds the current limit threshold the TPS2051 limits the output current and pulls the overcurrent logic output OC n low which is routed to the on board CPLD The TPS2051 is put into operation by setting J19 CLOSED J20 provides an extra 100uF decoupling capacitor in addition to 10uF to further stabilize the output signal Moreover a series terminating resistor of either 1K J9 1 2 3 or 10K J9 1 2 3 is selectable on the USB VBUS signal Both signals USB VBUS and VBUS V EN that enables the TPS2051 on high are routed as well as the corresponding D data lines via the on board connector directly to the USB 2 0 high speed transceiver PHY from SMSC USB3320 on the GigaZee module which is in turn connected to the Zynq FPGA In summary the default jumper settings are the following J9 1 2 3 1K series terminating resistor J19 CLOSED TPS2051 in operation J20 CLOSED 100 pF added Additionally the TE0701 carrier board is equipped with a second mini USB port J7 see 19 in Figure
42. r the configuration data The SRAM can be configured either via the on board IEEE 1149 1 compliant FTDI USB to JTAG interface or from data stored in the CPLD s on chip Flash memory The on chip Flash can also be programmed via JTAG Configuring SRAM or Programming Flash The JEDEC file created by e g Lattice Diamond Design Software can be simple downloaded free Copyright 2014 Trenz Electronic GmbH Page 13 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 download from Lattice website to the CPLD device via the FTDI USB to JTAG interface by the following steps 1 Make sure that JTAG mode is enabled on TE0701 Carrier Board see section Jumper Configurations Configuring CPLD JTAG Mode EN e TE0701 02 REV2 Jumper J22 labeled CPLD JTAG EN see Figure 3 has to be REMOVED to enable CPLD JTAG mode e TE0701 03 REV3 DIP switch S3 labeled ENJTAG must be moved to OFF position 2 Plug in 12V power supply 3 Plug a standard USB A Male to Mini B cable into the USB port of the Host PC and into the mini USB connector see 19 in Figure 1 of TEO701 Carrier Board User Manual on the TE0701 carrier board 4 Open Lattice Diamond and choose Tools gt Programmer IE Lattice Diamond Reports File Edit View Project Design Process Tools Window Help f g i d eo oi A Mh e
43. ring the TEO720 Zynq SoC module please consult the corresponding Trenz Electronic Wiki documentation Copyright 2014 Trenz Electronic GmbH Page 44 of 50 http www trenz electronic de e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 TE0703 Control and Data Flow with TE0720 e Control and Data Flow on TE0703 and TE0720 Intelligent Carrier Controller CC Features User LEDs Push Button DIP Switch Press lt Strg gt lt Pos1 gt to return back to this overview Control and Data Flow on TE0703 and TE0720 The TE0703 Carrier Board comprises several components that can be accessed by the TE0720 Zynq SoC Module The corresponding control and data flow paths are visualized in the following figure Figure 4 Control and Data Flow on the TE0703 and the TE0720 REV1 Copyright 2014 Trenz Electronic GmbH Page 45 of 50 http www trenz electronic de n e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 Intelligent Carrier Controller iCC Features Lattice XO2 1200 TQFP100 8Bit Softcore Processor 2KByte bootrom e AKByte Instruction RAM directly writeable as RAM write only 1Kbyte Data RAM 8KByte Flash memory for code and parameter storage User LEDs There are 4 LED s total on TE0703 Two LEDS D1 and D2 are connected to the Carrier Controller their function depends on the Firmware LED s D3 and D4 are connected to the 4x5 Module B
44. upply battery backup voltage to TE0720 If not required leave open A Ensure to connect the supply battery to jumper J7 with correct polarity Copyright 2014 Trenz Electronic GmbH Page 39 of 50 http www trenz electronic de n e trenz electronic Cort 4x5 Carrier Boards Overview Revision 0 1 TE0703 JTAG Programming Guide JTAG Programming Guide Lattice CPLD Programming Xilinx Zynq TE0720 Zynq SoC module Programming Press lt Strg gt lt Pos1 gt to return back to this overview JTAG Programming Guide The Lattice CPLD on TE0703 carrier board as well as the Xilinx Zynq FPGA on the TE0720 GigaZee board can be programmed via JTAG In the following figures the dedicated JTAG chains are illustrated Figure 3 TE0703 and TE0720 REV1 JTAG Chains Lattice CPLD Programming EI Normally the Carrier Controller Lattice CPLD is not required to be reprogrammed However if the user would like to configure the CPLD with an own bitfile or we recommend an important firmware update it is similarly described for the TEO701 REV3 in TE0701 Carrier Board User Manual Lattice CPLD Programming Copyright 2014 Trenz Electronic GmbH Page 40 of 50 http www trenz electronic de e trenz electronic eu 4x5 Carrier Boards Overview Revision 0 1 Xilinx Zynq TE0720 Zynq SoC module Programming The Xilinx Zynq FPGA on the TE0720 Zynq SoC module can be configured by Xilinx Design Tools p
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