Correction for Incorrect Description Notice RL78/I1A Descriptions in
Contents
1. A UNIT mm ITEM DIMENSION S 12 3 00 10 0 30 0 65 T P 0 10 0 307905 CELLS NOTE 0 12 540 075 Each lead centerline is located within 0 10 mm of its 2 00 MAX true position T P at maximum material condition 1 70 0 10 8 10 0 20 6 10 0 10 rinimimi o n o 1 00 0 20 40 10 0 1570 05 MOLLEN 0 50 0 10 0 10 3 5 0 25 T P 0 60 0 1 5 0 25 MAX Si lt icjalvizlair x 0 15 MAX 2012 Renesas Electronics Corporation All rights reserved RENESAS Page 39 of 45 RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Correct JEITA Package Code RENESAS Code Previous Code MASS TYP g P SSOP38 0300 0 65 PRSP0038JA A P38MC 65 2A4 2 0 3 detail of lead end pl H J i K UNIT mm ITEM DIMENSIONS A 12 30 0 10 0 30 0 65 T P 0 08 0 32 0 07 0 125 0 075 2 00 MAX 1 70 0 10 8 10 0 20 6 10 0 10 1 00 0 20 0 08 0 17 9 07 0 50 0 10 0 10 EE 0 25 T P 0 60 0 15 0 25 MAX 0 15 MAX NOTE Each lead centerline is located within 0 10 mm of its true position T P at maximum material condition B C D E F G H l J K L M N P 7 U V w 2012 Renesas Electronics Corporatio2. Correct Operational amplifier ANI2 CMPOP P22 ANI4 CMP1P P24 ANIS CMP2P P25 To A D converter ANI6 CMP3P P26 analog input channel PGAOUT ANI7 CMP4P P27 gt ANI16 CMP5P RxD1 P03 gt ANI18 CMP3P CMPCOM P147 PGAINS2 PGAINS1 PGAINSO PGAEN PGAVG1 PGAVGO isi lit a i tia 4 Programmable gain amplifier input enanne seec control register PGACTL register PGAINS Internal bus R Page 44 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 21 13 3 3 Programmable gain amplifier input channel select register PGAINS Incorrect description of programmable gain amplifier input channel select register PGAINS is revised Incorrect Figure 13 4 Format of Programmable Gain Amplifier Input Channel Select Register PGAINS Address F0551H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PGAINS2 PGAINS1 PGAINSO Analog input channel for input to programmable gain amplifier ANI5 CMP2P ANI6 CMP3P or ANI18 CMP3P En oo ANI7 CMP4P 1 1 ANI16 CMP5P Other than above Setting prohibited Note Selected by the comparator input switch control register CMPSEL 20 pin products only Caution Set the PGAINS register during stop operation of the programmable gain amplifier PGAEN 0 Correct Figure 13 4 Format of Programmable Gain Amplifier Input Channel Select Register PGAINS Address F0551H After reset 00H R W Symbol
3. Timer output forend stop request sgnal timers KBD KB1 INTCMP3 Timer restart request signal timer KBO Timer output forced stop request signal timor KB1 CMPIRPIANIT IP2T INTOM Timer output forced stop request sgnal timer KE2 CMPSPLANIG FRD ROG RON Timer output forced stop request signal timor KE2 COMPCOM COMP3PISI E ANHMS PMT OU zz Comparator input switch control register CMPSH 4 vonz ws wom Window comparator function selling register CMPWDC T t t 1 T MPZ jones Jones onee Jones ones omen ORSI low o oer oem SL Comparator intemal reference Comparator internal reference Peripheral function voltage select register m CmRVM voltage control register CVACTL switch er 0 PFSELO Note 20 pin products only ANI16 CMP3P P26 is selected by default for 30 and 38 pin products Remark m 0to2 RE Page 18 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Correct Peripheral function switch register 0 PFSELO Eternal interrupt INTP20 INTP21 control block Comparator rising edge enable register CMPEGPO Comparator falling edge enable register OMPEGNT Timer restart request signal timers KED to KEO Timer output forced stop request signal timers KBD to KE2 Timer restart request signal timers KBD to KE Comparator nang edge enable register OMPECPO Comp
4. lt 1 gt mh rek Receive data 2 Xo Recewedata1 Jj data 1 ReadNe e 4 9 ST Receive data 1 Xp sP Shift operati Shift operati L En NE L d Ld Data reception T S ST Receive data 2 P SP Data reception Figure 15 93 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 1 Normal operation Normal operation STOP mode SNOOZE mode STOP mode SNOOZE mode 4 3 ST Receive data 1 X P sP Se pem emm aen L lt 2 gt 5 86 Data reception T RENESAS Receive data 1 Receive data Read N 1 4 9 ST Receive data 2 P SP Data reception lt 5 gt lt 6 gt lt 7 gt 11 lt 8 gt Page 27 of 45 RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 9 Table 20 1 Interrupt Source List 2 3 Note for the interrupt source list is added Incorrect Notes 1 The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously Zero indicates the highest priority and 40 indicates the lowest priority 2 Basic configuration types A to D correspond to A to D in Figure 20 1 _INTCMP1 INTCMP3 INTCMP4 and INTCMP5 cannot be used to clear the STOP mode Correct Notes 1 The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously Zero indicates the highest priorit
5. CPU operation status SS01 STO1 SE01 SWCO EOCO1 SSECO L Clock request signal internal signal Receive data 2 SDRO1 Receivedata1 Jf data 1 9 Read RxDO pin Shift register 01 INTSRO INTSREO TSF01 3 4 ST Receive data 1 XP sP Oise X X IL DOBBEN 3 Data reception lt 7 gt lt 12 gt ST Receive data 2 P sP Data reception Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 0 lt 4 gt S Normal operation STOP mode SNOOZE mode T Receive data 1 XP sP Data reception lt 7 gt RENESAS Normal operation ST Receive data 2 P sP DOELEN LEENT IT Data reception Page 26 of 45 RENESAS TECHNICAL UPDATE TN RL A024C E Incorrect the clock request signal internal signal timing chart is revised Incorrect CPU operation status so1 STO1 SE01 SWCO EOCO1 SSECO Clock request signal internal signal SDRO1 RxDO pin Shift register 01 INTSRO INTSREO TSFO1 Correct CPU operation status SS01 STO1 SE01 SWCO EOCO1 SSECO Clock request signal internal signal SDRO1 RxDO pin Shift register 01 INTSRO INTSREO TSFO1 Date Apr 24 2015 Figure 15 93 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 1 Normal operation Normal operation STOP mode SNOOZE mode STOP mode SNOOZE mode lt 4 gt lt 3 gt
6. RE Page 36 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 14 32 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Descriptions of the data memory STOP mode low supply voltage data retention characteristics are added Incorrect 2 7 D Memory STOP M Low Ta 40 to 105 C Vss 0 V Note The value n othe POR ection voltage When the voltage dr he data is retained befor POR reset i ffec ut is not retained when a POR r is eff STOP mode Operation mode Data retention mode A STOP instruction execution Standby release signal interrupt request Correct 32 7 RAM Data Retention Characteristics Ta 40 to 105 C Vss 0 V Note The value depends on the POR detection voltage When the voltage drops the RAM data is retained before a POR reset is effected but RAM data is not retained when a POR reset is effected Caution When CPU is operated at the voltage of out of the operation voltage range RAM data is not retained Therefore set STOP mode before the supplied voltage is below the operation voltage range STOP mode Operation mode RAM Data retention STOP instruction execution Standby release signal interrupt request Page 37 of 45 RENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 15 33 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
7. 7 6 5 4 3 2 1 0 To o o meme 1 Po rr s avon CN s mwmawcowgwer y Note Selected by the comparator input switch control register CMPSEL 20 pin products only Caution Set the PGAINS register during stop operation of the programmable gain amplifier PGAEN 0 RI Page 45 of 45 sKENESAS
8. Descriptions of the data memory STOP mode low supply voltage data retention characteristics are added Incorrect JD Memory STOP M Low Ta 40 to 125 C Note The value n othe POR ection voltage When the voltage dr he data is retained befor POR reset i ffec ut is not retained when a POR r is eff STOP mode Operation mode Data retention mode A STOP instruction execution Standby release signal interrupt request Correct 33 7 RAM Data Retention Characteristics Ta 40 to 125 C Vss 0 V Note The value depends on the POR detection voltage When the voltage drops the RAM data is retained before a POR reset is effected but RAM data is not retained when a POR reset is effected Caution When CPU is operated at the voltage of out of the operation voltage range RAM data is not retained Therefore set STOP mode before the supplied voltage is below the operation voltage range STOP mode Operation mode RAM Data retention STOP instruction execution Standby release signal interrupt request Page 38 of 45 RENESAS RENESAS TECHNICAL UPDATE TN RL A024C E 16 34 3 38 pin Products Incorrect descriptions of the package code and dimensions are revised Incorrect JEITA Package Code RENESAS Code Previous Code Date Apr 24 2015 MASS TYP g P SSOP38 6 1x12 3 0 65 PRSP0038JA B P38MC 65 GAA 2 0 3 detail of lead end
9. TKBPAFXS1p0 Comparator trigger selection for forced output stop function 2 Comparator 0 can not be used as a trigger 5 N Comparator 0 can be used as a trigger gea TKBPAFCM1p Operation mode selection for forced output stop function 2 Forced output stop function 2 starts with trigger input and forced output stop function 2 is Note 4 cleared at the next counter period Forced output stop function 2 starts with trigger input and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger Note 4 EM TKBPAHZS1p2 Comparator trigger selection for forced output stop function 1 Comparator 3 can not be used as a trigger Note 2 Comparator 3 can be used as a trigger TKBPAHZS1p1 Comparator trigger selection for forced output stop function 1 oo Comparator 2 can not be used as a trigger Comparator 2 can be used as a trigger ies TKBPAHZS1p0 Comparator trigger selection for forced output stop function 1 aw Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger Nos zu Page 12 of 45 sENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Figure 7 74 Format of Forced Output Stop Function Control Register 1p TKBPACTL1p 2 2 TKBPAHCM1p1 TKBPAHCM1p0 Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared w
10. a setting other than 0 0 is specified the specified noise elimination width is added For fcuk or fet when PLLON 1 R Page 23 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Until the timer restart function starts operating an additional clock cycle is required after the timer restart request signal is received and an additional output delay time 10 to 40 ns is required until the level of the timer KB output changes The active level of INTP20 used for forced output stop function 2 is high An additional output delay time 10 to 40 ns is required from when forced output stop function 2 starts operating to when the level of the timer KB output changes Remark n 0 2 Table 14 6 Relationship of comparator 1 3 4 and 5 functions register settings and active signal width CEGPn CEGNn To 150 ns Net 2 to 3 clocks Nete 23 Forced output stop To 150 ns Noe 4 To 150 ns Note 2 5 2 to 3 clocks Nete 4 Timer restart CEGPn CEGNn To 150 ns Ne 4 To 150 ns Ne 4 2 to 3 clocks Nete 4 2 to 3 clocks Nete 34 Figure 14 21 Generation Timing of Forced Output Stop Request Signal and Timer Restart Request Signal by External interrupt STOP release is disabled Comparator 1 3 4 and 5 to 150 ns Nete 1 CMPnP pin ja Comparator respondence time Forced output stop request signal Edge comfirming time zc 2 to 3 clocksNete2 3 1 sn Timer restart i request signal Note 5
11. gt ee lt 11 gt HoA ReadNote ST Receive data 1 P sP ST Receive data 2 P sP register 01 SL S LELOCOCS testes JC SIL L OCOCSBSest OC TT INTSRO INTSREO L TSF01 Correct Data reception T dl Data reception Figure 15 90 Timing Chart of SNOOZE Mode Operation EOCm1 0 SSECm 0 1 CPU operation status Normal operation stoPmode sNoozbEmoe mode SNOOZE mode Normal operation SS01 STO1 1 SE01 SWCO EOCO1 L SSECO L Clock request signal internal signal Receive data 2 SDRO01 Recevedaa1 Jy data 1 RxDO pin Shift 4 H9 gt a Readhete ST Receive data 1 XP sP ST Receive data 2 P sP register 01 XS aero XI LOCOCSBSES OC IT INTSRO INTSREO L TSFO1 gt Data reception lt 7 gt RENESAS Data reception Page 25 of 45 RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Incorrect the timing chart of clock request signal internal signal and SDRO1 is revised Incorrect Figure 15 91 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 0 CPU operation status Normal operation sToPmode sNoozEmode mode SNOOZE mode Normal operation SS01 STO1 1 SE01 SWCO EOCO1 SSECO L Clock request signal internal signal Receive data 2 SDRO1 Recewedata1 fJ data 1 RxDO pin Shift register 01 INTSRO INTSREO TSF01 Correct Figure 15 91
12. i Interrupt request signal i When noise filtering is set to 0 0 by using the CnDFS1 and CnDFSO bits in the comparator n control register CnCTL If a setting other than 0 0 is specified the specified noise elimination width is added For fcuk or fet when PLLON 1 Until the timer restart function starts operating an additional clock cycle is required after the timer restart request signal is received and an additional output delay time 10 to 40 ns is required until the level of the timer KB output changes The active level of INTP20 used for forced output stop function 2 is high An additional output delay time 10 to 40 ns is required from when forced output stop function 2 starts operating to when the level of the timer KB output changes The timer restart function can be used for comparator 1 and 3 only n 1 3to5 RE Page 24 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E 8 Timing Chart of SNOOZE Mode Operation p 666 667 669 Incorrect the clock request signal internal signal timing is revised Incorrect Date Apr 24 2015 Figure 15 90 Timing Chart of SNOOZE Mode Operation EOCm1 0 SSECm 0 1 CPU operation status Normal operation stop mode SNOOZE mode mode SNOOZE mode Normal operation SS01 STO1 1 SEO1 SWCO EOCO1 L SSECO L Clock request signal internal signal Receive data 2 SDRO1 1 Recevedaa1 M data 1 RxDO pin Shift 4 3 lt 12
13. the forced output stop function is kept on until timer KB is restarted TKBCEn 1 Cautions 1 During timer operation setting the other bits of the TKBPACTL2p register is prohibited However the TKBPACTL2p register can be refreshed the same value is written 2 Be sure to clear bits 11 to 9 and 7 to 0 Remark n 0to2 p 0 1 Re Page 17 of 45 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 5 Figure 14 1 Block Diagram of Comparator Incorrect names of the noise filter and the edge detection circuit in the block diagram are revised and Note is added Incorrect Peripheral function switch register 0 PFSELO TMR TMR mem SIENI STEW External interrupt INTP20 INTP21 control block Comparator nang edge enable register CMPECFO T Comparator falling edge enabte register CMPECNT INIP20PI0 Timer restart request sgnal timers KEO to KE2 Timer output forced stop request signal timers KED to KEQ NIPPI Oe Timer restart request sgnal s timers KEO to KE Externa interrupt edge enable register EGP2 EGN2 Comparator nang edge enable register COMPECEO Comparator failing edge enable register CMPEGNO Timer output forced stop request sgnal timers KBD to KE INTCMPI Timer restart request signal timer KB1 Timer output forced stop request signal Timer restart request signal timer KB2
14. timer restart disabled Timer restart function forced output stop function 2 is selected stop mode release disabled timer restart enabled Note When INTP20 or INTP21 is used as a trigger of the timer KB forced output stop function 2 or timer restart function see 14 5 Caution for Using Timer KB Simultaneous Operation Function Remark See Figure 14 1 Block Diagram of Comparator R Page 5 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 2 Figure 7 73 Format of Forced Output Stop Function Control Register Op TKBPACTLOp Incorrect descriptions of forced output stop function control register Op TKBPACTLOp are revised and Note is added Incorrect Figure 7 73 Format of Forced Output Stop Function Control Register Op TKBPACTLOp 1 2 Address F0630H no F0632H pie ae After reset 0000H R W Symbol TKBPAHZS0p1 TKBPAHZSOpO TKBPAHCMOp1 TKBPAHCMOpO TKBPAMDOp1 TKBPAMDOpO TKBPAFXSOp3 External interruption trigger selection for forced output stop function 2 oo INTP20 can not be used as a trigger TKBPAFXSOp2 Comparator trigger selection for forced output stop function 2 oo Comparator 2 can not be used as a trigger P comarstor2canbeusedasatigges i TKBPAFXS0p1 Comparator trigger selection for forced output stop function 2 Oooo Comparator 1 can not be used as a trigger 1 Comparator tcan be used as astrigger OO TKBPAFXSOpO Comparator trigger selection for forced output
15. 0 TKBPAFXS2p3 External interruption trigger selection for forced output stop function 2 0 INTP20 can not be used as a trigger TKBPAFXS2p2 Comparator trigger selection for forced output stop function 2 NET Comparator 5 can not be used as a trigger n sememerseanteusedseatpom TKBPAFXS2p1 Comparator trigger selection for forced output stop function 2 oo Comparator 3 can not be used as a trigger 1 Gomparatorscanbeusedasatrigge OO TKBPAFXS2p0 Comparator trigger selection for forced output stop function 2 a Comparator 0 can not be used as a trigger TKBPAFCM2p Operation mode selection for forced output stop function 2 RE Page 14 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Figure 7 75 Format of Forced Output Stop Function Control Register 2p TKBPACTL2p 2 2 TKBPAHZS2p2 Comparator trigger selection for forced output stop function 1 Comparator 5 can not be used as a trigger Comparator 5 can be used as a trigger TKBPAHZS2p1 Comparator trigger selection for forced output stop function 1 Comparator 4 can not be used as a trigger Comparator 4 can be used as a trigger TKBPAHZS2p0 Comparator trigger selection for forced output stop function 1 Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger TKBPAHCM2p1 TKBPAHCM2p0 Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input and forced ou
16. 015 33 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics CHAPTER 34 PACKAGE DRAWINGS Incorrect descriptions 34 3 38 pin Products revised Explanations added Re Page 2 of 45 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Document Improvement The above corrections will be made for the next revision of the hardware user s manual Corrections in the hardware user s manual Applicable Item Applicable em English Ro1UHo169EJ0210 lege in this Figure 7 19 Format of Peripheral Function Switch Register 0 o en p E Figure 7 73 Format of Forced Output Stop Function Control 380 381 n8 Register Op TKBPACTLOp pen Figure 7 74 Format of Forced Output Stop Function Control p382883 pio 5 Register 1p TKBPACTL1p p 382 383 P410 Figure 7 75 Format of Forced Output Stop Function Control Register 2p TKBPACTL2p p 384 385 p 14 5 Figure 14 1 Block Diagram of Comparator p 527 Figure 14 12 Format of Peripheral Function Switch Register pa Jole ES Et 7 14 5 Caution for Using Timer KB Simultaneous Operation Function p 8 Timing Chart of SNOOZE Mode Operation p 666 667 669 9 Table 20 1 Interrupt Source List 2 3 p 898 95 Figure 20 1 Basic Configuration of Interrupt Function p 900 EN Table 21 1 Operating Statuses in HALT Mode 2 2 p 931 NN Table 21 2 Operating Statuses in STOP Mode p 936 EN Table 21 3 Operating Statuses in S
17. 1 TKBPAMDOpO TKBPAFXSOp3 External interruption trigger selection for forced output stop function 2 INTP20 can not be used as a trigger ote 1 INTP20 can be used as a trigger N TKBPAFXSOp2 Comparator trigger selection for forced output stop function 2 Comparator 2 can not be used as a trigger Comparator 2 can be used as a trigger otea TKBPAFXS0p1 Comparator trigger selection for forced output stop function 2 Comparator 1 can not be used as a trigger Comparator 1 can be used as a trigger Nees TKBPAFXSOpO Comparator trigger selection for forced output stop function 2 Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger Nona TKBPAFCMOp Operation mode selection for forced output stop function 2 Forced output stop function 2 starts with trigger input and forced output stop function 2 is Note4 cleared at the next counter period Forced output stop function 2 starts with trigger input and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger Note 4 EN TKBPAHZS0p2 Comparator trigger selection for forced output stop function 1 Comparator 2 can not be used as a trigger Note 2 Comparator 2 can be used as a trigger TKBPAHZS0p1 Comparator trigger selection for forced output stop function 1 oo Comparator 1 can not be used as a trigger Comparator 1 can be used as a trigger ies TKBPAHZSOpO Comparator tr
18. 15 12 Table 21 2 Operating Statuses in STOP Mode Incorrect description about the comparator operation in STOP mode is revised Incorrect STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on High speed On chip Oscillator X1 Clock fx External Main System Clock Clock fiu fex System clock Clock supply to the CPU is stopped Main system clock Stopped Subsystem clock Status before STOP mode was set is retained fi Set by bits 0 WDSTBYON and 4 WDTON of option byte 000C0H and WUTMMCKO bit of operation speed mode control register OSMC e WUTMMCKO 1 Oscillates e WUTMMCKO 0 and WDTON 0 Stops e WUTMMCKO 0 WDTON 1 and WDSTBYON 1 Oscillates e WUTMMCKO 0 WDTON 1 and WDSTBYON 0 Stops CPU Operation stopped Code flash memory Data flash memory RAM Port latch Status before STOP mode was set is retained Timer array unit Operation disabled Timer KBO to KB2 Timer KCO Real time clock RTC Operable 12 bit interval timer Watchdog timer See CHAPTER 11 WATCHDOG TIMER A D converter Wakeup operation is enabled switching to the SNOOZE mode Programmable gain amplifier Operable Comparator erabl nly for channel ncellation of STOP mode and when digital filter i not used Omitted R Page 33 of 45 sKENESAS RENESAS TE
19. 2 Omitted RI Page 34 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 13 Table 21 3 Operating Statuses in SNOOZE Mode Incorrect description about the comparator operation in SNOOZE mode is revised Incorrect STOP Mode Setting When Inputting CSI00 UARTO Data Reception Signal or A D Converter Timer Trigger Signal System clock While in STOP Mode When CPU Is Operating on High speed On chip Oscillator Clock fix Clock supply to the CPU is stopped Main system clock Operation started Subsystem clock Stopped Use of the status while in the STOP mode continues fi Set by bits 0 WDSTBYON and 4 WDTON of option byte 000COH and WUTMMCKO bit of operation speed mode control register OSMC e WUTMMCKO 1 Oscillates e WUTMMCKO 0 and WDTON 0 Stops e WUTMMCKO 0 WDTON 1 and WDSTBYON 1 Oscillates e WUTMMCKO 0 WDTON 1 and WDSTBYON 0 Stops CPU Code flash memory Data flash memory RAM Operation stopped Port latch Use of the status while in the STOP mode continues Timer array unit Timer KBO to KB2 Timer KCO Operation disabled Real time clock RTC 12 bit interval timer Operable Watchdog timer See CHAPTER 11 WATCHDOG TIMER A D converter Operable Programmable gain amplifier Operable Comparator Qperabl ncellation of STOP mode and when digital filt
20. 3 TKBO11 TKCOO2 INTP20 O P204 TKBO20 TKCO03 P205 TKBO21 TKCO04 DALITxD4 OANA UNBWN Correct O P20 ANIO AVrere O P03 RxD1 CMP5P ANI16 O P02 TxD1 ANI17 O O P21 ANI1 AVrerm O P22 ANI2 CMPOP O P24 ANI4 CMP1P P25 ANI5 CMP2P P26 ANI6 CMP3P P27 ANI7 CMP4P P147 CMPCOM ANI18 O P10 TxDO TKCOO00 INTP20 SCLAO DALITxD4 P11 RxDO TKCOO1 INTP21 SDAAO TIO7 DALIRXD4 TxRx4 INTPO P200 TKBOO0 INTP22 O P201 TKBOO1 O P202 TKBO10 INTP21 P31 T103 TO03 INTP4 P203 TKBO1 1 TKCOO2 INTP20 P77 INTP11 O O P204 TKBO20 TKCO03 P206 TKCO05 DALIRxD4 TxRx4 INTP23 O P205 TKBO21 TKCO04 DALITxD4 1 2 3 4 5 6 7 8 RE Page 42 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E 19 1 3 3 38 pin products Incorrect alternate function pin is revised Incorrect P20 ANIO AVreFe PO3 RxD1 CMP5P ANI16 P02 TxD1 ANI17 P120 ANI19 P40 TOOLO RESET P124 XT2 EXCLKS P123 XT1 P137 INTPO P122 X2 EXCLK P121 X1 REGC Vss Voo P31 T103 TO03 INTP4 P77 INTP11 P76 INTP10 P75 INTP9 P06 TIO6 TOO6 Correct P20 ANIO AVrerP P03 RxD1 CMP5P ANI16 P02 TxD1 ANI17 P120 ANI19 P40 TOOLO RESET P124 XT2 EXCLKS P123 XT1 P137 INTPO P122 X2 EXCLK P121 X1 REGC Vss Voo P31 1103 TO03 INTP4 P77 INTP11 P76 INTP10 P75 INTP9 P06 TIO6 TOO6 2 KO WON AU d WN OANA UR WN OO ce dou 06K O O Date Apr 24 2015 P21 ANI1 AVrerm P22 ANI2 CMPOP P2
21. 4 ANI4 CMP1P P25 ANI5 CMP2P P26 ANI6 CMP3P P27 ANI7 CMP4P P147 CMPCOM ANI18 P10 SO00 TxD0 TKCO00 INTP20 SCLA0 DALITxD4 P11 SIO0 RXDO TKCOO1 INTP21 SDAAO TIOZ DALIRXDA TXRx4 P12 SCKO0 TKCOO3 P200 TKBOO0 INTP22 P201 TKBOO1 P202 TKBO10 INTP21 P203 TKBO1 1 TKCOO2 INTP20 P204 TKBO20 TKCO03 P205 TKBO21 TKCO04 DALITxD4 P206 TKCOO05 DALIRXDA TXRx4 INTP23 P30 INTP3 RTC1HZ P05 TIO5 TOO5 P21 ANI1 AVrerm P22 ANI2 CMPOP P24 ANI4 CMP1P P25 ANI5 CMP2P P26 ANI6 CMP3P P27 ANI7 CMP4P P147 CMPCOM ANI18 P10 SO00 TxDO TKCOO0 INTP20 SCLAO DALITxD4 P11 SIO0 RXDO TKCOO1 INTP21 SDAAO TIO7 DALIRXDA TxRx4 INTPO P12 SCKOO TKCOO3 P200 TKBOO0 INTP22 P201 TKBOO1 P202 TKBO10 INTP21 P203 TKBO11 TKCO02 INTP20 P204 TKBO20 TKCO03 P205 TKBO21 TKCO04 DALITxD4 P206 TKCO05 DALIRxD4 TXRx4 INTP23 P30 INTP3 RTC1HZ P05 TIO5 TOO5 Page 43 of 45 RENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 20 Figure 13 1 Block Diagram of Operational Amplifier Incorrect block diagram is revised Incorrect Operational amplifier ANIG CMP3PIP26 ANI18 CMP3PY CMPOOM P147 te ANI2 CMPOP P22 ANI4 CMP1P P24 ANI5 CMP2P P25 To A D converter analog input channel PGAOUT ANI7 CMP4P P27 ANI16 CMPSP RxD1 P03 Comparator input switch duced pmet Programmable gain amplifier control register CMPSA register PGAINS control register PGACTL Internal bus
22. CHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Correct STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock System clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on High speed On chip Oscillator X1 Clock fx External Main System Clock Clock fix fex Clock supply to the CPU is stopped Main system clock Stopped Subsystem clock Status before STOP mode was set is retained fi Set by bits 0 WDSTBYON and 4 WDTON of option byte 000COH and WUTMMCKO bit of operation speed mode control register OSMC e WUTMMCKO 1 Oscillates e WUTMMCKO 0 and WDTON 0 Stops e WUTMMCKO 0 WDTON 1 and WDSTBYON 1 Oscillates e WUTMMCKO 0 WDTON 1 and WDSTBYON 0 Stops CPU Code flash memory Data flash memory RAM Operation stopped Port latch Status before STOP mode was set is retained Timer array unit Timer KBO to KB2 Timer KCO Operation disabled Real time clock RTC 12 bit interval timer Operable Watchdog timer A D converter See CHAPTER 11 WATCHDOG TIMER Wakeup operation is enabled switching to the SNOOZE mode Programmable gain amplifier Operable Comparator Only CMPO and CMP2 are operable when the STOP mode cancel is set CMPnSTEN 1 in the PFSELO register by the comparator interrupt detection and the noise filter is not used n 0
23. Date Apr 24 2015 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Document No Product Category MPU MCU 3 00 TN RL A024C E Rev Correction for Incorrect Description Notice RL78 11A Descriptions in the Hardware User s Manual Rev 2 10 Changed Information Tig Category Technical Notification Lot No RL78 11A User s Manual Hardware Rev 2 10 R01UHO0169EJ0210 Jul 2013 Reference Document Applicable Product RL78 11A Group R5F107xxx All lot This document describes misstatements found in the RL78 11A hardware user s manual Rev 2 10 RO1UH0169EJ0210 List of corrections to be added in this notification Incorrect descriptions revised Incorrect descriptions Revised Incorrect descriptions Revised Incorrect descriptions 1 3 Pin Configuration 1 3 1 20 pin products 1 3 Pin Configuration 1 3 2 30 pin products 1 3 Pin Configuration 1 3 3 38 pin products Figure 13 1 Block Diagram of Operational Amplifier Revised 13 3 3 Programmable gain amplifier input channel select register PGAINS Incorrect descriptions revised List of corrections of notified Correction Item Applicable Page Figure 7 19 Format of Peripheral Function Switch Register 0 PFSELO Figure 7 73 Format of Forced Output Stop Function Control Register Op TKBPACTLOp p 303 p 380 381
24. HNICAL UPDATE TN RL A024C E Date Apr 24 2015 Correct Figure 7 75 Format of Forced Output Stop Function Control Register 2p TKBPACTL2p 1 2 Address FO6BOH TKBPACTL20 FO6B2H TKBPACTL21 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 TKBPACTL2p TKBPAFXS2p3 TKBPAFXS2p2 TKBPAFXS2p1 TKBPAFXS2p0 foo o o TKBPAFCM2p 7 6 5 4 3 2 1 0 0 _ TKBPAHZS2p2 TKBPAHZS2p1 TKBPAHZS2p0 TKBPAHCM2p1 TKBPAHCM2p0 TKBPAMD2p1 TKBPAMD2p0 TKBPAFXS2p3 External interruption trigger selection for forced output stop function 2 INTP20 can not be used as a trigger ote 1 INTP20 can be used as a trigger N TKBPAFXS2p2 Comparator trigger selection for forced output stop function 2 Comparator 5 can not be used as a trigger a 2 Comparator 5 can be used as a trigger iis TKBPAFXS2p1 Comparator trigger selection for forced output stop function 2 Comparator 3 can not be used as a trigger Comparator 3 can be used as a trigger Note TKBPAFXS2p0 Comparator trigger selection for forced output stop function 2 Comparator 0 can not be used as a trigger 5 N Comparator 0 can be used as a trigger gea TKBPAFCM2p Operation mode selection for forced output stop function 2 Forced output stop function 2 starts with trigger input and forced output stop function 2 is Note 4 cleared at the next counter period Forced output stop function 2 starts with trigger input and forced output stop function 2 is cleared at t
25. Incorrect descriptions revised Incorrect descriptions revised Figure 7 74 Format of Forced Output Stop Function Control Register 1p TKBPACTL1p p 382 383 Incorrect descriptions revised Figure 7 75 Format of Forced Output Stop Function Control Register 2p TKBPACTL2p p 384 385 Incorrect descriptions revised Figure 14 1 Block Diagram of Comparator p 527 Incorrect descriptions revised Figure 14 12 PFSELO Format of Peripheral Function Switch Register 0 p 538 Incorrect descriptions revised 14 5 Caution for Using Timer KB Simultaneous Operation Function Timing Chart of SNOOZE Mode Operation p 666 667 669 Caution added Incorrect revised descriptions Table 20 1 Interrupt Source List 2 3 p 898 Caution added Figure 20 1 Basic Configuration of Interrupt Function p 900 Incorrect descriptions revised Table 21 1 Operating Statuses in HALT Mode 2 2 p 931 Incorrect revised descriptions Table 21 2 Operating Statuses in STOP Mode p 936 Incorrect revised descriptions Table 21 3 Operating Statuses in SNOOZE Mode p 942 Incorrect revised descriptions 32 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics p 1100 Explanations added c 2015 Renesas Electronics Corporation All rights reserved RENESAS Page 1 of 45 RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2
26. KO 0 and WDTON 0 Stops e WUTMMCKO 0 WDTON 1 and WDSTBYON 1 Oscillates e WUTMMCKO 0 WDTON 1 and WDSTBYON 0 Stops CPU Code flash memory Data flash memory RAM Operation stopped Port latch Status before HALT mode was set is retained Timer array unit Timer KBO to KB2 Timer KCO Operable when the RTCLPC bit is 0 operation is disabled when the RTCLPC bit is not 0 Real time clock RTC 12 bit interval timer Operable Watchdog timer A D converter See CHAPTER 11 WATCHDOG TIMER Operation disabled Programmable gain amplifier Operable However this is not used since the operation has been disabled for the A D converter that is the destination for input of the PGA output signal Comparator rable When in the low consumption RTC mode RTCLPC 1 in the MC register thi n us nly when the STOP m cancel is s MPnSTEN 1 in the PESELO register he comparator interr ion and the noise filter is n n 0 2 Omitted R Page 31 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Correct HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock System clock When CPU Is Operating on XT1 Clock fxr When CPU Is Operating on External Subsystem Clock fexs Clock supply to the CPU is stopped Main system clock Operation disabled Subsystem clock Operation continues c
27. NOOZE Mode p 942 32 7 Data Memory STOP Mode Low Supply Voltage Data 1100 37 Retention Characteristics p P 33 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics i CHAPTER 34 PACKAGE DRAWINGS 34 3 38 pin Products i 1 3 Pin Configuration 1 3 2 30 pin products 1 3 Pin Configuration 1 3 3 38 pin products Figure 13 1 Block Diagram of Operational Amplifier 13 3 3 Programmable gain amplifier input channel select register PGAINS Incorrect Bold with underline Correct Gray hatched 18 19 IN Issued Document History RL78 I1A Incorrect description notice issued document history Document Number Issue Date Description TN RL A024A E Apr 9 2014 First edition issued TN RL A024B E Nov 21 2014 Second edition issued Incorrect descriptions No 16 added TN RL A024C E Apr 24 2015 Third edition issued Incorrect descriptions No 17 to No 21 added this document R Page 3 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 1 Figure 7 19 Format of Peripheral Function Switch Register 0 PFSELO Incorrect descriptions of the TMRSTEN1 and TMRSTENO bits of Peripheral Function Switch Register 0 PFSELO are revised and Note is added Incorrect Figure 7 19 Format of Peripheral Function Switch Register 0 PFSELO Address F05C6H After reset 00H Symbol CMP2STEN CMPOSTEN Comparator interrupt selection See CHAPTER 14 COMPARATOR PNFEN Use Do not use e
28. Table 14 5 Relationship of comparator 0 and 2 functions register settings and active signal width External interrupt CMPnSTEN 1 Rising edge only To 150 ns STOP release is pone enabled Nete 1 External interrupt CMPnSTEN 0 CEGPn CEGNn To 150 ns N 3 STOP release is 2 to 3 clocks 5 disabled Forced ouputston cwersten i Notes Toron Toron Timer restart CMPnSTEN 0 CEGPn CEGNn To 150 ns Ne To 150 ns NS 4 2 to 3 clocks 2 to 3 clocks Figure 14 19 Generation Timing of Forced Output Stop Request Signal by Comparator 0 and 2 CMPnSTEN 1 GMENE pin Comparator respondence time to 150 ns Nete 3 Forced output stop request signal Interrupt request signal Figure 14 20 Generation Timing of Timer Restart Request Signal by Comparator 0 and 2 CMPnSTEN 0 CME ne pin Comparator respondence time Pa NN to 150 ns Nete 3 Comparator output signal i Edge comfirming time Xe 2 to 3 clocksNete 4 5 1 De D Timer restart request signal i Interrupt request signal i Notes 1 When noise filtering is set to 0 0 by using the CnDFS1 and CnDFSO bits in the comparator n control register CnCTL To change the level of the edge direction invert the comparator output signal by using the CnINV bit in the comparator n control register CnCTL This is the time required when noise filtering is set to 0 0 by using the CnDFS1 and CnDFSO bits in the comparator n control register CnCTL If
29. annot be stopped Cannot operate Cannot operate Operation continues cannot be stopped fi Set by bits 0 WDSTBYON and 4 WDTON of option byte 000CO0H and WUTMMCKO bit of operation speed mode control register OSMC e WUTMMCKO 1 Oscillates e WUTMMCKO 0 and WDTON 0 Stops e WUTMMCKO 0 WDTON 1 and WDSTBYON 1 Oscillates e WUTMMCKO 0 WDTON 1 and WDSTBYON 0 Stops CPU Code flash memory Data flash memory RAM Operation stopped Port latch Status before HALT mode was set is retained Timer array unit Timer KBO to KB2 Timer KCO Operable when the RTCLPC bit is 0 operation is disabled when the RTCLPC bit is not 0 Real time clock RTC 12 bit interval timer Operable Watchdog timer A D converter See CHAPTER 11 WATCHDOG TIMER Operation disabled Programmable gain amplifier Operable However this is not used since the operation has been disabled for the A D converter that is the destination for input of the PGA output signal Comparator Only CMPO and CMP2 are operable When in the low consumption RTC mode RTCLPC 1 in the OSMC register CMPn can be used only when the STOP mode cancel is set CMPnSTEN 1 in the PFSELO register by the comparator interrupt detection and the noise filter is not used n 0 2 Omitted RE Page 32 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 20
30. arator falling edge enable register OMPEGNO Timer output forced stop request sgnal timers KBD to KE INTCMP1 Timer restart request signal timer KB1 Timer output forced stop request sgnal timer KEO CMP2STEN Timer restart request signal timer KB2 fe Timer output forced stop request signal timers KED KBI INTCMP3 Timer restart request signal timer KBO Timer output forond stop request sgnal timer KB1 J e INTO Timer output forced stop request signal timer KE2 CMPSPLANTGIRIDU POS NIS Timer output forced stop request sgnal timer KEO POMM e ANMUPIAT 5 Comparator input switch control register CMPS Window comparator function setting register OMPWOC Va Avew ANIUP21 CMP2 meses or ew Comparator internal reference Penpheral function voltage control register CVACTL switch register 0 PFSELO Note 20 pin products only ANI16 CMP3P P26 is selected by default for 30 and 38 pin products Caution When INTP20 INTP21 and comparator are used as the timer KB forced output stop function 2 or timer KB restart function see 14 5 Caution for Using Timer KB Simultaneous Operation Function Remark m 0to2 RE Page 19 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 6 Figure 14 12 Format of Peripheral Function Switch Register 0 PFSELO Incorrect descriptions of the comparator and external inte
31. as the forced output stop function 2 see 14 5 Caution for Using Timer KB Simultaneous Operation Function When CMP3 is used as the timer KB forced output stop function see 14 5 Caution for Using Timer KB Simultaneous Operation Function When CMPO or CMP2 is used as the timer KB forced output stop function set CMPnSTEN 1 For details see 14 5 Caution for Using Timer KB Simultaneous Operation Function When timer KB is stopped TKBCEn 0 without waiting for the next counter period the forced output stop function is kept on until timer KB is restarted TKBCEn 1 Cautions 1 During timer operation setting the other bits of the TKBPACTL1p register is prohibited However the TKBPACTL1p register can be refreshed the same value is written 2 Be sure to clear bits 11 to 9 and 7 to 0 Remark n 0to2 p 0 1 R Page 13 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 4 Figure 7 75 Format of Forced Output Stop Function Control Register 2p TKBPACTL2p Incorrect descriptions of forced output stop function control register 2p TKBPACTL2p are revised and Note is added Incorrect Figure 7 75 Format of Forced Output Stop Function Control Register 2p TKBPACTL2p 1 2 Address FO6BOH ub E FO6B2H T After reset 0000H R W Symbol TKBPACTL2p TKBPAFXS2p3 TKBPAFXS2p2 TKBPAFXS2p1 TKBPAFXS2p0 TT TKBPAFCM2p ONE TKBPAHZS2p1 TKBPAHZS2p0 TKBPAHCM2p1 TKBPAHCM2p0 TKBPAMD2p1 TKBPAMD2p
32. d output stop function 1 starts with trigger input and forced output stop function 1 is cleared at the next counter period after forced output stop function release trigger TKBPAHTT2p 1 is written regardless of the trigger signal level 1 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing forced output stop function release trigger TKBPAHTT2p 1 is invalid Forced output stop function 1 is cleared at the next counter period after forced output stop function release trigger TKBPAHTT2p 1 is written when the trigger signal is in its inactive period TKBPAMD2p1 TKBPAMD2p0 Output status selection when executing forced output stop function 0 o j HMzotu Oupufwedatlowvl o0 1 PHouput Oupufredathighievel HM Output fixed at low level Output fixed at low level Output fixed at high level Output fixed at high level Notes 1 When INTP20 is used as the forced output stop function 2 see 14 5 Caution for Using Timer KB Simultaneous Operation Function When CMP4 or CMP5 is used as the timer KB forced output stop function see 14 5 Caution for Using Timer KB Simultaneous Operation Function When CMPO is used as the timer KB forced output stop function set CMPOSTEN 1 For details see 14 5 Caution for Using Timer KB Simultaneous Operation Function When timer KB is stopped TKBCEn 0 without waiting for the next counter period
33. er i not used oly for channels se nabl Omitted zu Page 35 of 45 sENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Correct STOP Mode Setting When Inputting CSIOO UARTO Data Reception Signal or A D Converter Timer Trigger Signal While in STOP Mode When CPU Is Operating on High speed On chip Oscillator Clock fix System clock Clock supply to the CPU is stopped Main system clock Operation started Stopped Subsystem clock Use of the status while in the STOP mode continues fi Set by bits 0 WDSTBYON and 4 WDTON of option byte 000C0H and WUTMMCKO bit of operation speed mode control register OSMC e WUTMMCKO 1 Oscillates e WUTMMCKO 0 and WDTON 0 Stops e WUTMMCKO 0 WDTON 1 and WDSTBYON 1 Oscillates e WUTMMCKO 0 WDTON 1 and WDSTBYON 0 Stops CPU Operation stopped Code flash memory Data flash memory RAM Port latch Use of the status while in the STOP mode continues Timer array unit Operation disabled Timer KBO to KB2 Timer KCO Real time clock RTC Operable 12 bit interval timer Watchdog timer See CHAPTER 11 WATCHDOG TIMER A D converter Operable Programmable gain amplifier Operable Comparator Only CMPO and CMP2 are operable when the STOP mode cancel is set CMPnSTEN 1 in the PFSELO register by the comparator interrupt detection and the noise filter is not used n 0 2 Omitted
34. function the timer KB forced output stop function and timer restart function the interrupt signal pass and the interrupt generation timing and the edge enable register for INTP20 and INTP21 and INTCMPm vary For details see 14 5 Caution for Using Timer KB Simultaneous Operation Function Remark Interrupt request flag Interrupt enable flag In service priority flag O In service priority flag 1 Interrupt mask flag Priority specification flag 0 Priority specification flag 1 20 pin n 0 20 21 22 m 0to3 30 pin n 0 4 11 20 to 23 m 0to5 38 pin n20 3 4 9t0 11 20 to 23 m 0to5 RENESAS Page 30 of 45 RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 11 Table 21 1 Operating Statuses in HALT Mode 2 2 Incorrect description about the comparator operation in HALT mode is revised Incorrect HALT Mode Setting System clock When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When CPU Is Operating on XT1 Clock fxr When CPU Is Operating on External Subsystem Clock fexs Clock supply to the CPU is stopped Main system clock Operation disabled Subsystem clock Operation continues cannot be stopped Cannot operate Cannot operate Operation continues cannot be stopped fi Set by bits 0 WDSTBYON and 4 WDTON of option byte 000COH and WUTMMCKO bit of operation speed mode control register OSMC e WUTMMCKO 1 Oscillates e WUTMMC
35. ger TKBPAHZS1p1 Comparator trigger selection for forced output stop function 1 Comparator 2 can not be used as a trigger Comparator 2 can be used as a trigger TKBPAHZS1p0 Comparator trigger selection for forced output stop function 1 Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger TKBPAHCM1p1 TKBPAHCM1p0 Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared when Hi Z stop trigger TKBPAHTT1 1 is written regardless of the trigger signal level 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing Hi Z stop trigger IKBPAHTT1 1 is invalid Forced output stop function 1 is cleared when Hi Z stop trigger TKBPAHTT1 1 is written while the trigger signal is in its inactive period 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared at the next counter period after Hi Z stop trigger TKBPAHTT1 1 is written regardless of the trigger signal level 1 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing Hi Z stop trigger IKBPAHTT1 1 is invalid Forced output stop function 1 is cleared at the next counter period after Hi Z stop trigger TKBPAHTT1 1 is written when the trigger signal is in i
36. he next counter period following detection of the reverse edge of the trigger Note 4 EN TKBPAHZS2p2 Comparator trigger selection for forced output stop function 1 Comparator 5 can not be used as a trigger Note 2 Comparator 5 can be used as a trigger TKBPAHZS2p1 Comparator trigger selection for forced output stop function 1 oo Comparator 4 can not be used as a trigger Comparator 4 can be used as a trigger ieee TKBPAHZS2p0 Comparator trigger selection for forced output stop function 1 oo Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger Noreg R Page 16 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Figure 7 75 Format of Forced Output Stop Function Control Register 2p TKBPACTL2p 2 2 TKBPAHCM2p1 TKBPAHCM2p0 Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared when forced output stop function release trigger TKBPAHTT 2p 1 is written regardless of the trigger signal level 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing forced output stop function release trigger TKBPAHTT2p 1 is invalid Forced output stop function 1 is cleared when forced output stop function release trigger TKBPAHTT2p 1 is written while the trigger signal is in its inactive period 1 Force
37. hen forced output stop function release trigger TKBPAHTT1p 1 is written regardless of the trigger signal level 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing forced output stop function release trigger TKBPAHTT1p 1 is invalid Forced output stop function 1 is cleared when forced output stop function release trigger TKBPAHTT1p 1 is written while the trigger signal is in its inactive period 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared at the next counter period after forced output stop function release trigger TKBPAHTT1p 1 is written regardless of the trigger signal level 1 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing forced output stop function release trigger TKBPAHTT1p 1 is invalid Forced output stop function 1 is cleared at the next counter period after forced output stop function release trigger TKBPAHTT1p 1 is written when the trigger signal is in its inactive period TKBPAMD1p1 TKBPAMD1p0 Output status selection when executing forced output stop function 0 o Hezoutput Outputtixedatiowlevel o0 1 PHouput Oupufredathighievel HM Output fixed at low level Output fixed at low level Output fixed at high level Output fixed at high level Notes 1 When INTP20 is used
38. igger selection for forced output stop function 1 o Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger Norea R Page 8 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Figure 7 73 Format of Forced Output Stop Function Control Register Op TKBPACTLOp 2 2 TKBPAHCMOp1 TKBPAHCMOpO Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared when forced output stop function release trigger TKBPAHTTOp 1 is written regardless of the trigger signal level 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing forced output stop function release trigger TKBPAHTTOp 1 is invalid Forced output stop function 1 is cleared when forced output stop function release trigger TKBPAHTTOp 1 is written while the trigger signal is in its inactive period 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared at the next counter period after forced output stop function release trigger TKBPAHTTOp 1 is written regardless of the trigger signal level Noten 1 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing forced output stop function release trigger TKBPAHTTOp 1 is invalid Forced outp
39. n All rights reserved RI Page 40 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 17 1 3 1 20 pin products Incorrect alternate function pin is revised Incorrect P21 ANI1 AVrerm O O P22 ANI2 CMPOP P20 ANIO AVrere O P24 ANI4 CMP1P P40 TOOLO O O P25 ANI5 CMP2P O P147 CMPCOM ANI18 CMP3P O P10 TxDO TKCOOO INTP20 SCLAO DALITxD4 O PLI RSDO TKCOOVINTP2 USDAAQ TIOZ DALIRXD4 CD R4 O P200 TKBOO0 INTP22 O P201 TKBOO1 O P202 TKBO10 INTP21 P203 TKBO11 TKCOO2 INTP20 Correct O P21 ANI1 AVrerm O P20 ANIO AVrerp O O P22 ANI2 CMPOP O P24 ANI4 CMP1P O P25 ANI5 CMP2P P147 CMPCOM ANI18 CMP3P O P10 TxDO TKCOOO INTP20 SCLAO DALITxD4 O P11 RxDO TKCOO1 INTP21 SDAAO TIO7 DALIRXD4 TxRx4 INTPO O P200 TKBOOO INTP22 O P201 TKBOO1 P202 TKBO10 INTP21 P203 TKBO1 1 TKCOO2 INTP20 1 2 3 4 5 6 7 8 9 1 o RE Page 41 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 18 1 3 2 30 pin products Incorrect alternate function pin is revised Incorrect O P20 ANIO AVnere O P03 RxD1 CMP5P ANI16 O P02 TxD1 ANI17 O O P21 ANI1 AVrerm O P22 ANI2 CMPOP O P24 ANI4 CMP1P P25 ANI5 CMP2P O P26 ANI6 CMP3P O P27 ANI7 CMP4P P147 CMPCOM ANI18 O P10 TxD0 TKCO00 INTP20 SCLAO DALITxD4 P11 RxD0 TKCO01 INTP21 SDAAO TI07 DALIRxD4 TxRx4 O P200 TKBOOO INTP22 P201 TKBOO1 P202 TKBO10 INTP21 P20
40. ol Register 1p TKBPACTL1p Incorrect descriptions of forced output stop function control register 1p TKBPACTL1p are revised and Note is added Incorrect Figure 7 74 Format of Forced Output Stop Function Control Register 1p TKBPACTL1p 1 2 Address F0670H 2 F0672H a 1 After reset 0000H R W Symbol TKBPACTL1p TKBPAFXS1p3 TKBPAFXS1p2 TKBPAFXS1p1 TKBPAFXS1p0 ee TKBPAFCM1p ee TKBPAHZS1p1 TKBPAHZS1p0 TKBPAHCM1p1 TKBPAHCM1p0 TKBPAMD1p1 TKBPAMD1p0 TKBPAFXS1p3 External interruption trigger selection for forced output stop function 2 0 INTP20 can not be used as a trigger TKBPAFXS1p2 Comparator trigger selection for forced output stop function 2 o Comparator 3 can not be used as a trigger P comarstorscanneusedasatigges TKBPAFXS1p1 Comparator trigger selection for forced output stop function 2 mE Comparator 2 can not be used as a trigger 1 Comparator 2 can be used as atrigger OO TKBPAFXS1p0 Comparator trigger selection for forced output stop function 2 e Comparator 0 can not be used as a trigger TKBPAFCM1p Operation mode selection for forced output stop function 2 R Page 10 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Figure 7 74 Format of Forced Output Stop Function Control Register 1p TKBPACTL1p 2 2 TKBPAHZS1p2 Comparator trigger selection for forced output stop function 1 Comparator 3 can not be used as a trigger Comparator 3 can be used as a trig
41. p function 1 is cleared at the next counter period after Hi Z stop trigger IKBPAHTTO 1 is written regardless of the trigger signal level 1 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing Hi Z stop trigger TKBPAHTTO 1 is invalid Forced output stop function 1 is cleared at the next counter period after Hi Z stop trigger TKBPAHTTO 1 is written when the trigger signal is in its inactive period TKBPAMDOp1 TKBPAMDOpO Output status selection when executing forced output stop function bind o o Hzoupt yOuputfxedatiowievel er iou Owmehensnone f o owputtnedatiowever Output tnedatow evel Cautions 1 During timer operation setting the other bits of the TKBPACTLOp register is prohibited However the TKBPACTLOp register can be refreshed the same value is written 2 Be sure to clear bits 11 to 9 and 7 to 0 Remark n 0to2 p 0 1 R Page 7 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Correct Figure 7 73 Format of Forced Output Stop Function Control Register Op TKBPACTLOp 1 2 Address F0630H TKBPACTLOO F0632H TKBPACTLO1 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 TKBPACTLOp TKBPAFXS0p3 TKBPAFXSOp2 TKBPAFXS0p1 TKBPAFXSOpO oo o o TKBPAFCMOp 7 6 5 4 3 2 1 0 o TKBPAHZSOp2 TKBPAHZS0p1 TKBPAHZSOpO TKBPAHCMOp1 TKBPAHCMOp0 TKBPAMDOp
42. rrupt INTCMPO switching dandi E Signal via digital edge detect circuit is selected STOP mode release is disabled Forced output stop request signal is selected STOP mode release is enabled but only when not using noise filter Can be set when operating in low power RTC mode RTCLPC 1 in the OSMC register PNFEN Use Do not use external interrupt INTP20 noise filter o Use noise filter Do not use noise filter TMRSTEN1 External interrupt INTP21 function switching Motos External interrupt function is selected STOP mode release is enabled but cannot be used for timer restart function 1 Timer restart function is selected STOP mode release is disabled but can be used for timer restart function TMRSTENO External interrupt INTP20 function switching Notes External interrupt function is selected STOP mode release is enabled but cannot be used for timer restart function 1 Timer restart function forced output stop function 2 is selected STOP mode release is disabled but can be used for timer restart function When the interrupt for CMPO and CMP2 is used adopt a function used with the interrupt input signal When the CMPO and CMP2 are used as a trigger of the timer KB forced output stop function set CMPnSTEN i When the CMP2 is used as a trigger of the timer restart function for timer KB set CMP2STEN 0 For details see 14 5 Caution for Using Timer KB Simultaneous Operation Function When INTP20 and INTP21 are u
43. rrupts are revised and Notes are added Incorrect Figure 14 12 Format of Peripheral Function Switch Register 0 PFSELO Address FO5C6H After reset 00H R W Symbol 7 lt 6 gt lt 5 gt lt 4 gt 3 2 lt 1 gt lt 0 gt PFSELO CMP2STEN CMPOSTEN PNFEN ADTRG11 ADTRG10 TMRSTEN1 TMRSTENO CMP2STEN ion interr INTCMP2 switchin PNFEN Use Do not use external interrupt INTP20 noise filter o Use noise filter Do not use noise filter External interr function can b ner xternal interr but cannot be used for timer restart function LE tart function nn xternal interr standby mode li r j n i but cannot be used for timer restart function imer restart functio annot be generated external interrupt and cannot release Caution Comparator detection interrupt other than CMPO and CMP2 cannot be used to clear the STOP mode Re Page 20 of 45 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Correct Figure 14 12 Format of Peripheral Function Switch Register 0 PFSELO Address FO5C6H After reset 00H Symbol CMP2STEN Comparator 2 detection interrupt INTCMP2 switching hoes p Signal via digital edge detect circuit is selected STOP mode release is disabled Forced output stop request signal is selected STOP mode release is enabled but only when not using noise filter Can be set when operating in low power RTC mode RTCLPC 1 in the OSMC register CMPOSTEN Comparator 0 detection inte
44. sed as a trigger of the timer KB forced output stop function 2 or timer restart function see 14 5 Caution for Using Timer KB Simultaneous Operation Function Caution Comparator detection interrupt other than CMPO and CMP2 cannot be used to clear the STOP mode Remark n 0 2 RE Page 21 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 7 14 5 Caution for Using Timer KB Simultaneous Operation Function As respects of INTP2m and comparator Caution for Using Timer KB Simultaneous Operation Function is added Incorrect No applicable item Correct 14 5 Caution for Using Timer KB Simultaneous Operation Function In addition to their use as an external interrupt input the INTP2m pin output and the comparator output signal can be used as a trigger for functions that operate simultaneously with timer KB such as the forced output stop function and timer restart function The settings in peripheral function switch register 0 PFSELO and the edge selection registers must be specified according to the function used The width of the active signal required until each function starts operating differs When using INTP2m or the comparator output signal refer to Tables 14 4 to 14 6 to specify the necessary register settings and configure external circuits so that the required active signal width is assured Table 14 4 Relationship of INTP2m function register settings and active signal width Peripheral enable Edge se
45. stop function 2 e Comparator 0 can not be used as a trigger TKBPAFCMOp Operation mode selection for forced output stop function 2 R Page 6 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Figure 7 73 Format of Forced Output Stop Function Control Register Op TKBPACTLOp 2 2 TKBPAHZS0p2 Comparator trigger selection for forced output stop function 1 oo Comparator 2 can not be used as a trigger mpar n ri r 1 Comparator 2 can be used as a trigger TKBPAHZS0p1 Comparator trigger selection for forced output stop function 1 Comparator 1 can not be used as a trigger r 1 ri TKBPAHZSOpO Comparator trigger selection for forced output stop function 1 Comparator 0 can not be used as a trigger Comparator 0 can be used as a trigger TKBPAHCMOp1 TKBPAHCMOpO Clear condition selection for forced output stop function 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared when Hi Z stop trigger TKBPAHTTO 1 is written regardless of the trigger signal level 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing Hi Z stop trigger TKBPAHTTO 1 is invalid Forced output stop function 1 is cleared when Hi Z stop trigger TKBPAHTTO 1 is written while the trigger signal is in its inactive period 1 Forced output stop function 1 starts with trigger input and forced output sto
46. tput stop function 1 is cleared when Hi Z stop trigger TKBPAHTT2 1 is written regardless of the trigger signal level 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing Hi Z stop trigger TKBPAHTT2 1 is invalid Forced output stop function 1 is cleared when Hi Z stop trigger TKBPAHTT2 1 is written while the trigger signal is in its inactive period 1 Forced output stop function 1 starts with trigger input and forced output stop function 1 is cleared at the next counter period after Hi Z stop trigger TKBPAHTT2 1 is written regardless of the trigger signal level 1 1 Forced output stop function 1 starts with trigger input and when the trigger signal is in its active period writing Hi Z stop trigger TKBPAHTT2 1 is invalid Forced output stop function 1 is cleared at the next counter period after Hi Z stop trigger TKBPAHTT2 1 is written when the trigger signal is in its inactive period TKBPAMD2p1 TKBPAMD2p0 Output status selection when executing forced output stop function pos mme ommen 0 1 MzZotwu Output fixed athigh level a oe Cautions 1 During timer operation setting the other bits of the TKBPACTL2p register is prohibited However the TKBPACTL2p register can be refreshed the same value is written 2 Be sure to clear bits 11 to 9 and 7 to 0 Remark n 0to2 p 0 1 R Page 15 of 45 sKENESAS RENESAS TEC
47. ts inactive period TKBPAMD1p1 TKBPAMD1p0 Output status selection when executing forced output stop function pos wmm ommen 0 1 MzZotwu Output fixed athigh level ii neemen oee Cautions 1 During timer operation setting the other bits of the TKBPACTL1p register is prohibited However the TKBPACTL1p register can be refreshed the same value is written 2 Be sure to clear bits 11 to 9 and 7 to 0 Remark n 0to2 p 0 1 Re Page 11 of 45 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Correct Figure 7 74 Format of Forced Output Stop Function Control Register 1p TKBPACTL1p 1 2 Address F0670H TKBPACTL10 F0672H TKBPACTL11 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 TKBPACTL1p TKBPAFXS1p3 TKBPAFXS1p2 TKBPAFXS1p1 TKBPAFXS1p0 oo o o TKBPAFCM1p 7 6 5 4 3 2 1 0 o eeAHzstpe TKBPAHZS1p1 TKBPAHZS1p0 TKBPAHCM1p1 TKBPAHCM1p0 TKBPAMD1p1 TKBPAMD1p0 TKBPAFXS1p3 External interruption trigger selection for forced output stop function 2 INTP20 can not be used as a trigger ote 1 INTP20 can be used as a trigger N TKBPAFXS1p2 Comparator trigger selection for forced output stop function 2 Comparator 3 can not be used as a trigger a 2 Comparator 3 can be used as a trigger iis TKBPAFXS1p1 Comparator trigger selection for forced output stop function 2 Comparator 2 can not be used as a trigger Comparator 2 can be used as a trigger Notes
48. tting Necessary active signal width to operate each function Function register setting registers Interrupt Forced output stop Timer restart External interrupt TMRSTENm 0 EGPn EGNn To 1 us STOP release is enabled CEGPp CEGNp 55 to 215 ns 55 to 215 ns Note 1 Note 2 2 to 3 clocks Note 4 Note 3 5 Timer restart TMRSTENm 1 CEGPp CEGNp 55 to 215 ns Note 34 55 to 215 ns N34 Figure 14 18 Generation Timing of Forced Output Stop Signal and Timer Restart Request Signal by INTP2m Forced output stop request signal Nete 1 Timer restart request signal Interrupt request signal Only INTP20 can be used as a trigger for forced output stop function 2 The active level of INTP20 used for forced output stop function 2 is high Edge selection is only applied to detection of an interrupt signal 5 to 15 ns when noise filtering on INTP20 is disabled PNFEN 1 For fcuk or fet when PLLON 1 An additional output delay time 10 to 40 ns is required from when forced output stop function 2 starts operating to when the level of the timer KB output changes zu Page 22 of 45 sENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Notes 6 Until the timer restart function starts operating an additional clock cycle is required after the timer restart request signal is received and an additional output delay time 10 to 40 ns is required until the level of the timer KB output changes Remark m 0 1 n 20 21 p 7 6
49. ut stop function 1 is cleared at the next counter period after forced output stop function release sem MRE RAMIMOR 1 is written when the trigger signal is in its inactive period TKBPAMD0p1 TKBPAMDOpO Output status selection when executing forced output stop function iini 0 0 Hzoupt Ouputtixedatiowievei o rz OMthedangnee o0 9 Output fixed at low level Output fixed at low level Output fixed at high level Output fixed at high level When INTP20 is used as the forced output stop function 2 see 14 5 Caution for Using Timer KB Simultaneous Operation Function When CMPO or CMP2 is used as the timer KB forced output stop function set CMPnSTEN 1 See 14 5 Caution for Using Timer KB Simultaneous Operation Function When CMP1 is used as the timer KB forced output stop function see 14 5 Caution for Using Timer KB Simultaneous Operation Function When timer KB is stopped TKBCEn 0 without waiting for the next counter period the forced output stop function is kept on until timer KB is restarted TKBCEn 1 Cautions 1 During timer operation setting the other bits of the TKBPACTLOp register is prohibited However the TKBPACTLOp register can be refreshed the same value is written 2 Be sure to clear bits 11 to 9 and 7 to 0 Remark n 0to2 p 0 1 R Page 9 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 3 Figure 7 74 Format of Forced Output Stop Function Contr
50. xternal interrupt INTP20 noise filter o Use noise filter Do not use noise filter ADTRG11 ADTRG10 Timer trigger selection for A D conversion oo o Timer KBO trigger source Foo oa Timer KB1 trigger source A Timer KB2 trigger source oo timer restart disabled Timer restart function external interr eneration di l tan rele isable TMRSTENO Function selection for external interrupt INTP20 timer restart disabled Remark See Figure 14 1 Block Diagram of Comparator RE Page 4 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 Correct Figure 7 19 Format of Peripheral Function Switch Register 0 PFSELO Address FO5C6H After reset 00H R W Symbol 7 lt 6 gt lt 5 gt lt 4 gt 3 2 lt 1 gt lt 0 gt PFSELO CMP2STEN CMPOSTEN PNFEN ADTRG11 ADTRG10 TMRSTEN1 TMRSTENO CMP2STEN CMPOSTEN Comparator interrupt selection See CHAPTER 14 COMPARATOR PNFEN Use Do not use external interrupt INTP20 noise filter o Use noise filter Do not use noise filter oe qeexewwemes TT E 3 Los rennes TMRSTEN1 Switch of external interrupt INTP21 N External interrupt function is selected stop mode release enabled timer restart disabled Timer restart function is selected stop mode release disabled timer restart enabled TMRSTENO Switch of external interrupt INTP20 Hole oo External interrupt function is selected stop mode release enabled
51. y and 40 indicates the lowest priority 2 Basic configuration types A to D correspond to A to D in Figure 20 1 3 INTCMP1 INTCMP3 INTCMP4 and INTCMP5 cannot be used to clear the STOP mode About interrupt generation timing see 14 5 Caution for Using Timer KB Simultaneous Operation Function RE Page 28 of 45 sKENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Date Apr 24 2015 10 Figure 20 1 Basic Configuration of Interrupt Function Incorrect the basic configuration of interrupt function is revised Incorrect B External maskable interrupt INTPn INTCMPm Internal bus External interrupt edge enable register EGP EGN INTPn INTCMPm pin input Standby release signal Interrupt request flag Interrupt enable flag In service priority flag 0 In service priority flag 1 Interrupt mask flag Priority specification flag 0 Priority specification flag 1 Remark 20 pin n 0 20 21 22 m 0to3 30 pin n 0 4 11 20 to 23 m 0to5 38 pin n 0 3 4 9to 11 20 to 23 m O0to5 Re Page 29 of 45 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A024C E Correct B External maskable interrupt INTPn INTCMPm Date Apr 24 2015 Internal bus External interrupt edge enable register EGP EGN Note INTPnNete INTCMPmNete pin input ISPO Vector table address generator Standby release signal According to setting for using of the timer KB simultaneous
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