FOSSY - Predictable SystemC(TM)/C++ Synthesis
Contents
1. 38 SC_CTHREAD myCthread clk pos 39 reset_signal_is reset true 40 SC_CTHREAD myCthread2 clk pos 41 reset_signal_is reset true 42 2There may be more than one possible first wait in the case of conditional wait s in the reset part 24 3 Synthesis as Listing 3 9 Reset part of an SC_CTHREAD 3 2 5 Datatypes The following basic data types can be used for writing synthesisable models e bool e char unsigned char signed char e short unsigned short e int unsigned int e long unsigned long e long long unsigned long long e sc_int lt N gt sc_uint lt N gt e sc_bigint lt N gt sc_biguint lt N gt e sc_bv lt N gt e sc_logic converted to sc_bv lt 1 gt e Enumeration types Currently not supported are e sc_bit e sc_lv lt N gt e sc_fixed lt WL IL Q 0 n gt sc_ufixed lt WL IL Q 0 n gt e sc_fixed_fast lt WL IL Q 0 n gt sc_ufixed_fast lt WL IL Q 0 n gt Complex types like arrays structures classes and unions are synthesisable as long as they are constructed from synthesisable basic types Classes however are regarded in greater detail in Section 3 2 7 All data types mentioned above can be used in the following places e Local variables in functions and processes e Member variables e Function parameters and member function parameters 3 2 Synthesis Subset 25 e Signals sc_signal lt T gt Note This requires T to define the operator and2. private process es af void processing JE sub module s and other members T y my_module process body SA void my_module processing reset block of wait while true main loop af wait y my_module processing sc_main x This is optional and only required if you have more than one x module in your design In that case you should your top level module here a int sc_main int char my_module top top return 0 instantiate Listing 1 1 Typographical conventions for listings Listing 1 1 shows the typographical conventions for terminal sessions The gt symbolises the user prompt Like is the source code listings the means that parts of the listing have been omitted 1 Introduction gt cd my_project_folder gt fossy my_top_level_design cc poe Listing 1 2 Typographical conventions for terminal sessions 2 Using Fossy 2 1 General Information For accessing and testing the synthesis tool OFFIS operates an online synthesis demo at http system synthesis org fossy home However the usage of this service is limited to input files of 8000 characters Moreover it is limited at the amount of provided synthesis features 2 2 Structure of Fossy Installation The installation of Fossy is separated into three distinct sub directories each containing either binary executables or header files
3. C SystemC feature Comment Translation units Only one translation unit allowed Modules Definition SC_MODULE sc_module in heritance Members signal sub module ctors HAS_PROCESS S Si S Ports Signals sc_signal sc_in sc_out sc_inout sc_in_clk Ports Signals sc_out_clk Not supported but deprecated any sc_inout_clk way Ports Signals _resolved _rv Not supported Ctor w and w o SC_CTOR macro Deriving Datatypes Integral types SS S Integral promotion arith conversion 14 3 Synthesis Operators V Compounds arrays enums y No pointers and no references sup class struct unions functions ported SysC sc_int sc_uint sc_bigint sc_biguint SysC fixed point types Not supported SysC sc_bv J SysC sc_logic y Converted to sc_bv lt 1 gt internally SysC sc_lv Not supported SysC arithmetic operators J SysC bitwise operators J SysC relational oparators J SysC shift operators J SysC assignment operators J No chained assignments LHS must be side effect free SysC bit select operators J SysC part select operators y Reverse ranges not supported SysC concatenation operators Assignment to concats not supported SysC conversion to C integral y to_int to_bool etc SysC additional methods iszero accepted
4. Frontend contains a full featured C front end including cc2cil to convert C files into a front end specific format and cil2rml to generate XML files for the backend transformation tool Fossy contains the main program fossy which performs all elaboration and synthesis related tasks Library contains the syntheis header files of SystemC Although each of the provided tools can be used on their own the only tool that has to be executed by the user is fossy which is located in installation_directory Fossy bin Depending on the type of the given input file C CIL or XML it automatically calls all other necessary tools The default behaviour of fossy is to take a given SystemC file execute the front end call the CIL to XML conversion load the result and run the synthesis pipeline As a result a VHDL file is generated containing the SystemC design as a synthesisable RT level design 2 3 Running Fossy Before executing fossy the user has to set the environment variable FOSSY_HOME to the top level directory of the Fossy installation e g for a bash environment gt export FOSSY_HOME opt sw Fossy The synopsis of fossy is gt fossy OPTION lt file gt 10 2 Using Fossy Available options are h V vV t STRING T STRING D STRING I STRING m a STRING help version verbose topModule STRING topInst STRING define STRING include STRING systemc noVari
5. OFFIS INSTITUTE FOR INFORMATION TECHNOLOGY R amp D Division Transportation Hardware Software Design Methodology Group Jossy Predictable SystemC C Synthesis The Fossy Manual Oldenburg 2009 Last compiled July 7 2009 Contents A o a na a a a a an na aaa na ern 5 TI OVERVIEW a RA Se Ke A ck Be We Aa beiskt 5 12 Typographical conventions ara ea era 5 2 Using FON aa a dd do Are daa 9 21 General Information 24 2 0002 AA 9 2 2 Structure of Fossy Installation s s ca aoma cca s o 002008 9 E IE 9 24 ESOS 2 ee eA AAA AA A a oS 10 BUN ee ee ee E E E EE E 13 oe IM is e er E E A A ee E 13 Oe SOLES SUBS o ae soea ne KOE a ea een 13 3 2 1 Compatibility to the SystemC Synthesisable Subset 13 322 Godin Guidelines s sse a a ae 15 2 Dein NENE 16 DA eo oa mo mee koe ok da popa bis aomi hoe poit 19 Go Data pS A e EO ER Ee Me ee a a ee e S 24 3 2 6 Statements and Expressions 2 2 a 0204s 25 3 2 7 Classes and Inheritance so soc psy roi p ee d p e E eee 26 32 TEIDE cds iras ara 27 32 9 Namespat s daa nee eh need 27 3 2 10 Pobmesrphie Obrette 2 ccosa e aoiu e eee edu ea cad 27 BE IE e io ac ee ee ac ach 27 3 2 12 Non Synthesisable oe ec 2 ee au Ok we eR we 27 4 Summary and Support nn 29 AE A sess ee san ee AR RE NN ARE 29 A ATAN 29 References and Further Reading oo ooococcocccnnnrnn ann een en nennen nun 29 1 Introduction The following document serves as a quic
6. myPort myPort eee One RISE constructor body ona oo 0 A OU NY Hr End of myModulel cc o Listing 3 5 Synthesisable module constructors source file Limitation Module constructors must have exactly one parameter the module name which must be of type sc_module_name Limitation Module constructors must not contain complex control structures if then else etc Simple unrollable for loops are allowed Note The name which is supplied as constructor argument to named objects like modules ports signals is ignored by Fossy The resulting name will always be the attribute name Ports The following ports are allowed e sc_in lt T gt 18 3 Synthesis e sc_out lt T gt e sc_inout lt T gt e osss_port_to_shared lt IF gt Ports may be used directly or by pointer If the pointer variant is used the port may be initialised in the intialiser list or in the constructor body as shown in Listing 3 6 1 include lt systemc h gt 2 3 SC MODULE Sub el 5 sc_in lt bool gt portl used directly 6 port2 by pointer 7 xport3 by pointer 8 9 SC_CTOR Sub 10 portl portl1 11 port2 new sc_in lt bool gt port2 initialised in the 12 initialiser list 13 14 port3 new sc_in lt bool gt port3 assigned in the body 15 16 Listing 3 6 Synthesisable ports The type T may be any valid data type see Section 3 2 5 The type I
7. but not fully implemented sign bit reverse etc Declarations typedef J enums J aggregates Not supported Reduced support for ROM initialization available arrays J references Copy in copy out support for func tions methods pointers Pointers allowed for sub module in stantiation Expressions y new delete pointers not supported no chained assignments new allowed for sub module instantiation Functions Statements Processes No SC_THREAD supported Sub module instantiation No support for positional port bind ing Namespaces Classes Member functions Member vars Inheritance SU 5 PE eI 3 2 Synthesis Subset 15 Abstract classes Constructors No default arguments allowed Overloading Templates Pre processing directives A Table 3 1 Fossy SystemC Synthesisable Subset support 3 2 2 Coding Guidelines An OSSS design should be divided into several header h and source files cc Usually each header source file pair should contain one module declaration definition An exception to this rule are templates Templates should be completely described in the header file A corresponding source file is not necessary more precisely not possible in this case Limitation Currently Fossy can only process a single translation unit i e a single cc file As a workaround you can write a special main file e
8. tialiser lists are currently ignored This limitation also applies to all inherited constructors 3 2 12 Non Synthesisable The following C SystemC OSSS constructs are not synthesisable e OSSS architecture layer models e Pointers Exception instantiation of modules port and signals e Pointer arithmetics e Member pointers e Dynamic memory allocation with new and delete e Placement new e Exceptions throw specifications e Runtime typeid 28 3 Synthesis Reference types Exception function parameters dynamic_cast Destructors except for empty destructors Static data members mutable volatile auto register asm inline has no effect does not harm Standard C C libraries with string handling file I O Floating point arithmetic Bit fields not needed use SystemC data types instead friend partially implemented sc_time partially implemented 4 Summary and Support 4 1 Support To provide support for the users of the OSSS library OFFIS maintains several mailing lists The subscription to public mailing lists can be initiated by sending a mail contain ing subscribe lt list name gt in the body to mdom offis2 offis uni oldenburg de The lt listname gt is the local part of the mailing list s address below e osss devel offis de is a closed mailing list which can be used to contact the developers of the OSSS library Subscription requires approval of the list maintainers mails to this list
9. an operator lt lt for stream insertion and a sc_trace function e Signal ports sc_in lt T gt sc_out lt T gt sc_inout lt T gt e typedef Limitation The resolved signal sc_signal_rv lt N gt and the corresponding ports sc_in_rv lt N gt sc_out_rv lt N gt and sc_inout_rv lt N gt are currently not allowed for synthe sisable models 3 2 6 Statements and Expressions The basic statements of C C such as variable declaration and definition assignments control structures like if else switch for and while loops are synthesisable It is allowed to have switch statements with fall through cases i e cases without a break statement Functions and function calls are synthesisable as long as they operate on synthesisable data types and consist of synthesisable constructs Parameters may be passed by value or by reference and may be const or non const Forbidden Functions and operators must not return references Limitation Chaining multiple operator in assignments such as a b c d 0 is not supported yet Limitation A case part of a switch statement which solely contains a break is not supported Workaround insert an empty expression statement right after the case label switch i case 1 break Limitation A variable declaration in a switch block before the first case label is not supported Limitation Non toplevel case labels are not supported Limitation Variable declarations in swit
10. can be sent from any e mail address e osss user offis de is a public mailing list for discussions on the usage of the above mentioned libraries Sending mails to the list requires prior subscription An nouncements of major changes and other important news are sent to this list as well 4 2 Conclusion More advanced features and details concerning synthesis can be found in GBG 08 References and Further Reading cpp98 ISO IEC 14882 C Standard first edition September 1998 13 GBG 08 Kim Griittner Claus Brunzema Cornelia Grabbe Philipp A Hartmann An dreas Herrholz Henning Kleen Frank Oppenheimer Andreas Schallenberg and Schubert Thorsten OSSS A Library for Synthesisable System Level Models in SystemC The OSSS 2 2 0 Manual 2008 29
11. g fossy_main cc which includes all necessary cc files You should not include any cc files in header files An example of such a structure is shown in Listing 3 1 and Listing 3 2 The synthesis always needs a top level module to start from i e in order to do something useful with the synthesiser the design must contain at least one module oo Naa A OU N PR SD u A O NB include lt systemc h gt include lt osss h gt SC_MODULE SomeModule sc_in lt bool gt somePort void someProcess SC_CTOR SomeModule SCMETHOD someProcess sensitive lt lt somePort y Listing 3 1 General structure of the Fossy input SomeModule h include SomeModule h void SomeModule someProcess do something useful here x Listing 3 2 Source file SomeModule cc corresponding to Listing 3 1 16 3 Synthesis 3 2 3 Design Hierarchy Modules SC_MODULE is supported An SC_MODULE can be defined via the macro SC_MODULE or by manually deriving from sc_module If the latter form is used the macro SC_HAS_PROCESS lt ModuleName gt has to inserted An example is shown in Listing 3 3 1 include lt systemc h gt 2 3 SCMODULE myModulel A 5 zz e 7 s struct myModule2 public sc_module o 10 VE 11 12 Required if this module contains processes 13 SC_HAS PROCESS myModule2 u i Listing 3 3 A synthesisable module definition Limitation Inheri
12. to OSSS but due to the following synthesis tool Limitation Fossy can only determine the number of iterations of for loops Examples are shown in Listing 3 8 Forbidden sensitive_pos and sensitive_neg are not allowed Use the corresponding pos and neg methods of the port Forbidden The deprecated watching is not allowed Use reset_signal_is instead 1 include lt systemc h gt SC LMODULE Top sc_in lt bool gt clk reset sc_in lt int gt px o won oo vv 2 OON 10 void myMethod 12 This CTHREAD is intended to show valid and invalid loop 13 constructs don t mind that the loops are actually unreachable 14 void myCthread 16 int x 4 17 wait 3 2 Synthesis Subset 21 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 vi 72 73 Valid loop always runs into a wait each iteration while true if x wait 1 else wait 2 ii Invalid loop may do iterations without running into the wait while true if x wait Valid loop always runs into a wait each iteration Note that the wait be skipped entirely if the condition is false before starting the loop while x wait Valid loop always runs into a wait each iteration while true if x wai
13. F may be any valid user defined interface class Limitation Arrays of ports are not supported Structs containing ports are not supported Signals and Channels The only synthesisable channel is sc_signal lt T gt where the type T may be any valid data type see Section 3 2 5 The instantiation and naming requirements are exactly the same as in the case of ports Section 3 2 3 Limitation Structs containing signals are not supported Bindings Every port of an instantiated module must be bound within the instantiating parent module Port bindings must be done via the operator as shown in the Listing 3 7 3 2 Synthesis Subset 19 1 include lt systemc h gt 2 3 SCMODULE Bottom al 5 sc_in lt bool gt pl 6 sc_out lt int gt p2 7 Sean SES gt p3 s 9 10 SCLMODULE Middle u 12 sc in lt bool gt ql 13 Bottom b 15 sc_signal lt int gt s r SC_CTOR Middle 18 bab 19 20 b pl ql OK port to port binding 21 b p2 s OK port to signal binding 22 NOT OK unbound b p3 23 24 25 26 SC MODULE Top 27 28 Serin lt sce Unt lt S 5 RS 30 Middle m 32 SC_CTOR Top 33 gt m m 34 35 m b p3 r3 NOT OK bypasses the module hierarchy 36 37 DE Listing 3 7 Synthesisable bindings Forbidden Bindings must not bypass modules within the hierarchy Limitation Positional binding is not supported 3 2 4 Processes The followin
14. a copy constructor must be defined Limitation Pointers to unused classes or template instances are not allowed Note This includes types like sc_signal lt gt which are actually templates Each data member must be of a synthesisable type see Section 3 2 5 and member functions must follow the same restrictions as functions do see Section 3 2 6 Forbidden Classes must not have an own thread of control i e any SC_METHODs SC_THREADs or SC_CTHREADs These are only allowed in modules 3 2 Synthesis Subset De 3 2 8 Templates Templates can be used to parameterise functions classes structs and member functions Note that template classes may have template methods Template specialisation and partial template specialisation are supported 3 2 9 Namespaces Namespaces are supported The namespaces osss osss synthesisable sc_dt sc_core and std are reserved and must not be extended by the user 3 2 10 Polymorphic Objects Limitation Polymorphic objects are not yet supported 3 2 11 Shared Objects Each guarded method must overwrite a virtual method from its interface class Parameters of guarded methods must be passed by value or const reference A guarded method which does not write any attribute must have a wait in its body Limitation The schedule method of a scheduler must have a single return at the end of its body Limitation Initialisation of schedulers must be performed in the constructor body i e ini
15. a path through its body without encountering a wait 3 2 Synthesis Subset 23 without reset which is generally not the case in real hardware However after a reset the state machines before and after synthesis show exactly the same behaviour Since an SC_CTHREAD begins its execution from the beginning of the method body when the reset signal becomes activated the reset state is determined by path s from the beginning of the method body to all potential first wait Os Note that it is not necessary to test the reset signal in the body of the process A typical structure is shown in Listing 3 9 Note that it is also valid to move the first wait into the while true loop because Fossy will detect that the loop will always be entered Consequently it is possible to save one wait and hence one state as shown in myCthread2 The first variant i e myCthread will result in two equivalent states both performing x px include lt systemc h gt SC MODULE Top sc_in lt bool gt clk reset sc_in lt int gt px 0 o nN Dat Bah OO N Hr 10 void myMethod 12 void myCthread x E 14 int x 4 Reset Part 15 wait Lhe 16 Statel 17 while true o M 19 x px V V State2 20 wait 21 22 23 24 25 void myCthread2 26 27 int x 4 Reset Part 5 29 while true 30 H Y 31 wait WE Statel 32 x px I 33 34 36 SC_CTOR Top
16. ableSizeCheck noMemStatistics multipleOutputFiles aciFile STRING odir STRING prefix STRING keepImplicitFsm simModel enumElimination procedurelnlining 2 4 Example Show this help Show version number and exit Be verbose Top level module if not given the elaborator will search for a suitable one Top level instance name if not given the elaborator generates one not used to search Additional define symbols for frontend Additional include paths for frontend Generate SystemC Code Disable variable size check Disable intermediate memory statistics Write results to multiple output files 1 file per module ACI file Set output directory Set name prefix for generated files Do not transform implicit to explicit FSM Finite State Machine Generate a pure simulation model not for synthesis Eliminate enum types used in top level ports or signals Inline procedures containing waits into processes Listing 2 1 shows a very simple register collection in SystemC It s a fully parallel register of a parametrised size and datatype with one hot encoded write enable signals and a synchronous reset It is implemented with an SC_METHOD process for best simulation per formance This is the simplest implementation since no internal FSM is required Note that the example uses the SC_SYNTHESIS macro to exclude simulation related code from being processed by Fossy If this code has been saved to a file ca
17. ch clauses without a surrounding block are not supported Limitation A non void routine must not contain a return statement without an expression Limitation Recursion is not supported Limitation sizeof is not supported Limitation Only SystemC bitvector literals with prefix ObO are supported e g sc_int lt 3 gt x x 0b0111 x 0b0 111 26 3 Synthesis 3 2 7 Classes and Inheritance The following features of classes are allowed for synthesis e Non const non static data members e const non static data members e const static data members e Non static member functions e static member functions e Virtual member functions in conjunction with polymorphic objects e Pure virtual member functions in conjunction with polymorphic objects e Base class es Limitation no non virtual multiple inheritance from one base e Virtual base class es Limitation the virtual bases must not have any data members e Constructors Limitation copy constructor must have exactly one const amp argument default constructor must not have defaulted arguments e Member initialiser lists e Overloaded operators e User defined implicit casts Limitation May collide with Fossy s SystemC header files especially the integer types e explicit constructors Limitation Copy assignment operators operator must have the return type void and exactly one const amp argument Limitation If a user class contains an array member attribute
18. cit main since we have to x instantiate our templated module here int sc main int charx sync_register lt sc_uint lt 32 gt 4 gt top top ifndef SC_SYNTHESIS sc_clock clock clock sc_time 10 SC_NS sc_signal lt bool gt reset sc_main my_testbench lt sc_uint lt 32 gt 4 gt tb tb tb clk clock tb reset rest top clock clock top reset reset 12 2 Using Fossy 61 62 63 64 65 66 67 68 69 Listing 2 1 Synchronous Parallel Register Design Example in SystemC 3 Synthesis 3 1 Introduction Both the internal Fossy data structure and the intermediate format of the front end are based on the ISO IEC C standard cpp98 All Fossy internal code transformations are performed on a C standard compliant AST Abstract Syntax Tree This approach allows writing out meaningful code after each transformation step enabling traceability and easy debugging 3 2 Synthesis Subset This section gives a short overview of the synthesisable SystemC language constructs ac cepted by the current implementation of the Fossy synthesis tool simply referred to as the synthesiser 3 2 1 Compatibility to the SystemC Synthesisable Subset Fossy is quite compatible to the SystemC Synthesisable Subset Table 3 1 lists all important features of the synthesis subset Unsupported features or features with restricted synthesis semantics are commented
19. e conventions shown in Table 1 1 are used An example of a source code listing is shown in Listing 1 1 Comments are printed in italics while C keywords are printed in bold font Special SystemC language elements are printed in blue color To better emphasise certain parts of the source code printed in red color 1 Introduction Convention Item Example Times New Roman Normal Text This is an example sentence Times New Roman Emphasised Text This word is emphasised Monospace font Class function method or macro names execute_operation Monospace italics Variables meant to be re placed when the language construct is used Sometimes variables or pa rameters are omitted my_class lt parameter gt my_class lt gt do_something Monospace font Shell commands make Table 1 1 Typographical conventions for continuous text 1 2 Typographical conventions include lt systemc h gt SCMODULE my_module input ports sc_in lt bool gt clock sc_in lt bool gt reset add your input ports here se in lt sc_uint lt 32 gt gt in_data Ve output ports af add your output ports here se out lt sc_uint lt 32 gt gt out_data 7 fe constructor SC_CTOR my_module process definitions af SCCTHREAD processing clock pos reset_signal_is reset true
20. g process types are supported e SC_METHOD e SC_CTHREAD Constraints on SC_CTHREADs 20 3 Synthesis e SC_CTHREADs must not share member variables of a module If two processes must exchange data either use a signal or a Shared Object If a data member is exclusively used by a single process better make it a local variable of the process body e SC_CTHREADs must not terminate i e an infinite loop is required in the process body If you somehow need a terminating SC_CTHREAD place a while true wait at the end of the process body Constraints on wait usage in SC_CTHREADs e Arbitrary wait n is allowed i e n can be any integer expression More specifically it is not required that n can be determined at compile time WARNING If n cannot be determined at compile time it is the user s responsibility to ensure that n never becomes zero If this happens during normal SystemC simulation the SystemC kernel will raise an error Fossy won t can t check this and consequently won t raise an error As a workaround you could write if n wait n In this case however you have to take special care for the following rules because the wait O is conditional in this case The constraints on conditional wait s however are checked by Fossy e Loops must either 1 always run into a wait in each iteration 2 or have a fixed number of iterations which can be determined at compile time This restriction is not due
21. k introduction to the usage of Fossy To under stand this manual you should already be familiar with basic concepts of hardware design Moreover basic knowledge of SystemC is required since Fossy is a compiler that transforms SystemC code into synthesisable VHDL 1 1 Overview e Fossy stands for Functional Oldenburg System SYnthesiser e Fossy is a tool for transforming system level SystemC models to synthesisable VHDL e Fossy enables a seamless design flow for embedded HW SW systems Fossy has been developed at the OFFIS Institute for Information Technology an application oriented research and development institute working on system level design methodologies for more than ten years Two consecutive research projects funded by the European Union in cooperation with leading industrial partners resulted in robust tools with a focus on practical applicability This manual is structured as follows e The follwing part of Chapter 1 presents the typographical conventions used throughout this manual e Chapter 2 gives an overview of the Fossy command line tool e Chapter 3 presents the SystemC synthesis capabilities of Fossy It start with an general introduction followed by the definition of the supported synthesis subset e Chapter 4 provides contact information in case of technical questions and recommands further readings 1 2 Typographical conventions This manual uses the following typographical conventions For continuous text th
22. lled example cpp it can be processed by the Fossy by entering gt fossy example cpp After Fossy has finished the working directory will contain a file called synthe sised_example vhdl including the RT level design I 2 3 4 include lt systemc h gt template lt typename DataType unsigned Size 8 gt SCMODULE sync_register 2 4 Example 11 o won na 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 typedef DataType value_type sc_in lt bool gt clock sc_in lt bool gt reset input ports of sc_in lt sc_uint lt Size gt gt in_wen sc_in lt value_type gt in_data fe output ports aff sc_out lt value_type gt data Size constructor Bf SC_CTOR sync_register process definitions SCMETHOD processing sensitive lt lt elock pos private process es void processing 7 y sync_register Ves process body af template lt typename DataType unsigned Size gt void sync_register lt DataType Size gt processing sc_uint lt 10 gt wen in_wen read for unsigned i 0 i lt Size Hi if reset read data i write 0 else if wen i to_bool datali write in_data y sync_register processing x We need an expli
23. t Some code wait More code el EE OK some x which is not zero wait x Valid loop always runs into a wait each iteration while true if x wait since this loop always causes a wait for int i 0 i lt 3 i if i x 1 wait else wait Valid loop always runs into a wait each iteration do wait while x 22 3 Synthesis 74 75 SC_CTOR Top 76 77 SC _METHOD myMethod 78 sensitive lt lt clk pos Note pos neg only works 79 lt PONELE IN for Boolean ports 80 81 sensitive lt lt px OK there may be multiple 82 bf sensitives 83 84 SC_CTHREAD myCthread clk pos 85 reset_signal_is reset true 86 s7 E Listing 3 8 Synthesisable processes Effect of wait usage on the number of states In general the number of states of the resulting state machine equals the number of wait Os in the process body A special case are loops if there is a path through the loop body which does not contain any wait s Fossy tries to unroll that loop Consequently the number of resulting states is the number of wait O statements times the number of iterations Please keep in mind that loops with many iterations which have to be unrolled due to non optimal wait usage cause long synthesis runtimes high memory consumption and finally a huge but fast circuit Another special case regarding the n
24. tance is not supported for user modules Note Each module must have exactly one constructor Constructors A module constructor can be defined via the macro SC_CTOR or it can be defined manually An example is given in Listing 3 4 and Listing 3 5 Begin of myModule1l h include lt systemc h gt 1 2 3 4 SCMODULE myModulel 5 6 sc_in lt bool gt myPort 7 8 Alternative 1 9 Use SCCTOR and place the body in the 10 header file 11 SC_CTOR myModulel 12 myPort myPort 13 eae mone wnat valasie ms 14 15 constructor body 16 18 Alternative 2 19 Manually specify the constructor and 20 place the body in the header file 3 2 Synthesis Subset 17 21 myModule sc_module_name name 22 myPort myPort 23 more initialisers 24 25 constructor body 26 28 Alternative 3 29 Manually specify the constructor and 30 place the body in the source file 31 myModule sc_module_name 32 the body is located in the cc file 34 Alternative 4 35 Use SCLCTOR and place the body in the 36 source file 37 SC_CTOR myModule1 38 the body is located in the cc file 39 and looks exactly like the one for 40 Alternative 3 a2 8 as End of myModulel h Listing 3 4 Synthesisable module constructors header file Begin of myModulel cc include myModulel h myModulel myModulel sc_module_name
25. umber of resulting states are wait n s There are two different synthesis strategies The first one is to simply unroll the wait n by n wait 1 s which results in n states The second one is to replace the wait n by a loop with an unconditional wait 1 in the loop body The resulting state machine of the second approach adds only one state to the state machine and one additional counter The decision which of both approaches is chosen depends on whether n is a compile time known constant and also on its value Reset The reset signal of an SC_CTHREAD is determined by the correpsonding reset_signal_is statement in the constructor body Please note that the re set of an SC_CTHREAD is always synchronous to the SC_CTHREAD s clock Consequently Fossy always creates a state machine with a synchronous reset Note that the pre reset behaviour before and after synthesis may differ This is due to the fact the in the simulation an SC_CTHREAD always starts from the beginning of the method whereas after synthesis and in real hardware the register which encodes the current state will start with a random value until it is reset Starting with a random state in the context of an SC_CTHREAD would mean to start at some arbitrary wait In other words the SystemC simulation with SC_CTHREADs suggests that the state machine starts in its initial state even In this case the wait Qs will be conditional ones because otherwise the loop would not have
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