Home

BIOS User`s Manual

1. 2 CYPRESS M ii Wns BIOS User s Manual Version 1 1 Cypress Semiconductor 3901 North First Street San Jose CA 95134 Tel 800 858 1810 toll free in the U S 408 943 2600 www cypress com Q LC o NENNEN CYPRESS EE emt IA EE _ L Cm Y y A X u A Y Y SE oe Cypress Disclaimer Agreement The information in this document is subject to change without notice and should not be con strued as a commitment by Cypress Semicon ductor Corporation Incorporated While reasonable precautions have been taken Cypress Semiconductor Corporation assumes no responsibility for any errors that may appear in this document No part of this document may be copied or reproduced in any form or by any means with out the prior written consent of Cypress Semi conductor Corporation Cypress Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Cypress Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Cypress Semiconductor products for any such unin tended or unauthorized application Buyer shall indemnify and hold Cypress Semiconductor and its officers employees s
2. 1 7 10 2 Interrupt 65 2 wire Serial EEPROM from 4 KByte to 64 KByte This interrupt offers the same functionality as INT 64 but address bits are set to 14 and the SDA and SCL are swapped The swapping of the GPIO lines forces the board designer to wire the EEPROM reverse for the two size ranges allowing only two GPIO pins to still be used During boot up INT 64 and INT 65 are used by the SCAN INT 67 to test for each type of EEPROM 1 7 11 UART functions 1 7 11 1 Interrupt 66 UART INT Note THE UART IS RESERVED FOR DEBUGGING In the EZ Host device 100 pin package this port is connected to pin GPIO27 and GPIO28 In the EZ OTG part 48 pin package this port is connected to pin GPIO7 and GPIOG The UART interrupt provides read write access to the UART The BIOS uses this interrupt and INT 67 Scan for enhancements to provide external access to the chip Code and data can be down loaded via the UART and the debugger utilities use the UART port for low level access Page 1 68 BIOS User s Manual v1 1 In the EZ Host device the BIOS uses GPIO28 for data transmit TX and GPIO27 for data receive RX In the EZ OTG device the BIOS uses GPIO7 and GPIO6 for the UART but it will be disabled when the chip is in HPI mode In general the UART pins are shared with other functions i e GPIO mode When other functions are selected the UART will no longer function and this interrupt will not work However besides the UART ther
3. word r7 Uses Routine pointed by R7 to Read byte r0 r7 r0 8 upper byte ro r15 YO r0 or pop r0 1 7 3 OTG Interrupt Functions The following functions are dedicated for the OTG design and subsequently described e OTG STATE OTG STATE INT OTG Descriptor OTG SRP INT e REMOTE WAKEUP INT Na Note These functions are not implemented in the current release of the BIOS and these interrupts and variables are reserved for future BIOS Chapter 1 BIOS Interface Page 1 25 BIOS User s Manual 1 7 3 1 Interrupt 50 OTG_STATE The BIOS uses this location as the variable for the OTG state machine i e b_idle and a_idle state machines from the On The Go OTG supplement to the USB 2 0 Specification This variable will be updated when users call the OTG_STATE_INT The defined state will be shown as follows a_idle equ 0 a wait bcon equ 1 a host equ 2 a suspend equ 3 a peripheral equ 4 a wait vfall equ 5 b idle equ 6 b peripheral equ 7 b host equ 8 Note This variable is used by the BIOS Users should not write to this location 1 7 3 2 Interrupt 112 OTG STATE INT The BIOS supports both a idle and b idle state machines for USB portA only This interrupt pro vides support for Session Request Protocol SRP and Host Negotiation Protocol HNP The BIOS controls and monitors all the low level interface i e VBUS OTG ID D D pull up down VBUS pump charge VBUS pull up VBUS discharge and user
4. 1 7 4 1 2 Example Set SIE1 as Host and be ready to execute the TD list int HUSB_SIE1_INIT_INT Set SIEl as Host ret 1 7 4 2 Interrupt 116 HUSB_RESET_INT HUSB_RESET_INT has three functions USB Reset Before accessing a USB device the HUSB_RESET_INT generates a USB reset and sends it to USB bus This forces the peripheral device to its default address of zero The minimum time required to hold the USB bus in USB reset is gt 10milliseconds After detecting a USB reset every device responds to USB address zero After a USB reset configuration software can read every device s descriptor at the same default address one device at a time Speed Detect The HUSB_RESET_INT detects the full low speed of the attached device then returns the port status FULL SPEED LOW SPEED or NO DEVICE SOF EOP Generation Based on the device speed HUSB_RESET_INT generates an SOF for full speed and an EOP for low speed If no device is attached on this port there will be no SOF EOP Chapter 1 BIOS Interface Page 1 29 BIOS User s Manual 1 7 4 2 1 Software Interface Entry R1 RO Port number OZUSB PortO 1 USB Port1 2 USB Port2 3 USB Port3 Time interval for USB reset in milliseconds Registers Usage None Return This interrupt will return the speed on that port RO Dm 0 Full speed BitO 1 Slow speed Bit1 1 No device Bit1 0 Device is connected 1 7 4 2 2 Example Reset port A generate SOF
5. BIOS User s Manual 5 3 7 5 COMM_READ_CTRL_REG via HPI Set Control Reg Address Send CMD COMM_READ CTR REG Wait for Response L_REG comm_CTRL_ Get Control GET Reg Value Figure 5 6 COMM_READ_CTRL_REG via HPI VA Notes The COMM_CTRL_REG_ADDR is defined the same as the COMM_MEM_ADDR which is a pointer to the CY16 address to be read the COMM_CTRL_REG_DATA is defined as the COMM_MEM_LEN Users should supply the COMM_CTRL_REG_ADDR before writing the command COMM_READ_CTRL_REG in the HPI mailbox After receiving the ACK the COMM_CTRL_REG_DATA i e COMM_MEM_LEN should be read via the HPI Direct Memory Access Page 5 8 BIOS User s Manual v1 1 5 3 7 6 COMM_READ_XMEM via HPI pointers and length Set COMM MEM appr Set COMM Last pat Get Data Figure 5 7 COMM READ XMEM VA Notes Users should supply the COMM_MEM_ADDR COMM_MEM_LEN and COMM_LAST_DATA before writing the command COMM_READ_XMEM in the HPI mailbox After receiving ACK from the EZ Host EZ OTG device the data should be read from COMM_LAST_DATA The external microprocessor should maintain the memory usage of EZ Host EZ OTG internal memory space The COMM_LAST_DATA should be allocated inside the internal memory space Chapter 5 HPI Transport Module Page 5 9 BIOS User s Manual 5 3 7 7 COMM_WRITE_XMEM via HPI Set memory Set COMM MEM LEN and pointers se C OMM MEM Appg coum Last paa COMM
6. COMM JUMP2CODE Action Jump Code Data Used COMM MEM ADDR Must point to Valid Code Space Response COMM ACK Note An ACK will be sent after completing the execution of COMM JUMP2CODE for exam ple the HUSB RESET take 10miliseconds then the ACK will be sent after 10 milliseconds If this code never returns the external microprocessor should not expect the ACK Page 2 4 BIOS User s Manual v1 1 Note For HPI the COMM MEM ADDR must use direct hardware access to modify this loca tion For the HSS SPI this variable is part of the 4 word command structure This command is used to jump to the start of program memory after a program is loaded via HPI HSS SPI COMM_CALL_CODE Action Call Subroutine Data Used COMM_MEM_ADDR Must point to Valid Code Space Response COMM_ACK CA Note An ACK will be sent after completing the execution of COMM_JUMP2CODE If this code never returns the external microprocessor should not expect the ACK For HPI the COMM_MEM_ADDR must use direct hardware access to modify this location For the HSS SPI this variable is part of the 4 word command structure This command is used to call a subroutine after a program is loaded via HPI HSS SPI COMM EXEC INT Action Execute hardware software interrupt Data Used COMM INT NUM 0 127 and COMM R0 COMM R13 Response COMM ACK Note An ACK will be sent after completing the execution of the COMM EXEC INT If this code never returns the external micr
7. GPIO30 4 GND SDA 5 AT24LC16B SN Figure 1 3 2 wire Serial for up to 256 byte up to 2 KByte Connection ae GPIO30 4 GND SDA 5 GPIO31 IC2 AT24C512 Figure 1 4 2 wire Serial from 4K up to 64 KByte Connection Note The GPIO 31 30 shared with boot up configuration pin The 10K pull up is required on both pins 1 7 10 1 1 Software Interface Uses Ptr to Param Struct to read write control params The current BIOS configures interrupt 64 with the following Page 1 66 BIOS User s Manual v1 1 Entry RO 1 1 for writes O for reads 2 for set parameters 3 for get parameters R1 2 wire serial address to read or write or parameter address R2 Contains the byte to be written in write operations Registers Usage none Return RO On Read RO contains the byte read from a 2 wire serial On Write 0 for no error not O if error R1 Incremented by 1 Note The default BIOS uses GPIO31 and GPIO30 for all I2C programming If developers like to use other GPIO pins for the 12C programming then the RO 2 and RO 3 can be used for this pur pose Na Note The 2 wire serial BIOS default parameters are set in the following format dw GPIO HI ENB dw GPIO HI IO dw SDA dw SCL db 0xa0 db 11 IO Port Location GPIO HI ENB equ GPIO HI IO equ SDA equ SCL equ GPIO address used to enable output GPIO address used to set clear output bit mask used for bit mask used for Signature byte
8. Page 1 34 BIOS User s Manual v1 1 1 7 5 3 Interrupt 91 107 SUSB1_CONFIGURATION_DESCRIPTOR_VEC SUSB2_CONFIGURATION_DESCRIPTOR_VEC These interrupt locations contain the pointer to the default Cypress Configuration Descriptor refer to USB Specification version 2 0 for details A pointer to a different configuration descriptor may be written here if necessary Note In stand alone mode these descriptors can be changed either via the serial EEPROM or the external ROM Note In co processor mode these descriptors can be changed via the LCP command Note The BIOS only supports one interface so the number of interfaces should be set to 1 see example To support multiple interfaces the user might need to change the SUSBx_DELTA_CONFIG_INT and SUSBx_STANDARD_INT 1 7 5 3 1 Software Interface The default Cypress Configuration Descriptor is as follows conf desc db 9 len of config db 2 type of config dw end all conf desc Total configuration desc length db 1 one interface db 1 config 1 db 0 index of string describing config db 0x80 attributes bus powered db 50 100 mA interface desc db 9 db 4 db O base db 0 alt db 2 2 endpoints db 0 interface class vendor db O subclass db 0 interface proto vendor db 0 index of string describing interface endpoints descriptor epl db 7 len db 5 type endpoint db 0x1 type number Host use WriteFile db 2 Bulk dw 64 packet size
9. Please see Figure 3 5 for the definition of EOT EOT value is in full speed bit time and is stored in address HUSB pEOT Chapter 3 USB Host BIOS Specifications Page 3 7 BIOS User s Manual EOT value SOF ST er s EOF SOF EOT SOF Figure 3 5 End Of Transfer Point BIOS For every frame all data transaction must be completed before the EOT point HCD The EOT value should be set to guarantee that the TD_ Load will be finished before next SOF The TD_DataCopy could cross the SOF because of the ping pong buffers When the EZ Host EZ OTG part boots up the HUSB_pEOT is cleared to zero The EOT value is based on the external processor speed and HCD mechanism During initialization of the HCD the EOT value should be written into HUSB_pEOT It only needs to be set one time VA Note When the EOT value is not set properly the USB host BIOS still works fine In that case sometimes the TD_Load may not be finished before the next SOF and there will be no transaction in the next frame 1 ms So the worst case for not setting the EOT value prop erly is the loss of some bandwidth 3 4 1 3 HUSB_SIEx_pTDListDone_Sem This semaphore indicates that the TD list is done It is equivalent to HUSB_TDListDone SIE mail box message It is used in case there is no mailbox available BIOS After completion of TD list set HUSB_SIEx_pTDListDone_Sem 1 HCD The HCD checks HUSB SIEx pTDListDone Sem to see if the TD list has been fin i
10. number of bits for address 0xc028 0xc024 0x4000 0x8000 the data line the clock line General Purpose IO Control register high General Purpose IO Data register high bit 14 serial bit 15 serial of the GPIO HI IO for the two wire Data line of the GPIO HI IO for the two wire Control line The user can configure the serial EEPROM interface for different GPIO lines The example below shows how to modify the default parameters This example shows how to reuse the BIOS code to access an additional serial EEPROM connected to different GPIO lines Chapter 1 BIOS Interface Page 1 67 BIOS User s Manual Example 20 Setting new two wire serial 2 KByte parameters align 2 new param dw 0xc028 General Purpose IO Control register high dw 0xc024 General Purpose IO Data register high dw 0x0001 GPIO16 SDA dw 0x0002 GPIO17 SCL db 0xa0 Signature byte db 11 number of bits for address addressable up to 2KByte align 2 mov ED 2 2 set param mov r2 new param new parameter int 64 call BIOS interrupt mov r0 0 O read int 64 Call BIOS interrupt mov data rO r0 is the return data VA Note At power up the EZ Host EZ OTG device will restore the old configuration which means the users cannot boot from the serial EEPROM that connects to GPIO16 and GPIO17 To be able to boot from the serial EEPROM the serial EEPROM must be connected to GPIO31 and GPIOSO The data pull up resistor is required on GPIO16
11. theader header Chapter 1 BIOS Interface Page 1 53 BIOS User s Manual Page 1 54 devreq wValue bLoad devreq bRequest 0xff devreq wLength wLen buffer length switch bLoad case 7 devreq bmRequest 0xc0 dev to host vendor device devreq wIndex WORD pData devreq wLength RdLen buffer length devreq ioBuff PBYTE pRdData RetVal DeviceloControl hDev DWORD IOCTL VENDOR CONTROL PVOID amp devreq DWORD sizeof DevReq NULL DWORD devreq wLength amp cbRet NULL break default devreq bmRequest 0x40 host to dev vendor device header sig 0xc3b6 header len wPreLen wLen header ltype bLoad if wPreLen 0 devreq ioBuff PBYTE pData RetVal DeviceloControl hDev DWORD IOCTL VENDOR CONTROL PVOID amp devreq DWORD sizeof DevReq NULL DWORD devreq wLength amp cbRet NULL else devreq wLength 5 2 wPreLen buffer length pdev char calloc 5 wPreLen wLen 2 1 memcpy pdev header 5 memcpy pdev 5 pPre wPreLen memcpy pdev 5 wPreLen pData wien devreq ioBuff PBYTE pdev RetVal DeviceloControl hDev DWORD IOCTL VENDOR CONTROL PVOID amp devreq DWORD sizeof DevReq NULL DWORD devreq wLength amp cbRet NULL free pdev break return RetVal BIOS User s Manual v1 1 1 7 5 13 Interrupt 95 111 SUSB1_DELTA_CONFIG_INT SUSB2_DELTA_CONFIG_INT The standard USB handler calls these interru
12. 83 54 3 167 1 1667 8 Data bc Host Delay ns 112 5 9 36 Data bc Host Delay full speed bit times Isochronous Transfer No Handshake 7268 83 54 Floor 3 167 BitStuffTime Data bc Host Delay 90 5 9 36 Data bc Host Delay full speed bit times Full speed Output Non Isochronous Transfer Handshake Included 9107 83 54 Floor 3 167 BitStuffTime Data bc Host Delay 112 5 9 36 Data bc Host Delay full speed bit times Isochronous Transfer No Handshake 6265 83 54 Floor 3 167 BitStuffTime Data bc Host Delay 78 4 9 36 Data bc Host Delay full speed bit times Page 3 18 BIOS User s Manual v1 1 Low speed Input 64060 2 Hub LS Setup 676 67 Floor 3 167 BitStuffTime Data bc Host Delay 768 7 2 4 8 12 3 167 1 1667 8 Data_bc Host_Delay full speed bit times 802 4 75 78 Data_bc Host_Delay full speed bit times Low speed Output 64107 2 Hub LS Setup 667 0 Floor 3 167 BitStuffTime Data bc Host Delay 769 3 2 4 8 3 167 1 1667 8 Data_bc Host_Delay full speed bit times 802 6 74 67 Data_bc Host_Delay full speed bit times 3 8 Detail Design 3 8 1 HUSB SIEx INIT INT 3 8 1 1 Software Interface Refer to Section 3 4 Software Interface Between HCD and BIOS 3 8 1 2 Example Set SIE1 as Host and be ready to execute the TD list int HUSB SIE1 INIT INT Set SIEl as Host ret 3 8 2 HUSB RES
13. Structure COMM_WRITE_MEM of INT Data COMM EXEC INT 7 0 COMM ExEC Nr 15 8 L un EE Send 8 Byte SE CMD Packet XXh XXh Poll for non OxFF a Wait _OxEF Get 2 Bytes of Response 7 01 Response Followed by QResemeliS8L RO Return Value RO RO 15 8 Figure 6 10 COMM_EXEC_INT via SPI Chapter 6 SPI Transport Module Firmware BIOS User s Manual Page 6 14 BIOS User s Manual v1 1 7 CYPRESS j Chapter 7 HSS Transport Module 7 1 Introduction 7 1 1 Overview The High Speed Serial interface HSS of the CY16 processor provides a 9600 to 2M baud asyn chronous serial interface to EZ Host EZ OTG device The HSS Transport uses the HSS hardware to receive LCP commands and data and to transmit responses The serial connection is used in a half duplex manner with no hardware or software handshaking 7 1 2 Scope This document provides details on the HSS support software A basic understanding of the EZ Host EZ OTG hardware and software architecture is assumed 7 2 Functional Requirements The HSS transport exposes the Link Control Protocol via the HSS hardware interface The trans port must be capable of receiving LCP commands from an external CPU and sending back responses 7 3 Detailed Design Refer to Figure 2 1 Link Control Protocol for details The HSS transport is inherently different from the HPI transport This is
14. This interrupt routine calls INT 70 IDLE INT in a loop such that the IDLE processing chain is exe cuted endlessly as a background process The BIOS calls this interrupt after all boot up activities are finished This interrupt behaves like the main program loop for the BIOS If the user decides to replace this interrupt the execution of the int 70 must be maintained for the BIOS to be alive Chapter 1 BIOS Interface Page 1 61 BIOS User s Manual The listing of interrupt 71 Int 71 addi a e 2 adjust the stack pointer int 70 execute IDLE INT int 71 execute int 71 1 7 8 2 1 Example Example 18 Execute Interrupt 71 int 71 interface to c language using Timerl for BIOS idle task IDLER VEC equ IDLER INT 2 cstartup mov IDLER VEC new 71 Replace idler loop mov 2 Timerl use timer 1 for BIOS tasks idle loop or intenb 2 enable Timer 1 interrupt ret PRR RRR kk ke kc ec ke kc kc ke ke he ke kkk kkk kkk k kk New Idle loop pk kk ckcke ke sk cec ke ke cec he ke e ke ke e ke ke e ke ke ke ke e k k k new 71 addi r15 2 call main int 71 call main PRR RR KEKE k k k k k k k k k k k k k k k k k k k k e k ke alternative execute BIOS task RRR RRR RK RK kkk kk e ke ke kkk kkk kkk k kk Timerl push flags int PUSHALL INT push all RO R14 int 70 call BIOS tasks mov 0xc012 10000 call BIOS task for every 1 mili seconds int POPALL INT pop all RO R14 pop flags sti ret vo
15. but are accessible to the user This interrupt cannot be called in the interrupt context 1 7 11 1 2 Example See examples in the KBHIT section 1 7 11 2 Interrupt 123 KBHIT 1 7 11 2 1 Overview This interrupt is used for UART debugging purpose during development It configures baud rate and disables enables the BIOS UART The interrupt is designed for standard I O and used by printf 1 7 11 2 2 Software Interface Entry RO baud rate 1 7 11 2 3 Example _kbhit mov r0 9 Setup 19 2K int 117 execute interrupt ret Page 1 70 BIOS User s Manual v1 1 Example 21 Get a character from the UART A Note To use this subroutine users must disable the UART task that supports the debugger by call ing the KBHIT_INT When the KBHIT_INT is enabled the debugger will no longer work _getchar xor int ret r0 ro RO read data from the keyboard UART_INT Call UART INT return character in RO Example 22 Put a character to the UART _putchar push mov mov int pop ret r2 r2 r0 ro 1 write to the UART UART_INT call UART_INT r2 void puts char buf while buf 0 putchar buf void main void int c Call User HW SW initialization here kbhit while 1 Application here puts Hello world c getchar Chapter 1 BIOS Interface Page 1 71 BIOS User s Manual Page 1 72 BIOS User s Manual v1 1 Ch
16. 1 Software Interface etre 1 60 1 7 7 8 2 Example seier ee teen eegene 1 60 1 7 8 BIOS dle task functions 2 Ee abcde age ne beta Eed 1 60 1 7 84 Interr pt 70 IDEE INT coat cipe ea nea 1 60 1 7 8 1 1 Software Interface rte rettet rne 1 61 IAS pepieta taae iaai t ataata titia 1 61 1 7 8 2 Interrupt 7 1 IDEER INT coi reete i seinen een 1 61 ID cule 1 62 1 7 8 3 Interrupt 72 INSERT DLE INTE 1 63 1 7 8 3 1 Software E terere redes ce tede eene eead 1 64 1 7 8 3 2 Example EE 1 64 1 7 9 Debugging Support functions ooononnncccnnoncnnnnonanononncon arc nn nonn conan ene eene ens 1 65 1 7 9 1 Interrupt 126 127 Reserved for Debugger A 1 65 1 740 Serial EEPROM SUppoltt 1 1n iere egener ee es her iaa 1 65 1 7 10 1 Interrupt 64 2 wire Serial EEPROM from 256 byte to 2 KByte 1 65 1 7 10 4 1 Software EE 1 66 1 7 10 2 Interrupt 65 2 wire Serial EEPROM from 4 KByte to 64 KByte 1 68 TAS e PUNCHONS P J 1 68 Table of Contents iii A CYPRESS Table of Contents 1 7 11 1 Interrupt 66 UART INTE 1 68 Ben bn A Sofware Interface EE 1 69 LE AS AAA A A ex hoe ER eU ER enn UE 1 70 1 7 11 2 Interr pt 123 BELT peor sshong snot DEENEN 1 70 EN a A OVerVIQW A mic EE 1 70 1 7 11 2 2 Software Interface 1 70 A PEA A AE E T E A A T 1 70 Chapter 2 Link Control Protocol Fir
17. 8 7 COMM_READ_MEM via SPI COMM READ MEM 7 0 COMM READ MEm 15 8 COMM MEM Appg 7 0 Send 8 Byte COMM CMD Packet To MEM ADDR 15 8 MM MEM LEN 7 0 CO MM MEM LEN 15 8 XXh XXh Poll for non OxFF Wait OxFF Response 7 0 Get 2 Bytes of Response 15 8 Response Mem Value 1 7 0 followed by n words of Data Mem Value 1 15 8 Mem Value n 7 0 Mem Value n 15 8 Figure 6 7 COMM READ MEM via SPI Page 6 10 BIOS User s Manual v1 1 6 3 8 8 COMM_WRITE_XMEM via SPI COMM_WRITE_xMEm 7 0 COMM_WRITE_xMEm 15 8 COMM MEM LEN 7 0 Send 8 Byte COMM CMD Packet MEM LEN 15 8 COMM MEM Ap 7 0 COMM_MEM_ADDR 15 8 COMM_LAST DATA COMM_LAST pata Poll for non OxFF Wait OxFF Get Response 7 0 2 Bytes of Response 15 8 Response Mem Value 1 7 0 Mem Value 1 15 8 Send n Words of H Data Mem Value n 7 0 Mem Value n 15 8 Figure 6 8 COMM_WRITE_XMEM via SPI Chapter 6 SPI Transport Module Firmware Page 6 11 BIOS User s Manual 6 3 8 9 COMM READ XMEM via SPI COMM READ XMEM 7 0 COMM READ vu 15 9 Send 8 Byte CMD Packet SOMM_LAST_DATAf7 0 COMM LAST Gar an 5 8 Poll for non OxFF Get 2 Bytes of Response Mem Valu followed by n words of Data Mem Valu Mem Value n Figure 6 9 COMM READ XMEM via SPI Page 6 12 BIOS User s Manual v1 1 6 3 8 10 COMM_EXEC_INT via SPI Full COMM_WRITE_MEM to set Interrupt Data
18. BIOS User s Manual v1 1 2 2 2 Transport Requirements Each Transport HPI HSS SPI or other must meet the following requirements e Have an INIT function that Enables HPI HSS SPI mode Configures the port for Default Communication Parameters baud rate for example INT enables etc Have a Receive Command ISR which receives a Command or Command Packet 2 2 3 BIOS ROM Code LCP All of the port command processing is included in the BIOS ROM via the Icp_idle task 2 2 3 1 Data Structures and Variables for Port Command Processing Several data structures are stored in the BIOS reserved section of RAM from 0x019A 0x01A2 These are described in 1cp data inc and lcp cmd inc DATA UNION FOR SIMPLE PORT CMDS COMM PORT CMD equ OxOlba For PORT Command COMM MEM ADDR equ OxOlbc For COMM RD WR MEM COMM MEM LEN equ OxOlbe For COMM RD WR MEM COMM LAST DATA equ 0x01c0 memory pointer for mem COMM BAUD RATE equ Ox0lbc Use in the HSS COMM CONFIG COMM CTRL REG LOGIC equ 0x01c0 User to AND OR Reg REG WRITE FLG equ 0x0000 REG AND FLG equ 0x0001 REG OR FLG equ 0x0002 COMM INT NUM equ 0x01c2 Interrupt number COMM RO equ 0x01c4 CY16 RO register COMM R1 equ 0x01c6 CY16 R1 register COMM R2 equ 0x01c8 CY16 R2 register COMM R3 equ 0x01ca CY16 R3 register COMM R4 equ 0x01cc CY16 R4 register COMM R5 equ 0x01ce CY16 R5 register COMM R6 equ 0x01d0
19. CY16 R6 register COMM R7 equ 0x01d2 CY16 R7 register COMM R8 equ 0x01d4 CY16 R8 register COMM R9 equ 0x01d6 CY16 R9 register COMM R10 equ 0x01d8 CY16 R10 register COMM R11 equ 0x01da CY16 R11 register COMM R12 equ 0x01dc CY16 R12 register COMM R13 equ 0x01de CY16 R13 register Chapter 2 Link Control Protocol Firmware Page 2 3 BIOS User s Manual 2 2 3 2 Command Descriptions This software interrupt service routine is for selected ports i e HPI HSS SPI will signal the Icp_idle task by posting new command to the COMM PORT CMD Upon receiving a new com mand set the Icp_idle task handles processing of all the port commands and their associated responses Entry COMM PORT CMD equ Ox0lba For PORT Command COMM MEM ADDR equ OxOlbc For COMM RD WR MEM COMM MEM LEN equ OxOlbe For COMM RD WR MEM COMM LAST DATA equ 0x01c0 memory pointer for mem Exit None Note When sending the COMM PORT CMD 0 the lcp idle task will not response to this com mand Each of the port commands is serviced by calling the Virtual Callback function in the selected transport module HPI HSS SPI The following port commands are serviced COMM RESET Action Do soft reset to the Icp idle task Data Used None Response COMM ACK The COMM RESET command can be used to do soft reset the Icp idle task Response COMM ACK Note An ACK will be sent immediately after receiving this command
20. EOP based on the speed and return the speed for that port rl cPortA port A ro 10 USB reset interval is 10 ms HUSB RESET INT Reset USB and genera SOF 1 7 5 USB Peripheral Interrupt Functions The following functions are dedicated for the USB Peripheral design and subsequently described SUSB INIT INT SUSB1 DEVICE DESCRIPTOR VEC SUSB2 DEVICE DESCRIPTOR VEC SUSB1 CONFIGURATION DESCRIPTOR VEC SUSB2 CONFIGURATION DESCRIPTOR VEC SUSB1 STRING DESCRIPTOR VEC SUSB2 STRING DESCRIPTOR VEC SUSB1 FINISH INT SUSB2 FINISH INT SUSB1 STALL INT SUSB2 STALL INT SUSB1 STANDARD INT SUSB2 STANDARD INT SUSB1 SEND INT SUSB2 SEND INT Page 1 30 BIOS User s Manual v1 1 SUSB1_RECEIVE_INT SUSB2 RECEIVE INT e SUSB1 VENDOR INT SUSB2 VENDOR INT e SUSB1 CLASS INT SUSB2 CLASS INT e SUSB1 LOADER INT SUSB2 LOADER INT e SUSB1 DELTA CONFIG INT SUSB2 DELTA CONFIG INT 1 7 5 1 Interrupt 113 SUSB INIT INT The BIOS start up or user code will call this interrupt to enable the designated SIE for peripheral operation In co processor mode this interrupt must be called via the LCP commands In stand alone mode the BIOS will set the SIE1 to the full speed peripheral if the OTG ID GPIO29 pin is high The BIOS will set the SIE2 as the full speed peripheral VA Note During power up ifthe user overrides this interrupt via either serial EEPROM or the external ROM the BIOS will skip this interrupt The debugger will not work with
21. INT and SUSB2 RECEIVE INT It handles retry when detect ERROR in the USB BUS After the transfer of data that defines this interface is complete it will set bits 1 7 in the HPI mailbox register 0x148 Chapter 1 BIOS Interface Page 1 17 BIOS User s Manual 1 6 Debugging Tools support The BIOS supports the debugger via the following interfaces UART Default baud rate 28800 8 bit no parity 1 stop bit flow control none The UART port will be used by the debugger USB portC will be used by the debugger HPI HSS SPI via LCP The debugger software does not support debugging over these interfaces Users will make use of these interfaces for their application development Note USB portA can also be used for the debugger when it is configured as the peripheral In co processor mode both USB portA and USB portC will not be available to the debugger Only the UART will be available in the EZ Host chip because of design requirements Note In co processor mode the debugger on the USB ports can be enabled by calling the SUSB_INIT_INT via the LCP interface in both EZ Host and EZ OTG devices Note The UART and USB debugging ports are not available when the EZ OTG chip is setup in the HPI mode co processor mode because HPI pins are shared with the UART pins However the UART will be available when the EZ OTG chip is setup in either HSS or SPI mode Note The UART debugging port is available when the EZ Host chip is setup in the HP
22. REG LOGIC Response COMM ACK This command is designed to poke a data word into any location from 0x0000 to OxFFFF address space For HPI the COMM MEM ADDR Ox1BE COMM MEM LEN and the COMM CTRL REG LOGIC variables must be written from the direct hardware memory access For HSS SPI these variables are part of the 4 word command data structure COMM CTRL REG LOGIC is an optional parameter it must default to zero for HSS and SPI It allows the write operation to write with bitwise AND or bitwise OR COMM_CTRL_REG_LOGIC WRITE OPERATION USED Direct Write AND the register value N 0 OR the register value COMM _READ_MEM Implemented in HSS and SPI Transports Only Action Read Memory Data Used COMM_MEM_ADDR COMM_MEM_LEN Response COMM_ACK This allows reading words from INTERNAL memory This command is not required for HPI communications since there is direct memory access The HPI can access the internal mem ory from Ox0000 0x3FFF and OxE000 OxFFFF Page 2 6 BIOS User s Manual v1 1 Note COMM_MEM_LEN specifies the number of words to transfer The BIOS will not check the valid range of INTERNAL memory If users want to access the external memory bus they should use the COMM_READ_XMEM However if the address range is not valid the data will not be valid COMM _WRITE_MEM Implemented in HSS and SPI Transports Only Action Write Memory Data Used COMM_MEM_ADDR COMM_MEM_LEN Respon
23. alignment dw 4 db 0 mov 0xc008 0 dw 0xc008 address 0xc008 dw 0 data 0 dw 0xC3B6 dw END START 2 Include the length 1byte alignment db 0 Type 0x00 Copy from external ROM to external RAM dw IRAM Copy to external RAM starts at 0x500 reloc IRAM Relocate compiled symbols START User code Beginning of program starts here Code and Data END The following sequence instructs the BIOS to execute the copied program Signaturel dw OxC3B6 dw 2 Length 2 db 5 Type 0x05 call the following location dw IRAM Jump to IRAM code start db 0 Stop Scan word 1 7 2 2 Interrupt 79 SCAN DECODE INT Interrupt 67 calls interrupt 79 for function table decoding of the interrupt 67 calls Interrupt 79 is reserved for BIOS use 1 7 2 2 4 Software Interface Entry R7 pointer to get next byte subroutine Registers Usage RO R8 R9 Return RO 0 Page 1 24 BIOS User s Manual v1 1 Example BIOS Listing of the SCAN INT that call the SCAN DECODE INT scan call cmp jne call mov call int jmp scan_get_word r0 0xc3b6 Scan exit Scan get word length 12 0 r7 Opcode SCAN DECODE INT scan Scan exit xor ret r0 ro PRR RRR RK RK KKK KKK KK KK KKK KK KK KK KK KK KK KK KK kk kk kkk kkk kk kk kkk KKK KK KK KKK return r0 word data PRR RR KR KEKE KEK KK KK KK KKK KK KK KK KK KK KK KK KKK KKK KEK KEK KKK KKK KKK ck ck ckck ck ck ckck ck k scan_get_ call push call shl or ret
24. by HPI Transport to support LCP Not used Reserved for BIOS Not used Reserved for BIOS ISR Used by SPI Transport to support LCP ISR ISR Used by SPI Transport to support LCP ISR ISR services a single packet via the Transfer Descriptor TD It will post the message to the HPI mailbox register x144 with 0x1000 after all the TD list items are serviced ISR services the TD list that supply from the application As soon as the TD is not empty it will start TD transaction IS om ISR enter this ISR after 5us of the falling edge of the USB_RESET This interrupt will call the SUSB1_INIT_INT and will post the message to the HPI mailbox register 0x144 with value 0x100 ISR services for every 1ms SOF detect from USB Host After second SOF detection it will send a message to HPI mailbox register 0x144 with value 0x200 After detecting seven consecutive missing SOFs it will set the value 0x800 to the HPI mailbox register 0x144 ISR services a single packet via the Transfer Descriptor TD It will post the message to the HPI mailbox register 0x148 with 0x1000 after all the TD list items are serviced ISR services the TD list that supply from the application As soon as the TD is not empty it will start TD transaction BIOS User s Manual v1 1 Table 1 6 Hardware Interrupt Table Continued Interrupt Number Interrupt Name Notes 28 SIE2 Peripheral Reset ISR enter this ISR after 5us of the falling edge of th
25. data from a USB host to complete a transaction involving multiple OUTs These interrupts will break up user data into multiple payloads that are defined by the Endpoint Descriptors and the call back will be called or the message interrupt will be set after finishing the transfer These interrupts supports both stand alone and co processor modes In stand alone mode the user should provide the call back to check for the completion In co processor mode a message interrupt will be set in either register 0x144 for SIE1 or register 0x148 for SIE2 1 7 5 9 1 Software Interface Each interrupt is passed an 8 byte structure to control the transmission of data over the USB bus and an endpoint number Device Descriptor must be setup prior this call For endpoint1 7 the Interface Endpoint descriptors must be setup and configured These inter rupts should be called after SUSBx_DELTA_CONFIG_INT If the interrupts are called before they are configured they will not work The call back subroutine should not use any sti and cli instructions Normally this subroutine will notify the application that either the task is complete or additional buffers are to be sent When using these interrupts in co processor mode via the HPI interface disable the interrupts uDone1 and uDone2 in the HPI SIE IE register at address 0x142 i e both bits should be cleared Note When both of these bits are enabled the co process
26. for each slave SIE that contains its configuration and state Device descriptors are required to support Chapter 9 processing and contain configuration information so descriptor cen tric routines should be used to facilitate flexibility and save space Each slave mode configured SIE would have a collection of information that the slave processing routines would use to service it SIE Chapter 4 Control Transfer Processor EPO ISR n P SIE Data EP Data Descriptors Generic EP Frame Control Regs Chapter 9 Loader Vendor 4 Class I Generic Endpoint Support Finish Transfer ee Figure 4 3 Control Transfer Processing Architecture Slave Support Module Firmware Page 4 5 BIOS User s Manual The overall structure of a slave control transfer processor is sketched in Figure 4 3 Each SIE has an ISR called on hardware interrupt and a collection of state and configuration data The ISR sets up the call into the Control Transfer Processor by referencing the appropriate collection and may complete a register bank switch The transfer processor then utilizes its logic and override able software interrupts shaded in Figure 4 3 to complete the transaction and prepare for the next This support is entirely contained in the BIOS 4 3 2 Generic Endpoint Support Generic Endpoint support is a routine that is at least initia
27. indicates the byte count of received packets was greater than the value from Port Length 3 5 9 NextTDPointer WORD 0x0A 0B Table 3 9 NextTDPointer WORD 0x0A 0B Bit Position Bit Name Function 0 15 NextTDPointer NextTDPointer The NextTDPointer must carry the pointer to the next TD when submitting a TD This Value stays the same in the BIOS process If the TD is the last one in the TD list its NextTDPointer should be 0 Example If the Next TD address is 0xA14 OxA14 should be written into NextTDPointer Note 1 All the reserved bits should put 0 2 The following table shows the fields that get updated inside EZ Host EZ OTG BIOS Name Updated inside the EZ Host EZ OTG device BaseAddress NO Port_Length NO PID_EP NO DevAdd NO Control NO Status YES RetryCnt YES Residue YES NextTDPointer NO In the RetryCnt field TransferType is not updated Chapter 3 USB Host BIOS Specifications Page 3 15 BIOS User s Manual 3 6 Error Handling Error handing is done by both BIOS and HCD BIOS will handle Control Bulk transaction errors HCD will handle ISO Interrupt transaction errors Details are shown in Figure 3 6 The BIOS handles the error in the following way Serious Error Sequence error Overflow Underflow e Stall For these serious errors BIOS halts this PIPE in that frame All the successive TDs with this PIPE having the same port number device number and endpoint number will be m
28. message is then readable by the host at HPIMAILBOX register on the HPI port When EZ Host EZ OTG writes to the MailBoxMsg register an interrupt is generated and sent to the HPI port as the HPI INTR signal The interrupt is automatically cleared when the Host reads from the HPIMAILBOX register of the HPI port When EZ Host EZ OTG is configured for HPI mode the HPI INTR signal shares the pin with GPIO24 The HPI INTR state can be polled by the CY16 processor at bit 8 of the GPIO INPUT REGISTER 1 This document describes BIOS operation and software interrupts The following sections define pictorially the interrupt vectors and the BIOS calls Page 5 4 BIOS User s Manual v1 1 5 3 7 HPI TRANSFER DIAGRAMS FOR LCP 5 3 7 1 COMM_RESET via HPI Send 16 byte LCOMM_REsSET Command Wait for Response Figure 5 2 COMM RESET via HPI 5 3 7 2 COMM JUMP2CODE via HPI Set Jump SET Co Address MM CODE Appg Send CMD COMM_JUMP2copE Wait for Response Jump After Send Response Figure 5 3 COMM JUMP2CODE via HPI VA Notes COMM_CODE_ADDR is defined as same as the COMM_MEM_ADDR which is a pointer to the code to jump to it is written via HPI Direct Memory Access not the mailbox Then the COMM_JUMP2CODE can be sent over the mailbox Of course before either of these operations is done the code itself should exist in the memory space that COMM_CODE_ADDR will point to If the code jumped to does not return then the ACK wi
29. rate is one word every 6 T where T is 1 48MHz resulting in a rate of 16 Mega byte second Refer to section 6 for HPI write and read cycle timing specifications Chapter 5 HPI Transport Module Page 5 3 BIOS User s Manual 5 3 4 HPI INIT Routine The HPI INIT routine is called to enable LCP messages to be processed via the HPI Transport The INIT Routine performs the following Loads HPI Commands Processor table Enables HPI I F via EZ Host EZ OTG Control Registers Enables RX in the Interrupt Enable Register 5 3 5 Host to EZ Host EZ OTG MailBox Message The HPI Mailbox RX ISR is triggered when the external CPU writes to the HPI mailbox The ISR will get the 16 bit word from the mailbox Host sends a single 16 bit word message to the EZ Host EZ OTG device by writing to the HPI MAILBOX register of the Host Interface Port The message word is readable by the CY16 CPU as the HostMailBoxMsg register When Host writes the HPIMAILBOX register of the HPI port an interrupt is generated within the EZ Host EZ OTG on chip processor The interrupt is automatically cleared when the CY16 CPU reads from the HostMailBoxMsg register The incoming mailbox interrupt is maskable via bit 6 of the INTERRUPT ENABLE REGISTER This register is initialized to zero by the hardware at reset 5 3 6 EZ Host EZ OTG to Host MailBox Message The EZ Host EZ OTG part sends a single 16 bit word message to Host by writing to the Mail BoxMsg register The
30. s request i e a bus drop a bus req b bus req etc The results of this interrupt will return the state transition from the current to the next state that follow the OTG supplement to the USB 2 0 specification 1 7 3 2 1 Software Interface Entry RO 15 0 bits are defined as follow a bus drop equ 0x0001 from application A device request bus drop a set b hnp en equ 0x0002 from application enable hnp bus_req equ 0x0004 from application for both a bus req amp b bus req a suspend req equ 0x0008 from application A device request bus suspend b do srp equ 0x0010 from app must call otg srp then set this variable b hnp en equ 0x0040 from app Slave needs to detect the SET FEATURE b speed equ 0x0080 from app O full 1 low Registers Usage None Return RO OTG_STATE location at address 50 2 0x0064 RO return one of the value define as shown below Page 1 26 BIOS User s Manual v1 1 a_idle equ 0 a wait bcon equ 1 a host equ 2 a suspend equ 3 a peripheral equ 4 a wait vfall equ 5 b idle equ 6 b peripheral equ 7 b host equ 8 Note BIOS handles these following states for a idle state machine a idle gt a wait vrise a wait bcon a wait vrise is handled by the BIOS Any state transition to a vbus err will go to a wait vfall b idle gt b em init when bus req and b do srpare true BIOS will do the b srp init and return back to b idle If the state is in b peripheral BIOS will handle
31. should not be used in the idle task context This interrupt is the functional equivalent of Interrupt 73 but avoid using multiple HW SWAP REG and nested interrupts 1 7 7 7 1 Software Interface Entry None Registers Usage RO R14 will be unknown Return All registers are saved in the second register bank fast equivalent to Interrupt 73 Use only in interrupt routines when interrupts are disabled NOT REENTRANT 1 7 7 7 2 Example Example 16 Hardware saves all working registers inside the interrupt service subroutine HW SWAP REG equ 71 HW REST REG equ 78 Endpoint2 int INT HW SWAP REG Save all registers process endpoint 2 interrupt Do not nest this interrupt INT HW REST REG restore all registers re enable int and return Chapter 1 BIOS Interface Page 1 59 BIOS User s Manual 1 7 7 8 Interrupt 78 HW_REST_REG Restore register bank This Interrupt is used to restore CPU flags and all registers from the second register bank and it will re enable the interrupt and return to the context switch from the HW_SWAP_REG This inter rupt is a functional equivalent of Interrupt 74 but avoid using multiple HW_REST_REG and nested interrupts This interrupt should be paired with interrupt 77 and cannot be called in the idle task context 1 7 7 8 1 Software Interface Entry None Registers Usage RO R14 will be restored of the previous value from HW SWAP REG Return All registers from the previous value from HW SWAP R
32. tasks call the SCAN interrupt for the special signature word 0xC3B6 not 0xCB36 from the UART USB All chip access utilities and debuggers use this command protocol The following functions are supported and subsequently described SCAN INT SCAN DECODE INT 1 7 2 1 Interrupt 67 SCAN INT The SCAN interrupt is used in conjunction with other software interrupts to allow loading and exe cuting of user code and data During boot up the BIOS scans the external ROM and serial EEPROM I2C for a valid Scan Signature of OxC3B6 If found the Signature Scan Opcodes and data are processed allowing code and data to be moved into the CY16 s RAM space and exe cuted As mentioned earlier the debugging utilities use this system for low level communication to the EZ Host or EZ OTG devices During run time BIOS will use the uart idle and usb idle back ground tasks to continuously scan the signature So these tasks need to be maintained see the STUB source code and this requires correct use of the IDLE INT Note Interrupts will not be enabled until these scans have been completed During the BIOS boot up a special external ROM signature of 0xCB36 will cause the BIOS to jump into the location following the signature for the entire BIOS override Chapter 1 BIOS Interface Page 1 21 BIOS User s Manual 1 7 2 1 1 Software Interface Entry R7 Contains the address of a subroutine that is called by this interrupt when the next byte is requi
33. will become the first task to be executed usb_idle This USB idle task handles all USB peripheral ports i e USB portA and USB portC It does all the call back services from the following interrupts SUSB1_SEND_INT SUSB2_SEND_INT SUSB1_RECEIVE_INT and SUSB2_RECEIVE_INT In addition it also sup ports the SCAN INT by monitoring the USB Vendor Command Class with the bmRequest OxFF The debugger tools will communicate through this USB Vendor Command Class Icp_idle This LCP idle task handles all the LCP command processing for HPI HSS and SPI ports that depend on the boot up pin configuration on GPIO31 30 In addition it also supports the mailbox message service when the chip is configured in co processor mode In stand alone it will be in idle mode uart_idle This UART idle task handles all debugging commands that support debugger tools via the SCAN_INT VA Note Interrupt 70 cannot be blocked If users decide to replace this interrupt vector the substi tuted vector must maintain execution of the idle task If it does not unpredictable behavior will occur When executing this interrupt users need to make sure all the registers should be reserved and properly restore see Example 17 Execute Interrupt 70 1 7 8 1 1 Software Interface None 1 7 8 1 2 Example Example 17 Execute Interrupt 70 int PUSHALL INT int 70 execute int 70 int POPALL INT Note Do not modify this interrupt 1 7 8 2 Interrupt 71 IDLER INT
34. 0 Dec RetryCnt No Figure 3 6 Error Handling Interface Chapter 3 USB Host BIOS Specifications Page 3 17 BIOS User s Manual 3 7 Schedule Bus Transaction Times Before transferring all TD data it must calculate how much bus time is required for a given TD data These calculations are required to ensure that the time available in a frame is not exceeded This schedule or calculation is based on USB 2 0 Specification Section 5 11 3 The equations used to determine transaction bus time are KEY Data bc Host Delay Floor Hub LS Setup BitStuffTime The byte count of the data payload The time required for the host to prepare for or recover from the transmission For the EZ Host EZ OTG parts the required time is 106 full speed bit times For the BIOS calculation after reading the SOF timer register it takes 21 full speed bit times to do the transfer The integer portion of the argument The time provided by the Host controller for hubs to enable low speed ports This is measured as the delay from the end of the PRE PID to the start of the low speed SYNC the minimum being four full speed bit times Function that calculates theoretical additional time required due to bit stuffing in signaling the worst case is 1 1667 8 Data bc Full speed Input Non Isochronous Transfer Handshake Included 9107 83 54 Floor 3 167 BitStuffTime Data bc Host Delay 9107
35. 0 calls to SUSBx RECEIVE INT should be made or to SUSBx SEND NT if data is to be returned This is at interrupt level you may use any registers but you should return promptly Page 1 38 BIOS User s Manual v1 1 1 7 5 7 2 Example Example 5 Intercept Standard Interrupt vector for SIE1 port A old_standard_vec dw 0 STD VEC equ SUSB1 STANDARD INT 2 usb init Software initialization subroutine mov old standard vec STD VEC save old standard vector replace new standard vector mov STD VEC new standard isr ret Given the following device request offsets bmRequest equ 0 bRequest equ 1 wValue equ 2 windex equ 4 wLength equ 6 new_standard_isr r8 was pointed to 0x300 test b r8 bRequest OxEO jis it a clear stall command jnz ef jit is not a clear stall command Add new stall request handler here ret jmp old standard vec 1 7 5 8 Interrupt 80 96 SUSB1 SEND INT SUSB2 SEND INT Send data to USB SIE1 2 endpoint x respectively The support these interrupts provide simplifies all transfers across all endpoints i e endpointO 7 by providing a uniform interface and behavior An application prepares a buffer and a control header block referencing the buffer The control header block will contain a pointer to the buffer the buffer s length a null next control header block pointer and a call back routine pointer These interrupts are utilized to send user data from any USB endpoin
36. 0x8000 used 0x0000 free Page 1 56 BIOS User s Manual v1 1 1 7 7 3 Interrupt 68 ALLOC_INT This interrupt is used to allocate available memory detected by the BIOS at boot up 1 7 7 3 1 Software Interface Entry RO Number of bytes to allocate Only bits 0 14 are used for the size of memory since 32 K is the max Registers Usage None Return RO Location of allocated memory Returns 0x0000 if not enough memory is available Note Memory is always allocated in an even number of bytes and is guaranteed to be on an even boundary 1 7 7 3 2 Example Example 13 Memory allocation ALLOC INT equ 68 malloc mov ro 100 allocate 100 bytes int ALLOC INT do interrupt 68 or r0 ro check if memory available jz Error mov r8 r0 r8 contains pointer to allocated memory mov r8 O clear first location Error 1 7 7 4 Interrupt 75 FREE INT This Interrupt is used to free the memory that has been allocated by Interrupt 68 1 7 7 4 1 Software Interface Entry RO is a pointer to memory allocated previously by Interrupt 68 Registers Usage None Return None Note You should use caution when allocating and freeing memory to avoid memory fragmenta tion Chapter 1 BIOS Interface Page 1 57 BIOS User s Manual 1 7 7 4 2 Example Example 14 Free memory FREE INT equ 75 see Interrupt 75 free mem mov r0 r8 get previous allocation pointer int FREE_INT free after used 1 7 7 5 Interr
37. 1 37 1 7 5 5 2 Example ta ee rr Ete e ERR re Dee E 1 37 1 7 5 6 Interrupt 82 98 SUSB1 STALL INT SUSB2 STALL INT 1 37 1 7 5 6 1 Software Interface oooooccoccnnnnnccccnnncococcconocononcnnncnononccnnnnnnnnccnncanannncnnnanns 1 37 1 7 5 7 Interrupt 83 99 SUSB1 STANDARD INT SUSB2 STANDARD JINT 1 37 1 7 5 7 1 Software Interface cion ee endete deas ne ee 1 38 Uca 1 39 1 7 5 8 Interrupt 80 96 SUSB1 SEND INT SUSB2 SEND INT Send data to USB SIE 1 2 endpoint x respectively sss 1 39 1 7 5 8 1 Software Interface oooooococcnnnnocccccnnocococccoconononcnnncnononccnnnnannnccncnanannncnnnanns 1 40 1 7 5 8 2 Example iit a e lo eset ada 1 41 1 7 5 9 Interrupt 81 97 SUSB1 RECEIVE INT SUSB2 RECEIVE INT Receive data from USB endpoint x 1 44 1 7 5 9 1 Software Interface oooooccoccnnnncccccnnnocococcconcnononcnnnnnono nono ncnannnccnncanannncnnnnnns 1 44 ARAS EE 1 46 1 7 5 10 Interrupt 85 101 SUSB1 VENDOR INT SUSB2 VENDOR INT 1 48 1 7 5 10 1 Software Interface 1 48 1 7 5 10 2 ul 1 49 1 7 5 11 Interrupt 87 103 SUSB1 CLASS INT SUSB2 CLASS JINT 1 50 1 7 5 11 1 Software Interface seesssssssssssssesseeenenenee nennen 1 50 IAS Eech EE RE etre aee i 1 51 1 7 5 12 Interrupt 94 110 SUSB1_LOADER_INT SUSB2_LOADER_ INT 1 52 Table of Contents CYPRESS Table of Contents 1 7 5 12 1 Software Inte
38. 3 16 0x20 SIE1 Host Done reserved for BIOS 1 17 0x22 SIE1 Host SOF reserved for BIOS 1 18 0x24 SIE1 Host Ins Remove free for developer 3 19 0x26 Reserved for future hardware 4 20 0x28 SIE1 Peripheral Reset reserved for BIOS 1 21 0x2A SIE1 Peripheral SOF reserved for BIOS 1 22 0x2C Reserved for future hardware 4 23 0x2E Reserved for future hardware 4 24 0x30 SIE2 Host Done reserved for BIOS 1 25 0x32 SIE2 Host SOF reserved for BIOS 1 Chapter 1 BIOS Interface Page 1 13 BIOS User s Manual Interrupt Number 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 NOTES Table 1 4 Hardware Interrupt Table Continued Vector Address 0x34 0x36 0x38 Ox3A 0x3C Ox3E 0x40 0x42 0x44 0x46 0x48 0x4A 0x4C 0x4E 0x50 0x52 0x54 0x56 0x58 Ox5A 0x5C Ox5E Interrupt Type SIE2 Host Ins Remove free for developer Reserved for future hardware SIE2 Peripheral Reset reserved for BIOS SIE2 Peripheral SOF reserved for BIOS Reserved for future hardware Reserved for future hardware SIE1 Endpoint 0 Interrupt reserved for BIOS SIE1 Endpoint 1 Interrupt reserved for BIOS SIE1 Endpoint 2 Interrupt reserved for BIOS SIE1 Endpoint 3 Interrupt reserved for BIOS SIE1 Endpoint 4 Interrupt reserved for BIOS SIE1 Endpoint 5 Interrupt reserved for BIOS SIE1 Endpoint 6 Interrupt reserved for BIOS SIE1 Endpoint 7 Interrupt reserved for BIOS SIE2 Endpoint 0 Interrupt reserved for BIO
39. A000 OxBFFF 8 KBytes 1 2 3 DRAM SRAM ROM Memory Mapped Registers 0xC000 OxCOFF 256 Bytes External ROM External SRAM 0xC100 OxDFFF 7 936 Bytes 3 Internal ROM OxE000 OxFFFF 8K Bytes NOTES 1 If code is contained in the Extended Memory Pages only 32K is usable because the CY16 RISC Core has 16 bit address generation 2 If used for ROM space total ROM space is 16K 7936 3 The external memory interfaces are only available on the EZ Host and not on EZ OTG Figure 1 2 illustrates how memory is organized Each external memory space can be 8 or 16 bits wide and can be programmed to have up to seven wait states On power up the BIOS sets all the default external memory wait state at 7 wait states i e Register OxCO03A will be initialized to 0x27F7 Note Each memory wait state results in an extra 20 8ns added to the read write cycle Chapter 1 BIOS Interface Page 1 5 BIOS User s Manual Internal Memory HW INT s 0x000 OxOFF SW INT s 0x100 Ox11F Primary Registers 0x120 Ox13F Swap Registers 0x140 0x148 HPI Interrupt and Mailbox 0x14A Ox1FF LCP CMD Processor Variables 0x200 Ox2FF USB Registers 0x300 Ox30F Slave Setup Packet 0x310 Ox3FF BIOS stack 0x400 0x4A2 USB slave and OTG USER CODE 0x4A4 Ox3FFF 15KB External Memory 0x4000 EXT RAM 8k 0x8000 8K Extended Memory Page 1 DRAM SRAM ROM 8K Extended Memory Page 2 DRAM SRAM ROM OxA00 OxC000 OXCO
40. BIOS Interface Page 1 51 BIOS User s Manual Usbl1_ep0 send data send count in 17 of data pointed to by 18 usbl epO send data mov epo link 0 mov epO call epO done mov ep0_loc image line image buffer pointer mov ep0_len r7 size of the image line mov r8 ep0 link r8 pointer to linker mov rl 0 r1 0 setup endpoint 0 int SUSB1 SEND INT call interrupt ret VCPUPoke Write a Word to a specific address vCPUPoke wValue Addr wIndex Data wLength 0 mov r9 r8 wValue get address mov r9 r8 wIndex write data jmp ep0_done send ack VCPUPeek reading data from given address and count vCPUPeek wValue Addr wIndex 0 wLength Count usbl ep send data mov r9 r8 wValue address mov r7 r8 wLength length mov 4r8 r9 jmp usbl ep0O send data host read from end point 0 ep0_ done int SUSB1_FINISH INT ret data send receive control header block ep0_link dw 0 ep0_loc dw 0 ep0_len dw 0 ep0 call dw 0 1 7 5 12 Interrupt 94 110 SUSB1_LOADER_INT SUSB2_LOADER_INT These interrupts vectors are designed to support the debugger and should not be modified by the user BIOS uses the USB idle task to monitor the Vendor Command Class packet with the bRequest value equal to Oxff i e debugger command When this command is detected it will call these interrupts 1 7 5 12 1 Software Interface Since the scan signature header is bigger than 8 all the debugger commands for the SCAN_INT are
41. BIOS User s Manual 1 3 1 CY16 Memory Map The total memory space directly addressable by the CY16 processor is 64 Kbytes Program data and I O space are contained within a 64 Kbyte address space The program code or data can be stored in internal RAM external RAM or external ROM The EZ Host device allows extended data or program code to be stored in external DRAM SRAM or ROM The total size of extended memory can be up to 2 MByte The CY16 processor can access extended memory via two address windows of 0x8000 0x9FFF and 0xA000 OxBFFF The page register 0xc018 is used to control the address window 0x8000 Ox9FFF and the page register 0xC01A is used to control the address window of 0xA000 0xBFFF The HSS HPI SIE1 SIE2 SPI IDE DMA engines ONLY transfer data between the support hard ware to internal RAM IRAM and or internal ROM IROM Setting up DMA to external memory space may result in internal RAM data corruption because the hardware does not check the address range For example setting up a DMA transfer to an external memory address like 0x8000 might result in a DMA transfer into address Ox0000 The EZ Host device provides a 16 bit memory interface that can support a wide variety of external DRAM RAM and ROM devices At boot up time the BIOS attempts to detect 8 bit 16 bit external RAM and external ROM For external RAM that is mapped to 0x4000 0x7FFF BIOS attempts to check the size 8 bit 16 bit via a write followed by a read verif
42. BIOS User s Manual v1 1 6 3 8 4 COMM_WRITE_CTRL_REG via SPI COMM WRITE CTRL REG 7 0 a OMM_WRITE CTRL REG 15 8 OMM CTRL REG appr 7 0 Send 8 Byte COMM SE CTRL REG Appg 15 8 OMM CTRL REG DATA 7 0 C OMM CTRL REG DATA 15 8 C DVM CTRL REG Logic C HMM CTRL REG Log 15 8 Poll for non OxFF Wait oxFF sponse 7 0 Get d Bye of Response 15 8 Response Figure 6 4 COMM WRITE CTRL REG via SPI Chapter 6 SPI Transport Module Firmware Page 6 7 BIOS User s Manual 6 3 8 5 COMM_READ_CTRL_REG via SPI COMM READ CTRL REG 7 0 COMM READ CTRL REG 15 8 C OMM CTRL REG Appr 7 0 Send 8 Byte COMM CTR CMD Packet REG ADDR 15 8 XXh Poll for non a OxFF OxFF QU Wait OXF Response 7 0 Get Response 15 8 2 Bytes of 7 0 Ens COMM CTRL REG DATA G DATA 15 8 followed by 2 L RE MM_CTRL_ bytes of Data oN Figure 6 5 COMM_READ_CTRL_REG via SPI Page 6 8 BIOS User s Manual v1 1 6 3 8 6 COMM_WRITE_MEM via SPI COMM WRITE Mey 7 0 COMM WRITE My 15 8 COMM MEM Appg Go Send 8 Byte C CMD Packet o ADDR 15 8 COMM_MEM_LeNr1 5 8 Poll for non OxFF Get 2 Bytes of e 15 8 Response Respons i Mem Value 1 7 0 Mem Value 1 15 8 Send n Words of Data Mem Value n 7 0 Mem Value n 15 8 Figure 6 6 COMM WRITE MEM via SPI Chapter 6 SPI Transport Module Firmware Page 6 9 BIOS User s Manual 6 3
43. B_RESET 1 117 OxEC KBHIT_INT 1 118 125 OxEE OxFA Free for developers 3 4 126 127 OxFC OxFF Reserved for debugger 3 NOTES 1 These software vectors are used by the internal BIOS 2 These vectors are used as the data pointers Users should not execute code i e JMP or INT to these vectors 3 These interrupt vectors are not initialized 4 These interrupt vectors are free for developers Page 1 20 BIOS User s Manual v1 1 1 7 1 Interrupt 48 49 LCP Message Subroutines The BIOS uses these two interrupts for the Icp_idle task so users should not modify these inter rupts Note LCP only supports the HPI HSS SPI hardware interfaces and is designed to work in co processor mode 1 7 2 Signature SCAN Support The signature scan support is a comprehensive control protocol that allows UART serial EEPROM 12C USB and external ROM to interface to the BIOS The design of this interface provides users a consistent method to expand the capabilities of the BIOS over ride BIOS functions and support a debugger interface At power up the BIOS will do a signature SCAN for the I2C stand alone mode and external ROM After power up the BIOS will create two idle tasks which are UART tasks and USB tasks for monitoring the signature SCAN in real time Note Both these tasks run concurrently so both debuggers can be executed at a same time The BIOS reserves a background task for the UART USB via the uart_idle and usb_idle tasks These background
44. CO OO OO Lu OO OH Chapter 1 BIOS Interface replace new device descriptor replace new configuration descriptor length desc type USB spec 1 1 device class device subclass protocol max packet size for endpoint 0 TBD is the new vendor id and new product id device release number index of manufacture string index of product string index of serial number string number of configurations len of config type of config one interface config 1 index of string describing config attributes self powered base alt endpoints interface class vendor subclass interface proto vendor index of string describing interface Page 1 33 BIOS User s Manual epl db 7 length db 5 type endpoint db 0x81 type number db 2 Bulk dw 64 packet size db 0 interval ep2 db 7 length db 5 type endpoint db 0x02 type number Host uses WriteFile db 2 Bulk dw 64 packet size db 0 interval ep4 db 7 length db 5 type endpoint db 0x84 type number Host uses WriteFile db 3 Interrupt dw 8 packet size db 0 interval new_end all align 2 new string desc db STRO LEN db 3 dw 0x409 english language id STRO LEN equ new string desc strl db STR1 LEN db 3 dw Manufacturing STR1 LEN equ strl str2 db STR2 LEN db 3 dw Product STR2 LEN equ str2 str3 db STR3 LEN db 3 dw SerialNumber STR3 LEN equ str3
45. DDR 7 0 CO Send 8 Byte M CMD Packet M CTRL REG ADDR 15 8 E Wait for 2 Bytes of Response followed by 2 bytes of Data Figure 7 5 COMM READ CTRL REG via HSS Page 7 8 BIOS User s Manual v1 1 7 3 7 6 COMM_WRITE_MEM via HSS COMM WRITE MEM 17 0 COMM WRITE Mem y Es COMM MEM appr 7 0 COMM MEM Ap 15 8 Send 8 Byte CMD Packet COMM MEM Len 15 8 XXh XXh Wait for 2 Bytes of Response Response 7 0 Response 15 8 Mem Value 1 7 0 Mem Value 1 15 8 Send n Words of Data Mem Value n 7 0 Mem Value n 15 8 Figure 7 6 COMM WRITE MEM via HSS Chapter 7 HSS Transport Module Page 7 9 BIOS User s Manual 7 3 7 7 COMM_READ_MEM via HSS COMM READ MEM 7 0 COMM READ MEm 15 8 COMM MEM Apps 7 0 Send 8 Byte COMM MEM ADDR 15 8 CMD Packet COMM MEM LEN 7 0 COMM MEM EN 15 8 AXh XXh Wait for 2 Bytes of ec byn Response 7 0 words of Data Soe 15 8 Figure 7 7 COMM READ MEM via HSS Page 7 10 BIOS User s Manual v1 1 7 3 7 8 COMM WRITE XMEM via HSS COMM WRITE XMEM 7 0 CO MM WRITE XMEM 15 8 COMM MEM LEN 7 0 O B Byte I COMM MEM EN 15 8 CMD Packet COMM MEM ADDR 7 0 CO MM MEM ADDR 15 8 COMM LAST pata 7 0 CO Wait for 2 Bytes of Response 7 01 Response Response 15 8 Mem Value 1 7 0 Mem Value 1 15 8 Send eS eee n Words of Data Mem Value n 7 0 M
46. EG Note Interrupt 77 and Interrupt 78 should be used in pairs The interrupt 78 does not need the addition sti and ret instructions see Example 16 for source code listing 1 7 7 8 2 Example Interrupt 77 and interrupt 78 source code hw swap reg ant 77 push 1ags Save CPU flags 0xc000 mov hw int stack 30 r15 new r15 cur r15 mov regbuf hw int stack regbuf 0xc002 swap the reg files jmp r15 2 return to the caller hw rest reg int 78 mov regbuf 0x100 restore hardware register addi r15 4 adjust to the last r15 mov flags r15 4 CPU_flags 0xc000 restore CPU flags sti for ISR use only ret 1 7 8 BIOS Idle task functions 1 7 8 1 Interrupt 70 IDLE_INT This interrupt is the entry point to a chain of idle tasks i e the beginning of the task link list This linked list of tasks is executed whenever there are no interrupt routines active They are performed as background tasks INT 71 calls this task list endlessly By default there are three idle tasks in the idle chain which are int 70 gt usb_idle gt Icp_idle gt uart_idle gt return Page 1 60 BIOS User s Manual v1 1 Each task polls its associated port for a Oxc3b6 SCAN_INT signature and allows access to the chip via the SCAN_INT INT 67 protocol The user can add user defined idle tasks via INT 72 INSERT_IDLE_INT Note when the new task is inserted it will be inserted at the top of the task list and it
47. ET INT 3 8 2 1 Software Interface Entry R1 Port number OZUSB PortO 1 USB Port1 2 USB Port2 3 USB Port3 RO time interval for USB reset in milliseconds Return This interrupt returns the speed on that port RO Bito 0 Full speed BitO 1 Slow speed Bit1 1 No device Bit1 0 Device is connected Chapter 3 USB Host BIOS Specifications Page 3 19 BIOS User s Manual 3 8 2 2 Example Reset port A Generate SOF EOP based on the speed and return the speed for that port mov mov int ret 3 8 2 3 Page 3 20 ri cPortA port A ro 10 USB reset interval is 10 ms HUSB RESET INT Reset USB and generate SOF Flow Chart Start v Generate SEO y Hold USB bus v Remove SEO If there is device If slow speed Port Status Port Status Port Status NO DEVICE gt LOW SPEED gt FULL SPEED Enable SOF for full speed device Enable EOP for low speed device Figure 3 7 Flow chart of HUSB_RESET_INT BIOS User s Manual v1 1 Chapter 4 Slave Support Module Firmware 4 1 Introduction 4 1 1 Overview The BIOS includes full speed and low speed slave support for both of its SIEs This support con sists of standard chapter 9 processing specific vendor command processing and generic endpoint support This functionality is all and in part override able The majority of chapter 9 su
48. FF Control Registers 0xC100 EXT ROM OxE000 OxFFFF Internal ROM BIOS 8K Figure 1 2 CY16 Memory Map VA Note The external memory interface is only available on the EZ Host device Page 1 6 BIOS User s Manual v1 1 1 3 2 BIOS Initialization Process On reset the BIOS performs the following Hardware reset Sets the speed control register to divide by 16 0xC008 0x000F This provides the CY16 processor with a 3 MHz clock Sets the program counter to OxFFOO Jumps to 0xE000 the start of BIOS ROM code Sets call stack pointer r15 to 0x400 Sets the speed control register to zero 0xC008 0x0 and disables global interrupt The BIOS then sets the external memory control register for a 16 bit XROM and 16 bit XRAM five wait states OxC03A 0x2777 If an external ROM contains the pattern OxCB36 in location 0xC 100 the BIOS immediately jumps to location 0xC102 The BIOS then tests ROM at location 0xC100 for the pattern OxC3B6 in 8 bit mode If the external ROM shows only the pattern OxB6 then bit 7 of the external memory control reg ister OxCO3A is set to one for 8 bit operation In the EZ OTG device i e the 48 pin package the BIOS sets up from 8 bit ROM mode to GPIO mode if the BIOS does not detect any valid scan signatures Sets 0xC018 0 pageo from 0x8000 0x9FFF and O0xCO1A 1 page1 from 0xA000 OxBFFF Tests and enables RAM at location 0x6000 for 8 or 16 bit operation as app
49. I HSS SPI mode Page 1 18 BIOS User s Manual v1 1 1 7 Software Interrupts The EZ Host and EZ OTG allocate address locations from 0x0060 to OxOOFE to software inter rupts The software interrupt vectors are listed in Table 1 7 Interrupt Number 48 49 50 51 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Vector Address 0x60 0x62 0x64 0x66 0x7F 0x80 0x82 0x84 0x86 0x88 Ox8A 0x8C 0x8E 0x90 0x92 0x94 0x96 0x98 Ox9A Ox9C Ox9E OxAO OxA2 OxA4 OxA6 OxA8 OxAA OxAC OxAE OxBO 0xB2 Chapter 1 BIOS Interface Table 1 7 Software Interrupt Table Interrupt Type Reserved for LCP status message Reserved for LCP asynchronous message Reserved for future BIOS on OTG Variable Data Default 0 OTG State Free for developers Two wire serial EEPROM from 256 byte to 2K byte Two wire serial EEPROM from 4k byte to 16k byte UART_INT SCAN_INT ALLOC_INT Variable Data Pointer start of free memory IDLE_INT IDLER_INT INSERT_IDLE_INT PUSHALL_INT POPALL_INT FREE_INT REDO_ARENA HW_SWAP_REG HW_REST_REG SCAN_DECODE_INT SUSB1_SEND_INT SUSB1_RECEIVE_INT SUSB1_STALL_INT SUSB1_STANDARD_INT OTG_SRP_INT SUSB1_VENDOR_INT default SUSB1_STALL_INT REMOTE_WAKEUP_INT SUSB1_CLASS_INT default SUSB1_STALL_INT Variable Data pointer OTG descriptor SUSB1_FINISH_INT Notes 3 4 e A Jl Al la a a a ay sch Aa a A sc
50. L AST_DATA Ppinter to External Pointer to Internal buffer data COm M WRITE XMEM Send CMD Wait for Response Figure 5 8 COMM WRITE XMEM via HPI Na Notes Users should supply the COMM MEM ADDR COMM MEM LEN COMM LAST DATA and also the users buffer to the address that is pointed to by the COMM LAST DATA before writ ing the command COMM WRITE XMEM in the HPI mailbox The external microprocessor should maintain the memory usage of EZ Host EZ OTG internal memory space The COMM LAST DATA should be allocated inside the internal memory space Page 5 10 BIOS User s Manual v1 1 5 3 7 8 COMM_EXEC_INT via HPI INT Set Int NUM Number and Register Values Wait for Seel Ge Response Response Optionally read COMM_RO Figure 5 9 COMM_EXEC_INT via HPI Notes Users should supply the COMM INT NUM and COMM_R0 R13 before writing the com mand COMM EXEC NT in the HPI mailbox The external microprocessor should read the COMM RO after receiving the ACK from the EZ Host EZ OTG device When executing the COMM INT NUM that does not require COMM_RO COMM_R73 setting value for these RO R13 can be ignored Chapter 5 HPI Transport Module Page 5 11 BIOS User s Manual Page 5 12 BIOS User s Manual v1 1 Chapter 6 SPI Transport Module Firmware 6 1 Introduction 6 1 1 Overview The Serial Peripheral Interface SPI of the CY16 processor provides a synchronous interface to the ext
51. M EXECINT via HSS ge tria qus i ps HR EN eidem du 7 13 Figure 7 4114 COMM CONFIG via HSS sra tuta t av ttbi ia 7 14 List of Figures List of Tables Table 1 1 Table 1 2 Table 1 3 Table 1 4 Table 1 5 Table 1 6 Table 1 7 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 3 7 Table 3 8 Table 3 9 Table 4 1 Table 4 2 Table 4 3 Memory Ee EE EE 1 5 Boot Control PIns vtr a RE otis bee NERO IR ch 1 8 Commands Used for each Transport 1 9 Hardware Interrupt Table 1 13 Interrupts not used by the BIOS 1 15 Hardware Interrupt Table 1 16 Software Interrupt Table s 2205 40 20 20s E deere Booch Miwa eee res 1 19 TD List Data Structure aicn d preia ed peda aa bebe dd be REN bee 3 9 BaseAddress WORD 0x00 01 0 000 cece teeta 3 9 Port Length WORD 0x02 03 auauua uaaa aaaea 3 10 PID EP BYTE 0x04 EE 3 11 DevAdd BYTE 0x05 ieia rea hene tte teens 3 12 Control BYTE 0X06 EE 3 12 status BYTES0x07 24 a bel ole er ee le es 3 13 RetryCnt BY TE 0X08 e eee eae ate ees ta Ee 3 14 NextTDPointer WORD OXDA 0B 3 15 Standard Command Chapter 9 Requirements 4 2 Vendor Request Requirements 00 00 oo 4 2 Generic Frame 1 Send Receive Request Used by Generic Endpoint Processing 4 8 xi n vas po a es M CYPRESS List of Tables Chapter1 BIOS Interface 1 1 Introduction 1 1 1 Overview Cypress Semiconductor off
52. NS 7 1 13 1 General OuiliNS uc E E E E 7 2 F325ASS INIT Kl EES 7 2 IS ASIA EE 7 2 Table of Contents CYPRESS Table of Contents 7 3 4 3 HS S DONE ISR iniadaianda add Sigi 7 2 7 3 5 HSS SEND BLOCK Routine 7 3 7 3 6 HSS RECEIVE BLOCK Routine nennen nennen nnn ens 7 3 7 3 7 HSS TRANSFER DIAGRAMS FOR LCD 7 4 TILA COMM RESET Vidi AS Susi dta db ERR Rcs E td E Ede aes 7 4 7 3 7 2 COMM_JUMP2CODE via Hp 7 5 7 3 7 3 COMM CALL CODE via HSS ssessssssssseseneeee nennen nennen nnne nen 7 6 7 3 7 4 COMM WRITE CTRL REG via Hp 7 7 7 3 7 5 COMM READ CTRL REG via HSS sse 7 8 7 3 7 6 COMM WRITE MEM via Hop 7 9 7 3 7 7 COMM READ MEM via HSS ssssssssseeeneeen nennen 7 10 7 3 7 8 COMM WRITE XMEM via HSS ssssssssseeeneen eee nnns 7 11 7 3 7 9 COMM READ XMEM via HSS sssssssssseeeeeen ene nennen nennen 7 12 7 3 7 10 COMM EXEC NT via Hp 7 13 7 3 7 11 COMM CONFIG via Hp 7 14 Appendix A Definitions ote ertet ie le le be e ee eig Appendix 1 Appendix B KE Appendix 3 Appendix C REVISION HIStory 1 tice stele A NEEN eege Appendix 5 Table of Contents vii dy V Uy Z CYPRESS viii Table of Contents List of Figures Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 2 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Fig
53. OTG part 3 1 2 Stand alone Mode In the stand alone mode the EZ Host or EZ OTG device works independently The TD list is built and submitted to BIOS in the same way as in co processor mode After completion of the TD list HCD is informed by semaphore 3 2 Functional Requirements The EZ Host EZ OTG USB Host performs the following Generates USB Reset e Detects the device speed Full or Low Speed Generates the SOF EOP Transfers the TD list over USB Performs error handling e Performs scheduling 3 3 USB Host BIOS Overview 3 3 1 Block Diagram The USB Host BIOS includes three software interrupts HUSB SIE INIT INT HUSB SIE2 INIT INT HUSB RESET INT Page 3 2 BIOS User s Manual v1 1 Their functions are illustrated in Figure 3 2 HCD EZ Host OTG USB Host BIOS Device TD List USB Device Figure 3 2 Block Diagram of USB Host BIOS 3 3 1 1 HUSB_SIEx_INIT_INT HUSB_SIEx_INIT_INT is used to execute the TD list It has the following functions Set SIE as Host and perform initialize The HUSB_SIEx_INIT_INT sets SIEx as a host and does initialization Check for pending TD list At the beginning of every frame it checks to see if there is a TD list waiting for transfer If true it begins the TD list transfer Schedule and perform transfer It transfers all TD data over USB Update status and error handling It updates the TD status after every transaction It als
54. PI hardware transfer length only support up to 1024 byte i e 512 word Page 1 12 BIOS User s Manual v1 1 1 5 Hardware Interrupts There are 48 hardware interrupt vectors for the EZ Host EZ OTG devices The only real difference between a hardware interrupt and a software interrupt is the fact that a hardware interrupt is trig gered by an event in hardware This may seem obvious but it is important to understand that hard ware interrupts can be called with the INT instruction the same way as software interrupts are and any reserved or free hardware interrupts can be used as a software interrupt since there is no hardware stimulus associated with it The EZ Host EZ OTG hardware interrupt vectors are listed in Table 1 4 Table 1 4 Hardware Interrupt Table eee Re eer Interrupt Type Note 0 0x00 Timero0 free for developer 2 1 0x02 Timer1 free for developer 2 2 0x04 GP IRQO free for developer 2 3 0x06 GP IRQ1 free for developer 2 4 0x08 UART Tx reserved for debugger 1 5 Ox0A UART Rx reserved for debugger 1 6 0x0C HSS DMA Done reserved for LCP 1 7 OxOE HSS Rx Full reserved for LCP 1 8 0x10 IDE DMA Done free for developer 3 9 0x12 Reserved for future hardware 4 10 0x14 HPI Mailbox RX Empty reserved for LCP 1 11 0x16 HPI Mailbox TX Full reserved for LCP 1 12 0x18 SPI Tx reserved for LCP 1 13 Ox1A SPI Rx reserved for LCP 1 14 0x1C SPI DMA Done reserved for LCP 1 15 0x1E OTG ID VBUS Valid free for developer
55. Processing Vendor Command Processing Load Program Generic Endpoint Support on an endpoint by endpoint basis Generic IN endpoint support Generic OUT Endpoint Support USB Initialization Finish Control Transfer tions can call This enables a user to modify particular behavior without having to rewrite entire functionality This is especially important for endpoint O control transfer processing Page 4 2 BIOS User s Manual v1 1 The chart below graphically depicts the dependencies of override able functionality for control transfer processing Small device and configuration descriptor changes shall not require the asso ciated processing routines to be overridden Any shaded block below may be overridden When a block is overridden it must also provide any behavior that is in a un shaded block below it and the override of shaded blocks below it are optional A special case is generic Endpoint processing SIE1 Endpoint0 ISR SIE2 Endpoint0 ISR Control Transfer State Management Chapter 9 Vendor Decoder GE Class eek Configuration Loader Poke Other Processing Vendor Arena Generic Slave Endpoint Support Figure 4 1 Override ability Dependency Stack The generic endpoint processing may be overridden on an endpoint by endpoint basis The generic endpoint processing framework is also entirely override able The framework itself has one special hook to differentiate between con
56. READ CTRL REG via Placenta uite 5 8 5 3 7 6 COMM READ XMEM via HPI EES 5 9 5 3 7 7 COMM WRITE KENE 5 10 5 3 7 8 COMM EXEG INT Via HP ak ee eee cane 5 11 Chapter 6 SPI Transport Module Firmware MI iterom 6 1 6 1 1 OVE EW EE 6 1 AS AO 6 1 6 2 Functional Requirements noni A ep Hie ee eed 6 1 6 3 Detailed Desig aistiin dba EE 6 1 6 3 1 General Outlirie ree ere er ere e rere depo e obe e ey eg 6 2 6 3 2 SPI INFT Ro tine iier e tec eee tee Eee Eege sto eig acido Ee 6 2 6 3 3 SP Ra ISR zio ded ede deed eee de aos 6 2 6 3 4 SPI Done LEE 6 2 6 3 5 SPI Send Blk Routine niei Ere ato 6 3 6 3 6 Zb Ree Blk Routine isni 2 91 2 1 Bc aed de ee eee ee 6 3 6 3 7 SPI polling the Status 2 2 irit endete eee Ier deret dnte Ae deer dete 6 3 6 3 8 SPI TRANSFER DIAGRAMS FOR LCD 6 4 6 3 8 1 COMM RESET via SPI eed nee sec reet eee eed 6 4 6 3 8 2 COMM JUMP2CODE via Pl 6 5 6 3 8 3 COMM CALL CODE via SPI emere 6 6 6 3 8 4 COMM WRITE CTRL REG via GPL 6 7 6 3 8 5 COMM READ CTRL REG via GP 6 8 6 3 8 6 COMM WRITE MEM via Pl 6 9 6 3 8 7 COMM READ MEM via GP 6 10 6 3 8 8 COMM WRITE XMEM via SPI eee nennen 6 11 6 3 8 9 COMM READ XMEM via GP 6 12 6 3 8 10 COMM EXEC INT via GP 6 13 Chapter 7 HSS Transport Module vi 121 IntrodUCllohi e e ederet eR REM ees 7 1 peo a hs bec Secon hh oo ong 7 1 EI tte EEN 7 1 7 2 Functional RequireMents cuicos did e 7 1 13 Detailed Desigr reete ee ED EE
57. RO 0 BIOS will try to pull down both Data and Data and it will check if either Data or Data is still high it will return RO with non zero value to indicate the ERROR 1 7 3 4 1 Software Interface Entry RO VBUS pulse time in milliseconds must be greater than zero and not more than 30 ms R1 0 full speed 1 low speed Registers Usage None Return RO 0 Success else ERROR VBUS and D D will turn off 1 7 3 5 Interrupt 86 REMOTE_WAKEUP_INT This interrupt can be used to do the remote wake up When calling this interrupt it will force the K State for 10 milliseconds in the USB bus 1 7 3 5 1 Software Interface Entry RO sie_num 0 SIE1 else SIE2 Registers Usage None Return RO 0 Success else ERROR 1 7 4 USB Host Interrupt Functions The following functions are dedicated for the USB Host design HUSB_SIE1_INIT_INT HUSB SIE2 INIT INT e HUSB RESET INT Page 1 28 BIOS User s Manual v1 1 1 7 4 1 Interrupt 114 115 HUSB_SIE1_INIT_INT HUSB_SIE2_INIT_INT HUSB SIEx INIT INT is used to execute the TD list Refer to Chapter 3 for a detailed discussion on these interrupts In co processor mode these interrupts must be called via the LCP commands In stand alone mode the BIOS will call the HUSB SIE1 INIT INT if the OTG ID GPIO29 pin is low The BIOS will set the SIE2 as the full speed peripheral 1 7 4 1 1 Software Interface Entry None Registers Usage None Return None
58. S SIE2 Endpoint 1 Interrupt reserved for BIOS SIE2 Endpoint 2 Interrupt reserved for BIOS SIE2 Endpoint 3 Interrupt reserved for BIOS SIE2 Endpoint 4 Interrupt reserved for BIOS SIE2 Endpoint 5 Interrupt reserved for BIOS SIE2 Endpoint 6 Interrupt reserved for BIOS SIE2 Endpoint 7 Interrupt reserved for BIOS we ee rma ma Ha ma mae Ha ee HS HS YH YH mH Note A sch a ee S a S sch 1 sch sch 1 sch 1 sch 1 sch 1 sch 1 Jl Pl o o Cc 1 These hardware interrupt vectors are reserved for internal BIOS usage Users should not attempt to overwrite these functions PON These hardware interrupt vectors are not initialized These hardware interrupt vectors are initialized with empty ISR subroutine These hardware interrupt vectors are reserved for future hardware expansion Users should not use these vectors All these vector interrupts are read write accessible Users can overwrite these default interrupt vectors by replacing their interrupt service subroutine Example 1 Modify Timer 1 Interrupt Vec tor demonstrates how you can replace the hardware interrupt Example 1 Modify Timer 1 Interrupt Vector Initialize mov 0x0002 Timerl isr New Timerl ISR Page 1 14 Or 0xc00e 2 ret enable timerl interrupt BIOS User s Manual v1 1 Timerl isr push 0xc000 mov 0xc012 pop 0xc000 sti ret push the flags register 30000 reload timer 1 Restore flags enable interrupts ret
59. S EE 4 4 4 3 1 EndointO Processing Outline oooonnnnccnnnnnnicccccnncncnonccnnnncnnnnnncnnnnnnnnncnnnnnnnn nennen 4 4 ALS Ast Behavior e iaa 4 4 4 3 1 2 ee 4 5 4 3 2 Generic Endpoint Support eicere rie Id o EE e tue cete ed eed ecd ge e 4 6 4 3 2 1 Behavi r 4 eire te A RAE Eon Cep rete nh 4 6 GW Ee pA e eee Rete era etr ate eec ot quee de RH OU ce eds 4 7 4 3 2 3 Data Structures x necne eB ERREUR NIU Ln unu 4 8 4324 Code Structure eite Ee a A cues 4 9 4 3 3 Reasons for Important Choices 0000 02 cccececeeecee cece ee ceeeeaeeeeeeeaeeeeeesesaeceeeeseaeaaeeeeeeeeaaees 4 11 Chapter 5 HPI Transport Module 5A INTO UCION D DA Be UE m Accor ita 5 2 Functional Requirements 5 3 Detailed Design nire EE ect ened ope ree aeo Io Doe lv ENEE 5 3 1 HR General Description A A Tenere 5 1 5 3 2 HPI Signal Description eicere ort cerit de oi detener nente genie te 5 2 5 3 3 Host DMA to from EZ Host EZ OTG Memory via HPI Port 5 3 5 3 4 HPEINIT Routine error eee iecit eae 5 4 5 3 5 Host to EZ Host EZ OTG MailBox Message seem 5 4 5 3 6 EZ Host EZ OTG to Host MailBox Message em 5 4 5 3 7 HPI TRANSFER DIAGRAMS FOR LC 5 5 Table of Contents v F CYPRESS Table of Contents 5 3 7 4 COMM RESET via MP x tee rati tenant espe lieta 5 5 5 3 7 2 COMM JUMP2ZCODE via HDI condire Aen t ee t ecce ep 5 5 5 3 7 3 COMM_CALL_CODE Ee EE 5 6 5 3 7 4 COMM WRITE CTRL REG via API ater eee ete 5 7 5 3 7 5 COMM
60. WORD wLength WORD wCallBack USB CMD USB CMD ep2 ctl short R0 R1 R8 define ep2 ctl ptr 0x1000 define image ptr 0x1008 define image size 320 define mbx_msg2 0x148 RO 0 R1 2 R8 ep2 ctl ptr ep2 ctl wNextLink 0 ep2 ctl wAddress image ptr ep2 ctl wLength image size ep2 ctl wCallBack 0 lication note HPI Buff Write WORD amp ep2 ctl 4 Store buffer into internal RAM HPI Exec int COMM EXEC INT SUSB2 SEND INT RO R1 R8 Note The BIOS also sets the mbx_msg2 for both stand alone and co processor modes A read of mbx msg 2 can be done with the following code short mbx copied if mbx copied HPI Read mbx msg2 0 HPI Write mbx_msg2 0 allow BIOS to update the new message If there only one interrupt i e endpoint2 then the value of the mbx copied will be equal to 0x0004 Chapter 1 BIOS Interface Page 1 43 BIOS User s Manual 1 7 5 9 Interrupt 81 97 SUSB1_RECEIVE_INT SUSB2_RECEIVE_INT Receive data from USB endpoint x The support these interrupts provide simplifies all transfers across all endpoints i e endpointO 7 by providing a uniform interface and behavior An application prepares a buffer and a control header block referencing the buffer The control header block contains a pointer to the buffer the buffer s length a null next control header block pointer and a call back routine pointer These interrupts are used to receive
61. Z Host EZ OTG This is done while the EZ Host EZ OTG part transfers the TD list for the next frame This is possible because of the ping pong buffers HUSB SIEx pCurrentTDPtr EZ Host OTG BIOS HUSB TDListDone HUSB SIEx pTDListDone Sem Figure 3 3 Flow Chart of USB Transfer Chapter 3 USB Host BIOS Specifications Page 3 5 BIOS User s Manual 3 4 Software Interface Between HCD and BIOS EZ Host OTG BIOS Data Buffer SIE Ping Pong SOF Update Status Pong Done E Updale Status Next TD Transfer Done y Update Status HUSB TDListDone e SIEx_pTDLisiDone_Sem TD_Check pong TD_Load Pi ES Load Ping SOF e Done 7 Update Status Next TD Transfer Update Status Next TD Transfer Done UpdatelStatus HUSB_TDListD de siex_pTDList TD_Check EN E TD Load Pong USE SOF Done ID Next TD Update Status Tender Done Update Status Next TD Transfer l Done Update Status HUSB_TDListD MED SIEx pTDListDone Sem l TD Check Ping X TD_Load Pong SOF Figure 3 4 Time Domain Behavior Figure 3 4 shows the time domain behavior for both EZ Host EZ OTG BIOS and HCD Page 3 6 BIOS User s Manual v1 1 The HCD is responsible for cooperating with the EZ Host EZ OTG BIOS to transfer data to the USB bus It performs th
62. apter 2 Link Control Protocol Firmware 2 1 Introduction 2 1 1 Overview The BIOS allocates an idle task for the Link Control Protocol which is called Icp_idle This LCP idle task handles all the LCP commands and also maintains support for the message interrupt to the external microprocessor VA Note The BIOS does not support queuing of LCP commands Only one LCP command may be executed at a time When EZ Host or EZ OTG is used in co processor mode it is connected to an external micropro cessor or an ASIC with an embedded processor core There is potential for some confusion in ter minology because in this case the external processor is the Host or Master and the EZ host or EZ OTG device is the Peripheral or Slave Using the terms Host and Peripheral to describe these interactions can be confusing because of Host and Peripheral USB Communication Terms To describe the external microprocessor the term System CPU or System Processor will be used since this external microprocessor is generally at the center of the overall system PORT commands are common to all Host Control Ports HPI HSS SPI for communication with the system CPU The port commands and associated responses form the basis of the Link Control Protocol LCP The LCP allows the system CPU full control of the EZ Host or EZ OTG chip 2 1 2 Scope The LCP is primarily used in co processor mode embedded host applications Stand a
63. arked as INACTIVE ActiveFlag 0 with Status 0 The HCD must interpret that these successive TDs are actually not successful So when HCD finds a TD with a serious error it should halt this PIPE except the short packet underflow it does not need to check the successive TDs For the short packet underflow the BIOS will halt the PIPE in that frame too and it will let HCD make the decision The HCD will treat short packets as either end of unit of data no error or serious error per the client Retry able Error Error CRC error or others Time Out For these retry errors BIOS will retry 3 times NAK For NAK the BIOS will retry until the end of the current frame When checking TD status HCD should handle the error in the following way ActiveFlag Status 0 Status 0 0 StatuszO 1 Status 0 1 StatuszO Page 3 16 HCD Action ISO INT N A N A Handle Error Handle Error HCD Action CTL BULK Success TD done except the halted pipe see Serious Error Serious Error except the short packet This TD hasn t been executed Continue to Retry BIOS User s Manual v1 1 Do TD Transfer ActiveFlag 1 update packte status and residue to TD Let HCD handle Yes error ActiveFlag 0 Yes 4 Status 0 ActiveFlag 0 Yes Stop all TD relate to same EP DEV Port A Serious error Yes Yes RetryCnt
64. ass but it only illustrates how to receive data from the host via these interrupts mbx msgi equ 0x144 mailbox message address Stand alone sample code usbl epO rec data mov epo next link 0 mov epO address data buff data buffer pointer mov epo length 120 Size of the image line mov epO call back epO done call back for endpointO mov r8 ep0 next link r8 pointer to linker mov r1 O rl 0 setup endpoint 0 int SUSB1 RECEIVE INT call interrupt ret ep done user s code here int SUSB1 FINISH INT call STATUS phrase ret data data buff dup 120 ep0 next link dw 0 ep0 address dw 0 ep0_ length dw 0 ep0 call back dw 0 Note In endpointO the STATUS phase is required for completion of DevicelOCTL from the host BIOS will check the epO call back If the pointer 0 BIOS will handle the STATUS For endpoints 1 7 users should provide a call back The BIOS also sets the mbx msgh1 for both stand alone and co processor modes To read the mbx_msg1 value the following code can be utilized short mbx copied if mbx_msgl 0 mbx copied mbx msgl copy the mailbox messagel mbx msgl 0 allow BIOS to update the new message Page 1 46 BIOS User s Manual v1 1 Example 9 Co processor mode receiving data over SIE1 port A USB endpoint 3 Co processor sample code detail of these code will be provided in the A typedef struct WORD wNextLink WORD wAddress WORD wLength WORD
65. be used to describe the code and data structure 4 3 1 Endoint0 Processing Outline 4 3 1 1 Behavior The USB slave architecture consists of endpoint 0 support and generic endpoint support for two SIEs Default Control endpoint processing is the processing of USB Control Transfers usually via endpoint 0 Chapter 9 support class commands and vendor specific commands are types of con trol transfers Control transfers always have at least two stages setup and status Control trans fers that require the transfer of more data to the slave or any data back to the host must have a third data stage The status stage is very similar to a data stage and can be considered a data less data stage The following state diagram generally demonstrates how a control transfers han dler should be behave Setup Arrived Setup Stage Ch 9 Vendor tools OUT zero length Setup Command OUT more data Status IN OUT Zero IN more data to to transfer Length transfer Waiting For OUT Waiting For IN Data Status Stage Figure 4 2 Control Transfer Handler State Diagram Page 4 4 BIOS User s Manual v1 1 4 3 1 2 Architecture Size and modularity are the two major considerations for this project An architecture that mini mizes size and maintains modularity and produces the desired behavior meets our design goals Code Size can be minimized by sharing processing routines between SIEs and maintaining a structure
66. because HSS is a single channel communication link which relies totally on software for access to the hardware Where the HPI interface has a direct memory access channel for memory reads and writes the HSS must access memory via LCP commands Chapter 7 HSS Transport Module Page 7 1 BIOS User s Manual 7 3 1 General Outline The HSS transport consists of the following functions HSS Init Routine e HSS_RX_ISR e HSS_Done_ISR e HSS SEND BLOCK Routine e HSS RECEIVE BLOCK Routine 7 3 2 HSS INIT Routine The HSS INIT routine is called to enable LCP messages to be processed via the HSS transport The INIT routine does the following Enables HSS I F via EZ Host EZ OTG Control Registers Sets the Baud Rate e Setup HSS Port Commands table Setup Packet BYTE Block mode Enables HSS Interrupts 7 3 3 HSS RX ISR The HSS_RX_ISR is triggered when the External CPU writes an 8 byte command block to the HSS interface The ISR gets the 16 bit port command and the six bytes that follow and places them in memory The extra six bytes contain parameters for the given LCP command For exam ple if the command is COMM_JUMP2CODE then the data after the command contains the address to jump to This is described in the HSS transfer diagrams 7 3 4 HSS_DONE_ISR The HSS_DONE_ISR is triggers when either a block transmit or block receive has completed The ISR will set the semaphore that signal the LCP idle task to indicate the completio
67. cation prepare buffer prepare frame Send Receive Int setup transaction processor configure ep regs for data subset Data Transferred Ve OK Interrupt La calls le configure ep regs for data subset Data E Transferred data pointers Interrupt are T p walked 7 calls 5 along configure ep lregs for data subset ata data 9 preg Transferred buffer Interrupt calls Callback Application aware of transfercompletion Figure 4 4 Generic Endpoint Support Sequence Diagram 4 3 2 2 Architecture Generic endpoint support will consist of a single set of routines that will operate on the endpoints Each endpoint configured to utilize generic endpoint support will have configuration and state information that will be passed to the support entry routine from the endpoint ISR This architecture will minimize code size maintain modularity and produce the desired behavior The architecture in Figure 4 5 uses rectangles to describe data structures and blocks with rounded corners to depict routines Lightly shaded routines are hardware interrupts and darker shaded rou tines are software interrupts The use of generic endpoint support for a particular endpoint can be overridden simply by providing a new ISR for that endpoint The Generic Support can be used for vendor specific control transfers but the call back must eventually call the Finish Transfer soft ware interrupt to signal
68. ce routines The following tables detail the functionality required by the two command processing categories Chapter 4 Slave Support Module Firmware Page 4 1 BIOS User s Manual Table 4 1 Standard Command Chapter 9 Requirements Standard Request Description CLEAR_FEATURE SET_FEATURE Enable and disable a device s ability to remotely wakeup and to stall and unstall an endpoint GET_CONFIGURATION SET_CONFIGURATION Set Get Configuration GET_DESCRIPTOR Provide DEVICE and CONFIGURATION descriptors GET_INTERFACE Specify or query for the current interface GET_STATUS Obtain DEVICE INTERFACE or ENDPOINT status SET_ADDRESS Set the USB address Table 4 2 Vendor Request Requirements Vendor Request Description LOAD_PROGRAM Load new binary either into RAM or Serial EEPROM PEEK Return specific memory contents POKE Change Specific memory locations There must also be a programmatic means of completely or just partially overriding the above functionality in both categories Behavior override ability will have the following granularity 2o0 5o00750 x e l m n Override ability equates to software interrupts effectively routines that the BIOS and user applica Endpoint O processing Chapter 9 Standard Processing Configuration Parsing Device Descriptor Change Configuration Descriptor Change String Descriptor Change Class Command
69. cessor Interface HPI High Speed Serial HSS or Serial Peripheral Interface SPI The BIOS uses the boot control pins to determine the default port This port is used to load code and data and is monitored for Link Control Protocol LCP commands GPIO pins 30 and 31 are used as the boot control pins The possible configurations are described below Table 1 2 Boot Control Pins GPIO 30 GPIO 31 Mode Boot Port and Baud 0 0 co processor HPI 0 1 co processor HSS GPIO mode Baud 115 2K 1 0 co processor SPI GPIO mode 1 1 stand alone EEPROM Note n co processor mode all USB ports are disabled at power up and must be turned on the external processor using LCP commands For example in peripheral mode the chip will not respond to any USB commands from the host until the ports have been enabled In stand alone mode the USB PortC always goes into full speed peripheral mode which is dedicated for the debugger usage The USB PortA goes into peripheral mode if GPIO29 is high and goes into host mode when GPIO29 is low n stand alone mode users can use the serial EEPROM to over ride the default mode for both USB PortA and USB PortC In this mode BIOS will use SCAN INT so user applica tions can be loaded into RAM from the EEPROM Page 1 8 BIOS User s Manual v1 1 1 4 Link Control Protocol LCP The link control protocol allows an external processor to have full access and control over the EZ Host EZ OTG devices The boot
70. command handles Data Transfers Data is transferred from HSS SPI to memory pointed to by COMM_LAST_DATA which should be located in the internal memory e Memory Copy Memory is copied from COMM_LAST_DATA to COMM_MEM_ADDR e COMM MEM ADDR can be any where from 0x0000 to OxFFFF The purpose of this command is to allow data transfer between HPI SPI and HSS hardware to external memory The sequence of data will be Data will transfer from HPI SPI and HSS hardware to the internal RAM that pointed by the COMM LAST DATA and then the BIOS will copy from the internal memory COMM LAST DATA to external memory that pointed by the COMM MEM ADDR Note COMM MEM LEN is the number of words to transfer and should be greater than zero COMM CONFIG Action Configures COMM Transport Features Data Used COMM BAUD RATE for HSS ONLY Response COMM ACK This command will change the default baud rate for the HSS For HPI SPI this command will return ACK and do nothing Note The external host processor is in full control of the interface as a master The Host must allot time to the BIOS in between sending LCP commands The Host should wait at least 30 microseconds between sending a new command packet When changing the BAUD rate com mand via the COMM CONFIG the Host must wait at least 100 microsecond before sending a new command with the new baud rate Page 2 8 BIOS User s Manual v1 1 FO PRESS j Chapter 3 USB Host BIOS Specificat
71. control determines which interface HPI HSS SPI will be enabled for receiving LCP commands on power up The LCP commands are common for all interfaces but the communication protocol varies slightly between them due to capability differences of the inter faces This section describes the methods used to access the EZ Host EZ OTG devices via each of the three interfaces The BIOS does not support queuing of LCP commands Only one LCP command may be exe cuted at one time The following table shows which LCP commands are available and useful for each port Table 1 3 Commands Used for each Transport HPI HSS SPI Eomae Transport Transport Transport COMM RESET Yes Yes Yes COMM JUMP2CODE Yes Yes Yes COMM CALL CODE Yes Yes Yes COMM EXEC INT Yes Yes Yes COMM READ CTRL REG Yes Yes Yes COMM WRITE CTRL REG Yes Yes Yes COMM READ MEM Yes Yes Yes COMM WRITE MEM Yes Yes Yes COMM READ XMEM Yes Yes Yes COMM WRITE XMEM Yes Yes Yes COMM CONFIG Yes Yes Yes Note BIOS returns COMM ACK ONLY 1 4 1 LCP Overview for Host Processor Interface HPI Refer to Chapter 5 HPI Transport Module for a complete discussion on this topic HPI is a dual channel interface By default the BIOS uses the HPI direct memory access for mem ory read write of data and the mailbox for LCP commands and responses LCP commands are always sent in a 16 bit word and a 16 bit response is expected A sequence diagram of each LCP command is given in Chapter 5 Note Un
72. criptor and String Descriptor Page 1 36 BIOS User s Manual v1 1 1 7 5 5 Interrupt 89 105 SUSB1_FINISH_INT SUSB2_FINISH_INT These interrupts are to be called by the standard vendor and class command handlers to enter the status phase and complete a control transfer 1 7 5 5 1 Software Interface Entry None Registers Usage R9 Return R9 DEVx EPO CTL REG either 0x200 or 0x280 Note These interrupts should only be used for the EndpointO 1 7 5 5 2 Example See Example 10 Intercept SUSB1 VENDOR INT vector 1 7 5 6 Interrupt 82 98 SUSB1 STALL INT SUSB2 STALL INT Each of these interrupt vectors will configure its associated SIE to stall the next transaction on its default endpoint 0 It is important to note that the setup phase of a control is always acknowl edged even if the SIE is configured to stall 1 7 5 6 1 Software Interface Entry None Registers Usage R9 Return R9 points to either 0x200 or 0x280 DEVx EPO CTL REG Na Note These interrupts should only be used for the EndpointO 1 7 5 7 Interrupt 83 99 SUSB1 STANDARD INT SUSB2 STANDARD INT These Interrupts implement the USB standard interface based on Chapter 9 of the USB Specifica tion version 2 0 These interrupts will be called whenever bit 6 and bit 5 of a bmRequest byte are cleared bmRequest amp 0x60 0 You can overwrite these interrupts for any extension of the application These interrupts will be called inside the inter
73. db 0 interval ep2 db 7 len db 5 type endpoint db 0x82 type number Host uses ReadFile db 2 Bulk Chapter 1 BIOS Interface Page 1 35 BIOS User s Manual dw 64 packet size db 0 interval support for OTG otg db 3 len 3 db 9 type OTG db 3 HNP SRP supported end all 1 7 5 3 2 Example See Example 4 Overwrite SIE1 SIE2 Device Descriptor Configuration Descriptor and String Descriptor 1 7 5 4 Interrupt 92 108 SUSB1 STRING DESCRIPTOR VEC SUSB2 STRING DESCRIPTOR VEC These interrupt locations may contain the address of a string descriptor request refer to USB Specification version 2 0 for details The location defaults to Cypress String Descriptor A pointer to a routine to service the string descriptor request may be written here if necessary Note In stand alone mode these descriptors can be changed via the serial EEPROM or the exter nal ROM Note In co processor mode these descriptors can be changed via LCP Note The address of the string descriptor should be word aligned 1 7 5 4 1 Software Interface The default Cypress String Descriptor is as follows String Require the string must be align 2 string desc db STRO LEN db 3 dw 0x409 english language id STRO LEN equ string desc stri db STR1_LEN db 3 dw CYPRESS EZ OTG Cypress EZ OTG STR1 LEN equ strl 1 7 5 4 2 Example See Example 4 Overwrite SIE1 SIE2 Device Descriptor Configuration Des
74. dpoint ISR Entry point Clears Int jump Sets EP e 1 per endpoint SUSB _EP_Hub Loads SIE V and NV Pointers and common cleanup E call Control Handler Call Processes Device Generic Endpoint Requests possibly Processing queing transactions Loads EP data to complete control return and completes transfers data transactions on behalf of the calls endpoint Chapter 9 Standard Command Processing Vendor Command Processing Class Command Processing Scan Processing Turns over transaction completion to scan idle routine Figure 4 6 Endpoint Processing Code Flow Page 4 10 BIOS User s Manual v1 1 Device ISRs for each SIE include the SUSB _Reset_Isr SUSB _SOF_Isr and the Timer1 Isr The reset ISR is used to re initialize the state registers and control data of the SUSB device The SUSB SOF _Isr is used with the Timer1 Isr to implement suspend and wake up functionality 4 3 3 Reasons for Important Choices Duplication Software Interrupts Just prior to implementation it was decided that each SIE should have its own set of software interrupts for maximizing BIOG code saving Generic Endpoint Support in BIOS The generic endpoint support is in the BIOS mainly because it does not consume a lot of space and facilitates slave USB utilization for applications and mod ules Modules and applications can then be more consistent sma
75. e USB_RESET This interrupt will call the SUSB2_INIT_INT and will post the message to the HPI mailbox register 0x148 with value 0x100 29 SIE2 Peripheral SOF ISR services for every 1ms SOF detect from USB Host After second SOF detection it will send a message to HPI mailbox register 0x148 with value 0x200 After detecting seven consecutive missing SOFs it will set the value 0x800 to the HPI mailbox register 0x148 32 SIE1 EndpointO ISR services USB full low speed enumeration in portA which defined by the SUSB INIT INT It handles retry when detect any ERROR in the USB bus It also supports RedHat debugger QTOOL and services the SUSB1 SEND INT SUSB1 RECEIVE INT It will set the bitO of the HPI mailbox register 0x144 for every SUSB1 SEND INT 32 39 SIE1 Endpoint 1 7 Interrupt ISR This interrupt supports the SUSB1 SEND INT and SUSB1 RECEIVE INT It handles retry when it detects an ERROR in the USB BUS After the transfer of data that defines this interface is complete it will set bits 1 7 in the HPI mailbox register 0x144 40 SIE2 EndpointO ISR services USB full low speed enumeration in portA which defined by the SUSB INIT INT It handles retry when detect any ERROR in the USB bus It also supports the Red Hat debugger and services the SUSB2 SEND INT SUSB2 RECEIVE INT It will set the bitO of the HPI mailbox register 0x148 for every SUSB2 SEND INT 41 47 SIE2 Endpoint 1 7 Interrupt ISR This interrupt supports the SUSB2 SEND
76. e COMM ACK 15 8 Figure 7 1 COMM RESET via HSS Page 7 4 BIOS User s Manual v1 1 7 3 7 2 COMM_JUMP2CODE via HSS COMM_JUMP2CODE 7 0 COMM_JUMP2CODE 15 8 COMM CODE ADDR 7 0 Send 8 Byte COMM copg ADDR 15 8 CMD Packe XXh XXh XXh XXh Wait for 2 Bytes of Jump After SE Response comm_ACK 7 0 E onse COMM ACK 15 8 Response Resp N Figure 7 2 COMM JUMP2CODE via HSS VA Notes The code should exist in the memory space that COMM_CODE_ADDR will point to If the code jumped to does not return then the ACK will not be sent Chapter 7 HSS Transport Module Page 7 5 BIOS User s Manual 7 3 7 3 COMM_CALL_CODE via HSS COMM CALL cope 7 0 COMM CALL one ns n M CODE ADDR 7 0 Response COMM ACK 15 8 Figure 7 3 COMM_CALL_CODE via HSS Send 8 Byte CMD Packet Wait for 2 Bytes of Response Call Code Then Send Response VA Notes The code should exist in the memory space that COMM_CODE_ADDR will point to If the code jumped to does not return then the ACK will not be sent Page 7 6 BIOS User s Manual v1 1 7 3 7 4 COMM_WRITE_CTRL_REG via HSS Send 8 Byte CMD Packet Wait for 2 Bytes of Response Figure 7 4 COMM_WRITE_CTRL_REG via HSS Chapter 7 HSS Transport Module Page 7 7 BIOS User s Manual 7 3 7 5 COMM_READ_CTRL_REG via HSS C OMM READ CTRL REG 7 0 C OMM READ CTRL REG 15 8 COMM CTRL REG A
77. e is another way to support software debugging the USB port can also be used by the debugger Note The BIOS will setup the default baud rate for the UART at 28 800 baud Other parameters are 1 stop bit 8 data bits no parity 1 7 11 1 1 Software Interface Entry RO Bits 3 0 0 for read 1 for write 2 for read control 3 for write control For write control only RO 3 0 3 Bits 7 4 baud rate of RO R2 For write only RO 3 0 1 Bits 7 0 Byte to transmit Registers Usage none Return Read Operations R0 3 0 20 RO Bits 7 0 contain input data Bit 15 1 if error has occurred Write Operations RO 3 0 1 RO Bit 15 1 if error has occurred Read Control R0 3 0 22 RO Bits 7 4 contain current baud rate R1 Points to the location to call when receive buffer goes not empty R2 Points to the receive buffer memory structure defined as follows dw length of buffer 1 must be 27 1 dw input pointer dw output pointer db data 0 data n Chapter 1 BIOS Interface Page 1 69 BIOS User s Manual R3 Points to the location to call when the transmit buffer becomes empty R4 Points to the transmit buffer memory structure as follows dw length of buffer 1 must be 27 1 dw input pointer dw output pointer db data0 datan Write Control R0 3 0 23 All of the registers returned in Read Control can be set using the same registers as inputs Note UART buffers are predefined by the BIOS
78. e of Contents 1 7 4 USB Host Interrupt FUNCtIONS 20 0 c cece ee ene ee cece ee onn cnn nn narrar 1 28 1 7 4 1 Interrupt 114 115 HUSB SIE1 INIT INT HUSB SIE2 INIT INT 1 29 1 7 4 1 1 Software Interface nennen 1 29 1 7 4 4 2 ue 1 29 1 7 4 2 Interrupt 116 HUSB RESET INTE 1 29 1 7 4 2 1 Software Interface oooooccccconinoccccnnnococccccononononcnnncnnnonccnnnnannncnnccananancnnnnnns 1 30 12 4 2 2 Example ome eet e E ERE re Dele taret 1 30 1 7 5 USB Peripheral Interrupt Funchons meme 1 30 1 7 5 1 Interrupt 113 SUSB_INIT_INT enne 1 31 1 7 5 1 1 Software Interface ooooococccnnnnocccccnnococcccconcnononcnnncnononccnnnnnnnncnncnnnannnnnnnnnns 1 31 17 512 Example EE 1 31 1 7 5 2 Interrupt 90 106 SUSB1 DEVICE DESCRIPTOR VEC SUSB2 DEVICE DESCRIPTOR MEI 1 32 1 7 5 2 1 Software Interface ooooococccnnnnoccccnnnocococcconcnonononnncnononccnnnnannncnnncanannncnnnnnns 1 32 UE 1 33 1 7 5 3 Interrupt 91 107 SUSB1_CONFIGURATION_DESCRIPTOR_VEC SUSB2 CONFIGURATION DESCRIPTOR VEC eee 1 35 1 7 5 3 1 Software Interface snee a eaaa ea aae aeih 1 35 1 7 5 3 2 Exam iinan e et ate a ec P e 1 36 1 7 5 4 Interrupt 92 108 SUSB1_STRING_DESCRIPTOR_VEC SUSB2 STRING DESCRIPTOR VEC eee 1 36 1 7 5 4 1 Software Interface eene 1 36 1 7 5 4 2 Examiple EE 1 36 1 7 5 5 Interrupt 89 105 SUSB1 FINISH INT SUSB2 FINISH INT cece 1 37 1 7 5 5 1 Software Interface iiec ecce ce cce hoe egen
79. e pipe support it also uses the ControlHandler rou tine to initiate control transfer processing The diagram below details endpoint code flow Square boxes indicate interrupt vectors software and hardware as previously described Other interfaces into the code include software interrupts and the initialization routine The initial ization routine works by constructing an endpoint table out of contiguous EP _Table_Entry s and then passing a pointer to the base of this table the number of endpoints in it to the SUSB _Init routine The BIOS will then initialize the SIE and related data structures The USB Int and SUSB Reset Jr are likely callers OUT and IN transactions may be queued via the RECEIVE and SEND software interrupts for each slave SIE These calls queue the generic frames for Generic Endpoint processing arming the end points if necessary Control transfers must be initiated from within a control transfer handler i e Chapter 9 Processor Vendor Processor Class Processor A data stage may be initiated here with a call back e g SUSBx FINISH INT to handle the status phase Two stage transfers may just initiate the status phase The software interrupt table provides place holders for data descriptor pointers loader com mands over rideable calls within the BIOS class vendor Chapter 9 string desc etc and utilities SUSBx FINISH INT etc Chapter 4 Slave Support Module Firmware Page 4 9 BIOS User s Manual En
80. em Value n 15 8 Memvalven tss Figure 7 8 COMM_WRITE_XMEM via HSS Page 7 11 Chapter 7 HSS Transport Module BIOS User s Manual 7 3 7 9 COMM_READ_XMEM via HSS Send 8 Byte CMD Packet Wait for 2 Bytes of Response followed by n words of Data COMM LAST Data 7 0 COMM LAST Goran 5 8 Response U 0 Respon Mem Value 1 7 0 7 0 Mem Value D Mem Value n 15 8 Figure 7 9 COMM READ XMEM via HSS Page 7 12 BIOS User s Manual v1 1 7 3 7 10 COMM EXEC INT via HSS Full COMM_WRITE_ME to set Interrupt Data Structure COMM_WRITE_MEM of INT Data Send 8 Byte CMD Packet Response 7 0 Wait for p 2 Bytes of Response 15 8 Response Followed by RO Return 5 8 Value RO 15 8 Figure 7 10 COMM EXEC INT via HSS Chapter 7 HSS Transport Module Page 7 13 BIOS User s Manual 7 3 7 11 COMM CONFIG via HSS MM_BAUD RATE 7 0 Send 8 Byte CO COMM_CONFIG 7 9 COMM CONFIG 15 8 M CMD Packet P ATE 15 8 Wait for 2 Bytes of Response Response COMM ACK 15 8 COMM ACK 70 Send Response Then change Baud Rate Figure 7 11 COMM_CONFIG via HSS VA Note Appropriate baud rate values can be found in the EZ Host or EZ OTG Datasheets Page 7 14 BIOS User s Manual v1 1 7 CYPRESS j Appendix A Definitions Term Definition 2 wire serial 2 wire serial flash EEPROM interface interface BIOS Basic Input Outpu
81. eneaeees 1 10 1 4 2 LCP Overview for High Speed Serial HSG 1 10 1 4 3 LCP Overview for Serial Peripheral Interface PI 1 12 1 5 Hardware Interrupts cio iaa cade aden 1 13 1 5 1 BIOS Hardware Interrupt Usage cnn nc nennen nennen 1 15 1 5 1 1 Interrupts Not Used by the BIO 1 15 1 5 1 2 Interrupts Used by the BIO 1 16 1 6 Debugging Tools Support aiii ad ocu 1 18 1 Software Interrupts cio ee ee Ae E Eege 1 19 1 7 1 Interrupt 48 49 LCP Message Subroutines sse 1 21 1 7 2 Signature SCAN Gupport ccc cee ceceeceeeeceeceaeeeeeeseaaeaeeeeseaaeaeeeeseseeaeceeseseaaeeeeeeeeeeaeees 1 21 1 7 2 1 Interrupt 67 SCAN INTE 1 21 1 7 2 1 1 Software Interface ertet meinte eden 1 22 121 2 Example roe epe e erret ioci ee ipee ee totis ecole 1 23 1 7 2 2 Interrupt 79 SCAN DECODE INTE 1 24 1 7 2 2 1 Software Interface seed critica 1 24 1 7 3 OTG Interrupt FUNCTIONS eene EE 1 25 1 7 3 1 Interrupt 50 OTG STATE reini aneneen en nennen ran n nana neret 1 26 1 7 3 2 Interrupt 112 OTG STATE INTE 1 26 1 7 3 2 1 Software EE 1 26 1 7 3 3 Interrupt 88 OTG Descriptor sse 1 27 1 7 3 4 Interrupt 84 OTG SRP INTE 1 28 1 7 3 4 1 Software Interface acre rte basse ete td ves 1 28 1 7 3 5 Interrupt 86 REMOTE WAKEUP INTE 1 28 1 7 3 5 1 Software Interface eter ee t e Se der ee eed 1 28 EAS o KN r p E es Vi CYPRESS Tabl
82. equ 4 wLength equ 6 VND_VEC equ SUSB1 VENDOR INT 2 usb init mov VND VEC vendor int replace vendor int ret Vendor Specific command table vendor table dw vCPUPoke 0x41 wValue Addr wIndex Data wLength 0 dw vCPUPeek 0x42 wValue Addr wLength Cnt usb1 ep send data v bad ep done int SUSB1 FINISH INT ret process vendor commands vendor int r8 0x300 SIE1 request base pointer mov r0 b r8 bRequest cmp ro 0x42 1 if r0 index of vRamTest goto v bad jnc v bad cmp r0 0x41 if r0 lt vCPUPoke goto v bad jc v bad sub r0 0x41 get the Offset mov r10 r0 shl r10 1 index 2 jmp r10 vendor table jump to vector table entry usbl ep0 send data send count in r7 of data pointed to by r8 usbl epO send data mov epo link 0 mov epO call epO done mov epo loc image line image buffer pointer mov epO len r7 Size of the image line mov r8 ep0 link r8 pointer to linker mov r1 0 r1 0 setup endpoint 0 int SUSB1 SEND INT call interrupt ret VCPUPoke Write a Word to a specific address vCPUPoke wValue Addr wIndex Data wLength 0 Chapter 1 BIOS Interface Page 1 49 BIOS User s Manual mov r9 r8 wValue get address mov r9 r8 wIndex write data jmp ep0_done send ack VCPUPeek reading data from given address and count vCPUPeek wValue Addr wIndex 0 wLength Count usbl_ ep0 send data mov r9 r8 wValue address mov r7 r8 wLength length mov 4
83. ernal host CPU For connection to a host CPU the SPI hardware is used in Slave Mode In slave mode the external host CPU can communicate to EZ Host EZ OTG device at up to a 2Mhz clock rate 6 1 2 Scope This document provides details on the SPI support software A basic understanding of the EZ Host EZ OTG hardware and software architecture is assumed 6 2 Functional Requirements The SPI Transport exposes the Link Control Protocol via the SPI hardware interface The transport must be capable of receiving LCP commands from an external CPU and sending back responses The transport must also allow asynchronous messages to be sent to the external CPU 6 3 Detailed Design Refer to Figure 2 1 Link Control Protocol for details The SPI Transport is unique in that it is truly a slave interface and cannot transmit or receive data unless requested from the EZ Host EZ OTG device This makes for a much tighter communication protocol than that of HPI or HSS The interface is synchronous with the EZ Host part initiating every data transfer to and from the EZ Host This means that the SPI Transport must be setup and ready for a Read or Write of data of the correct length at every phase of the protocol This is Chapter 6 SPI Transport Module Firmware Page 6 1 BIOS User s Manual accomplished through a simple state machine These details make the SPI Transport the most complicated it implements 6 3 1 General Outline The SPI Transport consists o
84. ers the industry s broadest portfolio of USB solutions EZ Host CY7C67300 and EZ OTG CY7C67200 are two of Cypress s dual role host peripheral control lers Although these devices are tailored toward different applications they rely on many common core blocks As a result they share the same microprocessor the CY16 processor Embedded within the internal ROM of these devices is a Basic Input Output System BIOS that is also com mon to both devices This document describes the BIOS operation and software interrupts 1 1 2 General Notes This specification assumes that you have some knowledge of the CY16 assembly language You should read and understand the EZ Host or EZ OTG datasheet before attempting to read this doc ument All numbers described in this document are marked as decimal numbers unless prefixed Ox for hexadecimal Ob for binary and unless otherwise indicated the contents of registers RO R1 R2 and R8 may be lost Unless otherwise mentioned if a register or memory location used as a pointer is zero it is used as a NULL pointer meaning that it does not point at anything If the specific USB controller that the BIOS is running on does not have the hardware associated with a particular software interrupt the BIOS will return without effect Chapter 1 BIOS Interface Page 1 1 BIOS User s Manual 1 2 Development Utilities 1 2 1 GNU Development Tools from RedHat In order to support firmware development for
85. ess db next configuration address dw next data to write dw 0xc3b6 if more data to follow or dw 0000 if no more data Note 1 If data is code the code must be re locatable e no calls or long jumps within the code unless a fix up is done see Note 2 Note 2 A fix up is an offset to code that is assembled assuming a start point of zero This off set should then have the real starting location added to it 1 7 2 1 2 Example BIOS Sample code for copying code and data from external ROM to external RAM starting at address 0xC100 PRR RRR RRR KEK KK RK ke e he KKK KKK he ke e he ke e ke he ke e he ke RR ke e KK kc e he ke e he he ke ce he ke e he kkk kkk he ke e Scan external ROM PRR RRR kc ke kc ke ke kc ke he ke e he ke ke ec ke ke ke ke e he ke e ke he ke e he ke ke he kk che kkk he ke e he he ke e he ke e he ke e ke k ke e he k e Scan xrom mov r10 0xc100 XROM BEGIN mov r7 get next byte get next byte from external ROM int SCAN INT ret get next byte mov r0 b r10 ret In this example the user creates a file called sample1 asm which has the following header in the external ROM that mapped to address 0xC100 Chapter 1 BIOS Interface Page 1 23 BIOS User s Manual Example 2 Download code data from external ROM to internal RAM at 0x500 and jump to execute this code after finish downloading org 0xc100 IRAM equ 0x500 destination execute address inside IRAM dw 0xC3B6 dummy signature for code
86. f the following functions e SPI INIT Routine SPI RX ISR SPI DONE ISR e SPI Send Block Routine SPI Receive Block Routine 6 3 2 SPI INIT Routine The SPI INIT routine is called to enable LCP messages to be processed via the SPI transport The INIT routine does the following Enables the SPI I F via the EZ Host EZ OTG control register s entry point spi ginit for GPIO Connection Sets up INT REQ via GPIO24 for every DATA ACK NAK e Enables the SPI Interrupt enable e Sets up to receive a CMD packet from the Host 6 3 3 SPI RX ISR The SPI_RX_ISR is triggered when the External CPU writes an 8 byte 4 word command block to the SPI interface The ISR gets the 16 bit port command and the six bytes that follow and places them in memory The extra six bytes contain parameters for the given LCP command For exam ple if the command is COMM JUMP2CODE then the data after the command contains the address to jump to This is described in the SPI transfer diagrams 6 3 4 SPI Done ISR The SPI DONE ISR triggers when either a block transmit or block receive has completed Before the SPI Send Blk exits the SPI hardware must be configured for the next transfer The next Page 6 2 BIOS User s Manual v1 1 transfer will be the Host polling for the LCP response So the ISR will configure the SPI hardware to be ready for a read and points to OxFF for the read data 6 3 5 SPI_Send_BIk Routine The SPI Send Blk routine is used to se
87. guage This application is about 512 bytes that use the interrupts 126 127 for all the debugging purpose 1 7 10 Serial EEPROM support 1 7 10 1 Interrupt 64 2 wire Serial EEPROM from 256 byte to 2 KByte The BIOS uses this interrupt to access an external serial EEPROM typically an Atmel MicroChip AT24CXX 24LCXX device family Currently the BIOS allows reads and writes of 256 bytes up to 64 Kbytes i e AT24LC16B SN up to AT24C512 If more than 64K bytes of either code or initialized data must be stored in EEPROM then the user can use GPIO lines to manipulate the AO and A1 lines of additional EEPROM and call the SCAN INT with a pointer to INT 64 or INT 65 A user s program and USB vendor device configuration can be programmed and stored into the external EEPROM device On power up the code or data in the EEPROM will be downloaded into RAM The 2 wire serial EEPROM interface provides a space and cost efficient means of non vola tile data storage The BIOS uses two GPIO pins GPIO31 and GPIO30 to interface with an external serial EEPROM refer to Figure 1 3 and Figure 1 4 GPIO31 is connected to the Serial Clock Input SCL e GPIO3O0 is connected to the Serial Data SDA e Use a 5K 15K pull up resistor on the data and clock lines i e GPIO30 and GPIO31 e Pin 1 A0 pin 2 A1 pin 3 A2 pin 4 GND and pin 7 write protect are connected to ground Chapter 1 BIOS Interface Page 1 65 BIOS User s Manual VCC
88. h a a MI a al Page 1 19 BIOS User s Manual Table 1 7 Software Interrupt Table Continued Interrupt Vector Number Address Interrupt Type Notes 90 0xB4 Variable Data pointer SUSB1 Device Descriptor Default 2 4 Cypress Device Descriptor 91 OxB6 Variable Data pointer SUSB1 Configuration Descriptor 2 4 Default Cypress Configuration Descriptor 92 0xB8 Variable Data pointer SUSB1 String Descriptor Default 2 4 Cypress String Descriptor 93 OxBA Reserved for future BIOS 1 94 OxBC SUSB1 LOADER INT 1 95 OxBE SUSB1 DELTA CONFIG INT 1 96 OxCO SUSB2_SEND_INT 1 97 0xC2 SUSB2_RECEIVE_INT 1 98 0xC4 SUSB2_STALL_INT 1 99 0xC6 SUSB2 STANDARD INT 1 100 0xC8 Reserved for future BIOS 1 101 OxCA SUSB2 VENDOR INT default SUSB2 STALL INT 4 102 OxCC Reserved for future BIOS 1 103 OxCE SUSB2 CLASS INT default SUSB2 STALL INT 4 104 OxDO Reserved for future BIOS 1 105 OxD2 SUSB2 FINISH INT 1 106 OxD4 Variable Data pointer SUSB2 Device Descriptor Default 2 4 Cypress Device Descriptor 107 OxD6 Variable Data pointer SUSB2Configuration Descriptor 2 4 Default Cypress Configuration 108 OxD8 Variable Data pointer SUSB2 String Descriptor Default 2 4 Cypress String Descriptor 109 OxDA Reserved for future BIOS 1 110 OxDE SUSB2 LOADER INT 1 111 OxEO SUSB2 DELTA CONFIG INT 1 112 OxE2 Reserved for future BIOS on OTG STATE INT 1 113 OxE4 SUSB_INIT_NT 1 114 OxE6 HUSB_SIE1_INIT_INT 1 115 OxE8 HUSB_SIE2_INIT_INT 1 116 OxEA HUS
89. id main void Call User HW SW initialization here while 1 Application here Page 1 62 BIOS User s Manual v1 1 interface to c language via calling BIOS idle task IDLER_VEC equ IDLER_INT 2 _cstartup mov IDLER VEC new 71 Replace idler loop ret PRR RRR k k k k k k k k k k k k k k k KK k k KEK KK KKK New Idle loop PRR RRR KERR kc ec ke kc ke ke ke e he ke e ke ke e ke ke ke e kk kk new 71 addi r15 2 call main Call main int 73 PRR RRR RRR RRE k k k k k k k k k k k k k ke k ke k ke ke Call BIOS idle tasks pE Kk kkk kk kk kk kk k k k k k k k k k k k k k k k k k _bios_idle int PUSHALL INT push all RO R14 int 70 call BIOS tasks int POPALL INT pop all RO R14 ret void main void Call User HW SW initialization here while 1 bios idle Application here 1 7 8 3 Interrupt 72 INSERT IDLE INT This interrupt allows the user to add new idle tasks into the idle chain via the head entry task list in interrupt 70 The listing of interrupt 72 is as follows The listing of interrupt 72 Int 72 push RO push new user s idle task mov RO 70 2 move current task to RO pop 70 2 replace interrupt 70 with new user s idle task ret Chapter 1 BIOS Interface Page 1 63 BIOS User s Manual 1 7 8 3 1 Software Interface Entry RO location of interrupt handler on user s machine Registers Usage None Return RO location of p
90. interrupt on SIE1msg SIE2msg from HPISTS register bit5 6 Endpoint6 interrupt on SIE1msg SIE2msg from HPISTS register bit6 7 Endpoint7 interrupt on SIE1msg SIE2msg from HPISTS register bit7 Notes The structures and buffers given to this routine must not be modified until the data can be reused call is made Note The data in this structure will be changed This call should set up the pointers and return immediately The length of the buffer can be any size from 0x0000 32K The length must be less than or equal to the internal RAM or ROM size The BIOS will partition the data into the user s defined payload and transfer across through the USB bus The call back will be called after the length is zero or short packet For endpoint1 7 the address must point to the internal RAM or internal ROM Any exter nal memory bus will work but this is not recommended For endpointO the address can be either internal or external RAM or ROM When transferring from external RAM the BIOS will copy data from internal RAM to external RAM Chapter 1 BIOS Interface Page 1 45 BIOS User s Manual 1 7 5 9 2 Example Example 8 Receiving data from host i e OUT transaction to SIE1 port A USB endpoint 0 In response to a device request only data may be sent over endpointO during the data phase of a control transfer EndpointO requires three phases SETUP DATA and STATUS Users can employ the sample code below to replace the Vendor Command Cl
91. ion Note In stand alone mode these descriptors can be changed either via the serial EEPROM or the external ROM Note In co processor mode these descriptors can be changed via the LCP command Note The BIOS only supports one configuration so the number of configurations should be set to 1 see the example below 1 7 5 2 1 Software Interface The default Cypress Device Descriptor is as follows dev_desc db 18 length db 1 desc type dw 0x0200 USB spec 1 1 db Oxff device class db 0 device subclass db 0 protocol db 8 max packet size for endpoint 0 dw 0x4b4 Vendor ID Cypress dw 0x7200 Product ID dw 0x0000 device release number db 1 index of manufacture string db 1 index of product string db 1 index of serial number string db 1 number of configurations Page 1 32 BIOS User s Manual v1 1 1 7 5 2 2 Example Example 4 Overwrite SIE1 SIE2 Device Descriptor Configuration Descriptor and String Descriptor usb init SIE 1 mov 90 2 new dev desc mov 91 2 new conf desc mov 92 2 new string desc SIE2 mov 106 2 new dev desc mov 107 2 new conf desc mov 108 2 new string desc ret new dev desc db 18 db 1 dw 0x0101 db Oxff db 0 db 0 db 64 dw OxTBD dw OxTBD dw 0x0100 db 1 db 2 db 3 db 1 new conf desc db 9 db 2 dw new end all new conf desc db 1 db 1 db 0 db OxCO db 0 new interface desc db 9 db 4 db db db db db db db
92. ions 3 1 Introduction The USB Host BIOS will support two application modes co processor mode and stand alone mode It includes support for TD list transfer USB Reset Speed Detection and SOF EOP gener ation 3 1 1 Co processor Mode In co processor mode the EZ Host EZ OTG device works with the System CPU via the HPI HSS or SPI port An example of an application is a USB Host Controller in a PDA or a cellular phone with an embedded microprocessor running a Real Time Operating System RTOS such as WinCE Linux VxWorks or Nucleus The RTOS has a USB stack Inside the USB stack the HCD Host Controller Driver is used to control the EZ Host or EZ OTG device Figure 3 1 illustrates this kind of application Applications Operating System Embedded USB System Device Stack USB Driver Stack Figure 3 1 Co processor Mode Chapter 3 USB Host BIOS Specifications Page 3 1 BIOS User s Manual The HCD builds a Transaction Descriptor TD list for each frame The TD list and data are loaded into the EZ Host EZ OTG buffer The EZ Host EZ OTG device then transfers the data associated with this TD list to or from USB The HCD is informed of completion of the TD list processing via the SIE mailbox at which time it checks the TD status The HCD then builds a new TD list for the next frame and loads it into the EZ Host EZ OTG device While the TD transfer is executed the HCD copies the previous frame s IN data from the EZ Host EZ
93. ks HUSB_SIEx_CurrentTDPtr If HUSB_SIEx_pCurrentTDPtr is not zero there is a TD list waiting for transfer If HUSB_SIEx_pCurrentTDPtr 0 there is no TD list waiting for transfer Continue checking at the beginning of every frame EZ Host EZ OTG device transfers this TD list to USB bus If there is a TD list waiting for transfer the EZ Host EZ OTG device begins to transfer this TD list to the USB bus After completion of the TD list the EZ Host EZ OTG device sends the HUSB_TDListDone to HCD The EZ Host EZ OTG device does this via SIE mailbox It informs the HCD that the TD list has been finished It also sets semaphore at HUSB SIEx pTDListDone Sem Page 3 4 BIOS User s Manual v1 1 HCD Host Controller Driver HCD Configures EOT End Of Transfer EOT is a configurable duration of time prior to the end of a frame All transactions should be completed by the time the starting point of EOT is reached During this time the HCD checks the status of the previous TD list and loads a new TD list before the next frame TD Load HCD prepares the TD list and loads it into the EZ Host EZ OTG buffer There are ping pong buffers in the EZ Host EZ OTG part to speed up the transfer After loading the TD list HCD writes the TD list pointer to HUSB SIEx pCurrentTDPtr TD Check After receiving the HUSB TDListDone the HCD checks the finished TD The HCD handles any transfer errors during this step TD DataCopy HCD copies the IN data from E
94. least 30 microsec onds between sending a new command packet While changing BAUD rate commands via the COMM CONFIG the Host must wait at least 100 microseconds before sending any new com mands with the new baud rate Page 1 10 BIOS User s Manual v1 1 bool hss xfer char cmd int len char buf int i stat bool data_wr FALSE if len gt 2048 return FALSE hss HW support upto 1024 words for i 0 i lt 8 i HSS Write byte cmd i 8 byte commands no delay here Read_ACK NAK status stat HSS Read_byte stat HSS Read_byte lt lt 8 stat i cmd 0 cmd 1 lt lt 8 switch i case COMM WRITE XMEM case COMM WRITE MEM data_wr TRUE if len gt 0 if data wr for i 0 i lt len i HSS Write byte buf i else for i 0 i lt len i buf i HSS Read byte if i COMM CONFIG Delay 100us requires for change baud rate else Delay 30us between LCP need this delay return TRUE The HSS hardware transfer length only supports up to 2048 bytes i e 1024 words Chapter 1 BIOS Interface Page 1 11 BIOS User s Manual 1 4 3 LCP Overview for Serial Peripheral Interface SPI Refer to Chapter 6 SPI Transport Module Firmware for complete details on this topic In SPI mode the EZ Host or EZ OTG device acts as an SPI Slave to the external host The SPI connection requires a more detailed protocol because it is a master driver synchronous half du
95. less specifically mentioned all responses are either COMM ACK or COMM NAK Chapter 1 BIOS Interface Page 1 9 BIOS User s Manual 1 4 1 1 Programming Overview HPI functionality is such that the following operations should happen for each LCP Command that is issued Any data required for the LCP CMD is sent via HPI DMA i e COMM CODE ADDR The LCP command is then sent via HPI mailbox e The HPI status register is polled or an ISR is used to wait for mailbox response back from the BIOS The response is then read from the mailbox e Any additional data from CMD execution is read using HPI DMA i e COMM CTRL REG DATA 1 4 2 LCP Overview for High Speed Serial HSS Refer to Chapter 7 HSS Transport Module for complete details on this topic HSS is a full duplex interface By default the BIOS sets up the HSS port as a simple 2 wire inter face with no hardware or software handshaking LCP commands are always sent in an 8 byte packet This packet contains the 16 bit LCP com mand and in some cases additional data for the command like address and length of data to fol low When the Host sends down a command the Host must be ready to receive the resultant data via an ISR A sequence diagram of each LCP command is given in Chapter 7 Na Note The external host processor is in full control of the interface as a master The Host must give time to the BIOS in between sending LCP commands The Host should wait at
96. ll not be sent Chapter 5 HPI Transport Module Page 5 5 BIOS User s Manual 5 3 7 3 COMM_CALL_CODE via HPI Set Call SET co Address MM CODE ADDR Send CMD LC9MM cart cope Call Code Wait Tor then Send Response R esponse Figure 5 4 COMM CALL CODE via HPI VA Notes COMM_CODE_ADDR is defined as same as the COMM_MEM_ADDR which is a pointer to the code to jump to it is written via HPI Direct Memory Access not the mailbox Then the COMM_CALL_CODE can be sent over the mailbox Of course before either of these operations is done the code itself should exist in the memory space that COMM_CODE_ADDR will point to Ifthe code jumped to does not return then the ACK will not be sent Page 5 6 BIOS User s Manual v1 1 5 3 7 4 COMM_WRITE_CTRL_REG via HPI Set Control Reg Address and Value SET COMM _CTRL REG ADDR SET COMM CTRL REG DATA Optionally set LOGIC Operation Send CMD OMM WRITE CTRL REG Wait for Response Figure 5 5 COMM_WRITE_CTRL_REG via HPI VA Notes The COMM_CTRL_REG_ADDR is defined the same as the COMM_MEM_ADDR which is a pointer to the CY 16 address to be read The COMM CTRL REG DATA is defined as the COMM MEM LEN and the COMM CTRL REG LOGIC is defined as the COMM LAST DATA Users should supply the COMM CTRL REG ADDR COMM CTRL REG DATA and COMM CTRL REG LOGIC before writing the command COMM WRITE CTRL REG in the HPI mailbox Chapter 5 HPI Transport Module Page 5 7
97. ller and more organized with a uniform interface less duplicity and less coupling Tool Support Is available on both USB ports but not simultaneously Speed Support Low or full speed configuration is possible for either or both SIEs Variable Number of Endpoints Since devices can have different numbers of endpoints and SIEs a configuration mechanism was needed to prevent memory space from being waste on unused endpoint buffers and data within the BIOS The passing of an initialization table to the init routine accommodates this This way the variable amount of memory in which the table lives resides in the users space i e only users with many endpoints get the many endpoint memory penalty This may be augmented later with a library routine that can parse a device s descriptors to generate the table Variable Endpoint Size Support a variable size amount on an endpoint by endpoint basis Odd Transaction Support Generic endpoint processing supports transactions that are not inte ger multiples of the endpoint length Chapter 4 Slave Support Module Firmware Page 4 11 BIOS User s Manual Page 4 12 BIOS User s Manual v1 1 7 CYPRESS j Chapter 5 HPI Transport Module 5 1 Introduction 5 1 1 Overview The Host Processor Interface HPI provides a high speed interface into the CY16 processor for control and debug purposes The interface port provides a bi directional mailbox and bi directional DMA The DMA channel i
98. lly shared among all endpoints It is a single processing routine that utilizes endpoint specific states to process transfers on behalf of the endpoints This support is also entirely contained in the BIOS 4 3 2 1 Behavior This support simplifies all transfers across all endpoints by providing a uniform interface and behavior An application would prepare a buffer and a frame referencing the buffer The frame would contain a pointer to the buffer the buffer s length a null next frame pointer and a call back routine pointer The application would then setup and call either the SUSBx_SEND_INT or SUSBx_RECEIVE_INT to submit the frame The generic processing block would log the frame and set up the endpoint registers in the SIE to transfer either a portion or all the data depending on the amount of data and the size of the endpoint The SIE would then trigger the endpoints ISR after the data transferred The ISR would call setup and call into the generic block where pointers would be walked along the data buffer and counts adjusted and SIE registers again configured for the next data portion Eventually all the data would be transferred and the ISR s call into the generic block would reset the state for that endpoint and issue a call back to the user application The following sequence diagram details this behavior Page 4 6 BIOS User s Manual v1 1 e N Endpoint ISR SIE E Cu Generic Endpoint Support User Appli
99. lone applica tions will typically not use LCP although they can Chapter 2 Link Control Protocol Firmware Page 2 1 BIOS User s Manual 2 2 Detailed Design 2 2 1 Architectural Outline As shown in Figure 2 1 the command processor is the heart of the communication system between EZ Host EZ OTG and the system CPU Link Control Protocol Port Commands LCP Idle Task L___ 4 Tess H COMM CALL CODE COMM EXEC INT Send Receving to E from HPI HSS SPI Po Cas Figure 2 1 Link Control Protocol The Icp_idle task handles port commands which are completely controlled by the chip The mem ory can be read and written control registers can be read and written and interrupts can be trig gered This level of access however does not hide all of the hardware dependencies from the programmer of the system CPU unless a library of functions is created on the system CPU to abstract the different functions of EZ Host EZ OTG into simple interfaces In order to make this abstraction simpler and faster for the system CPU a set of functions can be built and downloaded to the EZ Host EZ OTG device where all of the desired functionality of the chip for the given application is abstracted through the use of the command processor This allows the Host to communicate with a simple flexible and extensible API from system CPU to the EZ Host EZ OTG device Na Note The LCP exposes all of the functionality of the chip Page 2 2
100. mov epi call epi done mov epi loc image line image buffer pointer mov epi len r7 Size of the image line mov r8 ep0 link r8 pointer to linker mov Ti T r1 0 setup endpoint 0 int SUSB1_SEND_INT Call interrupt ret ep1_ done User s Application interface or call usbl epl send data again ret data send receive control header block Chapter 1 BIOS Interface Page 1 55 BIOS User s Manual epl link dw 0 epl loc dw 0 epl len dw 0 epl call dw 0 1 7 6 Interrupt 51 63 and 118 125 These interrupts are free and may be used for extended applications These locations are not ini tialized at power up 1 7 7 Memory Functions 1 7 7 1 Interrupt 76 REDO ARENA This interrupt is used to recalculate free memory when any additional memory becomes available to the memory pool This interrupt will be removed on the next revision of the BIOS The BIOS calls this interrupt at the beginning of the power up 1 7 7 2 Interrupt 69 Memory Data Pointer The interrupt 69 vector is used as a variable data pointer to the beginning of the memory area that is used by Interrupts ALLOC INT FREE INT This location is reserved for the BIOS DO NOT MODIFY THIS LOCATION 1 7 7 2 4 Software Interface This vector is a data pointer only do not execute code i e JMP or INT to this vector The vector points to the first memory structure Memory Structure dw MEM BLOCK SIZE Size of memory block including this structure dw USED FREE
101. mware KEN Wiese Ee N EE 2 1 2 14 Re ONE EE 2 1 DEV 2 SCOP EE 2 1 2 2 Detailed DESION EEN 2 2 2 2 1 Architectural Outline vico 2 2 2 2 2 Transport Requirements sssssssssssssssssssese esent enne enne n nennen sitne 2 3 2 23 BIOS ROM Code IE GP A eai reete epale ERC 2 3 2 2 3 1 Data Structures and Variables for Port Command Processing 2 3 2 2 3 2 Command Descriptions 2 ecciesie eterno io 2 4 Chapter 3 USB Host BIOS Specifications E Dulli TEE TTT EE 3 1 3 1 1 Co proc ssor Mode ci hn eid eines 3 1 3 1 2 Starid alone MOde iioii iice eiae eie pce vines Eed e ee pedites 3 2 3 2 Furictional Requiremernits ccrte prier tenente v e eee eene tpe Ene ah Eee up Ep boe eoe E eere d eed 3 2 3 3 USB Host BIOS OvervieW rini denne benc deer dE de be lune a Eee ade Spe i Ree ire ig 3 2 3 3 1 Bl ck Diagr EE 3 2 3 3 1 1 HUSBSIEX INITAN iure da AER 3 3 3 3 1 2 HUSB RESET INT icri ia ias 3 4 3 3 2 Flow Chart of USB Transfer sess eene nnne nenne 3 4 3 4 Software Interface Between HCD and BIOG 3 6 3 4 1 TD Semaphore Address rrt terret iaa 3 7 3 4 1 1 HUSB SIEx pCurrentTDPtr nunnana a nn mener 3 7 9 4 1 2 EOT and HUSB pEO Tipos 3 7 3 4 1 3 HUSB SIEx pTDListDone Gem 3 8 3 4 2 TD SIE Mailbox MESSAGE eerie io citt io metres eg ete I ERE EP e Reb dd 3 8 3 5 TD ListiData Structure 2 5 e
102. n of the transfer so other transactions can take place Page 7 2 BIOS User s Manual v1 1 7 3 5 HSS_SEND_BLOCK Routine The HSS_SEND_BLOCK routine is used to send data to the External CPU using DMA Entry R1 Number of Words to Send R8 Pointer to data R9 Pointer to HSS_TX_BLK_ADDR Return None 7 3 6 HSS_RECEIVE_BLOCK Routine The HSS_RECEIVE_BLOCK routine is used to receive data from the External CPU using DMA Entry R1 Number of Words to Send R8 Pointer to data R9 Pointer to HSS_RX_BLK_ADDR Return None A Note As a master the external host processor is in full control of the interface The Host must grant time to the BIOS in between sending LCP commands The Host should wait at least 30 microseconds between sending a new command packet This time is required due to the LCP idle task is running as part the BIOS idle tasks This number assumes only one SIE is activated at a time If two SIEs and UART idle tasks are involved then this time should be extended When changing the BAUD rate command via the COMM CONFIG the Host must wait at least 100 microsecond before sending any new command with the new baud rate Chapter 7 HSS Transport Module Page 7 3 BIOS User s Manual 7 3 7 HSS TRANSFER DIAGRAMS FOR LCP 7 3 7 1 COMM_RESET via HSS COMM RESET 7 0 COMM RESET 1 5 8 mm e E NN Send 8 Byte CMD Packet Wait for 2 Bytes of ende Response COMM ACK U 9l Respons
103. nRD gt gt gt read gt CPU Bus HPI_INTR outgoing mailbox interrupt HPI_D 15 0 data DMA memory address counter On chip Memory System DMA ROM RAM data buffer lt gt registers PO Figure 5 1 EZ Host EZ OTG Chip 5 3 3 Host DMA to from EZ Host EZ OTG Memory via HPI Port The host can access the on chip ROM and on chip RAM of the EZ Host EZ OTG part Obviously the on chip ROM is read only A data block write by the host to the on chip memory begins with the System Host writing the EZ Host EZ OTG memory address to the HPIADDR register followed by writing the data block contig uously to the HPIDATA register A data block read by the host from the on chip memory begins with the host writing the EZ Host EZ OTG memory address to the HPIADDRR register followed by reading the data block with con secutive reads from the HPIDATA register Loading the HPIADDR register must precede changing host read write direction The memory addresses are auto incremented after each access to the HPIDATA register The HPI interface pre fetches data from the on chip memory system when the HPIADDR register is loaded and after every read from the HPIDATA register Therefore reading a block of n words from the HPI port results in n 1 read accesses to the on chip memory system The pre fetch pipe line also delays the read data The maximum data transfer
104. nd data to the Host CPU Entry R1 Number of words to send R8 Pointer to data RQ Pointer to SPI_TX_ADDR Return Assert IRQO high 6 3 6 SPI_Rec_BIk Routine The SPI_Receive_BIk routine is used to send data to the Host CPU Entry R1 Number of words to send R8 Pointer to data R9 Pointer to SPI_RX_ADDR Return None 6 3 7 SPI polling the Status If the application interface decides to poll the STATUS after each LCP command it must poll the first MSB status byte until it returns a not equal to OxFF In the case of polling the STATUS byte the Host must give time to the BIOS in between sending LCP commands and reading responses The Host should wait at least 100 microseconds Assume only one SIE and no other activity like UART If there are more idle tasks this number needs to be adjusted after sending a CMD packet before attempting to poll the response Also after receiving a response the host should wait 100 micro seconds before issuing another CMD packet If the application interface decides to use the inter rupt then the IRQO GPIO24 can be used as the interrupt signal whenever the STATUS word is ready to be read IRQO is normally a low signal and the BIOS will set it high when the STATUS is ready This signal will be low when the STATUS word is finished reading from the external micro processor Note If the first byte of the STATUS word is equal to OxFF it must continue to read this byte until it returns a
105. o PID_EP when submitting a TD EP3 0 4 bit Endpoint Value in Binary PID3 0 4 bit PID Field See Table Below PID Type Bit7 Bit4 SETUP 1101 D Hex IN 1001 9 Hex OUT 0001 1 Hex SOF 0101 5 Hex PREAMBLE 1100 C Hex NAK 1010 A Hex STALL 1110 E Hex DATAO 0011 3 Hex DATA1 1011 B Hex Example If the TD is for endpoint 1 and PID_IN 0x91 should be written into PID_EP Chapter 3 USB Host BIOS Specifications Page 3 11 BIOS User s Manual 3 5 4 DevAdd BYTE 0x05 Table 3 5 DevAdd BYTE 0x05 Bit Position Bit Name Function 0 DAO Device Address 1 DA1 Device Address 2 DA2 Device Address 3 DA3 Device Address 4 DA4 Device Address 5 DA5 Device Address 6 DAG Device Address 7 Reserved The device address must be written into DevAdd when submitting a TD DA6 0 7 Bit Device Address in Binary EXAMPLE If the TD is to be sent to device address 3 0x3 should be written into DevAdd 3 5 5 Control BYTE 0x06 Table 3 6 Control BYTE 0x06 Bit Position Bit Name Function 0 ARM 1 Arm transaction 1 Reserved Reserved 2 Reserved Reserved 3 Reserved Reserved 4 ISO 1 allows ISO mode for this transaction 5 SynSOF 1 Synchronize transfer with SOF 6 DToggle Sequence Bit 0 if DATAO 1 if DATA1 7 Preamble When set to 1 sends pre amble packet The control register information must be written into Control when preparing a TD ARM bit Should always be 1 when loading a TD ISO bit Fo
106. o does error handling for control and bulk transfers For ISO and Interrupt transfer errors it will let the HCD handle the error The ActiveFlag is not changed to inactive for ISO and Interrupt transfers After the TD list is finished the BIOS sends HUSB_TDListDone to the HCD via the SIE mail box It also sets a semaphore at HUSB_SIEx_pTDListDone_Sem for the HCD Chapter 3 USB Host BIOS Specifications Page 3 3 BIOS User s Manual 3 3 1 2 HUSB_RESET_INT HUSB_RESET_INT performs three functions USB Reset Before accessing a USB device the HUSB_RESET_INT will generate a USB reset which forces the peripheral device to its default address of zero After USB reset configuration soft ware can read the device s descriptor at the default address Speed Detect The HUSB_REST_INT will detect the full low speed of the attached device and then return the port status FULL SPEED LOW SPEED or NO DEVICE SOF EOP Generation Based on the device speed HUSB_RESET_INT will generate SOF for full speed and EOP for low speed If no device is attached on this port there will be no SOF EOP 3 3 2 Flow Chart of USB Transfer The USB transfer needs the EZ Host EZ OTG Host BIOS and HCD to work together Figure 3 3 shows how data is transferred over USB EZ Host EZ OTG USB Host BIOS EZ Host EZ OTG reset Sets SIE to host mode initializes the registers sets the interrupt vectors and enables host interrupts EZ Host EZ OTG device chec
107. ontain the current device request structures for each SIE for example db bmRequest db bRequest Page 1 50 BIOS User s Manual v1 1 dw wValue dw windex dw wLength Registers Usage None Return None Na Note If more OUT data is to be received on endpoint 0 calls to SUSBx RECEIVE INT should be made If more data is to be sent calls to SUSBx SEND NT should be made This is at interrupt level you may use any registers but you should return promptly You must supply a routine for this if class specific commands are to be used 1 7 5 11 2 Example Example 11 Intercept SUSB1 CLASS INT vector All Software and Hardware initialization should be done here device request offsets bmRequest equ 0 bRequest equ 1 wValue equ 2 wIndex equ 4 wLength equ 6 CLASS VEC equ SUSB1 CLASS INT 2 usb init mov CLASS VEC class int replace class int ret Class Specific command table class table dw vCPUPoke 0x41 wValue Addr wIndex Data wLength 0 dw vCPUPeek 0x42 wValue Addr wLength Cnt usb1 ep send data v bad epO done int SUSB1 FINISH INT ret process vendor commands class int r8 0x300 SIE1 request base pointer mov r0 b r8 bRequest cmp r0 0x42 1 if r0 index of vRamTest goto v bad jnc v bad cmp r0 0x41 if r0 lt vCPUPoke goto v bad jc v bad sub r0 Ox41 get the Offset mov r10 r0 shl r10 1 index 2 jmp ri0 class table jump to vector table entry Chapter 1
108. oprocessor should not expect the ACK The Interrupt vector is stored in COMM INT NUM If the COMM R0 COMM R13 are used in the associate interrupt then it should be updated When the HPI is used the COMM INT NUM and COMM R0 COMM R13 locations are written using direct hardware access When HSS or SPI is used this value comes from a COMM MEM WhARITE transaction or as part of the port communication packet along with the command Note The BIOS will not check the interrupt range i e 0 127 Invalid ranges can cause unpre dictable results COMM READ CTRL REG i e Memory Peek command Action Read Control Register Data Used COMM MEM ADDR Response COMM ACK Chapter 2 Link Control Protocol Firmware Page 2 5 BIOS User s Manual This command is designed to read the entire address space of the CY16 64K i e internal RAM internal ROM external RAM ROM DRAM and all the CY16 CPU control registers Note All the Read cycles will be in 16 bit access For HPI the COMM_MEM_ADDR must use direct hardware access to modify this location For the HSS SPI this variable is part of the 4 word command structure HPI requires a read of the address 0x01BE COMM MEM LEN to get the return data after receiving an ACK from the command COMM READ CTRL REG For the HSS SPI the extra word read will be sent by the lcp idle task COMM WRITE CTRL REG i e Memory Poke Command Action Write Control Register Data Used COMM MEM ADDR Ox1BE COMM CTRL
109. or has full control of both SIEs and SUSBx RECEIVE INT is disabled Entry R8 points at an 8 byte control header block structure defined as follows a dw next link pointer used by this routine input must be 0x0000 dw address pointer to the address of the device that is sending data AAA dw length length of data to send AA dw call back pointer of the call back subroutine R1 Bits 3 0 select the endpoint determines where to send should be from 0 to 7 max Bits 15 4 are reserved for future BIOS usage Registers Usage R1 R8 R10 R11 Page 1 44 BIOS User s Manual v1 1 Return RO zero successful else error dw link pointer 0 reserved for future of BIOS dw address address length dw length 0 successful transfer else the remaining length has not transferred dw call_back if call_back 0 it will not be executed else it will be executed In HPI co processor mode the SIExmsg in the HPISTS register will get interrupted In co processor mode the data in the following table will be applied Registers Endpoint SUSB1_RECEIVE_INT SUSB2_RECEIVE_INT 0x144 0x148 0 EndpointO interrupt on SIE1msg SIE2msg from HPISTS register bm 1 Endpoint1 interrupt on SIE1msg SIE2msg from HPISTS register bit1 2 Endpoint2 interrupt on SIE1msg SIE2msg from HPISTS register bit2 3 Endpoint3 interrupt on SIE1msg SIE2msg from HPISTS register bit3 4 Endpoint4 interrupt on SIE1msg SIE2msg from HPISTS register bit4 5 Endpoint5
110. osition Bit Name Function 0 RetryCntO Retry Counter Bit 1 RetryCnt1 Retry Counter Bit 2 TransferTypeO Transfer Type 3 TransferType1 Transfer Type 4 ActiveFlag T is active 0 is inactive 5 Reserved 6 Reserved 7 Reserved RetryCnt1 0 2 bit RetryCnt Value in Binary The RetryCnt0 and RetryCnt1 must be 1 when submitting a TD When doing a TD Check check how many retries are left The maximum number of retries is three TransferType1 0 2 bit Transfer Type in Binary 00 Control 01 ISO 10 Bulk 11 Interrupt When doing a TD_Load the transfer type must be written into TransferType ActiveFlag TD active flag T Active Q Inactive The ActiveFlag must be 1 when submitting a TD When doing a TD_Check check this bit to see if the TD is active For more details please refer to Section 3 6 Error Handling Example If the TD transfer type is Bulk 0x1B should be written into RetryCnt Page 3 14 BIOS User s Manual v1 1 3 5 8 Residue BYTE 0x09 The Residue must be 0 when submitting a TD If the TD type is non ISO and the overflow bit is set when doing a TD_Check Residue must be checked For the non ISO transfer case the maximum packet size is 64 So If the 7 bit is 0 itis an UNDERFLOW and Residue contains the number of bytes left over from Port Length If the 7 bit is 1 it is an OVERFLOW The number is twos complement value in 8 bit rep resentation It
111. ote When both these bits are enabled the co processor has full control of both SIEs and SUSBx SEND INT will be disabled Entry R8 points at an 8 byte structure defined as follows A dw next link pointer used by this routine input must be 0x0000 dw address pointer to the address of sending data AAA dw length length of data to send AA dw call back pointer of the call back subroutine R1 Bits 3 0 select the endpoint determines where to send should be from 0 to 7 max Bits 15 4 are reserved for future BIOS usage Registers Usage R1 R8 R10 R11 Return RO zero successful else error dw link pointer 0 reserved for future of BIOS dw address address length dw length 0 successful transfer else the remainder length has not transferred dw call back if call back 0 it will not be executed else it will be executed In the HPI co processor mode the SIExmsg in the HPISTS register will get interrupt In co processor mode the data in the following table will be applied Page 1 40 BIOS User s Manual v1 1 Endpoint 0 s OOA W DN Notes SUSB1_SEND_INT SUSB2_SEND_INT Endpoint0 interrupt on SIE1msg SIE2msg from HPISTS register Endpoint1 interrupt on SIE1msg SIE2msg from HPISTS register Endpoint2 interrupt on SIE1msg SIE2msg from HPISTS register Endpoint3 interrupt on SIE1msg SIE2msg from HPISTS register Endpoint4 interrupt on SIE1msg SIE2msg from HPISTS register Endpoint5 interrupt on SIE1msg SIE2m
112. ow to send data to the host with these interrupts mbx msgi equ 0x144 mailbox message address Chapter 1 BIOS Interface Page 1 41 BIOS User s Manual Stand alone sample code usbl epO send data mov epO_ next link 0 mov ep0_address image line mov epO_ length 320 mov epO call back ep0_ done mov r8 ep0 next link mov rl O int SUSB1 SEND INT ret ep0_ done int SUSB1 FINISH INT ret data image line dup 320 ep0 next link dw 0 ep0 address dw 0 epO0 length dw 0 ep0 call back dw 0 VA image buffer pointer size of the image lin call back for endpointo r8 pointer to linker r1 0 setup endpoint 0 call interrupt call STATUS phrase Note In endpointO the STATUS phase is required for completion of DevicelOCTL from the host BIOS will check the epO call back If the pointer 0 BIOS will handle the STATUS For endpoints 1 7 users should provide a call back The BIOS also sets the mbx msg1 for both stand alone and co processor modes A read of the mbx_msg1 value can be done with the following code short mbx copied if mbx msgl 0 mbx copied mbx msgl mbx msgl 0 Page 1 42 copy the mailbox messagel allow BIOS to update the new message BIOS User s Manual v1 1 Example 7 Co processor mode sending data over SIE2 port C USB endpoint 2 Co processor sample code detail of these code will be provided in the A typedef struct WORD wNextLink WORD wAddress
113. plex interface Hence the master must poll for the data after an LCP command is issued or it must use an additional hardware interrupt to notify the Host that data is ready The BIOS supports both modes of communication In the SPI mode the GPIO24 line can be used as the interrupt line to the external processor if the application avoids polling the COMM_ACK status Note The external host processor is in full control of the interface as a master The Host must give time to the BIOS in between sending LCP commands and reading responses The Host should wait at least 100 microseconds after sending a CMD packet before attempting to poll the response Also after receiving a response the host should wait 100 microseconds before issuing another CMD packet For example bool spi_xfer char cmd int len char buf int i stat bool data_wr FALSE if len gt 1024 return FALSE spi HW support upto 512 words for i 0 i lt 8 i SPI Write byte cmd il 8 byte commands no delay here Read ACK NAK status do d Delay 100us Stat SPI Read byte while stat Oxff stat SPI Read byte lt lt 8 stat i cmd 0 cmd 1 lt lt 8 switch i case COMM WRITE XMEM case COMM WRITE MEM data_wr TRUE if len gt 0 if data wr for i 0 i lt len i SPI Write byte buf il else for i 0 i lt len i buf i SPI Read byte Delay 100us between LCP need this delay return TRUE The S
114. pport is the ability to service device requests required to enumerate and reset a device Vendor command pro cessing supports USB loader debugger and memory peek and poke functionality Generic end point support includes a software interrupt based interface to manage endpoint buffer framework 4 1 2 Scope This document describes functional requirements an architectural outline interrupt service rou tines register usage data structures subroutines error handling important design decisions and unit tests for the slave support module The software descriptions outline the processing flow and interfaces and include diagrams as needed The unit test descriptions describe the test themselves as well as the test environment and methodology The reader should have a cursory familiarity with USB control transfer processing generic USB endpoint support and the EZ Host EZ OTG hardware architecture see Appendix B 4 2 Functional Requirements The Slave Support Module s functional requirements consist of standard chapter 9 processing vendor specific command processing and generic endpoint support for both SIEs Standard chap ter 9 processing is the ability to service standard device requests via the default endpoints The specific vendor command support consists of software tool and USB loader support Generic end point support is the default BIOS support for servicing endpoint interrupts and the software inter rupt interface to these servi
115. pts every time a request to set the configuration and USB_RESET occurs If you want to receive notification of configuration changes you should chain these interrupts i e replace the vector with a vector to your code which ends with a jump to the original vector leaving the registers in the same state they were found These interrupts must be overridden to support multiple configurations refer to USB Specification version 2 0 for details These interrupts are called at the interrupt level If the procedure will take some time you should set a flag and process the procedure in the foreground see interrupt 70 1 7 5 13 1 Software Interface Entry The standard peripheral USB handler will call these interrupts whenever the configuration is changed These interrupts should be chained with a vector to a notification handler in order for a user application to receive notification of configuration changes Return None 1 7 5 13 2 Example Example 12 Intercept SIE1 port A Delta Configuration change and insert notification old usb delta config dw 0 DELTA VEC equ SUSB1 DELTA CONFIG INT 2 usb init mov old usb delta config DELTA VEC save old delta config vector mov DELTA VEC new delta config replace with new delta config ret new delta config configuration change handling here call usbi1 epl send data If use EP1 need to do this call old usb delta config usbl epl send data mov epi link 0
116. r ISO transfers it must be 1 For other transfers it must be 0 SynSOF bit When set to 1 the transaction takes place after the next SOF If set to 0 the transaction takes place immediately if the SIE is free Page 3 12 BIOS User s Manual v1 1 DToggle bit Data toggle 0 if DATAO 1 if DATA1 It must be written for both OUT data and IN data For IN data it is also used for checking the sequence error Preamble bit When requiring the SIE to generate PREAMBLE this bit must be set to 1 This happens when transferring a TD to low speed devices behind a hub Otherwise it must be set to 0 Example If the TD is to be sent to a low speed device behind a HUB with Sequence DATA1 0xC1 should be written into Control 3 5 6 Status BYTE 0x07 Table 3 7 Status BYTE 0x07 Bit Position Bit Name Function 0 Ack Transmission acknowledge 1 Error Error detected in transmission 2 Time Out Time Out occur 3 Seq Sequence Bit 0 DATAO 1 DATA1 4 Reserved 5 Overflow Overflow condition maximum length exceeded during receive or Underflow condition 6 NAK Peripheral returns NAK 7 STALL Peripheral returns STALL The Status must be set to 0 when submitting a TD and must be checked after the TD list is done Example Always write 0 into Status Chapter 3 USB Host BIOS Specifications Page 3 13 BIOS User s Manual 3 5 7 RetryCnt BYTE 0x08 Table 3 8 RetryCnt BYTE 0x08 Bit P
117. r8 r9 jmp usbl ep0O send data host read from end point 0 ep0_ done int SUSB1 FINISH INT ret data send receive control header block ep0_link dw 0 ep0_loc dw 0 ep0_len dw 0 ep0 call dw 0 1 7 5 11 Interrupt 87 103 SUSB1_CLASS_INT SUSB2_CLASS_INT The BIOS will return STALL for these interrupts as the default These Interrupts implement the USB vendor interface based on Chapter 9 of the USB Specification version 2 0 The interrupts will be called whenever bit 5 of a bmRequest byte is set omRequest amp 0x20 0x20 These inter rupts must be replaced for any extension of the application These interrupts will be called inside the interrupt 32 SIE1 and interrupt 40 SIE2 All the regis ter saves and restores will be maintained by these ISRs When a SETUP packet is detected the BIOS will call these interrupt after clearing the interrupt status register Oxc090 for SIE1 and OxCOBO for SIE2 For SIE1 the register R8 will point to the buffer at address 0x300 and R9 will point to 0x200 DEV1 EPO CTL REG For SIE2 register R8 will point to the buffer at address 0x308 and R9 will point to 0x280 DEV2 EPO CTL REG These interrupts cover the range of the bmRequest value from 0x20 to Ox3F 1 7 5 11 1 Software Interface Entry R8 0x300 for SIE1 0x308 for SIE2 R9 0x200 for SIE1 0x280 for SIE2 SIE buffers 1 and 2 ports A and C execute device requests at internal RAM addresses 0x0300 and 0x0308 respectively These memory locations c
118. red This routine must e Return the byte in the lower half of RO with the upper half cleared Leave R1 R2 R8 and R9 intact Registers Usage None Signature Data Structure Format dw 0xc3b6 Starting Signature dw Length Length of data to follow exclusive of signature length and opcode db OpCode Type of action to take db Data 1 to n bytes of data depending on OpCode and length Format of Data for each OpCode OpCode 0x00 Write Data dw Starting Address db Data0 DataN OpCode 0x01 Write At Interrupt Vector db Interrupt Vector Number db Data0 DataN OpCode 0x02 Write Interrupt Service Routine db Interrupt Vector Number db Data0 DataN see Note 1 below OpCode 0x03 Fix up relocate ISR Code db Interrupt Vector Number dw OffsetO OffsetN see Note 2 below OpCode 0x04 Jump to Absolute Address dw Address OpCode 0x05 Call Absolute Address dw Address OpCode 0x06 Call Interrupt db Interrupt Number Page 1 22 BIOS User s Manual v1 1 OpCode 0x07 Read Memory using Interrupt db Interrupt Number dw Interface Address if interface needs an address dw Address of data to write dw Length of data to write OpCode 0x08 Move Data using Interrupt db Interrupt Number dw initial address to write db Data0 DataN to write using Interrupt OpCode 0x09 Write Configuration db configuration address to write a Oxc000 is added for the device address dw data to write to above addr
119. ree basic functions to work with EZ Host EZ OTG part TD_Load s TD Check TD DataCopy The software interface between HCD and BIOS includes the followings TD Structure TD Semaphore Address e TD SIE Mailbox Message The TD structure is discussed in a separate section The TD semaphore address and TD SIE mail box message information is presented in this section 3 4 1 TD Semaphore Address The BIOS contains five TD semaphore addresses shared memory which deliver semaphore between BIOS and HCD They are listed below and subsequently described HUSB SIE1 pCurrentTDPtr equ Ox1BO Address to SIE1 current TD pointer HUSB SIE2 pCurrentTDPtr equ Ox1B2 Address to SIE2 current TD pointer HUSB pEOT equ 0x1B4 Address to End Of Transfer HUSB SIE1 pTDListDone Sem equ 0x1B6 Address to SIE1 TD List Done Semaphore HUSB SIE2 pTDListDone Sem equ 0x1B8 Address to SIE2 TD List Done Semaphore 3 4 1 1 HUSB SIEx pCurrentTDPtr BIOS At the beginning of every SOF BIOS checks HUSB SIEx pCurrentTDPtr to see If there is a TD list waiting for transfer If there is the BIOS begins the TD list transfer HCD When TD Load finishes loading the TD list to the EZ Host EZ OTG device it writes the TD list address to HUSB SIEx pCurrentTDPtr 3 4 1 2 EOT and HUSB pEOT TD Check and TD Load must be done with BIOS in sequence So it is important to keep proper timing A point called EOT End of Transfer is defined for each frame
120. ress WORD 0x00 01 Table 3 2 BaseAddress WORD 0x00 01 Bit Position Bit Name Function 0 15 BaseAddress Base Address The pointer to the TD data must be written into BassAddress when preparing a TD Example If the TD data address is OXAOC OxAOC should be written into BaseAddress Chapter 3 USB Host BIOS Specifications Page 3 9 BIOS User s Manual 3 5 2 Port_Length WORD 0x02 03 Bit Position OMAN DOR WN O A ect Sech WON zz o 15 Table 3 3 Port_Length WORD 0x02 03 Bit Name DLO DL1 DL2 DL3 DL4 DL5 DL6 DL7 DL8 DL9 Reserved Reserved Reserved Reserved PNO PN1 Function Data Length Data Length Data Length Data Length Data Length Data Length Data Length Data Length Data Length Data Length Port Number Port Number The TD data length and port number must be written into Port_Length when submitting a TD DL9 0 10 Bit Data Length Value in Binary PN1 0 2 Bit Port Number in Binary 00 Port 0 Port A 01 Port 1 Port B 10 Port 2 Port C 11 Port 3 Port D EXAMPLE If the TD is for port 1 port B and data length is 8 0x4008 should be written into Port_Length Page 3 10 BIOS User s Manual v1 1 3 5 3 PID_EP BYTE 0x04 Table 3 4 PID_EP BYTE 0x04 Bit Position Bit Name Function 0 EPO Endpoint 1 EP1 Endpoint 2 EP2 Endpoint 3 EP3 Endpoint 4 PIDO PID 5 PID1 PID 6 PID2 PID 7 PID3 PID The PID and Endpoint number must be written int
121. revious interrupt handler on user s machine SA Note To use this the routine calls interrupt 72 with RO pointing at its handler RO returns with the location of the previous handler After processing is complete your interrupt routine must JUMP to the previous handler Conversely if you want your handler to be at the end of the chain you can call the previous interrupt handler first and then continue with your own handler There is no guar antee that any registers RO R14 are preserved 1 7 8 3 2 Example Example 19 How to insert a new task into the idle chain interrupt INSERT IDLE INT equ 7 new symbol define my idle chain dw 0 variable to hold the old idle chain interrupt The initialization section mov CO ms idle setup insert new idle task to RO int INSERT IDLE INT insert new idle task mov my idle chain r0 this is a link list task The new idle handler should have the following form my idle execute your idle code here jmp my idle chain continue the idle chain The new idle chain tasks will be int 70 gt my idle chain usb idle gt Icp idle 2 uart idle gt return Page 1 64 BIOS User s Manual v1 1 1 7 9 Debugging Support functions 1 7 9 1 Interrupt 126 127 Reserved for Debugger BIOS reserves Interrupts 126 127 for the debugger The GNU debugger will load a STUB program into internal RAM of the CY16 The STUB is a small application program that is written in CY16 assembly lan
122. rface ecrire dic 1 52 AA iet Ee eR ed doe ee oec etu 1 53 1 7 5 13 Interrupt 95 111 SUSB1 DELTA CONFIG INT SUSB2 DELTA CONFIG INT iriure fece ace Scene dct dcos 1 55 1 7 5 13 1 Software ae 1 55 1 7 5 43 2 ue 1 55 1 7 6 Interrupt 51 63 and 11812 1 56 1 47 7 Memory FURiCtioris iioc See Ince a ea 1 56 1 7 7 1 Interrupt 76 REDO ARENA nennen enne nr neret 1 56 1 7 7 2 Interrupt 69 Memory Data bointer cee eeeeeeeeeeeeeeeeecaeeeeeeeeenneaeees 1 56 1 7 7 2 1 Software IMteriace c 2ccccceceesesesnncessdeesncsertgecdenseaeasedeneetegedpeoicesnecsedeuseree 1 56 1 7 7 3 Interrupt 68 ALLOC INTE 1 57 1 7 7 3 1 Software Interface enne nne 1 57 1 7 7 3 2 Example n Uere p tege pe leet eie e ee of etus 1 57 1 7 7 4 Interrupt 75 FREE INTE 1 57 1 714 1 Sofiware Interface cocidas 1 57 14 7 4 2 Example 5 eno ert er gr et oce ein ee A ERE dee nuces 1 58 1 7 7 5 Interrupt 73 PUSHALL_ INTE 1 58 1 7 7 5 Sofware Interface iii rere ern e d ete ttes 1 58 1 7 7 5 2 Example race rre LEE ee Dre AER e perse t aes d ene 1 58 1 7 7 6 Interrupt 74 POPALL INT secs ee cete e ee too ee yen der dde 1 58 1 7 7 6 1 Software Interface eee tre tete ritiene t reed 1 58 1 5 7 6 2 Example itr eee e geed retirees 1 59 1 7 7 7 Interrupt 77 HW SWAP REG Swap register bank 1 59 1 7 7 7 1 Software Interface aterert ieii 1 59 154156 EE een ege ee REAL 1 59 1 7 7 8 Interrupt 78 HW REST REG Restore register bank 1 60 1 7 7 8
123. ropriate Sets the global interrupt enable register OXCOOE to zero Initializes hardware software interrupt vectors Initializes arena information memory management Initializes hardware for serial EEPROM and UART Initializes software for LCP idle task and USB idle task Performs BOOT CONTROL see Section 1 3 3 Boot Control Performs SCAN INT if data at ROM address 0xC100 OxC3B6 Enters execution idle tasks and waits for interrupts Chapter 1 BIOS Interface Page 1 7 BIOS User s Manual 1 3 3 Boot Control Two pins GPIO 30 31 on the EZ Host and EZ OTG devices are used for boot control The boot control is used to configure the device for Host or peripheral operation and to select a communica tion port for connection to an external processor 1 3 3 1 SIE1 Host Peripheral USB Initialization GPIO 29 OTG ID pin is used to select either Host USB initialization or peripheral USB initializa tion 1 3 3 2 Co processor and Stand alone Boot Control EZ Host and EZ OTG devices can be used in two basic configurations stand alone mode and co processor mode In stand alone mode the chip is not connected to an external CPU of any kind Application specific firmware must be run on the internal processor One option for loading this code is to use an external EEPROM which is selected using the boot control pins In co processor mode the chip is connected to an external master via one of three possible inter faces Host Pro
124. rupt 32 SIE1 and interrupt 40 SIE2 All the regis ter saves and restores will be maintained by these ISRs When a SETUP packet is detected the Chapter 1 BIOS Interface Page 1 37 BIOS User s Manual BIOS will call these interrupts after clearing the interrupt status register Oxc090 for SIE1 and OxcObO for SIE2 For SIE1 the register R8 will point to the buffer at address 0x300 and R9 will point to 0x200 DEV1_EPO_CTL_REG For SIE2 the register R8 will point to the buffer at address 0x308 and R9 will point to 0x280 DEV2 EPO CTL REG These interrupts handle bmRequest value from 0 GET STATUS to 11 SET INTERFACE BIOS will send STALL for any other value in the bmRequest STALL will be set for any non supported commands Note BIOS will call SUSB1 STALL INT and SUSB2 STALL INT to send STALL to the USB Host Note These interrupts should only be used for EndpointO They will be called from inside the EndpointO ISR so all registers should be reserved 1 7 5 7 4 Software Interface Entry R8 0x300 for SIE1 0x308 for SIE2 R9 0x200 for SIE1 0x280 for SIE2 SIE buffers 1 and 2 ports A and C execute device requests at internal RAM addresses 0x0300 and 0x0308 respectively These memory locations contain the current device request structures for each SIE for example db bmRequest db bRequest dw wValue dw wIndex dw wLength Registers Usage RO R12 Return None Note If more data is to be received on endpoint
125. rupts after clearing the interrupt status register Oxc090 for SIE1 and OxcObO for SIE2 For SIE1 the register R8 will point to the buffer at address 0x300 and R9 will point to 0x200 DEV1 EPO CTL REG For SIE2 the register R8 will point to the buffer at address 0x308 and R9 will point to 0x280 DEV2 EPO CTL REG These interrupts cover the range of the bmRequest value from 0x40 to OxFF 1 7 5 10 1 Software Interface Entry R8 0x300 for SIE1 0x308 for SIE2 R9 0x200 for SIE1 0x280 for SIE2 SIE buffers 1 and 2 ports A and C execute device requests at internal RAM addresses 0x0300 and 0x0308 respectively These memory locations contain the current device request structures for each SIE for example db bmRequest db bRequest dw wValue dw wlndex dw wLength Registers Usage None Return None Note The SUSBx LOADER NT will be called if bmRequest OxFF If more OUT data is to be received on endpoint 0 calls to SUSBx RECEIVE INT should be made If data is to be sent calls to SUSBX SEND NT should be invoked This is at interrupt level you may use any registers but you should return promptly You must supply a routine for this if vendor commands are to be used Page 1 48 BIOS User s Manual v1 1 1 7 5 10 2 Example Example 10 Intercept SUSB1_VENDOR_INT vector All Software and Hardware initialization should be done here device request offsets bmRequest equ 0 bRequest equ 1 wValue equ 2 wIndex
126. s used for reading and writing EZ Host EZ OTG memory The mailbox channel is used for LCP commands and responses 5 1 2 Scope This document provides details on the HPI support software A basic understanding of the EZ Host or EZ OTG hardware and software architecture is assumed 5 2 Functional Requirements The HPI Transport exposes the Link Control Protocol via the HPI Hardware Interface The Trans port must be capable of receiving LCP commands from an external CPU and sending back responses via the mailbox The Transport must also allow asynchronous messages to be sent to the external CPU 5 3 Detailed Design See Figure 2 1 Link Control Protocol 5 3 1 HPI General Description 16 bit multiplexed address data interface with the following interface registers Chapter 5 HPI Transport Module Page 5 1 BIOS User s Manual Write Address Pointer Read Address Pointer Data Register Mailbox register Allows external processor to directly access the entire on chip memory by first loading either the Write Address Pointer or Read Address Pointer and then performing single or multiple write read to the data register The read write pointer auto increments during multiple read write accesses thus allowing a fast block mode transfer The external processor can write to the mailbox register and cause an internal interrupt in the on chip processor The on chip processor can write to the mailbox register and cause an external interrupt
127. se COMM_ACK This allows writing to INTERNAL memory only This command is not required for HPI commu nications since there is Direct Memory Access Note COMM MEM LEN specifies the number of words to transfer The BIOS will not check the valid range of INTERNAL memory If users want to access the external memory bus they should use the COMM WRITE XMEM However if the address range is not valid the INTER NAL memory might be corrupted COMM READ XMEM Action Read Memory Data Used COMM MEM ADDR COMM MEM LEN COMM LAST DATA Response COMM ACK This command handles e Memory Copy Memory is copied from COMM MEM ADDR to COMM LAST DATA where COMM MEM ADDR should be in the external memory space or it can be from 0x0000 OxFFFF and COMM LAST DATA must be in the internal memory i e 0x0000 Ox3FFF Data Transfers After copying data is transferred from COMM LAST DATA to the HSS SPI interface The purpose of this command is to allow reads from external memory or data transfers between external memory to internal memory the location where COMM MEM ADDR points to The COMM LAST DATA should point to the internal memory address and the COMM MEM LEN should be greater than zero Note COMM MEM LEN is the number of words to transfer Chapter 2 Link Control Protocol Firmware Page 2 7 BIOS User s Manual COMM _WRITE_XMEM Action Write Memory Data Used COMM_MEM_ADDR COMM_MEM_LEN COMM_LAST_DATA Response COMM_ACK This
128. seesene eene nennen nennen nnne nennen trennen 5 6 COMM WRITE CTRL REG via HPI A 5 7 COMM READ CTRL REG via HPI ssessssseeeeneeeene enne enne nnne 5 8 COMM READ XMEM criada idee een AAA deed 5 9 COMM WRITE XMEM via Hl 5 10 COMM EXEC INT via Hp 5 11 COMM RESET via SPI iios pr dote Ree epe Ee eter 6 4 COMM JUMP2CODE via SPI esee nennen enne 6 5 COMM CALL CODE via SPI sssssseesse eene nenne nnne borin nnne nene 6 6 COMM WRITE CTRL REG via GP 6 7 COMM READ CTRL REG via SPI sssssesseeene nennen nnnm rne 6 8 COMM WRITE MEM via SPI sssssssseeeneneeeeen nene nennen nennen nnne nen 6 9 COMM READ MEM via SPI sse nennen nennen rennen 6 10 COMM WRITE XMEM via SPI sssssseseeeeenennen nennen nennen nennen nnns 6 11 COMM READ XMEM via GP 6 12 pes EAS r 5 EH CYPRESS List of Figures Figure G0 COMM_EXEC_INT via Planea 6 13 Figure 7 1 COMM_RESET via HSS a tp aei indie Duaci te aea 7 4 Figure 7 2 COMM JUMP2CODE Via HB5 a o bias n Pet dist 7 5 Figure 7 3 DOMMSCALE CODE via EE 7 6 Figure 7 4 COMM OWRHIE e E 7 7 Figure 7 5 COMM READ CTRL REG via HSS EEN 7 8 Figure 7 6 COMM_WRITE_MEM via E 7 9 Figure 7 7 COMM_READ_MEM via HSS ca ia tet atre nsus tete 7 10 Figure 7 8 COMM_WRITE_XMEM via HSS coccion rones 7 11 Figure 7 9 COMM READ MEM via HS8 adeo ote etd a eds 7 12 Figure 7 10 COM
129. sg from HPISTS register Endpoint6 interrupt on SIE1msg SIE2msg from HPISTS register Endpoint interrupt on SIE1msg SIE2msg from HPISTS register Registers 0x144 0x148 bitO bit1 bit2 bit3 bit4 bit bit6 bit7 The structures and buffers given to this routine must not be modified until the data can be reused call is made Note The data in this structure will be changed This call should set up the pointers and return immediately The length of the buffer can be any size from 0x0000 32K The length must be less than or equal to the internal RAM internal ROM size The BIOS will partition the data into the user s defined payload and transfer across through the USB bus The call back will be called after the ACK and the length is zero For endpoints1 7 the address must be pointed to the internal RAM or internal ROM Any external memory bus will work but not recommended For endpointO the address can be either internal or external RAM or ROM When transferring from external RAM the BIOS will copy data into internal RAM before executing the transfer 1 7 5 8 2 Example Example 6 Sending IN transaction data from SIE1 port A USB endpoint 0 In response to a device request only data may be sent over endpointO during the data phase of a control transfer Three phases SETUP DATA and STATUS are required for endpointO Users can employ the same code below to replace the Vendor Command Class but it only illustrates h
130. shed then clears it to zero 3 4 2 TD SIE Mailbox Message There are two SIE mailboxes SIE1 s mailbox address is 0x144 and SIE2 s mailbox address is 0x148 After the completion of TD list the BIOS will send out the HUSB_TDListDone message to their respective SIE mailbox This message is bitmap Bit 12 is HUSB_TDListDone BIOS After the completion of TD list the BIOS will send the HUSB TDListDone message to HCD via HPI SIE mailbox write to address 0x144 0x148 Page 3 8 BIOS User s Manual v1 1 e HCD Upon receiving the HUSB_TDListDone message HCD will begin to check the fin ished TD and load the next TD list The following shows how HCD receives an HUSB_TDListDone message When the HPI mailbox interrupt is received check the HPISTS register If bit 4 of HPISTS is set read address 0x144 to get message If bit 5 of HPISTS is set read address 0x148 to get message If bit 12 of the message is set read the HUSB TDListDone message for the respective SIE 3 5 TD List Data Structure The TD is a 12 byte structure Table 3 1 TD List Data Structure TD Offset Name Function 0x00 01 BaseAddress Base Address of Data Buffer 0x02 03 Port Length Port Number Data Length 0x04 PID EP PID Endpoint 0x05 DevAdd Device Address 0x06 Control TD Control 0x07 Status Transaction Status 0x08 RetryCnt Retry Counter Transfer Type Active Flag 0x09 Residue Residue 0x0A 0B NextTDPointer Pointer to Next TD 3 5 1 BaseAdd
131. signal to be asserted which clears automatically upon a read from the mailbox The external processor access to on chip memory is re synchronized with the internal 48MHz clock and requires a successful arbitration of the on chip internal memory bus The HPI is the highest priority bus contender The maximum data transfer rate on the HPI port is 48MHz 6 8MHz 16 0 MByte sec using 16 bit data The 2 bit port address decodes to four port registers 00 HPIDATA data register 10 HPIADDR memory access address 01 HPIMAILBOX mailbox register 11 HPISTS HPI port status 5 3 2 HPI Signal Description The HPI port of the EZ Host EZ OTG device uses GPIO pins shared by the DMA and IDE sub systems To put the EZ Host EZ OTG device into HPI mode use the GPIO configuration register 0xC01C The HPI mode allows an external host processor to directly read write to EZ Host EZ OTG internal memory The HPI port consists of the following I O signals HPI_Addr 1 0 2 bit port address HPI_Data 15 0 16 bit port data HPI_n WRITE port writes pulse HPI_NREAD port read pulse HPI INTR mailbox interrupts from EZ Host EZ OTG to System Host Page 5 2 BIOS User s Manual v1 1 EZ Host OTG chip incoming HPI port mailbox interrupt HPI_nCS chi incoming select mailbox register HPI_A 1 0 address Host Processor HPI_nWR outgoing mailbox lt write register HPI_
132. supported as follows Host must use the Read DEV_IOCTL for endpointO SCAN_INT command 07 Page 1 52 BIOS User s Manual v1 1 bmRequest 0Oxc0 Read type Vendor Command Class bRequest Oxff debugger command wValue 7 signature command opcode 7 wIndex Memory Address pointer to 0x0000 0xFFFF address wLength 2 4K 2 byte to 4K byte Host must use the Write DEV_IOCTL for endpointO SCAN INT commands from 0 6 8 9 bmRequest 0x40 Read type Vendor Command Class bRequest Oxff debugger command wValue OxCMD Signature command opcode 0 6 8 9 windex 0 use data block as the header data wLength 2 4K 2 byte to 4K byte Data Block should contains Signature Header Data Signature Header Data etc See SCAN INT for more information The 4K max size is limited by the Windows OS BIOS support up to 64Kbyte 1 7 5 12 2 Example Sample code for Host interface to the debugger This code interface through the CyUsbgen SYS WDM driver typedef struct WORD sig signature WORD len length BYTE btype opcode WORD addr address theader pHdr typedef struct _IO SETUP PKG UCHAR bmRequest UCHAR bRequest USHORT wValue USHORT wIndex USHORT wLength PBYTE ioBuff SETUP PKG PSETUP PKG BOOL uXfer BYTE bLoad void pPre WORD wPreLen void pData WORD wLen void pRdData WORD RdLen DWORD cbRet DevReq devreq char pdev BOOL RetVal TRUE
133. t System EOT End Of Transfer EZ Host The EZ Host and EZ OTG are Cypress USB Controllers that provides multiple EZ OTG functions on a single chip HCD Host Controller Driver HPI Host Processor Interface HSS High Speed Serial port LCP Link Control Protocol Port CMD LCP Command sent over a Slave Transport PLL Phase Lock Loop PWM Pulse Width Modulation RO R15 CY16 Registers RO R7 Data registers or general purpose registers R8 R14 Address Data registers or general purpose registers R15 Stack pointer register RAM Random Access Memory R W Read Write SPI Serial Peripheral Interface System CPU An external CPU acting as a master to EZ Host or EZ OTG TD Transfer Descriptor host mode USB Universal Serial Bus WDT Watch Dog Timer Appendix A BIOS User s Manual BIOS User s Manual v1 1 Appendix B References CY16_HW CY16 Hardware Specification USB Specification 2 0 CY16_TOOLS CY16 Software Tools EZ Host EZ OTG BIOS bugs Tracking and Solving Issues Appendix B BIOS User s Manual B 4 BIOS User s Manual v1 1 W M Jj 7 CYPRESS E Appendix C Revision History Name and Version Rev 0 0 Appendix C Date Issue Comments 5 BIOS User s Manual C 6 BIOS User s Manual v1 1
134. t to a USB host to complete multiple IN transactions They will break up user data into multiple payloads that are defined by the endpoint descriptors and the call back routine will be invoked or the message interrupt will be set after the transfer is completed These interrupts provide support for both stand alone mode and co processor modes In stand alone mode the user should provide a call back routine to check for the completion In co proces sor mode a message interrupt will be set in either register 0x144 for SIE1 and register 0x148 for SIE2 Chapter 1 BIOS Interface Page 1 39 BIOS User s Manual 1 7 5 8 1 Software Interface Each interrupt is passed an 8 byte control header block structure to control the transmission of data over the USB bus and an endpoint number A device descriptor must be setup prior this call For endpoint1 7 the Interface Endpoint descriptors must be setup and configured The interrupts should not be called after SUSBx_DELTA_CONFIG_INT If the interrupts are called before they are configured they will not work The call back subroutine should not use an sti or cli instruction Normally the subroutine will notify the application that the task has completed or that additional buffers are to be sent When using these interrupts in co processor mode via the HPI interface disable the interrupts uDone1 and uDone2 in the HPI SIE IE register at address 0x142 i e both bits should be cleared N
135. the CY16 processor Cypress provides a complete development system including a GUI based Integrated Development Environment Assembler C Compiler Linker Debugger GDB and Binary Tools For detailed information on the capabilities and use of this system please refer to the documentation accompanying the tools This develop ment system may be used for creation of new application specific firmware or to develop code that will replace or supplement functionality provided by the BIOS 1 3 BIOS Overview The BIOS consists mostly of interrupt service routines and a main start up routine Other routines are typically not available to the user Users should only use software vectors and not call arbitrary BIOS functions since these may move in newer versions of the BIOS Page 1 2 BIOS User s Manual v1 1 Figure 1 1 illustrates various BIOS layers and components BOOT Layer Functional Layer SW INT Layer EEPRO STARTUP bi aa SC SW ISR s HUSB Services HW INT Layer HW Interrupt or INT Command Chapter 1 BIOS Interface ISR Groups TIMERS GPIO UART HSS SPI IDE HW HPI Interrupt Vector Table SIE1 Host SIE1 Slave SIE2 Host SIE2 Slave SIE1 OTG SIE1 EPO EP7 SIE2 EPO EP7 Figure HW ISR s ISR Groups p a 1 1 Overview sw Interrupt Vector Table DEBUG EEPROM PUSH POP ALLOC FREE REG SWAP Page 1 3
136. the USB port if SIEs are set in the Host mode However the debugger for the UART will be available Note This interrupt will be called by the user and also inside the USB_RESET When this subrou tine is called inside the USB_RESET it will remember the user s defined speed 1 7 5 1 1 Software Interface Entry R1 Speed 0 for Full Speed 1 for Low Speed R2 SIE Number 1 for SIE1 and 2 for SIE2 Registers Usage R8 R10 R12 R1 R4 Return None 1 7 5 1 2 Example Example 3 Initialize SIE1 for a device with 1 endpoint Full speed GIEL mov rl O 0 for full speed 1 for low mov r2 1 SIE1 int SUSB_INIT_INT Low speed SIE1 mov r1 1 low speed mov r2 1 SIE1 int SUSB INIT INT Chapter 1 BIOS Interface Page 1 31 BIOS User s Manual Full speed SIE2 mov ri1 0 full speed mov 12 2 SIE2 int SUSB INIT INT Full speed SIE2 mov r1 1 low Speed mov 12 2 SIE2 int SUSB INIT INT 1 7 5 2 Interrupt 90 106 SUSB1 DEVICE DESCRIPTOR VEC SUSB2 DEVICE DESCRIPTOR VEC These interrupt locations contains the pointer to the default Cypress Device Descriptor refer to USB Specification version 2 0 for details A pointer to a different device descriptor may be written here if necessary It is important to note that changing the descriptor will not have any effect unless the associated module has been previously enabled either by the BIOS or by the program via the SUSB INIT INT This must be done for low speed operat
137. the b wait acon state and the result will be either in the b host or the b peripheral state A For a complete understanding on how the a_idle and b_idle state machines work refer to the OTG supplement to the USB 2 0 specification for more details 1 7 3 3 Interrupt 88 OTG Descriptor The BIOS uses this interrupt as the variable data pointer for the OTG descriptor At power up the BIOS sets this location to zero i e BIOS will send STALL for SET_FEATURE command of requesting SRP HNP When this location contains the OTG descriptor the BIOS returns an ACK on the SET_FEATURE of SRP HNP command In co processor mode this location should be set before making a call to the SUSB_INIT_INT In stand alone mode it must be overridden by either serial EEPROM or external ROM if users wish to enable the OTG feature Example of the OTG descriptor otg desc db 3 len 3 db 9 type OTG db 3 HNP SRP supported To over ride the otg_desc do mov 88 2 otg desc Note The OTG descriptor should be part of the configuartion descriptor Chapter 1 BIOS Interface Page 1 27 BIOS User s Manual 1 7 3 4 Interrupt 84 OTG_SRP_INT This interrupt will do the SRP The BIOS will pulse the data bus either D or D depending on the user s speed and VBUS Before calling this function both VBUS and D D should be turned off If the OTG_ID pin changes from high to low during the pulsing of VBUS and or D D the function will exit and return
138. the default control transfer processor Chapter 4 Slave Support Module Firmware Page 4 7 BIOS User s Manual Endpoint Generic Endpoint Support Send Receive Data Endpoint ISR Registers Frame Data Block Ptr Count Next Frame Ptr Callback Ptr ane X N Finish Transfer Figure 4 5 Generic Endpoint Support Architecture 4 3 2 3 Data Structures The following table describes the structures and their relationships where dw is 16 bits Table 4 3 Generic Frame 1 Send Receive Request Used by Generic Endpoint Processing Name Size Description Link dw Pointer to the next Generic Frame in active frame list The current design requires this to be initial ized with zero BufferBase dw Pointer to a buffer BufferLen dw Length of buffer in bytes Callback dw Pointer to function to call when the send receive transaction has completed Page 4 8 BIOS User s Manual v1 1 4 3 2 4 Code Structure The code structure parallels the previous architecture diagram There are ISR and user entry points into the code provided via software interrupts The ISR code consists of two classes of device and endpoint service routines The endpoint service routines serve as entry points that setup subsequent calls to the Generic Endpoint routine common to all endpoints Since endpoint 0 is the default endpoint only one with messag
139. trol transfers and transfers on any other endpoint This special hook a finish control transfer software interrupt is used to reset the state of the control transfer processor at the end of a control transfer s data stage It is the responsibility of the generic endpoint processing functionality to abstract USB transfer management in a manner which simplifies its utilization for applications and module developers In doing so it will provide a means to queue multiple transactions and notify the caller upon com pletion Larger data transfers of data sequential in memory shall appear to users of this functional ity as a single transaction while the transfer is divided into smaller USB transactions across the endpoint Upon transfer completion a caller specified call back routine will be called The programmatic interface exposed by aforementioned functionality has other benefits aside from override able modularity It provides a set of utilities that can simplify applications development Similarly it also cleanly exposes itself to other internal modules an example would be an HPI HSS command processor Chapter 4 Slave Support Module Firmware Page 4 3 BIOS User s Manual 4 3 Detailed Design The architecture sequence code layout and data structure for EndpointO and Generic Endpoint Processing will be discussed State class and sequence diagrams will be utilized to detail desired behavior Decision call trees and or class diagrams will
140. ubsidiaries affili ates and distributors harmless against all claims costs damages expenses and rea sonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unautho rized use even if such claim alleges that Cypress Semiconductor was negligent regard ing the design or manufacture of the product The acceptance of this document will be con strued as an acceptance of the foregoing con ditions BIOS User s Manual v1 1 Copyright 2003 Cypress Semiconductor Corporation All rights reserved MA CYPRESS g Table of Contents Chapter 1 BIOS Interface Wed nice ere ET EE 1 1 Wels e dE 1 1 1 1 2 General NOt6S 1 2 rite ie 1 1 1 2 Development Utilities oe aie a eerte dee el ae od ee deo Eae cua eodera Te qeu 1 2 1 2 1 GNU Development Tools from RedHat seen eene 1 2 1 3 BIOS CEET eh Lee toc 1 2 1 321 CY 16 Memory Map i iiio tio pe rti te Ee feed ee eoi ee ii eee bee 1 4 1 3 2 BIOS Initialization Process A 1 7 1 3 3 BOO CONTO e M 1 8 1 3 3 1 SIE1 Host Peripheral USB Initialization see 1 8 1 3 3 2 Co processor and Stand alone Boot Control 1 8 1 4 Link Control Protocol Eege eege eege Gegend EEN 1 9 1 4 1 LCP Overview for Host Processor Interface HPI esse 1 9 1 4 1 1 Programming COverniew cesses seceeeeeeeseceeaeeeeeesenaeeeeeesee
141. uo deg EENS E E 3 9 3 5 1 BaseAddress WORD 0x00 01 coocooocccccccconocccccnconononcnncnnnnnnnnncnonnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnns 3 9 3 5 2 Port Length WORD 0x02 03 sse nennen nennen nennen tenens 3 10 3 5 3 PID EP BY TE 0X04 EE 3 11 3 5 4 DeVAdd BY TE 0x05 rie iet ED ree Edere es 3 12 3 5 5 Gontrol BYTE OX06 oe ei Ue ER E EREHRS e E e tee oe Lee R ee EA 3 12 33516 Status BYTE 0X07 niece een EU CORR SE RE 3 13 3 5 7 RetryCnt BY TE TEE 3 14 Table of Contents CYPRESS Table of Contents 3 5 8 Residue BY TE UND ege esercito ge peser EE Bo deed pe dO E decre nte Ad 3 15 3 5 9 NextTDPointer WORD OO D I 3 15 3 0 Error Flandlingi ecce ioter cao ll ira 3 16 3 7 Schedule Bus Transaction Times 3 18 3 97 Detail Design irte em e Lo eai eee as t ated ee tee 3 19 3 8 1 HUSB SIEX INIT INIT eege tenente dre tete iode e dede nie ecce teria 3 19 3 8 1 1 Software Interface n ier etate p ite rp danas Le eu ie tbe de cate 3 19 3 0 1 2 Example e eed poc rte Ey E E ee 3 19 3 8 2 H SBE RESET INT eintreten NA D en Pa oe esee 3 19 3 8 2 1 Software Interface 3 19 KR E 3 20 3 8 2 3 EE 3 20 Chapter 4 Slave Support Module Firmware 431 Introd ctiori n ais isis Veena dieat iced 4 1 AVA e MERE 4 1 4 1 2 e 4 1 4 2 Functional Requirements c cccceceeceecceececeeeeeeeeeeeeceeeeeeeeeeeaaeeeeeeecaaeeeeeeseaeaeeeeeeecequeeseesenieaeess 4 1 4 3 Detailed DE
142. upt 73 PUSHALL_INT This Interrupt is used to save all registers from RO R14 to the stack This interrupt will execute fourteen PUSH instructions and return 1 7 7 5 1 Software Interface Entry None Registers Usage none Return None R15 will be decremented by 32 1 7 7 5 2 Example Example 15 To save all the working registers inside the interrupt service subroutine PUSHALL INT EQU 73 POPALL INTEQU 74 endpoint1_int INT PUSHALL INT save all registers process endpoint 1 interrupt INT POPALL INT restore all registers sti re enable int ret return from interrupt service subroutine 1 7 7 6 Interrupt 74 POPALL_INT This Interrupt is used to restore all the registers from RO R14 to the stack that had been previ ously saved by the interrupt 73 This interrupt will execute fourteen POP instructions and return 1 7 7 6 1 Software Interface Entry None Registers Usage Restore all the registers from RO R14 to previous interrupt PUSHALL_INT Return None R15 will be incremented by 32 Page 1 58 BIOS User s Manual v1 1 1 7 7 6 2 Example See Example 15 To save all the working registers inside the interrupt service subroutine Note Interrupt 73 and Interrupt 74 should be used in pairs 1 7 7 7 Interrupt 77 HW_SWAP_REG Swap register bank This Interrupt is designed to save CPU flags and all registers including R15 using a second regis ter bank only in the interrupt context It
143. ure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 WEIEREN 1 3 CY 16 Memory Map estaa sad 1 6 2 wire Serial for up to 256 byte up to 2 KByte Connection oo eeeeeeeeeeeeeneeeeeeeeees 1 66 2 wire Serial from 4K up to 64 KByte Connection ssee e 1 66 Link Control Protocol i eroe ciet ede A a ea ee 2 2 Co processor Mode titi tua ee RU og etude toss Ponit 3 1 Block Diagram of USB Host BIOS sse eene nenne enne 3 3 Flow Chart of USB Transfer miccional id REENEN 3 5 Time Domain A 3 6 End Of Transfer Point gebeten ern ete ld e gases 3 8 Error Handling Interface EE 3 17 Flow chart of HUSB RESET INTE 3 20 Override ability Dependency Stack 4 3 Control Transfer Handler State Diagram essem een 4 4 Control Transfer Processing Architecture sssssssseeeeeem eme 4 5 Generic Endpoint Support Sequence Diagram sssssssssssseeseeene 4 7 Generic Endpoint Support Architecture ooooooccccccnncccccccccccnononccnconononccnnnnanoncnnnnnnnnn conc nnnannnns 4 8 Endpoint Processing Code Flow sees 4 10 Se EE EARCH UE 5 3 COMM RESET VIA EPI i i riui s NEE Ree o eee med 5 5 COMM JUMP2CODE via HPI essseee eene enne nnne 5 5 COMM CALL CODE via HPI sssssssss
144. urn 1 5 1 BIOS Hardware Interrupt Usage Most hardware interrupts are used by the BIOS The user can override these ISRs but care must be taken 1 5 1 1 Interrupts Not Used by the BIOS The following interrupts are not used by the BIOS and can be utilized by the developer Table 1 5 Interrupts not used by the BIOS Interrupt Number 0 1 2 3 8 15 18 26 Interrupt Name Notes TimerO Timer1 GPIO IRQO and GPIO IRQ1 IDE DMA Done OTG ID VBUS Valid 1 SIE1 Host Insert Remove SIE2 Host Insert Remove NOTE Interrupt 15 is available to implement USB On The Go support Chapter 1 BIOS Interface Page 1 15 BIOS User s Manual 1 5 1 2 Interrupts Used by the BIOS The following interrupts are used by the BIOS Interrupt Number 4 20 21 24 25 Page 1 16 Table 1 6 Hardware Interrupt Table Interrupt Name UART Tx UART Rx HSS DMA Done HSS Rx Full Reserved HPI Mailbox TX Empty HPI Mailbox RX Full SPI Tx SPI Rx SPI DMA Done SIE1 Host Done SIE1 Host SOF SIE1 Peripheral Reset SIE1 Peripheral SOF SIE2 Host Done SIE2 Host SOF Notes ISR transmits characters from the software 16 byte FIFO ote Overriding effects tool support over UART z ISR receives characters and store into the software 16 byte FIFO Note Overriding effects tool support over UART Used by HSS Transport to support LCP Used by HSS Transport to support LCP Reserved for future HW ISR Used
145. value other than OxFF Chapter 6 SPI Transport Module Firmware Page 6 3 BIOS User s Manual 6 3 8 SPI TRANSFER DIAGRAMS FOR LCP 6 3 8 1 COMM RESET via SPI COMM RESET GA COMM_RESET 15 8 XXh Send 8 Byte CMD Packet XXh XXh XXh XXh XXh Poll for non OxFF Wait OxFF M_ACK 7 0 Get _ Response COM e 45 Rem Response 7 COMM_ACK Figure 6 1 COMM_RESET via SPI Page 6 4 BIOS User s Manual v1 1 6 3 8 2 COMM_JUMP2CODE via SPI COMM_JUMP2CODE 7 0 COMM JUMP2CODE 15 8 COMM CODE appr 7 0 COMM Send 8 Byte CMD Packet Poll for non OxFF Get 2 Bytes of Jump After Response Send Response Figure 6 2 COMM JUMP2CODE via SPI VA Notes The code should exist in the memory space that COMM_CODE_ADDR will point to Ifthe code jumped to does not return then the ACK will not be sent Chapter 6 SPI Transport Module Firmware Page 6 5 BIOS User s Manual 6 3 8 3 COMM_CALL_CODE via SPI COMM CALL oner COMM CALL one ns COMM CODE Ap 7 0 Send 8 Byte COMM CMD Packet CODE ADDR 15 8 XXh XXh XXh XXh Poll for non OxFF n Wait OxFF Call Code Then Send Get Response 2 Bytes of Response Figure 6 3 COMM_CALL_CODE via SPI Nia Notes The code should exist in the memory space that COMM_CODE_ADDR will point to If the code jumped to does not return then the ACK will not be sent Page 6 6
146. wCallBack USB CMD USB CMD ep3 ctl short R0 R1 R8 define ep3 ctl ptr define image ptr define image size define mbx_msgl RO RI 2 R8 ep3_ctl ptr ep3 ctl wNextLink ep3 ctl wAddress ep3 ctl wLength ep3 ctl wCallBack 0 HPI Buff Write WORD amp ep3 ctl lication note 0x1000 0x1008 320 0x144 0 image ptr image size 0 4 Store buffer into internal RAM HPI Exec int COMM EXEC INT SUSB1 RECEIVE INT RO R1 R8 Note The BIOS also sets the mbx msg1 for both stand alone and co processor modes To read the mbx_msg1 value the following code can be utilized short mbx copied if mbx_copied HPI Read mbx msgl HPI Write mbx msg1 0 Chapter 1 BIOS Interface 120 allow BIOS to update the new message Page 1 47 BIOS User s Manual 1 7 5 10 Interrupt 85 101 SUSB1_VENDOR_INT SUSB2_VENDOR_INT For these interrupts the BIOS will return STALL as the default The Interrupts implement the USB vendor interface based on Chapter 9 of the USB Specification version 2 0 These interrupts will be called whenever bit 6 of a bmRequest byte is set omRequest amp 0x40 0x40 These interrupts must be replaced for any extension of the application These interrupts will be called inside interrupt 32 SIE1 and interrupt 40 SIE2 All the register saves and restores will be maintained by these ISRs When a SETUP packet is detected the BIOS will call these inter
147. y If there is SRAM connected to this BUS it will allocate this RAM to become part of the BIOS memory space If there is no SRAM con nected to the bus it will result in an 8 bit setting in the register OxCO3A If external ROM is mapped to the address 0xC100 which has a valid signatures scan i e OxC3B6 or OxCB36 the BIOS will allow a boot up from the external ROM code BIOS can also auto detect booting up from an 8 bit external ROM or 16 bit external ROM using the special scan signatures at location 0xC100 The BIOS will not setup the external memory space The decision to connect either SRAM or ROM is left to the user The EZ Host EZ OTG memory space is byte addressable Table 1 1 shows how memory is divided 1k 1024 bytes Page 1 4 BIOS User s Manual v1 1 Table 1 1 Memory Map Function Address Memory size Note Internal RAM 0x0000 Ox3FFF 16 KBytes Hardware Interrupts 0x0000 0x007F Software Interrupts 0x0080 Ox00FF Primary Register Bank 0x0100 0x010F Swapped Register Bank 0x0120 0x013F HPI Interrupt and Mailbox 0x0140 0x0148 LCP CMD Processor Variables 0x014A 0x01FF USB Control Registers 0x0200 0x02FF Slave Setup Packet 0x0300 0x030F BIOS Stack 0x0310 OxO3FF USB Slave and OTG Variables 0x0400 0x04A2 User Code Data Space Internal RAM 0x04A4 Ox3FFF External RAM 0x4000 Ox7FFF 16 KBytes 3 Extended Page 1 0x8000 Ox9FFF 8 KBytes 1 2 3 DRAM SRAM ROM Extended Page 2 Ox

BIOS User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents