SATA PHY TxRx Impedance MOI - Agilent 86100C
Contents
1. Logo Working Group Appendix A General Resource Requirements Purpose To define the hardware software requirements for performing the tests defined in this document References None Last Modification May 29 2008 Discussion Introduction In order to perform receiver jitter tolerance testing on SATA transceivers several pieces of equipment are needed The primary functional components are as follows mm Function vice Model Stressed Signal Generates jittered stressed test Agilent N4903 J BERT v4 91 FW or newer Generator SSG signal or Agilent 81133A one channel or 81134A two channels Pattern Generator plus external DJ RI modulation sources see below RI Noise Source Used RJ modulation source Agilent 81150A when using 81134A as SSG or NoiseCom PNG 7110 Equivalent models include UFX PNG 7107 08 09 10 12 and NC 6107 08 09 10 12 Di Sine Source Used as DI modulation source Agilent 81150A or 33250A when using 81134A as SSG or 4432B signal generator BIST Configuration Used to enable BIST L PC running Ulink DriveMaster software Tool loopback mode of PUT Jitter Measurement Used to verify calibrate SSG Agilent Infiniium DSO81304A 13GHz Real Time Device MD output DSO Recommended Agilent 86100C w 54754A or Agilent N4903 J BERT may be used for informative purposes only 3 Way 50 50 Used to combine DJ RJ Agilent 11636B or equivalent Resisti2. Note that it is also possible after pressing ENTER to simply pres 2 buttons to increment and decrement the noise amplitude by fractional ste litter D 5 Adjusting the Determinist e To adjust the Deterministic Jitter via the 33250A Function Arbitrary Waveform Generator turn on the output in pressing the Output button at the front panel Select a sinusoidal waveform by pressing the Sine button at the front panel Use the Frequency hotkey to set the required frequency Calibrate the deterministic jitter by adjusting the Amplitude and observing the jitter reading on the JMD SATA IO Logo Working Group 30 Agilent SATA RSG MOI Serial Logo Working Group Appendix Using the Agilent N4219B Serial ATA Probe as the Frame Error Detector Purpose To define a procedure for initial setup configuration and verification of the SATA Probe for the purpose of being used as the Frame Error Detector References 1 Serial ATA Interoperability Program Revision 1 2 Unified Test Document Section 2 16 Last Modification November 13 2006 Discussion Prior to running the actual stressed receiver tests it is necessary to perform several steps to configure and verify proper operation of the Frame Error Detector One possible implementation of a Frame Error Detector utilizes the Agilent N4219B SATA Probe in conjunction with an appropriate Logic Analyzer Probe Setup and Configuration 1 Connect the N4219B
3. 1100 1100 1100 1100 1100 1100 1100 11007 To create Framed COMP Use Agilent Pattern Loading Tool to upload pattern file to 81134A Configure the initial data amplitude by going to the Channel tab and under Channel 1 orange screen enter an Offset of OmV and Amplitude of 405 375mV Genli 2i or 270 310mV GenIm 2m Additionally select Data Normal and NRZ under the Channel 1 settings Select the delay control input to 250ps Levels Normal gt Select Pulse Pattern Mode in the upper part of the display and select the required frequency Enter 1 500000000GHz for RSG 01 and 3 000000000GHz for RSG 02 Tum on the transmitter by pressing the two Output buttons for the differential signal on the front panel Under the AUX screen of the 81134A set all values as shown in Figure F 2 below Figure F 2 81134A Aux Screen Showing Proper Test Settings Adjusting the Qutput Amplitude To adjust the output amplitude on the 81134A go to the Channel tab and under the settings for Channel 1 the orange screen enter the amplitude value under the Ampl field SATA IO Logo Working Group 29 Agilent SATA RSG MOI Serial Logo Working Group djusting the Random Jitter RJ To adjust the RJ simply increase decrease the output of the Noisecom PNG 7110 Programmable Noise Generator by pressing the NOISE ATTEN button entering a numeric value using the keypad then pressing ENTER the 1 INC and 2 DEC
4. fangs When you have it isolated on the screen it should look like Figure B 2 below Fi Cond Sip Meare tap eeu Figure B 2 Isolated Lone 1 and Lone 0 Bits Once you have the Lone 1 isolated we will now do a histogram measurement to determine the amplitude Zoom in to 200ps div Then go to Analyze gt Histogram to open the histogram configuration screen Check the Enable Histogram box Set Histogram Source to Waveform Set Orientation to Vertical Then hit Close SATA IO Logo Working Group 1 Agilent SATA RSG MOI Serial Logo Working Group Now manually drag the markers on the screen to isolate the amplitude of the Lone 1 bit Move the two vertical markers i e the horizontal bars to just above and below the top of the bit e For the horizontal markers ie the vertical bars we must position them at approximately the 40 and 60 UI width points to include only those samples in the histogram To do this we must roughly measure the width of the bit Use the zero crossing points to do this noting the width of the spacing between the zero crossings in terms of divisions Manually position the histogram cursors at the 40 and 60 time points When you are finished your display should resemble the image shown in Figure B 3 below E Figure B 3 Amplitude Histogram Measurement of the Lone 1 Bit e Adjust the
5. Gen 1 1 5Gb s Receiver Jitter Tolerance Test E configure ur DUT DUT Name sata Seri Number DUT Type SpeedClhes Desciptor Test LUser Blame User Coment Vii Stat Dete 16 5 2007 123037 PM Cenclance Mode Las TestDate 6572007 12 30 07 PM Evoer Mode Precision ID FegserDUT Press Configure DUT or Change Select 1 5 GBit s for Speed Class and pres Now proceed as described in 1 2 Test RSG Register DUT and SATA IO Logo Working Group 45 Agilent SATA RSG MOI Serial Logo Working Group Appendix Using the Agilent 81133 4A Pulse Pattern Generator and 81150A Pulse Function Arbitrary Noise Generator as the Stressed Signal Generator SSG Informative Purpose To document the necessary setup and configuration procedures required when using the Agilent 81133A or 81134A based system as the Stressed Signal Generator with the 81150A Pulse Function Arbitrary Noise Generator Note this appendix is classified as informative under the 11 3 Interop Program however it is intended to become normative under the 1 4 Program References 1 Serial ATA Interoperability Program Revision 1 3 Unified Test Document Section 2 16 Last Modification February 1 2008 Discussion There are multiple suitable options available for generating the stressing signal required for performing SATA Receiver Tolerance testing One
6. Performing this measurement requires isolating these bits on the scope so that the amplitude of only those bits can be measured To do this we will use a reference signal from the SSG which is synchronized to the start of the Framed COMP pattern as a trigger reference to trigger the scope The delay can then be adjusted to isolate the desired bits perform the amplitude measurement and adjust accordingly This procedure assumes that the SSG possesses a trigger out beginning of the pattern For details regarding particular SSG 81134A of this MOL which can output a rising edge at the refer to Appendices E J BERT and F First we will set up and connect the hardware Connect the Trigger Out signal of the SSG to the Channel 4 input of the DSO e Using the diagram in Appendix A Figure 1 as a guide configure the system so that the SSG is transmitting through the switches and into the DSO which should be connected to the ports of the uppermost switch Load the Framed COMP pattern into the SSG and set the initial amplitude See E 2 for J BERT and F 2 for 81134A SATA IO Logo Working Group 14 Agilent SATA RSG MOI Serial Logo Working Group Next configure the DSO Assuming the DSO has been properly deskewed press Default Setup to reset the DSO Connect the TX and TX outputs of the SSG to Channels 1 and 3 of the DSO respectively the DSO create a math waveform
7. 1 on Function 4 for the differential signal by going to Analyze gt Math to set up the function Select the f4 function click the Display On checkbox so it is selected then select Subtract in the Operator menu then select Channel 1 for Source 1 and Channel 3 for Source 2 Click Close then manually turn off the individual Channels 1 and 3 using the front panel hard buttons so that only the math waveform remains on the screen On the front panel trigger setup of the DSO set Trigger Mode to Edge Source to and Slope to Positive Set the trigger level to OmV using the front panel knob Turn the Channel 4 display ON using the front panel 4 button Using the front panel Vertical Gain knobs scale Channels 1 and 3 so they span as much of the screen as possible Keep the same setting for both channels Then turn both channel displays OFF using the front panel 1 and 3 buttons You should now see the rising edge trigger pulse on Channel 4 and the differential math waveform Once you have verified that you have a stable trigger on CH4 turn the CH4 display OFF using ihe front panel button e the scope s Horizontal setting to 2ns div Then using the Horizontal Delay knob on the front panel scroll through the waveform until you see the Lone 1 pattern shown below Note you may have to scroll for a while until you see it It is a 00001000 pattern followed by 110 110 Look for the lone spike followed by two
8. 2008 Feb 10 Version 0 90 MINOR UPDATE FOLLOWING FEB 8 LOGO WG REVIEW Andy Baldman UNH IOL Appendix A Added note to bottom of Table 1 denoting current status of 81150 generator as informative 2008 Feb 07 Version 0 85 MAJOR UPDATE TO SUPPORT REVISION 1 3 INTEROP PROGRAM Andy Baldman UNH IOL Entire Document Updated all UTD references to point to r1 3 UTD Entire Document Updated all spec references to point to SATA v2 6 RSG 01 and RSG 02 Added 5 2 DJ test case to procedure Appendix A Added Agilent 81150A DJ RJ Signal Generator to Table A 1 Appendix A Added Agilent N4915A Serial Bus Switches to Table A 1 Appendix A Added CHS TF eSATA NE ZP fixture to Table A 1 Appendix A Updated Figure 1 to show new setup using NA915A Serial Bus Switches Appendix A Modified Figure A 2 to make RJ DJ sources generic Appendix A Replaced A 3 and Figure A 3 cal setup diagram with modified Valiframe setup Appendix A Replaced all references to power splitters with Serial Bus Switches Appendix B Changed wording in B 2 to point to Figure 1 for setup Appendix B Added gen1m 2m levels to B 2 amplitude calibration procedure Appendix B Changed B S jitter text to indicate inclusion of m level PUTS Appendix B Added SMHz to B 7 list of DJ frequencies Appendix C Filled out C 5 previously TBD with TJ DJ measurement procedure Appendix C Added 5MHz to C 7 list of DJ frequencies Appendix D Added genIn 2m levels to D 2 and D 7 App
9. JMD d Figure K 4 Agilent 81150A remote interface with sinusoidal waveform configuration for channel 2 shown SATA IO Logo Working Group 48 Agilent SATA RSG
10. PG Output Setup adjust the Vampt value until the measured amplitude reads the desired value as shown below oat Loge tevet pup v F polarny ener T7 ck Tarmnaton pee uem Figure E 2 J BERT Amplitude Setup Screen E 4 Adjusting the Random Jitter RJ To set the initial RJ output value of the go to Jitter gt Jitter Setup Start by selecting the master jitter Enable checkbox in the upper left corner of the screen Select the 200ps delay line and check only the purple Random checkbox Under the Random settings specify 12 8 mUI for the Amplitude rms value Make sure that the 10MHz high pass and 500MHz low pass filters are OFF The Amplitude value should read 179 2mUI Note that this is just below the desired output value of 180mUI SATA IO Logo Working Group 26 Agilent SATA RSG MOL Serial Logo Working Group men Figure E 3 J BERT Jitter Setup Screen RJ E 5 Adjusting the Deterministic Jitter DJ To adjust the Deterministic Jitter on the J BERT go to Jitter gt Jitter Setup as shown below and adjust the Amplitude and Frequency values as desired Figure E 4 J BERT Jitter Setup Screen DJ SATA IO Logo Working Group 27 Agilent SATA RSG MOI Serial Logo Working Group Appendix F Using the Agilent 81133 4A Pulse Pattern Generator as the Stressed Signal Generator SSG Purpose To document the various necessary setup and config
11. Vertical knobs on the front panel Zoom in to 10ps div using the Horizontal knob on the front panel e Invert the Channel 3 signal by going to Analyze gt Math and selecting function f3 Check the Display On checkbox and select Invert as the Operator and Channel 3 as Source 1 Turn Channel 3 OFF using the selector button on the front panel e Visually compare the zero crossing times between the Channel 1 and Function 3 waveforms and verify that the difference between them is less than 10ps ie one horizontal division e If the skew is more than 10ps the SMA cables from the SSG are the likely cause Try different cables or change one of the two in the pair and re measure the skew until the result is less than 10 B 5 Calibrate RJ to 0 180 UI at the Reference Plane To measure jitter using the DSO we will use the RJ DJ Setup Wizard to set up the instrument Goto Analyze gt Jitter then click the RJ DJ Setup Wizard button Click Next then Next again the Source to Function 4 Pattern Length to Arbitrary Click Next Click Next again to skip past the Measurement Setup screen Under the Clock Recovery screen set Constant Frequency 1 5 or 3 0Gb s and select Semi Automatic as before Click Next Click Next again to skip past the Thresholds screen the Acquisition screen you will specify sample rate and memory depth setting This should be 40GS s and 131Kpts for Gen Then click N
12. amplitude setting of the SSG so that the Mean histogram amplitude is 162 5mV Genli or 137 5mV Gen2i or 120mV GenIm 2m Record the SSG settings that produce the desired amplitude at the reference plane e Repeat the histogram amplitude measurement procedure for the Lone 0 bit and verify that the differential amplitude between the Lone 0 and Lone 1 bits is 325mV Genli or 275mV Gen2i or 240mV GenIm 2m B 3 Verify 100ps Rise Time at the Reference Plane e With the DSO still set up to display the differential waveform as Function 4 load the pattern into the SSG e Perform risetime measurement on the DSO by going to Measure gt Time gt Rise Time You should now see the risetime result at the bottom of the screen However note that this is the 10 90 risetime not 20 80 as defined by SATA To change the risetime algorithm right click anywhere in the risetime result area and select Change Thresholds Under the Thresholds pulldown menu select 20 50 80 of Top Base and click Close You should now see the correct 20 80 risetime value in the sult measurement 4 Verify that the Skew at the Reference Plane is Less Than 10ps e Press Default Setup to reinitialize the DSO SATA IO Logo Working Group 16 Agilent SATA RSG MOL Serial Logo Working Group Turn Channel 3 ON using the selector button on the front panel Adjust Channels 1 and 3 to 200m V div using the
13. option is to use a system built around the Agilent 81133 4A Pulse Pattern Generator as explained in Appendix F In Appendix the Agilent 33250 and a NoiseCom noise generator are used to generate the required jitter signals In this appendix these jitter sources will be replaced by the Agilent 81150A Pulse Function Arbitrary Noise Generator The procedures shown here use a dual channel configuration of the 81150A instrument However if it s desired to keep one of the jitter sources mentioned in Appendix F either one can be replaced by the 81150A in a single or dual channel configuration This appendix documents the necessary procedures for setting up and configuring the system for RSG testing Note these procedures are referenced by other procedures in this document K 1 General SSG Setup The general setup using the 81134A and 81150A is shown below To rest of Test Setup See Figure A 1 Figure K 1 Agilent 81134A Pulse and Pattern Generator Agilent 81150A Pulse Function Arbitrary Noise Generator SATA IO Logo Working Group 46 Agilent SATA RSG MOI Serial ATA Logo Working Group Follow steps F 1 through F 3 in Appendix In addition make sure to connect output Outl of the 81150A to the delay control input of the 81134A when using the 81150A to generate random noise and sinusoidal waveforms If only one of the jitter signal shall be generated replace the respective generator in the setup shown in Appendix F Adjusting the
14. you should see a TJ result for 1 12 in the result area Output Timing method Preferred method faster than building complete eye Go to Analysis gt Output Timing on the J BERT e Set optimum settings under Properties e Press Start to build a bathtub curve C 6 Add Sinus lal DJ to Create 450 UI TJ at the Reference Plane With the DJ and RJ modulation enabled repeat the Eye Diagram TJ measurement method described in 5 above C 7 Verification of SSG Output for Gen 3 0Gb s Rate The setup and calibration procedure for the stressed Gen2 3 0Gb s signal is identical to the procedure described above for the signal except that the bit rate must be set for 3 0Gb s and the amplitude must be set to the proper value for the given interface type see C 2 Repeat the Gen procedure to determine the proper Gen2 SSG amplitude and RJ settings as well as the DJ settings for the 5 10 33 and 62MHz jitter frequencies SATA IO Logo Working Group 19 Agilent SATA RSG Serial Logo Working Group Appendix D SSG Calibration Procedure using Agilent 86100C DCA J as the JMD Informative Purp define a procedure for verification and calibration of the stressed signal generator setup using the Agilent 86100C DCA J as the Jitter Measurement Device References 1 Serial ATA Interoperability Program Revision 1 3 Unified Test Document Section 2 16 Last Modification Feb
15. 40 Agilent SATA RSG MOI Serial Logo Working Group Microsoft Framework 2 0 Microsoft Excel 2003 or higher Agilent IO Libraries Suite 14 2 Agilent T amp M Programmers Toolkit Redistributable Package 1 1 On the Agilent 16900A Logic Analyzer this software must be installe VFAg1600AServer After installing Valiframe Valiframe Station Configuration should be called once the setup the different addresses of the instruments Surt Valiframe Station Configuration Configuration Wizard Step 1 Station Selection Mole prebere dites ro not be conect sara siron Dastote dion FE tote Dre Actis Sene T Press Next EZ YaliF rame Configuration Wizard Stop 2 Instrumont Configuration 7723 Adis Denton LL ve soie TEPPI TGR INSTR 911348 ple gerer ce generator tore E Dine CAPO 11680700 ll INSTA Fade Tester vulh ceti SPONTE Sne crust ite EL Sven TEPPIR ISO OION INSTA one saines weer E Dime STR Noe sourse uso germina rardan ie E Drine Logs Log der SATA poto oda 0 TEPPIR TSADIN tob INSTR Digi Sage ers ayes I emm co Offline Flags of J BERT and Signal Generator should be checked Offline flags for all other instruments should be unchecked The addresses of the instruments must be changed Pre
16. G 01 and RSG 02 tests N5990A is also referred to as Valiframe References None Last Modification June 05 2007 Discussion The Agilent N5990A 103 test automation software automates all manual steps listed under RSG 01 and RSG 02 in this document All calibrations and measurements follow the same proceedings 3 1 General Setup The Setup consists of following components Agilent 81134A as SSG Agilent 33250A or Agilent ESG model number as sine source for generating sinusoidal jitter NoiseCom noise source as listed above for generating random jitter Agilent 05080000 series oscilloscope as JMD Agilent 16800 series or 16900 series Logic Analyzer N4219BA as Frame Error Detector PC with Windows XP and N5990A Option 130 Software as Host PC Alternatively the following instruments are also supported Crescent Heart Software SATA Probe as Frame Error Detector Agilent JBERT The cabling is identical to the setup for the manual test procedure described before in this document The following diagram shows how to connect the instruments to the host PC Host PC N5990A SW mm LAN GPIB Figure J 1 Test Equipment Network Diagram J2 Installing and Configuring the Software Before installing the Agilent 5990 Test Automation Software Option 103 the following components should be installed on the Host PC Microsoft Framework 1 1 SATA IO Logo Working Group
17. H 2 below SATA IO Logo Working Group Agilent SATA RSG MOL Serial Logo Working Group ounters SATA II Control Application Host Squelch OF Speed Genz Squelch cr count 13 008 error on count 0 Encoding error count 75 Running disparity error count 3 Link level error count Frame count 401105 Frame CRC erreresunt 0 DWord ALIGN x7B4A4A08 Probe commnicaton Ok Device Squelch OF Speed Gen2 Squelch on count 82 OOB count 38 Encoding error count 13986 Running disparity error count 13967 Link level error count Frame count 466279 Frama CRC eror count 0 DWord XXX data x40AD 1503 Linkerrors E peste Probe serial number 8 Status Ok Reset counters Figure H 2 Counters Window The Frame Count and Frame CRC Error Count values are the most pertinent to the RSG test procedure Making sure the Enable Periodic Update box is checked the Frame Count value should increment when the proble is connected and functioning properly Note that it is generally beneficial in every test setup to verify that the Frame CRC Error Count counter is also functioning properly by loading an intentionally CRC errored frame pattern into the SSG and sending it through the loopback enabled PUT In this case the CRC Error counter should increment for every received frame Note that for RSG testing it is normal for the Link Level Error Count counter to increment during
18. Jitter Tolerance testing for the purposes of the SATA IO Interoperability Program These requirements are a subset of the complete set of requirements defined in the SATA standard Note that this test requirement is only applicable to products running at 1 5Gb s For products that support 3 0Gb s this test is not required Test Setup See Appendix Test Procedure Note this test procedure assumes the user has already performed the initial system setup and calibration procedures outlined in Appendices A K of this document 1 Connect the PUT to the test system as outlined in Appendix A 2 Configure the N4915A Serial Bus Switches so that the TX and RX pairs of the PUT are connected to the BIST Configuration 1 3 Configure the Stressed Signal Generator SSG to send the Framed COMP pattern 2 at 1 5Gb s and turn the output of the generator OFF i e disable all signal output 4 Configure the PUT for BIST L operation at 1 5Gb s using the BIST Configuration Tool 5 Turn the output of the SSG ON but with jitter disabled i e clean pattern with nominal SATA amplitude 6 Activate the N4915A Switches so that the PUT RX is connected to the SSG and its TX is connected to the Frame Error Counter 7 Verify using the Frame Error Counter that the PUT is properly looping back the unstressed Framed COMP pattern data without error 8 Configure the SSG for Sinusoidal DJ at a frequency of 5MHz with the proper DJ RJ and Ampli
19. MD INFORMATIVE 20 APPENDIX E USING THE AGILENT N4903A J BERT FW v4 91 OR LATER AS THE STRESSED SIGNAL GENERATOR SSG 25 APPENDIX USING THE AGILENT 81133 4A PULSE PATTERN GENERATOR AS THE STRESSED SIGNAL GENERATOR SSG 28 APPENDIX G USING THE AGILENT N4219B SERIAL ATA PROBE AS THE FRAME ERROR DETECTOR 31 APPENDIX USING THE CRESCENT HEART SOFTWARE SATA II PROBE AS THE FRAME ERROR DETECTOR 37 APPENDIX I SUGGESTED INITIAL AMPLITUDE AND DJ RJ SETTINGS FOR VARIOUS SSG SETUPS INFORMATIVE 39 APPENDIX J USING THE AGILENT N5990A TEST AUTOMATION SOFTWARE OPTION 103 A K A VALIFRAME 40 APPENDIX K USING THE AGILENT 81133 4A PULSE PATTERN GENERATOR AND 81150A PULSE FUNCTION ARBITRARY NOISE GENERATOR AS THE STRESSED SIGNAL GENERATOR SSG INFORMATIVE 46 SATA IO Logo Working Group Agilent SATA RSG MOI Serial Logo Working Group MODIFICATION RECORD REVISIONS FOR 1 3 INTEROP PROGRAM 2008 May 29 Version 1 00RC minor UPDATE FOLLOWING MAY 29 LOGO WG REVIEW AND APPROVAL Andy Baldman UNH IOL RSG 01 Removed footnote in procedure Step 11 regarding the previous J BERT limitation for Gen1 62MHz Appendix A Added footnote to Table 1 stating that v4 91 FW or newer is required to use J BERT Appendix E Removed Informative status from appendix Title Appendix E Added text to appendix Title and Discussion stating v4 91 FW or newer is required to use J BERT
20. Make sure your The definition of Primitive Recognizers or Events is not required for this test EM mese ss eee dE ee Hai e 59153 oven Fesefessent E Lc sara s o E LC d Cem Cem 9 Open the Port 1 Device Analyer Trigger menu and define the trigger as illustrated below uu Dhow Fl repe Or Games Ecrans FTN w Oow 8 g BIE bem 8 ee SIT GEI z DENETARA Eror e nen eee Cen xe The underlying idea of this trigger definition is to use one of the logic analyzer s internal real time counters to count frames with wrong checksum EOF Bad CRC Based on the N4219B design this event will occur twice for each frame To count the number of events correctly it is important to know that EOF Bad CRC will occur 2 times in a consecutive manner for 1 wrong frame The Else if part of the trigger is not required for this test but avoids a Warning message that indicates a trigger SATA IO Logo Working Group 35 Agilent SATA RSG MOI Serial ATA Logo Working Group with no exit path 10 Before starting the logic analyzer for FER test open the Status window from the main overview topped 1 Host Listing Bf Packet Viewer Host De 1L Open the Details fo
21. RSG MOI Serial Logo Working Group Appendix B SSG Calibration Procedure using Agilent 05081204 Real Time DSO as the JMD define a procedure for verification and calibration of the str Agilent Infiniium 05081204 or equivalent 80000 series DSO a d signal generator setup using the the Jitter Measurement Device References 1 Serial ATA Interoperability Program Revision 1 3 Unified Test Document Section 2 16 Last Modification February 7 2008 Discussion Prior to running the actual stressed receiver tes teps to verify and calibrate the test system in order to ensure that the signal delivered to the receiver of the PUT exhibits the proper type and amount of stress for the each test as defined in 1 First we must verify that the SSG is providing the proper amounts of TJ and RJ at the reference plane Note that the reference plane in this case is the end of the SMA cables where they connect to the fixture that interfaces to the PUT The setup and calibration procedure is as follows B 1 Configure the SSG to send the Framed COMP signal See Sections E 2 for J BERT or F 2 for 81134A of this MOL B 2 Calibrate the Differential Amplitude at the Reference Plane The amplitude calibration procedure requires measuring the amplitude of two particular bits contained in the framed COMP pattern namely the Lone 0 and Lone 1 bits contained in the SATA Lone Bit Pattern LBP
22. Random Jitter To adjust the RJ turn on output 1 of the 81150A and make sure that the channel add feature is turned off Select the Noise function and Crest Factor 7 0 in the PDF menu Increase decrease the output amplitude This step is the same if the 81150A replaces only the NoiseCom noise generator in the setup shown in Appendix F CI aia gt Smaa Figure K 2 Agilent 81150A remote interface with noise settings for channel 1 shown The LXI interface pictures the local user interface and all front panel controls K 3 Adjusting the Deterministic Jitter DJ adjust the Deterministic Jitter via the 81150A tum on its channel add feature first If the 33250A shall be replaced in a setup as described in Appendix F this step is not needed Use the Utility menu to enter the Output Setup submenu When the channel add feature is turned on the signal that is generated by channel two will be internally added to output one No external power combiner will be needed SATA IO Logo Working Group 47 Agilent SATA RSG Serial Logo Working Group Figure K 3 Agilent 81150A remote interface with channel add feature turned on Select channel 2 and sinusoidal waveform by pressing the Sine button Use the Frequency hotkey to set the required frequency Calibrate the deterministic jitter by adjusting the Amplitude and observing the jitter reading on the
23. SERIAL Serial ATA International Organization Version L00RC 29 2008 Serial ATA Interoperability Program Revision 1 3 Agilent MOI for SATA RSG Tests This document is provided AS IS and without any warranty of any kind including without limitation any express or implied warranty of non infringement merchantability or fitness for a particular purpose In no SATA IO or any member of SATA IO be liable for any direct indirect special exemplary punitive or consequential damages including without limitation lost profits even if advised of the possibility of such damages This material is provided for reference only The Serial ATA International Organization does not endorse the vendor equipment outlined in this document Serial Logo Working Group TABLE OF CONTEN TABLE OF CONTENTS MODIFICATION RECORD ACKNOWLEDGMENT INTRODUCTION GROUP 1 RSG REQUIREMENTS TEST RSG 01 GENI 1 5GB s RECEIVER JITTER TOLERANCE TEST TEST RSG 02 GEN2 3 0GB S RECEIVER JITTER TOLERANCE TES APPENDICES 10 APPENDIX A GENERAL RESOURCE REQUIREMENTS dl APPENDIX B SSG CALIBRATION PROCEDURE USING AGILENT DSO81204 REAL TIME DSO 2 3 5 6 7 8 9 AS THE JMD 2 14 APPENDIX SSG CALIBRATION PROCEDURE USING AGILENT N4903A J BERT As THE JMD INFORMATIVE 18 APPENDIX D SSG CALIBRATION PROCEDURE USING AGILENT 86100C DCA J As THE J
24. Serial ATA probe to the logic analyzer according to the installation instructions 2 Make sure that POD 1 2 and POD 3 4 for Port 1 are connected to the logic analyzer A connection for Port 2 is not required for this test 3 Power up the N4219B and the logic analyzer and start from the default settings The following screen shot shows a typical start up screen SATA IO Logo Working Group E Agilent SATA RSG MOI 4 Serial Logo Working Group Pr ih ven Modul jos windows DEN seta owns A ENEI ERA File name 42198 GO a eE My Recent Documents Desktop My Documents My Computer Local Disk Documents and Settings All Users C3 Shared Documents 2 Agilent Technologies Logic Analyzer C3 Default Configs EE 018 5 Select the 4219 _1 file and open it SATA IO Logo Working Group 32 Agilent SATA RSG MOI Serial Logo Working Group Lookin 2188 E TENES Henne D Fert ope EET tm E A E bas armen yy moe Ome Teas Projet Descoton EATA Pat ZDreclons Fle seupibate Hl Data rd setup ince TeoVevers seupony The logic analyzer wil
25. The differential amplitude value should appear at the bottom of the screen e Adjust the SSG amplitude see and until the measured amplitude reads 325mVppd or 275 Gen2i or 240mV GenIm Gen2m Record the SSG amplitude setting that yields the desired output amplitude at the reference plane D 3 Verify 100ps Rise Time at the Reference Plane With the DCA still in Oscilloscope Mode switch to Eye Mask Mode by pressing the corresponding button just to the right of the display Measure the rise time by going to the Eye Meas tab on the left side of the screen and selecting More then the Rise Time measurement The rise time value should appear at the bottom of the screen Note that the value displayed by default is the 10 90 value but we want the 20 80 value for SATA measurements Change the measurement configuration by pressing the Setup amp lInfo button on the right side of the Measure tab where the risetime value is displayed Select Configure Meas and select the 20 50 80 radio button then hit Close Now verify that the measured rise time is 100ps SATA IO Logo Working Group 20 Agilent SATA RSG Serial Logo Working Group D 4 Verify that the Skew at the Reference Plane is Less Than 10ps Reinitialize the by pressing Default Setup again Turn Channel 2 On using the front panel selector button Select Eye Mask Mode on the front panel
26. and press Autoscale You should see the two Channels eyes appear on the display e Zoom in on the zero crossing area using the Horizontal knob A setting of about l ps div should work well Turn on Marker 1 using the leftmost vertical Marker button on the front panel and assign it to Channel 1 Assign the second vertical marker the dashed one 3 from the left on the front panel to Channel 2 Line Marker 1 up with the Channel 1 zero crossing point and do the same for Marker 2 Channel 2 Verify that the skew is no more than 10ps If the skew is excessive try replacing one or both of your cables and remeasuring the skew Note you ll probably also have to repeat the amplitude calibration also as different cables will have slightly different losses See the figure below for a sample screenshot of the skew measurement Seup Messe Liites hep oaj D me H wi dial oz 1 EPN sj otv a OONN 8 Tig ma G Panem QUU ny Dany omy Figure D 1 Skew measurement screenshot D 5 Calibrate RJ to 0 180 UI at the Reference Plane and then we will measure edure we will set the initial SSG RJ to be close to the desired ran and fine tune it using a jitter measurement instrument Note The first Jitter Mode procedure below tends to slightly overestimate RJ i e it measures more than what the J BERT s RJ value is configured f
27. counter on the Frame Error Counter 10 Run the test for 20 minutes and record the number of frame errors detected by the Frame Error Counter 11 Repeat steps 8 10 for the 10 33 and 62 MHz sinusoidal jitter frequencies Note that for any jitter frequency test case if excessive errors are observed i e gt 1000 the test may prematurely aborted and a failing result assigned for that test case Observable Results Forall jitter frequencies the number of frame errors observed should be zero Possible Problems None SATA IO Logo Working Group 9 Agilent SATA RSG Serial Logo Working Group APPENDICES Overview Test suite appendices are intended to provide additional low level technical detail pertinent to specific tests contained in this test suite These appendices often cover topics that are outside of the scope of the standard and are specific to the methodologies used for performing the measurements in this test suite Appendix topics may also include discussion regarding a specific interpretation of the standard for the purposes of this test suite for cases where a particular specification may appear unclear or otherwise open to multiple interpretations Test suite appendices are considered informative supplements and pertain solely to the test definitions and procedures contained in this test suite SATA IO Logo Working Group 10 Agilent SATA RSG Serial
28. djust the SSG s RJ Amplitude until the TJ 1E 12 value on the DCA J reads 180mUI Record the SSG setting that results in the properly calibrated 8 57ps RMS value at the reference plane Alternate method using Eye Mask mode Preferred method Connect the positive and negative output signals from the SSG to Channels 1 and 2 of the DCA J respectively Also connect the single ended clock signal from the SSG to the Front Panel Trigger input of the DCA J Press Default Setup on the DCA J to reinitialize the instrument Configure a differential trace by going to Measure Math and turn on Function 4 Configure Function 4 to subtract Channels 1 Source 1 and 2 Source 2 Then turn Channel 1 off using ihe front panel selector button so that only Function 4 remains Press Autoscale again to optimize Function 4 Enable Eye Mask mode by pressing the Eye Mask Mode button on the front panel The DCA I should auto detect the pattern and display the RMS measurement result on the screen which should read around 8 0 to 8 5ps On the SSG adjust the RJ Amplitude until the Jitter RMS f4 value on the DCA J reads 8 57ps Record the SSG setting that results in the properly calibrated 8 57ps RMS value at the reference plane D 6 Add Sinusoidal DJ to Create 450 UI TJ at the Reference Plane Now that the RJ has been calibrated the DJ must be added to calibrate TJ to at the specific jitter frequencies required for the te
29. endix E Deleted reference to resistive splitters in E L Appendix F Changed Figure F 1 to only show SSG components Appendix F Removed splitters from Figure F 1 and deleted text from discussing splitter use Added new informative Appendix K for using Agilent 81150A as DI RI source PREVIOUS REVISIONS FOR 1 2 INTEROP PROGRAM 2007 Oct 24 Version 1 00 FINAL APPROVED 11 2 RELEASE Andy Baldman UNH IOL Cover Page Updated document version number to 1 00 2007 Jul 12 Version 1 00RC1 EDITORIAL UPDATE FOLLOWING 12JUL2007 RC APPROVAL Andy Baldman UNH IOL Cover Page Updated document version number to 1 00RC 2007 Jun 07 Version 0 92 ADDITIONAL UPDATES POST IW3 Andy Baldman UNILIOL Acknowledgements pag Added Hermann for Bitfeye contributions of automaton software RSG 01 and RSG 02 Added note at hotiom of procedure to cov premature test abortion for css when txcesive are observed gt 1000 for any test cse as per he UTD Appendix A Added Apilent SMA cables and pat mombers to equipment Appendix A Adied model numbers of suitable equivalent Neiseeom sources to equipment Appendix A Added sine source to equipment ist as stable DI source Appendix I Added initial starting stings for using E4432B as DJ source with S1134A SSG Added new Appendix Appendix for Biteye automation software SATA IO Logo Working Group 3 Agilent SATA RSG Serial Logo W
30. ents The requirements section s generally expressed in terms of minimum requirements however in some c manufacturer model information may be provided ecifies the test hardware and or software needed to perform the test This is specific equipment Last Modification is specifies the date of the last modification to this test covers the assumptions made in the design or implementation of the test as well as known limitations Other items specific to the test are covered here as well Test Setup The setup section describes the initial configuration of the test environment Small changes in the configuration should not be included here and are generally covered in the test procedure section next Procedure The procedure section of the test description contains the systematic instructions for carrying out the test It provides a cookbook approach to testing and may be interspersed with observable results Observable Results This section lists the specific observables that can be examined by the tester in order to verify that the PUT is operating properly When multiple values for an observable are possible this section provides a short discussion on how to interpret them The determination of a pass or fail outcome for a particular test is generally based on the successful or unsuccessful detection of a specific observable Possible Problems This section contains a description of known i certa
31. erator SSG Purpose To document the various necessary setup and configuration procedures required when using the Agilent N4903A J BERT as the Stressed Signal Generator References 1 Serial ATA Interoperability Program Revision 1 3 Unified Test Document Section 2 16 Last Modification May 29 2008 Discussion There are multiple suitable options available for generating the stressing signal required for performing SATA Receiver Tolerance testing One option is to use the Agilent N4903A J BERT NOTE J BERT requires firmware v4 91 or later in order to support jitter frequencies For firmware update see www agilent com This appendix documents the necessary procedures for setting up and configuring the J BERT for RSG testing Note these procedures are referenced by other procedures in this document E General SSG Setup Because the J BERT is an integrated system no external active signal generating modulating devices are needed in order to create the stressed SATA signaling The N4903A J BERT is shown below Figure E 1 N4903A J BERT Note that the only external components that are needed are two Agilent 15435A Transition Time Converters TTC s which are needed to slow down the output risetime of the J BERT to the required SATA levels 100ps 20 8056 These are attached directly to the DATA outputs of the J BERT 2 Configuring SSG to send an signal Optional If one does not exist you
32. ext e Click Finish to exit the Wizard You can also click Close on the Jitter window to get rid of that The scope should start running and you should see the RJ DJ screen accumulating values Look at the RJ RMS narrow result at the bottom of the scope screen Adjust the RJ of the SSG until this value is 8 57ps RMS for Genli Im and 4 285ps RMS for Gen2i 2m See Appendix I for suggested initial SSG settings Record the SSG settings that produce the desired RJ value on the DSO display B 6 Add Sinusoidal DJ to Create 450 UI at the Reference Plane With the DSO still set up for the DJ RJ measurement increase the DJ of the SSG until the TJ is 0 450UI note this is 300ps for Genli Im and 150ps for Gen2i 2m Record the SSG settings that produce the 450UI TJ value on the DSO display B 7 Verification of SSG Output for Gen 3 0Gb s Rate The setup and calibration procedure for the stressed Gen2 3 0Gb s signal is identical to the procedure described above for the signal except that the bit rate must be set for 3 0Gb s and the amplitude must be set to the proper value for the given interface type see B 2 Repeat the Gen procedure to determine the proper Gen2 SSG amplitude and RJ settings as well as the DJ settings for the 5 10 33 and 62MHz jitter frequencies SATA IO Logo Working Group 17 Agilent SATA RSG MOI Serial Logo Working Group Appendix C SSG Calibration Procedure using Agi
33. in situations It may also refer the reader to test more detail regarding these issues ues with the test procedure which may affect test results in ite appendices and or other external sources that may provide SATA IO Logo Working Group 6 Agilent SATA RSG Serial Logo Working Group GROUP 1 RSG REQUIREMENTS Overview This group of tests verifies receiver functionality under stressed signal conditions for the purposes of performing SATA IO Interoperability Program testing These tests are limited to functionality which are covered by tests RSG 01 and RSG 02 Section 2 16 of the Serial ATA Interoperability Program Unified Test Document Revision 1 3 and do mot provide comprehensive coverage of all receiver tolerance requirements defined by the SATA Revision 2 6 standard SATA IO Logo Working Group 7 Agilent SATA RSG MOI Serial Logo Working Group Test RSG 01 Genl 1 5Gb s Receiver Jitter Tolerance Test Purp verify that the receiver of the Product Under T ignal conditions while operating at 1 5Gb s st PUT can operate without error under stressed References 1 SATA Interoperability Program Revision 1 3 Unified Test Document Section 2 16 1 2 SATA Interoperability Program Revision 1 3 Pre Test MOI Appendix B Framed COMP Pattern Resource Requirements See Appendix A Last Modification May 29 2008 Discussion Reference 1 specifies the basic requirements for Receiver
34. ity Program These requirements are a subset of the complete set of requirements defined in the SATA standard Note that this test applies only to products operating at 3 0Gb s Test Setup See Appendix A Test Procedure Note this test procedure assumes the user has already performed the initial system setup and calibration procedures outlined in Appendices A K of this document 1 Connect the PUT to the test system as outlined in Appendix A 2 Configure the N4915A Serial Bus Switches so that the TX and RX pairs of the PUT are connected to the BIST Configuration 1 3 Configure the Stressed Signal Generator SSG to send the Framed COMP pattern 2 at 1 5Gb s and turn the output of the generator OFF i e disable all signal output 4 Configure the PUT for BIST L operation at 3 0Gb s using the BIST Configuration Tool 5 Turn the output of the SSG ON but with jitter disabled i e clean pattern with nominal SATA amplitude 6 Activate the N4915A Switches so that the PUT RX is connected to the SSG and its TX is connected to the Frame Error Counter 7 Verify using the Frame Error Counter that the PUT is properly looping back the unstressed Framed COMP pattern data without error 8 Configure the SSG for Sinusoidal DJ at a frequency of 5MHz with the proper DJ RJ and Amplitude values determined during the cal procedure for 3 0Gb s operation Enable jitter generation on the SSG output and turn the SSG output ON 9 Reset the
35. l open a number of tabs and show the following default configuration SATA IO Logo Working Group 33 Agilent SATA RSG MOI Serial Logo Working Group 2 Modulos Windows NA210B 1 RI Par t Host pos ort Host B e d lem N Bracket Device _pa Device Decode Vewer Haste e Devica Listing JER Pott Hot ising JB Packet Viewer BB Device Using For Help press FL The Overview tab gives access to all required features for this test For setup the N4219B Properties and the Portl Device Analyzer Trigger will be configured later When running the FER test the Status button at the bottom of this window will lead to the test results 7 Make sure your PUT is transmitter output is connected to Port 1 HR DT The HT DR of Port 1 and Port 2 won t be connected for this test SATA IO Logo Working Group 34 Agilent SATA RSG MOI Serial Logo Working Group settings are as shown below Set the Port 1 Probe Rate according to your test speed requirements For RSG 01 this is 1 5Gbps and for RSG 02 this is 3Gpbs Once the PUT is transmitting the Port 1 Device Status will show the link status and speed Open the N4219B Properties Setup from the Overview tab of the logic analyzer
36. lent N4903A J BERT as the JMD Informative define a procedure for verification and calibration of the stress Agilent N4903A J BERT as the Jitter Measurement Device d signal generator setup using the References 1 Serial ATA Interoperability Program Revision 1 3 Unified Test Document Section 2 16 Last Modification February 7 2008 Discussion Prior to running the actual stressed receiver tes sssary to perform several steps to verify and calibrate the test system in order to ensure that the signal delivered to the RX port of the PUT exhibits the proper type and amount of stress for the each test as defined in 1 First we must verify that the SSG is provi Note that the reference plane in this interfaces to the PUT ing the proper amounts of DJ and RJ at the reference plane ase is the end of the SMA cables where they connect to the fixture that The setup and calibration procedure is as follows C 1 Configure the SSG to send a Framed COMP signal Sec Sections E 2 for J BERT or F 2 for 81134A of this document C2 Calibrate the Differential Amplitude at the Reference Plane Connect the TX and TX outputs of the SSG to the positive and negative DATA IN ports of the J BERT On the J BERT go to Analysis gt Eye Diagram and press Start to build eye You should see the eye measurement results appear below the eye diagram Read the Eye Amplitude value This is
37. mann stehling bitifeye com SATA IO Logo Working Group 5 Agilent SATA RSG MOL Serial Logo Working Group INTRODUCTION The tests contained in this document are organized in order to simplify the identification of information related to a test and to facilitate in the actual testing process Tests are separated into groups primarily in order to reduce setup time in the lab environment however the different groups typically also tend to focus on specific aspects of product functionality The test definitions themselves are intended to provide a high level description of the motivation resources procedures and methodologies specific to each test Formally each test description contains the following sections Purpose The purpose is a brief statement outlining what the test attempts to achieve The test is written at the functional level Referenc his section specifies all reference material external to the test suite including the speci 5 references for the test in question and any other references that might be helpful in understanding the t methodology and or test results External sources are always referenced by a bracketed number e g 1 when mentioned in the test description Any other references in the test description that are not indicated in this manner refer to elements within the test suite document itself e g Appendix 6 A or Table 6 1 1 17 Resource Requirem
38. must create a new pattern file This can be done by going to Pattern Pattern Editor then selecting the NEW icon Enter 20 bits into the Description field and 20 into the Length field The pattern type should be Standard Then use the cursor and keyboard to edit the pattern to read 1100 1100 1100 1100 1100 Click the Save As icon and save it to file MFTP20 ptrn Load the pattern by going to Pattern Pattern Select and select the User Pattern from File radiobutton and click the Browse button Select the MFTP20 ptrn pattern and press OK Also make sure the Error Detector Pattern tracks the Pattern Generator Pattern box is checked then press OK SATA IO Logo Working Group 25 Agilent SATA RSG MOI Serial Logo Working Group e Configure the initial J BERT data amplitude by going to PG Setup gt PG Output Setup and entering value for Vof and 375mV for Vampt For the Clock output enter OmV for Vof and S00mV for Vampt Next we will set the J BERT bit rate by going to PG Setup gt Bit Rate Setup Make sure Clock Source is set to Internal Sub Rate Clock Divider is 2 and enter 1 5Gb s for the rate If you haven t already done so add a preset for this rate by selecting the Add Preset button on the right e Tum on the J BERT transmitter by pressing the Data button on the front panel below the display djusting the Output Amplitude adjust the output amplitude go to PG Setup
39. of SSG sources are defined J BERT vs 81134A with external modulation source Note that both of these setups assume the use of Transition Time Converters TTC s and 50 50 power splitters on their outputs Note that the 50 50 power splitters add approximately 6dB of flat loss to the signal path This appendix contains suggested starting values for initializing the amplitude RJ and DJ settings prior to performing the calibration steps of Appendices B C and D These are informative values intended as initial starting points when performing the calibration procedure Ampl 1625 325mV 405 A0SmV TBD RJ 8 57ps RMS 18 00 18 00 TBD DI 10MHz TI0mVpp 280mV TBD DJ G3MHz 630mVpp 250mV N A DI 62MHz 810mVpp 260mV Gen Ampl 137 5 275mV 375mV 3I5mV TBD RJ 4285ps RMS 23 00 23 00 TBD DJ I0MHz 370mVpp 125mV TBD DJ G3MHz 350mVpp TismV TBD DJ 62MHz 370mVpp T20mV TBD For GenIm 2m amplitude levels informative Genl m Use 270mV to get 120 240mV at 1 5G Gen2m Use 310mV to get 120 240mV at 3 06 Table 1 1 Suggested Initial Settings for Various Equipment Setups SATA IO Logo Working Group 39 Agilent SATA RSG MOI Serial Logo Working Group Appendix J Using the Agilent N5990A Test Automation Software Option 103 a k a Valiframe Purpose To document the use of the N5990A Test Automation Software Option 103 for RS
40. onnect supporting PUT s to be put into BIST L using the BIST Configuration Tool then be sent the framed COMP test pattern into their RX from the SSG while being monitored on the TX by the Frame Error Counter Once the PUT is placed into BIST L loopback mode the BIST Configuration Tool is effectively switched out of the system in order to run the formal test Figure 1 Basic Test Configuration Figure A 2 illustrates how either the a Agilent 81133 4A pulse pattern generator or b Agilent N4903A J BERT may be used as the SSG If the J BERT is used as the SSG additional sources are required The setup using the 81133 4A requires two external sources to generate jitter The outputs of the DJ and RJ modulation sources are combined through a power divider into the 81133 4A s Delay Control Input SATA IO Logo Working Group 12 Agilent SATA RSG Serial Logo Working Group Figure 2 a Use of Agilent 81133 4A or b Agilent N4903A J BERT 2 only as the SSG A 3 Modified Setup for use with Valiframe Automation Software Figure A 3 shows a modified version of the basic setup from Figure A 1 which is to be used when using the Valiframe automation software in conjunction with the N4915A 005 Serial Bus Switches Tax PUT A suo US SATA fixture Figure A 3 Modified Setup for Switch Automation When Using Valiframe Software SATA IO Logo Working Group 13 Agilent SATA
41. or when using the J BERT as the SSG See the alternate Eye Mask mode procedure below which tends to better match the J BERT s RMS RJ setting SATA IO Logo Working Group 21 Agilent SATA RSG Serial Logo Working Group Procedure using Jitter mode Connect the positive and negative output signals from the SSG to Channels 1 and 2 of the DCA J respectively Also connect the single ended clock signal from the SSG to the Front Panel Trigger input of the DCA J Press Default Setup on the DCA J to reinitialize the instrument Configure a differential trace by going to Measure Math and turn on Function 4 Configure Function 4 to subtract Channels 1 Source 1 and 2 Source 2 Then turn Channel 1 off using the front panel selector button so that only Function 4 remains Press Autoscale again to optimize Function 4 Enable Jitter mode by pressing the Jitter Mode button on the front panel The DCA J should auto detect the pattern and display a jitter summary on the screen Look at the TJ 1E 12 result which should read around 140ps or so The DDJ p p result should be 100fs or less if it isn t your cables are skewed or there is some other source of DJ Check your setup The RJ rms value should read around 9 10 ps Change the units of the jitter results to UI by clicking on the Setup amp Info button selecting Config Meas and changing the Jitter Mode Units radiobutton to Unit Interval Then press Close A
42. orking Group 2007 Apr 28 Version 0 90 MINOR UPDATES IN RESPONSE TO I7APR2007 REVIEW Andy Baldinan UNH IOL Cover Page Updated SATA logo to trademarked version and added CHS Frame Error Detector Entire Document Changed noise source model name from UFX 7110 to PNG 7110 Appendix A Changed amplitude procedure BACK to using LBP lone rather than ALIGN minimum amplitude bis Renamed Appendix H to Appendix died new Appendix H or Crescent Heart Software ame Erro Detector 2007 Apr 16 Version 0 88 ADDITIONAL MAJOR UPDATI Andy Baldman UNH IOL Entire Document Updated DJ references to 27001 from 32001 Enfre Document Removed ll references to wing 1448 spies 5050 spliters are preferred for eter reum loss and matching Append A Changed amplitude procedure to use ALIGN Minimum Amplitude Bitinstead of LBP one bit Appendix D Cleaned up many typos and moved J BERT specific SSG info into Appendix 2007 Apr 08 Version 0 87 MAJOR UPDATE FoR REVISION 12 INTEROP PROGRAM Andy Baldman UNH IOL Entire document Updated UTD and MOI references to reflect Program Revision 12 RSG 01 02 Changed DJ frequencies fom 2 to 10S3162MHe per UTD updates Appendix A Added LAB pict testo Table A 1 and changed Figure A 3 toa block diagram Appendix B Completely overhauled adding procedure for amplitude calibration using isolated Lone 1 Appendices C D E Made informative Appendix F Major rewrite to incl
43. r Port 1 Device Analyzer Port 1 Device Analyzer Trigg Occurrence Counter 0 Global Counter 1 0 Global Counter 2 0 The Global Counter 1 values gives the actual number of FER errors in real time while running the test Based on the pass fail criteria for RSG 01 and RSG 02 the test may be interrupted if the number of FERs reached its limit The counter resets each time the logic analyzer is started Thus stop and start the logic analyzer once the setup is ready for the FER test SATA IO Logo Working Group 36 Agilent SATA RSG Serial ATA Logo Working Group Appendix Using the Crescent Heart Software SATA II Probe as the Frame Error Detector Purpose To provide a procedure for using the Crescent Heart Software SATA II Analyzer Probe as an alternate Frame Error Detector References None Last Modificatio April 28 2007 Discussion Appendix G of this MOI defines a procedure for using the Agilent N4219B Serial ATA Probe and associated Logic Analyzer as a Frame Error Detector An alternative to this Frame Error Detector implementation is the Crescent Heart Software SATA II Probe Adapter which provides a simple means for monitoring and counting variety of SATA error conditions in addition to CRC errored frames Note that a complete user s manual for the SATA II Probe can be obtained from the Crescent Heart Website as well as an abbreviated manual for using the SATA II probe for Frame Error Detection purpo
44. ruary 7 2008 Discussion Prior to rumning the actual stressed receiver tes sssary to perform several steps to verify and calibrate the test system in order to ensure that the signal delivered to the RX port of the PUT exhibits the proper type and amount of stress for the each test as defined in 1 First we must verify that the SSG is providing the proper amounts of DJ and RJ at the reference plane Note that the reference plane in this case is the end of the SMA cables where they connect to the fixture that interfaces to the PUT The setup and calibration procedure is as follows D 1 Configure the SSG to send an signal Sec Sections E 2 for J BERT or F 2 for 81134A of this document D 2 Calibrate the Differential Amplitude at the Reference Plane Initialize the DCA J by pressing the Default Setup button Note this will automatically select 0 Mode which is what we will use for the amplitude measurement Press the Autoscale button to get an eye on the screen Configure a differential trace by going to Measure gt Math and turn on Function 1 Configure Function 1 to subtract Channels 1 Source 1 and 2 Source 2 Then turn Channel 1 off using the front panel selector button so that only Function remains Press Autoscale again to optimize Function 1 Measure the amplitude by going to the Amplitude tab on the left side of the DCA J screen and selecting the Vamptd measurement
45. ses See hitp www c h s con SATA shtml The following set of instructions provides a general procedure but refer to the formal product documentation if additional detail is desired After installing the Application software on a standard USB equipped PC and launching the application you should see the following screen Fete common feni i OR regen D Testpointaigrale Normal Freba con Cay Fie ect rogus Copy be eps RUE oput te Hant Non OOB cet Cie uu MS FP intai het Re pens od epi Hen spent Donos Device OOB sac trestii Fe eM Ld keepin Dever sens Fx aped per Dade Diner signet Diese Got sime Signs 4 ate Orde ow re qai se NOn F pires se N3 le 1 Summarys ay s NO T Newsa stes every HO Che CORO Nm Deve AND p Many C Fomuemucnenming SR Figure H 1 SATA II Control Application Main Window Configure the settings as shown in Figure H 1 above making note to properly de select the Initial Host RX speed Gen2 and Initial Device RX speed Gen boxes if Gen PUT testing is being performed Once the Main Window settings are configured go to View gt Counters to select the Counters window shown in Figure
46. ss Finish J 2 Test RSG 02 Gen 3 0Gb s Receiver Jitter Tolerance Test Valiframe SATA IO Logo Working Group Agilent SATA RSG Serial Logo Working Group woe oe T _ Press Configure remm Sue ei Soest one Den Marne iini 1 O copies o Docet Select Speed Class 3 0 GBit s and press Register DUT and then OK SATA IO Logo Working Group 42 Agilent SATA RSG MOI Serial ATA Logo Working Group ie Sten Seem Hep bas E m 1 5 200 Sii Lael Pint Foes Log Te Tex ge Lp L MM t t B erres tng Caltete enna i E 8B Raion Catalin AUI 44H ruse ier leor 4242007 64021 PM IE Poca FEES Faded Cana Bohne U animo 5 sip ita 5 EB se Sipsi El eere mae C D e cn Fei Select Differential Voltage Calibration Random Jitter Calibration and Sinusoidal Jitter Calibration from the test tree on the left side of the window Press Start Then you are prompted to change the electrical connection according Appendix B 80 Calibration Procedure using Agilent 080081204 as the JMD When the calibration procedures are finished the indicators next to
47. st Note This is an older procedure for calibrating sinusoidal DJ not TJ Informative use only Note Jitter mode cannot be used here as jitter is too large in some cases and DCA J gives an error saying to decrease the jitter and or retard the edges Therefore Eye Mask mode must be used instead Connect the SSG to the DCA J and configure Function 4 to display the differenti first two bullets of D 5 Turn off all jitter from the SSG output and press AutoSeale on the DCA J On the SSG enable only the DJ component and set to approximately 270UI at 5MHz See Appendix I for SSG initial settings signal See SATA IO Logo Working Group 22 Agilent SATA RSG Serial Logo Working Group enabling the DJ the DCA J display should resemble the following Be Conr Sep Vere Liles Hb aimans cem gsx emos ev Run Figure D 2 DCA J display during DJ measurement Now we will set a histogram to measure the peak to peak width of the eye Note One could also use the Jitter p p automatic measurement shown on the left side of the DCA J screen above however this sometimes takes a while to converge to a stable value To set the histogram go to Measure gt Histograms gt Configure In the dialog that displays check the Histograms ON and Show Border checkboxes then hit Close e Adjust the histogram by going to Measure gt Histograms gt Window and adjusting
48. testing This is simply due to the fact that the normal Link Level protocol is not being obeyed by the PUT during the RSG test and thus this counter may be ignored Also note that in some cases it may be observed that the other error counters may increment during a test Although relatively uncommon it is possible for Running Disparity or Encoding Errors to occur on the wire that will be detected as errors by the probe but NOT cause a CRC error to occur This is due to the fact that these errors sometimes occur OUTSIDE of the SATA frame the contents covered by the CRC Because the SATA RSG test is defined as a frame error test rather than a bit error test these types of errors occurring outside of the CRC applicable frame are not counted as observed errors and therefore do not affect the pass fail criteria for a given PUT However it is recommended that if such errors are observed during testing some effort be made to determine the cause as such errors should not typically occur for devices operating with a significant degree of receiver margin SATA IO Logo Working Group 38 Agilent SATA RSG Serial Logo Working Group Appendix I Suggested Initial Amplitude and DJ RJ Settings for Various SSG Setups Informative Purpose To provide a table of initial i e pre calibrated amplitude DJ and RJ settings for various SSG s References None Last Modification June 7 2007 Discussion In this MOI two types
49. the calibration routines should be green The calibration routines should be performed once a day The date and time of the last calibration is noted next to the calibration routines names in the test tree SATA IO Logo Working Group 43 Agilent SATA RSG MOI Serial Logo Working Group Te cepere eb sit so Satay ban Pini Fee Te Tie Mengss GARI TE ree Tc tenet sistema i H Ho e 2 Hom n Pracene Eroi Casio PruceadvitMiuProsdn Procena fol PcsedehinaPicedrn T PETI mae D Select the RSG 02 Gen2 Rx Jitter Tolerance Test procedure Press Start Then you are prompted to change the electrical connection according groupl Test RSG 02 one hour the test RSG 02 is finished When the green indicator next to the test name is green the DUT has passed the test For a detailed test report double click on the test and an excel sheet will open SATA IO Logo Working Group 44 Agilent SATA RSG MOL Serial Logo Working Group Microsoft Excel RSG 02 1 RSG 02 es SS Product Number SATA Unknown Unknow User 61672007 24217 PM Darin 20min fr coh i Frequency Tsim 9 Em o M 4 656 02 13 Test RSG 01
50. the differential amplitude Adjust the amplitude setting of the SSG so that the Eye Amplitude is 325mV Genli or 275mV Gen i or 240mV GenIm 2m Record the SSG settings that produce the desired amplitude at the reference plane C3 Verify a 100ps Rise Time at the Reference Plane The procedure for performing the risetime verification using the J BERT is identical to the Differential Amplitude calibration see C 2 above The risetime value is also reported in the results of the Eye Diagram measurement CA Verify that the Skew at the Reference Plane is Less Than 10ps TBD Describe procedure using Output Timing analysis tool to compare skew of TX and TX signals 5 Calibrate RJ to 0 180 UI at the Reference Plane Eye Diagram method Can also use Output Timing method see below SATA IO Logo Working Group 18 Agilent SATA RSG MOI Serial Logo Working Group Go to Analysis gt Eye Diagram on the J BERT and press Start to build an eye You should see the eye measurement results appear below the eye diagram Read the Pk Pk Jitter value This is the TJ but not at the proper BER level of 1 12 To change this right click on the measurement and select Properties Under the View tab in the Calculate Measurement Results for arca make sure BER Threshold is selected and select 1E 12 from the pulldown menu Press OK Note it may take while for the measurement to complete but eventually
51. the window boundaries to select only a thin horizontal slice of the waveform zero crossing When finished your display should resemble the following Setup Meare Calbrate Lies Heb onos Ws BENE gi gs gon nete mrt amm Figure D 3 Using histogram to measure pk pk DJ Agilent SATA RSG MOI SATA IO Logo Working Group Serial Logo Working Group histogram may now be used to measure the pk pk jitter due to the sinusoidal DJ Adjust the J value until the DCA J reads 270UI Record the final SSG setting that yields the properly calibrated DJ value at the reference plane Repeat the above steps for DJ frequencies of 10 33 and 62MHz Be sure to record the SSG settings for each frequency D 7 Verification of SSG Output for Gen2 3 0Gb s Rate The setup and calibration procedure for the stressed Gen2 3 0Gb s signal is identical to the procedure described above for the Genl signal except that the bit rate must be set for 3 0Gb s and the amplitude must be set to the proper value for the given interface type see D 2 Repeat the procedure to determine the proper Gen2 SSG amplitude and RJ settings as well as the DJ settings for the 5 10 33 and 62MHz jitter frequencies SATA IO Logo Working Group 24 Agilent SATA RSG MOI Serial Logo Working Group Appendix Using the Agilent N4903A J BERT FW v4 91 or later as the Stressed Signal Gen
52. tude values determined during the cal procedure for 1 5Gb s operation Enable jitter generation on the SSG output and turn the SSG output ON 9 Reset the counter on the Frame Error Counter 10 Run the test for 20 minutes and record the number of frame errors detected by the Frame Error Counter 11 Repeat steps 8 10 for the 10 33 and 62 MHz sinusoidal jitter frequencies Note that for any jitter frequency test case if excessive errors are observed gt 1000 the test may prematurely aborted and a failing result assigned for that test case Observable Results For all 4 sinusoidal jitter frequencies the number of frame errors observed should be zero Possible Problems None SATA IO Logo Working Group 8 Agilent SATA RSG Serial Logo Working Group Test RSG 02 Gen2 3 0Gb s Receiver Jitter Tolerance Test Purp verify that the receiver of the Product Under T gnal conditions while operating at 3 0Gb s st PUT can operate without error under stressed References 1 SATA Interoperability Program Revision 1 3 Unified Test Document Section 2 16 2 2 SATA Interoperability Program Revision 1 3 Pre Test MOI Appendix B Framed COMP Pattern Resource Requirements See Appendix A Last Modification February 5 2008 Discussion Reference 1 specifies the basic requirements for Receiver Jitter Tolerance testing for the purposes of the SATA IO Interoperabil
53. ude procedure fr using Noisecom PNG 7110 noise source PREVIOUS REVISIONS FOR 1 0 AND 1 1 INTEROP PROGRAMS 2006 Nov 23 Version 0 85 ADDITIONAL UPDATES Michael Herz Agilent Added contents on an 81134A based setup 2006 Nov 22 Version 0 84 ADDITIONAL MAJOR UPDATES Andy Baldman UNH IOL Created separate appendices for J BERT DCA and real time DSO calibration Created separate append for using 81134A buscd setup instead of J BERT for jitter generation Renumbered all Appendices ax a result of above changes RSG 01 02 Replaced Patem Generator with SSC to make more modular and hardware independent 2006 Nov 13 Version 0 83 FIRST MAIOR UPDATE Andy Baldman UNH IOL Updated tle page to nw revision L1 naming convention Ald procedares to Appendix to support multiple iter Measurement Devices for calibration purposes Added Appendix C for SATA Probe set and configuration 2006 Sep 24 Version 0 81 INITIAL DRAFT RELEASE Andy Baldman UNH IOL Initial Release SATA IO Logo Working Group 4 Agilent SATA RSG Serial Logo Working Group ACKNOWLEDGMENTS The Serial ATA Logo Working Group would like to acknowledge the efforts of the following individuals in the development of this document David Woolf UNH InterOperability Lab djwoolf iol unh edu Andy Baldman UNH InterOperability Lab aab iol unh edu Dr Michael Herz Agilent Technologies michael_herz agilent com Hermann Stehling Bitifeye Digital Test Solutions her
54. uration procedures required when using the Agilent 81133A or 81134A based system as the Stressed Signal Generator References 1 Serial ATA Interoperability Program Revision 1 3 Unified Test Document Section 2 16 Last Modification February 7 2008 Discussion There are multiple suitable options available for generating the stressing signal required for performing SATA Receiver Tolerance testing One option is to use a system built around the Agilent 81133 4A Pulse Pattern Generator This appendix documents the necessary procedures for setting up and configuring the system for RSG testing Note these procedures are referenced by other procedures in this document General SSG Setup The general setup using the 81134A and associated components is shown below To rest of Test Setup See Figure 1 Figure F 1 Agilent 81134A Pulse and Pattern Generator Agilent 33250A Function Arbitrary Waveform Generator and Noisecom PNG 7110 Noise Generator Note the use of the Agilent 15435A Transition Time Converters on the output of the 81134A The Transition Time Converters are needed to slow the risetime of the 81134A s output to 100 20 809 SATA IO Logo Working Group 28 Agilent SATA RSG MOI Serial ATA Logo Working Group F 2 Configuring the SSG to send or Framed COMP signal To create an pattern Go to the Data tab Enter a pattern length of 32 bits Edit the pattern to read
55. ve Power modulation sources when using 1 needed Splitter PS 81134A as SSG Hi Speed Serial Bus Used to mux BIST Generator in Agilent N4915A 005 Switch HSS and out of test setup 2 needed Frame Error Used to detect and count frame Agilent 168 or 169 Logic Analyzer with 16910 Counter FERC errors on PUT TX 16911 or 16950 module and N4219B SATA Probe or Crescent Heart Software SATA II Probe Transition Time Used to create SSG risetime of Agilent N15435A Converters TTC 100ps 2 needed SATA to SMA Test Used to convert SATA P N H303000204A Fixture interface of PUT to SMA for Crescent Heart TF SATA NE XP or test instrument connections Agilent N5421 26401 or Crescent Heart TF eSATA NE ZP for Genl m 2m SMA Test Cables Used for all connections Agilent 15442 61601 includes 4 cables 14 total cables recommended Starting with firmware v4 91 all jitter frequencies are supported by J BERT Agilent 81150A is considered informative for r1 3 and is expected to be formally approved under the 1 4 program Table 1 Summary of Test Hardware Requirements SATA IO Logo Working Group Agilent SATA RSG Serial Logo Working Group 2 Basic Test Setup Figure A l shows a Test Setup that supports both disconnect and non disconnect PUT s The BIST Configuration Tool is multiplexed into the TX and RX pairs of the PUT using the N4914A 005 Serial Bus Switches which allow non disc
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