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Supplementary Information on Using

1. Set I Trace as Ch5 to Ch4 PtoP in the Combination action Sequential or PtoP dialog box When point to point and trace acquisition condition are set simultaneously they are ANDed R20UT0366EJ0300 Rev 3 00 Page 32 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Notes on Internal Trace Acquiring internal trace To acquire the internal trace both of CPUO and CPU1 must be in the execution states after the trace acquisition condition has been set If execution of one of CPUs is stopped acquisition of the internal trace is halted Timestamp The timestamp is the clock counts of Bd 48 bit counter Table 2 17 shows the timing for acquiring the timestamp Table 2 16 Timing for the Timestamp Acquisition Item Acquisition Information Counter Value Stored in the Trace Memory F bus fetch Counter value when a fetch has been completed M bus data access Counter value when data access read or write has been completed Branch Counter value when the next bus cycle has been completed after a branch l bus Fetch Counter value when a fetch has been completed Data access Counter value when data access has been completed Point to point The trace start condition is satisfied when the specified instruction has been fetched Accordingly if the trace start condition has been set for the overrun fetched instruction an instruction tha
2. Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expr
3. IV Write I Write IV PG relative addressing PG relative addressing VB Fi Branch AE are Software VV 5 Data access M Instruction Fetch P Instruction Fetch When trace buffer full Trace continue AUD mode AUD model Realtime trace C Non realtime trace AUD mode2 Trace continue Trace stop AUD Trace Memory Size oO so Mbyte AUD trace display range Start pointer D 255 End pointer D O Display Type Not Shared V GPUO M cpu M DMAG F Cancel Figure 2 2 Trace mode Page R20UT0366EJ0300 Rev 3 00 Page 37 of 50 Nov 18 2010 2tENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Select the AUD Trace CPU0 and AUD Trace CPU1 pages for tracing execution of CPU0 and CPU1 respectively a Branch Trace Function The branch source and destination addresses and their source lines are displayed Setting Method i Select the AUD Trace CPU0 page or the AUD Trace CPU1 page ii Branch trace can be acquired by selecting the Branch trace check box in the Trace Settings group box The branch type can be selected in the Branch trace group box R20UT0366EJ0300 Rev 3 00 Page 38 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Acquisition Trace mode AUD Trace CPUO
4. 16 Specify the size of the trace buffer of the emulator within the memory size Mbyte range of the 0 25 to 16 Mbyte The AUD trace acquisition mode is set in the AUD model AUD mode2 and AUD Trace Memory Size group boxes on the Trace mode page of the Acquisition dialog box The contents to be displayed in the Trace window can be selected from table 2 18 according to the item of Display Type The item of Display Type can be set separately by the both CPUs R20UT0366EJ0300 Rev 3 00 Page 35 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 18 Contents to be Displayed in the Trace Window Type Description CPUO check box Displays the contents including the CPUO operation among the acquired trace information CPU1 check box Displays the contents including the CPU1 operation among the acquired trace information DMAC check box Displays the contents including the DMAC operation among the acquired trace information R20UT0366EJ0300 Rev 3 00 Page 36 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Acquisition Trace mode AUD Trace CPUO AUD Trace CPUN m Trace type C Trace AUD function l Trace mode hannel 1 Ch el 2 M Bus amp Branch CPUO None Acquisition Acquisition JV Read I Read
5. AUD Trace CPU1 Trace Settings V Branch trace Window trace Channel 4 M Channel B I Software trace Branch Trace MV Acquire normal branch instruction trace MV Acquire subroutine branch instruction trace V Acquire exception branch instruction trace Window Trace C Read C Write Read Write Read Write C Read C Write Read Write Start address H0 End address Ho Bus state M Bus x Figure 2 3 Setting Branch Trace in the AUD Trace CPU0 Page R20UT0366EJ0300 Rev 3 00 Page 39 of 50 Nov 18 2010 2tENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 b Window Trace Function Memory access in the specified range can be acquired by trace Two memory ranges can be specified for channels A and B The read write or read write cycle can be selected as the bus cycle for trace acquisition Setting Method i Select the AUD Trace CPU0 page or the AUD Trace CPU1 page ii Select the Window trace check box in the Trace Settings group box iti Select the Channel A and Channel B check boxes in the Trace Settings group box Each channel will become valid iv Specify the bus cycle memory range bus type and bus type to be set for each channel R20UT0366EJ0300 Rev 3 00 Page 40 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications wh
6. Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 7F No 363 Fu Shing North Road Taipei Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 1 harbourFront Avenue 06 10 keppel Bay Tower Singapore
7. address in which an exception occurs is acquired Set the AUD clock AUDCK frequency to 50 MHz or lower If the frequency is higher than 50 MHz the emulator will not operate normally The AUD clock can be set in the Configuration dialog box 6 If breaks occur immediately after executing non delayed branch and TRAPA instructions and generating a branch due to exception or interrupt a trace for one branch will not be acquired R20UT0366EJ0300 Rev 3 00 Page 42 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 immediately before such breaks However this does not affect on generation of breaks caused by a BREAKPOINT and a break before executing instructions of Event Condition 7 By default a maximum of 131070 lines 65535 branches can be shown in the trace display of this emulator If a larger number of lines is to be acquired switch the display range by modifying the value of the start pointer and end pointer in the AUD Trace display range box on the Trace mode page of the Acquisition dialog box 8 When the traces for both CPUO and CPU1 are being displayed at the same time do not select supplementation of branch trace information 2 2 4 Note on Using the JTAG H UDI Clock TCK 1 Set the JTAG clock TCK frequency to lower than the frequency of the peripheral module clock 2 The initial value of the JTAG clock TCK is 5 00 MHz 3 A val
8. of signal levels and may damage the user system R20UT0366EJ0300 Rev 3 00 Page 7 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 1 Connecting the Emulator with the User System 1 5 2 Recommended Circuit 38 Pin Type Figure 1 5 shows a recommended circuit for connection between the H UDI and AUD port connectors 38 pins and the MCU when the emulator is in use Notes 1 2 10 11 Do not connect anything to the N C pins of the H UDI port connector The ASEMD pin must be 0 when the emulator is connected and when the emulator is not connected respectively 1 When the emulator is used ASEMD 0 2 When the emulator is not used ASEMD 1 Figure 1 5 shows an example of circuits that allow the ASEMD pin to be GND 0 whenever the emulator is connected by using the user system interface cable When the ASEMD pin is changed by switches etc ground pin 3 Do not connect this pin to the ASEMD pin When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The pattern between the H UDI port connector and the MCU must be as short as possible Do not connect the signal lines to other components on the board The AUD signals AUDCK AUDATA3 to AUDATAO and AUDS YNC operate in high speed Isometric connection is needed if possible Do not separate connection nor connect other signal lines adjacently Since the H UDI and the AUD
9. of the MCU operate with the PVcc supply only the PVcc to the UVCC pin The resistance value shown in figure 1 5 is for reference For the AUDCK pin guard the pattern between the H UDI port connector and the MCU at GND level The TRST pin must be at the low level for a certain period when the power is supplied whether the H UDI is used or not The GND bus lead at the center of the H UDI port connector must be grounded For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MCU R20UTO366EJ0300 Rev 3 00 Page 8 of 50 Nov 18 2010 2tENESAS SuperH Family E10A USB Emulator Section 1 Connecting the Emulator with the User System PVcc l O power supply All pulled up at 4 7 kQ PVcc PVcc PVcc H UDI port connector 38 pin type SH7265 SH7205 AUDCK AUDSYNC AUDSYNC AUDATAO AUDATAO AUDATA1 AUDATA1 AUDATA2 28 AUDATA2 AUDATAS 24 AUDATA3 TCK TMS TRST TDI TDO ASEBRKAK ASEBRKAK ASEBRK ASEBRK ASEMD GND UVCC UVCC_AUD UCON GND Power on GND GND BUS Leads reset 1 2 4 7 Notes 1 Open drain buffer 10 13 16 18 P i i 20 22 23 25 27 29 2 The given resistor values are reference values 31 33 34 35 36 37 38 Select the appropriate values according to the characteristics of the user system Figure 1 5 Recommended Circuit for Connection between the H UDI Port Connector and MCU when the Emulator is in Use 38 Pin Type R20UT0366EJ0300
10. program is continuously executed becomes full Break CPUO Break in execution of the user program on the CPUO side Break CPUO Break in execution of the user program on the CPU1 side Break CPUO Break in execution of the user program on both the CPUO CPU1 and CPU1 sides The contents to be displayed in the Trace window can be selected from table 2 14 according to the Display Type item The Display Type item can be set separately in the High performance Embedded Workshop for each CPU Table 2 14 Contents to be Displayed in the Trace Window Type Description CPUO check box Displays the contents including the CPUO operation among the acquired trace information CPU1 check box Displays the contents including the CPU1 operation among the acquired trace information DMAC check box Displays the contents including the DMAC operation among the acquired trace information After selecting Channel 1 or Channel 2 of I Trace mode select the content to be acquired from Acquisition Typical examples are described below note that items disabled for Acquisition are not acquired e Example of acquiring only 1024 step branch information executed in CPUO Select M Bus amp Branch CPU0 from Channel 1 and enable Branch on Acquisition Select None from Channel 2 R20UT0366EJ0300 Rev 3 00 Page 30 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specification
11. read e If the cache is hit the corresponding position in the data array is read e If the cache is not hit a single read from the external area is performed The instruction cache is not searched for The contents of the address array are not changed before or after reading of memory BREAKPOINT The V and LRU bits for all entries in the instruction cache are cleared to 0 when a BREAKPOINT is set or canceled Also the V and LRU bits for all entries in the instruction cache for the other core are cleared to 0 The V and LRU bits for all entries in the instruction cache are cleared to 0 when a break occurs after a BREAKPOINT has been set Also the V and LRU bits for all entries in the instruction cache for the other core are cleared to 0 Use the Event Condition if you do not wish to change the contents of the instruction cache R20UT0366EJ0300 Rev 3 00 Nov 18 2010 RENESAS Page 14 of 50 SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Function Operation Notes Program load After loading of the program has been completed the contents of the operand cache are written to external memory and the V and LRU bits of all entries in the instruction and operand caches are cleared to 0 Furthermore in the case of a break in execution by the other core the V and LRU bits for all entries in the instruction cache for the other core are cleared to
12. the SR register is changed in the Registers window it is actually reflected in that register immediately before execution of the user program is started It also applies when the value is changed by the REGISTER_SET command 2 The emulator uses the H UDI do not access the H UDI R20UT0366EJ0300 Rev 3 00 Page 11 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 3 Low Power States The single processor state can be cleared with either the STOP button or a break after satisfaction of the conditions of the Event Condition function and a break will then occur The dual sleep state can be cleared with either the STOP button or a break after satisfaction of the conditions of the Event Condition function and a break will then occur When Sleep is selected for Standby Mode in the Configuration dialog box the software standby and deep standby states become the dual sleep state Accordingly the state can be cleared with either the STOP button or a break after satisfaction of the conditions of the Event Condition function and a break will then occur When Standby is selected for Standby Mode in the Configuration dialog box the software standby and deep standby states transit to their respective standby states as does the MCU The memory must not be accessed or modified in the software standby state and a break should not be g
13. 0 If memory is read from or written to the disabled cache area cache is not searched for but the external area is accessed Do not update the cache while the user program is being executed Notes 1 The CPU on the side which wrote to the memory handles the above operations after writing is completed However the other side for which a program was not loaded will not perform the operations even if caching is enabled When updating of the cache is required write the memory on both the CPUO side and CPU1 side or flash the cache by setting the control register for the cache in the CPU which did not write the memory 2 Ifthe CPU on the side which did not write to the memory was operating the V and LRU bits for all entries in the instruction cache are not cleared The contents of the instruction caches on the CPUO and CPU1 sides may not match 3 Ifthe CPU on the side which did not write to the memory was operating the V and LRU bits for all entries in the instruction and operand caches are not cleared The contents of the instruction and operand caches on the CPUO and CPU1 sides may not match 9 Multiplexing the AUD Pins The AUD pins are multiplexed as shown in table 2 5 R20UT0366EJ0300 Rev 3 00 Page 15 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 5 Multiplexed Functions MCU Function 1 Function 2 SH7265 PJ5 VIDA
14. 098632 Tel 65 6213 0200 Fax 65 6278 8001 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2007 2009 2010 Renesas Electronics Corporation and Renesas Solutions Corp All rights reserved Colophon 1 0 SuperH Family E10A USB Emulator for Multi core Additional Document for User s Manual Supplementary Information on Using the SH7265 and SH7205 RENESAS Renesas Electronics Corporation Previous Number REJ10J1767 0200
15. 2rCENESAS E 7 D mL T lt D 3 D SuperH Family E10A USB Emulator for Multi core Additional Document for User s Manual Supplementary Information on Using the SH7265 and SH7205 SuperH Family E10A USB for SH7265 HS7265KCU04HE All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corporation without notice Please review the latest information published by Renesas Electronics Corporation through various means including the Renesas Electronics Corporation website http www renesas com Renesas Electronics www renesas com Rev 3 00 Nov 2010 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics prod
16. A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 2 Displaying the measured result The measured result is displayed in the Performance Analysis window or the PERFORMANCE_ANALYSIS command with hexadecimal 32 bits Note Ifa performance counter overflows as a result of measurement will be displayed 3 Initializing the measured result To initialize the measured result select Initialize from the popup menu in the Performance Analysis window or specify INIT with the PERFORMANCE_ANALYSIS command R20UT0366EJ0300 Rev 3 00 Page 49 of 50 Nov 18 2010 7tENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 2 3 Table 2 21 No Notes on SH7265 and SH7205 E10A USB Emulator Notes Function Name Note 1 The external flash memory When using the emulator to program the external flash memory break execution by both CPUs beforehand Software break Do not set the software break to the same address from the High performance Embedded Workshop for the CPUO side and the one for the CPU1 side When software breaks are in use the execution stepping and break buttons in the Synchronized Debug Function group box of the Synchronized Debug window should be all available Event Condition Operations on one High performance Embedded Workshop should not proceed while the Event condition dialog box on t
17. L20 ASEBRK 2 Output TMS Input TDI Input RES Output User reset N C GND _ 11 UVCC Output 10 12 13 GND 14 GND Output Notes 1 Input to or output from the user system 2 The symbol means that the signal is active low 3 The emulator monitors the GND signal of the user system and detects whether or not the user system is connected 4 When the user system interface cable is connected to this pin and the ASEMD pin is set to 0 do not connect to GND but to the ASEMD pin directly Pin 1 mark Nn H UDI port connector top view H UDI port connector top view i 1 mark Figure 1 2 Pin Assignments of the H UDI Port Connector 14 Pins R20UT0366EJ0300 Rev 3 00 Page 4 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 1 Connecting the Emulator with the User System Input SH7265 inp SH7265 Signal tout SH7205 Note 1 SH7205 9 Output Pin No Output Pin No N C N C 4 ASEMD GND N C N C N C UCON GND AUDAT Output Y11 AUDCK Output N C N C AUDAT Output ASEBRKAK Input N C ASEBRK 2 Output RES Output User reset AUDAT Output N C N C TDO Output AUDAT Output UVCC_AUD Output N C N C AUDSYNC Output UVCC Output N C TCK Input N C N C N C TMS N C N C N C TDI Input H20 N C 1 Input to or output from the use
18. REAKPOINT software break to the same address When the emulator is being connected the user break controller UBC function is not available When DMA is selected as the bus condition specify either Read or Write as the Read and Write conditions i e do not specify both Read and Write at the same time 2 2 3 Trace Functions The emulator supports the trace functions listed in table 2 10 Table 2 10 Trace Functions Function Internal Trace AUD Trace Branch trace Supported Supported Memory access trace Supported Supported Software trace Supported Supported R20UT0366EJ0300 Rev 3 00 Page 26 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Internal Trace Function Right click on the Trace window to produce the pop up menu and then select Settings The Acquisition dialog box will be opened When I Trace is selected for Trace type on the Trace mode page of the Acquisition dialog box the internal trace can be used Acquisition Trace mode Trace type Trace C AUD function Trace mode Channel 1 Channel 2 M Bus amp Branch CPUO E M Bus amp Branch CPUT E Acquisition Acquisition V Read v Read v Write JV Write IV PG relative addressing IV PC relative addressing V Branch V Branch V Software V Software MV Data access V Data access ia jz When trace buffer full Trace continue Sa Display Type Not S
19. Read Watchdog timer counter WRCSRO W Write Watchdog reset control status register WRCSR1 W Write Watchdog reset control status register WRCSRO R Read Watchdog reset control status register WRCSR1 R Read Watchdog reset control status register Customization of the I O register definition file After the I O register definition file lt device name gt io is created the MCU s specifications may be changed If each I O register in the I O register definition file differs from addresses described in the hardware manual change the I O register definition file according to the description in the hardware manual The I O register definition file can be customized depending on its format However the emulator does not support the bit field function Verify In the IO window the verify function of the input value is disabled 13 Illegal Instructions Do not execute illegal instructions with STEP type commands 14 Reset Input During execution of the user program the emulator may not operate correctly if a contention occurs between the following operations for the emulator and the reset input to the target device Setting an Event Condition Setting an internal trace Displaying the content acquired by an internal trace Reading or writing of a memory Note that those operations should not contend with the reset input to the target device R20UT0366EJ0300 Rev 3 00 Page 17 of 50 Nov 18 2010 RENESAS S
20. Rev 3 00 Page 9 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 1 Connecting the Emulator with the User System CAUTION Do not issue a reset signal when the open drain buffer is not in use Doing so will cause a conflict of signal levels and may damage the user system R20UT0366EJ0300 Rev 3 00 Page 10 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Section 2 Software Specifications when Using the SH7265 and SH7205 2 1 Differences between the MCU and the Emulator 1 When the emulator system is initiated it initializes the general registers and part of the control registers as shown in table 2 1 The initial values of the MCU are undefined When the emulator is initiated from the workspace a value to be entered is saved in a session Table 2 1 Register Initial Values at Emulator Link Up Register Emulator at Link Up RO to R14 H 00000000 R15 SP Value of the SP in the power on reset vector table PC Value of the PC in the power on reset vector table SR H 000000F0 GBR H 00000000 VBR H 00000000 TBR H 00000000 MACH H 00000000 MACL H 00000000 PR H 00000000 FPSCR H 00040001 FPUL H 00000000 FPRO 15 H 00000000 Note If the MCU does not incorporate the floating point unit FPU these registers are not displayed Note When a value of the interrupt mask bit in
21. Section 1 Connecting the Emulator with the User System 1 1 Components of the Emulator The E10A USB emulator supports the SH7265 and SH7205 Table 1 1 lists the components of the emulator Table 1 1 Components of the Emulator Classi Quan fication Component Appearance tity Remarks Hard Emulator box 1 Depth 68 0 mm Width 101 5 mm ware Height 22 7 mm Mass 66 9 g User system interface 1 14 pin type cable uo i owe dy Length 17 cm Mass 12 3 g User system interface 1 38 pin type cable eee a Length 20 cm Mass 10 8 g USB cable 1 Length 150 cm Mass 53 g Soft E10A USB emulator setup 1 HSOO005KCU04SR ware program CSD SuperH Family E10A HS0005KCU04HJ USB Emulator Users HSOOOSKCUO4HE Manual Supplementary HS7265KCU04Hu Information on Using the HS7265KCU04HE SH7265 and SH7205 HS0005TM04HJ and and Test program manual HS0005TM04HE for HS0005KCU04H and HS0005KCU14H Provided on the CD R Note Additional document for the MCUs supported by the emulator is included Check the target MCU and refer to its additional document R20UT0366EJ0300 Rev 3 00 Nov 18 2010 tENESAS Page 1 of 50 SuperH Family E10A USB Emulator Section 1 Connecting the Emulator with the User System 1 2 Connecting the Emulator with the User System To connect the E10A USB emulator hereinafter referred to as the emulator the H UDI port connector must be installed on the user system to connect the user s
22. TAO DACK3 DACT3 AUDCK SM72035 PJ6 VIDATA1 TEND3 AUDSYNG PJ7 VIDATA2 TIOCIA AUDATAO PJ8 VIDATA3 TIOC1B AUDATAt PJ9 VIDATA4 SSCK1 AUDATA2 PJT0 VIDATAS SSI1 AUDATA3 Note Function 1 can be used when the AUD pins of the device are not connected to the emulator The AUD pins are multiplexed with other pins When the AUD function is used by the emulator AUD pins are used regardless of the settings of the pin function controller PFC 10 Using WDT The WDT for the MCU where a break has occurred does not operate during break 11 Loading Sessions Information in JTAG clock of the Configuration dialog box cannot be recovered by loading sessions Thus the TCK value will be 5 00 MHz 12 1O Window Display and modification There are two registers to be separately used for write and read operations R20UT0366EJ0300 Rev 3 00 Nov 18 2010 RENESAS Page 16 of 50 SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 6 Register with Different Access Size Register Name Usage Register WTCSRO W Write Watchdog timer control status register WTCSR1 W Write Watchdog timer control status register WTCNTO W Write Watchdog timer counter WTCNT1 W Write Watchdog timer counter WTCSRO R Read Watchdog timer control status register WTCSR1 R Read Watchdog timer control status register WTCNTO R Read Watchdog timer counter WTCNT1 R
23. ales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics Regulatory Compliance Notices European Union regulatory notices This product complies with the following EU Directives These directives are only valid in the European Union CE Certifications Electromagnetic Compatibility EMC Directive 2004 108 EC EN 55022 Class A WARNING This is a Class A product In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures EN 55024 e Information for traceability e Authorised representative Name Renesas Electronics Corporation Address 1753 Shimonumabe Nakahara ku Kawasaki Kanagawa 211 8668 Japan e Manufacturer Name Renesas Solutions Corp Address Nippon Bldg 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan e Person responsible for placing on the market Name Renesas Electronics Europe Limited Address Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Environmental Compliance and Certifications e Waste Electrical and Electronic Equipment WEEE Di
24. delayed branch instruction the PC value becomes an illegal value Accordingly do not set a BREAKPOINT to the slot instruction of a delayed branch instruction If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area a mark will be displayed in the c area of the address on the Source or Disassembly window by refreshing the Memory window etc after Go execution However no break will occur at this address When the program halts with the event condition the mark disappears When synchronized stepped execution is in use with one CPU BREAKPOINTs set for the other CPU are invalid Do not set BREAKPOINTs at the same address for both CPUs 2 2 6 Notes on Setting the Event Condition Dialog Box and the BREAKCONDITION_SET Command When Go to cursor Step In Step Over or Step Out is selected in CPUO the settings of Event Condition 3 are disabled When Go to cursor Step In Step Over or Step Out is selected in CPU1 the settings of Event Condition 5 are disabled When an Event Condition is satisfied emulation may stop after two or more instructions have been executed 2 2 7 Performance Measurement Function The emulator supports the performance measurement function 1 Setting the performance measurement conditions To set the performance measurement conditions use the Performance Analysis dialog box and the PERFORMANCE_SET command When any line in the Performance Analysi
25. eing performed while the other core is executing the user program operation of the other core at the end of step execution depends on the setting for Break Halt Synchronized or non synchronized operation can be set as desired Connect Operation of the emulator in response to Connect is synchronized in all sessions Connection is always synchronized Non synchronized connection is not available R20UT0366EJ0300 Rev 3 00 Page 18 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Download Modules Operation of the emulator in response to Download Modules is synchronized in all sessions Downloading is always synchronized Non synchronized downloading is not available Initialize Operation of the emulator in response to Initialize is synchronized in all sessions Initialization is always synchronized Non synchronized initialization is not available Notes 1 If Master Debugger in the Synchronization Style group box of the Synchronized debug window is selected synchronization will not be performed i e the effect is the same as selecting None 2 In synchronized debugging if execution by one CPU is proceeding the other CPU cannot be connected or disconnected 3 If the following dialog box is displayed in one of the High performance Embedded Workshops during synchronized debugging in the parallel mode do not execute the user program
26. en Using the SH7265 and SH7205 Acquisition Trace mode AUD Trace CPUO AUD Trace CPU1 Trace Settings Branch trace IV Window trace V Channel V Channel B I Software trace peered E Branch Trace J Acquire normal branch instruction trace V Acquire subroutine branch instruction trace J Acquire exception branch instruction trace Window Trace Channel Read Write C Read C White Read Write Start address H O End address H O Bus state M Bus Channel B Read Write C Read C Write Read Write Start address End address Bus state Cancel Figure 2 4 Setting Window Trace in the AUD Trace CPU0 Page Note When M Bus or DMAC is selected the following bus cycles will be traced R20UT0366EJ0300 Rev 3 00 Page 41 of 50 Nov 18 2010 7tENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 e M Bus A bus cycle generated by the CPU is acquired A bus cycle is also acquired when the cache has been hit e DMAC A bus cycle generated by the DMA is acquired c Software Trace Function Note This function is supported with SHC C compiler manufactured by Renesas Electronics Corp including OEM and bundle products V7 0 or later A software trace can be used by describing the Trace x function x is a variable name which is compiled and linked on the C source line
27. en set break and trace acquisition will be halted if the sequential condition is satisfied for the specified count 2 Ifa reset point is satisfied the satisfaction of the condition set in Event Condition will be disabled For example if the condition is satisfied in the order of Event Condition 3 2 reset point 1 the break or trace acquisition will not be halted If the condition is satisfied in the order of Event Condition 3 2 reset point 3 2 1 the break and trace acquisition will be halted 3 If the start condition is satisfied after the end condition has been satisfied by measuring performance performance measurement will be restarted For the measurement result after a break the measurement results during performance measurement are added R20UT0366EJ0300 Rev 3 00 Nov 18 2010 Page 24 of 50 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 4 lf the start condition is satisfied after the end condition has been satisfied by the point to point of the internal trace trace acquisition will be restarted 5 When a sequential condition is satisfied the CPU core in which a break will occur is CPUO or CPU1 specified by the Action page of the Event Condition Usage Example of Sequential Break Extension Setting A tutorial program provided for the product is used as an example For the tutorial program refer to section 6 Tutorial in the SuperH Fa
28. enerated The memory must not be accessed or modified in the deep standby state and a break should not be generated When the emulator is in use the state is in pseudo deep standby The operation of registers whose values are held or updated is the same as in the deep standby state of the MCU However the power is not shut down only the clock is halted Do not stop the clock input to the H UDI module by using the module standby function 4 Reset Signals The MCU reset signals are only valid in the emulation state while both of CPUs are being executed If one of CPUs is in a break state reset signals are not sent to the MCU Note Do not break the user program when the RES or WAIT signal is being low A TIMEOUT error will occur If the WAIT signal is fixed to low during break a TIMEOUT error will occur at memory access 5 Direct Memory Access Controller DMAC The DMAC operates even when the emulator is used When a data transfer request is generated the DMAC executes DMA transfer 6 Memory Access during User Program Execution During execution of the user program memory is accessed by the following two methods as shown in table 2 2 each method offers advantages and disadvantages R20UT0366EJ0300 Rev 3 00 Page 12 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 2 Memory Access during User Program Execution Meth
29. essly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor produc
30. formance measurement period Performance For CPUO performance measurement the period from the Ch1 to Ch2 satisfaction of the condition set in Event Condition 1 start PtoP for CPUO condition to the satisfaction of the condition set in Event Condition 2 end condition is set as the performance measurement period Other than The period from the start of execution of the user program to the above occurrence of a break is measured Selection in Performance For CPU1 performance measurement the period from the the Ch7 8 Ch8 to Ch7 satisfaction of the condition set in Event Condition 8 start list box PtoP for CPU1 condition to the satisfaction of the condition set in Event Condition 7 end condition is set as the performance measurement period Performance For CPU1 performance measurement the period from the Ch7 to Ch8 satisfaction of the condition set in Event Condition 7 start PtoP for CPU1 condition to the satisfaction of the condition set in Event Condition 8 end condition is set as the performance measurement period Other than above The period from the start of execution of the user program to the occurrence of a break is measured R20UT0366EJ0300 Rev 3 00 Nov 18 2010 Page 45 of 50 2tENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Performance Analysis Condition GPUO Channel 1 z Channel 2 Disabled Channel 3 Disabled Cha
31. formance measurement start or end condition is enabled for CPU1 The Event Condition 11 dialog box is used to specify the count of Event Condition 1 and becomes a reset point when the sequential condition is specified R20UT0366EJ0300 Rev 3 00 Page 22 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Sequential Setting Using the Combination action Sequential or PtoP dialog box specifies the sequential condition and the start or end of performance measurement Table 2 9 Sequential Conditions in the Combination action Sequential or PtoP Dialog Box Classification Item Description Ch1 2 3 list box Sets the sequential condition and the start or end of performance measurement using Event Conditions 1 to 3 and 11 Don t care Sets no sequential condition or the start or end of performance measurement Break Ch3 2 1 Breaks when a condition is satisfied in the order of Event Condition 3 2 1 Break Ch3 2 1 Breaks when a condition is satisfied in the order of Reset point Event Condition 3 2 1 Enables the reset point of Event Condition 11 Break Ch2 1 Breaks when a condition is satisfied in the order of Event Condition 2 1 Break Ch2 1 Breaks when a condition is satisfied in the order of Reset point Event Condition 2 1 Enables the reset point l Trace stop Ch3 2 1 Halts acq
32. hared jv CPUO m CPU M DMAG E Cancel Figure 2 1 Acquisition Dialog Box Internal Trace Function R20UT0366EJ0300 Rev 3 00 Page 27 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 For the internal trace using Channel 1 or Channel 2 of I Trace mode enables acquisition of 512 step trace information on a different bus When only Channel 1 is used 1024 step trace information can be acquired The internal trace functions are common resources for CPUO or CPU1 and can be set from the High performance Embedded Workshop for either CPU For Channel 1 and Channel 2 it is possible to select a bus that acquires trace information among the items shown in table 2 11 Table 2 11 Information on Acquiring the Internal Trace Item Acquisition Information Note M Bus amp Branch Acquires the data and branch information on the 7 CPUO M bus for CPUO e Data access read write e PC relative access e Branch information e Software trace l Bus CPUO Acquires the data on the I bus for CPUO e Data access read write e Instruction fetch F Bus CPUO Acquires the data on the F bus for CPUO e Instruction fetch M Bus amp Branch Acquires the data and branch information on the CPU1 M bus for CPU1 e Data access read write e PC relative access e Branch information e Software trace I Bus CPU1 Acqu
33. he other the High performance Embedded Workshop is open Close the Event condition dialog box before proceeding with operations on the other the High performance Embedded Workshop When DMA is selected as the bus condition specify either Read or Write as the Read and Write conditions i e do not specify both Read and Write at the same time Trace The traces for both CPUO and CPU1 are being displayed at the same time by selecting the buttons for both CPUs in the Display type group box of the Acquisition dialog box do not select supplementation of branch trace information Memory access during execution of the user program If a break has been generated for one CPU at a time when execution of the other CPU should be temporarily suspended by a short break for memory access execution of the CPU may continue despite generation of the short break Cache Do not update the cache while the user program is being executed Emulation with single core Be sure to connect the CPUO and CPU1 Emulation with only one CPU is not supported R20UT0366EJ0300 Rev 3 00 Nov 18 2010 Re Page 50 of 50 s lt ENESAS SuperH Family E10A USB Emulator for Multi core Additional Document for User s Manual Supplementary Information on Using the SH7265 and SH7205 Publication Date Rev 1 00 November 26 2007 Rev 3 00 November 18 2010 Published by Renesas Electronics Corporation RENESAS SALES OFFICES
34. ifications when Using the SH7265 and SH7205 Table 2 20 Measurement Item Selected Name Option Disabled None Elapsed time AC The number of execution cycles Id Branch instruction counts BT Number of execution instructions Number of execution 32bit instructions 132 Exception interrupt counts EA Interrupt counts INT Data cache miss counts DC Instruction cache miss counts IC All area access counts ARN All area instruction access counts ARIN All area data access counts ARND Cacheable area access counts CDN data access Cacheable area instruction access counts CIN Non cacheable area data access counts NCN URAM area access counts UN URAM area instruction access counts UIN URAM area data access counts UDN Internal I O area data access counts IODN All area access cycle ARC All area instruction access cycle ARIC All area data access cycle ARDC All area access stall ARS All area instruction access stall ARIS All area data access stall ARDS Note Selected names are displayed for CONDITION in the Performance Analysis window Options are parameters for lt mode gt of the PERFORMANCE_SET command Note In the non realtime trace mode of the AUD trace normal counting cannot be performed because the generation state of the stall or the execution cycle is changed R20UT0366EJ0300 Rev 3 00 Nov 18 2010 Page 48 of 50 RENESAS SuperH Family E10
35. in connector 2514 6002 3M Limited 14 pin straight type 38 pin connector 2 5767004 2 Tyco Electronics Corporation 38 pin Mictor type Note If you are using the 14 pin H UDI connector do not mount any other component within 3 mm of the user system connector and wiring runs to the MCU When designing the layout for the 38 pin connector on the user board reduce cross talk noise etc by keeping other signal lines out of the region where the H UDI port connector is situated As is shown in figure 1 1 an upper limit 5 mm applies to the heights of components mounted around the user system connector E10A USB Multi 38 pin Pa user system interface cable 37 1 Po et UUUUUUUUUNUUUUUUUUU 38 2 E Area to be kept free of other components 2 5767004 2 __ __ gt Target system H UDI port connector Figure 1 1 Restriction on Component Mounting 1 4 Pin Assignments of the H UDI Port Connector Figures 1 2 and 1 3 show the pin assignments of the 14 pin and 38 pin H UDI port connectors respectively Note Note that the pin number assignments of the H UDI port connector shown on the following pages differ from those of the connector manufacturer R20UT0366EJ0300 Rev 3 00 Page 3 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 1 Connecting the Emulator with the User System SH7265 Input 4 Signal SH7205 Output Pin No TCK Input J19 TRST Input K20 TDO Output J20 ASEBRKAK Input
36. in the other High performance Embedded Workshop Only proceed with further execution after closing the dialog box e Configuration dialog box e Performance Analysis dialog box e Acquisition dialog box e Event Condition dialog box 2 2 2 Event Condition Functions The emulator is used to set event conditions for the following three functions e Break of the user program e Internal trace e Start or end of performance measurement The Event Condition functions are common resources for CPUO or CPU1 and can be set from the High performance Embedded Workshop for either CPU R20UT0366EJ0300 Rev 3 00 Page 19 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 7 lists the types of Event Condition Table 2 7 Types of Event Condition Event Condition Type Description Address bus condition Address Sets a condition when the address bus data access value or the program counter value before or after execution of instructions is matched Data bus condition Data Sets a condition when the data bus value is matched Byte word or longword can be specified as the access data size Bus state condition There are two bus state condition settings Bus State Bus state condition Sets a condition when the data bus value is matched Read Write condition Sets a condition when the read write condition is matched C
37. ing a trace If a trace is displayed during execution of the program execution will be suspended to acquire the trace information The number of clocks to be suspended during execution of the program is the maximum is around 20480 peripheral clock P 4096 bus clock Bo The program will be suspended for 676 52u when the peripheral clock Po is 33 3MHz the bus clock B is 66 6MHz Branch trace If breaks occur immediately after executing non delayed branch and TRAPA instructions and generating a branch due to exception or interrupt a trace for one branch will not be acquired immediately before such breaks However this does not affect on generation of breaks caused by a BREAKPOINT and a break before executing instructions of Event Condition Writing memory immediately before generating a break If an instruction is executed to write memory immediately before generating a break trace acquisition may not be performed Displaying the Trace The Supplementation of Branch Trace Information The traces for both CPUO and CPU are being displayed at the same time do not select supplementation of branch trace information R20UT0366EJ0300 Rev 3 00 Page 34 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 AUD Trace Functions Right click on the Trace window to produce the pop up menu and then select Settings The Acquisition dialog box will be o
38. ires the data on the I bus for CPU1 e Data access read write e Instruction fetch F Bus CPU1 Acquires the data on the F bus for CPU1 e Instruction fetch R20UT0366EJ0300 Rev 3 00 Page 28 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 11 Information on Acquiring the Internal Trace cont Item Acquisition Information Note DMAC Acquires the access of the internal DMA bus e Internal DMA write bus access e Internal DMA read bus access Selected only for Channel 1 None Selects no acquisition information this item is only set when 1024 step trace information is acquired in Channel 1 Selected only for Channel 2 Note Itis not possible to select the same items for Channel 1 and Channel 2 Acquired information can be selected from the Acquisition item for the bus information specified for Channel 1 or Channel 2 Table 2 12 Acquired Information Item Description M bus l bus F bus Read Selects acquisition of the read Enabled Enabled Disabled cycle on the M bus or l bus Write Selects acquisition of the write Enabled Enabled Disabled cycle on the M bus or l bus PC relative addressing Selects acquisition of the PC Enabled Disabled Disabled relative access Branch Selects acquisition of branch Enabled Disabled Disabled information Software Selects acqu
39. isition of the software Enabled Disabled Disabled trace Data access Selects acquisition of the data Enabled Enabled Disabled access read or write on the M bus or l bus Instruction Fetch Acquires instruction fetch from the Disabled Enabled Enabled external area Note This function is supported with the SHC C compiler manufactured by Renesas Technology Corp V7 0 or later A software trace can be used by describing the Trace x function x is a variable name which is compiled and linked on the C source lines For details refer to the SHC manual When the load module is downloaded on the emulator and executed while a software trace function is valid the PC value that has executed the Trace x function the general register value for x and the source lines are displayed R20UT0366EJ0300 Rev 3 00 Nov 18 2010 RENESAS Page 29 of 50 SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 When the on chip trace buffer becomes full the operation is selected through When trace buffer full from the following modes Table 2 13 Operation Mode when the On Chip Trace Buffer Becomes Full Type Mode Description Acquisition Trace continue This function overwrites the oldest trace information to store mode when the latest trace information shee Trace stop After the trace buffer becomes full the trace information is no race Seer longer acquired The user
40. mily E10A USB Multi core Emulator User s Manual Notes 1 If the Event condition is set for the slot in the delayed branch instruction by the program counter after execution of the instruction the condition is satisfied before executing the instruction in the branch destination when a break has been set it occurs before executing the instruction in the branch destination 2 Do not set the Event condition for the SLEEP instruction by the program counter after execution of the instruction 3 When the Event condition is set for the 32 bit instruction by the program counter set that condition in the upper 16 bits of the instruction 4 If the power on reset and the Event condition are matched simultaneously no condition will be satisfied 5 Do not set the Event condition for the DIVU or DIVS instruction and the instruction followed by DIVU and DIVS by the program counter after execution of the instruction 6 Ifa condition of which intervals are satisfied closely is set no sequential condition will be satisfied e For the same core set the Event conditions which are satisfied closely by the program counter with intervals of two or more instructions e For the same core after the data access condition has been matched set the Event condition by the program counter with intervals of 17 or more instructions 7 Ifthe settings of the Event condition or the sequential conditions are changed during execution of the program execu
41. n to the ASEMD pin 3 When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances 4 The pattern between the H UDI port connector and the MCU must be as short as possible Do not connect the signal lines to other components on the board 5 Since the H UDI and the AUD of the MCU operate with the PVcc supply only the PVcc to the UVCC pin The resistance value shown in figure 1 4 is for reference The TRST pin must be at the low level for a certain period when the power is supplied whether the H UDI is used or not 8 For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MCU R20UT0366EJ0300 Rev 3 00 Page 6 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 1 Connecting the Emulator with the User System PVcc l O power supply All pulled up at 4 7 kQ PVcc PVcc PVcc PVcc PVcc PVcc H UDI port connector 14 pin type SH7265 SH7205 TCK GND TRST Oo T T TRST TDO od ASEBRKAK ASEBRK TMS TMS TDI RES Power on reset Open drain buffer The given resistor values are reference values Select the appropriate value for the individual user system Figure 1 4 Recommended Circuit for Connection between the H UDI Port Connector and MCU when the Emulator is in Use 14 Pin Type CAUTION Do not issue a reset signal when the open drain buffer is not in use Doing so will cause a conflict
42. ndition 2 0 1 and B T1 and P1 DMA Event Ch3 O X X X O O Condition 3 0 and 1 B and T2 Event Ch4 O X X X O O Condition 4 0 and 1 B and T3 Event Ch5 O X X X O O Condition 5 0 and 1 B and T3 Event Ch6 O xX X X O O Condition 6 0 and 1 B and T2 Event Ch7 O X X X O O Condition 7 0 and 1 B T2 and P2 Event Ch8 O X X X O O Condition 8 0 and 1 B T2 and P2 Event Ch9 O X X X O O Condition 9 0 and 1 B and T2 Event Ch10 O X X X O O Condition 10 0 and 1 B and T2 Event Ch11 O X X X O O Condition 11 reset point 0 and 1 B and T2 Notes 1 O Can be setin the dialog box X Cannot be set in the dialog box 2 For the CPU Select item 0 1 and DMA Setting a condition is enabled when CPUO CPU1 and internal DMA bus are accessed 0 and 1 Setting a condition is enabled when CPUO and CPU1 are accessed R20UT0366EJ0300 Rev 3 00 Page 21 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 3 4 For the Action item B Setting a break is enabled T1 Setting the trace halt and acquisition conditions are enabled for the internal trace T2 Setting the trace halt is enabled for the internal trace T3 Setting the trace halt and point to point is enabled for the internal trace P1 Setting a performance measurement start or end condition is enabled for CPUO P2 Setting a per
43. nnel 4 Disabled Channel 1 Disabled Channel 2 Disabled Channel Disabled Channel4 Disabled Canes Figure 2 5 Performance Analysis Dialog Box For measurement tolerance e The measured value includes tolerance e Tolerance will be generated before or after a break R20UT0366EJ0300 Rev 3 00 Page 46 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Notes 1 When Performance Ch2 to Chl PtoP for CPUO or Performance Ch1 to Ch2 PtoP for CPU0 is selected to execute the user program specify conditions set in Event Condition 2 and Event Condition 1 and one or more items for performance measurement Similarly when Performance Ch8 to Ch7 PtoP for CPU1 or Performance Ch7 to Ch8 PtoP for CPU1 is selected to execute the user program specify conditions set in Event Condition 8 and Event Condition 7 and one or more items for performance measurement 2 During user program execution the change of settings or the measurement items for the CPU cannot be displayed b Measurement item Items are measured by setting channels in the Performance Analysis dialog box A maximum of eight conditions four conditions for each of CPUO and CPU1 can be specified at the same time R20UT0366EJ0300 Rev 3 00 Page 47 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Spec
44. od Advantage Disadvantage H UDI read write The stopping time of the user Cache access is disabled Actual program is short because memory memory is always accessed by the is accessed by the dedicated bus H UDI read or write master When using the cache in write back mode values written are not reflected in the actual memory so the results of reading and writing by the H UDI will not be correct Short break Cache access is enabled The stopping time of the user program is long because the user program temporarily breaks Note Accessing memory to cache control registers 1 and 2 is fixed as a short break during execution of the user program The method for accessing memory during execution of the user program is specified by using the Configuration dialog box Table 2 3 Stopping Time by Memory Access Reference Method Condition Stopping Time H UDI read write Reading of one longword for the Reading Maximum three bus clocks internal RAM Bo Writing of one longword for the Writing Maximum two bus clocks internal RAM Bo Short break CPU clock 66 MHz About 70 ms JTAG clock 2 5 MHz Reading or writing of one longword for the external area 7 Memory Access to the External Flash Memory Area The emulator can download the load module to the external flash memory area for details refer to section 6 23 Download Function to the Flash Memory Area in the SuperH Family E10A USB Multi core Emulator User
45. oint to point of the internal trace the start or end condition of trace acquisition using Event Conditions 4 and 5 Don t care Sets no start or end condition of trace acquisition I Trace Ch5 to Ch4 PtoP Sets the acquisition period during the time from the satisfaction of the condition set in Event Condition 5 start condition to the satisfaction of the condition set in Event Condition 4 end condition I Trace Ch5 to Ch4 PtoP power on reset Sets the acquisition period during the time from the satisfaction of the condition set in Event Condition 5 start condition to the satisfaction of the condition set in Event Condition 4 end condition or the power on reset Ch7 8 list box Sets the start or end of performance measurement using Event Conditions 7 and 8 Performance Ch8 to Ch7 PtoP for CPU1 Sets the performance measurement period for CPU1 during the time from the satisfaction of the condition set in Event Condition 8 start condition to the satisfaction of the condition set in Event Condition 7 end condition Performance Ch7 to Ch8 PtoP for CPU1 Sets the performance measurement period for CPU1 during the time from the satisfaction of the condition set in Event Condition 7 start condition to the satisfaction of the condition set in Event Condition 8 end condition Notes 1 After the sequential condition and the count specification condition of Event Condition 1 have be
46. ondition 2 dialog box Address condition Set Address and H FFF80000 Bus state condition Set M Bus and Write CPU core condition Set CPUO Action condition Disable Acquire Break and set Acquire Trace for Stop R20UT0366EJ0300 Rev 3 00 Page 31 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 e Example of acquiring only write access M bus to H FFF80000 in CPUO by the user program trace acquisition condition Select M Bus amp Branch CPUO from Channel 1 and enable Write and Data access on Acquisition Set the following in the Event Condition 1 or Event Condition 2 dialog box Address condition Set Address and H FFF80000 Bus state condition Set M Bus and Write CPU core condition Set CPUO e Action condition Disable Acquire Break and set Acquire Trace for Condition For the trace acquisition condition the condition to be acquired by Event Condition should be acquired by I Trace mode e Example of acquiring a trace for the period while the user program executed in CPUO passes H 1000 through H 2000 point to point Set the condition to be acquired on I Trace mode Set the address condition as H 1000 in the Event Condition 5 dialog box and the CPU core condition as CPUO Set the address condition as H 2000 in the Event Condition 4 dialog box and the CPU core condition as CPUO
47. ount Sets a condition when the specified other conditions are satisfied for the specified counts CPU core condition Sets a condition when the CPU core CPUO and CPU1 or CPU Core Select the internal DMA bus internal DMA write bus and internal DMA read bus is accessed Reset point A reset point is set when the count and the sequential condition are specified Action Selects the operation when a condition such as a break a trace halt condition or a trace acquisition condition is matched For a break the CPU core in which a break will occur is selected Using the Combination action Sequential or PtoP dialog box which is opened by selecting Combination action Sequential or PtoP from the pop up menu on the Event Condition sheet specifies the sequential condition and the start or end of performance measurement Table 2 8 lists the combinations of conditions that can be set under Ch1 to Ch1 1 R20UT0366EJ0300 Rev 3 00 Page 20 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 8 Dialog Boxes for Setting Event Conditions Function Address Bus Data Bus Bus State Count CPU Core Condition Condition Condition Condition Condition CPU Dialog Box Address Data Bus Status Count Select Action Event Ch1 O O O O O O Condition 1 0 1 and B T1 and P1 DMA Event Ch2 O O O X O O Co
48. pened When AUD function is selected for Trace type on the Trace mode page of the Acquisition dialog box the internal trace can be used This function is operational when the AUD pin of the device is connected to the emulator The AUD trace functions are common resources for CPU0 or CPU1 and can be set from the High performance Embedded Workshop for either CPU Table 2 17 shows the AUD trace acquisition mode that can be set in each trace function Table 2 17 AUD Trace Acquisition Mode Type Mode Description Continuous Realtime trace When the trace information is being generated intensively that trace occurs the output from the AUD pin incapable of keeping up the CPU temporarily suspends the acquisition of trace information Therefore although the user program is run in real time the acquisition of some trace information might not be possible Non realtime When trace information is being generated so intensively that trace the output from the AUD pin is incapable of keeping up CPU operations are temporarily suspended and the output of trace information takes priority In such cases the realtime characteristics of the user program are lost Trace buffer Trace continue This function overwrites the oldest trace information to store the full latest trace information Trace stop After the trace buffer becomes full the trace information is no longer acquired The user program is continuously executed AUD trace 0 25 to
49. r system 2 The symbol means that the signal is active low 3 The emulator monitors the GND signal of the user system and detects whether or not the user system is connected 4 When the user system interface cable is connected to this pin and the ASEMD pin is set to 0 do not connect to GND but to the ASEMD pin directly 5 The GND bus lead at the center of the H UDI port connector must be grounded Unit mm H UDI port connector top view Figure 1 3 Pin Assignments of the H UDI Port Connector 38 Pins R20UT0366EJ0300 Rev 3 00 Page 5 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 1 Connecting the Emulator with the User System 1 5 Recommended Circuit between the H UDI Port Connector and the MCU 1 5 1 Recommended Circuit 14 Pin Type Figure 1 4 shows a recommended circuit for connection between the H UDI port connectors 14 pins and the MCU when the emulator is in use Notes 1 Do not connect anything to the N C pins of the H UDI port connector 2 The ASEMD pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used ASEMD 0 2 When the emulator is not used ASEMD 1 Figure 1 4 shows an example of circuits that allow the ASEMD pin to be GND 0 whenever the emulator is connected by using the user system interface cable When the ASEMD pin is changed by switches etc ground pin 9 Do not connect this pi
50. rective 2002 96 EC WEEE Marking Notice European Union Only Renesas development tools and products are directly covered by the European Union s Waste Electrical and Electronic Equipment WEEE Directive 2002 96 EC As a result this equipment including all accessories must not be disposed of as household waste but through your locally recognized recycling or disposal schemes As part of our commitment to environmental responsibility Renesas also offers to take back the equipment and has implemented a Tools Product Recycling Program for customers in Europe This allows you to return equipment to Renesas for disposal through our approved Producer Compliance Scheme To register for the program click here http www renesas com weee United States Regulatory notices on Electromagnetic compatibility FCC Certifications United States Only This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be requi
51. red to correct the interference at his own expense CAUTION Changes or modifications not expressly approved by the party responsible for compliance could void the user s authority to operate the equipment Table of Contents Section 1 Connecting the Emulator with the User System ou ccc cece ccseeseeecsecsesesseeeseseeesseseees 1 1 1 Components of the Emulator 1 2 Connecting the Emulator with the User System 1 3 Installing the H UDI Port Connector on the User System 1 4 Pin Assignments of the H UDI Port Connector 1 5 Recommended Circuit between the H UDI Port Connector and the MCU 1 5 1 Recommended Circuit 14 Pin Type 1 5 2 Recommended Circuit 38 Pin Type Section 2 Software Specifications when Using the SH7265 and SH7205 ccccceeese cee eeeeeeeeeeee 11 2 1 Differences between the MCU and the Emulator wi Ld 2 2 Specific Functions for the Emulator when Using the SH7265 and SH7205 18 2 2 1 Functions for Synchronized Debugging 18 2 2 2 Event Condition Functions 22 3 Trace Functions 2 2 4 Note on Using the JTAG H UDD Clock TCK 2 2 5 Notes on Setting the Breakpoint Dialog Box 2 2 6 Notes on Setting the Event Condition Dialog Box and the BREAKCONDITION_SET Command 22 7 Performance Measurement Function oe 2 3 Notes on SH7265 and SH7205 ELOA USB Emulator iere t ANEN TEATE A EAE 50 SuperH Family E10A USB Emulator Section 1 Connecting the Emulator with the User System
52. s window is clicked with the right mouse button a popup menu is displayed and the Performance Analysis dialog box can be displayed by selecting Setting The performance measurement functions are common resources for CPUO or CPU1 and can be set from the High performance Embedded Workshop for either CPU Setting channels of the CPUO group box measures performance of CPUO Similarly setting channels of the CPU1 group box measures performance of CPU1 Note For the command line syntax refer to the online help R20UT0366EJ0300 Rev 3 00 Page 44 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 a Specifying the measurement start end conditions For CPUO performance measurement the measurement start end conditions are specified by using Event Condition 1 2 For CPU1 performance measurement the measurement start end conditions are specified by using Event Condition 7 8 The Ch1 2 3 and Ch7 8 list boxes of the Combination action Sequential or PtoP dialog box can be used Table 2 19 Measurement Period Classification Item Description Selection in Performance For CPUO performance measurement the period from the the Ch1 2 3 Ch2 to Ch1 satisfaction of the condition set in Event Condition 2 start list box PtoP for CPUO condition to the satisfaction of the condition set in Event Condition 1 end condition is set as the per
53. s For details refer to the SHC manual When the load module is downloaded on the emulator and is executed while a software trace function is valid the PC value that has executed the Trace x function the general register value for x and the source lines are displayed Setting Method i Select the AUD Trace CPUO page or the AUD Trace CPU1 page ii Select the Software trace check box in the Trace Settings group box Notes on AUD Trace 1 When the trace display is performed during user program execution the mnemonics or operands is not displayed The AUD trace function outputs the differences between newly output branch source addresses and previously output branch source addresses The window trace function outputs the differences between newly output addresses and previously output addresses If the previous branch source address is the same as the upper 16 bits the lower 16 bits are output If it matches the upper 24 bits the lower 8 bits are output If it matches the upper 28 bits the lower 4 bits are output The emulator regenerates the 32 bit address from these differences and displays it in the Trace window If the emulator cannot display the 32 bit address it displays the difference from the previously displayed 32 bit address If the 32 bit address cannot be displayed the source line is not displayed Ifacompletion type exception occurs during exception branch acquisition the next address to the
54. s Manual When using the emulator to program the external flash memory break execution by both CPUs beforehand Only memory write operations other than downloading to the flash memory are possible for the RAM area Therefore an operation such as writing to memory setting of BREAKPOINTS and so on should only be for the RAM area R20UT0366EJ0300 Rev 3 00 Page 13 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 8 Operation while Cache is Enabled When cache is enabled the emulator operates as shown in table 2 4 Table 2 4 Operation while Cache is Enabled Function Operation Notes Memory write Look up proceeds to check whether or not the e The contents of the instruction or operand cache is hit for the address to be written e Ifa cache is hit the corresponding position in the data array is changed to the data being written and a single write to the external area is performed e Ifthe cache is not hit the contents of the cache are not changed and a single write to the external area is performed Furthermore in the case of a break in execution by the other core the V and LRU bits for all entries in the instruction cache for the other core are cleared to 0 address array are not changed before or after writing of memory Memory read Look up proceeds to check whether or not the operand cache is hit for the address to be
55. s when Using the SH7265 and SH7205 Example of acquiring only 1024 step read or write access M bus in CPUO by a user program Select M Bus amp Branch CPUO from Channel 1 and enable Read Write and Data access on Acquisition Select None from Channel 2 Example of acquiring only 1024 step read access by DMA Select DMAC from Channel 1 and enable Read on Acquisition Select None from Channel 2 Using Event Condition restricts the condition the following three items are set as the internal trace conditions Table 2 15 Trace Conditions of the Internal Trace Item Acquisition Information Trace halt Acquires the internal trace until the Event Condition is satisfied The trace content is displayed in the Trace window after a trace has been halted No break occurs in the user program Trace acquisition Acquires only the data access where the Event Condition is satisfied Point to point Traces the period from the satisfaction of Event Condition 5 to the satisfaction of Event Condition 4 To restrict trace acquisition to access for only a specific address or specific function of a program an Event Condition can be used Typical examples are described below Example of halting a trace with a write access M bus to H FFF80000 in CPUO by the user program as a condition trace halt Set the condition to be acquired on I Trace mode Set the following in the Event Condition 1 or Event C
56. t is not executed although it has been fetched at a branch or transition to an interrupt tracing is started during overrun fetching of the instruction However when overrun fetching is achieved a branch is completed tracing is automatically suspended If the start and end conditions are satisfied closely trace information will not be acquired correctly The execution cycle of the instruction fetched before the start condition is satisfied may be traced When the I bus is acquired do not specify point to point When a memory access is generated immediately or several instructions before the point to point condition for ending the internal trace is satisfied acquisition of the internal trace information might not be possible R20UT0366EJ0300 Rev 3 00 Page 33 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Halting a trace Do not set the trace halt condition for the sleep instruction and the branch instruction that the delay slot becomes the sleep instruction Trace acquisition condition If the settings of I Trace mode are changed during execution of the program execution will be suspended The number of clocks to be suspended during execution of the program is the maximum is around 51 peripheral clock P 15 bus clock Bo The program will be suspended for 1 7571 when the peripheral clock Pd is 33MHz the bus clock Po is 66MHz Display
57. tion will be suspended The number of clocks to be suspended during execution of the program is 102 bus clocks BQ If the bus clock Bo is 66 6 MHz the program will be suspended for 1 53 us 8 Ifthe settings of Event conditions or the sequential conditions are changed during execution of the program the emulator temporarily disables all Event conditions to change the settings During this period no Event condition will be satisfied R20UT0366EJ0300 Rev 3 00 Page 25 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 9 If the break condition before executing an instruction is set to the instruction followed by DIVU and DIVS the factor for halting a break will be incorrect under the following condition If a break occurs during execution of the above DIVU and DIVS instructions the break condition before executing an instruction which has been set to the next instruction may be displayed as the factor for halting a break 10 If the break conditions before and after executing instructions are set to the same 11 12 13 address the factor for halting a break will be incorrectly displayed The factor for halting a break due to the break condition after executing an instruction will be displayed even if a break is halted by the break condition before executing an instruction Do not set the break condition after executing instructions and B
58. ts have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics s
59. ucts or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations
60. ue to be set for the JTAG clock TCK is initialized after executing Reset CPU or Reset Go Thus the TCK value will be the initial value 2 2 5 Notes on Setting the Breakpoint Dialog Box 1 In synchronized debugging a breakpoint can be set only when the Synchronization options shown below are set e Synchronization of all debuggers is set under Synchronization style e The check boxes for Go Break Halt and Step in the Synchronized Debug Function group box are all selected 2 When an odd address is set the next lowest even address is used 3 A BREAKPOINT is accomplished by replacing instructions of the specified address It cannot be set to the following addresses An area other than CS and the internal RAM An instruction in which Break Condition 2 is satisfied A slot instruction of a delayed branch instruction 4 The specification of BREAKPOINTs and Event Condition breaks is disabled for a CPU that is performing stepped execution 5 When execution resumes from the address where a BREAKPOINT is specified and a break occurs before Event Condition execution single step operation is performed at the address before execution resumes Therefore realtime operation cannot be performed R20UT0366EJ0300 Rev 3 00 Page 43 of 50 Nov 18 2010 RENESAS 6 SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 When a BREAKPOINT is set to the slot instruction of a
61. uisition of an internal trace when a condition is satisfied in the order of Event Condition 3 2 1 I Trace stop Ch3 2 1 Reset point Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 3 2 1 Enables the reset point l Trace stop Ch2 1 Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 2 1 I Trace stop Ch2 1 Reset point Halts acquisition of an internal trace when a condition is satisfied in the order of Event Condition 2 1 Enables the reset point Performance Ch2 to Chi PtoP for CPUO Sets the performance measurement period for CPUO during the time from the satisfaction of the condition set in Event Condition 2 start condition to the satisfaction of the condition set in Event Condition 1 end condition R20UT0366EJ0300 Rev 3 00 Nov 18 2010 Page 23 of 50 2tENESAS SuperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2 9 Conditions to Be Set cont Classification Item Description Ch1 2 3 list box cont Performance Ch1 to Ch2 PtoP for CPUO Sets the performance measurement period for CPUO during the time from the satisfaction of the condition set in Event Condition 1 start condition to the satisfaction of the condition set in Event Condition 2 end condition Ch4 5 list box Sets the p
62. uperH Family E10A USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 2 2 Specific Functions for the Emulator when Using the SH7265 and SH7205 2 2 1 Functions for Synchronized Debugging For use with the E10A USB the following facilities for synchronization of debugging are available in the Synchronized Debug Function group box of the Synchronized Debug window Reset Operations in response to the Reset CPU and Reset Go functions are synchronized For synchronization of the response to the Reset Go function the Go check box must also should be checked Response to the reset function is always synchronized and non synchronized operations are not available Go Operations in response to the Go and Reset Go functions are synchronized For synchronization of the response to the Reset Go function the Reset check box must also should be checked Synchronized or non synchronized operation can be set as desired Break Halt Operations in response to a device break and selection of the Halt Program function are synchronized Selection of synchronized or non synchronized operation in response to individual types of break is not possible Synchronized or non synchronized operation in response to breaks in general and to selection of the Halt Program can be set as desired Step Operations in response to the various functions for step execution are synchronized When synchronized stepping is b
63. ystem interface cable When designing the user system refer to the recommended circuit between the H UDI port connector and the MCU In addition read the E10A USB emulator user s manual and hardware manual for the related device Table 1 2 shows the type number of the emulator the corresponding connector type and the use of AUD function Table 1 2 Type Number AUD Function and Connector Type Type Number Connector AUD Function HS0005KCU04H HS0005KCU14H 14 pin connector Not Available HS0005KCU04H HS0005KCU14H 38 pin connector Available The H UDI port connector has the 14 pin and 38 pin types as described below Use them according to the purpose of the usage 1 14 pin type without AUD interface The H UDI function is supported The AUD function is not available 2 38 pin type with AUD interface This connector supports AUD tracing through which a large amount of trace information can be acquired in realtime It also supports window tracing i e acquisition of the addresses and data involved in access to a specified area of memory R20UT0366EJ0300 Rev 3 00 Page 2 of 50 Nov 18 2010 RENESAS SuperH Family E10A USB Emulator Section 1 Connecting the Emulator with the User System 1 3 Installing the H UDI Port Connector on the User System Table 1 3 shows the recommended H UDI port connectors for the emulator Table 1 3 Recommended H UDI Port Connectors Connector Type Number Manufacturer Specifications 14 p

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