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MPC106 PCI Bridge/Memory Controller Hardware Specifications

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1. 66 6 133 0101 2 1 x4 33 3 133 40 160 50 200 0110 5 22 x2 83 3 166 0111 5 22 x4 41 6 166 1000 3 1 x2 60 120 75 150 0011 PLL bypass PLL off SYSCLK clocks core circuitry directly 1x core SYSCLK ratio implied 1111 Clock off 4 PLL off no core clocking occurs otes PLL 0 3 settings not listed are reserved Some PLL configurations may select bus CPU or VCO frequencies which are not useful not supported or not tested See Section 1 4 2 1 Clock AC Specifications for valid SYSCLK and VCO frequencies 5 2 clock modes are only supported by MPC106 Rev 4 0 earlier revisions do not support 5 2 clock modes The 5 2 modes require a 60x bus clock applied to the 60x clock phase LBCLAIM configuration input signal during power on reset hard reset and coming out of sleep and suspend power saving modes In PLL bypass mode the SYSCLK input signal clocks the internal circuitry directly the PLL is disabled and the core SYSCLK ratio is set for 1 1 mode operation This mode is intended for factory use and third party tool vendors only Note also The AC timing specifications given in this document do not apply in PLL bypass mode In clock off mode no clocking occurs inside the MPC106 regardless of the SYSCLK input MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Desig
2. 4 Except TS and ARTRY AS a SYSCLK vM mn Ea ALL la PCI OUTPUTS VM Midpoint Voltage 1 4V Figure 5 Output Timing Diagram 1 4 3 JTAG AC Timing Specifications Table 9 provides the JTAG AC timing specifications Assume Vdd AVdd 3 3 5 V DC GND 0 V DC CL 50 pF and 0 lt Tj lt 105 C Table 9 JTAG AC Timing Specifications Independent of SYSCLK Num Characteristic Min Max Unit Notes TCK frequency of operation 0 25 MHz 1 TCK cycle time 40 ns _ 2 TCK clock pulse width measured at 1 4 V 20 ns 3 TCK rise and fall times 0 3 ns 1 4 TRST setup time to TCK rising edge 10 ns 2 5 TRST assert time 10 ns 1 12 MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Table 9 JTAG AC Timing Specifications Independent of SYSCLK Continued Num Characteristic Min Max Unit Notes 6 Boundary scan input data setup time 5 ns 3 7 Boundary scan input data hold time 15 ns 3 TCK to output data valid 0 30 ns 4 TCK to output high impedance 0 30 ns 4 10 TMS TDI data setup time 5 ns 11 TMS TDI data hold time 15 ns 1 12 TCK to TDO data valid 0 15 ns 13 TCK to TDO high i
3. 10 V DC 1 4 Electrical and Thermal Characteristics This section provides both the AC and DC electrical specifications and thermal characteristics for the 106 1 4 1 DC Electrical Characteristics The tables in this section describe the 106 DC electrical characteristics Table 1 provides the absolute maximum ratings Functional and tested operating conditions are given in Table 2 Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed Stresses beyond those listed may affect device reliability or cause it permanent damage Table 1 Absolute Maximum Ratings Characteristic Symbol Value Unit Notes Supply voltage Vdd 0 3 to 3 6 V PLL supply voltage AVdd 0 3 to 3 6 V Input voltage Vin 0 3 to 5 5 V 1 Junction temperature Tj 0 to 105 C 2 Storage temperature range Tstg 55 to 150 C Notes 1 Caution Vin must not exceed Vdd by more than 2 5 V at all times including during power on reset 2 The extended temperature parts have die junction temperature of 40 to 105 C See MPC106ARXTGPNS D for more information Table 2 provides the recommended operating conditions for the 106 Proper device operation outside of these recommended and tested conditions is not guaranteed AD MOTOROLA MPC106 PCI Bridge Memory Controller Hardware Specifications 5 For More Information On This Product Go to www freescale com Freescale Semiconductor
4. 15 A14 Ate TT TASZ CAS4 CAS5 oo TH RTC eee BAS Vdd cssocwooe vad PAR LOCK Vss Vdd Vss TSIZ1 TsIzo A17 TTO BCTLO BOTOI BONE TCK Vss Vdd Vss PERR DEVSEL Vad Vss Vdd A21 Tsiz2 ARTRY A18 TAS3 CAS7 MDLE pa pasa NMI CAS MOLE Too Vss Vdd SERR IRDY Vss Vdd A31 A29 A22 A20 M9 PARo PARI TMS FOE AD28 AD24 AD21 AD17 AD14 AD10 CIBEO AD4 ADO A30 BACK A23 PAR2 PAR3 PARS Ana ARs ARS AD30 AD26 AD23 AD19 CED CBE AD12 AD8 AD6 AD2 A27 A25 A24 Para PAR7 m REG __ ISACMASTER ae pa AD1 TDI AD7 AD11 AD15 TRDY AD18 AD22 AD25 AD29 REG was A28 A26 Pane GNT AD3 AD5 AD9 AD13 FRAME STOP AD16 AD20 CIBES AD27 AD31 FLSHREQ MEMACK 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 10 Pin Assignments NC No Connect Vdd Power Supply Positive VIEW Vss Power Supply Ground Vdd Clock Power Supply Positive K9 Signals Figure 11 Pin Assignments Shading Key Y MOTOROLA MPC106 PCI Bridge Memory Controller Hardware Specifications 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pinout Listings 1 6 Pinout Listings Table 10 provides the pinout listing for the MPC106 Some signals have dual functions and are shown more than once Table 10 Pinout Listing Signal Name Pin Number Active 1 0 60x Processor Interface Signals A 0 31 R2 P2 N2 M2 L2 K2 J5 K4 K5
5. Inc Electrical and Thermal Characteristics Table 2 Recommended Operating Conditions Characteristic Symbol Value Unit Notes Supply voltage Vdd 3 3 165 mv V PLL supply voltage AVdd 3 3 165 mv V gt Input voltage Vin 0 to 5 5 V Die junction temperature Tj 0 to 105 C The extended temperature parts have die junction temperature of 40 to 105 C Table 3 provides the package thermal characteristics for the 106 Table 3 Package Thermal Characteristics Characteristic Symbol Value Rating CBGA package thermal resistance junction to top of die 0 133 Note Refer to Section 1 8 System Design Information for more details about thermal management Table 4 provides the DC electrical characteristics for the 106 assuming Vdd AVdd 3 3 5 V DC GND 0V DC and 0 lt T lt 105 C Table 4 DC Electrical Specifications canis arene Te a To GND SYSCLK input low voltage CV 0 4 Input leakage current Vin 3 3 V I Hi Z off state leakage current Vin 3 3 V l 2 Output high voltage low 7 MA Von 2 4 Output low voltage lon 7 mA EMNE PCI 3 3 V signaling output high voltage loH 0 5 mA 2 PCI 3 3 V signaling output low voltage lot 1 5 mA ee ee Capacitance Vin 0V f 1 MHz E MRN Notes 1 Excludes test signals LSSD_MODE and JTAG signals 2 This value represents worst ca
6. K6 J2 J6 J3 J4 H3 High 1 0 H4 H2 G2 F1 E1 E2 F4 E3 D1 C1 C2 B1 C3 B2 E4 D3 E5 AACK D2 Low 1 0 ARTRY F2 Low 1 0 BGO K3 Output BG1 R4 Output DIRTY_OUT BG2 R5 Output TWE BG3 T1 Output DCS BRO L3 Input BR1 T3 Input DIRTY_IN BR2 T6 Input TV BR3 T5 Input BAO Cl N3 Low 1 0 DBGO L5 Low Output DBG1 U4 Low Output TOE DBG2 P3 Low Output DWEO DBG3 H11 Low Output DWET DBGLB J10 Low Output CKE DH 0 31 T14 R13 R14 P13 P14 N13 U3 W1 V2 W2 V3 W3 V4 High VO W4 V5 W5 V6 W6 V7 W7 V8 W8 N8 W9 V9 W10 V10 W11 V11 W12 V12 W13 DL 0 31 U6 T7 U7 T8 U8 R8 P8 N9 P9 R9 U9 T9 U10 T10 High 1 0 U13 T13 R12 N14 M13 T2 U1 U2 V1 U15 V16 U14 W16 V15 W15 V14 W14 V13 GBL M3 Low 1 0 16 MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pinout Listings Table 10 Pinout Listing Continued Signal Name Pin Number Active 1 0 LBCLAIM N4 Low Input MCP J11 Output TA N1 1 0 TBST L4 K TEA Ji Output TS Ri 1 0 TSIZ 0 2 G3 G4 F3 1 0 TT 0 4 G1 H1 K1 L1 M1 High O WT M4 Low 1 0 XATS P1 Low Input SDMA1 L2 Cache Interface Signals ADS DALE BRL2 R3 1 0 BAO T5 Output BR3 BA1 BAA BGL2 P4 Output DBGL2 DOE U5 Output DCS T1 Output BG3 DIRT
7. and Figure 4 These specifications are for operation between 16 67 and 33 33 MHz PCI bus clock SYSCLK frequencies Assume Vdd AVdd 3 3 5 V DC GND 0 V DC and 0 lt T lt 105 C 8 MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Table 7 Input AC Timing Specifications 66 MHz 83 3 MHz Num Characteristic t Unit Notes Min Max Min Max 10a Group input signals valid to 60x Bus Clock input setup 4 0 3 5 ns 1 2 3 10a Group II input signals valid to 60x Bus Clock input setup 3 5 3 5 ns 1 2 4 10a Group III input signals valid to 60x Bus Clock input setup 3 0 2 5 ns 1 2 5 10a Group IV input signals valid to 60x Bus Clock input setup 5 0 4 0 ns 1 2 6 10b Group V input signals valid to SYSCLK input setup 7 0 7 0 ns 7 8 10b Group VI input signals valid to SYSCLK input setup 7 0 7 0 ns 7 9 11a 60x Bus Clock to group I IV inputs invalid input hold 0 0 ns 3 4 5 6 11b SYSCLK to group V VI inputs invalid input hold 0 5 0 5 ns 8 9 HRST pulse width 255 x 255x tsysclk tsysclk 100 us 100 us 10c Mode select inputs valid to HRST input setup 3 X teysck 3X tsysck ns 10 11 12 11c HRST to mode select input invalid input hold 1 0 1 0 ns 10 12 Notes 1 Input s
8. clock which is internally synchronized to SYSCLK All units are nanoseconds 10 MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Table 8 Output AC Timing Specifications 66 MHz 83 3 MHz Num Characteristic Notes Min 12 SYSCLK to output driven output 2 0 1 enable time 13a SYSCLK to output valid for TS and 2 3 4 ARTRY 13b SYSCLK to output valid for all non PCI 2 3 5 signals except TS ARTRY RAS 0 7 CAS 0 7 and DWE 0 2 14a SYSCLK to output valid for RAS O 7 2 3 and CAS 0 7 14b SYSCLK to output valid for PCI signals 3 6 15a SYSCLK to output invalid for all 1 0 7 10 non PCl signals output hold 15b SYSCLK to output invalid for PCI 1 0 7 signals output hold 18 SYSCLK to ARTRY high impedance 1 before precharge output hold 19 SYSCLK to ARTRY precharge enable 0 4 0 4 x 8 1 tsyscik 2 0 tsyscik 2 0 21 SYSCLK to ARTRY high impedance 1 5 1 5 x 8 1 after precharge tsyscik 8 0 tsyscik 8 0 Notes 1 These values are guaranteed by design and are not tested 2 Output specifications are measured from 1 4 V on the rising edge of the appropriate clock to the TTL level 0 8 V or 2 0 V of the signal in question Both input and output timings are measured at the pin see Figur
9. or SYSCLK for input and output specifications Changed Group and Group II signals input setup requirement for 83 MHz in Table 7 from 3 0 ns to 3 5 ns min Changed Group I IV non PCI signals input hold requirement Spec 11a in Table 7 from 1 0 ns to 0 ns Changed Group V and VI PCI signals input hold requirement Spec 11b in Table 7 from 1 0ns to 0 5ns Changed output valid times for all non PCI signals Specs 13a 13b and 14a from 8 ns to 7 ns at 66 Mhz and from 7 ns to 6 ns at 83 MHz Corrected Figure 10 to reflect TOE signal is shared with DBG1 on pin U5 Changed input and Hi Z leakage current Vin in Table 4 from 5 5V to 3 3V Changed the power consumption data in Table 5 Changed note 7 of Table 8 to show the minimum timing specification assumes CL 0 pF Rev 3 Deleted PLL 0 3 0010 from Table 11 to remove 1 1 mode operation between 16MHz and 25MHz Lowered PCI 3 3V signalling output high voltage from 3 0 V to 2 7V and added current conditions Added note 10 to Table 8 regarding PCI hold time for PCI 3 3V VOH and VOL in Table 4 to reflect current production test Included note 12 in Specification 10c of Table 4 Clarified note 9 in Table 8 and included in Specification 12 and 18 Added a similar guaranteed by design and not tested note to Table 9 and included in Specifications 3 7 and 11 All to reflect current production test Corrected Figure 12 dimensions from TBD to actual di
10. A15 Input TRDY E8 O ISA_MASTER B3 Input BERR LOCK G8 Input MEMACK A2 Output PAR G9 1 0 PERR F9 VO PIRQ H10 Output SDRAS REQ B4 Low Output 18 MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pinout Listings Table 10 Pinout Listing Continued Signal Name Pin Number Active 1 0 SERR E9 Low 1 0 STOP A9 Low 1 0 TRDY B9 Low 1 0 Interrupt Clock and Power Management Signals CKO L11 High Output DWE2 HRST L16 Low Input NMI E15 High Input QACK L14 Low Output QREQ H16 Low Input SYSCLK L6 Clock Input SUSPEND H14 Low Input Test Configuration Signals PLL 0 3 U11 711 U12 T12 Input TCK F13 Input TDI B13 Input TDO E12 Output TMS D14 Input TRST H13 Input Power and Ground Signals AVdd K9 High Clock Power LSSD_MODE 2 G11 Low Input Vdd E10 E6 F11 F5 F7 G10 G12 G6 H5 H7 K10 K7 L12 High Power M11 M5 M7 N10 N12 N6 P11 P5 P7 R10 R6 J8 L8 Vss E11 E7 F10 F12 F6 G5 G7 H12 H6 J7 L7 M10 M12 Low Ground M6 N11 N5 N7 P10 P12 P6 R11 R7 K8 J9 L9 NC H8 H9 M8 M9 Note 1 All PCI signals are in little endian bit order 2 This test signal is for factory use only It must be pulled up to Vdd for normal device operation AD MOTOROLA MPC106 PCI Bridge Memory Controller Hardware Specif
11. Freescale Semiconductor Inc Order Number MPC106EC D MOTOROLA Rev 6 10 2001 Semiconductor Products Sector Technical Data MPC106 PCI Bridge Memory Controller Hardware Specifications The Motorola MPC106 PCI bridge memory controller provides a PowerPC microprocessor common hardware reference platform CHRP compliant bridge between the PowerPC microprocessor family and the Peripheral Component Interconnect PCI bus In this document the term 106 is used as an abbreviation for the phrase MPC106 PCI bridge memory controller This document contains pertinent physical characteristics of the 106 For functional characteristics refer to the MPC106 PCI Bridge Memory Controller User s Manual This document contains the following topics Topic Page Section 1 1 Overview 2 Section 1 2 Features 3 Section 1 3 General Parameters 5 Section 1 4 Electrical and Thermal Characteristics 5 Section 1 5 Pin Assignments 15 Section 1 6 Pinout Listings 16 Section 1 7 Package Description 20 Section 1 8 System Design Information 22 Section 1 9 Document Revision History 27 Section 1 10 Ordering Information 27 This document contains information on a new product under development by Motorola Spi IDNA Motorola reserves the right to change or discontinue this product without notice ita Motorola Inc 2001 All rights reserved From Motorola For More Information
12. ME PAGE http www motorola com semiconductors DOCUMENT COMMENTS FAX 512 933 2625 Attn RISC Applications Engineering WORLD WIDE WEB ADDRESSES http www motorola com PowerPC http www motorola com NetComm http www motorola com ColdFire MPC106EC D A MOTOROLA For More Information On This Product Go to www freescale com
13. On This Product Go to www freescale com Freescale Semiconductor Inc Overview In this document the term 60x is used to denote a 32 bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601 PowerPC 603 or PowerPC 604 microprocessors Note that this does not include the PowerPC 602 microprocessor which has a multiplexed address data bus 60x processors implement the PowerPC architecture as it is specified for 32 bit addressing which provides 32 bit effective logical addresses integer data types of 8 16 and 32 bits and floating point data types of 32 and 64 bits single precision and double precision To locate any published errata or updates for this document refer to the website at http www mot com SPS PowerPC 1 1 Overview The MPC106 provides an integrated high bandwidth high performance TTL compatible interface between a 60x processor a secondary L2 cache or additional up to four total 60x processors the PCI bus and main memory This section provides a block diagram showing the major functional units of the 106 and describes briefly how those units interact Figure 1 shows the major functional units within the 106 Note that this is a conceptual block diagram intended to show the basic features rather than how these features are physically implemented on the device L2 Cache Interface Memory 60x Processor Interface Interface Power Mana
14. ROM or 64 bit burst mode ROM Supports writing to Flash ROM Configurable external buffer control logic Programmable interface timing e PCI interface Compliant with PCI Local Bus Specification Revision 2 1 Supports PCI interlocked accesses to memory using LOCK signal and protocol Supports accesses to all PCI address spaces Selectable big or little endian operation Store gathering on PCI writes to memory Selectable memory prefetching of PCI read accesses Only one external load presented by the MPC106 to the PCI bus Interface operates at 20 33 MHz Word parity supported 3 3 V 5 0 V compatible e Support for concurrent transactions on 60x and PCI buses e Power management Fully static 3 3 V CMOS design Supports 60x nap doze and sleep power management modes and suspend mode e JTEEE 1149 1 compliant JTAG boundary scan interface e 304 pin ceramic ball grid array CBGA package MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Parameters 1 3 General Parameters The following list provides a summary of the general parameters of the 106 Technology 0 5 um CMOS four layer metal Die size 5 8 mm x 7 2 mm 41 8 mm Transistor count 250 000 Logic design Fully static Packages Surface mount 304 lead C4 ceramic ball grid array CBGA Power supply 3 3 V 5 V DC Maximum input rating 5 0 V
15. TBST Pull up to 3 3 VDC address transfer WT Cl GBL attributes Cache control ADS Pull up to 3 3 VDC HIT TV Pull up to 3 3 VDC or pull down to GND depending on programmed polarity PCI bus control REQ Typically pull up to 5 VDC FRAME IRDY DEVSEL TRDY STOP Note For closed systems not requiring 5V power SERR PERR these may be pulled up to 3 3 VDC LOCK FLSHREQ ISA_MASTER JTAG TRST Pull down to GND during normal system operation Factory test LSSD_MODE Pull up to 3 3 VDC 1 8 5 Thermal Management Information This section provides thermal management information for the C4 CBGA package Proper thermal control design is primarily dependent on the system level design The use of C4 die on a CBGA interconnect technology offers significant reduction in both the signal delay and the microelectronic packaging volume Figure 14 shows the salient features of the C4 CBGA interconnect technology The C4 interconnection provides both the electrical and the mechanical connections for the die to the ceramic substrate After the C4 solder bump is reflowed epoxy encapsulant is under filled between the die and the substrate Under fill material is commonly used on large high power die however this is not a requirement of the C4 technology The package substrate is a multilayer cofired ceramic The package to board interconnection is by an array of orthogonal 90 10 lead tin solder balls on 1 27 mm pitch During assembly of the C4 CBGA packag
16. Y_IN T3 Input BR1 DIRTY_OUT R4 Output BG1 DWEO P3 Output DBG2 DWE1 H11 Low Output DBG3 DWE2 L11 Low Output CKO HIT T4 Low Input TOE U4 Low Output DBG1 TV T6 High V O BR2 TWE R5 Low Output BG2 Memory Interface Signals BCTL 0 1 F16 F15 Low Output BERR B3 Low Input ISA_MASTER Y MOTOROLA MPC106 PCI Bridge Memory Controller Hardware Specifications 17 For More Information On This Product Go to www freescale com Pinout Listings Freescale Semiconductor Inc Table 10 Pinout Listing Continued Signal Name Pin Number Active 1 0 CAS DQM 0 7 J15 H15 G16 E16 G14 G13 F14 E14 Low Output CKE DBGLB J10 Output FOE D13 Output MAO0 SDBA1 SDMAO ARO N15 Output SDMA1 P1 Output XATS MA1 SDBAO AR9 U16 Output MA 2 12 SDMA 2 12 AR T16 R16 P15 P16 N16 M15 M16 L15 K15 K16 J16 Output 10 20 MDLE SDCAS E13 Output PAR 0 7 AR 1 8 D16 D15 C16 C15 B16 C14 A16 B15 1 0 PPEN J14 Output RAS CS 0 7 M14 L13 K13 K14 K12 L10 J12 K11 Output RCSO R15 O RCS1 J13 Output RTC G15 Input SDRAS H10 Output PIRQ WE T15 Output PCI Interface Signals1 AD 31 0 A4 C13 B5 D12 A5 C12 B6 D11 C11 B7 D10 A7 C10 High O B8 D9 A8 B10 D8 A11 C7 B11 D7 A12 C6 B12 C5 A13 D5 A14 C4 B14 D4 C BE 3 0 A6 C9 C8 D6 Low I O DEVSEL F8 Low 1 0 FLSHREQ A3 Input FRAME A10 1 0 GNT
17. e 5 The maximum timing specification assumes C 50 pF The shared outputs TS and ARTRY require pull up resistors to hold them negated when there is no bus master driving them When the 106 is configured for asynchronous L2 cache SRAMs the DWE 0 2 signals have a maximum SYSCLK to output valid time of 0 5 x tprgc 8 0 ns where tppoc is the 60x bus clock cycle time PCI 3 3 V signaling environment signals are measured from 1 65 V Vdd 2 on the rising edge of SYSCLK to Vou 3 0 V or VoL 0 3V The minimum timing specification assumes CL 0 pF tsyscik is the period of the external bus clock SYSCLK in nanoseconds ns When the unit is given as tsyscik the numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration in nanoseconds of the parameter in question PCI devices which require more than the PCl specified hold time of T Ons or systems where clock skew approaches the PCl specified allowance of 2ns may not work with the MPC106 For workarounds see Motorola application note Designing PCI 2 1 Compliant MPC 106 Systems order number AN1727 D A MOTOROLA MPC106 PCI Bridge Memory Controller Hardware Specifications 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Figure 5 provides the output timing diagram for the 106 60x Bus Clock YM wM 1O 9 FP ALL Non PCI L OUTPUTS
18. e L2 cache using the internal L2 cache controller of the 106 e Upto four 60x processors plus an externally controlled L2 cache such as the Motorola MPC2605 integrated secondary cache The memory interface controls processor and PCI interactions to main memory and is capable of supporting a variety of configurations using DRAM EDO SDRAM ROM or Flash ROM The PCI interface of the 106 complies with the PCI Local Bus Specification Revision 2 1 and follows the guidelines in the PCI System Design Guide Revision 1 0 for host bridge architecture The PCI interface connects the processor and memory buses to the PCI bus to which I O components are connected The PCI bus uses a 32 bit multiplexed address data bus plus various control and error signals The PCI interface of the 106 functions as both a master and target device As a master the 106 supports read and write operations to the PCI memory space the PCI I O space and the PCI configuration space The 106 also supports PCI special cycle and interrupt acknowledge commands As a target the 106 supports read and write operations to system memory The 106 provides hardware support for four levels of power reduction doze nap sleep and suspend The design of the MPC106 is fully static allowing internal logic states to be preserved during all power saving modes 1 2 Features This section summarizes the major features of the 106 as follows e 60x processor interface Supports up
19. e size Table 1 and Table 2 include notes on extended temperature parts Rev 4 Table 8 Note 8 changed to include These values are guaranteed by design and are not tested Rev 5 Added PNS references below Table 1 and Table 6 Changed footnote ordering in Table 8 Table 9 and Table 10 Added new footnote 2 to Table 6 Changed part number key A MOTOROLA MPC106 PCI Bridge Memory Controller Hardware Specifications 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 10 Ordering Information Figure 16 provides the Motorola part numbering nomenclature for the 106 In addition to the core frequency the part numbering scheme also consists of a part modifier and application modifier The part modifier indicates any enhancements in the part from the original production design The application modifier may specify special bus frequencies or application conditions Each part number also contains a revision code This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only MPC 106 A RX xx X x Product Code Part Identifier Part Modifier Package Frequency Application Modifier Revision Level RX BGA 66o0r83 C No 5 2 mode E 3 0 D 5 2 mode G 4 0 T Extended temperature Notes 1 See Part Number Specifications MPC106ARXTGPNS D 2 For current revision level contac
20. e to the board the high melt balls do not collapse 24 MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Design Information Chip with C4 Encapsulant Ceramic Substrate OOOOQOQOOOO CBGA Joint al alear al alraaraT Printed Circuit Board Figure 14 Exploded Cross Sectional View 1 8 5 1 Internal Package Conduction Resistance For this C4 CBGA packaging technology the intrinsic conduction thermal resistance paths are as follows e The die junction to case thermal resistance e The die junction to lead thermal resistance These parameters are shown in Table 13 In this C4 CBGA package the silicon chip is exposed therefore the package case is the top of the silicon Table 13 Thermal Resistance Thermal Metric Effective Thermal Resistance Junction to case thermal resistance 0 133 C W Junction to lead ball thermal resistance 3 8 C W Figure 15 provides a simplified thermal network in which a C4 CBGA package is mounted to a printed circuit board External Resistance Radiation Convection Heat Sink lt Thermal Interface Material Die Package Internal Resistance gt _ Die Junction Package Leads Printed Circuit Board Radiation Convection External Resistance Note the internal versus
21. ency as shown in Section 1 4 2 1 Clock AC Specifications and tested for conformance to the AC specifications for that frequency These specifications are for operation between 16 67 and 33 33 MHz PCI bus SYSCLK frequencies The 60x processor bus frequency is determined by the PCI bus SYSCLK frequency and the settings of the PLL 0 3 signals All timings are specified relative to the rising edge of SYSCLK 1 4 2 1 Clock AC Specifications Table 6 provides the clock AC timing specifications as shown in Figure 2 and assumes Vdd AVdd 3 3 5 V DC GND 0 V DC and 0 lt T lt 105 C AN MOTOROLA MPC106 PCI Bridge Memory Controller Hardware Specifications 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Table 6 Clock AC Timing Specifications SYSCLK Core SYSCLK Core Num Characteristic 93 60 MHz 33 83 3 MHZ Unit Notes Min Max Min Max 60x processor bus core frequency 16 67 66 16 67 83 3 MHz 1 VCO frequency 120 200 120 200 MHz 1 2 SYSCLK frequency 16 67 33 33 16 67 33 33 MHz 1 1 SYSCLK cycle time 30 0 60 0 30 0 60 0 ns 2 3 SYSCLK rise and fall time 2 0 2 0 ns 3 4 SYSCLK duty cycle measured at 1 4 V 40 60 40 60 4 SYSCLK jitter 200 200 ps 5 106 internal PLL relock time 100 100 us 4 6 Notes Caution The SYSCLK frequency and PLL 0 3 set
22. external package resistance Figure 15 C4 CBGA Package Mounted to a Printed Circuit Board AN MOTOROLA MPC106 PCI Bridge Memory Controller Hardware Specifications 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Design Information 1 8 5 2 Board and System Level Modeling A common figure of merit used for comparing the thermal performance of various microelectronic packaging technologies is the junction to ambient thermal resistance The final chip junction operating temperature is not only a function of the component level thermal resistance but the system level design and its operating conditions In addition to the component s power consumption a number of factors affect the final operating die junction temperature For example these factors might include airflow board population heat sink efficiency heat sink attach next level interconnect technology and system air temperature rise Due to the complexity and the many variations of system level boundary conditions for today s microelectronic equipment the combined effects of the heat transfer mechanisms radiation convection and conduction may vary widely For this reason we recommend using conjugate heat transfer models for the board as well as system level designs To expedite system level thermal analysis several compact CBGA thermal models are available on request within FLOTHERM The die junction to ambien
23. gement Error Interrupt Control Configuration PCI Interface Registers el PCI Bus Figure 1 Block Diagram 2 MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Features The 106 provides a PowerPC microprocessor CHRP compliant bridge between the PowerPC microprocessor family and the PCI bus CHRP documentation provides a set of specifications that define a unified personal computer architecture PCI support allows the rapid design of systems using peripherals already designed for PCI and the other standard interfaces available in the personal computer hardware environment The 106 integrates secondary cache control and a high performance memory controller uses an advanced 3 3 V CMOS process technology and is fully compatible with TTL devices The 106 supports a programmable interface to a variety of PowerPC microprocessors operating at select bus speeds The 60x address bus is 32 bits wide and the data bus is 64 bits wide The 60x processor interface of the 106 uses a subset of the 60x bus protocol supporting single beat and burst data transfers The address and data buses are decoupled to support pipelined transactions The 106 provides support for the following configurations of 60x processors and L2 cache e Up to four 60x processors with no L2 cache e A single 60x processor plus a direct mapped lookasid
24. he bus the address and transfer attributes on the bus A 0 31 TT 0 4 TBST WT CI and GBL are not driven by any master and may float in the high impedance state for relatively long periods of time Since the MPC106 must continually monitor these signals this float A MOTOROLA MPC106 PCI Bridge Memory Controller Hardware Specifications 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Design Information condition may cause excessive power draw by the input receivers on the MPC106 or by other receivers in the system It is recommended that these signals be pulled up or restored in some manner by the system The 60x data bus input receivers on the MPC106 do not require pull up resistors on the data bus signals DH 0 31 DL O 31 and PAR 0 7 However other data bus receivers in the system may require pull up resistors on these signals In general the 60x address and control signals are pulled up to 3 3 VDC and the PCI control signals are pulled up to 5 VDC through weak 2 10 KQ resistors Resistor values may need to be adjusted stronger to reduce induced noise on specific board designs Table 12 summarizes the pull up pull down recommendations for the MPC106 Table 12 Pull Up Pull Down Recommendations Signal Type Signals Pull Up Pull Down 60x bus control BRn Pull up to 3 3 VDC TS XATS AACK ARTRY TA 60x bus A 0 31 TT 0 4
25. ications 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Package Description 1 7 Package Description The following sections provide the package parameters and the mechanical dimensions for the 106 1 7 1 Package Parameters The package parameters are as provided in the following list The package type is a 21 mm x 25 mm 304 lead C4 ceramic ball grid array CBGA Package outline 21 mm x 25 mm Interconnects 303 16 x 19 ball array minus one Pitch 1 27 mm Solder attach 63 37 Sn Pb Solder balls 10 90 Sn Pb 0 89 mm diameter Maximum module height 3 16 mm Co planarity specification 0 15 mm 20 MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Package Description imensions 1 7 2 Mechanical D 2X Neen Figure 12 shows the mechanical dimensions for the MPC106 2X Soa 12345 6 7 8 9 101112131415 16 2 9 8 5 2 8 28 s x vet ees e see mMm m olo N ziloler allog EINI aN RJ o eI NIS eN Nilo o lo N lt l lolnANIOJIITI XIZ a S gt Dromazsuxr5 rouwacmac Note All measurements are in mm Bottom View Not to scale Figure 12 Mechanical Dimensions 21 MPC106 PCI Bridge Memory Controller Hardware Specifications A MOTOROLA For More Information On This Pr
26. ignal 10 The setup and hold time is with respect to the rising edge of HRST see Figure 4 Mode select inputs include the RCSO FOE and DBGO configuration inputs 1 tsyscik is the period of the external clock SYSCLK in nanoseconds ns When the unit is given as tsyscik the numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration in nanoseconds of the parameter in question 12 These values are guaranteed by design and are not tested Figure 3 provides the input timing diagram for the 106 A MOTOROLA MPC106 PCI Bridge Memory Controller Hardware Specifications 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics 60x Bus Clock o fw NOAS N lt Group II III e7 A and IV INPUTS SYSCLK A NMN JSN lt Group V and e7 Ni VI INPUTS VM Midpoint Voltage 1 4 V Figure 3 Input Timing Diagram Figure 4 provides the mode select input timing diagram for the 106 HRST VM MODE PINS VM Midpoint Voltage 1 4 V Figure 4 Mode Select Input Timing Diagram 1 4 2 3 Output AC Specifications Table 8 provides the output AC timing specifications for 106 shown in Table 5 Assume Vdd AVdd 3 3 5 V DC GND 0 V DC CL 50 pF and 0 lt T lt 105 C Processor and memory interface signals are specified from the rising edge of the 60x bus
27. lead inductance In addition it is recommended that there be several bulk storage capacitors distributed around the PCB feeding the Vdd plane to enable quick recharging of the smaller chip capacitors These bulk capacitors should have a low equivalent series resistance ESR rating to ensure the quick response time necessary They should also be connected to the power and ground planes through two vias to minimize inductance Suggested bulk capacitors 100 uF AVX TPS tantalum or 330 uF AVX TPS tantalum 1 8 4 Connection Recommendations To ensure reliable operation it is recommended to connect unused inputs to an appropriate signal level Unused active low inputs should be tied using pull up resistors to Vdd Unused active high inputs should be tied using pull down resistors to GND All no connect NC signals must remain unconnected Power and ground connections must be made to all external Vdd AVdd and GND pins of the 106 1 8 4 1 Pull up Resistor Recommendations The MPC106 requires pull up or pull down resistors on several control signals of the 60x and PCI buses to maintain the control signals in the negated state after they have been actively negated and released by the 106 or other bus masters The JTAG test reset signal TRST should be pulled down during normal system operation Also as indicated in Table 10 the factory test signal LSSD_MODE must be pulled up for normal device operation During inactive periods on t
28. mpedance 0 15 ns Notes 1 These values are guaranteed by design and are not tested 2 TRST is an asynchronous signal The setup time is for test purposes only 3 Non test signal input timing with respect to TCK 4 Non test signal output timing with respect to TCK Figure 6 provides the JTAG clock input timing diagram TCK VM Midpoint Voltage 1 4 V Figure 6 JTAG Clock Input Timing Diagram Figure 7 provides the TRST timing diagram TCK TRST Figure 7 TRST Timing Diagram AD MOTOROLA MPC106 PCI Bridge Memory Controller Hardware Specifications 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Figure 8 provides the boundary scan timing diagram TCK X N INJ Data Outputs x Output Data Valid Ny Ay Data Outputs gt Ny Data Outputs Ny Output Data Valid Figure 8 Boundary Scan Timing Diagram Figure 9 provides the test access port timing diagram TCK X Ny p aa TDO N x Output Data Valid N TDO N gt N TDO Ny Output Data Valid Figure 9 Test Access Port Timing Diagram 14 MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Pin Assignments 1 5 Pin Assignments Figure 10 contains the pin assignments fo
29. n Information 1 8 2 PLL Power Supply Filtering The AVdd power signal is provided on the 106 to provide power to the clock generation phase locked loop To ensure stability of the internal clock the power supplied to the AVdd input signal should be filtered using a circuit similar to the one shown in Figure 13 The circuit should be placed as close as possible to the AVdd pin to ensure it filters out as much noise as possible 109 Vdd o WWW AV sey 1OnF E gt 0 1 BF GND Figure 13 PLL Power Supply Filter Circuit 1 8 3 Decoupling Recommendations Due to the 106 s large address and data buses and high operating frequencies it can generate transient power surges and high frequency noise in its power supply especially while driving large capacitive loads This noise must be prevented from reaching other components in the system and the 106 itself requires a clean tightly regulated source of power It is strongly recommended that the system design include six to eight 0 1 uF ceramic and 10 uF tantalum decoupling capacitors to provide both high and low frequency filtering These capacitors should be placed closely around the perimeter of the 106 package or on the underside of the PCB It is also recommended that these decoupling capacitors receive their power from separate Vdd and GND power planes in the PCB utilizing short traces to minimize inductance Only surface mount technology SMT capacitors should be used to minimize
30. oduct Go to www freescale com Freescale Semiconductor Inc System Design Information 1 8 System Design Information This section provides electrical and thermal design recommendations for successful application of the 106 1 8 1 PLL Configuration The 106 requires a single system clock input SYSCLK The SYSCLK frequency dictates the frequency of operation for the PCI bus An internal PLL on the MPC106 generates a master clock that is used for all of the internal core logic The master clock provides the core frequency reference and is phase locked to the SYSCLK input The 60x processor L2 cache and memory interfaces operate at the core frequency In the 5 2 clock mode Rev 4 0 only the MPC106 needs to sample the 60x bus clock on the LBCLAIM configuration input to resolve clock phasing with the PCI bus clock SYSCLK The PLL is configured by the PLL 0 3 signals For a given SYSCLK PCI bus frequency the clock mode configuration signals PLL 0 3 set the core frequency and the frequency of the VCO controlling the PLL lock The supported core and VCO frequencies and the corresponding PLL 0 3 settings are provided in Table 11 Table 11 PLL Configuration N 1 22 Core Frequency VCO Frequency in MHz PLL 0 3 Core SYSCL VCO K Ratio Multiplier PCI Bus PCI Bus PCI Bus PCI Bus 16 6 MHz 20 MHz 25 MHz 33 3 MHz 0001 1 1 x4 33 3 133 0100 2 1 x2
31. pecifications are measured from the TTL level 0 8 or 2 0 V of the signal in question to the 1 4 V of the rising edge of SYSCLK Both input and output timings are measured at the pin see Figure 3 2 Processor and memory interface signals are specified from the rising edge of the 60x bus clock which is internally synchronized to SYSCLK 3 Group input signals include the following processor L2 and memory interface signals A 0 31 PAR O 7 AR 1 8 BR O0 4 BRL2 XATS LBCLAIM ADS BAO TV and HIT when configured for external L2 4 Group II input signals include the following processor and memory interface signals TBST TT 0 4 TSIZ 0 2 WT Cl GBL AACK and TA 5 Group III input signals include the following processor and memory interface signals DL 0 31 and DH 0 31 G Group IV input signals include the following processor and L2 interface signals TS ARTRY DIRTY_IN and HIT when configured for internal L2 controller 7 PCI 3 3 V signaling environment signals are measured from 1 65 V Vdd 2 on the rising edge of SYSCLK to Vou 3 0 V or VoL 0 3 V PCI 5 V signaling environment signals are measured from 1 65 V Vdd 2 on the rising edge of SYSCLK to Voy 2 4 V or Vo 0 55 V 8 Group V input signals include the following bussed PCI interface signals FRAME C BE 0 3 AD 0 31 DEVSEL IRDY TRDY STOP PAR PERR SERR LOCK FLSHREQ and ISA_MASTER 9 Group VI input signal is the point to point PCI GNT input s
32. r the MPC106 and Figure 11 provides a key to the shading 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DL26 DL28 DL30 DH31 DH29 DH27 DH25 DH23 DH21 DH19 DH17 DH15 DH13 DH11 DH9 DH7 DL24 DL27 DL29 DL31 DH30 DH28 DH26 DH24 DH20 DH18 DH16 DH14 DH12 DH10 DH8 DL22 MAN DOE TOE SDBA0 DL23 DL25 DL14 PLL2 PLLO DL12 DL10 DL4 DL2 DLO RE we DH6 DL21 DL20 AR9 soma WE DHO DL15 PLL3 PLL DL13 DL11 DL3 DL1 RAJA Bas aT DIRTYTIN Di9 bes Mis BRZ BR3 BRT BG3 MA3 ADS SDMA3 RCSO DH2 DHI DL16 Vss Vdd DLO DLS Vss Vdd WE IRTEOUT DALE AO TS AR11 BRL2 MAS MA4 BA1 are SDMAS SDMA4 DH4 DH3 Vss Vdd Vss DL8 DL6 Vdd Vss Vdd BAA WED Ai PATSEDMA AR13 AR12 BGLZ MAO MAG SDBA1 a e spmae SDBAY pLiz DH5 Vdd Vss Vdd DL DH22 Vss Vdd Vss BCLAIM a A2 TA AR14 ARO MA8 MA7 RASU ma spmas spmaz PAS DL18 Vss Vdd Vss NC NC Vdd Vss Vdd wr GBL A3 TT4 AR16 AR15 ERST spac GACK RASI Vdd GKO RASS v Vdd v SYSCLK DBGO TBST BRO A4 TT3 ARTY ST DWE2 css ES s MA11 MA10 BASA BAO RAS3 RAS2 RASA RAS7 _ spmait SDMA10 RASS iS aS py Vdd AVdd Vss Vdd AQ A8 A7 BGO A5 TT2 AR19 AR18 MA12 TASO EEE acer RASG uco DBGLB spmaiz BAS PPEN RCS mee MCP BaN Vss Vdd Vss Ait A6 M3 A12 Ato TEA AR20 GASTI leqepexn Teet DWET PRO area GASI 5USPEND TRST Vss DNET FRO NC NC Vdd Vss Vdd
33. se 40 ohm drivers default value for Processor L2 control signals CI WT GBL TBST TSIZ 0 2 TT 0 4 TWE and TV only Other signals have lower default driver impedance and will support larger lop and lo All drivers may optionally be programmed to different driver strengths 3 Capacitance is periodically sampled rather than 100 tested Table 5 lists the power consumption of the 106 6 MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Electrical and Thermal Characteristics Table 5 Power Consumption Mode SYSCLK Core SYSCLK Core Unit 33 66 MHz 33 83 3 MHz Full On Typical 1 2 2 2 WwW Maxim m 1 4 2 4 W Doze Typical 1 0 1 1 W Maxinurn 1 2 1 4 W Nap Typical 1 0 1 1 W Maximum 1 2 1 4 W Sleep Typical 260 330 mW Masxim rh 360 450 mW Suspend Typical 140 220 mW Maximum 190 270 mW Notes e Power consumption for common system configurations assuming 50 pF loads e Suspend power saving mode assumes SYSCLK off and PLL in bypass mode Typical power is an average value measured at Vdd AVdd 3 30 V and T4 25 C e Maximum power is measured at Vdd AVdd 3 45 V and T4 25 C 1 4 2 AC Electrical Characteristics This section provides AC electrical characteristics for the 106 After fabrication parts are sorted by maximum 60x processor bus frequ
34. t designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and A are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer HOW TO REACH US USA EUROPE LOCATIONS NOT LISTED Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 TECHNICAL INFORMATION CENTER 1 800 521 6274 HO
35. t local Motorola sales office Figure 16 Part Number Key DigitalDNA is a trademark of Motorola Inc The PowerPC name the PowerPC logotype and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are no
36. t thermal resistance is shown in Table 14 The model results are in accordance with SEMI specification G38 This standard specifies a single component be placed on a 7 5 cm x 10 cm single layer printed circuit card Note that this single metric may not adequately describe three dimensional heat flow Table 14 Die Junction to Ambient Thermal Resistance Airflow Velocity Airflow Velocity Die Junction to Ambient Thermal Resistance Meter Second Feet Minute SEMI G38 C W 1 196 8 22 0 2 393 7 18 5 3 590 0 17 0 26 MPC106 PCI Bridge Memory Controller Hardware Specifications AX MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Document Revision History 1 9 Document Revision History Table 15 lists significant changes between revisions of this document Table 15 Document Revision History Document Revision Substantive Change s Rev 0 Initial release Rev 1 Rev 2 Changed VCO maximum frequency in Table 6 to 200 MHz Changed input and Hi Z leakage current in Table 4 from 10A to 15A Changed low and lo in Table 4 from 18mA and 14mA respectively to 7mA and 7mA to correct the sign and reduce the current to worst case value for the lowest strength default driver Changed footnote 4 to Table 6 to be consistent with SYSCLK jitter spec of 200ps Modified Table 7 Figure 3 Table 8 and Figure 5 to clarify reference clock 60x Bus Clock
37. tings must be chosen such that the resulting SYSCLK bus frequency CPU core frequency and PLL VCO frequency do not exceed their respective maximum or minimum operating frequencies Refer to the PLL O 3 signal description in Section 1 8 System Design Information for valid PLL O 3 settings and to Section 1 9 Document Revision History for available frequencies and part numbers VCO operating range for extended temperature devices is different Refer to MPC106ARXTGPNS D for more information Rise and fall times for the SYSCLK input are measured from 0 4 V to 2 4 V Timing is guaranteed by design and characterization and is not tested The total input jitter short term and long term combined must be under 200 ps PLL relock time is the maximum time required for PLL lock after a stable Vdd AVdd and SYSCLK are reached during the power on reset sequence This specification also applies when the PLL has been disabled and subsequently re enabled during the sleep and suspend power saving modes Also note that HRST must be held asserted for a minimum of 255 bus clocks after the PLL relock time 100 us during the power on reset sequence ao a A O Figure 2 provides the SYSCLK input timing diagram SYSCLK VM Midpoint Voltage 1 4 V Figure 2 SYSCLK Input Timing Diagram 1 4 2 2 Input AC Specifications Table 7 provides the input AC timing specifications for the 106 as defined in Figure 3
38. to four 60x processors Supports various operating frequencies and bus divider ratios 32 bit address bus 64 bit data bus Supports full memory coherency Supports optional 60x local bus slave Decoupled address and data buses for pipelining of 60x accesses Store gathering on 60x to PCI writes A MOTOROLA MPC106 PCI Bridge Memory Controller Hardware Specifications 3 For More Information On This Product Go to www freescale com Features Freescale Semiconductor Inc e Secondary L2 cache control Configurable for write through or write back operation Supports cache sizes of 256 Kbytes 512 Kbytes and 1 Mbyte Up to 4 Gbytes of cacheable space Direct mapped Supports byte parity Supports partial update with external byte decode for write enables Programmable interface timing Supports pipelined burst synchronous burst or asynchronous SRAMs Alternately supports an external L2 cache controller or integrated L2 cache module e Memory interface 1 Gbyte of RAM space 16 Mbytes of ROM space Supports parity or error checking and correction ECC High bandwidth 64 bit data bus 72 bits including parity or ECC Supports fast page mode DRAMs extended data out EDO DRAMs and synchronous DRAMs SDRAMs Supports 1 to 8 banks of DRAM EDO SDRAM with sizes ranging from 2 Mbyte to 128 Mbytes per bank ROM space may be split between the PCI bus and the 60x memory bus 8 Mbytes each Supports 8 bit asynchronous

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