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VXI-MIO Series User Manual Multifunction I/O Modules for VXIbus

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1. 4 20 Analog Output Signal Connections 4 20 Digital I O Signal Connections 4 22 Table of Contents National Instruments Corporation vii VXI MIO Series User Manual Power Connections 4 23 Timing Connections 4 23 Programmable Function Input Connections 4 24 Data Acquisition Timing Connections 4 25 SCANCLK Signal 4 26 EXTSTROBE Signal 4 26 TRIG1 Signal 4 27 TRIG2 Signal 4 28 STARTSCAN Signal 4 30 CONVERT Signal 4 32 AIGATE Signal
2. 4 45 Chapter 5 Calibration Loading Calibration Constants 5 1 Self Calibration 5 2 External Calibration 5 2 Other Considerations 5 3 Table of Contents VXI MIO Series User Manual viii National Instruments Corporation Appendix A Specifications VXI MIO 64E 1 A 1 VXI MIO 64XE 10 A 10 Appendix B Optional Cable Connector Descriptions Appendix C Common Questions Appendix D Customer Communication Glossary Index Figures Figure 1 1 The Relationship between the Programming Environment Your Instrument Driver and Your VXI DAQ Hardware 1 5 Figure 2 1 VXI MIO 64E 1 Parts Locator Diagram 2 3 Figure 2 2 VXI MIO 64XE 10 Parts Locator Diagram 2 4 Figure 2 3 VX
3. 5 000 V 0 5 mV actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm 1 000 h Appendix A Speci cations for VXI MIO 64XE 10 National Instruments Corporation A 13 VXI MIO Series User Manual Analog Output Output Characteristics Number of channels 2 voltage Resolution 16 bits 1 in 65 536 Max update rate 100 kS s Type of DAC Double buffered FIFO buffer size 2 048 samples Data transfers DMA interrupts programmed I O Transfer Characteristics Relative accuracy INL 0 5 LSB typ 1 LSB max DNL 1 LSB max Monotonicity 16 bits guaranteed Offset error After calibration 305 V max Before calibration 20 mV max Gain error relative to internal reference After calibration 30 5 ppm max Before calibration 2 000 ppm max Voltage Output Range 10 V 0 to 10 V software selectable Output coupling DC Output impedance
4. 4 26 Figure 4 13 SCANCLK Signal Timing 4 26 Figure 4 14 EXTSTROBE Signal Timing 4 27 Figure 4 15 TRIG1 Input Signal Timing 4 28 Figure 4 16 TRIG1 Output Signal Timing 4 28 Figure 4 17 TRIG2 Input Signal Timing 4 29 Figure 4 18 TRIG2 Output Signal Timing 4 29 Figure 4 19 STARTSCAN Input Signal Timing 4 30 Figure 4 20 STARTSCAN Output Signal Timing 4 31 Figure 4 21 CONVERT Input Signal Timing 4 32 Figure 4 22 CONVERT Output Signal Timing 4 33 Figure 4 23 SISOURCE Signal Timing 4 34 Figure 4 24 WFTRIG Input Signal Timing 4 35 Figure 4 25 WFTRIG Output Signal Timing 4 35 Figure 4 26 UPDATE Input Signal
5. 0 1 max Current drive 5 mA Protection Short circuit to ground Power on state 0 V 20 mV Dynamic Characteristics Settling time for full scale step 10 s to 1 LSB accuracy Slew rate 5 V s Noise 60 Vrms DC to 1 MHz Appendix A Speci cations for VXI MIO 64XE 10 VXI MIO Series User Manual A 14 National Instruments Corporation Stability Offset temperature coefficient 50 V C Gain temperature coefficient 7 5 ppm C Onboard calibration reference Level 5 000 V 0 5 mV actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm Digital I O Number of channels 8 input output Compatibility TTL CMOS Power on state Input High Z Data transfers Programmed I O Digital logic levels Level Min Max Input low voltage 0 V 0 8 V Input high voltage 2 V 5 V Input low current 320 A Input high current 10 A Output low voltage IOL 24 mA 0 4 V Output hig
6. 3 7 Multichannel Scanning Considerations 3 8 Analog Output 3 10 Analog Output Reference Selection 3 10 Analog Output Polarity Selection 3 10 Analog Output Reglitch Selection 3 11 Analog Trigger 3 11 Digital I O 3 14 Timing Signal Routing 3 15 Programmable Function Inputs 3 16 Module and Timebase 3 16 VXIbus Triggers 3 17 Chapter 4 Signal Connections I O Connector 4 1 I O Connector Signal Descriptio
7. 20 V s Noise 200 Vrms DC to 1 MHz Glitch energy at midscale transition Magnitude Reglitching disabled 70 mV Reglitching enabled 40 mV Duration 1 5 s Stability Offset temperature coefficient 50 V C Gain temperature coefficient Internal reference 25 ppm C External reference 25 ppm C Appendix A Speci cations for VXI MIO 64E 1 National Instruments Corporation A 7 VXI MIO Series User Manual Onboard calibration reference Level 5 000 V 0 5 mV actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm Digital I O Number of channels 8 input output Compatibility TTL CMOS Power on state Input High Z Data transfers Programmed I O Timing I O Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers 24 bits Frequency
8. 4 33 SISOURCE Signal 4 34 Waveform Generation Timing Connections 4 34 WFTRIG Signal 4 36 UPDATE Signal 4 36 UISOURCE Signal 4 37 General Purpose Timing Signal Connections 4 38 GPCTR0_SOURCE Signal 4 38 GPCTR0_GATE Signal 4 39 GPCTR0_OUT Signal 4 40 GPCTR0_UP_DOWN Signal 4 40 GPCTR1_SOURCE Signal 4 41 GPCTR1_GATE Signal 4 41 GPCTR1_OUT Signal 4 42 GPCTR1_UP_DOWN Signal 4 43 FREQ_OUT Signal 4 44 Field Wiring Considerations
9. 5 to 90 noncondensing National Instruments Corporation B 1 VXI MIO Series User Manual Optional Cable Connector Descriptions Appendix B This appendix describes the connectors on the optional cables for the VXI MIO Series modules Figure B 1 shows the pin assignments for the 68 pin MIO connector This connector is one of the two 68 pin connectors available when you use the SH966868 cable assembly with the VXI MIO 64E 1 or VXI MIO 64XE 10 Appendix B Optional Cable Connector Descriptions VXI MIO Series User Manual B 2 National Instruments Corporation Figure B 1 68 Pin MIO Connector Pin Assignments FREQ_OUT GPCTR0_OUT PFI9 GPCTR0_GATE DGND PFI6 WFTRIG PFI5 UPDATE DGND 5 V DGND PFI1 TRIG2 PFI0 TRIG1 DGND DGND 5 V DGND DIO6 DIO1 DGND DIO4 EXTREF DAC1OUT DAC0OUT ACH15 AIGND ACH6 ACH13 AIGND ACH4 AIGND ACH3 ACH10 AIGND ACH1 ACH8 DGND PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_SOURCE PFI2 CONVERT DGND DGND DGND EXTSTROBE SCANCLK DIO3 DIO7 DIO2 DGND DIO5 DIO0 DGND AOGND AOGND AIGND ACH7 ACH14 AIGND ACH5 ACH12 AISENSE ACH11 AIGND ACH2 ACH9 AIGND ACH0 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61
10. 4 LSB All 3 s typ 5 s max 2 s typ 3 s max 1 8 s typ 2 s max System noise LSBrms not including quantization Gain Noise dither off Noise dither on 0 5 to 20 0 15 0 5 50 0 3 0 6 100 0 5 0 7 1 000 h Appendix A Speci cations for VXI MIO 64E 1 National Instruments Corporation A 5 VXI MIO Series User Manual Analog Output Output Characteristics Number of channels 2 voltage Resolution 12 bits 1 in 4 096 Max update rate FIFO mode waveform generation Internally timed 1 MS s per channel All other cases 950 kS s per channel Type of DAC Double buffered multiplying FIFO buffer size 2 048 samples Data transfers DMA interrupts programmed I O Transfer Characteristics Relative accuracy INL After calibration 0 3 LSB typ 0 5 LSB max Before calibration 4 LSB max DNL After calibration 0 3 LSB typ 1 0 LSB max Before calibration 3 LSB max Monotonicity 12 bits guaranteed after calibration Off
11. 1 k min Input bias current 200 pA Input offset current 100 pA CMRR DC to 60 Hz Gain 0 5 95 dB Gain 1 100 dB Gain 2 106 dB Appendix A Speci cations for VXI MIO 64E 1 VXI MIO Series User Manual A 4 National Instruments Corporation Dynamic Characteristics Crosstalk 70 dB DC to 100 kHz Stability Recommended warm up time 15 min Offset temperature coefficient Pregain 5 V C Postgain 240 V C Gain temperature coefficient 20 ppm C Onboard calibration reference Level 5 000 V 0 5 mV actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm Bandwidth Small signal 3 dB Large signal 1 THD 1 6 MHz 1 MHz Settling time for full scale step Gain Accuracy 0 012 0 5 LSB 0 024 1 LSB 0 098
12. 256 KB x 32 bit or 256 KB x 36 bit 1 MB ON 256 KB x 32 bit or 256 KB x 36 bit 256 KB x 32 bit or 256 KB x 36 bit 2 MB ON 512 KB x 32 bit or 512 KB x 36 bit 2 MB ON 512 KB x 32 bit or 512 KB x 36 bit 512 KB x 32 bit or 512 KB x 36 bit 4 MB ON SIMM Size Factory Default SIMM Size Factory Default S3 S3 a 4 MB X 32 bit or larger b Smaller than 4 MB X 32 bit Chapter 2 Con guration and Installation National Instruments Corporation 2 7 VXI MIO Series User Manual Load USER FACTORY Configuration The VXI MIO module has an onboard EEPROM which stores default register values that are loaded at power on The EEPROM is divided into two halves a factory configuration half and a user configuration half Both halves were factory configured with the same configuration values so you can modify the user configurable half while the factory configured half stores a back up of the factory settings Use switch S2 to control the operation of the EEPROM The switch causes the VXI MIO module to boot off the factory configured half instead of the user modified settings This is useful in the event that the user configured half of the EEPROM becomes corrupted in such a way that the VXI MIO module boots to an unusable state Refer to Figure 2 5 for configuration settings 1 MB x 32 bit or 1 MB x 36 bit 4 MB Yes ON 1 MB x 32 bit or 1 MB x 36 bit 1 MB x 32
13. 3 3 Table 3 2 Actual Range and Measurement Precision 3 4 Table 3 3 Actual Range and Measurement Precision VXI MIO 64XE 10 3 6 Table 4 1 VXI MIO 64E 1 I O Signal Summary 4 6 Table 4 2 VXI MIO 64XE 10 I O Signal Summary 4 8 About This Manual National Instruments Corporation xi VXI MIO Series User Manual This manual describes the electrical and mechanical aspects of each module in the VXI MIO Series product line and contains information concerning their installation operation and programming Unless otherwise noted text applies to all modules in the VXI MIO Series The VXI MIO Series includes the following modules VXI MIO 64E 1 VXI MIO 64XE 10 The VXI MIO Series modules are high performance multifunction analog digital and timing I O modules for VXIbus Organization of This Manual The VXI MIO Series User Manual is organized as follows Chapter 1 Introduction describes the VXI MIO Series modules lists what you need to get started describes the optional software and optional equipment and explains how to unpack your VXI MIO Series module Chapter 2 Configuration and Installation explains how to configure and install your VXI MIO Series module Chapter 3 Hardware Overview prese
14. indicates that the text following it applies only to specific VXI MIO Series modules lt gt Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a bit port or signal name for example ACH lt 0 7 gt stands for ACH0 through ACH7 bold Bold text denotes parameters bold italic Bold italic text denotes a note caution or warning italic Italic text denotes emphasis on a specific module in the VXI MIO Series or on other important information a cross reference or an introduction to a key concept NI DAQ NI DAQ refers to the NI DAQ software for PC compatibles unless otherwise noted SCXI SCXI stands for Signal Conditioning eXtensions for Instrumentation and is a National Instruments product line designed to perform front end signal conditioning for National Instruments plug in DAQ boards The Glossary lists abbreviations acronyms metric prefixes mnemonics symbols and terms About This Manual National Instruments Corporation xiii VXI MIO Series User Manual National Instruments Documentation The VXI MIO Series User Manual is one piece of the documentation set for your VXI DAQ system You could have any of several types of manuals depending on the hardware and software in your system Use the manuals you have as follows Getting Started with SCXI If you are using SCXI this is the first manual you shou
15. 3 17 Table of Contents National Instruments Corporation ix VXI MIO Series User Manual Figure 4 1 I O Connector Pin Assignment for the VXI MIO 64E 1 and VXI MIO 64XE 10 4 2 Figure 4 2 VXI MIO Series PGIA 4 10 Figure 4 3 Summary of Analog Input Connections 4 13 Figure 4 4 Differential Input Connections for Ground Referenced Signals 4 15 Figure 4 5 Differential Input Connections for Nonreferenced Signals 4 16 Figure 4 6 Single Ended Input Connections for Nonreferenced or Floating Signals 4 19 Figure 4 7 Single Ended Input Connections for Ground Referenced Signal 4 20 Figure 4 8 Analog Output Connections 4 21 Figure 4 9 Digital I O Connections 4 22 Figure 4 10 Timing I O Connections 4 24 Figure 4 11 Typical Posttriggered Acquisition 4 25 Figure 4 12 Typical Pretriggered Acquisition
16. Bias Chapter 4 Signal Connections VXI MIO Series User Manual 4 8 National Instruments Corporation Table 4 2 shows the I O signal summary for the VXI MIO 64XE 10 Table 4 2 VXI MIO 64XE 10 I O Signal Summary Signal Name Drive Impedance Input Output Protection Volts Power On Off Source mA at V Sink mA at V Rise Time ns Bias ACH lt 0 63 gt AI 100 G in parallel with 100 pF 25 15 1 nA AISENSE AI 100 G in parallel with 100 pF 25 15 1 nA AIGND AI DAC0OUT AO 0 1 Short circuit to ground 5 at 10 V 5 at 10 V 5 V s DAC1OUT AO 0 1 Short circuit to ground 5 at 10 V 5 at 10 V 5 V s AOGND AO DGND DO 5 V DO 0 1 Short circuit to ground 1A DIO lt 0 7 gt DIO 5 5 V 13 at 4 6 V 24 at 0 4 1 1 50 k pu SCANCLK DO 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu EXTSTROBE DO 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI0 TRIG1 DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 4 75 k pu PFI1 TRIG2 DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI2 CONVERT DIO 5 5 V 3 5 at 4 6 V 5 at 0 4
17. To set up and use your VXI MIO Series module you will need the following K One of the following modules VXI MIO 64E 1 VXI MIO 64XE 10 K VXI MIO Series User Manual K One or more of the following software packages and documentation ComponentWorks LabVIEW for Windows LabWindows CVI Measure NI DAQ for PC Compatibles VirtualBench VXI plug amp play instrument driver K Your VXIbus system Software Programming Choices There are several options to choose from when programming your National Instruments VXI DAQ hardware You can use LabVIEW LabWindows CVI Measure ComponentWorks VirtualBench or other application development environments with either NI DAQ or the VXI plug amp play instrument driver Both NI DAQ and the VXI plug amp play instrument drivers access the VXI DAQ hardware through the VISA driver software National Instruments Application Software ComponentWorks contains tools for data acquisition and instrument control built on NI DAQ driver software ComponentWorks provides a higher level programming interface for building virtual instruments through standard OLE controls and DLLs With ComponentWorks you can use all of the configuration tools resource management utilities and interactive control utilities included with NI DAQ Chapter 1 Introduction National Instruments Corporation 1 3 VXI MIO Series User Manual LabVIEW features interac
18. Trigger lowValue Chapter 3 Hardware Overview VXI MIO Series User Manual 3 14 National Instruments Corporation In low hysteresis analog triggering mode the trigger is generated when the signal value is less than lowValue with the hysteresis specified by highValue Figure 3 8 Low Hysteresis Analog Triggering Mode The analog trigger circuit generates an internal digital trigger based on the analog input signal and the user defined trigger levels This digital trigger can be used by any of the timing sections of the DAQ STC including the analog input analog output and general purpose counter timer sections For example the analog input section can be configured to acquire n scans after the analog input signal crosses a specific threshold As another example the analog output section can be configured to update its outputs whenever the analog input signal crosses a specific threshold Digital I O The VXI MIO Series modules contain eight lines of digital I O for general purpose use You can individually configure each line through software for either input or output At system startup and reset the digital I O ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines
19. V 6 10 V 3 05 V 1 The value of 1 LSB of the 12 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 12 bit count Note See Appendix A Specifications for absolute maximum ratings Chapter 3 Hardware Overview National Instruments Corporation 3 7 VXI MIO Series User Manual Dither When you enable dither you add approximately 0 5 LSB rms of white Gaussian noise to the signal to be converted by the ADC This addition is useful for applications involving averaging to increase the resolution of your VXI MIO Series module as in calibration or spectral analysis In such applications noise modulation is decreased and differential linearity is improved by the addition of the dither When taking DC measurements such as when checking the module calibration you should enable dither and average about 1 000 points to take a single reading This process removes the effects of quantization and reduces measurement noise resulting in improved resolution For high speed applications not involving averaging or spectral analysis you may want to disable the dither to reduce noise You enable and disable the dither circuitry through software Figure 3 2 illustrates the effect of dither on signal acquisition Figure 3 2a shows a small 4 LSB sine wave acquired with dither off The quantization of the ADC is clearly visible Figure 3 2b shows what ha
20. compatible multifunction analog digital and timing I O modules for VXIbus This family of modules features 12 bit and 16 bit ADCs with 64 analog inputs 12 bit and 16 bit DACs with voltage outputs eight lines of TTL compatible digital I O and two 24 bit counter timers for timing I O The VXI MIO Series modules use the National Instruments DAQ STC system timing controller for timer related functions The DAQ STC consists of three timing groups that control analog input analog output and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing resolution of 50 ns A common problem with other VXI modules is that you cannot easily synchronize several measurement functions to a common trigger or timing event The VXI MIO Series modules solve this problem by using VXIbus triggers to synchronize measurements on several VXI MIO Series modules You can interface the VXI MIO Series modules to an SCXI signal conditioning and multiplexing system to acquire over 3 000 analog signals from thermocouples RTDs strain gauges voltage sources and current sources You can also acquire or generate digital signals for communication and control Detailed specifications of the VXI MIO Series modules are in Appendix A Specifications Chapter 1 Introduction VXI MIO Series User Manual 1 2 National Instruments Corporation What You Need to Get Started
21. 0 7 can be configured as either one differential input or two single ended inputs ACH lt 16 63 gt AIGND Input Analog Input Channels 16 through 63 Each channel pair ACH lt i i 8 gt i 16 23 32 39 48 55 can be configured as either one differential input or two single ended inputs AISENSE AIGND Input Analog Input Sense This pin serves as the reference node for any of channels ACH lt 0 15 gt in NRSE configuration AISENSE2 AIGND Input Analog Input Sense This pin serves as the reference node for any of channels ACH lt 16 63 gt in NRSE configuration DAC0OUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output of analog output channel 0 DAC1OUT AOGND Output Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 EXTREF AOGND Input External Reference This is the external reference input for the analog output circuitry This pin is not available on the VXI MIO 64XE 10 AOGND Analog Output Ground The analog output voltages are referenced to this node All three ground references AIGND AOGND and DGND are connected together on your VXI MIO Series module DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply All three ground references AIGND AOGND and DGND are connected together on your VXI M
22. ACH See text for information on bias resistors See text for information on bias resistors R Signal Source Type ACH AIGND V1 ACH AIGND NOT RECOMMENDED ACH Vg V1 Ground loop losses Vg are added to measured signal V1 ACH AISENSE R AIGND V1 ACH AISENSE AIGND AIGND Chapter 4 Signal Connections VXI MIO Series User Manual 4 14 National Instruments Corporation Differential Connection Considerations DIFF Input Configuration A differential connection is one in which the VXI MIO Series module analog input signal has its own reference signal or signal return path These connections are available when the selected channel is configured in DIFF input mode The input signal is tied to the positive input of the PGIA and its reference signal or return is tied to the negative input of the PGIA When you configure a channel for differential input each signal uses two multiplexer input lines one for the signal and one for its reference signal Therefore with a differential configuration for every channel up to 32 analog input channels are available You should use differential input connections for any channel that meets any of the following conditions The input signal is low level less than 1 V The leads connecting the signal to the VXI MIO Series module are greater than 1
23. Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits For more information refer to the application note Field Wiring and Noise Consideration for Analog Signals available from National Instruments National Instruments Corporation 5 1 VXI MIO Series User Manual Calibration Chapter 5 This chapter discusses the calibration procedures for your VXI MIO Series module NI DAQ and the VXI plug amp play instrument drivers include calibration functions for performing all of the steps in the calibration process Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments On the VXI MIO Series modules these adjustments take the form of writing values to onboard calibration DACs CalDACs Some form of module calibration is required for all but the most forgiving applications If you do not perform module calibration your signals and measurements could have offset gain and linearity errors Three levels of calibration are available to you and described in this chapter The first level is the fastest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants Your VXI MIO Series module is factory calibrated before shipment at approximately 25 C to the lev
24. Signal Name Drive Impedance Input Output Protection Volts Power On Off Source mA at V Sink mA at V Rise Time ns Bias ACH lt 0 63 gt AI 100 G in parallel with 100 pF 25 15 200 pA AISENSE AISENSE2 AI 100 G in parallel with 100 pF 25 15 200 pA AIGND AI DAC0OUT AO 0 1 Short circuit to ground 5 at 10 V 5 at 10 V 20 V s DAC1OUT AO 0 1 Short circuit to ground 5 at 10 V 5 at 10 V 20 V s EXTREF AO 10 k 25 15 AOGND AO DGND DO 5 V DO 0 1 Short circuit to ground 1 A at 5 V DIO lt 0 7 gt DIO 5 5 V 13 at 4 6 V 24 at 0 4 1 1 50 k pu 1 SCANCLK DO 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu EXTSTROBE DO 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI0 TRIG1 ADIO 10 k 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu 2 PFI1 TRIG2 DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI2 CONVERT DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI3 GPCTR1_SOURCE DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI4 GPCTR1_GA
25. instrument drivers free of charge VXI plug amp play instrument drivers are one level above the NI DAQ device driver and contain high level software functions whose architecture is specified by the VXI plug amp play Systems Alliance The VXI plug amp play standards increase interoperability with other vendors and ensure that drivers are designed and presented in a consistent fashion that facilitates ease of use Refer to Figure 1 1 to see the relationship between your software components Chapter 1 Introduction National Instruments Corporation 1 5 VXI MIO Series User Manual Figure 1 1 The Relationship between the Programming Environment Your Instrument Driver and Your VXI DAQ Hardware Optional Equipment National Instruments offers a variety of products to use with your VXI MIO Series module including cables connector blocks and other accessories as follows Cables and cable assemblies shielded and ribbon Connector blocks SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3072 channels Low channel count signal conditioning modules boards and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays For more specific information about these products refer to your National Instruments catalogue or call
26. multiplexers oscillators operator interfaces and counters DGND digital ground signal DIFF differential mode differential input An analog input consisting of two terminals both of which are isolated from computer ground whose difference is measured DIO digital input output dithering The addition of Gaussian noise to an analog input signal DLL Dynamic Link Library A software module in Microsoft Windows containing executable code and data that can be called or used by Windows applications or by other DLLs Functions and data in a DLL are loaded and linked at run time when they are referenced by a Windows application or other DLLs DMA Direct Memory Access A method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to from computer memory DNL differential nonlinearity A measure in LSB of the worst case deviation of code widths from their ideal value of 1 LSB DRAM Dynamic RAM drivers driver software Software that controls a specific hardware device such as a DAQ board Glossary VXI MIO Series User Manual G 6 National Instruments Corporation dual access memory Memory that can be sequentially but not simultaneously accessed by more than one controller or processor Also known as shared memory dual ported memory Memory that can be simultaneously accessed by
27. 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A ACH55 ACH61 ACH52 ACH58 ACH49 ACH47 ACH38 ACH44 ACH43 ACH34 ACH40 ACH23 ACH29 ACH20 ACH26 ACH17 AIGND ACH14 ACH5 AISENSE3 ACH10 ACH1 EXTREF2 AOGND DIO1 DIO6 DGND EXTSTROBE PFI2 CONVERT GPCTR1_OUT PFI7 STARTSCAN GPCTR0_OUT B ACH62 ACH53 ACH59 ACH50 ACH56 ACH39 ACH45 ACH36 ACH35 ACH41 ACH32 ACH30 ACH21 ACH27 ACH18 ACH24 ACH15 ACH6 ACH12 ACH11 ACH2 ACH8 DAC1OUT DIO0 DIO5 DIO3 SCANCLK PFI0 TRIG1 PFI3 GPCTR1_SOURCE PFI5 UPDATE PFI8 GPCTR0_SOURCE FREQ_OUT C 1 SENSE for ACH16 through ACH63 2 This pin is not connected on the VXI MIO 64XE 10 3 SENSE for ACH0 through ACH15 Chapter 4 Signal Connections National Instruments Corporation 4 3 VXI MIO Series User Manual I O Connector Signal Descriptions Signal Name Reference Direction Description AIGND Analog Input Ground These pins are the reference point for single ended measurements and the bias current return point for differential measurements All three ground references AIGND AOGND and DGND are connected together on your VXI MIO Series module ACH lt 0 15 gt AIGND Input Analog Input Channels 0 through 15 Each channel pair ACH lt i i 8 gt i
28. EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks LabVIEW NI DAQ ComponentWorks DAQ STC MANTIS MITE NI PGIA NI VISA NI VXI SCXI and VirtualBench are trademarks of National Instruments Corporation Product and company names listed
29. computers electrical storms welders radio transmitters and Glossary National Instruments Corporation G 11 VXI MIO Series User Manual internal sources such as semiconductors resistors and capacitors Noise corrupts signals you are trying to send or receive NRSE nonreferenced single ended mode All measurements are made with respect to a common NRSE measurement system reference but the voltage at this reference can vary with respect to the measurement system ground O OLE Object Linking and Embedding A set of system services that provides a means for applications to interact and interoperate Based on the underlying Component Object Model OLE is object enabling system software Through OLE Automation an application can dynamically identify and use the services of other applications to build powerful solutions using packaged software OLE also makes it possible to create compound documents consisting of multiple sources of information from different applications onboard channels Channels provided by the plug in data acquisition board operating system Base level software that controls a computer runs programs interacts with users and communicates with installed hardware or peripheral devices optical isolation The technique of using an optoelectric transmitter and receiver to transfer data without electrical continuity to eliminate high potential differences and transients OUT output output
30. table 4 9 PFI6 WFTRIG signal description table 4 5 VXI MIO 64E 1 table 4 7 VXI MIO 64XE 10 table 4 9 PFI7 STARTSCAN signal description table 4 5 VXI MIO 64E 1 table 4 7 VXI MIO 64XE 10 table 4 9 PFI8 GPCTR0_SOURCE signal description table 4 5 VXI MIO 64E 1 table 4 7 VXI MIO 64XE 10 table 4 9 PFI9 GPCTR0_GATE signal description table 4 5 VXI MIO 64E 1 table 4 7 VXI MIO 64XE 10 table 4 9 PFIs programmable function inputs 4 24 to 4 25 common questions about C 5 to C 6 overview 4 23 signal routing 3 16 timing input connections 4 24 to 4 25 illustration 4 24 PGIA programmable gain instrumentation amplifier analog input connections 4 10 to 4 11 illustration 4 10 Index National Instruments Corporation I 7 VXI MIO Series User Manual common mode signal rejection 4 20 differential connections floating signal sources 4 16 to 4 17 ground referenced signal sources 4 15 single ended connections floating signal sources figure 4 19 grounded signal sources figure 4 20 physical specifications VXI MIO 64E 1 A 9 VXI MIO 64XE 10 A 16 pin assignments See I O connectors polarity input polarity and range 3 4 to 3 6 output polarity selection 3 10 to 3 11 posttriggered data acquisition 4 25 illustration 4 25 power connections 4 23 power requirement specifications VXI MIO 64E 1 A 9 VXI MIO 64XE 10 A 16 pretriggered data acquisition 4 25 illustration 4 26
31. when to use 4 18 SISOURCE signal 4 34 software installation 2 9 to 2 10 programming choices ComponentWorks 1 2 LabVIEW and LabWindows CVI 1 3 NI DAQ driver software 1 3 to 1 4 VirtualBench 1 3 specifications VXI MIO 64E 1 analog input A 1 to A 4 amplifier characteristics A 3 dynamic characteristics A 4 input characteristics A 1 to A 2 stability A 4 transfer characteristics A 3 analog output A 5 to A 7 dynamic characteristics A 6 output characteristics A 5 stability A 6 to A 7 transfer characteristics A 5 to A 6 voltage output A 6 Index National Instruments Corporation I 9 VXI MIO Series User Manual digital I O A 7 environment A 9 physical A 9 power requirements A 9 timing I O A 7 to A 8 triggers A 8 analog trigger A 8 digital trigger A 8 VXIbus A 8 VXI MIO 64XE 10 analog input A 10 to A 12 amplifier characteristics A 11 dynamic characteristics A 12 input characteristics A 10 stability A 12 transfer characteristics A 11 analog output A 13 to A 14 dynamic characteristics A 13 output characteristics A 13 stability A 14 transfer characteristics A 13 voltage output A 13 digital I O A 14 environment A 16 physical A 16 power requirement A 16 timing I O A 15 triggers analog trigger A 15 to A 16 digital trigger A 16 VXIbus A 16 stability analog input specifications VXI MIO 64E 1 A 4 VXI MIO 64XE 10 A 12 analog output specifications VXI MIO 64E 1 A 6 to A 7
32. 1 5 50 k pu PFI3 GPCTR1_SOURCE DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI4 GPCTR1_GATE DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu GPCTR1_OUT DO 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu Chapter 4 Signal Connections National Instruments Corporation 4 9 VXI MIO Series User Manual Analog Input Signal Connections The VXI MIO 64E 1 and VXI MIO 64XE 10 analog input signals are ACH lt 0 63 gt AISENSE AISENSE2 and AIGND The ACH lt 0 63 gt signals are tied to the 64 analog input channels of both modules In single ended mode signals connected to ACH lt 0 63 gt are routed to the positive input of both modules In differential mode signals connected to ACH lt 0 7 16 23 32 39 48 55 gt are routed to the positive input of the PGIA and signals connected to ACH lt 8 15 24 31 40 47 56 63 gt are routed to the negative input of the PGIA Warning Exceeding the differential and common mode input ranges distorts your input signals Exceeding the maximum input voltage rating can damage the VXI MIO Series module and your VXIbus system National Instruments is NOT liable for any damages resulting from such signal connections The maximum input voltage ratings are listed in Tables 4 1 and 4 2 in the Protection column PFI5 UPDATE DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI6 WFTRIG
33. 28 62 29 63 30 64 31 65 32 66 33 67 34 68 Not connected on the VXI MIO 64XE 10 Appendix B Optional Cable Connector Descriptions National Instruments Corporation B 3 VXI MIO Series User Manual Figure B 2 shows the pin assignments for the 68 pin extended analog input connector This is the other 68 pin connector available when you use the SH966868 cable assembly with the VXI MIO 64E 1 or VXI MIO 64XE 10 Figure B 2 68 Pin Extended Analog Input Connector Pin Assignments NC NC NC NC NC NC NC NC NC ACH 55 ACH 54 ACH 61 ACH 52 ACH 51 ACH 58 ACH 49 ACH 48 ACH 47 ACH 38 ACH 37 ACH 44 AIGND ACH 35 ACH 34 ACH 41 ACH 32 ACH 23 ACH 30 ACH 21 ACH 20 ACH 27 ACH 18 ACH 17 ACH 24 NC NC NC NC NC NC NC NC NC ACH 63 ACH 62 ACH 53 ACH 60 ACH 59 ACH 50 ACH 57 ACH 56 ACH 39 ACH 46 ACH 45 ACH 36 AISENSE2 ACH 43 ACH 42 ACH 33 ACH 40 ACH 31 ACH 22 ACH 29 ACH 28 ACH 19 ACH 26 ACH 25 ACH 16 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68 National Instruments Corporation C 1 VXI MIO Series User Manual Common Questions Appendix C This appendix contains a list of commonly asked questions and the
34. 5 Tighten the retaining screws on the top and bottom edges of the front panel 6 Replace or close any doors or covers to the mainframe Software Installation Regardless of your programming methodology proper operation of your VXI MIO module depends on the correct installation of VISA on your VXIbus controller If VISA is not installed you must get this information from your VXIbus controller manufacturer If you have a National Instruments VXIbus controller contact our sales department for information on obtaining the NI VISA software at no charge If you are using NI DAQ refer to your release notes Find the installation section for your operating system and follow the instructions given there If you are using LabVIEW refer to your LabVIEW release notes to install your application software After you have installed LabVIEW refer to the NI DAQ release notes and follow the instructions given there for your operating system and LabVIEW Chapter 2 Con guration and Installation VXI MIO Series User Manual 2 10 National Instruments Corporation If you are using LabWindows CVI refer to your LabWindows CVI release notes to install your application software After you have installed LabWindows CVI refer to the NI DAQ release notes and follow the instructions given there for your operating system and LabWindows CVI If you are using ComponentWorks Measure or VirtualBench application software refer to your docume
35. 84 00 32 84 86 00 Singapore 2265886 2265887 Spain 91 640 0085 91 640 0533 Sweden 08 730 49 70 08 730 43 70 Switzerland 056 200 51 51 056 200 51 55 Taiwan 02 377 1200 02 737 4644 U K 01635 523545 01635 523154 FaxBack Support E Mail Support currently U S only Click here to comment on this document via the National Instruments website at http www natinst com documentation daq Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name__________________________________________________________________________ Company_______________________________________________________________________ Address ________________________________________________________________________ _______________________________________________________________________________ Fax ___ ___________________ Phone ___ ________________________________________ Computer brand ________________ Model ________________ Processor __________________ Opera
36. Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title VXI MIO Series User Manual Edition Date August 1996 Part Number 321246A 01 Please comment on the completeness clarity and organization of the manual _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ If you find errors in the manual please record the page numbers and describe the errors _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ __________________________________
37. DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI7 STARTSCAN DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI8 GPCTR0_SOURCE DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI9 GPCTR0_GATE DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu GPCTR0_OUT DO 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu FREQ_OUT DO 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output Note The tolerance on the 50 k pullup and pulldown resistors is very large Actual value may range between 17 and 100 k Table 4 2 VXI MIO 64XE 10 I O Signal Summary Continued Signal Name Drive Impedance Input Output Protection Volts Power On Off Source mA at V Sink mA at V Rise Time ns Bias Chapter 4 Signal Connections VXI MIO Series User Manual 4 10 National Instruments Corporation In NRSE mode the AISENSE and AISENSE2 signals are connected internally to the negative input of the VXI MIO Series module PGIA when their corresponding channels are selected In DIFF and RSE modes the AISENSE AISENSE signals are left unconnected AIGND is an analog input common signal that is routed directly to the ground tie point on the VXI MIO Series modules You can use this signal for a general anal
38. National Instruments Documentation xiii Related Documentation xiv Customer Communication xiv Chapter 1 Introduction About the VXI MIO Series 1 1 What You Need to Get Started 1 2 Software Programming Choices 1 2 National Instruments Application Software 1 2 NI DAQ Driver Software 1 3 VXI plug amp play Instrument Drivers 1 4 Optional Equipment 1 5 Custom Cabling 1 6 Unpacking 1 6 Chapter 2 Configuration and Installatio
39. Scans occurring within a data acquisition sequence may be gated by either the hardware AIGATE signal or software command register gate AIGATE Signal Any PFI pin can externally input the AIGATE signal which is not available as an output on the I O connector The AIGATE signal can mask off scans in a data acquisition sequence You can configure the PFI pin you select as the source for the AIGATE signal in either the level detection or edge detection mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur In the edge detection mode the first active edge disables the STARTSCAN signal and the second active edge enables STARTSCAN The AIGATE signal can neither stop a scan in progress nor continue a previously gated off scan in other words once a scan has started t w t w 50 100 ns Chapter 4 Signal Connections VXI MIO Series User Manual 4 34 National Instruments Corporation AIGATE does not gate off conversions until the beginning of the next scan and conversely if conversions are being gated off AIGATE does not gate them back on until the beginning of the next scan SISOURCE Signal Any PFI pin can externally input the SISOURCE signal which is not available as an output on the I O connector The onboard scan interval counter uses the SISOURCE signal as a cloc
40. Timing 4 37 Figure 4 27 UPDATE Output Signal Timing 4 37 Figure 4 28 UISOURCE Signal Timing 4 38 Figure 4 29 GPCTR0_SOURCE Signal Timing 4 39 Figure 4 30 GPCTR0_GATE Signal Timing in Edge Detection Mode 4 40 Figure 4 31 GPCTR0_OUT Signal Timing 4 40 Figure 4 32 GPCTR1_SOURCE Signal Timing 4 41 Figure 4 33 GPCTR1_GATE Signal Timing in Edge Detection Mode 4 42 Figure 4 34 GPCTR1_OUT Signal Timing 4 43 Figure 4 35 GPCTR Timing Summary 4 43 Figure B 1 68 Pin MIO Connector Pin Assignments B 2 Figure B 2 68 Pin Extended Analog Input Connector Pin Assignments B 3 Table of Contents VXI MIO Series User Manual x National Instruments Corporation Tables Table 2 1 VXI MIO Series DRAM Configuration 2 6 Table 3 1 Available Input Configurations for the VXI MIO Series
41. VXI MIO 64XE 10 VXI MIO Series User Manual A 16 National Instruments Corporation External input PFI0 TRIG1 Impedance 10 k Coupling DC Protection 0 5 to 5 5 V when configured as a digital signal 35 V when configured as an analog trigger signal or disabled 35 V powered off Accuracy 1 of fullscale range Digital Trigger Compatibility TTL Response Rising or falling edge Pulse width 10 ns min VXIbus Trigger Trigger lines Supports 5 TTL and 2 ECL trigger lines Power Requirement 5 VDC 2 82 A typ 3 38 A max Not including current used by accessories 5 2 VDC 0 15 A typ 0 18 A max 2 VDC 0 04 A typ 0 06 A max Power available at I O connector 4 65 VDC to 5 25 VDC at 1 A Physical Dimensions VXI C size single slot I O connector 96 pin DIN Environment Operating temperature 0 to 55 C Storage temperature 20 to 70 C Relative humidity
42. VXI MIO 64XE 10 A 14 STARTSCAN signal timing connections 4 30 to 4 31 input timing figure 4 30 output timing figure 4 31 T technical support D 1 to D 2 theory of operation See hardware overview timebase 3 16 timing connections 4 23 to 4 44 common questions about C 4 to C 6 data acquisition timing connections 4 25 to 4 34 AIGATE signal 4 33 to 4 34 CONVERT signal 4 32 to 4 33 EXTSTROBE signal 4 26 to 4 27 SCANCLK signal 4 26 SISOURCE signal 4 34 STARTSCAN signal 4 30 to 4 31 TRIG1 signal 4 27 to 4 28 TRIG2 signal 4 28 to 4 29 typical posttriggered acquisition figure 4 25 typical pretriggered acquisition figure 4 26 general purpose timing signal connections 4 38 to 4 44 FREQ_OUT signal 4 44 GPCTR0_GATE signal 4 39 to 4 40 GPCTR0_OUT signal 4 40 GPCTR0_SOURCE signal 4 38 to 4 39 GPCTR0_UP_DOWN signal 4 40 GPCTR1_GATE signal 4 41 to 4 42 GPCTR1_OUT signal 4 42 to 4 43 GPCTR1_SOURCE signal 4 41 GPCTR1_UP_DOWN signal 4 43 to 4 44 programmable function input connections 4 24 to 4 25 timing I O connections figure 4 24 Index VXI MIO Series User Manual I 10 National Instruments Corporation waveform generation timing connections 4 34 to 4 38 UISOURCE signal 4 37 to 4 38 UPDATE signal 4 36 to 4 37 WFTRIG signal 4 34 timing I O specifications VXI MIO 64E 1 A 7 to A 8 VXI MIO 64XE 10 A 15 timing signal routing 3 15 to 3 16 CONVERT signal routing figu
43. VXI MIO Series User Manual Multifunction I O Modules for VXIbus August 1996 Edition Part Number 321246A 01 Copyright 1996 National Instruments Corporation All Rights Reserved Click here to comment on this document via the National Instruments website at http www natinst com documentation daq GPIB gpib support natinst com DAQ daq support natinst com VXI vxi support natinst com LabVIEW lv support natinst com LabWindows lw support natinst com HiQ hiq support natinst com Lookout lookout support natinst com E mail info natinst com FTP Site ftp natinst com Web Address http www natinst com BBS United States 512 794 5422 or 800 327 3077 BBS United Kingdom 01635 551422 BBS France 1 48 65 15 59 512 418 1111 Tel 512 795 8248 Fax 512 794 5678 Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Israel 03 5734815 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 95 800 010 0793 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02 377 1200 U K 01635 523545 National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin TX 7873
44. VXI mainframe via one or more VXIbus extended controllers The computer then exerts overall control over VXIbus system operations external trigger A voltage pulse from an external source that triggers an event such as A D conversion EXTREF external reference signal EXTSTROBE external strobe signal Glossary National Instruments Corporation G 7 VXI MIO Series User Manual F FIFO first in first out memory buffer The first data stored is the first data sent to the acceptor FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be retrieved or output For example an analog input FIFO stores the results of A D conversions until the data can be retrieved into system memory a process that requires the servicing of interrupts and often the programming of the DMA controller This process can take several milliseconds in some cases During this time data accumulates in the FIFO for future retrieval With a larger FIFO longer latencies can be tolerated In the case of analog output a FIFO permits faster update rates because the waveform data can be stored on the FIFO ahead of time This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device floating signal sources Signal sources with voltage signals that are not connected to an absolute reference or system ground Also called nonreferenced signal sources Some common examp
45. although they also apply to signal routing in general Take the following precautions to minimize noise pickup and maximize measurement accuracy Use differential analog input connections to reject common mode noise Use individually shielded twisted pair wires to connect analog input signals to the module With this type of wire the signals attached to the CH and CH inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference Route signals to the module carefully Keep cabling away from noise sources A common noise source in many data acquisition systems is the video monitor Separate the monitor from the analog signals as much as possible The following recommendations apply for all signal connections to your VXI MIO Series module Separate VXI MIO Series module signal lines from high current or high voltage lines These lines are capable of inducing currents in or voltages on the VXI MIO Series module signal lines if they run in parallel paths at a close distance To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other Do not run signal lines through conduits that also contain power lines
46. and correct for almost all of its calibration related errors without any external signal connections Your National Instruments software provides a self calibration method for you This self calibration process which generally takes less than a minute is the preferred method of assuring accuracy in your application Initiate self calibration to ensure that you minimize the effects of any offset gain and linearity drifts particularly those due to warmup Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference External calibration addresses this error which is discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration Your VXI MIO Series module has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are listed in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using your module at an extreme temperature or if the onboard reference has not been measured for a year or more you may wish to externally calibrate your module An external calibration refers to calibrating your module w
47. are recommended for greater signal integrity for any input signal that does not meet the preceding conditions You can software configure the VXI MIO Series module channels for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the VXI MIO Series module provides the reference ground point for the external signal The NRSE input configuration is used for ground referenced signal sources in this case the external signal supplies its own reference ground point and the VXI MIO Series module should not supply one In single ended configurations more electrostatic and magnetic noise couples into the signal connections than in differential configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors Chapter 4 Signal Connections National Instruments Corporation 4 19 VXI MIO Series User Manual Single Ended Connections for Floating Signal Sources RSE Configuration Figure 4 6 shows how to connect a floating signal source to a channel on the VXI MIO Series module configured for RSE mode Figure 4 6 Single Ended Input Connections for Nonreferenced or Floating Signals Single Ended Connections for Grounded Signal Sources N
48. bit or 1 MB x 36 bit 8 MB ON 2 MB x 32 bit or 2 MB x 36 bit 8 MB Yes ON 2 MB x 32 bit or 2 MB x 36 bit 2 MB x 32 bit or 2 MB x 36 bit 16 MB ON 4 MB x 32 bit or 4 MB x 36 bit 16 MB Yes OFF 4 MB x 32 bit or 4 MB x 36 bit 4 MB x 32 bit or 4 MB x 36 bit 32 MB OFF 8 MB x 32 bit or 8 MB x 36 bit 32 MB Yes OFF 8 MB x 32 bit or 8 MB x 36 bit 8 MB x 32 bit or 8 MB x 36 bit 64 MB Yes OFF Table 2 1 VXI MIO Series DRAM Configuration Continued Bank 0 Bank 1 Total DRAM National Instruments Option Switch Setting of S3 Chapter 2 Con guration and Installation VXI MIO Series User Manual 2 8 National Instruments Corporation Figure 2 5 Load User Factory Configuration Protect Change Factory Configuration Use switch S1 to change the factory default configuration settings by permitting writes to the factory settings section of the EEPROM This switch serves as a safety measure and should not be needed under normal circumstances When this switch is off its default setting the factory configuration of the EEPROM is protected so any writes to the factory area will be ignored Refer to Figure 2 6 for configuration settings Figure 2 6 Protect Change Factory Configuration Hardware Installation This section contains general installation instructions for the VXI MIO Series modules Consult your VXIbus mainframe user manua
49. channel 1 then 100 points from channel 2 and so on Chapter 3 Hardware Overview VXI MIO Series User Manual 3 10 National Instruments Corporation Analog Output VXI MIO 64E 1 This module supplies two channels of analog output voltage at the I O connector The reference and range for the analog output circuitry is software selectable The reference can be either internal or external whereas the range can be either bipolar or unipolar VXI MIO 64XE 10 This module supplies two channels of analog output voltage at the I O connector The range is bipolar or unipolar Analog Output Reference Selection VXI MIO 64E 1 You can connect each D A converter DAC to this module s internal reference of 10 V or to the external reference signal connected to the external reference EXTREF pin on the I O connector This signal applied to EXTREF should be between 10 and 10 V You do not need to configure both channels for the same mode Analog Output Polarity Selection Selecting a bipolar range for a particular DAC means that any data written to that DAC will be interpreted as two s complement format In two s complement mode data values written to the analog output channel can be either positive or negative If you select unipolar range data is interpreted in straight binary format In straight binary mode data values written to the analog output channel range must be positive VX
50. low hysteresis analog triggering mode figure 3 14 digital I O 3 14 timing signal routing 3 15 to 3 16 CONVERT signal routing figure 3 15 programmable function inputs 3 16 VXIbus triggers 3 17 I input characteristics VXI MIO 64E 1 A 1 to A 2 VXI MIO 64XE 10 A 10 input configurations 4 12 to 4 20 available input modes 3 3 to 3 4 DIFF table 3 3 NRSE table 3 3 RSE table 3 3 common mode signal rejection 4 20 differential connections DIFF input configuration 4 14 floating signal sources 4 16 to 4 17 ground referenced signal sources 4 15 nonreferenced signal sources 4 16 to 4 17 recommended configuration figure 4 13 single ended connections 4 18 to 4 20 floating signal sources RSE configuration 4 19 grounded signal sources NRSE configuration 4 19 to 4 20 input polarity and range 3 4 to 3 6 mixing bipolar and unipolar channels note 3 5 selection considerations 3 6 VXI MIO 64E 1 3 4 to 3 5 actual range and measurement precision table 3 4 to 3 5 VXI MIO 64XE 10 3 5 to 3 6 actual range and measurement precision table 3 6 installation See also configuration common questions about C 2 hardware installation 2 8 to 2 9 software installation 2 9 to 2 10 unpacking VXI MIO series boards 1 6 I O connectors 4 1 to 4 9 exceeding maximum ratings warning 4 1 optional cable connectors 68 pin extended analog input connector pin assignments figure B 3 68 pin MIO conne
51. output low V ref reference voltage Glossary VXI MIO Series User Manual G 16 National Instruments Corporation VXIbus VMEbus eXtensions for Instrumentation VXIbus trigger lines These are the eight TTL and two ECL lines on the VXIbus backplane which are used for intermodule communication Typical applications are triggering and clocking measurements VXI plug amp play Systems A group of VXI developers dedicated to making VXI devices as Alliance easy to use as possible primarily by simplifying software development W waveform Multiple voltage readings taken at a specific sampling rate WFTRIG waveform generation trigger signal wire Data path between nodes word serial The simplest required communication protocol used by message based devices in the VXIbus system It uses the A16 communication registers to transfer data with a simple polling handshake method National Instruments Corporation I 1 VXI MIO Series User Manual Index Numbers 5 V signal description 4 3 power connections 4 23 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 A ACH lt 0 15 gt signal table 4 3 ACH lt 0 63 gt signal analog input connections 4 9 VXI MIO 64XE 10 table 4 8 ACH lt 16 63 gt signal table 4 3 address logical See VXIbus logical address AIGATE signal 4 33 to 4 34 AIGND signal analog input connections 4 9 4 10 description table 4 3 differen
52. power distribution system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference may appear as an error in the measurement The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal Chapter 4 Signal Connections VXI MIO Series User Manual 4 12 National Instruments Corporation Input Configurations You can configure your VXI MIO Series module for one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources Chapter 4 Signal Connections National Instruments Corporation 4 13 VXI MIO Series User Manual Figure 4 3 summarizes the recommended input configuration for both types of signal sources Figure 4 3 Summary of Analog Input Connections Input Differential DIFF Referenced Single Ended Ground RSE Nonreferenced Single Ended NRSE Floating Signal Source Not Connected to Earth Ground Grounded Signal Source Examples Ungrounded thermocouples Signal conditioning with isolated outputs Battery devices Examples Plug in instruments with nonisolated outputs V1 ACH V1 ACH
53. properly Analog Input and Output 8 I m using my module in differential analog input mode and I have connected a differential input signal but my readings are random and drift rapidly What s wrong Check your ground reference connections Your signal may be referenced to a level that is considered floating with reference to the module ground reference Even if you are in differential mode the signal must still be referenced to the same ground level as the module reference There are various methods of achieving this Appendix C Common Questions National Instruments Corporation C 3 VXI MIO Series User Manual while maintaining a high common mode rejection ratio CMRR These methods are outlined in Chapter 4 Signal Connections 9 Can I sample across a number of channels on a VXI MIO Series module while each channel is being sampled at a different rate NI DAQ features a function called SCAN_Sequence_Setup which allows for multirate scanning of your analog input channels Refer to the NI DAQ Function Reference Manual for PC Compatibles for more details 10 I m using the DACs to generate a waveform but I discovered with a digital oscilloscope that there are glitches on the output signal Is this normal When it switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of
54. scalers 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Digital logic levels Level Min Max Input low voltage 0 V 0 8 V Input high voltage 2 V 5 V Input low current Vin 0 V 320 A Input high current Vin 5 V 10 A Output low voltage IOL 24 mA 0 4 V Output high voltage IOH 13 mA 4 35 V 1 000 h Appendix A Speci cations for VXI MIO 64E 1 VXI MIO Series User Manual A 8 National Instruments Corporation Frequency scalers 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns in edge detect mode Min gate pulse duration 10 ns in edge detect mode Data transfers DMA interrupts programmed I O Triggers Analog Trigger Source ACH lt 0 63 gt PFI0 TRIG1 Level full scale internal 10 V external Slope Positive or negative software selectable Resolution 8 bits 1 in 256 Hysteresis Programmable Bandwidt
55. to 0 2 V 100 0 1 V 0 to 0 1 V Appendix A Speci cations for VXI MIO 64XE 10 National Instruments Corporation A 11 VXI MIO Series User Manual Transfer Characteristics Relative accuracy 0 75 LSB typ 1 LSB max DNL 0 5 LSB typ 1 LSB max No missing codes 16 bits guaranteed Offset error Pregain error after calibration 3 V max Pregain error before calibration 2 2 mV max Postgain error after calibration 76 V max Postgain error before calibration 102 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max Before calibration 2 150 ppm of reading max With gain error adjusted to 0 at gain 1 Gain 1 200 ppm of reading Amplifier Characteristics Input impedance Normal powered on 100 G in parallel with 100 pF Powered off 1 k min Overload 1 k min Input bias current 1 nA Input offset current 2 nA CMRR DC to 60 Hz Gain 1 92 dB Gain 2 97 dB Gain 5 101 dB Gain 10 104
56. to 64 MB The VXI MIO module supports DRAM speeds of 80 ns or faster Use switch S3 to select the size of each SIMM The SIMM sockets are accessible only by removing the component right side cover but S3 is P1 Connector U73 VXI MIO 64XE 10 Module 1 2 3 4 5 6 7 8 Logical Address Switch Push up for logic 1 Push down for logic 0 a Switch Set to Logical Address 2 Default 1 2 3 4 5 6 7 8 Logical Address Switch Push up for logic 1 Push down for logic 0 b Switch Set to Logical Address 192 LSB MSB MSB LSB P1 Connector U73 VXI MIO 64XE 10 Module Chapter 2 Con guration and Installation VXI MIO Series User Manual 2 6 National Instruments Corporation accessible with the cover on To access the SIMM sockets perform the following steps 1 Remove the four screws on the top the four screws on the bottom and the three screws on the right side cover of the metal enclosure 2 If the SIMMs are 4 MB x 32 bit or larger set S3 as shown in Figure 2 4a 3 For SIMMs smaller than 4 MB x 32 bit set S3 as shown in Figure 2 4b Figure 2 4 SIMM Size Configuration Refer to Table 2 1 to properly adjust the switch ON or OFF for all supported DRAM configurations Many of the DRAM options are available from National Instruments Table 2 1 VXI MIO Series DRAM Configuration Bank 0 Bank 1 Total DRAM National Instruments Option Switch Setting of S3 0
57. to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 12 shows a typical pretriggered data acquisition sequence The description for each signal shown in these figures is included later in this chapter Figure 4 11 Typical Posttriggered Acquisition 1 3 0 4 2 TRIG1 STARTSCAN CONVERT Scan Counter Chapter 4 Signal Connections VXI MIO Series User Manual 4 26 National Instruments Corporation Figure 4 12 Typical Pretriggered Acquisition SCANCLK Signal SCANCLK is an output only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configured so that a low to high leading edge can clock external analog input multiplexers indicating when the input signal has been sampled and can be removed This signal has a 400 to 500 ns pulse width and is software enabled Figure 4 13 shows the timing for the SCANCLK signal Figure 4 13 SCANCLK Signal Timing EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode your software controls the EXTSTROBE Don t Care 0 1 2 3 1 0 2 2 2 TRIG1 TRIG2 S
58. 0 5 10 V 1 5 V 0 to 10 V 2 2 5 V 0 to 5 V 5 1 V 0 to 2 V 10 500 mV 0 to 1 V 20 250 mV 0 to 500 mV 50 100 mV 0 to 200 mV 100 50 mV 0 to 100 mV Appendix A Speci cations for VXI MIO 64E 1 National Instruments Corporation A 3 VXI MIO Series User Manual Transfer Characteristics Relative accuracy 0 5 LSB typ dithered 1 5 LSB max undithered DNL 0 5 LSB typ 1 0 LSB max No missing codes 12 bits guaranteed Offset error Pregain error after calibration 12 V max Pregain error before calibration 2 5 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration gain 1 0 02 of reading max Before calibration 2 5 of reading max Gain 1 with gain error adjusted to 0 at gain 1 0 02 of reading max Amplifier Characteristics Input impedance Normal powered on 100 G in parallel with 100 pF Powered off 1 k min Overload
59. 0 5039 Tel 512 794 0100 Internet Support Bulletin Board Support FaxBack Support Telephone Support U S International Offices Important Information Warranty The VXI MIO Series boards are warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is ac
60. 0 ft 3 m The input signal requires a separate ground reference point or return signal The signal leads travel through noisy environments DIFF input connections reduce pick up noise and increase common mode noise rejection Differential signal connections also allow input signals to float within the common mode limits of the PGIA Chapter 4 Signal Connections National Instruments Corporation 4 15 VXI MIO Series User Manual Differential Connections for Ground Referenced Signal Sources Figure 4 4 shows how to connect a ground referenced signal source to a channel on a VXI MIO Series module configured in DIFF input mode Figure 4 4 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the VXI MIO Series module ground shown as V cm in Figure 4 4 Ground Referenced Signal Source Common Mode Noise and Ground Potential Other Input Multiplexers AISENSE Instrumentation Amplifier Vm Measured Voltage AIGND Vs Vcm I O Connector ACH lt 0 7 gt ACH lt 8 15 gt Selected Channel in DIFF Configuration PGIA Chapter 4 Signal Connections VXI MIO Series User Manual 4 16 National Instruments Corporation Differential Connections for Nonreferenced or Floating Sig
61. 2 self calibration 5 2 charge injection 3 9 commonly asked questions See questions about VXI MIO series common mode signal rejection 4 20 ComponentWorks software 1 2 configuration See also input configurations block diagrams VXI MIO 64E 1 parts locator diagram 2 3 VXI MIO 64XE 10 parts locator diagram 2 4 common questions about C 2 loading USER FACTORY configuration 2 7 to 2 8 protecting changing FACTORY configuration 2 8 SIMM size 2 5 to 2 6 accessing SIMM sockets 2 6 DRAM configuration table 2 6 to 2 7 VXIbus logical address 2 1 to 2 2 connectors See I O connectors CONVERT signal signal routing 3 15 timing connections 4 32 to 4 33 input timing figure 4 32 output timing figure 4 33 customer communication xiv D 1 to D 2 Index National Instruments Corporation I 3 VXI MIO Series User Manual D DAC0OUT signal analog output connections 4 20 to 4 21 description table 4 3 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 DAC1OUT signal analog output connections 4 20 to 4 21 description table 4 3 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 DAQ STC C 1 data acquisition timing connections 4 25 to 4 34 AIGATE signal 4 33 to 4 34 CONVERT signal 4 32 to 4 33 EXTSTROBE signal 4 26 to 4 27 posttriggered acquisition figure 4 25 pretriggered acquisition figure 4 26 SCANCLK signal 4 26 SISOURCE signal 4 34 STARTSCAN sign
62. 48 channels 16 differentially configured channels and 32 single ended channels Table 3 1 describes the three input configurations Table 3 1 Available Input Configurations for the VXI MIO Series Configuration Description DIFF A channel configured in DIFF mode uses two analog input channel lines One line connects to the positive input of the module programmable gain instrumentation amplifier PGIA and the other connects to the negative input of the PGIA RSE A channel configured in RSE mode uses one analog input channel line which connects to the positive input of the PGIA The negative input of the PGIA is internally tied to analog input ground AIGND NRSE A channel configured in NRSE mode uses one analog input channel line which connects to the positive input of the PGIA The negative input of the PGIA connects to the analog input sense AISENSE input Chapter 3 Hardware Overview VXI MIO Series User Manual 3 4 National Instruments Corporation For more information about the three types of input configuration refer to the Analog Input Signal Connections section in Chapter 4 Signal Connections which contains diagrams showing the signal paths for the three configurations Input Polarity and Input Range VXI MIO 64E 1 This module has two input polarities unipolar and bipolar The VXI MIO 64E 1 has a unipolar input range of 10 V 0 to 10 V and a bipolar input ra
63. C also makes buffered operations possible such as direct up down control single or pulse train generation equivalent time sampling buffered period and buffered semiperiod measurement 14 I m using one of the general purpose counter timers on my VXI MIO Series module but I do not see the counter timer output on the I O connector What am I doing wrong If you are using the NI DAQ language interface or LabWindows CVI you must configure the output line to output the signal to the I O connector Use the Select_Signal call in NI DAQ to configure the output line By default all timing I O lines except EXTSTROBE are tri stated 15 How does NI DAQ treat bogus missed data transfer errors that can arise during DMA driven GPCTR buffered input operations When doing buffered transfers using GPCTR function calls with DMA you can call GPCTR_Watch to indicate dataTransfer errors NI DAQ takes a snapshot of transfers and counts how many points have been transferred If all the points have been transferred and the first instance of this error occurs NI DAQ returns a gpctrDataTransferWarning indicating that the error could be bogus If all the points have not been transferred NI DAQ returns the genuine error The error continues to be returned until the acquisition completes The error occurs because NI DAQ disarms the counter from generating any more requests in the interrupt service routine Due to int
64. DIN Environment Operating temperature 0 to 55 C Storage temperature 20 to 70 C Relative humidity 5 to 90 noncondensing Appendix A Speci cations for VXI MIO 64XE 10 VXI MIO Series User Manual A 10 National Instruments Corporation VXI MIO 64XE 10 Analog Input Input Characteristics Number of channels 64 single ended or 32 differential software selectable Type of ADC Successive approximation Resolution 16 bits 1 in 65 536 Maximum sampling rate 100 kS s guaranteed Input coupling DC Maximum working voltage Each input should remain within 11 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ACH lt 0 63 gt AISENSE AISENSE2 FIFO buffer size 512 S Data transfers DMA interrupts programmed I O Configuration memory size 512 words Input signal ranges Module Gain Software Selectable Module Range Software Selectable Bipolar Unipolar 1 10 0 V 0 to 10 V 2 5 0 V 0 to 5 V 5 2 0 V 0 to 2 V 10 1 0 V 0 to 1 V 20 0 5 V 0 to 0 5 V 50 0 2 V 0
65. G 14 National Instruments Corporation signal Any communication between message based devices consisting of a write to a Signal register SIMM Single In line Memory Module SISOURCE SI counter clock signal slot A position where a module can be inserted into a VXIbus backplane Each slot provides the 96 pin J connectors to interface with the board P connectors A slot can have one two or three connectors S s Samples per Second Used to express the rate at which a DAQ board samples an analog signal STARTSCAN start scan signal statically configured device A device whose logical address cannot be set through software that is it is not dynamically configurable system A system consists of one or more mainframes that are connected all sharing a common Resource Manager Each device in a system has a unique logical address system RAM RAM installed on a personal computer and used by the operating system as contrasted with onboard RAM T TC terminal count The highest value of a counter THD total harmonic distortion The ratio of the total rms signal due to harmonic distortion to the overall rms signal in dB or percent transfer rate The rate measured in bytes s at which data is moved from source to destination after software initialization and set up operations the maximum rate at which the hardware can operate TRIG trigger signal trigger Any event that causes or starts some form of data ca
66. Glossary VXI MIO Series User Manual G 4 National Instruments Corporation command Any communication from a Commander to a Message Based Servant that consists of a write to the Servants Data Low register possibly preceded by a write to the Data High or Data High and Data Extended registers commander A message based device that is also a bus master and can control one or more servants component software An application that contains one or more component objects that can freely interact with other component software Examples include OLE enabled applications such as Microsoft Visual Basic and OLE Controls for virtual instrumentation in ComponentWorks Configuration Registers 1 A set of registers through which the system can identify a module device type model manufacturer address space and memory requirements In order to support automatic system and memory configuration the VXIbus specification requires that all VXIbus devices have a set of such registers 2 The A16 registers of a device that are required for the system configuration process CONVERT convert signal counter timer A circuit that counts external pulses or clock pulses timing crosstalk An unwanted signal on one channel due to an input on a different channel D D A digital to analog DAC D A converter DAC0OUT analog channel 0 output signal DAC1OUT analog channel 1 output signal DAQ data acquisition 1 Collecting and mea
67. I Local Bus VXI Local Bus Digital I O 8 Configuration Memory DRAM Circuitry AD Control IO Data Lines AI Control IO Data Lines IO Control IRQ and DMA Lines IO Control IO Control IO Control Address Data Control Signals Arbitration Signals Interrupts Utility Signals VXI Triggers ECL Triggers CLK10 CLK10 ECL Triggers TTL Level MODIO Lines IO Data Lines IO Data Lines IO Data Lines IO Data Lines IO Address Lines IO Address Lines IO Address Lines Optional RITSI Bus DRAM Control Signals RITSI Bus Logical Address Switch AD Control Chapter 3 Hardware Overview National Instruments Corporation 3 3 VXI MIO Series User Manual Analog Input The analog input section of each VXI MIO Series module is software configurable You can select different analog input configurations through application software designed to control the VXI MIO Series modules The following sections describe in detail each of the analog input categories Input Mode The VXI MIO Series modules have three different input modes nonreferenced single ended NRSE input referenced single ended RSE input and differential DIFF input The single ended input configurations use up to 64 channels The DIFF input configuration uses up to 32 channels Input modes are programmed on a per channel basis for multimode scanning For example you can configure the circuitry to scan
68. I MIO 64E 1 You can configure each analog output channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to V ref at the analog output A bipolar configuration has a range of V ref to V ref at the analog output V ref is the voltage reference used by the DACs in the analog output circuitry and can be either the 10 V onboard reference or an externally supplied reference between 10 and 10 V You do not need to configure both channels for the same range Chapter 3 Hardware Overview National Instruments Corporation 3 11 VXI MIO Series User Manual VXI MIO 64XE 10 You can configure each analog output channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to 10 V at the analog output A bipolar configuration has a range of 10 to 10 V at the analog output You do not need to configure both channels for the same range Analog Output Reglitch Selection VXI MIO 64E 1 In normal operation a DAC output will glitch whenever it is updated with a new value The glitch energy differs from code to code and appears as distortion in the frequency spectrum Each analog output of this module contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at the major code transitions This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum Notice th
69. I MIO 64XE 10 Logical Address Selection 2 5 Figure 2 4 SIMM Size Configuration 2 6 Figure 2 5 Load User Factory Configuration 2 8 Figure 2 6 Protect Change Factory Configuration 2 8 Figure 3 1 VXI MIO Series Block Diagram 3 2 Figure 3 2 Dither 3 8 Figure 3 3 Analog Trigger Block Diagram 3 12 Figure 3 4 Below Low Level Analog Triggering Mode 3 12 Figure 3 5 Above High Level Analog Triggering Mode 3 13 Figure 3 6 Inside Region Analog Triggering Mode 3 13 Figure 3 7 High Hysteresis Analog Triggering Mode 3 13 Figure 3 8 Low Hysteresis Analog Triggering Mode 3 14 Figure 3 9 CONVERT Signal Routing 3 15 Figure 3 10 VXIbus Trigger Utilization
70. IO Series module DIO lt 0 7 gt DGND Input or Output Digital I O signals DIO6 and 7 can control the up down signal of general purpose counters 0 and 1 respectively 5 V DGND Output 5 VDC Source These pins are fused for up to 1 A of 5 V supply The circuit breaker is self resetting Chapter 4 Signal Connections VXI MIO Series User Manual 4 4 National Instruments Corporation SCANCLK DGND Output Scan Clock This pin pulses once for each A D conversion in the scanning modes when enabled The low to high edge indicates when the input signal can be removed from the input or switched to another signal EXTSTROBE DGND Output External Strobe This output can be toggled under software control to latch signals or trigger events on external devices PFI0 TRIG1 DGND Input Output PFI0 Trigger 1 As an input this is either one of the PFIs or the source for the hardware analog trigger PFI signals are explained in the Timing Connections section later in this chapter The hardware analog trigger is explained in the Analog Trigger section in Chapter 2 As an output this is the TRIG1 signal In posttrigger data acquisition sequences a low to high transition indicates the initiation of the acquisition sequence In pretrigger applications a low to high transition indicates the initiation of the pretrigger conversions PFI1 TRIG2 DGND Input Output PFI1 Trigger 2 As an input this is
71. It includes all non linearity and quantization errors It does not include offset and gain errors of the circuitry feeding the ADC RESMAN The name of the National Instruments Resource Manager in NI VXI bus interface software See Resource Manager resolution The smallest signal increment that can be detected by a measurement system Resolution can be expressed in bits in proportions or in percent of full scale For example a system has 12 bit resolution one part in 4 096 resolution and 0 0244 percent of full scale Resource Manager A message based Commander located at logical address 0 which provides configuration management services such as address map configuration Commander and Servant mappings and self test and diagnostics management responses Signals or interrupts generated by a device to notify another device of an asynchronous event Responses contain the information in the Response register of a sender Glossary National Instruments Corporation G 13 VXI MIO Series User Manual rms root mean square RSE referenced single ended mode All measurements are made with respect to a common reference measurement system or a ground Also called a grounded measurement system RTD resistive temperature detector A metallic probe that measures temperature based upon its coefficient of resistivity RTSI Bus Real Time System Integration Bus The National Instruments timing bus that connects DAQ boa
72. RSE Configuration To measure a grounded signal source with a single ended configuration you must configure your VXI MIO Series module in the NRSE input configuration The signal is then connected to the module s PGIA positive input and the signal local ground reference is connected to the PGIA negative input The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference between the VXI MIO Series ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the PGIA and this difference is rejected by the amplifier If the input circuitry of the VXI MIO module were referenced to ground in this situation as in the RSE input configuration this difference in ground potentials would appear as an error in the measured voltage Figure 4 7 shows how to connect a grounded signal source to a channel on the VXI MIO Series module configured for NRSE mode Vs Vm Measured Voltage Floating Signal Source ACH lt 0 15 gt AIGND Instrumentation Amplifier I O Connector AISENSE Selected Channel in RSE Configuration PGIA Other Input Multiplexers Chapter 4 Signal Connections VXI MIO Series User Manual 4 20 National Instruments Corporation Figure 4 7 Single Ended Input Connections for Ground Referenced Signal Common Mode Signal Rejection Considerations Figures 4 6 and 4 7 show connections f
73. TARTSCAN CONVERT Scan Counter t w t w 400 to 500 ns t d 50 to 100 ns td CONVERT SCANCLK Chapter 4 Signal Connections National Instruments Corporation 4 27 VXI MIO Series User Manual signal level A 10 and 1 2 s clock is available for generating a sequence of eight pulses in the hardware strobe mode Figure 4 14 shows the timing for the hardware strobe mode EXTSTROBE signal Figure 4 14 EXTSTROBE Signal Timing TRIG1 Signal Any PFI pin can externally input the TRIG1 signal which is available as an output on the PFI0 TRIG1 pin Refer to Figures 4 11 and 4 12 for the relationship of TRIG1 to the data acquisition sequence As an input the TRIG1 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG1 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG1 signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions The VXI MIO 64E 1 and VXI MIO 64XE 10 support analog triggering on the PFI0 TRIG1 pin See Chapter 3 for more information on analog triggering As an output the TRIG1 signal reflects the action that initiates a data acquisition sequence This is true even if the acquisition is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This signal is set to input High Z at startup Figur
74. TE DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu Chapter 4 Signal Connections National Instruments Corporation 4 7 VXI MIO Series User Manual GPCTR1_OUT DO 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI5 UPDATE DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI6 WFTRIG DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI7 STARTSCAN DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI8 GPCTR0_SOURCE DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu PFI9 GPCTR0_GATE DIO 5 5 V 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu GPCTR0_OUT DO 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu FREQ_OUT DO 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Output ADIO Analog Digital Input Output 1 DIO lt 6 7 gt are also pulled down with a 50 k resistor 2 Also pulled down with a 10 k resistor Note The tolerance on the 50 k pullup and pulldown resistors is very large Actual value may range between 17 and 100 k Table 4 1 VXI MIO 64E 1 I O Signal Summary Continued Signal Name Drive Impedance Input Output Protection Volts Power On Off Source mA at V Sink mA at V Rise Time ns
75. TR1_GATE signal Figure 4 33 GPCTR1_GATE Signal Timing in Edge Detection Mode GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC module general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This signal is set to input High Z at startup Figure 4 34 shows the timing requirements for the GPCTR1_OUT signal Rising edge polarity Falling edge polarity tw tw 10 ns minimum Chapter 4 Signal Connections National Instruments Corporation 4 43 VXI MIO Series User Manual Figure 4 34 GPCTR1_OUT Signal Timing GPCTR1_UP_DOWN Signal This signal can be externally input on the DIO7 pin and is not available as an output on the I O connector General purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high This input can be disabled so that software can control the up down functionality and leave the DIO7 pin free for general use Figure 4 35 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of your VXI MIO Series module Figure 4 35 GPCTR Timing Summary GPCTR1_SOURCE GPCTR1_OUT GPCTR1_OUT Toggle output on TC Pulse on TC TC SOURCE V IH VIL V IH V IL t sc t sp t
76. ___ Base I O Address of VXI MIO Series Module ________________________________________ Programming Choice NI DAQ LabVIEW LabWindows CVI or other ___________________ Software Version ______________________________________________________________ Other Products Computer Model ______________________________________________________________ Microprocessor _______________________________________________________________ Clock Frequency ______________________________________________________________ Type of Video Board Installed ___________________________________________________ Operating System DOS or Windows _____________________________________________ Operating System Version_______________________________________________________ Operating System Mode ________________________________________________________ Programming Language ________________________________________________________ Programming Language Version__________________________________________________ Other Boards in System_________________________________________________________ Base I O Address of Other Boards ________________________________________________ DMA Channels of Other Boards __________________________________________________ Interrupt Level of Other Boards __________________________________________________ Click here to comment on this document via the National Instruments website at http www natinst com documentation daq Documentation
77. ___ _______________________________________________________________________________ The following steps reproduce the problem ___________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ Click here to comment on this document via the National Instruments website at http www natinst com documentation daq VXI MIO Series Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products VXI MIO Series Module ________________________________________________________ VXI MIO Series Module Serial Number ____________________________________________ Interrupt Level of VXI MIO Series Module __________________________________________ DMA Channels of VXI MIO Series Module ______________________________________
78. _____________________________________________ _______________________________________________________________________________ Thank you for your help Name _________________________________________________________________________ Title __________________________________________________________________________ Company_______________________________________________________________________ Address _______________________________________________________________________ _______________________________________________________________________________ Phone _____________________________________________________________________ Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway 512 794 5678 Austin TX 78730 5039 Click here to comment on this document via the National Instruments website at http www natinst com documentation daq National Instruments Corporation G 1 VXI MIO Series User Manual Symbols degree negative of or minus ohm per percent plus or minus positive of or plus square root of 5V 5 VDC source signal Prefix Meaning Value p pico 10 12 n nano 10 9 micro 10 6 m milli 10 3 k kilo 10 3 M mega 10 6 G giga 10 9 Glossar
79. a group whose task is active LabVIEW clears the task and returns a warning LabVIEW does not restart the task after you reconfigure the group H h hour hardware The physical components of a computer system such as the circuit boards plug in boards chassis enclosures peripherals cables and so on hardware triggering A form of triggering where you set the start time of an acquisition and gather data at a known position in time relative to a trigger signal hex hexadecimal Hz hertz A unit of frequency equal to one cycle per second I IC integrated circuit in inches INL Integral Nonlinearity A measure in LSB of the worst case deviation from the ideal A D or D A transfer characteristic of the analog I O circuitry input range The difference between the maximum and minimum voltages an analog input channel can measure at a gain of 1 The input range is a scalar value not a pair of numbers By itself the input range does not uniquely determine the upper and lower voltage limits An input range of 10 V could mean an upper limit of 10 V and a lower of 0 V or an upper limit of 5 V and a lower limit of 5 V The combination of input range polarity and gain determines the input limits of an analog input channel For some boards jumpers Glossary National Instruments Corporation G 9 VXI MIO Series User Manual set the input range and polarity while you can program them for other boards Most boa
80. a logic value of 1 See Figures 2 1 and 2 2 for the VXI MIO Series parts locator diagrams Chapter 2 Con guration and Installation National Instruments Corporation 2 3 VXI MIO Series User Manual Figure 2 1 VXI MIO 64E 1 Parts Locator Diagram 1 DRAM 2 Product Name 3 Assembly Number 4 P3 5 Serial Number 6 S1 7 S2 8 S3 9 Logical Address Switch 10 P1 11 P2 1 1 3 4 5 6 7 8 9 10 11 2 Chapter 2 Con guration and Installation VXI MIO Series User Manual 2 4 National Instruments Corporation Figure 2 2 VXI MIO 64XE 10 Block Diagram Figure 2 3 shows the VXI MIO 64XE 10 switch settings for logical address 2 and 192 1 DRAM 2 Product Name 3 Assembly Number 4 P3 5 S1 6 S2 7 S3 8 Logical Address Switch U73 9 Serial Number 10 P1 11 P2 1 1 3 4 5 6 7 8 10 9 11 2 Chapter 2 Con guration and Installation National Instruments Corporation 2 5 VXI MIO Series User Manual Figure 2 3 VXI MIO 64XE 10 Logical Address Selection SIMM Size Each VXI MIO module can accommodate up to two 1 35 in DRAM SIMMs Table 2 1 lists the SIMMS you can use You can use 32 bit or 36 bit SIMMS since DRAM parity is not required Because the VXI MIO module supports only one organization at a time all SIMMs installed must be of the same type Use bank 0 first when installing the SIMMs so that you can install up
81. al 4 30 to 4 31 TRIG1 signal 4 27 to 4 28 TRIG2 signal 4 28 to 4 29 DGND signal description table 4 3 digital I O connections 4 22 power connections 4 23 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 DIFF differential input mode definition table 3 3 description 4 14 ground referenced signal sources 4 15 illustration 4 15 nonreferenced or floating signal sources 4 16 to 4 17 illustration 4 16 recommended configuration figure 4 13 single ended connections 4 18 floating signal sources RSE 4 19 grounded signal sources NRSE 4 19 to 4 20 when to use 4 14 digital I O common questions about C 4 to C 6 operation 3 14 signal connections 4 22 to 4 23 specifications VXI MIO 64E 1 A 7 VXI MIO 64XE 10 A 14 digital trigger specifications VXI MIO 64E 1 A 8 VXI MIO 64XE 10 A 16 DIO lt 0 7 gt signal description table 4 3 digital I O connections 4 22 to 4 23 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 dither enabling 3 7 to 3 8 signal acquisition effects figure 3 8 documentation conventions used in manual xii National Instruments documentation xiii organization of manual xi xii related documentation xiv DRAM configuration table 2 6 to 2 7 dynamic characteristics analog input VXI MIO 64E 1 A 4 VXI MIO 64XE 10 A 12 analog output VXI MIO 64E 1 A 6 VXI MIO 64XE 10 A 13 E EEPROM loading USER FACTORY configuration 2 7 to 2 8 pro
82. annel 1 the input circuitry has to settle to within 0 0003 3 ppm or 1 80 LSB of the 4 V step It may take as long as 100 s for the circuitry to settle to this accuracy For a 16 bit module to settle within 0 0015 15 ppm or 1 LSB of the 100 mV full scale range on channel 1 the input circuitry has to settle within 0 00004 0 4 ppm or 1 400 LSB of the 4 V step It may take as long as 200 s for the circuitry to settle to this accuracy In general this extra settling time is not needed when the PGIA is switching to a lower gain Settling times can also increase when scanning high impedance signals due to a phenomenon called charge injection where the analog input multiplexer injects a small amount of charge into each signal source when that source is selected If the impedance of the source is not low enough the effect of the charge a voltage error will not have decayed by the time the ADC samples the signal For this reason you should keep source impedances under 1 k to perform high speed scanning Multichannel scanning is not recommended unless sampling rates are low enough or it is necessary to sample several signals as near to simultaneously as possible Single channel scanning yields more accurate settling times The data is much more accurate and channel to channel independent if you acquire data from each channel independently for example 100 points from channel 0 then 100 points from
83. anual I 2 National Instruments Corporation transfer characteristics A 5 to A 6 voltage output A 6 VXI MIO 64XE 10 dynamic characteristics A 13 output characteristics A 13 stability A 14 transfer characteristics A 13 voltage output A 13 analog trigger 3 11 to 3 14 above high level analog triggering mode figure 3 13 below low level analog triggering mode figure 3 12 block diagram 3 12 high hysteresis analog triggering mode figure 3 13 inside region analog triggering mode figure 3 13 low hysteresis analog triggering mode figure 3 14 specifications VXI MIO 64E 1 A 8 VXI MIO 64XE 10 A 15 to A 16 AOGND signal analog output connections 4 20 to 4 21 description table 4 3 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 B bipolar input mixing with unipolar channels note 3 5 bipolar output 3 10 to 3 11 block diagrams VXI MIO series 3 2 VXI MIO 64E 1 parts locator diagram 2 3 VXI MIO 64XE 10 parts locator diagram 2 4 board configuration See configuration bulletin board support D 1 C cables See also I O connectors field wiring considerations 4 45 optional cable connectors 68 pin extended analog input connector pin assignments figure B 3 68 pin MIO connector pin assignments figure B 2 optional equipment 1 6 calibration 5 1 to 5 3 adjusting for gain error 5 3 external calibration 5 2 to 5 3 loading calibration constants 5 1 to 5
84. are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment National Instruments Corporation v VXI MIO Series User Manual About This Manual Organization of This Manual xi Conventions Used in This Manual xii
85. at this reglitch circuit does not eliminate the glitches it only makes them more uniform in size Reglitching is normally disabled at startup and can be independently enabled for each channel through software VXI MIO 64XE 10 This module does not require reglitch selection Analog Trigger In addition to supporting internal software triggering and external digital triggering to initiate a data acquisition sequence the VXI MIO 64E 1 and VXI MIO 64XE 10 also support analog triggering You can configure the analog trigger circuitry to accept either a direct analog input from the PFI0 TRIG1 pin on the I O connector or a postgain signal from the output of the PGIA as shown in Figure 3 3 The trigger level range for the direct analog channel is 10 V in 78 mV steps for the VXI MIO 64E 1 and 10 V in 4 9 mV steps for theVXI MIO 64XE 10 The range for the post PGIA trigger selection is simply the full scale range of the selected channel and the resolution is that range divided by 256 for the VXI MIO 64E 1 and divided by 4 096 for the VXI MIO 64XE 10 Chapter 3 Hardware Overview VXI MIO Series User Manual 3 12 National Instruments Corporation Note The PFI0 TRIG1 pin is a high impedance input Therefore it is susceptible to cross talk from adjacent pins which can result in false triggering when the pin is left unconnected To avoid false triggering make sure this pin is connected to a low
86. ates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the VXI MIO Series modules Figure 4 35 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal FREQ_OUT Signal This signal is available only as an output on the FREQ_OUT pin The FREQ_OUT signal is the output of the VXI MIO Series module frequency generator The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This signal is set to input High Z at startup Chapter 4 Signal Connections National Instruments Corporation 4 45 VXI MIO Series User Manual Field Wiring Considerations Environmental noise can seriously affect the accuracy of measurements made with your VXI MIO Series module if you do not take proper care when running signal wires between signal sources and the module The following recommendations apply mainly to analog input signal routing to the module
87. bly typically a printed circuit board with 96 pin connectors and signal paths that bus the connector pins VXIbus systems will have two sets of bused connectors called the J1 and J2 backplanes or have three sets of bused connectors called the J1 J2 and J3 backplane base address A memory address that serves as the starting address for programmable registers All other addresses are located by adding to the base address BCD binary coded decimal BIOS basic input output system or built in operating system bipolar A signal range that includes both positive and negative values for example 5 to 5 V bit One binary digit either 0 or 1 bus The group of conductors that interconnect individual circuitry in a computer Typically a bus is the expansion vehicle to which I O or other devices are connected byte Eight related bits of data an eight bit binary number Also used to denote the amount of memory required to store one byte of data C C Celsius CalDAC calibration DAC channel Pin or wire lead to which you apply or from which you read the analog or digital signal Analog signals can be single ended or differential For digital signals you group channels to form ports Ports usually consist of either four or eight digital channels clock Hardware component that controls timing for reading from or writing to groups CMOS complementary metal oxide semiconductor CMRR common mode rejection ratio
88. can also program the module to drive its internal timebase over the VXIbus trigger line to another module that is programmed to receive this timebase signal This clock source whether local or from the VXIbus trigger line is used directly by the module as the primary frequency source The default configuration at startup is to use the internal timebase without driving the VXIbus trigger line timebase signal This timebase is software selectable Chapter 3 Hardware Overview National Instruments Corporation 3 17 VXI MIO Series User Manual VXIbus Triggers The VXI MIO Series modules can use up to seven of the 10 VXIbus trigger lines to coordinate sampling and or triggering across multiple modules When using NI DAQ software the VXIbus trigger lines are functionally equivalent to RTSI bus trigger lines Figure 3 10 VXIbus Trigger Utilization Refer to the Timing Connections section of Chapter 4 for a description of the signals shown in Figure 3 10 VXIbus Trigger Lines Crossbar Switch TTL Triggers 5 ECL Triggers 2 DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC 20 MHz National Instruments Corporation 4 1 VXI MIO Series User Manual Signal Connections Chapter 4 This chapter describes how to make input and output signal connections to your VXI MIO Series mod
89. chnical support questions to the appropriate applications engineering team through e mail at the Internet addresses listed below Remember to include your name address and phone number so we can contact you with solutions and suggestions GPIB gpib support natinst com LabVIEW lv support natinst com DAQ daq support natinst com HiQ hiq support natinst com VXI vxi support natinst com VISA visa support natinst com LabWindows lw support natinst com Lookout lookout support natinst com Fax and Telephone Support National Instruments has branch offices all over the world Use the list below to find the technical support number for your country If there is no National Instruments office in your country contact the source from which you purchased your software to obtain support Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Canada Ontario 905 785 0085 905 785 0086 Canada Quebec 514 694 8521 514 694 4399 Denmark 45 76 26 00 45 76 26 02 Finland 90 527 2321 90 502 2930 France 01 48 14 24 24 01 48 14 24 14 Germany 089 741 31 30 089 714 60 35 Hong Kong 2645 3186 2686 8505 Israel 03 5734815 03 5734816 Italy 02 413091 02 41309215 Japan 03 5472 2970 03 5472 2977 Korea 02 596 7456 02 596 7455 Mexico 95 800 010 0793 5 520 3282 Netherlands 0348 433466 0348 430673 Norway 32 84
90. ck is being externally generated by another PFI This signal is set to input High Z at startup Figure 4 32 shows the timing requirements for the GPCTR1_SOURCE signal Figure 4 32 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source GPCTR1_GATE Signal Any PFI pin can externally input the GPCTR1_GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input the GPCTR1_GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and t p t w t w t p t w 50 ns minimum 23 ns minimum Chapter 4 Signal Connections VXI MIO Series User Manual 4 42 National Instruments Corporation configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform such actions as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTR1_GATE signal monitors the actual gate signal connected to general purpose counter 1 This is true even if the gate is being externally generated by another PFI This signal is set to input High Z at startup Figure 4 33 shows the timing requirements for the GPC
91. ctor pin assignments figure B 2 pin assignments figure 4 2 signal descriptions table 4 3 to 4 5 Index VXI MIO Series User Manual I 6 National Instruments Corporation L LabVIEW and LabWindows CVI software 1 3 M manual See documentation memory See SIMM size configuration multichannel scanning 3 8 to 3 9 N NI DAQ driver software 1 3 to 1 4 noise avoiding 4 45 NRSE nonreferenced single ended input description table 3 3 differential connections 4 16 to 4 17 recommended configuration figure 4 13 single ended connections NRSE configuration 4 19 to 4 20 O onboard EEPROM See EEPROM operation of VXI MIO series boards See hardware overview output characteristics VXI MIO 64E 1 A 5 VXI MIO 64XE 10 A 13 P parts locator diagrams 2 3 2 4 PFI0 TRIG1 signal description table 4 4 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 PFI1 TRIG2 signal description table 4 4 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 PFI2 CONVERT signal description table 4 4 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 PFI3 GPCTR1_SOURCE signal description table 4 4 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 PFI4 GPCTR1_GATE signal description table 4 4 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 9 PFI5 UPDATE signal description table 4 5 VXI MIO 64E 1 table 4 7 VXI MIO 64XE 10
92. curate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it E XCEPT AS SPECIFIED HEREIN N ATIONAL I NSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE C USTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF N ATIONAL I NSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER N ATIONAL I NSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES
93. d to channel 0 and a 1 mV 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 LSBs LSBs LSBs LSBs 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 a Dither disabled no averaging b Dither disabled average of 50 acquisitions c Dither enabled no averaging 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 d Dither enabled average of 50 acquisitions LSBs LSBs LSBs LSBs 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 100 200 300 400 0 500 4 0 2 0 0 0 2 0 4 0 6 0 6 0 Chapter 3 Hardware Overview National Instruments Corporation 3 9 VXI MIO Series User Manual signal is connected to channel 1 and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1 When the multiplexer switches to channel 1 and the PGIA switches to a gain of 100 the new full scale range is 100 mV if the ADC is in unipolar mode The approximately 4 V step from 4 V to 1 mV is 4 000 of the new full scale range For a 12 bit module to settle within 0 012 120 ppm or 1 2 LSB of the 100 mV full scale range on ch
94. dB Gain 20 105 dB Gain 50 105 dB Gain 100 105 dB Appendix A Speci cations for VXI MIO 64XE 10 VXI MIO Series User Manual A 12 National Instruments Corporation Dynamic Characteristics Bandwidth All gains 255 kHz Settling time for full scale step all gains and ranges To 0 5 LSB 50 s typ To 1 LSB 25 s typ To 6 LSB 10 s typ System noise including quantization noise Gain 1 2 5 10 0 6 LSB rms bipolar 0 8 LSB rms unipolar Gain 20 0 7 LSB rms bipolar 1 1 LSB rms unipolar Gain 50 1 1 LSB rms bipolar 2 0 LSB rms unipolar Gain 100 2 0 LSB rms bipolar 3 8 LSB rms unipolar Dynamic range 91 7 dB full scale input with gain 1 to 10 Crosstalk 70 dB max DC to 100 kHz Stability Recommended warm up time 15 min Offset temperature coefficient Pregain 5 V C Postgain 120 V C Gain temperature coefficient 7 ppm C Onboard calibration reference Level
95. e data acquisition sequence As an input the STARTSCAN signal is configured in the edge detection mode You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter starts if you select internally triggered CONVERT As an output the STARTSCAN signal reflects the actual start pulse that initiates a scan This is true even if the starts are being externally triggered by another PFI You have two output options The first is an active high pulse with a pulse width of 50 to 100 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last conversion in the scan which indicates a scan in progress STARTSCAN will be deasserted t off after the last conversion in the scan is initiated This signal is set to input High Z at startup Figures 4 19 and 4 20 show the input and output timing requirements for the STARTSCAN signal Figure 4 19 STARTSCAN Input Signal Timing Rising edge polarity Falling edge polarity tw tw 10 ns minimum Chapter 4 Signal Connections National Instruments Corporation 4 31 VXI MIO Series User Manual Figure 4 20 STARTSCAN Output Signal Timing The CONVERT pulses are masked off until the module generates the STARTSCAN signal If you are using internally generated c
96. els indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the module is unpowered Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM NI DAQ the VXI plug amp play instrument drivers or your application software determine when this is necessary and do it automatically If you are not using NI DAQ the VXI plug amp play instrument drivers or your application software you must load these values yourself In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area This means that you can load Chapter 5 Calibration VXI MIO Series User Manual 5 2 National Instruments Corporation the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed This method of calibration is not very accurate because it does not take into account the fact that the module measurement and output voltage errors can vary with time and temperature It is better to self calibrate when the module is installed in the environment in which it will be used Self Calibration Your VXI MIO Series module can measure
97. er TC and GPCTR0_OUT Many of these timing signals are also available as outputs on the VXIbus trigger as indicated in the VXIbus Triggers section later in this chapter and on the PFI pins as indicated in Chapter 4 Signal Connections Programmable Function Inputs The 10 PFIs are connected to the signal routing multiplexer for each timing signal and software can select one of the PFIs as the external source for a given timing signal It is important to note that any of the PFIs can be used as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously This flexible routing scheme reduces the need to change physical connections to the I O connector for different applications You can also individually enable each of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector your software can turn on the output driver for the PFI5 UPDATE pin Module and Timebase Many functions that the VXI MIO Series modules perform require a frequency timebase to generate the necessary timing signals for controlling A D conversions DAC updates or general purpose signals at the I O connector A VXI MIO Series module can use either its internal 20 MHz timebase which is phase locked to CLK10 on the VXIbus or a timebase received over a VXIbus trigger line In addition if you configure the module to use the internal timebase you
98. eries Board Chapter 4 Signal Connections National Instruments Corporation 4 25 VXI MIO Series User Manual driver for the PFI2 CONVERT pin Be careful not to drive a PFI signal externally when it is configured as an output As an input you can individually configure each PFI for edge or level detection and also for polarity selection You can use the polarity selection for any of the 13 timing signals but the edge or level detection will depend upon the particular timing signal being controlled The detection requirements for each timing signal are listed in the section that discusses that individual signal In edge detection mode a minimum pulse width of 10 ns is required This applies for both rising edge and falling edge polarity settings There is no maximum pulse width requirement in edge detection mode In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but limits may be imposed by the particular timing signal being controlled These requirements are listed later in this chapter Data Acquisition Timing Connections The data acquisition timing signals are SCANCLK EXTSTROBE TRIG1 TRIG2 STARTSCAN CONVERT AIGATE and SISOURCE Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered data acquisition sequence is shown in Figure 4 11 Pretriggered data acquisition allows you
99. error information National Instruments Corporation A 1 VXI MIO Series User Manual Specifications Appendix A This appendix lists the specifications of each module in the VXI MIO Series These specifications are typical at 25 C unless otherwise noted VXI MIO 64E 1 Analog Input Input Characteristics Number of channels 64 single ended or 32 differential software selectable Type of ADC Successive approximation Resolution 12 bits 1 in 4 096 Max sampling rate 1 25 MS s guaranteed Appendix A Speci cations for VXI MIO 64E 1 VXI MIO Series User Manual A 2 National Instruments Corporation Input coupling DC Max working voltage signal common mode Each input should remain within 11 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ACH lt 0 63 gt AISENSE AISENSE2 FIFO buffer size 8 192 S Data transfers DMA interrupts programmed I O Configuration memory size 512 words Input signal ranges Module Gain Software Selectable Module Range Software Selectable Bipolar Unipolar
100. errupt latencies it is possible that the counter may have generated some spurious requests which the DMA controller may not satisfy because it has already transferred the required number of points 16 What are the PFIs and how do I configure these lines PFIs are Programmable Function Inputs These lines serve as connections to virtually all internal timing signals If you are using the NI DAQ language interface or LabWindows CVI use the Select_Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use the AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Appendix C Common Questions National Instruments Corporation C 6 VXI MIO Series User Manual Gate Config CTR Mode Config and CTR Pulse Config advanced level VIs to indicate which function the connected signal will serve Use the Route Signal VI to enable the PFI lines to output internal signals Warning If you enable a PFI line for output do not connect any external signal source to it if you do you can damage the module and the connected equipment 17 What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardwa
101. es 4 15 and 4 16 show the input and output timing requirements for the TRIG1 signal t w t w VOH VOL t w 600 ns or 5 s Chapter 4 Signal Connections VXI MIO Series User Manual 4 28 National Instruments Corporation Figure 4 15 TRIG1 Input Signal Timing Figure 4 16 TRIG1 Output Signal Timing The module also uses the TRIG1 signal to initiate pretriggered data acquisition operations In most pretriggered applications the acquisition is started by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered data acquisition operation TRIG2 Signal Any PFI pin can externally input the TRIG2 signal which is available as an output on the PFI1 TRIG2 pin Refer to Figure 4 12 for the relationship of TRIG2 to the data acquisition sequence As an input the TRIG2 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG2 signal initiates the posttriggered phase of a pretriggered acquisition sequence In pretriggered mode the TRIG1 signal initiates the data acquisition The scan counter indicates the minimum number of Rising edge polarity Falling edge polarity tw tw 10 ns minimum t w t w 50 100 ns Chapter 4 Signal Connections National Instruments Corporati
102. fferential Connections for Nonreferenced or Floating Signal Sources section later in this chapter If you have a grounded source you should not reference the signal to AIGND You can avoid this reference by using DIFF or NRSE input configurations Types of Signal Sources When configuring the input channels and making signal connections you must first determine whether the signal sources are floating or ground referenced The following sections describe these two types of signals Floating Signal Sources A floating signal source is one that is not connected in any way to earth ground but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolated outputs and isolation amplifiers Tie the ground reference of a floating signal to your VXI MIO Series module analog input ground to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is one that is connected in some way to the same ground reference as the VXI MIO Series module An example of this type of signal is a nonisolated output of a signal generator which is powered from the same power strip as the VXIbus system The difference in ground potential between two instruments connected to the same
103. fore removing the module from the package Remove the module from the package and inspect the module for loose components or any other sign of damage Notify National Instruments if the module appears damaged in any way Do not install a damaged module into your VXIbus chassis Never touch the exposed pins of connectors National Instruments Corporation 2 1 VXI MIO Series User Manual Configuration and Installation Chapter 2 This chapter explains how to configure and install your VXI MIO Series module Module Configuration The VXI MIO Series modules are software configurable except for the VXIbus logical address You must perform two types of configuration on the VXI MIO Series modules bus related configuration and data acquisition related configuration Bus related configuration includes setting the VXIbus logical address VXIbus address space A24 versus A32 VXIbus interrupt levels and amount of VXIbus address space required Data acquisition related configuration explained in Chapter 3 Hardware Overview includes such settings as analog input polarity and range analog output reference source and other settings VXIbus Logical Address Each module in a VXIbus system is assigned a unique number between 0 and 254 This 8 bit number called the logical address defines the base address for the VXIbus configuration registers located on the module With unique
104. g that connectors fit properly and that adjacent modules do not contact each other It also provides cooling airflow and ensures that modules do not disengage from the backplane due to vibration or shock MB megabytes of memory memory device A memory storage device that has configuration registers MIO multifunction I O MITE A National Instruments custom ASIC A sophisticated dual channel DMA controller that incorporates the Synchronous MXI and VME64 protocols to achieve high performance block transfer rates module Typically a board assembly and its associated mechanical parts front panel optional shields and so on A module contains everything required to occupy one or more slots in a mainframe MSB most significant bit multitasking A property of an operating system in which several processes can be run simultaneously mux multiplexer A switching device with multiple inputs that sequentially connects each of its inputs to its output typically at high speeds in order to measure several signals with a single analog input channel N NC Normally closed or not connected NI DAQ National Instruments driver software for DAQ hardware node Execution elements of a block diagram consisting of functions structures and subVIs noise An undesirable electrical signal Noise comes from external sources such as the AC power line motors generators transformers fluorescent lights soldering irons CRT displays
105. gnificantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 k to 1 M In this case you can tie the negative input directly to AIGND If the source has high output impedance you should balance the signal path as previously described using the same value resistor on both the positive and negative inputs you should be aware that there is some gain error from loading down the source Refer to Application Note 025 Field Wiring and Noise Considerations for Analog Signals for more information Chapter 4 Signal Connections VXI MIO Series User Manual 4 18 National Instruments Corporation Single Ended Connection Considerations A single ended connection is one in which the VXI MIO Series module analog input signal is referenced to a ground that can be shared with other input signals The input signal is tied to the PGIA positive input and the ground is tied to the PGIA negative input When you configure every channel for single ended input up to 64 analog input channels are available You can use single ended input connections for any channel signal that meets all of the following conditions The input signal is high level greater than 1 V The leads connecting the signal to the VXI MIO Series module are less than 10 ft 3 m The input signal can share a common reference point with other signals DIFF input connections
106. h 3 dB 1 5 MHz internal 7 MHz external External input PFI0 TRIG1 Impedance 10 k Coupling DC Protection 0 5 to 5 5 V when configured as a digital signal 35 V when configured as an analog trigger signal or disabled 35 V powered off Digital Trigger Compatibility TTL Response Rising or falling edge Pulse width 10 ns min VXIbus Trigger Trigger lines Supports 5 TTL and 2 ECL trigger lines Appendix A Speci cations for VXI MIO 64E 1 National Instruments Corporation A 9 VXI MIO Series User Manual Power Requirement 5 VDC 1 80 A typ 2 16 A max Not including current used by accessories 5 2 VDC 0 15 A typ 0 18 A max 2 VDC 0 04 A typ 0 06 A max 24 VDC 0 09 A typ 0 10 A max 24 VDC 0 09 A typ 0 10 A max Power available at I O connector 4 65 VDC to 5 25 VDC at 1 A Physical Dimensions VXI C size single slot I O connector 96 pin
107. h voltage IOH 13 mA 4 35 V 1 000 h Appendix A Speci cations for VXI MIO 64XE 10 National Instruments Corporation A 15 VXI MIO Series User Manual Timing I O Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers 24 bits Frequency scaler 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns edge detect mode Min gate pulse duration 10 ns edge detect mode Data transfers DMA interrupts programmed I O Triggers Analog Trigger Source ACH lt 0 63 gt PFI0 TRIG1 Level Fullscale internal 10 V external Slope Positive or negative software selectable Resolution 12 bits 1 in 4 096 Hysteresis Programmable Bandwidth 3 dB 255 kHz internal 4 MHz external Appendix A Speci cations for
108. h signal conditioning or accessory products NI DAQ has an extensive library of functions that you can call from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation timed D A conversion digital I O counter timer operations SCXI triggering calibration messaging and acquiring data to extended memory NI DAQ has both high level DAQ I O functions for maximum ease of use and low level DAQ I O functions for maximum flexibility and performance Examples of high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level function is writing directly to registers on the DAQ device NI DAQ does not sacrifice the performance of National Instruments Chapter 1 Introduction VXI MIO Series User Manual 1 4 National Instruments Corporation DAQ devices because it lets multiple devices operate at their peak performance NI DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers NI DAQ maintains a consistent software interface between its different versions so that you can change platforms with minimal modifications to your code VXI plug amp play Instrument Drivers National Instruments distributes VXI plug amp play
109. highValue Trigger lowValue Chapter 3 Hardware Overview National Instruments Corporation 3 15 VXI MIO Series User Manual Timing Signal Routing The DAQ STC provides a very flexible interface for connecting timing signals to other modules or external circuitry Your VXI MIO Series module uses the VXIbus trigger for interconnecting timing signals between modules and the Programmable Function Input PFI pins on the I O connector for connecting to external circuitry These connections are designed to enable the VXI MIO Series module to both control and be controlled by other modules and circuits There are a total of 13 timing signals internal to the DAQ STC that can be controlled by an external source These timing signals can also be controlled by signals generated internally to the DAQ STC and these selections are fully software configurable For example the signal routing multiplexer for controlling the CONVERT signal is shown in Figure 3 9 Figure 3 9 CONVERT Signal Routing VXI TTL Trigger lt 0 4 gt VXI ECL Trigger lt 0 1 gt PFI lt 0 9 gt CONVERT Sample Interval Counter TC GPCTR0_OUT Chapter 3 Hardware Overview VXI MIO Series User Manual 3 16 National Instruments Corporation This figure shows that CONVERT can be generated from a number of sources including the external signals VXI TTL Trig lt 0 4 gt VXI ECL Trig lt 0 1 gt and PFI lt 0 9 gt and the internal signals Sample Interval Count
110. impedance signal source less than 10 k source impedance if you plan to enable this input via software Figure 3 3 Analog Trigger Block Diagram There are five analog triggering modes available as shown in Figures 3 4 through 3 8 You can set lowValue and highValue independently in software In below low level analog triggering mode the trigger is generated when the signal value is less than lowValue HighValue is unused Figure 3 4 Below Low Level Analog Triggering Mode In above high level analog triggering mode the trigger is generated when the signal value is greater than highValue LowValue is unused Analog Input Channels PFI0 TRIG1 PGIA ADC DAQ STC Analog Trigger Circuit Mux lowValue Trigger Chapter 3 Hardware Overview National Instruments Corporation 3 13 VXI MIO Series User Manual Figure 3 5 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the lowValue and the highValue Figure 3 6 Inside Region Analog Triggering Mode In high hysteresis analog triggering mode the trigger is generated when the signal value is greater than highValue with the hysteresis specified by lowValue Figure 3 7 High Hysteresis Analog Triggering Mode highValue Trigger highValue Trigger lowValue highValue
111. ined in the Data Acquisition Timing Connections section later in this chapter The waveform generation signals are explained in the Waveform Generation Timing Chapter 4 Signal Connections VXI MIO Series User Manual 4 24 National Instruments Corporation Connections section later in this chapter The general purpose timing signals are explained in the General Purpose Timing Signal Connections section later in this chapter All digital timing connections are referenced to DGND This reference is demonstrated in Figure 4 10 which shows how to connect an external TRIG1 source and an external CONVERT source to two of the VXI MIO Series module PFI pins Figure 4 10 Timing I O Connections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externally control from the PFI pins The source for each of these signals is software selectable from any of the PFIs when you want external control This flexible routing scheme reduces the need to change the physical wiring to the module I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT signal as an output on the I O connector your software can turn on the output TRIG1 Source DGND PFI0 TRIG1 PFI2 CONVERT CONVERT Source I O Connector VXI MIO S
112. ing figure 2 5 VXIbus triggers 3 17 specifications VXI MIO 64E 1 A 8 VXI MIO 64XE 10 A 16 trigger line utilization figure 3 17 Index National Instruments Corporation I 11 VXI MIO Series User Manual VXI MIO series See also hardware overview common questions about C 1 to C 6 custom cabling 1 6 features 1 1 optional equipment 1 5 requirements for getting started 1 2 software programming choices ComponentWorks 1 2 LabVIEW and LabWindows CVI 1 3 NI DAQ driver software 1 3 to 1 4 VirtualBench 1 3 unpacking 1 6 VXI plug amp play instrument drivers 1 4 to 1 5 VXI plug amp play instrument drivers 1 4 to 1 5 W waveform generation timing connections 4 34 to 4 38 UISOURCE signal 4 37 to 4 38 UPDATE signal 4 36 to 4 37 WFTRIG signal 4 34 WFTRIG signal timing connections 4 35 input timing figure 4 35 output timing figure 4 35 wiring considerations 4 45
113. invoke the AI Clock Config VI with clock source code set to PFI pin high to low and clock source string set to 5 c Initiate analog input data acquisition which will start only when the analog output waveform generation starts If you are using NI DAQ call DAQ_Start with appropriate parameters If you are using LabVIEW invoke the AI Control VI with control code set to 0 start d Initiate analog output waveform generation If you are using NI DAQ call WFM_Group_Control with operation set to 1 start If you are using LabVIEW invoke the AO Control VI with control code set to 0 start Timing and Digital I O 12 What types of triggering can be hardware implemented on my VXI MIO Series module Digital triggering is supported by hardware on every VXI MIO Series module In addition the VXI MIO 64E 1 and VXI MIO 64XE 10 support analog triggering in hardware 13 What added functionality does the DAQ STC make possible in contrast to the Am9513 The DAQ STC incorporates much more than just 10 Am9513 style counters within one chip In fact the DAQ STC has the complexity of more than 24 chips The DAQ STC makes possible PFI lines Appendix C Common Questions National Instruments Corporation C 5 VXI MIO Series User Manual analog triggering selectable logic level and frequency shift keying The DAQ ST
114. ir answers relating to usage and special features of your VXI MIO Series module General Information 1 What is the DAQ STC The DAQ STC is the system timing control ASIC application specific integrated circuit designed by National Instruments and is the backbone of the VXI MIO Series modules The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into three groups Analog input two 24 bit two 16 bit counters Analog output three 24 bit one 16 bit counters General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 s With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New capabilities such as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate are possible 2 How fast is each VXI MIO Series module The last numeral in the name of an VXI MIO Series module specifies the fastest sample period in microseconds for that particular module For example the VXI MIO 64E 1 has a 1 s sample period which corresponds to a sampling rate of 1 25 MS s These sampling rates are aggregate one channel at 1 25 MS s or two channels at 500 kS s per channel illustrates the relationship Notice howeve
115. ith a known external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM so you should not have to perform an external calibration very often Externally calibrate your Chapter 5 Calibration National Instruments Corporation 5 3 VXI MIO Series User Manual module by calling the NI DAQ or VXI plug amp play instrument driver calibration function To externally calibrate your module be sure to use a very accurate external reference The reference should be several times more accurate than the module itself For example to calibrate a 12 bit module the external reference should be at least 0 005 50 ppm accurate To calibrate a 16 bit module the external reference should be at least 0 001 10 ppm accurate Other Considerations The CalDACs adjust the gain error of each analog output channel by adjusting the value of the reference voltage supplied to that channel This calibration mechanism is designed to work only with the internal 10 V reference Thus in general it is not possible to calibrate the analog output gain error when using an external reference In this case it is advisable to account for the nominal gain error of the analog output channel either in software or with external hardware See Appendix A Specifications for analog output gain
116. k to time the generation of the STARTSCAN signal You must configure the PFI pin you select as the source for the SISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source Figure 4 23 shows the timing requirements for the SISOURCE signal Figure 4 23 SISOURCE Signal Timing Waveform Generation Timing Connections The analog group defined for your VXI MIO Series module is controlled by WFTRIG UPDATE and UISOURCE WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin t p t w t w t p t w 50 ns minimum 23 ns minimum Chapter 4 Signal Connections National Instruments Corporation 4 35 VXI MIO Series User Manual As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UI counter is started if you select internally generated UPDATE As an output the WFTRIG signal
117. l or technical reference manual for specific instructions and warnings 1 Plug in your mainframe before installing your VXI module The power cord grounds the mainframe and protects it from electrical damage while you install the module Do not turn on the mainframe Warning To protect yourself and your mainframe from electrical hazards DO NOT turn the mainframe on until you are finished installing your VXI MIO Series module Load User Configuration Load Factory Configuration S2 S2 Protect Factory Configuration Change Factory Configuration S1 S1 Chapter 2 Con guration and Installation National Instruments Corporation 2 9 VXI MIO Series User Manual 2 Remove or open any doors or covers blocking access to the mainframe slots 3 If you are installing your VXI DAQ module into a D size mainframe first install an appropriate support for C size modules in D size mainframes 4 Insert the VXI DAQ module in the slot you have selected a Align the top and bottom of the module with the card edge guides inside the mainframe b Slowly push the VXI DAQ module straight into the slot until its plug connectors are resting on the backplane receptacle connectors c Using evenly distributed pressure slowly press the VXI DAQ module straight in until it seats in the expansion slot d Make sure the front panel of the VXI DAQ module is even with the front panel of the mainframe
118. ld read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software Your SCXI hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints Your VXI DAQ hardware user manuals These manuals have detailed information about the VXI DAQ hardware that plugs into or is connected to your system Use these manuals for hardware installation and configuration instructions specification information about your VXI DAQ hardware and application hints Software documentation You may have both application software and driver software documentation National Instruments application software includes ComponentWorks LabVIEW LabWindows CVI Measure and VirtualBench National Instruments driver software includes NI DAQ and VXI plug amp play instrument drivers After you set up your hardware system use either your application or driver software documentation to help you write your application If you have a large and complicated system it is worthwhile to look through the software documentation before you configure your hardware Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides They explai
119. le of floating signal sources are batteries transformers or thermocouples FREQ_OUT frequency output signal ft feet function A set of software instructions executed by a single line of code that may have input and or output parameters and returns a value when executed G gain The factor by which a signal is amplified sometimes expressed in decibels gain accuracy A measure of deviation of the gain of an amplifier from the ideal gain GND ground signal or bit GPCTR0_GATE general purpose counter 0 gate signal GPCTR1_GATE general purpose counter 1 gate signal GPCTR0_OUT general purpose counter 0 output signal GPCTR1_OUT general purpose counter 1 output signal GPCTR0_SOURCE general purpose counter 0 clock source signal Glossary VXI MIO Series User Manual G 8 National Instruments Corporation GPCTR1_SOURCE general purpose counter 1 clock source signal group A collection of digital ports combined to form a larger entity for digital input and or output Groups can contain analog input analog output digital input digital output or counter timer channels A group can contain only one type of channel however You use a task ID number to refer to a group after you create it You can define up to 16 groups at one time To erase a group you pass an empty channel array and the group number to the group configuration VI You do not need to erase a group to change its membership If you reconfigure
120. librate your VXI MIO 64XE 10 analog input circuitry for either a unipolar or bipolar polarity If you mix unipolar and bipolar channels in your scan list and you are using NI DAQ then NI DAQ will load the calibration constants appropriate to the polarity for which analog input channel 0 is configured The software programmable gain on this module increases its overall flexibility by matching the input signal ranges to those that the ADC can accommodate The VXI MIO 64XE 10 has gains of 1 2 5 10 20 50 and 100 These gains are suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 3 shows 5 to 5 V 0 5 1 0 2 0 5 0 10 0 20 0 50 0 100 0 10 to 10 V 5 to 5 V 2 5 to 2 5 V 1 to 1 V 500 to 500 mV 250 to 250 mV 100 to 100 mV 50 to 50 mV 4 88 mV 2 44 mV 1 22 mV 488 28 V 244 14 V 122 07 V 48 83 V 24 41 V 1 The value of 1 LSB of the 12 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 12 bit count Note See Appendix A Specifications for absolute maximum ratings Table 3 2 Actual Range and Measurement Precision Continued Range Configuration Gain Actual Input Range Precision 1 Chapter 3 Hardware Overview VXI MIO Series User Manual 3 6 National Instruments Corp
121. limits The upper and lower voltage or current outputs for an analog output channel The output limits determine the polarity and voltage reference settings for a board output settling time The amount of time required for the analog output voltage to reach its final value within specified limits P PC personal computer PFI Programmable Function Input PGIA Programmable Gain Instrumentation Amplifier Glossary VXI MIO Series User Manual G 12 National Instruments Corporation plug and play devices Devices that do not require dip switches or jumpers to configure resources on the devices also called switchless devices port 1 A communications connection on a computer or a remote controller 2 A digital port consisting of four or eight lines of digital input and or output ppm parts per million pretriggering The technique used on a DAQ board to keep a continuous buffer filled with data so that when the trigger conditions are met the sample includes the data leading up to the trigger condition Q quantization error The inherent uncertainty in digitizing an analog value due to the finite resolution of the conversion process R RAM random access memory referenced signal sources Signal sources with voltage signals that are referenced to a system ground such as the earth or a building ground Also called grounded signal sources relative accuracy A measure in LSB of the accuracy of an ADC
122. lling edge The selected edge of the CONVERT signal initiates an A D conversion As an output the CONVERT signal reflects the actual convert pulse that is connected to the ADC This is true even if the conversions are being externally generated by another PFI The output is an active low pulse with a pulse width of 50 to 100 ns This signal is set to input High Z at startup Figures 4 21 and 4 22 show the input and output timing requirements for the CONVERT signal Figure 4 21 CONVERT Input Signal Timing Rising edge polarity Falling edge polarity tw tw 10 ns minimum Chapter 4 Signal Connections National Instruments Corporation 4 33 VXI MIO Series User Manual Figure 4 22 CONVERT Output Signal Timing The ADC switches to hold mode within 60 ns of the selected edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next Separate the CONVERT pulses by at least one conversion period The sample interval counter on the VXI MIO Series module normally generates the CONVERT signal unless you select some external source The STARTSCAN signal starts the counter and the counter continues to count down and reload itself until the scan is finished It then reloads itself in readiness for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT signal are inhibited unless they occur within a data acquisition sequence
123. logical addresses each VXIbus module in the system is assigned 64 bytes of configuration space in the upper 16 KB of the A16 address space Logical address 0 is reserved for the Resource Manager in the VXIbus system Because the VXI MIO Series modules cannot act as a Resource Manager do not configure the VXI MIO Series modules with a logical address of 0 The factory default logical address for the VXI MIO 64E 1 is 3 and for the VXI MIO 64XE 10 is 2 Some VXIbus modules have dynamically configurable logical addresses These modules have an initial logical address of hex FF or decimal 255 which indicates that they can be dynamically configured Chapter 2 Con guration and Installation VXI MIO Series User Manual 2 2 National Instruments Corporation Your VXI MIO Series module does not support dynamic configuration of its logical address Ensure that no other statically configurable VXIbus modules have the same logical address as the VXI MIO Series module If they do change the logical address setting of either the VXI MIO Series module or the other module so that every module in the system has a different associated logical address To change the logical address of the VXI MIO Series modules modify the setting of the 8 bit DIP switch labeled LOGICAL ADDRESS SWITCH U3 for the VXI MIO 64E 1 and U73 for the VXI MIO 64XE 10 The down position of the DIP switch corresponds to a logic value of 0 and the up position corresponds to
124. more than one controller or processor dynamic configuration A method of automatically assigning logical addresses to VXIbus devices at system startup or other configuration times Each slot can contain one or more devices Different devices within a slot can share address decoding hardware dynamically configured A device that has its logical address assigned by the Resource device Manager A VXI device initially responds at Logical Address 255 when its MODID line is asserted The Resource Manager subsequently assigns it a new logical address which the device responds to until powered down dynamic range The ratio of the largest signal level a circuit can handle to the smallest signal level it can handle usually taken to be the noise level normally expressed in dB E ECL Emitter Coupled Logic EEPROM electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogrammed EISA Extended Industry Standard Architecture embedded controller An intelligent CPU controller interface plugged directly into the VXI backplane giving it direct access to the VXIbus It must have all of its required VXI interface capabilities built in event Signals or interrupts generated by a device to notify another device of an asynchronous event The contents of events are device dependent external controller In this configuration a plug in interface board in a computer is connected to the
125. n Module Configuration 2 1 VXIbus Logical Address 2 1 SIMM Size 2 5 Load USER FACTORY Configuration 2 7 Protect Change Factory Configuration 2 8 Hardware Installation 2 8 Software Installation 2 9 Table of Contents Table of Contents VXI MIO Series User Manual vi National Instruments Corporation Chapter 3 Hardware Overview Analog Input 3 3 Input Mode 3 3 Input Polarity and Input Range 3 4 Considerations for Selecting Input Ranges 3 6 Dither
126. n how to physically connect the relevant pieces of the system Consult these guides when you are making your connections SCXI chassis manuals If you are using SCXI read these manuals for maintenance information on the chassis and installation instructions About This Manual VXI MIO Series User Manual xiv National Instruments Corporation Related Documentation The following National Instruments document contains information you may find helpful Application Note 025 Field Wiring and Noise Considerations for Analog Signals Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix D Customer Communication at the end of this manual National Instruments Corporation 1 1 VXI MIO Series User Manual Introduction Chapter 1 This chapter describes the VXI MIO Series modules lists what you need to get started describes the optional software and optional equipment and explains how to unpack your VXI MIO Series module About the VXI MIO Series Thank you for buying a National Instruments VXI MIO Series module The VXI MIO Series modules are completely VXI plug amp play
127. nal Sources Figure 4 5 shows how to connect a floating signal source to a channel on a VXI MIO Series module configured in DIFF input mode Figure 4 5 Differential Input Connections for Nonreferenced Signals Figure 4 5 shows two bias resistors connected in parallel with the signal leads of a floating signal source If you do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA and the PGIA will saturate causing erroneous readings You must reference the source to AIGND The easiest way is simply to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AIGND as well as to the negative input of the PGIA without Floating Signal Source Other Input Multiplexers Instrumentation Amplifier Vm Measured Voltage VS I O Connector AIGND Bias Current Return Paths Bias resistors see text ACH lt 8 15 gt ACH lt 0 7 gt AISENSE Selected Channel in DIFF Configuration PGIA Chapter 4 Signal Connections National Instruments Corporation 4 17 VXI MIO Series User Manual any resistors at all This connection works well for DC coupled sources with low source impedance less than 100 However for larger source impedances this connection leaves the differential signal path significantly out of balance Noise that couples elect
128. nge of 10 V 5 V You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely The software programmable gain on this module increases its overall flexibility by matching the input signal ranges to those that the ADC can accommodate The VXI MIO 64E 1 has gains of 0 5 1 2 5 10 20 50 and 100 and is suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 2 shows the overall input range and precision according to the configuration and gain used Table 3 2 Actual Range and Measurement Precision Range Configuration Gain Actual Input Range Precision 1 0 to 10 V 1 0 2 0 5 0 10 0 20 0 50 0 100 0 0 to 10 V 0 to 5 V 0 to 2 V 0 to 1 V 0 to 500 mV 0 to 200 mV 0 to 100 mV 2 44 mV 1 22 mV 488 28 V 244 14 V 122 07 V 48 83 V 24 41 V Chapter 3 Hardware Overview National Instruments Corporation 3 5 VXI MIO Series User Manual VXI MIO 64XE 10 This module has two input polarities unipolar and bipolar The VXI MIO 64XE 10 has a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 20 V 10 V You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely Note You can ca
129. ns 4 3 Analog Input Signal Connections 4 9 Types of Signal Sources 4 11 Floating Signal Sources 4 11 Ground Referenced Signal Sources 4 11 Input Configurations 4 12 Differential Connection Considerations DIFF Input Configuration 4 14 Differential Connections for Ground Referenced Signal Sources 4 15 Differential Connections for Nonreferenced or Floating Signal Sources 4 16 Single Ended Connection Considerations 4 18 Single Ended Connections for Floating Signal Sources RSE Configuration 4 19 Single Ended Connections for Grounded Signal Sources NRSE Configuration 4 19 Common Mode Signal Rejection Considerations
130. nt condition These pins are referenced to DGND and can be used to power external digital circuitry Power rating 4 65 to 5 25 VDC at 1 A Warning Under no circumstances should you connect these 5 V power pins directly to analog or digital ground or to any other voltage source on the VXI MIO Series module or any other device Doing so can damage the VXI MIO Series module and your device National Instruments is NOT liable for damages resulting from such a connection Timing Connections Warning Exceeding the maximum input voltage ratings which are listed in Tables 4 1 and 4 2 can damage the VXI MIO Series module National Instruments is NOT liable for any damages resulting from incorrect signal connections All external control over the VXI MIO module timing is routed through the 10 programmable function input signals labeled PFI lt 0 9 gt These signals are explained in detail in the Programmable Function Input Connections section in this chapter These PFI signals are bidirectional as output signals they are not programmable and reflect the state of many data acquisition waveform generation and general purpose timing signals There are five other dedicated output lines for the remainder of the timing signals As input signals the PFI signals are programmable and can control any data acquisition waveform generation and general purpose timing signals The data acquisition signals are expla
131. ntation for installation instructions National Instruments Corporation 3 1 VXI MIO Series User Manual Hardware Overview Chapter 3 This chapter presents an overview of the hardware functions on your VXI MIO Series module Figure 3 1 shows the block diagram for the VXI MIO Series modules Chapter 3 Hardware Overview VXI MIO Series User Manual 3 2 National Instruments Corporation Figure 3 1 VXI MIO Series Block Diagram EEPROM Config EPROM VXI Transceivers P1 MANTIS P2 MANTIS VXI Trigger and Clock Circuitry N V RAM Analog Bus I O Connector VXI Bus 3 2 A D Converter Programmable Gain Amplifier Bank Select Mux Mode Selection Switches Ref Buffer Cal Aux Trigger Level DACS External Trigger Analog Trigger Circuit Voltage REF Analog Muxes Banks 0 3 Calibration DACs Calibration DACS Signal Conditioning Control Circuitry DAC FIFOS DAC0 DAC1 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface ACH 48 63 ACH 32 47 ACH 16 31 ACH 0 15 Analog Input Control EEPROM Control EPF8282 DAQ STC Interface DMA Interface Bus Interface Analog Output Control Configuration EPROM Interface MITE VXI Port MXI Port I O Port ADC FIFO Timing VX
132. nts an overview of the hardware functions on your VXI MIO Series module Chapter 4 Signal Connections describes how to make input and output signal connections to your VXI MIO Series module via the module I O connector Chapter 5 Calibration discusses the calibration procedures for your VXI MIO Series module Appendix A Specifications lists the specifications for each module in the VXI MIO Series Appendix B Optional Cable Connector Descriptions describes the connectors on the optional cables for the VXI MIO Series modules About This Manual About This Manual VXI MIO Series User Manual xii National Instruments Corporation Appendix C Common Questions contains a list of commonly asked questions and their answers relating to usage and special features of your VXI MIO Series module Appendix D Customer Communication contains forms you can use to request help from National Instruments or to comment on our products The Glossary contains an alphabetical list and description of terms used in this manual including acronyms abbreviations metric prefixes mnemonics and symbols The Index alphabetically lists topics covered in this manual including the page where you can find the topic Conventions Used in This Manual The following conventions are used in this manual The
133. nts for the UISOURCE signal Figure 4 28 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source General Purpose Timing Signal Connections The general purpose timing signals are GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT GPCTR0_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP_DOWN and FREQ_OUT GPCTR0_SOURCE Signal Any PFI pin can externally input the GPCTR0_SOURCE signal which is available as an output on the PFI8 GPCTR0_SOURCE pin As an input the GPCTR0_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR0_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTR0_SOURCE signal reflects the actual clock connected to general purpose counter 0 This is true even if another PFI is externally inputting the source clock This signal is set to input High Z at startup t p t w t w t p t w 50 ns minimum 23 ns minimum Chapter 4 Signal Connections National Instruments Corporation 4 39 VXI MIO Series User Manual Figure 4 29 shows the timing requirements for the GPCTR0_SOURCE signal Figure 4 29 GPCTR0_SOURCE Signal Timing The maximum allowed frequency i
134. offer fax and telephone support through our technical support centers which are staffed by applications engineers Electronic Services National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and example programs For recorded instructions on how to use the bulletin board and FTP services and for BBS automated information call 512 795 6990 You can access these services at United States 512 794 5422 or 800 327 3077 Up to 14 400 baud 8 data bits 1 stop bit no parity United Kingdom 01635 551422 Up to 9 600 baud 8 data bits 1 stop bit no parity France 1 48 65 15 59 Up to 9 600 baud 8 data bits 1 stop bit no parity To access our FTP site log on to our Internet host ftp natinst com as anonymous and use your Internet address such as joesmith anywhere com as your password The support files and documents are located in the support directories Bulletin Board Support FTP Support Click here to comment on this document via the National Instruments website at http www natinst com documentation daq FaxBack is a 24 hour information retrieval system containing a library of documents on a wide range of technical information You can access FaxBack from a touch tone telephone at 512 418 1111 You can submit te
135. og ground tie point to your VXI MIO Series module if necessary Connection of analog input signals to your VXI MIO Series module depends on the configuration of the analog input channels you are using and the type of input signal source With the different configurations you can use the PGIA in different ways Figure 4 2 shows a diagram of your VXI MIO Series module PGIA Figure 4 2 VXI MIO Series PGIA The PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals connected to your VXI MIO Series module Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the module The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage is referenced to the board Instrumentation Amplifier Measured Voltage Vm PGIA Vin Vin Vm Vin Vin Gain Chapter 4 Signal Connections National Instruments Corporation 4 11 VXI MIO Series User Manual ground Your VXI MIO Series module ADC measures this output voltage when it performs A D conversions You must reference all signals to ground either at the signal source or at the module If you have a floating source reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors see the Di
136. on 4 29 VXI MIO Series User Manual scans before TRIG2 can be recognized After the scan counter decrements to zero it is loaded with the number of posttrigger scans to acquire while the acquisition continues The module ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero After the selected edge of TRIG2 is received the module will acquire a fixed number of scans and the acquisition will stop This mode acquires data both before and after receiving TRIG2 As an output the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence This is true even if the acquisition is being externally triggered by another PFI The TRIG2 signal is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 50 to 100 ns This signal is set to input High Z at startup Figures 4 17 and 4 18 show the input and output timing requirements for the TRIG2 signal Figure 4 17 TRIG2 Input Signal Timing Figure 4 18 TRIG2 Output Signal Timing Rising edge polarity Falling edge polarity tw tw 10 ns minimum t w t w 50 100 ns Chapter 4 Signal Connections VXI MIO Series User Manual 4 30 National Instruments Corporation STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal which is available as an output on the PFI7 STARTSCAN pin Refer to Figures 4 11 and 4 12 for the relationship of STARTSCAN to th
137. one of the PFIs As an output this is the TRIG2 signal In pretrigger applications a low to high transition indicates the initiation of the posttrigger conversions TRIG2 is not used in posttrigger applications PFI2 CONVERT DGND Input Output PFI2 Convert As an input this is one of the PFIs As an output this is the CONVERT signal A high to low edge on CONVERT indicates that an A D conversion is occurring PFI3 GPCTR1_SOURCE DGND Input Output PFI3 Counter 1 Source As an input this is one of the PFIs As an output this is the GPCTR1_SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTR1_GATE DGND Input Output PFI4 Counter 1 Gate As an input this is one of the PFIs As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 GPCTR1_OUT DGND Output Counter 1 Output This output is from the general purpose counter 1 output Signal Name Reference Direction Description Continued Chapter 4 Signal Connections National Instruments Corporation 4 5 VXI MIO Series User Manual PFI5 UPDATE DGND Input Output PFI5 Update As an input this is one of the PFIs As an output this is the UPDATE signal A high to low edge on UPDATE indicates that the analog output primary group is being updated PFI6 WFTRIG DGND Input Output PFI6 Wa
138. onversions the first CONVERT will appear when the onboard sample interval counter reaches zero If you select an external CONVERT the first external pulse after STARTSCAN will generate a conversion Separate the STARTSCAN pulses by at least one scan period A counter on your VXI MIO Series module internally generates the STARTSCAN signal unless you select some external source This counter is started by the TRIG1 signal and is stopped either by software or by the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a data acquisition sequence Scans occurring within a data acquisition sequence may be gated by either the hardware AIGATE signal or software command register gate tw 50 100 ns a Start of Scan toff toff 10 ns minimum Start Pulse CONVERT STARTSCAN STARTSCAN b Scan in Progress Two Conversions per Scan tw Chapter 4 Signal Connections VXI MIO Series User Manual 4 32 National Instruments Corporation CONVERT Signal Any PFI pin can externally input the CONVERT signal which is available as an output on the PFI2 CONVERT pin Refer back to Figures 4 11 and 4 12 for the relationship of CONVERT to the data acquisition sequence As an input the CONVERT signal is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or fa
139. or signal sources that are already referenced to some ground point with respect to the VXI MIO Series module In these cases the PGIA can reject any voltage caused by ground potential differences between the signal source and the module In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the module The PGIA can reject common mode signals as long as V in and V in are both within 11 V of AIGND Analog Output Signal Connections The analog output signals are DAC0OUT DAC1OUT EXTREF and AOGND EXTREF is not available on the VXI MIO 64XE 10 DAC0OUT is the voltage output signal for analog output channel 0 DAC1OUT is the voltage output signal for analog output channel 1 EXTREF is the external reference input signal for both analog output channels You must configure each analog output channel individually for external reference selection in order for the signal applied at the Vs Vm Measured Voltage ACH lt 0 15 gt AIGND Instrumentation Amplifier I O Connector AISENSE Vcm Selected Channel in NRSE Configuration Common Mode Noise and Ground Potential Ground Referenced Signal Source PGIA Input Multiplexers Chapter 4 Signal Connections National Instruments Corporation 4 21 VXI MIO Series User Manual external reference input
140. oration the overall input range and precision according to the configuration and gain used Considerations for Selecting Input Ranges Which input polarity and range you select depends on the expected range of the incoming signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range For best results you should match the input range as closely as possible to the expected range of the input signal For example if you are certain the input signal will not be negative below 0 V unipolar input polarity is best However if the signal is negative or equal to zero using unipolar input polarity will yield inaccurate readings Table 3 3 Actual Range and Measurement Precision VXI MIO 64XE 10 Range Configuration Gain Actual Input Range Precision 1 0 to 10 V 1 0 2 0 5 0 10 0 20 0 50 0 100 0 0 to 10 V 0 to 5 V 0 to 2 V 0 to 1 V 0 to 500 mV 0 to 200 mV 0 to 100 mV 152 59 V 76 29 V 30 52 V 15 26 V 7 63 V 3 05 V 1 53 V 10 to 10 V 1 0 2 0 5 0 10 0 20 0 50 0 100 0 10 to 10 V 5 to 5 V 2 to 2 V 1 to 1 V 500 to 500 mV 200 to 200 mV 100 to 100 mV 305 18 V 152 59 V 61 04 V 30 52 V 15 26
141. pose counter 0 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This signal is set to input High Z at startup Figure 4 31 shows the timing of the GPCTR0_OUT signal Figure 4 31 GPCTR0_OUT Signal Timing GPCTR0_UP_DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 will count down when this pin is at a logic low and count up when it is at a logic high You can disable this input so that software can control the up down functionality and leave the DIO6 pin free for general use Rising edge polarity Falling edge polarity tw tw 10 ns minimum GPCTR0_SOURCE GPCTR0_OUT GPCTR0_OUT Toggle output on TC Pulse on TC TC Chapter 4 Signal Connections National Instruments Corporation 4 41 VXI MIO Series User Manual GPCTR1_SOURCE Signal Any PFI pin can externally input the GPCTR1_SOURCE signal which is available as an output on the PFI3 GPCTR1_SOURCE pin As an input the GPCTR1_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTR1_SOURCE monitors the actual clock connected to general purpose counter 1 This is true even if the source clo
142. ppens when 50 such acquisitions are averaged together quantization is still plainly visible In Figure 3 2c the sine wave is acquired with dither on There is a considerable amount of noise visible But averaging about 50 such acquisitions as shown in Figure 3 2d eliminates both the added noise and the effects of quantization Dither has the effect of forcing quantization noise to become a zero mean random variable rather than a deterministic function of the input signal Chapter 3 Hardware Overview VXI MIO Series User Manual 3 8 National Instruments Corporation Figure 3 2 Dither You cannot disable dither on the VXI MIO 64XE 10 This is because the ADC resolution is so fine that the ADC and the PGIA inherently produce almost 0 5 LSB rms of noise This is equivalent to having a dither circuit that is always enabled Multichannel Scanning Considerations All of the VXI MIO Series modules can scan multiple channels at the same maximum rate as their single channel rate however you should pay careful attention to the settling times for each of the modules Refer to Appendix A Specifications for a complete listing of settling times for each of the VXI MIO Series modules When scanning among channels at various gains the settling times may increase When the PGIA switches to a higher gain the signal on the previous channel may be well outside the new smaller range For instance suppose a 4 V signal is connecte
143. programmable function inputs PFIs See PFIs programmable function inputs programmable gain instrumentation amplifier See PGIA programmable gain instrumentation amplifier Q questions about VXI MIO series C 1 to C 6 analog input and analog output C 2 to C 4 general information C 1 to C 2 installation and configuration C 2 timing and digital I O C 4 to C 6 R reference selection analog output 3 10 referenced single ended input RSE See RSE referenced single ended input reglitch selection 3 11 RSE referenced single ended input description table 3 3 recommended configuration figure 4 13 single ended connections for floating signal sources 4 19 S SCANCLK signal description table 4 4 timing connections 4 26 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 settling time 3 9 signal connections analog input 4 9 to 4 20 analog output 4 20 to 4 21 digital I O 4 22 to 4 23 field wiring considerations 4 45 input configurations 4 12 to 4 20 common mode signal rejection 4 20 differential connections DIFF input configuration 4 14 floating signal sources 4 16 to 4 17 ground referenced signal sources 4 15 nonreferenced signal sources 4 16 to 4 17 recommended configuration figure 4 13 single ended connections 4 18 to 4 20 floating signal sources RSE configuration 4 19 grounded signal sources NRSE configuration 4 19 to 4 20 I O connector 4 1
144. pture TTL transistor transistor logic Glossary National Instruments Corporation G 15 VXI MIO Series User Manual U UI update interval UISOURCE update interval counter clock signal unipolar Unipolar input means that the input voltage range is between 0 and V ref where V ref is a positive reference voltage update The output equivalent of a scan One or more analog or digital output samples Typically the number of output samples in an update is equal to the number of channels in the output group For example one pulse from the update clock produces one update which sends one new sample to every analog output channel in the group UPDATE update signal update rate The number of output updates per second V V volts VDC volts direct current VI Virtual Instrument 1 A combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 A LabVIEW software module VI which consists of a front panel user interface and a block diagram program VISA A new driver software architecture developed by National Instruments to unify instrumentation software GPIB DAQ and VXI It has been accepted as a standard for VXI by the VXI plug amp play Systems Alliance V IH volts input high V IL volts input low V in volts in V OH volts output high V OL volts
145. r that some VXI MIO Series modules have settling times that vary with gain and accuracy See Appendix A for exact specifications Appendix C Common Questions VXI MIO Series User Manual C 2 National Instruments Corporation 3 What type of 5 V protection do the VXI MIO Series modules have The VXI MIO Series modules have 5 V lines equipped with a self resetting 1 A fuse Installation and Configuration 4 What jumpers should I be aware of when configuring my VXI MIO Series module Refer to the Module Configuration section of Chapter 2 Installation and Configuration for this information 5 Which National Instruments document should I read first to get started using DAQ software The release notes document for your application or driver software is always the best starting place 6 What version of NI DAQ must I have to program my VXI MIO Series module You must have NI DAQ version 4 9 0 or higher for the VXI MIO 64E 1 or VXI MIO 64XE 10 modules 7 What is the best way to test my module without having to program the module The NI DAQ Configuration Utility formerly WDAQCONF has a Test menu with some excellent tools for doing simple functional tests of the module such as analog input and output digital I O and counter timer tests Also the Test Configuration option will verify that the logical address and interrupt settings for the module are functioning
146. rds directly for precise synchronization of functions For the VXI MIO Series modules the RTSI bus trigger lines are implemented using VXIbus trigger lines S s seconds S sample scan One or more analog or digital input samples Typically the number of input samples in a scan is equal to the number of channels in the input group For example one pulse from the scan clock produces one scan which acquires one new sample from every analog input channel in the group scan clock The clock controlling the time interval between scans On boards with interval scanning support this clock gates the channel clock on and off On boards with simultaneous sampling this clock clocks the track and hold circuitry SCANCLK scan clock signal scan rate The number of scans per second scan width The number of channels in the channel list or number of ports in the port list you use to configure an analog or digital input group SCXI Signal Conditioning eXtensions for Instrumentation The National Instruments product line for conditioning low level signals within an external chassis near sensors so only high level signals are sent to DAQ boards in the noisy PC environment SE single ended inputs A term used to describe an analog input that is measured with respect to a common ground settling time The amount of time required for a voltage to reach its final value within specified limits Glossary VXI MIO Series User Manual
147. rds have programmable gains instrument driver A set of high level software functions that controls a specific VXI or RS 232 programmable instrument or a specific plug in DAQ board interrupt A computer signal indicating that the CPU should suspend its current task to service a designated activity interrupt level The relative priority at which a device can interrupt interval scanning Scanning method where there is a longer interval between scans than there is between individual channels comprising a scan I O input output The transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces I OH current output high I OL current output low ISA Industry Standard Architecture K KB kilobytes 1 024 bytes when referring to memory kS 1 000 samples L LabVIEW Laboratory Virtual Instrument Engineering Workbench LASTCHAN last channel bit LED light emitting diode logical address An 8 bit number that uniquely identifies each VXIbus device in a system It defines the A16 register addresses of a device and indicates Commander and Servant relationships LSB least significant bit Glossary VXI MIO Series User Manual G 10 National Instruments Corporation M m meters mainframe The chassis of a VXIbus system that mechanically contains VXI modules inserted into the backplane ensurin
148. re 3 15 programmable function inputs 3 16 timebase 3 16 VXIbus triggers 3 17 transfer characteristics analog input VXI MIO 64E 1 A 3 VXI MIO 64XE 10 A 11 analog output VXI MIO 64E 1 A 5 to A 6 VXI MIO 64XE 10 A 13 TRIG1 signal timing connections 4 27 to 4 28 input timing figure 4 28 output timing figure 4 28 TRIG2 signal timing connections 4 28 to 4 29 input timing figure 4 29 output timing figure 4 29 triggers analog 3 11 to 3 14 above high level triggering mode figure 3 13 below low level triggering mode figure 3 12 block diagram 3 12 high hysteresis triggering mode 3 13 inside region triggering mode figure 3 13 low hysteresis triggering mode 3 14 specifications VXI MIO 64E 1 analog trigger A 8 digital trigger A 8 VXIbus A 8 VXI MIO 64XE 10 analog trigger A 15 to A 16 digital trigger A 16 VXIbus A 16 VXIbus triggers 3 17 troubleshooting See questions about VXI MIO series U UISOURCE signal 4 37 to 4 38 unipolar input mixing with bipolar channels note 3 5 unipolar output 3 10 to 3 11 unpacking VXI MIO series boards 1 6 UPDATE signal timing connections 4 36 to 4 37 input timing figure 4 37 output timing figure 4 37 USER FACTORY configuration loading 2 7 to 2 8 protecting changing factory configuration 2 8 V VirtualBench software 1 3 voltage output VXI MIO 64E 1 A 6 VXI MIO 64XE 10 A 13 VXIbus logical address 2 1 to 2 2 select
149. re This means that the module circuitry is not actively driving the output either high or low However these lines may have pull up or pull down resistors connected to them as shown in Table 4 1 These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 will be in the high impedance state after power on and Table 4 1 shows that there is a 50 k pull up resistor This pull up resistor will set the DIO 0 pin to a logic high when the output is in a high impedance state National Instruments Corporation D 1 VXI MIO Series User Manual Customer Communication Appendix D For your convenience this appendix contains forms to help you gather the information necessary to help us solve your technical problems and a form you can use to comment on the product documentation When you contact us we need the information on the Technical Support Form and the configuration form if your manual contains one about your system configuration to answer your questions as quickly as possible National Instruments has technical assistance through electronic fax and telephone systems to quickly provide the information you need Our electronic services include a bulletin board service an FTP site a FaxBack system and e mail support If you have a hardware or software problem first try the electronic support systems If the information available on these systems does not answer your questions we
150. reflects the trigger that initiates waveform generation This is true even if the waveform generation is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This signal is set to input High Z at startup Figures 4 24 and 4 25 show the input and output timing requirements for the WFTRIG signal Figure 4 24 WFTRIG Input Signal Timing Figure 4 25 WFTRIG Output Signal Timing Rising edge polarity Falling edge polarity tw tw 10 ns minimum t w t w 50 100 ns Chapter 4 Signal Connections VXI MIO Series User Manual 4 36 National Instruments Corporation UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an output on the PFI5 UPDATE pin As an input the UPDATE signal is configured in the edge detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output the UPDATE signal reflects the actual update pulse that is connected to the DACs This is true even if the updates are being externally generated by another PFI The output is an active low pulse with a pulse width of 300 to 350 ns This signal is set to input High Z at startup Figures 4 26 and 4 27 sho
151. rostatically onto the positive line does not couple onto the negative line because it is connected to ground Hence this noise appears as a differential mode signal instead of a common mode signal and so the PGIA does not reject it In this case instead of directly connecting the negative line to AIGND connect it to AIGND through a resistor that is about 100 times the equivalent source impedance The resistor puts the signal path nearly in balance so that about the same amount of noise couples onto both connections yielding better rejection of electrostatically coupled noise Also this configuration does not load down the source other than the very high input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND as shown in Figure 4 5 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example the source impedance is 2 k and each of the two resistors is 100 k the resistors load down the source with 200 k and produce a 1 gain error Both PGIA inputs require a DC path to ground in order for the PGIA to work If the source is AC coupled capacitively coupled the PGIA needs a resistor between the positive input and AIGND If the source has low impedance choose a resistor that is large enough not to si
152. s 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR0_SOURCE signal unless you select some external source GPCTR0_GATE Signal Any PFI pin can externally input the GPCTR0_GATE signal which is available as an output on the PFI9 GPCTR0_GATE pin As an input the GPCTR0_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR0_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTR0_GATE signal reflects the actual gate signal connected to general purpose counter 0 This is true even if the gate is being externally generated by another PFI This signal is set to input High Z at startup Figure 4 30 shows the timing requirements for the GPCTR0_GATE signal t p t w t w t p t w 50 ns minimum 23 ns minimum Chapter 4 Signal Connections VXI MIO Series User Manual 4 40 National Instruments Corporation Figure 4 30 GPCTR0_GATE Signal Timing in Edge Detection Mode GPCTR0_OUT Signal This signal is available only as an output on the GPCTR0_OUT pin The GPCTR0_OUT signal reflects the terminal count TC of general pur
153. set error After calibration 1 0 mV max Before calibration 200 mV max Gain error relative to internal reference After calibration 0 01 of output max Before calibration 0 5 of output max Appendix A Speci cations for VXI MIO 64E 1 VXI MIO Series User Manual A 6 National Instruments Corporation Gain error relative to external reference 0 to 0 5 of output max not adjustable Voltage Output Ranges 5 V 0 to 10 V EXTREF 0 to EXTREF software selectable Output coupling DC Output impedance 0 1 max Current drive 5 mA max Protection Short circuit to ground Power on state 0 V External reference input Range 11 V Overvoltage protection 25 V powered on 15 V powered off Input impedance 10 k Bandwidth 3 dB 1 MHz Dynamic Characteristics Settling time for full scale step 3 s to 0 5 LSB accuracy Slew rate
154. signal 4 41 GPCTR1_UP_DOWN signal 4 43 to 4 44 GPCTR0_GATE signal 4 39 to 4 40 GPCTR0_OUT signal description table 4 5 VXI MIO 64E 1 table 4 7 VXI MIO 64XE 10 table 4 9 waveform generation timing connections 4 40 GPCTR0_SOURCE signal 4 38 to 4 39 GPCTR0_UP_DOWN signal 4 40 GPCTR1_GATE signal 4 41 to 4 42 GPCTR1_OUT signal description table 4 4 VXI MIO 64E 1 table 4 7 VXI MIO 64XE 10 table 4 8 waveform generation timing connections 4 42 to 4 43 GPCTR1_SOURCE signal 4 41 GPCTR1_UP_DOWN signal 4 43 to 4 44 ground referenced signal sources description 4 11 differential connections 4 15 recommended configuration figure 4 13 single ended connections NRSE configuration 4 19 to 4 20 Index National Instruments Corporation I 5 VXI MIO Series User Manual H hardware installation 2 8 to 2 9 hardware overview analog input 3 3 to 3 9 considerations for selecting input ranges 3 6 dither 3 7 to 3 8 input modes 3 3 to 3 4 input polarity and range 3 4 to 3 6 multichannel scanning considerations 3 8 to 3 9 analog output 3 10 to 3 11 output polarity selection 3 10 to 3 11 reference selection 3 10 reglitch selection 3 11 analog trigger 3 11 to 3 14 above high level analog triggering mode figure 3 13 below low level analog triggering mode figure 3 12 block diagram 3 12 high hysteresis analog triggering mode figure 3 13 inside region analog triggering mode figure 3 13
155. sp t gsu t gh t gw GATE t out OUT V OH V OL sc t t t t t t 50 ns minimum sp 23 ns minimum gsu 10 ns minimum gh 0 ns minimum gw 10 ns minimum out 80 ns maximum Source Clock Period Source Pulse Width Gate Setup Time Gate Hold Time Gate Pulse Width Output Delay Time Chapter 4 Signal Connections VXI MIO Series User Manual 4 44 National Instruments Corporation The GATE and OUT signal transitions shown in Figure 4 35 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram but with the source signal inverted and referenced to the falling edge of the source signal would apply when the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on your VXI MIO Series module Figure 4 35 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by t gsu and t gh in Figure 4 35 The gate signal is not required to be held after the active edge of the source signal If an internal timebase clock is used the gate signal cannot be synchronized with the clock In this case g
156. suring electrical signals from sensors transducers and test probes or fixtures and inputting them to a computer for processing 2 Collecting and measuring the same kinds of electrical signals with A D and or DIO boards plugged into a computer and possibly generating control signals with D A and or DIO boards in the same computer DC direct current Glossary National Instruments Corporation G 5 VXI MIO Series User Manual default setting A default parameter value recorded in the driver In many cases the default input of a control is a certain value often 0 that means use the current default setting For example the default input for a parameter may be do not change current setting and the default setting may be no AMUX 64T boards If you do change the value of such a parameter the new value becomes the new setting You can set default settings for some parameters in the configuration utility or by manually using switches located on the device device 1 A plug in data acquisition board card or pad that can contain multiple channels and conversion devices Plug in boards PCMCIA cards and devices such as the DAQPad 1200 which connects to your computer parallel port are all examples of DAQ devices 2 A component of a VXIbus system normally one VXIbus board However multiple slot devices and multiple device modules can operate on a VXIbus system as a single device Some examples of devices are computers multimeters
157. tecting changing factory configuration 2 8 storage of calibration constants 5 1 Index VXI MIO Series User Manual I 4 National Instruments Corporation e mail support D 2 environment specifications VXI MIO 64E 1 A 9 VXI MIO 64XE 10 A 16 environmental noise avoiding 4 45 equipment optional 1 5 EXTREF signal analog output connections 4 20 to 4 21 analog output reference selection 3 10 description table 4 3 VXI MIO 64E 1 table 4 6 EXTSTROBE signal description table 4 4 timing connections 4 26 to 4 27 illustration 4 27 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 F factory configuration See USER FACTORY configuration fax support D 2 FaxBack support D 2 field wiring considerations 4 45 floating signal sources description 4 11 differential connections 4 16 to 4 17 recommended configuration figure 4 13 single ended connections RSE configuration 4 19 FREQ_OUT signal description table 4 5 VXI MIO 64E 1 table 4 7 VXI MIO 64XE 10 table 4 9 waveform generation timing connections 4 44 frequently asked questions See questions about VXI MIO series FTP support D 1 G general purpose timing signal connections 4 38 to 4 44 FREQ_OUT signal 4 44 GPCTR0_GATE signal 4 39 to 4 40 GPCTR0_OUT signal 4 40 GPCTR0_SOURCE signal 4 38 to 4 39 GPCTR0_UP_DOWN signal 4 40 GPCTR1_GATE signal 4 41 to 4 42 GPCTR1_OUT signal 4 42 to 4 43 GPCTR1_SOURCE
158. the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually to be inputs or outputs Warning Exceeding the maximum input voltage ratings which are listed in Tables 4 1 and 4 2 can damage the VXI MIO Series module National Instruments is NOT liable for any damages resulting from such incorrect signal connections Figure 4 9 shows signal connections for three typical digital I O applications Figure 4 9 Digital I O Connections Complex switch circuitry is not shown in order to simplify the figure LED 5 V TTL Signal 5 V DGND Switch I O Connector VXI MIO Series Board DIO lt 0 gt DIO lt 1 gt DIO lt 2 gt DIO lt 3 gt DIO lt 4 gt DIO lt 5 gt DIO lt 6 gt DIO lt 7 gt Chapter 4 Signal Connections National Instruments Corporation 4 23 VXI MIO Series User Manual Figure 4 9 shows DIO lt 0 2 3 5 6 gt configured for digital input and DIO lt 1 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch Digital output applications include sending TTL signals and driving external devices such as the LED Power Connections One pin on the I O connector supplies 5 V from the VXIbus power supply via a self resetting fuse The fuse will reset automatically after you remove the overcurre
159. the D A code switches You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of your output signal The VXI MIO 64E 1 module has built in reglitchers which can be enabled through software on its analog output channels See the Analog Output Reglitch Selection section in Chapter 3 for more information about reglitching 11 Can I synchronize a one channel analog input data acquisition with a one channel analog output waveform generation on my VXI MIO Series module Yes One way to accomplish this is to use the waveform generation timing pulses to control the analog input data acquisition To do this follow steps a through d below in addition to the usual steps for data acquisition and waveform generation configuration Appendix C Common Questions VXI MIO Series User Manual C 4 National Instruments Corporation a Enable the PFI5 line for output as follows If you are using NI DAQ call Select_Signal deviceNumber ND_PFI_5 ND_OUT_UPDATE ND_HIGH_TO_LOW If you are using LabVIEW invoke the Route Signal VI with signal name set to PFI5 and signal source set to AO Update b Set up data acquisition timing so that the timing signal for A D conversion comes from PFI5 as follows If you are using NI DAQ call Select_Signal deviceNumber ND_IN_CONVERT ND_PFI_5 ND_HIGH_TO_LOW If you are using LabVIEW
160. the office nearest you LabVIEW or LabWindows CVI VXIplug amp play Instrument Driver NI DAQ Driver Software VISA VXI DAQ Hardware Other Application Development Environments Chapter 1 Introduction VXI MIO Series User Manual 1 6 National Instruments Corporation Custom Cabling Mating connectors and a backshell kit for making custom 96 pin cables for your VXI MIO Series module are available from National Instruments If you want to develop your own cable however the following guidelines may be useful For the analog input signals shielded twisted pair wires for each signal yields the best results assuming that you use differential inputs Tie the shield for each signal pair to the ground reference at the source You should route the analog lines separately from the digital lines When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals Unpacking Your VXI MIO Series module is shipped in an antistatic package to prevent electrostatic damage to the module Electrostatic discharge can damage several components on the module To avoid such damage in handling the module take the following precautions Ground yourself via a grounding strap or by holding a grounded object Touch the antistatic package to a metal part of your VXIbus chassis be
161. tial connections for floating signal sources 4 16 to 4 17 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 AISENSE signal analog input connections 4 9 4 10 description table 4 3 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 AISENSE2 signal analog input connections 4 9 4 10 description table 4 3 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 amplifier characteristics VXI MIO 64E 1 A 3 VXI MIO 64XE 10 A 11 analog input 3 3 to 3 9 common questions about C 2 to C 4 considerations for selecting input ranges 3 6 dither 3 7 to 3 8 input modes 3 3 to 3 4 input polarity and range 3 4 to 3 6 VXI MIO 64E 1 3 4 to 3 5 VXI MIO 64XE 10 3 5 to 3 6 multichannel scanning considerations 3 8 to 3 9 signal connections 4 9 to 4 20 analog input specifications VXI MIO 64E 1 amplifier characteristics A 3 dynamic characteristics A 4 input characteristics A 1 to A 2 stability A 4 transfer characteristics A 3 VXI MIO 64XE 10 amplifier characteristics A 11 dynamic characteristics A 12 input characteristics A 10 stability A 12 transfer characteristics A 11 analog output 3 10 to 3 11 common questions about C 2 to C 4 output polarity selection 3 10 to 3 11 reference selection 3 10 reglitch selection 3 11 signal connections 4 20 to 4 21 analog output specifications VXI MIO 64E 1 dynamic characteristics A 6 output characteristics A 5 stability A 6 to A 7 Index VXI MIO Series User M
162. ting system include version number ____________________________________________ Clock speed ______MHz RAM _____MB Display adapter _________ Mouse ___yes ___no Other adapters installed _______________________________________ Hard disk capacity _____MB Brand ____________________________________________ Instruments used ________________________________________________________________ _______________________________________________________________________________ National Instruments hardware product model_________ Revision ________________________ Configuration ___________________________________________________________________ National Instruments software product____________________________ Version _____________ Configuration ___________________________________________________________________ The problem is _________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ List any error messages ___________________________________________________________ ____________________________________________________________________________
163. tive graphics a state of the art user interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of VIs for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to the NI DAQ software LabWindows CVI features interactive graphics a state of the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using LabWindows CVI with National Instruments DAQ hardware is included with the NI DAQ software kit The LabWindows CVI Data Acquisition Library is functionally equivalent to the NI DAQ software VirtualBench features VIs that combine DAQ products software and your computer to create a standalone instrument with the added benefit of the processing display and storage capabilities of your computer VirtualBench instruments load and save waveform data to disk in the same forms that can be used in popular spreadsheet programs and word processors VirtualBench features report generation and printing capabilities Using ComponentWorks LabVIEW LabWindows CVI or VirtualBench software will greatly reduce the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ is not packaged wit
164. to 4 9 exceeding maximum ratings warning 4 1 pin assignments figure 4 2 signal descriptions table Index VXI MIO Series User Manual I 8 National Instruments Corporation 4 3 to 4 5 power connections 4 23 timing connections 4 23 to 4 44 data acquisition timing connections 4 25 to 4 34 AIGATE signal 4 33 to 4 34 CONVERT signal 4 32 to 4 33 EXTSTROBE signal 4 26 to 4 27 SCANCLK signal 4 26 SISOURCE signal 4 34 STARTSCAN signal 4 30 to 4 31 TRIG1 signal 4 27 to 4 28 TRIG2 signal 4 28 to 4 29 typical posttriggered acquisition figure 4 25 typical pretriggered acquisition figure 4 26 general purpose timing signal connections 4 38 to 4 44 FREQ_OUT signal 4 44 GPCTR0_GATE signal 4 39 to 4 40 GPCTR0_OUT signal 4 40 GPCTR0_SOURCE signal 4 38 to 4 39 GPCTR0_UP_DOWN signal 4 40 GPCTR1_GATE signal 4 41 to 4 42 GPCTR1_OUT signal 4 42 to 4 43 GPCTR1_SOURCE signal 4 41 GPCTR1_UP_DOWN signal 4 43 to 4 44 programmable function input connections 4 24 to 4 25 waveform generation timing connections 4 34 to 4 38 UISOURCE signal 4 37 to 4 38 UPDATE signal 4 36 to 4 37 WFTRIG signal 4 34 types of signal sources 4 11 floating 4 11 ground referenced 4 11 SIMM size configuration 2 5 to 2 6 accessing SIMM sockets 2 6 DRAM configuration table 2 6 to 2 7 single ended connections description 4 18 floating signal sources RSE 4 19 grounded signal sources NRSE 4 19 to 4 20
165. to be used by that channel If you do not specify an external reference the channel will use the internal reference You cannot use an external analog output reference with the VXI MIO 64XE 10 Analog output configuration options are explained in the Analog Output section in Chapter 3 Hardware Overview The following ranges and ratings apply to the EXTREF input signal Usable input voltage range 11 V peak with respect to AOGND Absolute maximum ratings 15 V peak with respect to AOGND AOGND is the ground reference signal for both analog output channels and the external reference signal Figure 4 8 shows how to make analog output connections and the external reference input connection to your VXI MIO Series module Figure 4 8 Analog Output Connections The external reference signal can be either a DC or an AC signal The module multiplies this reference signal by the DAC code divided by the full scale DAC code to generate the output voltage Channel 0 Channel 1 External Reference Signal Optional Load Load VOUT 0 VOUT 1 DAC1OUT AOGND DAC0OUT EXTREF Analog Output Channels VXI MIO Series Board Vref Chapter 4 Signal Connections VXI MIO Series User Manual 4 22 National Instruments Corporation Digital I O Signal Connections The digital I O signals are DIO lt 0 7 gt and DGND DIO lt 0 7 gt are
166. ule via the module I O connector The VXI MIO 64E 1 and VXI MIO 64XE 10 I O connector has 96 pins that you can connect to 68 pin accessories with the SH966868 shielded cable Refer to Appendix B Optional Cable Connector Descriptions for more information I O Connector Figure 4 1 shows the 96 pin I O connector pin assignments on the VXI MIO 64E 1 and VXI MIO 64XE 10 A signal description follows the connector pinouts Warning Connections that exceed any of the maximum ratings of input or output signals on the VXI MIO Series modules can damage the module Maximum input ratings for each signal are given in Tables 4 1 and 4 2 in the Protection column National Instruments is NOT liable for any damages resulting from signal connections that exceed these maximum ratings Chapter 4 Signal Connections VXI MIO Series User Manual 4 2 National Instruments Corporation Figure 4 1 I O Connector Pin Assignment for the VXI MIO 64E 1 and VXI MIO 64XE 10 ACH63 ACH54 ACH60 ACH51 ACH57 ACH48 ACH46 ACH37 AISENSE21 ACH42 ACH33 ACH31 ACH22 ACH28 ACH19 ACH25 ACH16 ACH7 ACH13 ACH4 ACH3 ACH9 ACH0 DAC0OUT DIO4 DIO2 DIO7 5 V PFI1 TRIG2 PFI4 GPCTR1_GATE PFI6 WFTRIG PFI9 GPCTR0_GATE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
167. veform Trigger As an input this is one of the PFIs As an output this is the WFTRIG signal In timed analog output sequences a low to high transition indicates the initiation of the waveform generation PFI7 STARTSCAN DGND Input Output PFI7 Start of Scan As an input this is one of the PFIs As an output this is the STARTSCAN signal This pin pulses once at the start of each analog input scan in the interval scan A low to high transition indicates the start of the scan PFI8 GPCTR0_SOURCE DGND Input Output PFI8 Counter 0 Source As an input this is one of the PFIs As an output this is the GPCTR0_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTR0_GATE DGND Input Output PFI9 Counter 0 Gate As an input this is one of the PFIs As an output this is the GPCTR0_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 0 GPCTR0_OUT DGND Output Counter 0 Output This output is from the general purpose counter 0 output FREQ_OUT DGND Output Frequency Output This output is from the frequency generator output Signal Name Reference Direction Description Continued Chapter 4 Signal Connections VXI MIO Series User Manual 4 6 National Instruments Corporation Table 4 1 shows the I O signal summary for the VXI MIO 64E 1 Table 4 1 VXI MIO 64E 1 I O Signal Summary
168. w the input and output timing requirements for the UPDATE signal Chapter 4 Signal Connections National Instruments Corporation 4 37 VXI MIO Series User Manual Figure 4 26 UPDATE Input Signal Timing Figure 4 27 UPDATE Output Signal Timing The DACs are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The VXI MIO Series module UI counter normally generates the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE signal You must configure the PFI pin you select as the source for the UISOURCE signal in the level detection mode You can configure the Rising edge polarity Falling edge polarity tw tw 10 ns minimum t w tw 300 350 ns Chapter 4 Signal Connections VXI MIO Series User Manual 4 38 National Instruments Corporation polarity selection for the PFI pin for either active high or active low Figure 4 28 shows the timing requireme
169. y Glossary VXI MIO Series User Manual G 2 National Instruments Corporation A A amperes A16 space VXIbus address space equivalent to the VME 64 KB short address space In VXI the upper 16 KB of A16 space is allocated for use by VXI module s configuration registers This 16 KB region is referred to as VXI configuration space A24 space VXIbus address space equivalent to the VME 16 MB standard address space A32 space VXIbus address space equivalent to the VME 4 GB extended address space AC alternating current ACH analog input channel signal A D analog to digital ADC A D converter address space A set of 2 n memory locations differentiated from other such sets in VXI VMEbus systems by six addressing lines known as address modifiers n is the number of address lines required to uniquely specify a byte location in a given space Valid numbers for n are 16 24 and 32 In VME VXI because there are six address modifiers there are 64 possible address spaces address window A portion of address space that can be accessed from the application program AIGATE analog input gate signal AIGND analog input ground signal AISENSE analog input sense signal AISENSE2 analog input sense 2 signal ANSI American National Standards Institute AOGND analog output ground signal Glossary National Instruments Corporation G 3 VXI MIO Series User Manual B backplane An assem

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