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USER`S MANUAL

1. Eomum SS ph S E wum E Omaume HE AAA TA 10 P7C P7C P7 output by program control 11 1 TIMF CNTF P1C 1 TIMFC CNTFC P1C Ref Tmr Cnt Sleep Off mode control register Timebase control register Counter control register Timer control register Watch Dog Timer control register Po EM73PA00 User s Manual Pin Type Circuity Diagrams e 36 Chapter 5 Clock and Timing 5 1 Overview This chapter summarizes the clock and timing for EM73PA00 CPU 5 2 Clock and Timing Generator The clock generator is supported by a single clock system The clock sources from crystal The working frequency range is 200KHz to 4MHz depending on the actual working voltage 5 2 1 Clock and Timing Generator Structure The clock generator unit generates a basic system clock fc When CPU is in off mode the clock generator will remain disabled until the off condition ends EM73PA00 User s Manual Clock and Timing e 37 He The system clock control unit generates 4 basic clock phase 1 2 3 S4 and a system clock signal Mask option sleep System clock System clock control 1 S2 S3 S4 5 2 2 Clock and Timing Generator Function The fc frequency is equal to the oscillation frequency of pins XIN and XOUT with crystal resonator When CPU is under off mode the XOUT pin is in high state The instruction cycle equals to 4 ba
2. 50 8 4 DC ELECTRICAL CHARACTERISTICS c cccsssseceessscecsesseeecensceeesseeecsssueeecseseeceesaeeecsesaeeeceeseeesceeeeecessaeeecsesaesecseeeeenees 51 EM73PA00 User s Manual Introduction e 4 Chapter 1 Introduction 1 1 Overview EM73PA00 is an advanced single chip CMOS 4 bit OTP One Time Programming microcontroller It contains 24K byte ROM 128 nibble RAM 4 bit ALU 16 level subroutine nesting 13 bit programmable counter 8 bit watchdog timer and 13 bit programmable timer on one chip 1 2 Key Features e Si gate CMOS process e Low power consumption e Single power supply 2 5V to 5 5V e High speed operation 4MHz max ROM capacity 24576 X 8 bits RAM capacity 128 X 4 bits e Built in time base counter 22 stages e P 8 bits input port e O P 8 bits output port e 5 bits bi direction I O port e Programmable counter and timer e Built in watchdog timer e Low voltage detector e Subroutine nesting Up 16 levels e Interrupt Three Internal e Standby function Instruction execution time 1us 4MHz e Packaging chip form 7 28 pin SOP 7 28 TSSOP EM73PA00BM e RMO carrier wave output port of remote controller EM73PA00 User s Manual Introduction e 5 aus 1 3 Functional Block Diagram The figure below illustrates a simplified block diagram of the EM73PA00 followed by pin assignments descript
3. 6 3 2 Off and Sleep Conditions The following conditions exist when system is under Off Sleep Mode stop off only and CPU internal status held e Internal time base clear to 0 CPU internal memory flags register and held original states e Program Counter freezes at the executed address until CPU released 46 e Interrupt and Power Saving Functions EM73PA00 User s Manual EM73PA00 User s Manual Example Entry the Off Sleep mode LDIA 0101B 16 entry Off model wakeup in edge 6 3 3 Release Condition The following conditions exists when system is wakes up from Off Sleep Mode Osc starts to oscillate off only e Warm up period in process off only e According PC to execute the following program 6 3 4 Edge Off Sleep Mode Releases the Off Sleep condition by the falling edge of any of the following pins e PO 0 3 4 0 3 When 4 wakeup in edge level release mode must attend to the other PO P4 whether enable wakeup release mode because the wakeup result decide by wakeup function gating Ref 4 1 3 NOTE There are 8 independent mask options for wake up function in 7 So the wake up function of PO 0 3 or P4 0 3 is enabled or disabled independently HALT condition Program Counter execute HALT instruction OSC not stop and CPU internal status held CPU internal memory flags register and I O held original state When Interrupt happen the HALT
4. EM73PA00 User s Manual Miscellaneous Function e 49 ene Chapter 8 Electrical Properties 8 1 Overview This chapter provides information on electrical thermal and timing properties of the 7 8 2 Absolute Maximum Ratings Items Sym Ratings Conditions Supply Voltage 0 3V to 6V Topr 25 C Input Voltage Vss 0 3V to Vpp 0 3V 25 C Operating Temperature Tex cem SS 8 3 Recommended Operating Conditions Items Sym Ratings Condition 50 e Electrical Properties EM73PA00 User s Manual 8 4 DC Electrical Characteristics Vop 3V Vss 0V 20 to 70 Parameters Sym Min Unit Conditions 1 Typ no load Fc 4MHz Operation current 0 4 mA consumpion no load at OFF mode No use low voltage Standby current 0 4 1 uA detector consumption no load at OFF mode Use low voltage Standby current 4 uA detector consumption A Input Current li 3 TEST High level input m 1 uA PO P4 P7 Voo current 1 High level input lin2 5 2 uA RESET Vin Vdd 0 3V current 2 Low level input uA PO P4 P7 with pull up resistor current 1 Low level input 5 uA RESET Vin Vss current 2 High level output 10 5 A Vout 2 1V current 1 20 High level output uA P5 P6 Vout 2 6V current 3 Low level output A RMO Vout 0 9V current 1 Low level output P1 1 P7 Vout 0 9V current 2 Low level output P5 P6
5. 8n 6 n 1 15 a 86h n 0 STACK SP lt PC 0100 1111 PC STACK SP SP SP 1 1 7 10 Input Output Object Code Binary m Description ere foe ers INA p 011011110100 1111 0100 01101111 0100pppp Acc PORT AcePORT p A soii NENNT CNN 3 gt 1 7 11 Flag Manipulation mm Object Code Binary a Description ME CIEJES TECFC 0011 SFeCP CF 0 lt 0 fo enn se 1 7 12 Interrupt Control n Object Code Binary P Description ep ps 01100011007 ILelL amp r gt UR NDS E EN O D A EXAE onion 11 0101 MASKoAc 0100 1101 FLAG PC lt STACK SP SP lt SP 1 EIF 1 EM73PA00 User s Manual Introduction e 16 1 7 13 CPU Control ere t Object Code Binary Operation Description genes oe Impe NOP 0101010 0110 no no operation HALT 0100 0111 CPU halt wait interrupt release 1 7 14 Timer Counter Data Pointer and Stack Pointer Control mem Object Code Binary PEE Description Le ere LDADRL 011010101111 1100 10101111 1100 011010101111 1100 STADPL 0110 1001 1111 1100 PE STADPM 0110 1001 1111 1101 DPyeace 2 2 STADPH 0110 10011111 1110 2 2 1 stase fono
6. Under Addition operation if the result is 0 Z will be 1 Otherwise Z will be 0 When Addition operation has a carry out C is 1 Otherwise C will be 0 Example Operation 4 7 8 8 0 2 Subtraction ALU supports Subtraction function with instructions SUBM k SUBA SBCAM and DECM The Subtraction operation affects C and Z Under Subtraction operation if the result is negative C is equal to borrow out If the result is positive C will be 1 Likewise if the result of subtraction operation is 0 the Z is 1 Otherwise Z will be 1 Example Operation Z e s Lacs v ps AAA 3 Rotation Two types of Rotation operations are available One is Rotation Left the other is Rotation Right Signal and Function Descriptions e 29 ics i 3 4 HL Register EM73PA00 User s Manual RLCA instruction rotates ACC value counter clockwise shift the CF value into the LSB bit of ACC and then hold the shift out data in CF MSB LSB is ACC RRCA instruction rotates ACC value clockwise shift the CF value into the MSB bit of ACC and then hold the shift out data in CF MSB LSB ACC Example Rotate ACC clockwise right and shift 1 into the MSB bit of ACC TTCFS CF lt 1 RRCA rotate ACC right and shift CF 1 into MSB HL Register are two 4 bit registers They are used as a pair of pointer for RAM memory address They are
7. P4 0 3 INPUT 4 bit input port Pull up pull down resistor Wakeup 5 0 3 4 bit output port Push pull or open drain P6 0 3 4 bit output port Push pull or open drain EM73PA00 User s Manual Introduction e 12 062 1 7 Instruction Set Overview The instruction set is optimized to support those instructions most commonly used or executed 1 7 1 Data Transfer Object Code Operation Description Byte Cycle Binary X 0110 1010 xxxx xxxx Acc RAM x 2 2 LDAM 0101 1010 Acc lt RAM HL LD 0110 0101 Acc lt ROM DP LDAXI 01100111 Accc ROM DP DP 1 1 7 2 Rotate Object Code Operation Description Byte Cycle Binary RRCA 0101 0001 mE 1 7 3 Arithmetic Operation Flag Object Code Operation Description Byte Cycle Binary 1 ADCAM 0111 0000 lt RAM HL CF 1 ADD 0100 1001 kkkk yyyy RAMIy RAMIy E EM73PA00 User s Manual Introduction e 13 EE MESA DEAN NE 1 7 4 Logical Operation Object Code Operation Description Byte orte ee fer or Binary ors cen prr fonon E E sow ono mos 2 7 7 Fors mo oo 7 7 1 camera 2 onion aseacerawiny 1 1 1212 1 7 5 Exchange Flag Object Code Operation Description Byte Cycle CF Binary
8. 0002h 000Ch 3 Address 000Eh 0086h 4 Address 0000h 1FFFh Address 0000h 0002h 0004h 0006h 0008h 000Ah 000Ch 000Eh 0086h Bank 0 Reset start address Reserved 07FFh 0800h OFFFh 1000h 1FFFh RR Reset start address 3 kinds of interrupt service routine entry addresses SCALL subroutine entry address only available at OOOEh 0016h 001Eh 0026h 002Eh 0036h 003Eh 0046h 004Eh 0056h 005 0066h 006Eh 0076h 007Eh 0086h Except for the regions used for the above functions other region can be used as user s program region Data table for LDAX LDAX instructions Programming Model e 19 2 1 1 User s Program and Fixed Data User s program and fixed data are stored in the program ROM User s program is executed using the PC value to fetch an instruction code User s Program The 24Kx8 bits program ROM can be divided into 4 banks at 4Kx8 bits per bank The program ROM bank is selected by P3 2 0 The program counter is a 13 bit binary counter The PC and P3 are initialized to O during reset When P3 2 0 000B program ROM and Bankd are selected When P3 2 0 001B Bank0 and 2 are selected When P3 2 0 010B Bank0 and Bank3 are selected Address P3 x000B P32x001B P32x010B P3 x011B P3 x100B 0000h OFFFh 1000h Bank1 Bank2 Bank3 Bank4 Bank5 1FFFh Example BANK 0 START LDIA 00H set program ROM to
9. 24K X 8BITS FOR EM73PAOQ cessere nennen 19 2I Users Prosram and Dat ie tecti iba 20 22 128 NIBBLE 23 22A Zero Page ON 23 VIN 24 or le a oe Pr Re EA ee 24 22 Address Mode cred v bead teret de ndun er metet uar teta ass 24 2 3 PROGRAM COUNTER 24K ROM FOR EM73PA O0 enne enne nennen nnne 25 2 I Branch essentiae etam mei ent 25 2 3 2 JUMP instr cti n ise ii areae i i este er P iie e ES 25 2 3 3 Subroutine Instruction esses eene ener ettet en E AE RENAT ERRE E EE ER enter tnn enne 25 2 3 4 Interrupt Acceptance 26 2 3 3 Interrupt Return Operai Mitad dd dida le 26 2 3 6 Reset Operati t A A 26 2 3 7 Other Operations nai OE REP 26 SIGNAL AND FUNCTION DESCRIPTIONS 27 3 1 ACCUMULATOR A CC c 27 3 2 BLAGS detecte cr o 27 32A Carry Flap CF RET 27 3 22 Zero ZF horn tet vt 28 3 2 3 SLAMS Flag 28 3 2 4 a 28 28 3 3 1 ce 29 EM73PA00 User s Manual Introduction e 3 3 3 2 ALU Supported Functions 29 SA REGISTER sionista odiada ias 30 3 4 1 HL Regis
10. 6 Reset Operation PCLo 2 3 7 Other Operations For 1 byte instruction execution PC 1 For 2 byte instruction execution PC 2 For 3 byte instruction execution PC 3 EM73PA00 User s Manual Programming Model 26 Chapter 3 Signal and Function Descriptions 3 1 Accumulator ACC Accumulator ACC is a 4 bit data register for temporary data ACC plays the role of holding the source data and result for arithmetic logic and comparison operations 3 2 Flags There are three types of flag e Carry Flag CF e Zero Flag ZF e Status Flag SF These three 1 bit flags are influenced by the arithmetic logic and comparison operation All flags are loaded into stack when an interrupt subroutine is served and the flags are restored after RTI instruction is executed 3 2 1 Carry Flag CF The Carry Flag is affected by the following operations a Addition CF as a carry out indicator Under Addition operation when a carry out occurs CF is 1 Likewise if the operation has no carry out CF is EM73PA00 User s Manual Signal and Function Descriptions e 27 b Subtraction CF as borrow in indicator Under Subtraction operation when a borrow in occurs the CF is 0 Likewise if there is no borrow in CF will be Tu c Comparison CF is as a borrow in indicator for Comparison operation as in the Subtraction operation d Rotati
11. SF 1 Clear El to inhibit other interrupts happened Clear the IL with which interrupt source has already been Execute interrupt subroutine from the interrupt entry address 7 CPU accept RTI restore PC and flags from stack Set El to accept other interrupt requests Example Enable interrupt TRGA LDIA 11008 EM73PA00 User s Manual EXAE set mask register 1100B EICIL 111111B enable interrupt F F Interrupt and Power Saving Functions e 45 6 3 Power Saving OFF Sleep Function During Off and Sleep Modes CPU keeps the systems internal status under low power consumption condition Under Off Mode the system clock changes into snooze state The system needs a warm up period to stabilize the system clock back to running condition after wake up Under Sleep Mode the system clock does not turn into snooze state It needs no warm up period 6 3 1 Off Sleep Control The Off and Sleep Modes are controlled by Port 16 and released by PO 0 3 or P4 0 3 dependent on Mask Option P16 3 2 1 0 SWWT Initial value 0000 WM Set wake up release mode SE Enable off sleep 0 Wake up in edge release mode 0 Reserved 1 Wake up in level release mode 1 Enable off sleep mode SWWT Set wake up warm up time OSC Note 00 2 5 XIN Stop Off mode 0 01 2 XIN Stop Off mode 1 10 2 XIN Stop Off mode 2 11 Sleep mode No Stop No Need warm up time
12. Vout 0 4V current 3 Hysteresis width Vo High level output mA P1 1 P7 Vout 2 1V current 2 EM73PA00 User s Manual Electrical Properties e 51 aus Vpp 4 5V Vss 0V Topr 20 C to 70 C Parameters Sym Min Typ Max Unit Conditions Operation current consumpion Standby current consumption Standby current consumption Input Current High level input current 1 High level input current 2 Low level input 200 150 100 current 1 Low level input current 2 High level output current 1 High level output current 2 High level output current 3 Low level output current 1 Low level output current 2 Low level output current 3 Hysteresis width Low battery detector 52 e Electrical Properties I No load Fc 4MHz No load at OFF mode No use low voltage detector No load at OFF mode Use low voltage detector p RESET Vin Vdd 0 3V RESET Vin Vss pep pem P5 P6 Vout 0 4V vp o OA EM73PA00 User s Manual
13. and CALL User can assign any level as the starting stack by providing the level number to stack pointer SP When an instruction CALL or subroutine is invoked before the subroutine is entered the previous PC address is saved into the stack until its return from those subroutines The PC value is restored by the data saved in stack 2 2 3 Data Area Except for the area used for user application the whole RAM can be used as data area for storing and loading general data 2 2 4 Address Mode The Data Memory also consisted of three Address Modes namely 1 Indirect Address Mode The address is specified by the HL registers Example LDAM RAM HL STAM RAM HL lt Acc 2 Direct Address Mode The address is specified by 8 bits of the second byte in the instruction field Instruction field RAM address Example LDA 43h Accc RAM 43h STA 23h RAM 23h lt Programming Model 24 3 Zero Page Address Mode The zero page is in address 000h 00Fh The address are the lower nibble of the second byte in the instruction field Instruction field RAM address 0000 y Example STD 4k y RAM y e fk 2 3 Program Counter 24K ROM for EM73PA00 The Program Counter PC consisted of 13 bit counter It indicates the next address to be executed by program ROM instruction For an 8K byte size ROM PC indicates address 0000h 1FFFh as BRANCH and CALL instructions PC is changed when ind
14. condition released Interrupt and Power Saving Functions e 47 Ent Chapter 7 Miscellaneous Function T 1 Overview This chapter describes the remote control signal output low voltage detector and watch dog timer features of EM73PA00 7 2 Remote control signal output port This RMO is a dedicate terminal for carrier wave output of remote controller When a remote control data is written into the remote control output data register P1 0 the data is output from RMO terminal as it is 3 2 1 0 Function Description RMO output low Output high Initial state 0 7 3 Low Voltage Detector If power supply voltage is lower than normally operating voltage automatically initializes internal system This function can be used by masking option 48 e Miscellaneous Function EM73PA00 User s Manual 7 4 Watch Dog Timer The watch dog timer is an 8 bit timer that protects from runaway programs The block diagram of the watch dog timer are shown below The watch dog timer is enabled or disabled by mask option If watch dog timer is enabled each interval time whice choosing by P21 the system will be reset WDT counter LE WDT control P21 WDT register XIN 2 RESET pin Mask option P21 is the control port of watch dog timer and the WDT time up signal will reset the system Porat 2 1 0 Function Description Nothing wor w pm _ Initial state 0 00
15. 0 664 7 23 P4 0 610 0 492 9 24 P4 1 612 1 1604 6 25 P4 2 489 9 1604 6 26 P4 3 368 8 1604 6 27 P5 0 247 7 1604 6 28 P5 1 126 6 1604 6 Chip size 1520 3550 um For PCB layout IC substrate must be floated or connected to Vss EM73PA00 User s Manual Introduction e 11 aus 1 6 Pin Descriptions Symbol Pin Ty Function Mask Options 1 Power supply 2 Power supply for programming OTP 1 Power supply 2 Power supply for programming OTP 1 Test pin high active Pull down resistor 2 VPP high voltage 12V power source for programming OTP 1 System reset input signal low active Pull up resistor 2 RESET reset input signal for programming OTP Low voltage detector enable OSC A 1 Crystal or RC or external clock source connecting pin Crystal or RC osc type OSC H 2 Xin oscillator signal input for programming OTP RMO I O RMO Remote control signal output terminal P7 0 3 IO 4 bit bi direction I O port Output open drain or push pull P7 1 DOUT data output for programming OTP Input pull up resistor or none P7 0 DIN data input for programming OTP 1 bit bi direction I O port PO 0 3 INPUT 4 bit input port Pull up pull down resistor P0 0 ALCK address counter clock for programming OTP Wakeup P0 1 PGMB program data to OTP cells for programming OTP P0 2 0EB data output enable for programming P0 3 DCLK data in out clock signal for programming
16. 0 User s Manual Stack Pointer is a 4 bit register that stores the present stack level number The SP value must be set first before using stack CPU will not initiate the SP value after a reset condition When a new subroutine is received the SP value is automatically decreased by one Likewise if a subroutine 1 sent the SP value is increased by one The data transfer between ACC and SP 1 done with instructions LDASP and STASP Example LDIA 0FH STASP SP lt 0 LCALL NEXT1 SP OEH PC lt NEXT1 Signal and Function Descriptions e 31 NEXT1 RET lt SP OEH 3 6 Data Pointer DP Data Pointer is a 12 bit register that stores the ROM address indicating the ROM code data specified by user refer to Chapter 2 Program 3 7 Reset Function When RESET pin is held in low level for at least 3 instruction cycles with the CPU working normally the CPU will begin to initialize the whole internal states When RESET pin changes to high level the CPU will begin to work in normal condition The following table shows the CPU internal state during reset condition Interrupt latch IL The RESET pin is a hysteresis input pin and it has a pull up resistor The simplest RESET circuit is to connect RESET pin with a capacitor to Vss and diode to Vpp RESET EM73PA00 User s Manual Signal and Function Descriptions e 32 Chapter Pin Type Circuity Diagrams 4 1 P
17. 1 7 VERSION ELAN MICROELECTRONICS CORPORATION USERS MANUAL 4 Bit Microcontroller ELAN MICROELECTRONICS CORPORATION Hsinchu Headquarters Hong Kong Office No 12 Innovation Road 1 Rm 1005B 10 F Empire Centre Science based Industrial Park 68 Mody Road Tsimshatsui HsinChu Taiwan ROC Kowloon Hong Kong Phone 886 3 563 9977 Phone 852 2723 3376 Fax 8863 563 9966 Fax 852 2723 7780 http www emc com tw Trademark Acknowledgments IBM is a registered trademark and PS 2 is a trademark of IBM Microsoft MS MS DOS and Windows are registered trademarks of Microsoft Corporation 2002 ELAN MICROELECTRONICS CORPORATION All Rights Reserved Printed in Taiwan ROC 6 2002 The material in this manual is subject to change without notice ELAN MICROELECTRONICS assumes no responsibility for errors that may appear in this manual ELAN MICROELECTRONICS makes no commitment to update nor to keep current the information contained in this manual The software described in this manual is furnished under a license or nondisclosure agreement and may be used or copied only in accordance with the terms of the agreement No part of this manual may be reproduced or transmitted in any form or by any means without the express written permission of ELAN MICROELECTRONICS INTRODUCTION 6 cccssisscsiscvsacssostsicessovsiseinctssctacsveisesscvssiesedsedesssssoasevasdesectateesestsdseuacbcavbanei
18. 10010111 sPcAcc STATAL 0110 10011111 0100 2 2 1 STATAM orn 1001 1111 0101 0110 1001 1111 0110 STATBL 0110 10011111 1000 TBheAc gt 2 2 1 STATBM 0110 1001 1111 1001 2 2 1 STATBH 0110 1001 1111 1010 2 2 Jg N N N NINININI N NINININI r2 N t2 N N EM73PA00 User s Manual Introduction e 17 1 8 Notation Conventions The following are the notation conventions used in the above tables and throughout this manual unless otherwise specified De TT STACKISP MASK RAMA m DP y High 4 bit of data pointer register Low 4 bit of CounterA TimerB register Middle 4 bit of CounterA TimerB High 4 bit of CounterA TimerB register register Transfer e uon ion oran O Y O 1 0 Contents of bit EX NM by bit Bit 5 to 0 of destination address for 1 to O of LR branch instruction EM73PA00 User s Manual Introduction e 18 Chapter 2 Programming Model 2 1 Program ROM 24K x 8bits for EM73PA00 24K x 8 bits program ROM contains user s program and some fixed data The basic structure of the program may be categorized into 4 partitions EM73PA00 User s Manual 1 Address 0000h 2 Address
19. 6sieceevuisesoosencedesbentsnsdseeseesesesbesies 5 1 1 OVERVIBW 5 1 2 Sog wp 5 1 3 FUNCTIONAL BLOCK DIAGRAM 6 1 4 PIN ASSIGNMENTS D 6 1 4 PIN ASSIGNMENTS 7 10 ANNA m 12 1 7 INSTRUCTION SET OVERVIEW icio titi tot etre ii 13 ERIT HT 13 1 7 2 13 1 73 Arithmetic Operation nen e ep eR RE 13 1 7 4 MENA NA 14 T EXCHIHBO eee titia feet estes tee 14 1 70 Branch 15 GT CR O 15 1 78 s coda e e eO ONE HE DER RINT IE Ie reperio DER C eR eM HERES 15 WATER AAE nos loo AE E E SE E A 16 Tipit a 16 III Blag ea ous 16 1 7 12 Interrupt Control oi oi a e a Hb id 16 1 7 13 CPU Controla ne ated etie 17 1 7 14 Timer Counter Data Pointer and Stack Pointer Control eene 17 1 8 NOTATION CONVENTIONS 18 PROGRAMMING 19 2 1 PROGRAM ROM
20. 778h STAMI RAM 31 lt 5h OUT 01h P3 set bank 1 LDIA 01h STADPL 2 0 lt 01h STADPM 5 3 lt 01h STADPH DP8 6 lt 01h Load DP 111h LDL 028 LDH 038 LDAX ACC lt Ch STAMI 32 Ch LDAXI ACC lt Ah increase DP 112h STAMI RAM 33 Ah 1 ORG 0777h DATA 56h BANK 2 ORG 111h DATA ACh EM73PA00 User s Manual Programming Model e 22 2 2 Data RAM 128 nibble A total of 128 nibble data RAM is available from address 000 to 7Fh Data RAM includes the Zero Page region Stacks and Data areas Increment Address 000h 00Fh Zero Page er E o a o 2 Ej jua waJ9u 040h 04Fh LEVEL 0 LEVEL 1 LEVEL 2 LEVEL 3 050h 05Fh LEVEL 4 LEVEL 5 LEVEL 6 LEVEL 7 060h O6Fh LEVEL 8 LEVEL 9 LEVEL 10 LEVEL 11 070h 07Fh LEVEL 12 LEVEL 13 LEVEL 14 LEVEL 15 T 080h OEFh No Used Area OFOh OFFh System Used Area 2 2 1 Zero Page From 000h to OOFh is the zero page location It is used as the zero page address mode pointer for instructions STD k y ADD k y CLR y b and CMP y b Example Write immediate data 07h to address 03h of RAM and clear bit 2 from RAM STD 07 03h RAM 03 lt 07h CLR OEh 2 RAM OEh 2 lt 0 EM73PA00 User s Manual Programming Model e 23 EM73PA00 User s Manual 2 2 2 Stack There are 16 maximum stack levels that user can use as subroutines including interrupt
21. ETAIL A EM73PA00 User s Manual Introduction e 7 Symbol a me 237 269 o a m orm 0308 oo n 0330 0406 0308 o w is oz 025 0318 o ws ns 17 704 17907 18 10 E s s oue um Ca ETE IE TN Physical Dimension of TSSOP28 7 a L1 DETAIL 2 1 EM73PA00 User s Manual Introduction e 8 EM73PA00 User s Manual Symbol min Max la pu oo om oe o om lo 5E aome a ae 0 65 BSC Introduction e 9 7 2 7 1 7 0 RESET lt An en r E GND XOUT XIN 1 5 Pad Diagram Introduction e 10 EM73PA00 User s Manual Pad No Symbol X Y 1 P5 2 5 5 1604 6 2 P5 3 115 6 1604 6 3 P6 0 236 7 1604 6 4 P6 1 357 8 1604 6 5 P6 2 478 9 1604 6 6 P6 3 600 0 1604 6 7 P1 1 610 0 489 8 8 P1 0 610 0 686 4 9 TEST 610 0 833 4 10 VDD 610 0 1058 6 11 XIN 537 5 1625 0 12 XOUT 365 7 1625 0 13 VSS 186 2 1625 0 14 RESET 38 6 1625 0 15 P7 0 210 4 1625 0 16 P7 1 382 2 1625 0 17 P7 2 554 0 1625 0 18 P7 3 610 0 1351 9 19 P0 0 610 0 1180 1 20 PO 1 610 0 1008 3 21 P0 2 610 0 836 5 22 P0 3 610
22. Jan moo PP 23 gt me o 3 mw s owners nen spannend 2 3 EM73PA00 User s Manual Introduction e 14 1 7 6 Branch E preme Object Code Binary Operation Description Cycle 000a aaaa aaaa aaaa If SF 1 than Else null 0100 0110 PC lt RAM HL 3 RAM HL 2 RAM HL 1 RAM HL 1 7 7 Compare Flag wnemoni Object Code Binary Operation Description Tor cw E femra gt a ono rotor em 2 EA ma m pora 3 T pz 2 ow ono monn far 1 7 8 Bit Manipulation Object Code Binary Operation Description ere fome erar Tar raw awe um 1 2 ux ye ono noone ramo 2 Sw nome CTE P 1 ff ser po ono moron e ser ye onono Je gt 13 ENE vo ono an 21 Dm o pue i E 3 po ono nora ms srcrorring CCC ES E m ve fonono semw o Pre pe ono nario pp _ srcrorrinn 2 2 EM73PA00 User s Manual Introduction e 15 1 7 9 Subroutine Object Code Binary Operation Description orse ce or LCALL a 001a aaaa aaaa SP lt SP 1 PCa STACK SP lt PC SCALL a 1110 nnnn SP lt SP 1 PC lt a
23. also used as 2 independent temporary 4 bit data registers For certain instructions L Register can be a pointer to indicate the pin number Port 4 The following illustrates the HL Register structure 1 0 3 2 1 H REGISTER L REGISTER 3 4 1 HL Register Function 1 Temporary Register Function HL Register is used as a temporary register for instructions LDL k LDH k LDHL THA THL INCL DECL EXAL EXAH LDHL legal address should be even number Example Load immediate data 5h into L register Dh into H register LDL 051 LDH 001 Signal and Function Descriptions e 30 2 Memory Pointer Function HL Register is used as a pointer of RAM memory address for instructions LDAM STAM STAMI Example Store immediate data into RAM of address 35h LDL 5h LDH 3h STDMI 0Ah RAM 35 lt Ah 3 I O Port Pointer Function HL Register is used as a pointer to indicate the I O port bit for instructions SELP CLPL TFPL when LR 0 it indicates P4 0 Example Set bit 0 of Port 4 to 1 LDL 00h SEPL 4 0 lt 1 4 direct Jump function HL Register is used as a pointer to indicate the destination address for instructions JHL HL should be limited on xxxxxx00 Example Jump to address 1234h LDL HO7H LDH H01H LDIA H01H STAMD 17 01H LDIA 02 STAMD 16 lt 02H LDIA 03H STAMD 15 lt 03H LDIA H04H STAM 14 lt 04H JHL lt 1234 3 5 Stack Pointer SP EM73PA0
24. bank1 OUTA P3 BR LDIA 01 set program ROM to bank2 OUTA P3 BR XB1 XB LDIA 02H set program ROM to bank3 OUTA P3 BR XC1 XC BR XD XD EM73PA00 User s Manual Programming Model 20 EM73PA00 User s Manual BANK 1 1 BR XA XA2 BR XA2 2 XB1 BR XB XB2 BR XB2 3 XC1 BR XC XC2 B XC2 Fixed Data Fixed Data is read out by table look up instruction The instruction requires the Data Pointer DP to indicate the ROM address in obtaining the ROM code data except Bank0 LDAX Acc ROM DP LDAXI ROM DP DP 1 Where DP is a 12 bit data register that stores the program ROM address as pointer for the ROM code data User must to initially load ROM address into DP register with instructions LDADPL LDADPM and LDADPH and assign the bank by out bank 1 into P3 To obtain the lower nibble of ROM code data use instruction LDAX and use LDAXI to obtain the higher nibble After LDAXI instruction The DP value will be increased one automatically Example Read out the ROM code of address 777h in Bank 1 and 111h in Bank 2 by table look up instruction OUT 00h P3 set bank 1 LDIA 07h STADPL DP2 0 lt 07h STADPM DP5 3 lt 07h STADPH DP8 6 lt 07h Load DP 777h LDL 00h LDH 03h Programming Model e 21 LDAX ACC lt 6h STAMI RAM 30 lt 6h LDAXI ACC lt 5h increase DP
25. e below consisted of two identical modules The timer or counter module can be set as initial timer or counter values which are sent to the register P28 and P29 are the command ports for Counter and Timer User can choose different operating modes and internal clock rates to set these two ports When timer counter overflows it will generate a TRGB TRGA interrupt request to interrupt control unit EM73PA00 User s Manual Clock and Timing e 39 CNTF TIMF CNTFC TIMFC 5 4 1 Counter Function RMO and P7 0are the external inputs for Counter Port 28 RMO input counter P7 0 input counter Under counter the counter increased by one at any falling edge of RMO and P7 0 When counter counts overflow it will provide an interrupt request TRGA to interrupt control Function Description P11 3 2 1 0 Read TIMF CNTF PIC Write TIMFC CNTFC CNTF When MASK2 0 if Counter overflow then read P11 2 whose value CNTF is 1 CNTFC When write 1 to P11 2 then Flag is reset CNTFC 0 EM73PA00 User s Manual Clock and Timing e 40 EM73PA00 User s Manual Example Enable Counter with P28 LDIA 10008 OUTA P28 Enable Counter with counter mode EICIL 110111b interrupt latch 0 enable El 5 4 2 Timer Function P29 is the command port for timer Function Description Internal pulse rate selection EC Under Timer Timer increased by one at any falling edge of internal pulse user can choose above 4 typ
26. eesaeennees 39 2324 40 5 42 LM EU O 41 INTERRUPT AND POWER SAVING FUNCTIONS ceres scene eee 43 6 1 Gus 43 0 2 INTERRUPT FUNCTION cm 43 6 2 1 Interrupt SHU CLUE adn 44 0 2 2 Interrupt Operation ts RA 45 6 3 POWER SAVING OFF SLEEP FUNCTION niter nnne rr en nene nein rre nnns 46 6 3 1 OFF Sleep Controlan diia 46 6 3 2 Off Gnd Sleep Conditions wees 46 6 3 3 Release CONAN 47 6 3 4 Edge Off Sleep 47 MISCELLANEOUS FUNGCTI QON ene oo se eR Soin RE Fe oS PE So sonssease 48 7 OVERVIEW P H E 48 7 2 REMOTE CONTROL SIGNAL OUTPUT PORT 48 7 3 LOW VOLTAGE DETEGTOR 31 rte Pe V Rec E EORR 48 Tb WATCH DOG TIMER he sett s ees anion dud eei eee aeons 49 ELECTRICAL PROPERTIES 50 8 1 OVERVIEW 50 8 2 ABSOLUTE MAXIMUM RATINGS acia 50 8 3 RECOMMENDED OPERATING
27. es of internal pulse rate by setting IPS to timer command When timer counts overflow it will provide an interrupt request TRGB to interrupt control P11 3 2 1 0 Read TIMF CNTF PIC Write TIMFC CNTFC TIMF When MASK1 0 if Timer overflow then read P11 3 whose value TIMF is 1 TIMFC When write 1 to P11 3 then Flag is reset TIMFC 0 Example To generate TRGB interrupt request after GOms with system clock XIN 4MHz LDIA 00108 EXAE Enable mask 1 EICIL 111011B interrupt latch lt 0 enable El Clock and Timing e 41 06 STATBL 01h STATBM LDIA 0Fh STATBH LDIA 10018 OUTA P29 enable Timer with internal pulse rate XIN 2 10 Hz NOTE The preset value of Timer Counter Register is calculated as follows Internal pulse rate XIN 2 10 4MHz The time of Timer Counter count one 2 10 XIN 1024 4000 0 256ms The number of internal pulse to get timer overflow 60 ms 0 256ms 234 375 OEAh The preset value of Timer Counter Register 10001 OEAh F16h EM73PA00 User s Manual Clock and Timing e 42 Chapter 6 Interrupt and Power Saving Functions 6 1 Overview This chapter summarizes the interrupt and power saving functions of EM73PA00 CPU 6 2 Interrupt Function They are 3 internal interrupt sources Multiple interrupts are admitted according to their priority 2 Interrupt Interrupt Enable Progra
28. icating the desired instruction 2 3 1 Branch Instruction BRa Object code 000a aaaa aaaa aaaa Condition SFz1 PC lt branch condition satisfied SF 0 lt 2 branch condition not satisfied Original PC value 2 2 3 2 JUMP instruction JHL Object code 0100 0110 Condition PC RAM HL 3 RAM HL 2 RAM HL 1 RAM HL HL 4 0 2 3 3 Subroutine Instruction SCALL a Object Code 1110 nnnn Condition PC lt a a 8n 6 nz1 Fh a 86h n 0 1 10 EM73PA00 User s Manual Programming Model e 25 LCALL a Object code 001a aaaa aaaa aaaa Condition a Pc a A a ajajajajajajajajaja RET Object code 0100 1111 Condition PC STACK SP SP 1 PC The return address stored in stack 2 3 4 Interrupt Acceptance Operation When an interrupt is received the original PC is entered into stack and interrupt vector is loaded into PC The interrupt vectors are as follows TRGA Counter overflow interrupt Pc o o ojo ojo ojojo o o 1 1 o TRGB Timer overflow interrupt TBI Time base interrupt PC o o ojo o o ojojo o t o s o 2 3 5 Interrupt Return Operation Object code 0100 1101 Condition FLAG lt STACK SP Ele 1 SP 1 PC The return address stored in stack 2 3
29. in Type Circuitry Diagrams 4 1 1 Reset Pin Type Type Reset A 4 1 2 Oscillation Pin Types X N OSCIN SC Type Osc A Type Osc H EM73PA00 User s Manual Pin Type Circuity Diagrams e 33 4 1 3 Input Pin Types WAKEUP CONTROL MASK OPTION WAKEUP FUNCTION ype Input A Type Input A Type Input B 4 1 4 1 0 Pin Types Special function SHL control input Output data Type O P Output data Output control Input enable Input data Type O P EM73PA00 User s Manual Pin Type Circuity Diagrams e 34 4 1 5 Bi direction Program Controlling P10 is the command port for controlling P7 Port10 4 2 1 0 Input Output mode selection P7C3 P7C2 P7C1 P7CO Function Description Initial state 0000 P7 n as input port P7 n as output port n 3 0 P11 1 is the command port for controlling P1 1 Port 11 3 2 1 0 Input Output mode selection TIMF CNTF PIC Function Description Initial state 0000 P1 1 as input port P1 1 as output port Example P7 output by program control LDIA 1110B P7C 1110 OUTA P10 P7 3 1 define output port LDIA 401118 OUTA P7 P7 0110B EM73PA00 User s Manual Pin Type Circuity Diagrams e 35 En EM73PA00 I O Port Descriptions Port Input Function Output Function Remarks o E 1 Pitino AO 4
30. ion RESET XIN XOUT Reset Clock Sleep Mode Control Generator Generator Control System Control Data pointer Instruction Decoder Stack pointer 12 bits ROM Time 12 bits counter Base timer amp P0 0 WAKEUPO po 1 WAREUPI I O Control PEN P0 2 WAKEUP2 P0 3 WAKEUP3 RMO 1 1 P5 0 P5 3 P6 0 P6 3 lt 7 0 7 3 lt gt WAKEUP P4 0 P4 3 EM73PA00 Block Diagram EM73PA00 User s Manual Introduction e 6 a 1 4 Pin Assignments TOP view P52 284 P51 P53 27 P50 60 26 P43 P61 25 P42 P62 5 24 P41 P63 16 23 P40 Pll 7 22 DCLK 8 21 P02 OEB VPP TEST 0 20 PO1 PGMB VDD VDD 10 19 POO ALCK Xin Xin I1 181 P73 I2 17 P72 GND Vss 13 16 P71 DOUT RESET RESET 14 15 P70 DIN Progrmming OTP signal lines Physical Dimension of SOP28 DETAIL A D
31. m ROM Int rmupt Source Lateh Condition Entry Address Counter overflow interrupt TRGA IL3 El 1 MASK2 1 006h Timer overflow interrupt TRGB 12 El 1 MASK1 1 008h Time base interrupt TBI IL1 El 1 MASKO 1 00Ah EM73PA00 User s Manual Interrupt and Power Saving Functions e 43 6 2 1 Interrupt Structure TRGB MASKI TRGA 2 TIMFC gt P11 TIMF CNTFC gt P11 CNTF Reset by TBI MASKO system reset 44 2 3 and program instruction IL Reset by system reset Priority Checker and program instruction Entry address generator Set by program 44 e Interrupt and Power Saving Functions EM73PA00 User s Manual Interrupt Controller IL1 IL3 MASKO0 MASK2 Priority Checker Interrupt latch Holds all interrupt requests from all interrupt sources IL can not be set by the program but can be reset by program or system reset So IL can only decide which interrupt source can be accepted MASK register may promote or inhibit all interrupt Sources Enable interrupt Flip Flop may promote or inhibit all interrupt sources When interrupt occurs El is auto cleared to 0 After RTI instruction is executed El is auto set to 1 again Check interrupt priority when multiple interrupts occur 6 2 2 Interrupt Operation Follow the steps below for interrupt operation 1 Locate PC and all flags to stack afk O MN accepted O Set interrupt entry address to Set
32. on CF shifts into the empty bit of accumulator for rotation and holds the shift out data after rotation e CF Test Instruction Under TFCFC instruction the CF content is sent into SF then clears itself as 0 For TTCFS instruction the content of CF is sent into SF then sets itself as 1 3 2 2 Zero Flag ZF ZF is affected by the result of ALU If the ALU operation generate a O result the ZF is 1 Otherwise the ZF is O 3 2 3 Status Flag SF The SF is affected by instruction operation and system status a SF is initiated to 1 for reset condition b Branch instruction is decided by SF When SF 1 branch condition is satisfied Likewise when SF 0 branch condition is dissatisfied 3 2 4 Examples Check the following arithmetic operation for CF ZF and SF Arithmetic Operation CF ZF mason Lt iomon fo o 0 3 3 ALU The Arithmetic and logic operations of 4 bit data are performed in ALU unit EM73PA00 User s Manual Signal and Function Descriptions e 28 EM73PA00 User s Manual 3 3 1 ALU Structure ALU supports user arithmetic operation functions including Addition Subtraction and Rotation The C Z affect the ZF CF and SF results 3 3 2 ALU Supported Functions 1 Addition ALU supports Addition function with instructions ADDAM ADCAM ADDM k and ADD k y The Addition operation affects signal C and signal 2
33. sic clock fc 1 instruction cycle 4 fc 5 3 Internal Time Base As illustrated below a time base has 23 stages Prescaler Binary Counter te 243 e s 901212223 Time base provides basic frequency for the following functions e TBI time base interrupt e Timer counter internal clock source e Warm up time for off mode disable EM73PA00 User s Manual Clock and Timing e 38 5 3 1 Time Base Interrupt TBI The time base is used to generate a single fixed frequency interrupt Eight types of frequencies can be selected with the P25 setting Single clock mode P25 3 2 1 0 initial value 0000 00 x x Interrupt disable 0 1 0 0 Interrupt frequency XIN 27 Hz 0 1 0 1 Interrupt frequency XIN 2 Hz 0110 Interrupt frequency XIN 2 Hz 0 1 1 1 Interrupt frequency XIN 2 Hz 1100 Interrupt frequency XIN 2 Hz 110 1 Interrupt frequency XIN 2 Hz 1 1 10 Interrupt frequency XIN 2 Hz 1 1 1 1 Interrupt frequency XIN 217 Hz 10xx Reserved 5 4 Timer Counter With Counter the counter data are saved in the timer registers TAH TAM and TAL User can set initial counter value Such value is loaded or stored by executing instructions LDATAH M L STATAH M L With Timer the timer data are saved in the TBH TBM and TBL User can set initial counter value Such value is loaded or stored by executing instructions LDATBH M L STATBH M L The timer counter basic structure see figur
34. ter Function ire id oc ion adidas 30 3 5 STACK POINTER ai 31 3 6 DATA POINTER DP icones aii 32 3 7 RBSET EUNGTION citet ue elim anbietet iere im 32 PIN TYPE CIRCUITY DIAGRAMS e eee eese toes ossa sosta setas seen esso seen Pese P seen Ps sese Poena ease sess eo seen toss 33 4 1 PIN TYPE CIRCUITRY DIAGRAMS ies enne ener rennen 33 BELL Reset Pin LY Pe 33 41 2 PIN IDO dl altas 33 41 3 Inp t Pin Types a a dci ascii a 34 ALA VOPIN TYPES E 34 4 1 5 Bi direction I O Program Controlling sss eee 35 EM73PA00 I O PORT DESCRIPTIONS eese nennen enhn ennt rnnt ee nn setas er nn sets setas etra 36 CLOCK AND 37 37 5 2 CLOCK AND TIMING GENERATOR RM 37 5 2 1 Clock and Timing Generator Structure bis asne e 37 5 2 2 Clock and Timing Generator Function 38 5 3 INTERNAL TIME BASE 3i GO peret d e Hee e 38 5 3 1 Time Base Interrupt TBI 39 5 4 TIMER COUNTER ccssssessccssssecssecessseesseceseessaecessssesaecsssecsuecesssesaecessecsuecessecsaecsssecsuscensecsuecssesecaueceaae

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