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RX610 Group Peripheral Driver Library User`s Manual

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2. Description Read the interrupt status data2 The status flags shall be stored in the following format b7 b1 bO 0 0 Idle 1 Bus error condition detected Return value True Category Bus Controller Reference R_BSC_Create Remarks Ifthe flag is set to 1 it shall be automatically cleared to 0 by this function Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t status Read the flags R_BSC_GetStatus amp status Y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 48 l ENESAS Under development Preliminary Specification RX610 Group 4 2 8 Specifications in this preliminary version are subject to change DMA Controller 1 R_DMAC_Create Synopsis Prototype Description 1 3 data1 The channel number n where n 0 to 3 data2 Configure the operation of channel DMAn If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Configure the DMA controller bool R_DMAC_Create uint8_t data1 uint32_t data2 uint8_t data3 void data4 void data5 uint32_t data6 void data7 void data8 uint32_t data9 void func uint8_t data10 Set up a DMA channel Transfer system
3. ce to be compared with Between 0x00 and OxFF for a port 0 or 1 for a pin Return value True if the parameters are valid otherwise false Functionality I O port References R_IO_PORT_Set R_IO_PORT_Read Remarks e f an invalid port or pin is specified the operation of the function cannot be guaranteed e This function waits for the I O port or port pin value to match the comparison data If the I O port s control registers are directly modified by the user this function may lock up Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions tinclude r_pdl_definitions h void func void Wait until pin P05 reads as 0 R_IO_PORT_Wait PDL_IO_PORT_0_5 0 i Wait until port 6 reads as 0x55 R_IO PORT Wait PDL_IO_PORT_6 0x55 i R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 28 ztENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 2 4 Port Function Control 1 R_PFC_Read Synopsis Prototype Description Return value Functionality References Remarks Program example Read a PFC register bool R_PFC_Read uint8_t data1 uint8_t data2 PFC register selection Get the value of a PFC register data1 Any value from 0
4. de PDL_CMT_FREQUENCY 1E3 PDL_NO_FUNC 0 Y Configure CMT channel 2 using register values R_CMT_Create 2 PDL_CMT_PCLK_DIV_32 Ox55AA PDL_NO_FUNC 0 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 2 R_CMT_CreateOneShot Synopsis Prototype Description Return value Category Reference R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 106 Configure a CMT channel as a one shot event bool R_CMT_CreateOneShot uint8_t data1 Timer channel selection uint16_t data2 Configuration selection float data3 Period void func Callback function uint8_t data4 Interrupt priority level Set up a Compare Match Timer channel and start the timer data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Control the CPU during the one shot operation PDL_CMT_CPU_ON or Allow the CPU to run normally while the one shot operates Stop the CPU when the one shot timer starts POLEMICA The CPU will re start when any valid interrupt occurs e DMAC DTC trigger control EN el Disable or enable activation of the DMAC PDL CMT DTC TRIGGER ENABLE when a compare match occu
5. Figure 5 11 Example of Pulse Output code R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 21 ENESAS 5 Usage Examples Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples For full flexibility the R_TMR_CreateChannel function can be used In this example Timer channel 0 is configured to provide pulses on pin TMOO with a pulse width of 200 ticks of PCLK and a duty cycle of 50 Note that the output transitions and counter clearing occur after the compare match has occurred So the values for compare match A and compare match B should be 1 less than the required count Peripheral driver function prototypes include r_pdl_tmr h include r_pdl_definitions h void main void Configure TMRO to clear on a compare match A output 1 at a compare match A and output O at a compare match B R_TMR_CreateChannel 0 DL_TMR_CLK_PCLK_DIV_1 PDL_TMR_CLEAR_CM_A PDL_TMR_OUTPUT_HIGH_CMA PDL_TMR_OUTPUT_LOW_CM_B L_NO_DATA L_NO_FUNC L_NO_FUNC L_NO_FUNC D 2 200 2 1 D D D Figure 5 12 Example of Pulse Output code Counter value Figure 5 13 Example of pulse output operation R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 22 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX6
6. Prototype Description Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 14 Read the external interrupt status bool R_INTC_GetExtInterruptStatus uint8_t data1 Pin selection uint8_t data2 Acquire the status for the specified external interrupt data1 Choose the interrupt pin to be checked A pointer to the buffer where the status data shall be stored PDL_INTC_IRQn n 0 to 15 or IRQn n 0 to 15 interrupt pin or PDL_INTC_NMI NMI interrupt pin data2 The status flags shall be stored in the following format For an IRQ pin b7 b4 b3 b2 bi bO Detection condition Pin level Detection status 00b Low level 0 01b Falling edge 0 Low 0 Not detected 10b Rising edge 1 High 1 Detected 11b Both edges For the NMI pin b7 b2 b1 bO Detection condition Detection status 0 0 Falling edge 0 Not detected 1 Rising edge 1 Detected True if all parameters are valid and exclusive otherwise false External interrupt R_INTC_CreateExtInterrupt R_INTC_ControlExtInterrupt 1 0 port register PFCR8 or PFCR9 is checked to determine which pin is used for IRQn e If this function is called from within a callback function the detection status will be 0 RPDL definitions include r_pdl_intc h RPDL
7. Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group Description 3 3 Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 117 data4 The interrupt priority level Select between 1 lowest priority and 7 highest priority 4 Library Reference This parameter will be ignored if PDL_NO_FUNC is specified for parameter func in functions R_SCI_Send or R_SCI_Receive True if all parameters are valid exclusive and achievable otherwise false SCI R_SCI_Destroy R_SCI_Send R_SCI_Receive Function R_CGC_Set must be called before any use of this function e This function configures each SCI pin that is required for operation It also disables the alternative modes on those pins For pin TXD5 it is not possible for this function to ensure that external bus signals CS4 or CS7 are not output on the same pin If pin TXD5 is required for transmission avoid selecting PDL_BSC_CS4_D or PDL_BSC_CS7_D when calling function R_BSC_Create For pin SCK5 it is not possible for this function to ensure that external bus signal CS5 is not output on the same pin If pin SCK5 is required avoid selecting PDL_BSC_CS5_D when calling function R_BSC_ Create The wait time of 1 data bit period that is required during configuration is handled within th
8. Description Shut down a timer pulse unit data The timer pulse unit n where n 0 or 1 Unit 0 comprises channels TPUO to TPUB Unit 1 comprises channels TPU6 to TPU11 Return value True if the unit selection is valid otherwise false Category Timer Pulse Unit Reference R_TPU_Create Remarks The timer pulse unit is put into the stop state to reduce power consumption Program example include r_pdl_tpu h void func void Shutdown TPU channels 0 to 5 R_TPU_Destroy 0 Y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 74 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 3 R_TPU_Control Synopsis Control a timer channel Prototype bool R_TPU_Control uint8_t data1 Channel selection uint8_t data2 Register selection uint16_tdata3 Register value uint16_tdata4 Register value uint16_tdata5 Register value uint16_tdata6 Register value uint16_tdata7 Register value Description Modify a timer channel s registers data1 The channel number n where n 0 to 11 data2 The channel settings to be modified If multiple selections are required use to separate each selection e Counter stop re start PDL_TPU_STOP or PDL_TPU_START Disable or re enable the counter clock source
9. Group 7 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 79 l ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group Description 2 2 data2 Operation control If multiple selections are required use to separate each selection Output trigger selection 4 Library Reference PDL_PPG_TRIGGER_TPUO or PDL_PPG_TRIGGER_TPU1 or PDL_PPG_TRIGGER_TPU2 or PDL_PPG_TRIGGER_TPU3 or Select Compare Match on TPU channel 0 to 3 as the output trigger PDL_PPG_TRIGGER_TPU6 or PDL_PPG_TRIGGER_TPU7 or PDL_PPG_TRIGGER_TPU8 or PDL_PPG_TRIGGER_TPU9 Non overlap control Select Compare Match on TPU channel 6 to 9 as the output trigger valid only for groups 4 to 7 PDL_PPG_NORMAL or PDL_PPG_NON_OVERLAP Select normal update on Compare Match A or non overlapping update on Compare Match A or B operation Invert control PDL_PPG_DIRECT or PDL_PPG_INVERT Select direct or inverted output data3 The initial and next output values for the enabled pins using the following format b7 b6 b5 b4 b3 b2 b1 bO Group Next pulse output values Initial output values Return value Category Reference PO3 PO2 PO1 POO PO3 PO2 PO1 POO PO7 PO6 PO5 PO4 PO7 PO6 PO5 PO4 PO11 PO10 PO9 PO8 PO11 PO10 PO9 PO8 PO15 PO14 PO 13 PO12 PO1
10. The registers to be modified PDL_TPU_COUNTER Update the timer counter register TCNT PDL_TPU_TGRA Update the general register A TGRA PDL_TPU_TGRB Update the general register A TGRB PDL_TPU_TGRC Update the general register A TGRC PDL_TPU_TGRD Update the general register A TGRD data3 The counter value This will be ignored if the register is not selected data4 The general register A value This will be ignored if the register is not selected data5 The general register B value This will be ignored if the register is not selected data6 The general register C value This will be ignored if the register is not selected data7 The general register D value This will be ignored if the register is not selected Return value True if all parameters are valid and exclusive otherwise false Category Timer Pulse Unit Reference R_TPU_Create Remarks e None R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 75 ztENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_tpu h RPDL device specific definitions tinclude r_pdl_definitions h void func void Load the counter on channel TPU channel 0 R_TPU_Controli 0 PDL_TPU_COUNTER OxFFDD 0 f 0 0
11. Description Shut down a TMR timer unit data The timer unit n where n 0 or 1 Unit 0 comprises channels TMRO and TMR1 Unit 1 comprises channels TMR2 and TMR3 Return value True if the unit selection is valid otherwise false Category Timer TMR Reference R_TMR_CreateChannel R_TMR_CreateUnit Remarks The timer unit is put into the stop state to reduce power consumption Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown channels 0 and 1 R_TMR_Destroy 0 Y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 95 l ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 6 R_TMR_ControlChannel Synopsis Write to timer channel registers Prototype bool R_TMR_ControlChannel uint8_t data1 Channel selection uint32_t data2 Configuration selection uint8_t data3 Register value uint8_t data4 Register value uint8_t data5 Register value Description Modify a timer channel s operation counter and compare registers data1 The channel number n where n 0 1 2 or 3 data2 The channel settings to be modified If multiple selections are required use to separate each selection
12. R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 22 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 23 include RPDL definitions r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set the lower 4 bits on port P1 to output R_IO_PORT_ModifyControl PDL_IO_PORT PDL_IO_POR Ox0F ri DIRECTION PDL_IO_PORT_OR Enable the pull up on pin PA3 R_IO_PORT_ModifyControl PDL_IO_PORT_A_3 PDL_IO_PORT_PULL_UP PDL_IO_PORT_OR 1 ENESAS 4 Library Reference Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 R_IO_PORT_Read Synopsis Read data from an I O port Prototype bool R_IO_PORT_Read uint16_tdata1 Port or port pin selection uint8_t data2 Pointer to the variable in which the value shall be stored Description Gets the value of an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 The value will be between 0x00 and OxFF for a port
13. Description 1 2 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 34 Configure the MCU low power conditions bool R_LPC_Create uint32_t data1 Configuration options uint32_t data2 Waiting times Load the registers that control module or CPU operation data1 Select the required settings If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Software and Deep Software Standby mode output port control PDL_LPC_EXT_BUS_ONor Leave the external bus address and control signals active or PDL_LPC_EXT BUS HI_Z set them to the high impedance state e On chip RAM power control PDL_LPC_RAM_ONor Enable or disable power to the RAM from 00000000h to PDL_LPC_RAM OFF QOOOFFFFh in deep software standby mode 1 O port retention control PDL_LPC_IO SAME or Select whether IO port retention is cancelled when deep software PDL _LPC_IO DELAY standby mode is ended or when CPU operation has resumed e Deep software standby cancel control PDL_LPC_CANCEL_IRQO_DISABLE or PDL_LPC_CANCEL_IRQO_FALLING or PDL_LPC_CANCEL_IRQO_RISING PDL_LPC_CANCEL_IRQ1_DISABLE or PDL_LPC_CANCEL_IRQ1_FALLING or PDL_LPC_CANCEL_IRQ1_RISING PDL_LPC_CANCEL_IRQ2 DISABLE or PDL_LPC_CANCEL_IRQ2_ FALLING or PDL_LPC_CANCEL_IRQ2_ RISING PDL_LPC_CANCEL_IRQ3_DISABLE or PDL_LPC_CANCEL_IRQ3_FALLING or PDL_LPC_CANCEL_IRQ3_RISING PDL
14. ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 3 R_DTC_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 63 Shutdown the Data Transfer Controller bool R_DTC_Destroy void No parameter is required Shutdown the Data Transfer Controller True Data Transfer Controller R_DTC_Control If another peripheral is being used to trigger a DTC transfer stop the triggers from that peripheral using Control or Destroy for that peripheral before calling this function e Use R_DTC_Control to stop the DTC before calling this function RPDL definitions include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown the DTC R_DTC_Destroy ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 R_DTC_Control Synopsis Control the Data Transfer Controller Prototype bool R_DTC_Control uint32_t data1 Control options uint32_t data2 Transfer data start address void data3 Source start address void data4
15. R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 60 PDL_DTC_TRIGGER_IRQ1 PDL_DTC_TRIGGER_IRQ2 PDL_DTC_TRIGGER_IRQ3 PDL_DTC_TRIGGER_IRQ4 PDL_DTC_TRIGGER_IRQ5 PDL_DTC_TRIGGER_IRQ6 PDL_DTC_TRIGGER_IRQ7 PDL_DTC_TRIGGER_IRQ8 PDL_DTC_TRIGGER_IRQ9 PDL_DTC_TRIGGER_IRQ10 PDL_DTC_TRIGGER_IRQ11 PDL_DTC_TRIGGER_IRQ12 PDL_DTC_TRIGGER_IRQ13 PDL_DTC TRIGGER _IRQ14 PDL_DTC_TRIGGER_IRQ15 External interrupt pin Valid edge detected on pin IRQn n 0 to 15 PDL_DTC_TRIGGER_ADIO PDL_DTC TRIGGER ADN PDL_DTC_TRIGGER_ADI2 PDL_DTC_TRIGGER_ADI3 Analog to Digital converter Conversion completed on unit n n 0 to 3 PDL_DTC_TRIGGER_TGIOA PDL_DTC_TRIGGER_TGIOB PDL_DTC_TRIGGER_TGI0C PDL_DTC_TRIGGER_TGIOD Timer Pulse Unit channel 0 Input capture or compare match A Input capture or compare match B Input capture or compare match C Input capture or compare match D PDL_DTC_TRIGGER_TGI1A Timer Pulse Unit Input capture or compare match A PDL_DTC_TRIGGER_TGI1B channel 1 Input capture or compare match B PDL_DTC_TRIGGER_TGI2A Timer Pulse Unit Input capture or compare match A PDL_DTC_TRIGGER_TGI2B channel 2 Input capture or compare match B PDL_DTC_TRIGGER_TGI3A PDL_DTC_TRIGGER_TGI3B PDL_DTC_TRIGGER_TGI3C PDL_DTC_TRIGGER_TGI3D Timer Pulse Unit channel 3 Input capture
16. Figure 5 2 Example of I O Port Operations ENESAS 5 Usage Examples Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 3 Bus Controller Figure 5 3 shows an example of external bus controller usage Peripheral driver function prototypes include r_pdl_bsc h include r_pdl_cgc h include e pdl inten RPDL device specific definitions include r_pdl_definitions h void BSC_error_handler void Clear the error signals R_BSC_Control PDL_BSC_ERROR_CLEAR i void main void uint8_t cs1l location 8 uint16_t cs7_location_16 csl_location_8 uint8_t 0x07000000ul cs7_location_16 uint16_t 0x01000000ul Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Configure the bus controller R_BSC_Create PDL_BSC_CS2_B 0 PDL_BSC_ERROR_ILLEGAL_ADDRESS_ E PDL_BSC_ERROR_TIM ENABL BSC_error_handler 5 di Configure area CS7 R_BSC_CreateArea 7 PDL_BSC_WRITE_SINGL oF oo oOo 8 0 GOG Configure area CS1 R_BSC_CreateArea 1 PDL_BSC_WIDTH_8 PDL_BSC_WRIT R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 6 ENESAS Un
17. Overflow PDL_INTC_VECTOR_CMIA1 PDL_INTC_VECTOR_CMIB1 PDL_INTC_VECTOR_OVI1 8 bit timer TMR channel 1 Compare match A Compare match B Overflow PDL_INTC_VECTOR_CMIA2 PDL_INTC_VECTOR_CMIB2 PDL_INTC_VECTOR_OVI2 8 bit timer TMR channel 2 Compare match A Compare match B Overflow PDL_INTC_VECTOR_CMIA3 PDL_INTC_VECTOR_CMIB3 PDL_INTC_VECTOR_OVI3 8 bit timer TMR channel 3 Compare match A Compare match B Overflow PDL_INTC_VECTOR_DMTENDO PDL_INTC_VECTOR_DMTEND1 PDL_INTC_VECTOR DMTEND2 Direct memory access Transfer complete on channel n n 0 to 3 PDL_INTC VECTOR DMTEND3 ntroller PDL_INTC_VECTOR_ERIO Error in data received PDL_INTC_VECTOR_RXIO SCI channel 0 Data received PDL_INTC_VECTOR_TXIO Start of next data transfer PDL_INTC_VECTOR_TEIO End of data transfer PDL_INTC_VECTOR_ERI1 Error in data received PDL_INTC_VECTOR_RXI1 SCI channel 1 Data received PDL_INTC_VECTOR_TXI1 i Start of next data transfer PDL_INTC_VECTOR_TEI1 End of data transfer PDL_INTC_VECTOR_ERI2 Error in data received PDL_INTC_VECTOR_RXI2 SCI channel 2 Data received PDL_INTC_VECTOR_TXI2 Start of next data transfer PDL_INTC_VECTOR_TEI2 End of data transfer PDL_INTC_VECTOR_ERI3 Error in data received PDL_INTC_VECTOR_RXI3 Data received PDL_INTC_VECTOR T
18. e abe to be written to the channel 0 output register Ignored if the channel is not selected data3 The value to be written to the channel 1 output register Ignored if the channel is not selected Return value True if all parameters are valid otherwise false Category DAC Reference R_DAC_10_Create Remarks Refer to the data alignment that was selected when R_DAC_10_Create was called Program example RPDL definitions include r_pdl_dac_10 h RPDL device specific definitions include r_pdl_definitions h void func void Write new data to DAC channel 0 R_DAC_10_Write PDL _DAC_10_CHANNEL_0 100 0 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 155 2tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 Usage Examples This chapter shows programming examples for each driver in this library R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 1 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 1 Interrupt control Figure 5 1 shows an example of external interrupt use Pin IRQO A is used to detect a falling edge and generates an interrupt Pin IRQ1 B is used to detect a falling edge and is polled Pin IRQ2 A is used to detect a low level signal and generates an
19. PDL ADC 10 0 ON or PDL_ADC_10_0 OFF Start or stop ADC unit 0 conversion PDL ADC 10 1 ONor PDL ADC_10_1_OFF Start or stop ADC unit 1 conversion PDL ADC 10 2 ONor PDL_ADC 10 2 OFF Start or stop ADC unit 2 conversion PDL ADC 10 3 ONor PDL_ADC 10 3 OFF Start or stop ADC unit 3 conversion e Control the CPU during the ADC conversion The default setting is shown in bold PDL_ADC_10_CPU_ON or Allow the CPU to run normally during the conversion Stop the CPU when the conversion starts PORDE CIO a The CPU will re start when any valid interrupt occurs True if all parameters are valid and exclusive otherwise false ADC R_ADC_10_Create R_ADC_10 Read Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 151 Use this API function only when the software trigger option is selected For single or one cycle scan modes the ADC will stop automatically when the conversion is complete The time delay between starting conversions on multiple units is minimised but has to use separate instructions This function minimises the delay between starts by using an interrupt to prevent other interrupts from occurring during the start sequence If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up For true simultaneous starting of ADC units select an appropriate hardware trigge
20. R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 31 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 2 5 MCU operation 1 R_MCU_Control Synopsis Control the operation of the MCU Prototype bool R_MCU_Control uint8_tdata Control options Description Modify the MCU control registers data Select the operation states If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults On chip ROM control PDL_MCU_ROM_ENABLE or PDL_MCU_ROM_DISABLE Enable or disable the on chip ROM e On chip RAM control PDL_MCU_RAM_ENABLE or PDL_MCU_RAM_DISABLE Enable or disable the on chip RAM Return value True if a valid register is specified otherwise false Functionality MCU registers References R_MCU_GetStatus Remarks None Program example RPDL definitions include r_pdl_mcu h RPDL device specific definitions tinclude r_pdl_definitions h void func void Modify the MCU operation R_MCU_Control PDL_MCU_ROM_DISABLE y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 32 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary vers
21. R_DTC_Set PDL_DTC_ADDRESS_FULL dtc_vector_table Set up a DTC channel for IIC transmission R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_PLUS PDL_DTC_DESTINATION_ADDR PDL C_SIZE_8 PDL_DTC_IRQ COMPLETE PDL_DTC_TRIGGER_ICTXI1 _D _D _ D1 2D R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 39 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples dtc_iicl_ tx transfer _data eeprom_data_array_l uint8_t RIIC1 ICDRI 6 PDL_NO_DATA Set up a DTC channel for IIC reception R_DTC_Create PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_ FIXED PDL_DTC_DESTINATION_ADDRESS PLUS PDL_DTC_SIZE 8 PDL_DTC_IRO_ COMPLETE PDL_DTC_TRIGGER_ICRXI1 dtc_iicl_rx transfer_data uint8_t RIIC1 ICDRR data_storage 4 PDL_NO_DATA Y Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 1 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 0 0 0 0 100E3 300 lt lt 16 200 Y Enable the DTC R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Y Write the data into the EEPROM write _eeprom_data Prepare the next data for the EEPROM R_DTC_Con
22. 4 Library Reference Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 R_BSC_Control Synopsis Modify the External Bus Controller operation Prototype bool R_BSC_Control uint8_t data Area selection Description Provide interrupt flag clearing data e Error clearing PDL_BSC_ERROR_CLEAR Clear the bus error signals This will also clear the interrupt flag Return value True if all parameters are valid otherwise false Category Bus Controller Reference R_BSC_Create R_BSC_Destroy Remarks This function can be called from the error handling function see R_BSC_ Create Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Clear the bus error signals R_BSC_Control PDL_BSC_ERROR_CLEAR y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 47 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 5 R_BSC_GetStatus Synopsis Read the External Bus Controller status flags Prototype bool R_BSC_GetStatus uint8_t data A pointer to the data storage location
23. CMT channel 1 interrupt PDL_DMAC_REQUEST_CMT2 or CMT channel 2 interrupt PDL_DMAC_REQUEST_CMTS3 or CMT channel 3 interrupt PDL_DMAC_REQUEST_IRQO or External pin IRQO interrupt PDL_DMAC_REQUEST_IRQ1 or External pin IRQ1 interrupt PDL_DMAC_REQUEST_IRQ2 or External pin IRQ2 interrupt PDL_DMAC_REQUEST_IRQS3 or External pin IRQ3 interrupt PDL_DMAC_REQUEST_ADCO or ADC unit 0 interrupt PDL_DMAC_REQUEST_ADC1 or ADC unit 1 interrupt PDL_DMAC_REQUEST_ADC2 or ADC unit 2 interrupt PDL_DMAC_REQUEST_ADC3 or ADC unit 3 interrupt PDL_DMAC_REQUEST_TPUO or TPU channel 0 interrupt PDL_DMAC_REQUEST_TPU1 or TPU channel 1 interrupt PDL_DMAC_REQUEST_TPU2 or TPU channel 2 interrupt PDL_DMAC_REQUEST_TPU3 or TPU channel 3 interrupt PDL_DMAC_REQUEST_TPU4 or TPU channel 4 interrupt PDL_DMAC_REQUEST_TPU5 or TPU channel 5 interrupt PDL_DMAC_REQUEST_TPU6 or TPU channel 6 interrupt PDL_DMAC_REQUEST_TPU7 or TPU channel 7 interrupt PDL_DMAC_REQUEST_TPU8 or TPU channel 8 interrupt PDL_DMAC_REQUEST_TPU9 or TPU channel 9 interrupt PDL_DMAC_REQUEST_TPU10 or TPU channel 10 interrupt PDL_DMAC_REQUEST_TPU11 or TPU channel 11 interrupt PDL_DMAC_REQUEST_SCIO_RX or SCI channel O data received interrupt PDL_DMAC_REQUEST_SCIO_TX or SCI channel 0 data transmitted interrupt PDL_DMAC_REQUEST_SCHM_RXor
24. ENESAS Under development Preliminary Specification RX610 Group 4 R_INTC_ControlExtinterrupt Synopsis Prototype Description Return value Category Reference Remarks External interrupt control bool R_INTC_ControlExtinterrupt Pin selection uint8_t data1 uint16 tdata2 Control data1 Choose the interrupt pin to be configured Specifications in this preliminary version are subject to change 4 Library Reference Enables or disables the specified external interrupt PDL_INTC_IRQn n 0 to 15 or PDL_INTC_NMI IRQi n 0 to 15 interrupt pin or NMI interrupt pin data2 Select the controls If multiple selections are required use to separate each selection e Enable or disable the interrupt pin for the IRQ pins PDL_INTC_ENABLE or PDL_INTC_DISABLE Enable or disable the IRQn interrupt pin e Detection sense selection for the IRQ pins PDL_INTC_LOW or Low level detection PDL_INTC_FALLING or Falling edge detection PDL_INTC_RISING or Rising edge detection PDL_INTC_BOTH Falling and rising edge detection e Interrupt request clearing PDL_INTC_CLEAR_IR_FLAG Clear the Interrupt Request flag This is not required if e Acallback function has been specified e The interrupt priority level is higher than 0 e The processor inte
25. Page 4 140 This function must only be used to terminate a Read process that has used the DMAC or DTC Use R_IIC_GetStatus to determine if the transfer was successful RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t data_array 5 void func void Read 1 byte on channel 1 and stop R_IIC_MasterReceiveLast 1 amp data_array 4 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 6 R_IIC_SlaveMonitor Synopsis Prototype Description Monitor the bus bool R_IIC_SlaveMonitor uint8_t data1 Channel selection uint16_t data2 Channel configuration uint8_t data3 Receive data start address uint16_tdata4 Receive threshold void func Callback function uint8_t datad Interrupt priority level Monitor the bus until an address match occurs and store any data received Register the storage area and transfer method for data received on the selected I2C channel data1 Select channel IICn where n 0 or 1 data2 Select the operation options The default setting is shown in bold Specify PDL_NO_DATA to use the default e DMAC DTC trigger control PDL_IIC_RX_DMAC_DTC_TRIGGER_DISABLE or PDL_IIC_RX_DMAC_TRIGGER_ENABLE or PDL_IIC_
26. R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 127 2tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 2 R_CRC_Destroy Synopsis Shut down the CRC calculator Prototype bool R_CRC_Destroy void No parameter is required Description Put the CRC calculator into the Power down state with minimal power consumption Return value True Category CRC Reference R_CRC_Create Remarks None Program example RPDL definitions include r_pdl_crc h RPDL device specific definitions include r_pdl_definitions h void func void Shut down the CRC R_CRC_Destroy R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 128 2tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 3 R_CRC Write Synopsis Write data into the CRC calculation register Prototype bool R_CRC_Write uint8_t data The data to be used for the calculation Description Write the data into the data input register data The data to be written into the register Return value True Category CRC Reference R_CRC_Create Remarks e None Program example RPDL definitions include r
27. R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 19 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples Figure 5 10 Example of Compare Match Timer use R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 20 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 5 8 8 bit Timer 1 Periodic operation Timer channel 0 is configured to provide pulses on pin TMOO with a pulse width of 500us and an on time of 200us Peripheral driver function prototypes include r_pdl_tmr h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void main void Initialise the system clocks R_CGC_Set 12 5E6 10056 50E6 2556 PDL_CGC_BCLK_DISABLE y Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Configure TMRO for 500us pulse width 200us on time R_TMR_CreatePeriodic PDL_TMR_TMRO PDL_TMR_PERIOD PDL_TMR_OUTPUT_ON 500E 6 200E 6 PDL_NO_FUNC PDL_NO_FUNC 0 di The same operation using frequency and duty cycle R_TMR_CreatePeriodic PDL_TMR_TMRO _TMR_FREQUENCY PDL_TMR_OUTPUT_ON L_NO_FUNC L_NO_FUNC
28. Remarks bool R_PPG_Destroy Output pin selection Disable the pulse output on the selected pins Output pin selection 4 Library Reference PDL_PPG_POO PDL_PPG_PO1 PDL_PPG_PO2 Group 0 PDL_PPG_PO3 PDL_PPG_PO4 PDL_PPG_PO5 PDL_PPG_PO6 Group 1 PDL_PPG_PO7 PDL_PPG_PO8 PDL_PPG_PO9 PDL_PPG_PO10 Group 2 PDL_PPG_PO11 PDL PPG PO12 PDL_PPG_PO13 PDL_PPG_PO14 Group 3 PDL_PPG_PO15 Unit O PDL_PPG_PO16 PDL_PPG_PO17 PDL_PPG_PO18 Group 4 PDL_PPG_PO19 PDL_PPG_PO20 PDL_PPG_PO21 PDL_PPG_PO22 Group 5 PDL_PPG_PO23 PDL_PPG_PO24 PDL_PPG_PO25 PDL_PPG_PO26 Group 6 PDL_PPG_PO27 PDL_PPG_PO28 PDL_PPG_PO29 PDL_PPG_PO30 Group 7 PDL_PPG_PO31 Unit 1 R_PPG_Create True if the unit selection is valid otherwise false Programmable Pulse Generator If all the outputs in a unit become disabled that unit will be put into the stop state to reduce power consumption R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 81 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example include r_pdl_ppg h void func void Disable outputs PO24 and PO26 R_PPG_Destroy PDL_PPG_P
29. func2 The function to be called at the periodic interval Use PDL_NO_FUNC if not required ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Description 2 2 data5 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for both parameters func1and func2 Return value Category Reference Remarks True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_Destroy Function R_CGC_Set must be called before any use of this function This function is an alternative to R_TMR_CreateChannel and R_TMR_CreateUnit If an output pin TMOn is enabled this function will disable other output functions on that pin If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function use in 86 The timing limits depend on the peripheral module clock PCLK frcik MHz Equation 50 12 5 8 1 Timer resolution 20ns 80ns 125ns f PCLK 2 Periodmin a 40ns 160ns 250ns PCLK 2 Periodmax_cHANNEL 41 9ms 167 7ms 262ms Trog 92 Periodmax_unit 10 7s 42 9s 67 1s Frerk Widthmin Periodmin Widthmax_cHaNNneL Periodmax_CHANNEL Widthmax_unit
30. r_pdl_tmr h RPDL device specific definitions tinclude r_pdl_definitions h void func void Change timer TMR1 to 600ns period 100ns pulse width R_TMR_ControlPeriodic PDL_TMR_TMR1 PDL_TMR_PERIOD 600E 9 100E 9 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 100 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 9 R_TMR_ReadChannel Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 101 Read from timer channel registers bool R_TMR_ReadChannel uint8_t data1 Channel selection uint8_t data2 A pointer to the data storage location uint8_t data3 A pointer to the data storage location uint8_t data4 A pointer to the data storage location uint8_t data5 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 1 2 or 3 data2 The status flags shall be stored in the format below The flag will be set to 1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read b7 b3 b2 bi bO Overflow Compare match B Compare match A da
31. 10 bit Digital to Analog converter R_DAC_10 Create Configure the 10 bit DAC module R_DAC_10 Destroy Disable a DAC channel O0 N A OM N O 0MO J D NM A O N A O N DO 0O BA O ND O N 0O A O N R_DAC_10 Write Write data to a DAC channel R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 2 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 2 Description of Each API This section describes each API and explains how to use them showing a program example for each The description of each API is divided into the following items Synopsis Summarises processing by the API function Prototype The function format and a brief explanation of the arguments Description Explains how to use the API function and shows assignable parameters separating each argument with argument Return value Describes the returned value of the API function Category Indicates the category of the API function Reference Indicates the API functions to be referred Remark Describes notes to use the API function Program example Represents how to use the API function by a program example Two examples of return value checking are shown below RPDL definitions include r_pdl_pfc h include r_pdl_sci h RPD
32. ENESAS E 0 D 0 lt 5 C v Renesas Peripheral Driver Library User s Manual O NO RX610 Group Release All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Technology Corp website http www renesas com Renesas Electronics www renesas com Rev 1 00 Jul 2010 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under
33. L_NO_PTR L_NO_PTR L_NO_DATA G G GU U GOG G UU transmission_completed false reception_completed false while 1 Any bus activity if transmission_completed true reception_completed true Read the status flags R_IIC_GetStatus SLAVE_CHANNEL status_flags PDL_NO_PTR PDL_NO_PTR transmission_completed true Which address was detected if status_flags 0x0001 0x0u Prepare the next data for the Master R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 46 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples R_DMAC_Control PDL_DMAC_3 PDL_DMAC_SUSPEND PDL_DMAC_ENABLE PDL_DMAC_UPDATE_SOURCE PDL_DMAC_UPDAT L_DMAC_CLEAR_DREQ L_NO_DATA L_NO_DATA else if status_flags 0x0002 0x0u Prepare the next data for the Master R_DMAC_Control PDL_DMAC_3 PDL_DMAC_SUSPEND PDL_DMAC_ENABLE L_DMAC_UPDATE_SOURCE PDL_DMAC_UPDAT L_DMAC_CLEAR_DREO L_NO_DATA ave_data_storage_l Bi p p pP D D D D L PD U D D D PDL_NO_DATA transmission_completed false else if reception_completed true Re
34. PDL_SCI_CLK_TMR For SCI5 select Timer output TMOO SCK5 is set to high impedance For SCI6 select Timer output TMO2 SCK6 is set to high impedance Data length PDL_SCI_8_BIT_LENGTH or PDL_SCI_7_BIT_LENGTH 8 or 7 bit data length Parity mode PDL_SCI_PARITY_NONE or PDL_SCI_PARITY_EVEN or PDL_SCI_PARITY_ODD No parity bit even parity bit or odd parity bit Stop bit length PDL_SCI_STOP_1 or PDL_SCI_STOP 2 One or two stop bits 00 Jul 23 2010 ENESAS Under development RX610 Group Preliminary Specification Specifications in this preliminary version are subject to change Description 2 3 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 116 4 Library Reference The option PDL_SCI_8N1 can be used to select 8 bit data length no parity and one stop bit Options which are available in Clock Synchronous mode e Data clock source selection PDL_SCI_CLK_INT_OUT or Select the On chip baud rate generator The SCKn pin outputs the bit clock PDL_SCI_CLK_EXT Input the clock to the SCKn pin Options which are available in Smart Card Interface mode e Base clock pulse cycle count PDL_SCI_BCP_32 or PDL_SCI_BCP_64 or PDL_SCI_BCP_93 or PDL_SCI_BCP_128 or PDL_SCI_BCP_186 or PDL_SCI_BCP_256 or PDL_SCI_BCP_372 or PDL_SCI_BCP_512 The number of base clock cycles in a 1 bit data transfer period Parity sele
35. Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 11 Assign handlers for the fixed vector interrupts bool R_INTC_CreateExceptionHandlers void func1 Callback function void func2 Callback function void func3 Callback function Register the user functions to be called by the fixed vector interrupts func1 The function to be called when a privileged instruction is detected while in user mode Specify PDL_NO_FUNC if no callback function is required func2 The function to be called when an undefined instruction is detected Specify PDL_NO_FUNC if no callback function is required func3 The function to be called when a floating point exception is detected Specify PDL_NO_FUNC if no callback function is required True if all parameters are valid and exclusive otherwise false Interrupt control Please see the notes on callback function use in 86 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Declaration of callback function void CallBackFunc void void func void Add a function to manage floating point errors R_INTC_CreateExceptionHandlers PDL_NO_FUNC PDL_NO_FUNC FloatingPointFunc Y
36. RX610 Group 5 Usage Examples Y Wait for 1 character to be received on channel 1 R_SCI_Receive 1 PDL_NO_DATA amp result 1 PDL_NO_FUNC PDL_NO_FUNC Y Check that channel 0 has completed do R_SCI_GetStatus 0 amp result PDL_NO_PTR PDL_NO_PTR while result amp 0x10 0 Shut down channel 0 R_SCI_Destroy 0 SCI channel 0 receive data handler void SCIORxFunc void char str_ptr rx_string while str_ptr 0 Process the string contents SCI channel 0 error handler void SCIOErrFunc void uint8_t error_flags Read the status R_SCI_Get Status 0 amp error_flags PDL_NO_PTR PDL_NO_PTR Y Overrun error if error_flags 0x20 System_failed Figure 5 14 Example of Asynchronous Reception code R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 24 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 2 Asynchronous Transmission Figure 5 15 shows the configuration of SCI channels 0 and 1 and the transmission of data on channel 0 using polling and then interrupts Peripheral driver function prototypes tinclude r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include
37. SCI channel 1 data received interrupt PDL_DMAC_REQUEST SCI1_TX or SCI channel 1 data transmitted interrupt PDL_DMAC_REQUEST_SCI2_RX or SCI channel 2 data received interrupt PDL_DMAC_REQUEST SCI2_TX or SCI channel 2 data transmitted interrupt PDL_DMAC_REQUEST_SCI3_RX or SCI channel 3 data received interrupt PDL_DMAC_REQUEST_SCI3_TX or SCI channel 3 data transmitted interrupt PDL_DMAC_REQUEST_SCI4_RX or SCI channel 4 data received interrupt PDL_DMAC_REQUEST _SCI4 TX or SCI channel 4 data transmitted interrupt PDL_DMAC_REQUEST_SCI5_RX or SCI channel 5 data received interrupt PDL_DMAC_REQUEST_SCI5_TX or SCI channel 5 data transmitted interrupt PDL_DMAC_REQUEST_SCI6_RX or SCI channel 6 data received interrupt PDL_DMAC_REQUEST SCI6 TX or SCI channel 6 data transmitted interrupt PDL_DMAC_REQUEST_IICO_TXor Il C channel 0 data transmitted interrupt PDL_DMAC_REQUEST_IICO_RXor Il C channel 0 data received interrupt PDL_DMAC_REQUEST_IIC1_TXor Il C channel 1 data transmitted interrupt PDL_DMAC_REQUEST_IIC1_RX I C channel 1 data received interrupt data4 The source start address ENESAS Under development Preliminary Specification RX610 Group Description 3 3 Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 0
38. TIOCBO TIOCAO Figure 5 9 Example of TPU operation R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 18 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 7 Compare Match Timer Figure 5 10 shows an example of Compare Match Timer usage One channel is used to generate interrupts at regular intervals Peripheral driver function prototypes include r_pdl_cmt h include r_pdl_cgc h include r_pdl_io_port h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function prototype void CMTO_handler void void main void Initialise the system clocks R_CGC_Set 12 556 100E6 50E6 25E6 PDL_CGC_BCLK_DISABLE Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Y Configure a port pin for output R_IO_PORT_Set DL_IO_PORT_3_6 DL_IO_PORT_OUTPUT 1 f Configure CMT channel 0 for 1kHz operation R_CMT_CreatePeriodic 0 DL_CMT_FREQUENCY E3 MTO_handler Change the frequency to 10kHz R_CMT_Control 0 PDL_CMT_FREQUENCY 10E3 void CMTO_handler void Invert the port pin R_IO_PORT_Modify PDL_IO_PORT_3_6 PDL_IO_PORT_XOR
39. e Counter stop re start PDL_TMR_STOP or PDL_TMR_START Disable or re enable the counter clock source The counter or compare registers to be modified PDL_TMR_COUNTER Update the timer counter register TCNT PDL_TMR_TIME_CONSTANT_A Update the timer compare match A register TCORA PDL_TMR_TIME_CONSTANT_B Update the timer compare match B register TCORB data3 The counter value This will be ignored if the register is not selected data4 The compare match A value This will be ignored if the register is not selected data5 The compare match B value This will be ignored if the register is not selected Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_CreateChannel R_TMR_ReadChannel Remarks None Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Load the counter on channel TMRO R_TMR_ControlChannel 0 PDL_TMR_COUNTER OxFF PDL_NO_DATA PDL_NO_DATA R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 96 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 7 R_TMR_ControlUnit Synopsis Write to timer unit registers Prototype bool
40. lf the requested period is not a multiple of the minimum period the actual time period will be more than the requested time period Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 107 RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Use CMT channel 0 for a lms pause R_CMT_CreateOneShot E r E 3 DL_NO_FUNC ombrool ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 3 R_CMT_Destroy Synopsis Disable a CMT unit Prototype bool R_CMT_Destroy uint8_tdata Unit selection Description Shut down a CMT unit data The timer unit n where n 0 or 1 Unit O comprises channels CMTO and CMT1 Unit 1 comprises channels CMT2 and CMT3 Return value True if the unit selection is valid otherwise false Category Compare Match Timer Reference R_CMT_Create Remarks The timer unit is put into the stop state to reduce power consumption Program example RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h void func void Shutdown channels 0 and 1 R_CMT_Destroy 0 R20UT0083EE0100 Rev 1 00 Jul 23 2010 P
41. while bus_busy true void iic_tx_dmac_end_handler void uint16_t status_flags 0 Wait for the transmission to complete do R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 37 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples R_IIC_GetStatus 1 amp status_flags PDL_NO_PTR PDL_NO_PTR 3 while status_flags amp 0x0080u 0x0u Issue a Stop condition on channel 1 R_IIC_Controli 1 PDL_IIC_STOP bus_busy false void iic_rx_dmac_end_handler void uint32_t DestAddr 0 Read the next destination address for the current transfer R_DMAC_GetStatus 2 PDL_NO_PTR PDL_NO_PTR amp DestAddr PDL_NO_PTR Read one more byte with NACK condition on channel 1 and stop R_IIC_MasterReceiveLast 1 uint8_t DestAddr bus_busy false Figure 5 25 An example of write data to and reading data from an EEPROM using two DMAC channels R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 38 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 11 3 Master mode with DTC In the following example data is written to an EEPROM in two bursts The DTC is used to handle the data transfer The same EEPROM address locations are
42. y void func void Clear I O port retention R_LPC_Control PDL_LPC_IO_RELEASE ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 3 R_LPC_WriteBackup Synopsis Write to the Backup registers Prototype bool R_LPC_WriteBackup uint8_t data1 Data pointer uint8_t data2 Data count Description Write data into the backup registers data1 The data to be written to the backup area data2 The number of bytes to be written to the backup area Valid from 1 to 32 Return value True if all parameters are valid otherwise false Functionality Low Power Consumption control registers References R_LPC_ReadBackup Remarks eric R_PDL_LPC_BACKUP_AREA_SIZE specifies the number of bytes that are available Program example RPDL definitions tinclude r_pdl_lpc h RPDL device specific definitions tinclude r_pdl_definitions h void func void uint8_t data_to_save R_PDL_LPC_BACKUP_AREA SIZE Write data into the backup registers R_LPC_WriteBackup data_to_save R_PDL_LPC_BACKUP_AREA_ SIZE R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 37 ENESAS Under development Preliminary Specification Specifications in this preliminary ve
43. 23 2010 RENESAS Page 2 14 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 15 Compare Match Timer Driver The driver functions support the use of the four 16 bit timers providing the following operations 1 Configuration for use including e Automatic clock setting using frequency or period as an input e Manual clock setting using register values as inputs e Automatic interrupt control 2 Configuration for use as a one shot timer 3 Disabling channels that are no longer required and enabling low power mode 4 Control of a timer including constant register updates 5 Control of a timer including change of frequency Note The Clock Generation Circuit must be configured before configuring any timer channel R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 15 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 16 Watchdog Timer Driver The driver functions support the use of the watchdog timer providing the following operations 4 Configuring the timer for use including Automatic clock setting using frequency or period as an input Internal timer mode Watchdog timer mode MCU reset generation while in watchdog timer mode Automatic interrupt control 5 Control of the timer including e Stopping the timer e Counter refresh
44. Data Transfer Controller oooonnconcccnnnnnninnnnnnncconcnnncccnnccnrrrccn cr 5 15 A RS A eh een a Desa aces ox vata Ses ta aceasta AEAT aces AEAEE ATE AAPEEE AEA 5 17 5 7 Compares Match TM usos 5 19 A ie Airis eee eel ead ea Suis ohne dnd acter Al dei ee aaa 5 21 5 9 Serial Communication Interface ccsccccecceceeeeeeeeeeeeeeceeeeeaaaesseneeseaeeesaaeeseaeeseeeeeseaeeesaeeneneessaees 5 23 5 40 GRO calcular aia 5 29 51i eC Bus INtentace sti o A dl co 5 30 Sia Master MOOG ciutat alta ida 5 30 1 Configuration and transmission oonmicnnccnnnnnnnnnnncnnccnnnrccnn crac nr 5 31 2 Recopa did 5 33 3 Repeated Startinio onte aater ean at a 5 34 5 11 2 Master mode with DMAC ooonncccnnnccnnnncconcccconccnonncnn noc n cnn cc narran ran rre 5 35 5 11 3 Master mode with DTC ooonninnnnnnnnccnnnccnnncnnncncnannconarccn nn nan cnn 5 39 DATA Slave Mode tacita taras 5 43 5 11 5 Slave mode with DMAC ccccceesseceeeeeceeeeeeaeeeceeeeceaeeeeaaeeeeaeeseaeeecaaeessaaeeseaeeseaeeeesaeeseeeeseneeeas 5 45 5 12 Analog to Digital Converter sacs ik ete thn ation ee tial ed ect aie eens 5 50 AX Specific Note Siriane a aaia eel a nee hited li ha eee 6 1 6 1 Interrupts and processor MORE eesriie ieee eenei k innne EnEn KEEA ARREK EAR RKA REENA EEEa ELARA EE 6 1 6 2 Interrupts and DSP iNStrUCtIONS ooooonnnnncnnnnnnnnccnnnccnnccnnanccnnrn cnn rca rn rara rra 6 1 REVISION HIStory ico cc A A dd ct 1 Under dev
45. P P OO U OO Ooo y Suspend transfers on all enabled channels R_DMAC_Control DL_DMAC_ALL L_DMAC_SUSPEND L_NO_DATA L_NO_PTR L_NO_PTR L_NO_DATA L_NO_PTR L_NO_PTR L_NO_DATA ao ao A wy ty O G G O G ee ENESAS 4 Library Reference Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 4 R_DMAC_GetStatus Synopsis Prototype Description Return value Check the status of a DMA channel bool R_DMAC_GetStatus uint8_t data1 Channel selection uint16_t data2 Status flags pointer uint32_t data3 Current source address pointer uint32_t data4 Current destination address pointer uint32_t data5 Current transfer byte count pointer Return status flags and current channel registers data1 The channel number n where n 0 to 3 data2 The status flags shall be stored in the following format Specify PDL_NO_PTR if the flags are not to be read b15 b9 b8 0 0 Idle 1 Transfer End interrupt request set b7 b6 b5 b4 b3 b2 b1 bO Ch 0 Ch 1 Ch 2 Ch 3 Ch 0 Ch 1 Ch 2 Ch 3 0 Transfer end not detected 0 Data transfer is not in progress 1 Transfer end detected 1 Data transfer in progress data3 Where the current source address shall
46. TIOCAn initial output low toggles at compare match TIOCAn initial output high goes low at compare match TIOCAn output high TIOCAn initial output high toggles at compare match PDL_TPU_A_IC_RISING EDGE or PDL_TPU_A_IC_FALLING_EDGE or PDL_TPU_A_IC_BOTH_EDGES or Input capture at TIOCAn rising edge Input capture at TIOCAn falling edge Input capture at TIOCAn both edges PDL_TPU_A_IC_TPU_COUNT_CLK or Input capture at TPU n 1 count clock count up or count down Invalid if TPU n 1 uses PCLK 1 Valid for n 0 3 6 and 9 PDL_TPU_A_IC_TPU_CM_IC Input capture at TPU n 1 TGRA compare match or input compare Valid for n 1 4 7 and 10 e TIOCAn input capture pin selection PDL_TPU_A_IC_SHARED or PDL_TPU_A_IC_SEPARATE Input capture is shared with output compare or uses the adjacent pin e Input capture output compare control for register TGRB PDL_TPU_B_OC DISABLED or PDL_TPU_B_OC LOW or PDL_TPU_B_ OC _LOW_CM HIGH or PDL_TPU_B_OC_LOW_CM_INV or PDL_TPU_B_OC_HIGH_CM_LOW or PDL_TPU_B_OC_HIGH or PDL_TPU_B_OC_HIGH_CM_INV or TIOCBn output disabled TIOCBn output low TIOCBn initial output low goes high at compare match TIOCBn initial output low toggles at compare match TIOCBn initial output high goes low at compare match TIOCBn output high TIOCBn initial output high toggles at compare match PDL_TPU_B_IC_RISING EDGE or PDL_TPU
47. r_pdl_definitions h Callback function prototype void SCIOTxFunc void volatile char result 2 void main void Put a null at the end result 1 0 Initialise the system clocks R_CGC_Set 12 5E6 100E6 50E6 25E6 PDL_CGC_BCLK_DISABLE Y Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Set up SCI channel 0 Async 8N1 38400 baud R_SCI_Create 0 PDL_SCI_ASYNC PDL_SCI_8N1 38400 0 y Set up SCI channel 1 Async 8N1 19200 baud R_SCI_Create 1 PDL_SCI_ASYNC PDL_SCI_8N1 19200 0 y Wait for 1 character to be received on channel 1 R_SCI_Receive 1 PDL_NO_DATA result 1 PDL_NO_FUNC PDL_NO_FUNC y Send a string on channel 0 wait for completion R_SCI_Send R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 25 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 0 PDL_NO_DATA Renesas RX 0 PDL_NO_FUNC Send another string on channel 0 R_SCI_Send 0 PDL_NO_DATA www renesas com 0 SCIOTxFunc Echo the character on channel 1 R_SCI_Send 1 PDL_NO_DATA result 0 PDL_NO_FUNC SCI channel 0 transmit complete handler void SCIOTxFunc void Shut down channel
48. uint16_t data10 void func1 void func2 void func3 void func4 uint8_t data11 void func5 void func6 uint8_t data12 Set up a 16 bit TPU channel data1 The channel number n where n 0 to 11 data2 Configure the channel mode If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Operation mode Channel selection Configuration selection Configuration selection Configuration selection Configuration selection Register value Register value Register value Register value Register value Callback function Callback function Callback function Callback function Interrupt priority level Callback function Callback function Interrupt priority level 4 Library Reference PDL_TPU_MODE_NORMAL or Normal operation PDL_TPU_MODE_PWM1 or PDL_TPU_MODE_PWM2 or Pulse Width Modulation PWM mode 1 or 2 PDL_TPU_MODE_PHASE1 or PDL_TPU_MODE_PHASE2 or PDL_TPU_MODE_PHASE3 or PDL_TPU_MODE_PHASE4 Phase counting mode 1 2 3 or 4 Valid for n 1 2 4 5 7 8 10 and 11 Synchronous mode PDL_TPU_SYNC_DISABLE or PDL_TPU_SYNC_ENABLE Disable or enable synchronous operation DMAC and or DTC trigger control for TGRA PDL_TPU_TGRA_DMAC_DTC_TRIGGER_DISABLE or PDL_TPU_TGRA_DMAC_TRIGGER_ENABLE or PDL_TPU_T
49. 3 ADTRG3 input pin valid for unit 3 only PDL_ADC_10_TRIGGER_TPU0_CM A signal from TPU channel 0 Unit 0 compare match input capture A Unit 1 compare match input capture B Unit 2 compare match input capture C Unit 3 compare match input capture D Data alignment selection PDL_ADC_10_DATA_ALIGNMENT_LEFT or PDL_ADC_10_DATA_ALIGNMENT_RIGHT The alignment of the 10 bit ADC conversion result within the 16 bit storage area Left padded at the MSB end Right aligned to the LSB end e DMAC DTC trigger control PDL_ADC_10 DTC TRIGGER ENABLE PDL_ADC_10_DMAC_DTC_TRIGGER_DISABLE or PDL_ADC_10_DMAC_TRIGGER_ENABLE or Disable or enable activation of the DMAC or DTC when a conversion or scan cycle completes e Sampling time calculation PDL_ADC_10_ADSSTR_CALCULATE or PDL_ADC_10_ADSSTR_SPECIFY Select whether parameter data4 is used to calculate the ADSSTR value or contains the value to be stored in register ADSSTR data3 The desired frequency of the conversion clock ADCLK in Hertz data4 The data to be used for the sampling state register value calculations Data use The timer period in seconds or The value to be put in register ADSSTR func Parameter type float uint8_t The function to be called when the ADC conversion or scan cycle is complete Specify PDL_NO_FUNC if no callback function is required data5 The interrupt priori
50. 5 Differences between Products Before changing from one product to another i e to one with a different part number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different part numbers implement a system evaluation test for each of the products Table of Contents Table of Contents cui a A adi lo pi 1 1 Te INTO CU CTO AAA IAE aa a a date as A ARIES daa 1 1 1 1 Using the library within yOUr Project essetis eeure kaa e EnaA EEKE REEE eE CEE RE EEKE EUERE ERNE EEN KERESERE 1 2 1 1 1 Unzip the RPDE MIES Guitar rca Daa aia aa a aa Add 1 2 1 1 2 Copy the files into your project area ooocncicnnininncccnnnccnnoccnnccnnnnrcnarcnn arrancar 1 2 1 1 3 Include the new directory oooooccconnnncconnonacccnn canon narran 1 4 1 1 4 Include the new source files oooonoconcconinicinncncncccconccnnnccnnnncnn nono c crac 1 5 1 1 5 Avoid conflicts with standard project files 02 ceeeeececeneeeeeeeeeeeeeceeeeeseaeeeseaeeseeeesaeeesaaeeeeneeeaas 1 6 1 FROIMOVEA ii A E E E S 1 6 2 EXCIUSION EE aia 1 7 1 1 62 Add the library fle Pati ida a aislada das 1 8 VA Build the Project uii nai As 1 8 1 2 Document StructurO centralita dat la iria 1 9 1 3 Acronyms and abbreviations senises erisin ieii iia cnn narrar 1 10 a E 2 1 Aer O
51. Configure the Watchdog timer R_WDT_Control Control the Watchdog operation R_WDT_Read Read the Watchdog timer status and registers R_SCI_Create SCI channel setup Serial R_SCI_Destroy Shut down a SCI channel eae R_SCI_Send Send a string of characters Communication R_SCI_Receive Receive a string of characters Interface R_SCI_Control Control the SCI channel R_SCI_GetStatus Check the status of a SCI channel CRC calculator R_CRC_Create Configure the CRC calculator R_CRC_Desitroy Shut down the CRC calculator 12C bus interface R_CRC Write Write data into the CRC calculation register R_CRC_Read Read the CRC calculation result R_IIC_Create 12 channel setup R_IIC_Destroy Disable an C channel R_IIC_MasterSend Write data to a slave device R_IIC_MasterReceive Read data from a slave device R_IIC_MasterReceiveLast Complete a DMAC or DTC based read process R_IIC_SlaveMonitor Monitor the bus and receive data from a master R_IIC_SlaveSend Write data to a master device R_IIC_Control 12C channel control R_IIC_GetStatus Read the status for an 12C channel 10 bit Analog to Digital converter R_ADC_10 Create Configure an ADC unit R_ADC_10_ Destroy Shut down an ADC unit R_ADC_10_Control Start or stop an ADC unit R_ADC_10_Read Read the ADC conversion results
52. DISABLE Disable the output of the A12 signal PDL_BSC_A13_DISABLE Disable the output of the A13 signal PDL_BSC_A14 DISABLE Disable the output of the A14 signal PDL_BSC_A15_ DISABLE Disable the output of the A15 signal PDL_BSC_A16_DISABLE Disable the output of the A16 signal PDL_BSC_A17 DISABLE Disable the output of the A17 signal PDL_BSC_A18_DISABLE Disable the output of the A18 signal PDL_BSC_A19_ DISABLE Disable the output of the A19 signal PDL_BSC_A20_DISABLE Disable the output of the A20 signal PDL_BSC_A21_DISABLE Disable the output of the A21 signal PDL_BSC_A22 DISABLE Disable the output of the A22 signal PDL_BSC_A23 DISABLE Disable the output of the A23 signal data3 Error monitoring PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE or Enable or disable illegal address PDL_BSC_ERROR_ILLEGAL_ADDRESS DISABLE access detection PDL_BSC_ERROR_TIME_OUT_ENABLE or Enable or disable time out PDL_BSC_ERROR_TIME_OUT_DISABLE detection func The function to be called when a bus error occurs Specify PDL_NO_FUNC if not required data4 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid and exclu
53. Destination start address uint16_t data5 Transfer count uint8_t data6 Block size Description Modify the operation of the Data Transfer Controller data1 Control the operation e Stop Start control PDL_DTC_START or PDL DTC_STOP Enable re enable or suspend all DTC transfers e The registers to be modified using the selected parameters PDL_DTC_UPDATE_SOURCE The Source Address register using parameter data3 PDL_DTC_UPDATE_DESTINATION The Transfer Address register using parameter data4 PDL_DTC_UPDATE_COUNT The Transfer Count register using parameter data5 PDL_DTC_UPDATE_BLOCK_SIZE The Block Size register using parameter data6 Transfer trigger control After being triggered the DTC will ignore further interrupts from that trigger source Specify the trigger used in the relevant call of R_DTC_Create if you require the interrupt to trigger another transfer data2 The start address of the transfer data area the same as that declared in R_DTC_Create Ignored if no registers are to be modified data3 The source start address The valid range depends on the address mode short or full data4 The destination start address The valid range depends on the address mode short or full data5 The number of transfers to take place For normal or block mode valid between 0 and 65535 0 65536 transfers For repeat mode valid between 0 an
54. Detection control PDL_IIC_NTALD_DISABLE or Disable or enable arbitration to be lost when an ACK is PDL_IIC_NTALD_ENABLE detection during transmission of a NACK in receive mode e Slave Arbitration Lost Detection control PDL_IIC_SALD_DISABLE or Disable or enable arbitration to be lost when a mismatch PDL_IIC_SALD_ENABLE occurs during slave data transmission e Slave address detection control PDL_IIC_SLAVE_0 DISABLE or Disable or enable detection of slave address 0 in PDL_IIC_SLAVE_0_ENABLE_7 or 7 bit or PDL_IIC_SLAVE_0 ENABLE 10 10 bit format PDL_IIC_ SLAVE _1_DISABLE or Disable or enable detection of slave address 1 in PDL_IIC_SLAVE_1_ENABLE_7 or 7 bit or PDL_IIC_SLAVE 1 ENABLE 10 10 bit format PDL_IIC_SLAVE_2 DISABLE or Disable or enable detection of slave address 2 in PDL_IIC_SLAVE_2 ENABLE_7 or 7 bit or PDL_IIC_SLAVE 2 ENABLE 10 10 bit format PDL_IIC_SLAVE_GCA_DISABLE or Disable or enable detection of the General Call PDL_IIC_SLAVE_GCA_ENABLE address e Device ID detection control PDL_IIC_DEVICE_ID_DISABLE or Disable or enable detection of the Device ID address PDL_IIC_DEVICE_ID_ ENABLE 1111 100b e Host Address detection control PDL_IIC_HOST_ADDRESS_DISABLE or Disable or enable detection of the SMBus host PDL_IIC_HOST_ADDRESS_ENABLE address data4 Slave address 0 Ignored if slave address 0 detection is disabled data5 Slave address 1 Igno
55. OR or Exclusive OR PDL_IO_PORT_XOR O to be used for the modification Between 0x00 and OxFF for a port O or 1 for a pin Return value True if the parameters are valid otherwise false Functionality I O port References R_IO_PORT_Set R_IO_PORT_Read R_IO_PORT_Write Remarks If an invalid port or pin is specified the operation of the function cannot be guaranteed Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions tinclude r_pdl_definitions h void func void Invert port pin P05 R_IO_PORT_Modify PDL_IO_PORT_0_5 PDL_IO_PORT_XOR 1 i And the value port 6 with 0x55 R_IO_PORT_Modify PDL_IO_PORT_6 PDL _IO_PORT_AND 0x55 di R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 27 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 8 R_IO_PORT Wait Synopsis Wait for a match on an I O port Prototype bool R_IO_PORT_Wait uint16_t data1 Output port or port pin selection uint8_t data2 Comparison value Description Loop until an I O port or I O port pin matches the comparison value data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition
56. PDL_DAC 10 CHANNEL 1 Enable channel 1 e Data alignment selection The alignment of the 10 bit output data within the 16 bit PDL_DAC_10_ALIGN_LEFT or parameters data2 and data3 PDL_DAC_10_ALIGN_RIGHT Left padded at the MSB end Right aligned to the LSB end data2 The value to be written to the channel 0 output register Ignored if the channel is not enabled data3 The value to be written to the channel 1 output register Ignored if the channel is not enabled True if all parameters are valid and exclusive otherwise false DAC R_DAC_10_Destroy R_DAC_10_Write e This function configures the relevant pin for DAC operation The port control settings for any DAC pins that subsequently become inactive are not modified e This function brings the converter module out of the power down state RPDL definitions tinclude r_pdl_dac_10 h RPDL device specific definitions tinclude r_pdl_definitions h void func void Set up DAC channel 0 with default operation mid voltage R_DAC_10_Create PDL_DAC_10_CHANNEL_0O 1024 2 0 ENESAS Under development RX610 Group Preliminary Specification Specifications in this preliminary version are subject to change 2 R_DAC_10_ Destroy Synopsis Disable a DAC channel Prototype bool R_DAC_10_Destroy uint8 tdata Channel selection Description Disable the channel outp
57. PDL_NO_PTR PDL_NO_DATA DMAC2_transfer_end_handler 7 Enable channel 2 R_DMAC_Control PDL_DMAC_2 PDL_DMAC_ENABL PDL_NO_DATA PDL_NO_PTR PDL_NO_PTR PDL_NO_DAT PDL_NO PTR PDL_NO PTR PDL_NO DATA Y 5 Usage Examples Initiate reception triggering the DMAC when data is received R_SCI_Receive 1 PDL_SCI_DMAC_TRIGG PDL_NO_PTR PDL_NO_DATA PDL_NO_FUNC PDL_NO_FUNC Y void DMAC2_transfer_end _handler void Disable channel 2 R_DMAC_Control PDL_DMAC_2 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 13 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples PDL_DMAC_SUSP1 PDL_NO_DAT PDL_NO_PT PDL_NO_PT PDL_NO_DAT PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA Figure 5 6 An example of using the DMAC for serial port reception R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 14 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 5 Data Transfer Controller Figure 5 8 shows an example of Data Transfer Controller usage Peripheral driver function prototypes include r_pdl_dtc h include r_pdl_cgc h include r_pdl_io_port h include r_pdl_i
58. Re designed the use of fast 0 20 Feb 25 2010 interrupts Re designed the SCI control to match the restrictions in the control of TE and RE bits 0 21 Mar 04 2010 Updates to ADC and IIC descriptions 0 22 Mar 26 2010 Added support for the 176 pin package Separated DMAC and DTC control Finished IIC 1 1 Changed the company name 4 68 Corrected the TGRC and TGRD trigger options 4 120 Added a remark about avoiding combining interrupts and DMAC DTC triggering 4 124 Removed the comment that Mark is the default 0 23 Apr 06 2010 4 128 Corrected the category 4 129 Corrected the example code 4 130 Corrected the example code 5 12 Added SCI_Stop call in DMAC callback 5 27 Added C usage examples 4 72 Updated the PFC function call in remark 2 0 24 Apr 26 2010 4 142 Added a note that the byte count is reset if the data loops back 5 26 Added an example of synchronous reception and transmission 3 1 Added the device group 4 6 Added the DDR register to the remarks 4 20 Re designed the parameter list 4 21 Re designed the parameter list 4 53 Separated the Enable and Suspend control Added access to the current address and count registers Added Transfer Request flag control 4 60 Removed level valid for IRQn 4 64 Added register parameters 026 Jun 11 2010 4 66 Added the block size parameter 4 75 Changed two channel references to unit 4 115 Removed the reference to reading the counter value 4 118 Added a remark for SCK5 4 12
59. Start of next data transfer PDL_DTC_TRIGGER_RXI3 Data received SCI channel 3 PDL_DTC_TRIGGER_TXI3 Start of next data transfer PDL_DTC_TRIGGER_RXI4 Data received PDL_DTC_TRIGGER_TXI4 SCl channel 4 Start of next data transfer PDL_DTC_TRIGGER_RXI5 SCI channel 5 Data received PDL_DTC_TRIGGER_TXI5 i Start of next data transfer PDL_DTC_TRIGGER_RXI6 SCI channel 6 Data received PDL_DTC_TRIGGER_TXI6 Start of next data transfer PDL_DTC_TRIGGER_ICRXIO 12C bus interface Data received PDL_DTC_TRIGGER_ICTXIO channel 0 Start of next data transfer PDL_DTC_TRIGGER_ICRXI1 12C bus interface Data received PDL_DTC_TRIGGER_ICTXI1 channel 1 Start of next data transfer data2 The start address of the transfer data area It must be a multiple of 4 For short address mode 12 bytes are required to store the transfer data For full address mode 16 bytes are required data3 The source start address The valid range depends on the address mode short or full data4 The destination start address The valid range depends on the address mode short or full data5 The number of transfers to take place For normal or block mode valid between 0 and 65535 0 65536 transfers For repeat mode valid between 0 and 255 0 256 transfers data6 The block size for each transfer Valid between 0 and 255 0 256 units Ignored in normal or repeat mode True if all parameters are
60. an 4 15 7 ROINTO Wie cti id ttt vinden bites dz ica aan 4 16 8 RAINT MOGI aeiia a kiana ea ARE AE a A dE 4 17 423 WO PO ed e do o o ad be iL Bd aM Pe a 4 18 1 RAOLPOR E Set Aviso ot ete A A a e he eet e 4 20 2 R 1O PORT ReadContrO Lit ia di 4 21 3 RUO PORT Modify CONTO licita ia dd ic 4 22 4 RJO PORT Rd tt ida de dl ido Pahioo dotada pcia 4 24 5 RIO PORTAN E sti titi 4 25 6 RJO PORT COMDATE tit diia 4 26 7 PAR PORT Modyo menee it a aa a e 4 27 8 RUO PORT Walt ar nt tilda 4 28 4 2 4 Port Function Control i aetate enade ta ld dad ant 4 29 1 ROPERO Ad eiae a a a e a e A 4 29 2 PERE Ge WIE ti e e add in tad 4 30 3 PEC MOAN tata ta dt diia 4 31 4 25 MGU Operation ascitis ita 4 32 1 RA MCU Control tias taba aii 4 32 2 REMCUSGEtSalUS a locas 4 33 4 2 6 Low Power Consumption oococcncccnnnnncnnncccnonccnnnrn nono n crac cnn 4 34 1 Ra LRE Create erie those aia 4 34 2 REP Ge Controla a a tias 4 36 3 REEPO WriteBackUD E ria arrasa 4 37 4 RELPC REAU BACKUP nicas lidia can dd dada Lido ld is 4 38 5 ROEPCGelStalls acta coer esate eet cede rarae case cess a aaar adaa idear ees 4 39 4 2 7 Bus Controle tess ci a a a aE aaa e aa ede 4 40 1 R amp A BS C Create ieciesticsiieck ecect a ici bdvestecieesas 4 40 2 REBSGCreateAreass iec ciicccsssihesescs aiea a a a 4 43 3 Re BSC DESNO arais a EE EEA E casadbenedasiesasausbcan ta cuueny Getexansceddseadaaeadveadcneeenl dee 4 46 4 RUBSOS CONTO vias id A E E AI
61. bytes value Specify PDL_NO_DATA if not required data7 The source address reload value Specify PDL_NO_PTR if not required data8 The destination address reload value Specify PDL_NO_PTR if not required data9 The number of bytes reload value Specify PDL_NO_DATA if not required Return value True if all parameters are valid and exclusive otherwise false Category DMA controller Reference R_DMAC_ Create Remarks The Software trigger control is valid only if the Software trigger option has been selected e This function must be called in order to start the DMAC The Suspend operation is executed at the start of this function The Enable operation is executed at the end Therefore both options can be selected together with other control changes in one function call R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 54 ztENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group Program example RPDL definitions include r_pdl_dmac h RPDI L device specific definitions include r_pdl_definitions h void func void Enable transfers on channel 2 R_DMAC_Control D L_DMAC_2 DMAC_ENABLE L_NO_ L_NO_ L NO PT PT DATA R R R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 55 L_NO_DATA L_NO_PTR L_NO_PTR L_NO_DATA P P P P P P P
62. capture compare match Co ntdirection detection detection detection 0 Counter counts down 3 Y i s A 1 Counter counts up data3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the general register A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where the general register B value shall be stored Specify PDL_NO_PTR if it is not required data6 Where the general register C value shall be stored Specify PDL_NO_PTR if it is not required data7 Where the general register D value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Timer Pulse Unit R_TPU_Create Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 77 Ifthe flags are read any detection flag that has been set to 1 shall be automatically cleared to O by this function ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_tpu h RPDL device specific definitions tinclude r_pdl_definitions h uint8_t Flags uint General_A uintl General_D L6_t L6_t void func void Read the status flags and registers A and D for channel TPUO R_TPU_Re
63. clock PCLK a P fpcik MHz Parameter Limit Equation 50 125 32 8 Conversion clock Minimum froik 8 4 2 1 24 0 6 25 MHz 6 25 MHz 4 0 MHz 4 0 MHz ADCLK Maximum frcLk 50 00 MHz 12 50 MHz 32 00 MHz 8 00 MHz ee Maximum 4 0us 4 0us 6 25us 6 25us Conversion time Minimum FS AUR N 0 5us 2us 0 78ius 3 13us Sampling time Minimum 0 5us ping Maximum 255 ADCLK e g 5 1us at 50 MHz Total ae Conversion time conversi n time Minimum sampling time 1 0us 2 5us 1 28us 3 63us Program example RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h ADC unit 1 callback function void ADC1IntFunc void void func void Set up ADC 1 at 50 MHz in single mode using AN1 with 0 6us sampling time R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 149 R_ADC_10_Create 1 PDL_ADC_10_CHANNELS_OPTION_2 50E6 0 6E 6 ADClIntFunc 2 i Set up ADC 1 at 50 MHz in single mode using AN1 R_ADC_10_Create 1 PDL_ADC_10_CHANNELS_OPTION_2 PDL_ADC_10_ADSSTR_SPECIFY 50E6 0x40 ADC1IntFunc 2 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 2 R_ADC_10_ Destroy Synopsis Protot
64. if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuit
65. in two bursts DMAC channel 2 is used to handle the data transfer Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_cmt h include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h static void write_eeprom_data void static void read_eeprom_data void void iic_tx_dmac_end_handler void void iic_rx_dmac_end_handler void define EEPROM_MEMORY_ADDRESS_UPPER 0x00 define EEPROM_MEMORY_ADDRESS_LOWER 0x00 define EEPROM_ADDRESS 0x00A0 EEPROM_MEMORY_ADDRESS_UPPER volatile uint8_t bus_busy volatile uint8_t data_storage 20 void main void const uint8_t eeprom_data_array_1 EEPROM _MEMORY_ADDRESS_LOWER 0x01 0x02 0x03 0x04 0x05 const uint8_t eeprom_data_array_2 EEPROM_MEMORY_ADDRESS_LOWER 5 0x06 0x07 0x08 0x09 Ox0A 0x0B Ox0C 0x0D 0x0E 0x0F uint8_t 1 Configure the clocks R_CGC_Set 12 5E6 100E6 50E6 PDL_NO_DATA PDL_CGC_BCLK_DISABLE Set up a DMAC channel for IIC transmission R_DMAC_Create 3 PDL_DMAC_SINGLE PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_REQUEST_11C1_TX eeprom_data_array_l uint8_t amp RIIC1 ICDRT 6 PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA lic_tx_dmac_end_handler 7 y
66. instructions i DSP MACHI MACLO MULHI MULLO MVTACHI MVTACLO and RACW ii Multiply and multiply and accumulate EMUL EMULU FMUL MUL and RMPA The accumulator ACC register is not pushed onto the stack by the API interrupt handlers If DSP instructions are being utilised in the users code callback functions which are called by the API interrupt handlers should either a Avoid using instructions which modify the ACC register b Take acopy of the ACC register and restore it before exiting the callback function R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Page 6 1 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group Revision History Revision History RX610 Group User s Manual Description Rev Date Page Summary 0 13 Nov 24 2009 First edition issued 0 14 Dec 02 2009 Issued with WS 3C driver source 0 15 Dec 11 2009 Updated with feedback from RSO 0 16 Dec 16 2009 Created a single I O pin definitions table 0 17 Dec 23 2009 Added DTC and PPG functions 0 18 Jan 08 2010 Corrected errors updated IIC and PPG functions exe Feb 03 2010 Synchronised with some of the changes in the hardware manual Updated IIC Added MCU Added LPC Updated DTC Standardised the declaration for prototypes with unknown types Re wrote the installation guide Added general definitions
67. not important data5 Configuration options The default setting is shown in bold BCLK pin output control PDL_CGC_BCLK_ENABLE or Output the external bus clock signal on pin BCLK PDL_CGC_BCLK_DISABLE or leave the BCLK pin as an input PDL_CGC_BCLK_HIGH or fix the BCLK pin high Return value True if all parameters are valid and exclusive otherwise false For RX610 the following rules shall be checked e Main clock oscillator frequency 8 to 14 MHz e ficix 8 to 100 MHz e freix 8 to 50 MHz e fecix 8 to 25 MHz e fictk 2 fecik and ficik 2 fecik e ficik froik and fecix are achievable main clock oscillator x 8 1 2 4 or 8 Functionality Clock generation circuit References None Remarks e This function must be called before configuring clock dependent modules e This function modifies the BCLK pin for input or output R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 4 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_cgc h RPDL device specific definitions include r_pdl_definitions h void func void Configure operation using a 12 5 MHz input clock ICLK 100 MHz PCLK 50 MHz BCLK 25 MHz R_CGC_Set 12 5E6 100E6 50E6 25E6 PDL_CGC_BCLK_EN
68. on channel n n 0 to 3 PDL_INTC_VECTOR_IRQO PDL_INTC_VECTOR_IRQ1 PDL_INTC_VECTOR_IRQ2 PDL_INTC_VECTOR_IRQ3 PDL_INTC_VECTOR_IRQ4 PDL_INTC_VECTOR_IRQ5 PDL_INTC_VECTOR_IRQ6 PDL_INTC_VECTOR_IRQ7 PDL_INTC_VECTOR_IRQ8 PDL_INTC_VECTOR_IRQ9 PDL_INTC_VECTOR_IRQ10 PDL_INTC_VECTOR_IRQ11 PDL_INTC_VECTOR_IRQ12 PDL_INTC_VECTOR_IRQ13 PDL_INTC_VECTOR_IRQ14 PDL_INTC_VECTOR_IRQ15 External interrupt pin Valid edge or level detected on pin IRQn n 0 to 15 PDL_INTC_VECTOR_WOVI Watchdog timer Overflow PDL_INTC_VECTOR_ADIO PDL_INTC_VECTOR_ADI1 PDL_INTC_VECTOR ADI2 PDL_INTC_VECTOR_ADI3 Analog to Digital converter Conversion completed on unit n n 0 to 3 PDL_INTC_VECTOR_TGIOA PDL_INTC_VECTOR_TGIOB PDL_INTC_VECTOR_TGIOC PDL_INTC_VECTOR_TGIOD PDL_INTC_VECTOR_TCIOV Timer Pulse Unit channel 0 Input capture or compare match A Input capture or compare match B Input capture or compare match C Input capture or compare match D Overflow PDL_INTC_VECTOR_TGI1A PDL_INTC_VECTOR_TGI1B PDL_INTC_VECTOR_TCI1V PDL_INTC_VECTOR_TCI1U Timer Pulse Unit channel 1 Input capture or compare match A Input capture or compare match B Overflow Underflow PDL_INTC_VECTOR_TGI2A PDL_INTC_VECTOR_TGI2B PDL_INTC_VECTOR TCI2V PDL_INTC_VECTOR_TCI2
69. polling mode The TXI and TEND flags will be used to manage the data transmission If the SCI channel s control registers are directly modified by the user this function may lock up The maximum number of characters to be transmitted is 65535 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed e If reception is enabled and receive errors occur transmission will be blocked until the errors are cleared ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions tinclude r_pdl_definitions h void func void uint8_t data_store 100 Send a string on channel 2 R_SCI_Send 2 PDL_NO_DATA Renesas RX 0 PDL_NO_FUNC Send 50 bytes of binary data on channel 1 R_SCI_Send 2 PDL_NO_DATA data_store 50 PDL_NO_FUNC R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 120 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 4 R_SCI_Receive Synopsis Prototype Description Receive data on a SCI cha
70. registers Programmable Pulse Generator R_PPG_Create Configure a PPG group R_PPG_Destroy Disable a PPG unit WIN A VINI f On B G PO BH Co PO OT BY CO PO 01 BY CO PO PO CO PO CO N OD O01 RB Co PO 100 N or AON IL R_PPG_Control Control a PPG group R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 1 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change nner Group 4 Library Reference 1 R_TMR_CreateChannel Configure a TMR timer channel 2 R_TMR_CreateUnit Configure a TMR timer unit 3 R_TMR_CreatePeriodic Select periodic operation 4 R_TMR_CreateOneShot Configure and use a one shot timer serio 5 R_TMR_Destroy Disable a TMR timer unit S bit Timer 6 R_TMR_ControlChannel Write to timer channel registers 7 R_TMR_ControlUnit Write to timer unit registers 8 R_TMR_ControlPeriodic Control periodic operation 9 R_TMR_ReadChannel Read from timer channel registers 10 R_TMR_ReadUnit Read from timer unit registers Compare Match Timer R_CMT_Create Configure a CMT channel R_CMT_CreateOneShot Configure a CMT channel as a one shot event R_CMT_Destroy Disable a CMT unit R_CMT_Control Control CMT operation R_CMT_Read Read CMT channel status and registers Watchdog Timer R_WDT_Create
71. selection 4 Library Reference Channel selection Configuration selection Trigger selection Source start address Destination start address Transfer byte count Source reload address Destination reload address Transfer byte count reload value Callback function Interrupt priority level PDL_DMAC_SINGLE or PDL_DMAC_CONSECUTIVE or PDL_DMAC_NON_STOP Single operand consecutive operand or non stop transfers Address direction selection PDL_DMAC_SOURCE_ ADDRESS FIXED or Leave the address unchanged PDL_DMAC_SOURCE ADDRESS PLUS or Increment the address PDL_DMAC_ SOURCE ADDRESS MINUS or Decrement the address PDL_DMAC_SOURCE_ADDRESS_ROTATE Increment the address and return to the start address when a single operand transfer is completed PDL_DMAC_DESTINATION_ADDRESS FIXED or Leave the address unchanged PDL_DMAC_DESTINATION ADDRESS PLUS or Increment the address PDL_DMAC_DESTINATION_ADDRESS_MINUS or Decrement the address PDL_DMAC_DESTINATION_ADDRESS_ ROTATE Increment the address and return to the start address when a single operand transfer is completed Transfer data size PDL_DMAC _SIZE_8 or PDL_DMAC_SIZE_16 or PDL_DMAC_ SIZE 32 Select 8 16 or 32 bits for the data to be transferred Operand transfer data count appli cable only for single operand transfers PDL_DMAC_COUNT_1 or PD
72. the buffer is big enough for the requested number of values e If no callback function is used this function waits for the ADI flag to indicate that conversion is complete before reading the results If the ADC unit s control registers are directly modified by the user this function may lock up RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void uint16_t ADCresult 2 Read the ADC values for unit 2 R_ADC_10_Read 2 ADCresult 3 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 4 2 19 10 bit Digital to Analog Converter 1 R_DAC 10 Create Synopsis Prototype Description Return value Functionality References Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 153 Configure the 10 bit DAC module bool R_DAC_10_Create uint8_t data1 Configuration uint16_tdata2 Output value uint16_tdata3 Output value Enable the DAC module and set the operating conditions data1 Configuration options To set multiple options at the same time use to separate each value The default settings are shown in bold e Channel enable PDL_DAC_10 CHANNEL 0 Enable channel 0
73. then read out in two bursts The DTC is used to handle the data transfer Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_cmt h include r_pdl_dtc h RPDL device specific definitions include r_pdl_definitions h static void write_eeprom_data void static void read_eeprom_data void void iic_tx_dmac_end_handler void void iic_rx_dmac_end_handler void define EEPROM_MEMORY_ADDRESS_UPPER 0x00 define EEPROM_MEMORY_ADDRESS_LOWER 0x00 define EEPROM_ADDRESS 0x00A0 EEPROM_MEMORY_ADDRESS_UPPER volatile uint8_t bus_busy volatile uint8_t data_storage 20 Reserve an area for the DTC vector table pragma address dtc_vector_table 0x00001000 uint32_t dtc_vector_table 256 Reserve 16 bytes full address mode for the transfer data areas uint32_t dtc_iicl_tx_transfer_data 4 uint32_t dtc_iicl_rx_transfer_data 4 void main void const uint8_t eeprom_data_array_1 EEPROM _MEMORY_ADDRESS_LOWER 0x01 0x02 0x03 0x04 0x05 const uint8_t eeprom_data_array_2 EEPROM_MEMORY_ADDRESS_LOWER 5 0x06 0x07 0x08 0x09 Ox0A Ox0B Ox0C Ox0D Ox0E Ox0F uint8_t i Configure the clocks R_CGC_Set 12 5E6 100E6 50E6 PDL_NO_DATA PDL_CGC_BCLK_DISABLE Configure the DTC controller
74. this preliminary version are subject to change 4 Library Reference 5 R_DTC_GetStatus Synopsis Prototype Description Return value Category Reference Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 66 Check the status of the Data Transfer Controller bool R_DTC_GetSiatus uint32_t data1 Transfer data start address uint8_t data2 Status flags pointer uint32_t data3 Current source address pointer uint32_t data4 Current destination address pointer uint16_t data5 Current transfer count pointer uint8_t data6 Current block size count pointer Return status flags and current channel registers data1 The start address of the transfer data area Ignored if parameters data3 data4 and data5 are all PDL_NO_PTR data2 The status flags shall be stored in the following format Specify PDL_NO_PTR if the status flags are not required b7 b1 bO 0 0 Normal 1 ADTC transfer stop request is generated data3 Where the current source address shall be stored Specify PDL_NO_PTR if it is not required data4 Where the current destination address shall be stored Specify PDL_NO_PTR if it is not required data5 Where the current transfer count shall be stored Specify PDL_NO_PTR if it is not required data6 Where the current block size count shall be stored Specify PDL_NO_PTR if it is not requi
75. to 9 data2 The value read from the register True if a valid register is specified otherwise false PFC reg isters R_PFC_Write None RPDI L definit ions include r_pdl_pfc h RPDI L device specific definitions include r_pdl_definitions h void func void uint8_t data Get th R_PFC_Read ly amp data R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 29 value of register PFC1 ENESAS 4 Library Reference Pointer to the variable where the PFC register s value shall be stored Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 2 R_PFC_Write Synopsis Write to a PFC register Prototype bool R_PFC_Write uint8_t data1 PFC register selection uint8_t data2 Data to be written to the PFC register Description Write the value to a PFC register data1 Any value from 0 to 9 data2 The value to be written to the register Return value True if a valid register is specified otherwise false Functionality PFC registers References R_PFC_Read R_PFC_Modify Remarks pi PFC registers are modified by other driver functions Take care to not overwrite existing settings Program example RPDL definitions include r_pd
76. to the data storage location uint16_t data4 A pointer to the data storage location uint16_t data5 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The unit number n where n 0 or 1 data2 The status flags shall be stored in the format below A flag will be set to 1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read The unit 0 status flags shall be stored in the format b7 b6 b5 b4 b3 b2 b1 bO TMRO TMR1 0 Compare Compare 0 Compare Compare Overflow match B match A OVENI match B match A The unit 1 status flags shall be stored in the format b7 b6 b5 b4 b3 b2 b1 bO TMR2 TMR3 0 Compare Compare 0 Compare Compare Oveitlow match B match A Overflow match B match A data3 Where the counter value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the compare match A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where the compare match B value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_CreateUnit R_TMR_ControlUnit Ifthe status flags are read any flag that has been set to 1 shall be automatically cleared to O by this function ENESAS Under development Preliminary Specification Speci
77. until the callback function has completed The timing limits depend on the frequency of the peripheral module clock PCLK Period ie or Frequency frax Frcrk nx256 Where n 4 64 128 512 2048 8192 32768 or 131072 Examples for different values of fecix are given below frcik MHz 50 12 5 32 8 Periodpcik 4 20 5 us 81 9 us 32 0 us 128 us PeriodrcLk 64 328 us 1 31 ms 512 0 us 2 05 ms Periodpcik 128 655 us 2 62 ms 1 02 ms 4 10 ms Periodpcik 512 2 62 ms 10 5 ms 4 10 ms 16 4 ms Periodpck 2048 10 5 ms 41 9 ms 16 4 ms 65 5 ms Periodrcik 8192 41 9 ms 168 ms 65 5 ms 262 ms PeriodpcLk 32768 168 ms 671 ms 262 ms 1 05s PeriodrcLk 131072 671 ms 2 68 s 1 05 s 4 19s frcLk 4 48 8 kHz 12 2 kHz 31 3 kHz 7 81 kHz rcLk 64 3 05 kHz 763 Hz 1 95 kHz 488 Hz frcLk 128 1 53 kHz 381 Hz 977 Hz 244 Hz rcLk 512 381 Hz 95 4 Hz 244 Hz 61 0 Hz PcLk 2048 95 4 Hz 23 8 Hz 61 0 Hz 15 3 Hz frcLk 8192 23 8 Hz 5 96 Hz 15 3 Hz 3 81 Hz fPcLk 32768 5 96 Hz 1 49 Hz 3 81 Hz 0 954 Hz PcLK 131072 1 49 Hz 0 373 Hz 0 954 Hz 0 238 Hz Program example RPDL definitions include r_pdl_wdt h RPDL device specific definitions tinclude r_pdl_definitions h void func void Configure the watchdog timer for PCLK 4 operation R_WDT_Create PDL_WDT_PCLK_DIV_4 WDT_handler 7 Y Configure the watchdog timer for PCLK 131072 operatio
78. valid and exclusive otherwise false Data Transfer Controller R_DTC_Set R_DTC_Control lf address increment or decrement is selected the address changes according to the number of bytes 1 2 or 4 in each transfer Call this function before configuring the peripherals that will be involved in the data transfer Call R_DTC_Set before calling this function e Call this function once for each peripheral that will trigger a transfer and for each chained transfer When all calls to this function are complete call R_DTC_Control to start the DTC ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 62 RPDI 4 Library Reference L definitions include r_pdl_dtc h RPDI L device specific definitions include r_pdl_definitions h Reserve 16 bytes full address mode for the CMTO triggered transfer data area Use a 32 bit type to make the address a multiple of 4 uint32_t dtc_cmt0O_transfer_data 4 void func void R_DTC_Create Configure the DTC for CMTO PDL_DTC_NORMAL PDL_DTC_SOURCE_ADDRESS_FIXED PDL_DTC_DESTINATION_ADDRESS_PLUS PDL_DTC_SIZE_8 PDL_DTC_TRIGGER_CMTO dtc_cmt0_transfer_data Ox0000AA00 0x0000BB0OO 100 0
79. value data5 The compare match A value data6 The compare match B value func1 The function to be called when an overflow occurs Use PDL_NO_FUNC if not required func2 The function to be called when a Compare match A occurs Use PDL_NO_FUNC if not required func3 The function to be called when a Compare match B occurs Use PDL_NO_FUNC if not required data7 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 func2 and func3 True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_Destroy R_TMR_ControlChannel R_TMR_ControlUnit R TMR_ReadChannel R_TM R_ReadUnit e If an input pin TMCIn or TMRIn is selected this function will configure the direction and input buffer control for that pin e If the output pin TMOn is made active this function will disable other output functions on that pin Aclosed clock loop will be created if The overflow signal from TMR1 is selected for TMRO and the compare match A signal from TMRO is selected for TMR1 or The overflow signal from TMR3 is selected for TMR2 and the compare match A signal from TMR2 is selected for TMR3 Either case should be avoided e If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function usage in 6 Acallback function is
80. void main void Initialise the system clocks R_CGC_Set 12 5E6 100E6 50E6 25E6 PDL_CGC_BCLK_DISABLI Y Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Y Select the B pins for TLCKA TCLKB TCLKC and TCLKD by setting bit TCLKS in register PFCR5 to 1 R_PFC_Modify 5 PDL_PFC_OR 0x08 Configure channel 0 for dual waveform A and B output R_TPU_Create 0 0 PDL_TPU_CLK_PCLK_DIV_1 PDL_TPU_CLEAR CM _B PDL_TPU_A_OC_LOW_CM_INV PDL_TPU_B_OC_HIGH_CM_ INV L_NO_FUNC L_NO_FUNC L_NO_FUNC L_NO_FUNC L_NO_FUNC L_NO_FUNC Y Read the status flags and resisters A and D for channel 0 R_TPU_Read 0 Flags PDL_NO_PTR amp General_A R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 17 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples PDL_NO_PT PDL_NO_PT amp General_D Y Modify channel 0 R_TPU_Control 0 PDL_TPU_COUNTER OxFFDD PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA Y Shutdown channels 0 to 5 R_TPU_Destroy 0 Y Figure 5 8 Example of Timer Pulse Unit use The counter is reset when it reaches 399 The 0 value is a valid state so the output toggle frequency is 50 MHz 400 i Counter value
81. 0 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 76 l ENESAS Under development Preliminary Specification RX610 Group 4 R_TPU_Read Synopsis Prototype Description Return value Category Reference Specifications in this preliminary version are subject to change 4 Library Reference Read from timer channel registers bool R_TPU_Read uint8_t data1 Channel selection uint8_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location uint16_t data4 Apointer to the data storage location uint16_t data5 A pointer to the data storage location uint16_t data6 A pointer to the data storage location uint16_t data7 A pointer to the data storage location Read any of the timer s counter compare or status flag registers data1 The channel number n where n 0 to 11 data2 The status flags shall be stored in the format below The input capture compare match flags A to D will be set to1 if the condition has been detected Specify PDL_NO_PTR if the flags are not to be read For n 0 3 60r9 b7 b6 b5 b4 b3 b2 b1 bO l Overflow Input capture compare match Count direction detection detection 0 Counter counts down i y D S a A 1 Counter counts up For n 1 2 4 5 7 8 100r 11 b7 b6 b5 b4 b3 b2 b1 bO E Underflow Overflow Input
82. 0 R_SCI_Destroy 0 Figure 5 15 Example of Asynchronous Transmission code R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 26 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 3 Synchronous Transmission and Reception Figure 5 16 shows the configuration of SCI channel 3 as the clock master followed by the simultaneous transmission and reception of data The Receive function call uses interrupts while the Transmit function uses polling Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function prototype void SCIB3RxFunc void volatile uint8_t data_received define BUFFER_SIZE 10 void main void uint8_t Tx _Data BUFFER_SIZE uint8_t Rx_Data BUFFER_SIZE uint8_t transfer_size 8 uint8_t 1 Configure the system clocks R_CGC_Set 12 5E6 100E6 50E6 PDL_NO_DATA PDL_CGC_BCLK_DISABLE Y Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Set up SCI channel 3 Sync MSb first 2 Mbps R_SCI_Create 3 PDL_SCI_SYNC PDL_SCI_MSB_FIRST 2E6 1 Load the required data into the transmit buf
83. 0 Jul 23 2010 Page 4 51 Specifications in this preliminary version are subject to change 4 Library Reference data5 The destination start address data6 The number of bytes to be transferred data7 The source reload address value This value is ignored if the reload function is disabled data8 The destination reload address value This value is ignored if the reload function is disabled data9 The number of bytes reload value This value is ignored if the reload function is disabled func The function to be called when a DMA transfer completes Specify PDL_NO_FUNC if not required data10 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false DMA controller R_DMAC_Destroy R_DMAC_Control R_DMAC_GetStatus e If another peripheral will be used to trigger a DMA transfer call this function before calling the Create function for the peripheral lf address increment or decrement is selected the address changes according to the transfer data size Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed RPDL definitions include r_pdl_dmac h RPDL device specific definitions include r_pdl_defi
84. 0 Rev 1 00 Jul 23 2010 Page 4 141 ENESAS Under development Preliminary Specification RX610 Group Specificat Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 142 1 1 VO VO ions in this preliminary version are subject to change 4 Library Reference If a callback function is specified interrupts are used Use R_IIC_GetStatus in the callback function to identify the activity that has occurred Please see the notes on callback function usage in 6 If no callback function is specified this function will read the status flags to monitor the bus activity Use R_IIC_GetStatus to identify the activity that has occurred If the 12C channel s control registers are directly modified by the user this function may lock up If the master sends more data than is expected and the DMAC DTC trigger is disabled this function will issue a NACK to the master When a Stop condition is detected if the DMAC or DTC is used for transferring data use R_DMAC_Control or R_DTC_Control to re set the address and count before the next transfer begins RPDL definitions nclude r_pdl_iic h RPDL device specific definitions nclude r_pdl_definitions h latile uint8_t data_array 5 id func void Monitor channel 0 using polling R_IIC_SlaveMonitor 0 PDL_NO_DATA data_array 5 PDL_NO_FUNC 0 ENESAS Under deve
85. 0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Page 1 1 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 1 Introduction 1 1 Using the library within your project The driver library can be used 1 Via the PDG graphical utility PDG can be downloaded from www renesas com pdg The directions for use of the PDG utility are given in the PDG manual 2 Or added to a project by the user and used stand alone To add the driver library to your project s build environment you need to Unzip the RPDL distribution Copy the required source header and library files into your project folder Include the required source files Add the driver library file to the linked files list Doga 1 1 1 Unzip the RPDL files Double click on the file RPDL_RX610 exe to unpack the files The default location is C Renesas RPDL_RX610 1 1 2 Copy the files into your project area Navigate to where the RPDL files were unpacked fm C Renesas RPDL_RX610 SEE a File Edit View Favorites Tools Help Q Back f S ya Search Key Folders EE Address C Renesas RPDL_RX610 A 5 Common File and Folder Tasks Device specific FS5 copy RPDL_RX610 bat Make a new folder MA oublich thicfaldanta 3 objects 4 My Computer v Double click on Copy_RPDL_RX610 bat to start the copy process cx C WINDOWS system32 cmd exe Renesas RPDL R amp 616 copy uti
86. 01 0 Disable IRQ1 R_INTC_ControlExtInterrupt PDL_INTC_IRO1 PDL_INT_DISABLE y Has IRQ2 triggered if irq2_low true Re enable the interrupt if the signal has returned to the high level R_IO_PORT_Compare L_IO_PORT_3_2 EnableIRQ2 void IRQOHandler void Process the IRQO event here the flag is cleared automatically switch_swl_pressed true void IRO2Handler void Disable the level triggered interrupt R_INTC_ControlExtInterrupt PDL_INTC_IRO2 PDL_INTC_DISABLI Y irq2_low true static void ReEnableIRQ2 void Re enable the interrupt and try to clear it R_INTC_ControlExtInterrupt PDL_INTC_IRO2 PDL_INTC_ENABLE PDL_INTC_CLEAR_IR_FLAG i Figure 5 1 Example of External Interrupt R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 3 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 2 I O Port Figure 5 2 shows examples of I O port configuration reading and writing Peripheral driver function prototypes include r_pdl_io_port h include r_pdl_pfc h RPDL device specific definitions include r_pdl_definitions h void main void uint8_t result Configure port 4 as an input R_IO_PORT_Set PDL_IO_PORT_4 PDL_IO_PORT_IN
87. 10 Group 5 Usage Examples 5 9 Serial Communication Interface 1 Asynchronous Reception Figure 5 14 shows the setting of SCI channels 0 and 1 and the reception of data using interrupts channel 0 and polling channel 1 Peripheral driver function prototypes include r_pdl_sci h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Callback function prototypes void System_failed void void System_reset void void SCIORxFunc void void SCIOErrFunc uint8_t volatile char rx_string 10 void main void uint8_t result Initialise the system clocks R_CGC_Set 12 5E6 100E6 50E6 25E6 PDL_CGC_BCLK_DISABLE Y Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Set up SCI channel 0 Async 8N1 38400 baud R_SCI_Create 0 PDL_SCI_ASYNC PDL_SCI_8N1 38400 1 y Set up SCI channel 1 Async 8N1 19200 baud R_SCI_Create 1 PDL_SCI_ASYNC PDL_SCI_8N1 19200 0 Start the interrupt based reception of 9 characters on channel 0 R_SCI_Receive 0 PDL_NO_DATA tring SCIORxFunc SCIOErrFunc R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 23 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change
88. 2 strlen char source_string_2 PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_FUNC 0 Enable the SW3 interrupt R_INTC_CreateExtInterruptAll PDL_INTC_IRQ3 PDL_INTC_FALLING PDL_INTC_B PDL_INTC_DMAC_TRIGG PDL_NO_FUNC 0 Enable channel 0 R_DMAC_Control PDL_DMAC_0 PDL_DMAC_ENABL PDL_NO_DATA PDL_NO_PTR PDL_NO_PTR P P P DL_NO_DAT DL_NO_PTR DL_NO_PTR PDL_NO_DA7 Enable and start channel 1 R_DMAC_Control PDL_DMAC_1 DL_DMAC_ENABLE PDL_DMAC_START PDL_NO_DATA PDL_NO_PTR PDL_NO_PTR PDL_NO_DA7 PDL_NO_PTR PDL_NO_PTR PDL_NO_DA7 Read the status for channel 0 R_DMAC_GetStatus 0 amp StatusValue amp SourceAddr amp DestAddr R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 9 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples amp ByteCount i void DMACO_transfer_end_handler void Invert the port pin R_IO_PORT_Modify PDL_IO_PORT_3_6 PDL_IO_PORT_XOR 1 Stop all channels R_DMAC_Control PDL_DMAC_ALL PDL_DMAC_SUSPEND PDL_NO_DATA PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA y Stop the DMAC R_DMAC_Destroy Figure 5 4 Two exampl
89. 4 Added GSM clock control options 4 139 Removed the Stop and Start control options 4 141 New function 4 142 Added TX DMAC DTC control 4 144 Removed TX DMAC DTC control 4 145 Added NACK control R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Revision History 1 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group Revision History Description Rev Date Page Summary 4 146 Added Transmission status bit 4 154 Removed the reference to right aligned limits 4 156 Removed the reference to right aligned limits 5 34 Added IIC with DMAC example 5 38 Added IIC with DTC example 1 5 Re generated the screen shots 4 80 Re named the overlap parameter 4 83 Moved the odd group next data settings to the upper nybble 4 91 Corrected one Description page number 4 130 Swapped the parameters 0 26 Jun 21 2010 4 133 Corrected one entry in the second timing table 4 142 Added a remark about re setting the DMAC or DTC after a Stop condition is detected 5 9 Updated the DMAC_ Control parameters 5 16 Updated the DTC_Control parameters 5 29 Updated the CRC_Read parameters 5 45 Added a usage example for Slave with DMAC 1 1 Added a note about required documents 4 59 Added the chain transfer trigger option 4 87 Corrected the TMRI pin assignment 4 91 Corrected the cross reference and modified the second remark 4 93 Updated the func parameter description 4 94 C
90. 5 PO14 PO13 PO12 PO19 PO18 PO 17 PO16 PO19 PO18 PO17 PO16 PO23 PO22 PO PO27 PO26 PO 21 PO20 PO23 PO22 PO21 PO20 25 PO24 PO27 PO26 PO25 PO24 NO0AG0DNnN 0 PO31 PO30 PO 29 PO28 PO31 PO30 PO29 PO28 Programmable Pulse Generator R_PPG_Control Remarks If more than one group must be True if all parameters are valid and exclusive otherwise false configured use multiple calls of this function The applicable PPG unit O or 1 is brought out of the stop state This function disables the alternative modes on each PO pin that is enabled Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 80 include v r_pdl_ppg h void func void Configure PPG outputs PO4 and PO6 group 1 R_PPG_Create PDL_PPG_PO4 PDL_PPG_PO6 PDL_PPG_TRIGGER_TPU2 0x15 Y ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 R_PPG_Destroy Synopsis Prototype Description Disable PPG outputs uint32_t data data Select the outputs to be disabled If multiple selections are required use to separate each selection Select only outputs within one group Return value Category Reference
91. 6 Port pin P7 PDL_IO_PORT_7_7 Port pin P77 PDL_IO PORT 8 0 Port pin P8o PDL_IO_PORT_8_1 Port pin P8 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 18 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference PDL IO PORT 8 2 Port pin P82 PDL_IO PORT_8 3 Port pin P83 PDL_IO_PORT_8 4 Port pin P8 PDL_IO_PORT_8_5 Port pin P85 PDL_IO PORT_8 6 Port pin P86 PDL_IO PORT_9 0 Port pin P9 PDL_IO_PORT_9 1 Port pin P9 PDL_IO_PORT_9 2 Port pin P92 PDL_IO PORT_9 3 Port pin P93 PDL_IO_PORT_9 4 Port pin P94 PDL_IO_PORT_9 5 Port pin P9s PDL_IO PORT_9 6 Port pin P9 PDL_IO_PORT_9 7 Port pin P97 PDL_IO PORT_A O Port pin PAo PDL_IO_PORT_A_1 Port pin PA PDL_IO_PORT_A_2 Port pin PA2 PDL_IO_PORT_A_3 Port pin PAs PDL IO PORT A 4 Port pin PA PDL_IO_PORT_A_5 Port pin PAs PDL_IO PORT_A 6 Port pin PAs PDL_IO_PORT_A 7 Port pin PA7 PDL_IO PORT_B_0 Port pin PBo PDL_IO_PORT_B_1 Port pin PB PDL IO PORT B2 Port pin PB2 PDL_IO PORT_B 3 Port pin PBs PDL IO PORT B4 Port pin PB PDL_IO PORT_B_5 Port pin PBs PDL_IO PORT_B_6 Port pin PBs PDL_IO_PORT_B 7 Port pin PB PDL_IO PORT_C_0 Port pin PCo PDL_IO_PORT_C_1 Port pin PC PDL_IO_PORT_C_2 Port p
92. ABLE R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 5 l ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 2 2 Interrupt Control Unit 1 R_INTC_CreateExtinterrupt Synopsis Configure an external interrupt pin Prototype bool R_INTC_CreateExtinterrupt uint8_t data1 Pin selection uint16_t data2 Configuration void func Callback function uint8_t data3 Interrupt priority level Description Sets the specified external interrupt data1 Choose the interrupt pin to be configured PDL_INTC_IRQn n 0 to 15 or IRQn n 0 to 15 interrupt pin or PDL_INTC_NMI NMI interrupt pin data2 Choose the pin settings If multiple selections are required use to separate each selection The default settings are shown in bold e Detection sense selection for the IRQ pins PDL_INTC_LOW or Select Low level PDL_INTC_FALLING or Falling edge PDL_INTC_RISING or Rising edge or PDL_INTC_BOTH Falling and rising edge detection Detection sense selection for the NMI pin PDL_INTC_FALLING or Falling or rising edge detection PDL_INTC_RISING 9 g eag i Alternate pin selection for the IRQ pins PDL_INTC_A or A ER PDL_INTC B Select the IRQn A or IRQn B pin to be used DMAC DTC trigger control Not enabled if low l
93. Build Debug Setup Tools Test Window Help Ded 4l izale rpdl_lib_test ajo SRA rpdl_lib_test C source file 4 dbsct c 2 Interrupt ADC_10 c Y e ss es ls ls ls Ls ls Ls os Ls os Ls Interrupt_BSC c 2 Interrupt_CMT c 2 Interrupt_DMAC c 2 Interrupt_INTC c 2 Interrupt_not_RPDL c 2 Interrupt_SCl c 2 Interrupt_TMR c 2 Interrupt_TPU c E Interrupt WDT c inpo C led c en sbrk c wecttbl c Dependencies iodefine h ee ra Ready R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 1 7 E Default1 desktop Z Figure 1 3 intprg c and vecttbl c have been excluded sia zS E S Oca Oca ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 1 Introduction 1 1 6 Add the library file path The library file is added to the list used by the linker application Use the key sequence Alt B R to open the RX Standard Toolchain window Select the Link Library tab From the Show entries for drop down menu select Library files Click on the Add button In the Add library file window enter the details as shown Add library file Relative to Project directory Cancel File path RPDL AX61 0_library Click on OK to close the window Click on OK to return to the main HEW window 1 1 7 Build the project No fu
94. C calculator These driver functions are used for controlling the calculator 17 C Bus Interface These driver functions are used for controlling the 12C bus channels 18 Analog to Digital Converter These driver functions are used for configuring the ADC units controlling the units and reading the conversion results 19 Digital to Analog converter These driver functions are used for configuring the DAC module and setting the output voltages R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Page 2 2 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 3 Clock Generation Circuit Driver The driver functions support the control of the internal clock generator providing the following operations 1 Configuration of the multiple clock outputs for system peripheral and external bus operation Note Configuring the Clock Generation Circuit also provides information on clock frequencies that will be used by the integrated drivers for other peripherals R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 3 RENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 2 Driver 2 4 Interrupt Control Driver The driver functions support the use of the interrupt controller providing the following operations 1 2 Configuration an external interrupt pin for us
95. CI channel data1 Select channel SCIn where n 0 to 6 data2 4 Library Reference Channel selection Channel configuration Bit rate or register value Interrupt priority level Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold e Operation mode PDL_SCI_ASYNC or PDL_SCI_SYNC or PDL_SCI_SMART Choose between Asynchronous Clock synchronous or Smart Card Interface operation Data transfer format PDL_SCI_LSB_FIRST or PDL_SCI_MSB_FIRST Select least or most significant bit first In 7 bit mode the format is fixed to LSB first Data inversion PDL_SCI_INVERSION_OFF or PDL_SCI_INVERSION_ON Control data inversion transmission and reception Transmit Receive connections PDL_SCI_TX_CONNECTED or PDL_SCI_TX_DISCONNECTED or The TXDn output is required not required PDL_SCI_RX_CONNECTED or PDL_SCI_RX_DISCONNECTED The RXDn input is required not required Options which are available in Asynchronous mode e Data clock source selection PDL_SCI_CLK_INT_IO or PDL_SCI_CLK_INT_OUT or Select the on chip baud rate generator The SCKn pin functions as an I O pin The SCKn pin outputs the bit clock PDL_SCI_CLK_EXT_DIV_8 or PDL_SCI_CLK_EXT_DIV_16 or Input a clock of 8 or 16 times the desired bit rate to the SCKn pin
96. CM_A_DTC_TRIGGER_ENABLE Disable or enable activation of the DTC when a Compare Match A occurs e Compare Match B DTC trigger control PDL_TMR_CM_B_DTC_TRIGGER_DISABLE or PDL_TMR_CM_B_DTC_TRIGGER_ENABLE Disable or enable activation of the DTC when a Compare Match B occurs ENESAS Under development Preliminary Specification RX610 Group Description 2 2 Return value Category Reference Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 85 Specifications in this preliminary version are subject to change 4 Library Reference data3 Configure the output control If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Output control for pin TMOn PDL_TMR_OUTPUT_IGNORE_CM_A or No change if a compare match A occurs PDL_TMR_OUTPUT_LOW_CM_A or 0 is output if a compare match A occurs PDL_TMR_OUTPUT_HIGH_CM_A or 1 is output if a compare match A occurs PDL_TMR_OUTPUT_INV_CM_A The output toggles if a compare match A occurs PDL_TMR_OUTPUT_IGNORE_CM_B or No change if a compare match B occurs PDL_TMR_OUTPUT_LOW_CM_B or 0 is output if a compare match B occurs PDL_TMR_OUTPUT_HIGH_CM_B or 1 is output if a compare match B occurs PDL_TMR_OUTPUT_INV_CM_B The output toggles if a compare match B occurs data4 The counter
97. CRCresult Y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 130 2tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 2 17 1 R_IIC_Create Synopsis Prototype Description 1 3 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 131 12C Bus Interface 12C channel setup bool R_IIC_Create uint8_t data1 uint32_t data2 uint32_t data3 uint16_t data4 uint16_t data5 uint16_t data6 uint32_t data7 uint32_t data8 Set up the selected C channel data1 Select channel IICn where n 0 or 1 data2 4 Library Reference Channel selection Channel configuration Detection configuration Slave address Slave address Slave address Transfer rate control Rise and fall time correction Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Bus mode selection PDL_IIC_MODE_IIC or PDL_IIC_MODE_IIC_FMP or PDL_IIC_MODE_SMBUS Choose between I2C Bus 12C Bus with Fast mode Plus for data rate gt 400 kbps or SMBus mode Internal reference clock PDL_IIC_INT_PCLK_DIV_1 or PDL_IIC_INT_PCLK_DIV_2 or PDL_IIC_INT_PCLK_DIV_4 or PDL_IIC_INT_PCLK_DIV_8 or PDL_IIC_INT_PCLK_DIV_16 or PDL_IIC_INT_PCLK_DIV_32 or PDL_IIC_INT_PCLK_DIV_64 or PDL_I
98. C_ERROR_TIME_OUT_ENABLE BusErrorFunc 5 i R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 42 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 2 R_BSC_CreateArea Synopsis Configure an external bus area Prototype bool R_BSC_CreateArea uint8_t data1 Area selection uint16_t data2 Configuration selection uint8_t data3 RRCV cycles uint8_t data4 WRCV cycles uint8_t data5 CSPRWAIT cycles uint8_t data6 CSPWWAIT cycles uint8_t data7 CSRWAIT cycles uint8_t data8 CSWWAIT cycles uint8_t data9 CSROFF cycles uint8_t data10 CSWOFF cycles uint8_t data11 WDOFF cycles uint8_t data12 RDON cycles uint8_t data13 WRON cycles uint8_t data14 WDON cycles uint8_t data15 CSON cycles Description 1 2 Set up an external bus area data1 The address area n where n 0 to 7 data2 Configure the operation of area CSn If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e External bus width PDL_BSC_WIDTH_16 or PDL_BSC WIDTH 8 Select 16 or 8 bit data bus width Endian mode PDL_BSC_ENDIAN_SAME or Set the bus endian mode to be the same or PDL_BSC_ENDIAN_OPPOSITE opp
99. ESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions tinclude r_pdl_definitions h void func void Terminate SCI reception on channel 0 R_SCI_Control 0 PDL SCI STOP RX R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 124 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 6 R_SCI_GetStatus Synopsis Check the status of a SCI channel Prototype bool R_SCI_GetStatus uint8_t data1 Channel selection uint8_t data2 Status flags uint8_t data3 Last byte received uint16_t data4 Bytes transmitted uint16_t data5 Bytes received Description Acquires the channel status and the byte counts data1 Select channel SCIn where n 0 to 6 data2 The status flags shall be stored in the format Asynchronous or Synchronous mode b7 to b6 b5 b4 b3 b2 b1 bO Reception error detection Transmit status RxD pin 0 Overrun Framing i Parity 0 Active 0 voltage level 0 No error 0 No error 0 No error 1 Comolete 0 Low 1 Detected 1 Detected 1 Dete
100. E_STANDBY or PDL_LPC_MODE _DEEP_SOFTWARE STANDBY PDL_LPC_MODE ALL MODULE_CLOCK_STOP or 4 Library Reference Select the mode to be entered e All module clock stop cancellation modification PDL_LPC_TMR_OFF or PDL_LPC_TMR_UNIT_0 or PDL_LPC_TMR_UNIT_1 or PDL_LPC_TMR BOTH Select whether the TMR units can be used to exit from All module clock stop mode 1 O port retention cancellation PDL_LPC_IO RELEASE Cancel the retention of I O port pin states Return value Functionality Low Power Consumption control registers References R_LPC_Create Remarks True if all parameters are valid and exclusive otherwise false Sleep mode is utilised by some peripheral drivers to turn off the CPU when required The peripheral Create functions bring modules out of the clock stop state as required The peripheral Destroy functions put modules into the clock stop state as required When All Module Clock Stop mode is cancelled the peripherals that were active when that mode was entered will be re activated Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 36 RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void Enter deep software standby mode R_LPC_Control PDL_LPC_MODE_DEEP_SOFTWARE_STANDBY
101. GGER_DISABLE or PDL_SCI_DMAC_TRIGGER_ENABLE or PDL_SCI_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a data byte is transmitted data3 The start address of the data to be sent If the DMAC or DTC shall be used to transfer the data specify PDL_NO_PTR data4 Set this to 0 if the transmit data is a character string ending with a null character For sending binary data set this to the number of bytes to be sent If the DMAC or DTC shall be used to transfer the data specify PDL_NO_DATA func The function to be called when the last byte has been sent Use R_SCI_Control to terminate this operation early R_SCI_GetStatus can be used to find out how many characters have been transmitted Specify PDL_NO_FUNC for this function to wait until the last byte has been sent True if all parameters are valid and the operation completed without errors False if a parameter was out of range or if the channel was already transmitting or if an error occurred during transmission SCI R_SCI_Create R_SCI_Control R_SCI_GetStatus The compiler adds a null character to the end of string constants If a callback function is specified transmission interrupts are used Please see the notes on callback function usage in 86 e If a callback function is specified avoid enabling activation of the DMAC or DTC for data transmission If no callback function func is specified this function will operate in
102. GRA_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a TGRA compare match occurs DTC trigger control for TGRB PDL_TPU_TGRB_DTC_TRIGGER_DISABLE or PDL_TPU_TGRB_DTC_TRIGGER_ENABLE Enable activation of the DTC when a TGRB compare match occurs DTC trigger control for TGRC valid for n 0 3 6 a nd 9 PDL_TPU_TGRC_DTC_TRIGGER_DISABLE or PDL_TPU_TGRC_DTC_TRIGGER_ENABLE Enable activation of the DTC when a TGRB compare match occurs ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change Description 2 5 4 Library Reference DTC trigger control for TGRD valid for n O 3 6 and 9 PDL_TPU_TGRD_DTC_TRIGGER_DISABLE or PDL_TPU_TGRD_DTC_TRIGGER_ENABLE Enable activation of the DTC when a TGRB compare match occurs data3 Configure the counter operation If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Counter clock source selection PDL_TPU_CLK_PCLK_DIV_1 or ity hie T k HOR The internal clock signal PCLK 1 4 16 or 64 PDL_TPU_CLK_PCLK_DIV_64 or PDL TPU CLK PCLK _DIV_256 or PCLK 256 Valid forn 1 3 5 7 9 and 11 PDL TPU CLK PCLK DIV_1024 or PCLK 1024 Valid for n 2 3 4 8 9 an
103. I O port References R_IO_PORT_Set Remarks e If an invalid port or pin is specified the operation of the function cannot be guaranteed Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void IoHandlerl void IoHandler2 void func void Call function IoHandlerl if port pin P05 is high R_IO_PORT_Compare PDL_TO_PORT_0_5 ly IoHandlerl i Call function IoHandler2 if port 6 reads as 0x55 R_IO_PORT_Compare PDL_IO_PORT_6 0x55 ToHandler2 i R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 26 ztENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 7 R_IO_PORT_Modify Synopsis Modify the pin states on an I O port Prototype bool R_IO_PORT_Modify uint16_tdata1 Output port or port pin selection uint8_t data2 Logical operation uint8_t data3 Modification value Description Read the output state of an I O port or I O port pin modify the result and write it back to the port data1 Use either one of the following definition values from 4 2 3 One port definition or e One port pin definition data2 e The logical operation to be applied to the port or port pin PDL_IO_PORT_AND or PDL_IO_PORT_OR or Select between AND amp
104. IC_INT_PCLK_DIV_128 The reference clock source used inside the 12 module e Timeout detection control PDL_IIC_TIMEOUT_DISABLE or PDL_IIC_TIMEOUT_LOW or PDL_IIC_TIMEOUT_HIGH or PDL_IIC_TIMEOUT_BOTH Disable timeout detection or enable for SCL stuck at a low level high level or both low and high level Timeout mode PDL_IIC_TIMEOUT_LONG or PDL_IIC_TIMEOUT_SHORT Select 16 bit long or 14 bit short mode e SDA output delay count PDL_IIC_SDA _DELAY_0 or PDL_IIC_SDA_DELAY_1 or PDL_IIC_SDA_DELAY_2 or PDL_IIC_SDA_DELAY_3 or PDL_IIC_SDA_DELAY_4 or PDL_IIC_SDA_DELAY_5 or PDL_IIC_SDA_DELAY_6 or PDL_IIC_SDA_DELAY_7 Select the number of cycles for the SDA output delay counter SDA output delay clock source PDL_IIC_SDA_DELAY_DIV_1 or PDL_IIC_SDA_DELAY_DIV_2 Select the clock source internal reference clock 1 or 2 for the SDA output delay counter ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Description 2 3 Noise filter control PDL_IIC_NF_DISABLE or PDL_IIC_NF_1 or PDL_IIC_NF_2 or Select the number of stages in the noise filter PDL_IIC_NF_3 or PDL_IIC_NF_4 data3 Detection settings Specify PDL_NO_DATA to use the defaults NACK Transmission Arbitration Lost
105. IGGER_TGI10B channel 10 Input capture or compare match B PDL_DTC_TRIGGER_TGI11A Timer Pulse Unit Input capture or compare match A PDL_DTC_TRIGGER_TGI11B channel 11 Input capture or compare match B PDL_DTC_TRIGGER_CMIAO 8 bit timer TMR Compare match A PDL_DTC_TRIGGER_CMIBO channel 0 Compare match B PDL_DTC_TRIGGER_CMIA1 8 bit timer TMR Compare matchA PDL_DTC_TRIGGER_CMIB1 channel 1 Compare match B PDL_DTC_TRIGGER_CMIA2 8 bit timer TMR Compare matchA PDL_DTC_TRIGGER_CMIB2 channel 2 Compare match B PDL_DTC_TRIGGER_CMIA3 8 bit timer TMR Compare matchA PDL_DTC_TRIGGER_CMIB3 channel 3 Compare match B PDL_DTC_TRIGGER_DMTENDO PDL_DTC_TRIGGER_DMTEND1 PDL_DTC_TRIGGER_DMTEND2 PDL_DTC_TRIGGER_DMTEND3 Direct memory access controller Transfer complete on channel n n 0 to 3 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference Description 3 3 PDL_DTC_TRIGGER_RXIO Data received Return value Category Reference Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 61 PDL_DTC_TRIGGER_TXIO SCl channel Start of next data transfer PDL_DTC_TRIGGER_RXI1 SEL channel 1 Data received PDL_DTC_TRIGGER_TXI1 Start of next data transfer PDL_DTC_TRIGGER_RXI2 SCI channel 2 Data received PDL_DTC_TRIGGER_TXI2 i
106. IO_PORT_PULL_UP or Pull up control register Valid for ports A to E PDL_IO_PORT_TYPE Open drain control register Valid for ports 2 and C data3 The address to where the register value shall be stored The value will be between 0x00 and OxFF for a port 0 or 1 for a pin Return value Functionality References Remarks Program example I O port True if all parameters are valid and exclusive otherwise false R_IO_PORT_Set R_IO_PORT_ModifyControl Ensure that the specified register is valid for the selected port pin RPDL definitions r_pdl_io_port h include M RPDL device specific definitions include r_pdl_definitions h void func void uint8_t direction uint8_t output Read the direction register for port PC R_IO_PORT_ReadControl PDL_IO_PORT_C PDL_IO_PORT_DIRI amp direction Read the output ECTION type for pin P03 R_IO_PORT_ReadControl PDL_IO_PORT_0_3 PDL_IO_PORT_TYPE soutput R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 21 l ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 3 R_IO_PORT_ModifyControl Synopsis Modify an I O port s control registers Prototype bool R_IO_PORT_ModifyControl uint16_tdata1 Port o
107. L DMAC COUNT_2 or PDL DMAC COUNT_4 or PDL DMAC COUNT _8 or PDL DMAC COUNT_16 or PDL DMAC COUNT_32 or PDL DMAC COUNT_64 or PDL DMAC COUNT_128 Select the data count to be transferred in a single operand transfer R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 49 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change Description 2 3 4 Library Reference End of transfer reload control not applicable for single operand transfers R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 50 PDL_DMAC_SOURCE_ADDRESS_RELOAD DISABLE or PDL_DMAC_SOURCE_ADDRESS_RELOAD ENABLE Control reloading of the source address PDL_DMAC_DESTINATION_ADDRESS PDL_DMAC_DESTINATION_ADDRESS_RELOAD_DISABLE or Control reloading of the RELOAD_ENABLE destination address PDL_DMAC_COUNT_RELOAD_DISABLE or PDL_DMAC_COUNT_RELOAD ENABLE Control reloading of the byte count DTC trigger control PDL_DMAC_DTC_TRIGGER_OFF or PDL_DMAC_DTC_ TRIGGER ON Disable or enable activation of the DTC upon completion of a DMA transfer data3 Configure the start trigger for channel DMAn e Start trigger PDL_DMAC_REQUEST_SW or Software trigger PDL_DMAC_REQUEST_CMTO0 or CMT channel 0 interrupt PDL_DMAC_REQUEST_CMT1 or
108. L device specific definitions include r_pdl_definitions h void func void bool result Write OxFF to register PFC1 result R_PFC_Write 1 OxFF if result false Handle th rror here Keep trying to send a string if the channel is busy do result R_SCI_Send 2 Renesas RX NULL PDL_NO_FUNC i whil result false For clarity the return value is not checked in the examples used in this manual R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 3 ztENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 2 1 Clock Generation Circuit 1 R_CGC_Set Synopsis Configure the clock generation circuit Prototype bool R_CGC_Set uint32_t data1 Input frequency uint32_t data2 System clock frequency uint32_t data3 Peripheral module clock frequency uint32_t data4 External bus clock frequency uint8_t data5 Configuration options Description Set the clock output frequencies and options data1 The frequency of the main clock oscillator in Hertz data2 The desired frequency of the System clock ICLK in Hertz data3 The desired frequency of the Peripheral module clock PCLK in Hertz data4 The desired frequency of the External bus clock BCLK in Hertz Specify 0 if the value is
109. LK DIV 512 or PDL WDT PCLK DIV 2048 or PDL WDT PCLK DIV 8192 or PDL WDT PCLK DIV 32768 or PDL WDT PCLK DIV 131072 The division ratio for the internal clock signal PCLK MCU reset control PDL_WDT_RESET_DISABLE or PDL_WDT_RESET_ENABLE Disable or enable reset of the MCU when the watchdog timer overflows with no callback function specified func The function to be called at the periodic interval Specify PDL_NO_FUNC to have the timer output a WOTOVF signal The MCU will also be reset if selected above data2 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Watchdog Timer R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 111 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Remarks Function R_CGC_Set should be called before any use of this function e If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function use in 6 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed
110. NTC_VECTOR_ICRXI1 interface Data received PDL_INTC_ VECTOR _ICTXI1 pai Start of next data transfer End of data transfer True Interrupt control The fast interrupt processing is allocated to only one interrupt handler Open the file r_pdl_user_definitions h and edit the definition FAST_INTC_VECTOR to give it the same value as the interrupt vector used in parameter data1 For example define FAST_INTC_VECTOR PDL_INTC_VECTOR_ADIO This will direct the compiler to generate the instructions required for a fast interrupt vector This function uses an interrupt routine to modify the FINTV register If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Assign the fast interrupt to the handler for pin IRQ3 R_INTC_CreateFastInterrupt PDL_INTC_VECTOR_IRQ3 i Do not forget to edit r_pdl_user_definitions h see remark 2 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 3 R_INTC_CreateExceptionHandlers Synopsis Prototype Description Return value Category Reference Remarks
111. O or 1 for a pin Return value If the I O port specification is incorrect false is returned otherwise true is returned Functionality I O port Reference R_IO_PORT_Set Remark e lf an invalid port or pin is specified the operation of the function cannot be guaranteed Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t data Get the value of port pin P12 R_IO_PORT_Read PDL_10_PORT_1_2 amp data i Get the value of port 4 R_IO_PORT_Read PDL_IO_PORT_4 amp data i R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 24 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 5 R_IO_PORT Write Synopsis Write data to an I O port Prototype bool R_IO_PORT_Write uint16_tdata1 Port or port pin selection uint8_t data2 The data to be written to the I O port or port pin Description Write data to an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 e One port definition or One port pin definition data2 The value must be between 0x00 and OxFF for a port 0 or 1 for a pin Return value True if the parameters are valid otherwise false Functio
112. O24 PDL_PPG_PO26 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 82 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 3 R_PPG_Control Synopsis Control a PPG group Prototype bool R_PPG_Control uint32_t data1 Group selection uint8_t data2 Next output values Description Set the next output for a PPG group data1 Select the group s to be modified If multiple selections are required use to separate each selection e Group selection PDL_PPG_GROUP_0or PDL_PPG_GROUP_1 or PDL_PPG_GROUP_2 or PDL_PPG_GROUP _3or If a pair of groups 0 1 2 3 4 5 or 6 7 is using the same output PDL_PPG_GROUP_4 or trigger both groups may be selected PDL_PPG_GROUP_5 or PDL_PPG_GROUP_6 or PDL_PPG_GROUP_7 data2 The next output values either for a single group or a pair of groups using the format Group 1 3 5 or 7 Group 0 2 4 or 6 Group pair b7 b6 b5 b4 b3 b2 b1 b0 1 amp 0 PO7 PO6 PO5 PO4 PO3 PO2 PO1 POO 3 amp 2 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 584 PO23 PO22 PO21 PO20 PO19 PO18 PO17 PO16 786 PO31 PO30 PO29 PO28 PO27 PO26 PO25 PO24 Return value True if all parameters are valid and exclusive otherwise false Category Programmable P
113. OUTPUT_SPACE Y else Stop the SCI R_SCI_Control 1 PDL_SCI_STOP_TX PDL_SCI_OUTPUT_MARK Y sci_dma_transfer_complete true Figure 5 5 An example of using the DMAC for serial port transmission 3 SCI reception trigger DMAC channel 2 will transfer 5 received characters into the assigned storage area and then call the callback function PDL functions and definitions include r_pdl_dmac h include r_pdl_cgc h include r_pdl_intc h include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h Callback function prototype void DMAC2_ transfer_end_handler void Data destination area void main void R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 12 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change Initialise the system clocks El E6 E6 r L_NO_DATA L_CGC_BCLK_DISABL Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Configure the RS232 port R_SCI_Create 1 PDL_SCI_TX_DISCONN ED PDL_SCI_8N1 115200 0 Y Configure channel 2 R_DMAC_Create 2 PDL_DMAC_ SINGLE PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_REQUEST_SCI1_RX uint8_t amp SCI1 RDR destination_string_l 5 PDL_NO_PTR
114. PU PDL_IO_PORT_INPU 0 0 y Configure port pin P21 as an open drain output R_IO_PORT_Set PDL_IO PORT 2 1 PDL_IO_PORT_OUTPUT 0 0 L_IO_POR EN_DRAIN Write 0x44 to register PFC2 R_PFC_Write 2 0x44 Read the value of all the pins on port 4 R_IO_PORT_Read PDL_IO_PORT_4 result y Set pin P21 to output high R_IO_PORT_Write PDL_IO PORT 2 1 1 Invert pin P21 R_IO_PORT_Modify PDL_IO_PORT_2_1 PDL_IO_PORT_XOR 1 And the value on port 4 with 55h R_IO_PORT_Modify PDL_IO_PORT_4 PDL_IO_PORT_AND 0x55 Read the control registers for port PC R_IO_PORT_ReadControl PDL_IO_PORT_1 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 4 RENESAS Under development Preliminary Specification RX610 Group R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 5 Specifications in this preliminary version are subject to change direction buffer pull_up output Read the direction for pin P03 R_IO_PORT_ReadControl PDL_IO_PORT_0_3 direction PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR y Set the lower 4 bits on port P1 to output R_IO_PORT_ModifyControl PDL_IO_PORT_1 PDL_IO_PORT_DIRECTION PDL_IO_PORT_OR Ox0F y Enable the pull up on pin PA3 R_IO_PORT_ModifyControl PDL_1IO_PORT_A_3 PDL_IO_PORT_PULL_UP PDL_IO_PORT_OR
115. Periodmax UNIT fmax rox 25 MHz 6 25 MHz 4MHz 2 MIN_CHANNEL fas 23 8 Hz 5 96 Hz 3 81 Hz fuin_unit Lra 0 0931 Hz 0 0232 Hz 0 0149 Hz If the requested period is not a multiple of the timer resolution the actual time period will be more than the requested time period The actual duty cycle will be less than the requested duty cycle if the resulting pulse width is not a multiple of the timer resolution A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 91 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions include r_pdl_definitions h void func void Configure pin TMO1 for 500ns period 200ns pulse width R_TMR_CreatePeriodic PDL_TMR_TMR1 PDL_TMR_PERIOD PDL_TMR_OUTPUT_HIGH 500E 9 200E 9 PDL_NO_FUNC PDL_NO_FUNC 0 eo En i Configure pin TMO1 for 5MHz frequency 60 duty cycle R_TMR_CreatePeriodic PDL_TMR_TMR1 PDL_TMR_FREQUENCY PDL_TMR_OUTPUT_HIGH 5E6 60 PDL_NO_FUNC PDL_NO_FUNC 0 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Pa
116. Portpin P1 PDL_IO_PORT_1_7 Port pin P17 PDL IO PORT 2 0 Port pin P2 PDL IO PORT 2 1 Port pin P2 PDL IO PORT 2 2 Port pin P22 PDL_IO PORT_2 3 Port pin P2s PDL_IO_PORT_2 4 Port pin P24 PDL_IO_PORT_2 5 Port pin P25 PDL IO PORT 2 6 Port pin P2 PDL IO PORT 2 7 Port pin P27 PDL IO PORT 3 0 Portpin P3 PDL IO PORT 3 1 Port pin P3 PDL IO PORT 3 2 Port pin P32 PDL_IO_PORT_3_3 Port pin P33 PDL IO PORT 3 4 Port pin P34 PDL_IO_PORT_3 5 Port pin P35 PDL IO PORT 3 6 Portpin P3 PDL_IO_PORT_3_7 Port pin P37 PDL IO PORT 4 0 Port pin P4o PDL IO PORT 4 1 Port pin P4 PDL IO PORT 4 2 Port pin P42 PDL_IO_PORT_4 3 Port pin P4s PDL_IO_PORT_4 4 Port pin P44 PDL_IO_PORT_4 5 Port pin P4s PDL IO PORT 46 Port pin P4 PDL_IO_PORT_4 7 Port pin P4 PDL_IO PORT 5 0 Port pin P5o PDL_IO_PORT_5_1 Port pin P5 PDL IO PORT 5 2 Port pin P52 PDL_IO PORT_5 3 Port pin P53 PDL IO PORT 5 4 Port pin P54 PDL_IO_PORT_5_5 Port pin P5s PDL IO PORT 5 6 Port pin P5 PDL_IO_PORT_5 7 Port pin P57 PDL_IO PORT 6 0 Port pin P6o PDL_IO_PORT_6_1 Port pin P6 PDL IO PORT 6 2 Port pin P62 PDL_IO_PORT_6_3 Port pin P63 PDL IO PORT 6 4 Port pin P64 PDL_IO_PORT_6_5 Port pin P6s PDL IO PORT 6 6 Portpin P6 PDL_IO_PORT_6 7 Port pin P67 PDL_IO PORT_7_0 Port pin P7o PDL_IO_PORT_7_1 Port pin P7 PDL IO PORT 72 Port pin P72 PDL_IO PORT 7 3 Port pin P73 PDL IO PORT 74 Port pin P74 PDL_IO PORT_7_5 Port pin P75 PDL_IO PORT 7
117. R if it is not required Return value True if all parameters are valid otherwise false Category Compare Match Timer Reference R_CMT_Create Remarks lf the flag is read and is set to 1 it shall be automatically cleared to O by this function Program example RPDL definitions include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags uint16_t Counter void func void Read the channel 2 values R_CMT_Read 2 amp Flags amp Counter R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 110 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 2 14 Watchdog Timer 1 R_WDT_Create Synopsis Prototype Description Return value Category Reference Configure the Watchdog timer bool R_WDT_Create Set up and start the Watchdog timer data1 uint16_t data1 void func uint8_t data2 4 Library Reference Configuration selection Callback function Interrupt priority level Configure the timer To set multiple options at the same time use to separate each value The default settings are shown in bold Clock selection PDL WDT PCLK DIV 4 or PDL WDT PCLK DIV 64 or PDL WDT PCLK DIV 128 or PDL WDT PC
118. REQUEST_SCI1_TX source_string_l uint8_t amp SCI1 TDR strlen source_string_1 PDL_NO_DATA P P D 7 DL_NO_DATA DL_NO_DATA AC3_transfer_end_handler Enable channel 3 R_DMAC_Control PDL_DMAC_3 PDL_DMAC_ENABL PDL_NO_DATA PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA Y Initialise the flags sci_dma_transfer_complete false break_required false Enable the transmission using the DMAC R_SCI_Send 1 PDL_SCI_DMAC_TRIGG PDL_NO_PTR PDL_NO_DATA PDL_NO_FUNC Y Wait for the DMAC to complete the transfer while sci_dma_transfer_complete false Send the next string using polling mode R_SCI_Send 1 PDL_NO_DATA R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 11 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples source_string_2 0 PDL_NO_FUNC void DMAC3_transfer_end_handler void uint8_t SCI_status Wait for the SCI transmission to end do R_SCI_Get Status 1 amp SCI_status PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR de while SCI_status amp 0x04 0 if break_required true Stop the SCI to allow the break signal to be output R_SCI_Control 1 PDL_SCI_STOP_TX PDL_SCI_
119. RIOD or The counter clock source and compare match value will be calculated by this function The parameter data3 will specify the timer frequency PDL_CMT_FREQUENCY or The counter clock source and compare match value will be calculated by this function PDL_CMT_PCLK_DIV_8 or PDL_CMT_PCLK_DIV_32 or PDL_CMT_PCLK_DIV_128 or PDL_CMT_PCLK_DIV_512 Select the internal clock signal PCLK 8 32 128 or 512 as the counter clock source The parameter data3 will be the register CMCOR value e DMAC DTC trigger control PDL_CMT_DMAC_DTC_TRIGGER_DISABLE or PDL_CMT_DMAC_TRIGGER_ENABLE or PDL_CMT_DTC_ TRIGGER ENABLE Disable or enable activation of the DMAC or DTC when a compare match occurs data3 The data to be used for the register value calculations Data use Parameter type The timer period in seconds or float The timer frequency in Hz or float The value to be put in register CMCOR uint16_t func The function to be called at the periodic interval Specify PDL_NO_FUNC if not required data4 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value True if all parameters are valid and exclusive otherwise false Category Compare Match Timer Reference R_CMT_Destroy R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 104 RENESAS Under de
120. RX_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a byte is received PDL_IIC_TX_DMAC_DTC_TRIGGER_DISABLE or PDL_IIC_TX_DMAC_TRIGGER_ENABLE or PDL_IIC_TX_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC for data transmission data3 The start address of the storage area for any received data If the DMAC or DTC shall be used to handle the received data specify PDL_NO_PTR data4 The number of bytes in the storage area If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Return value Category Reference Transfer method Parameter PDL_NO_FUNC This function will continue until a Stop condition is detected Polling e or the master tries to read data from this slave The function to be called when a Stop condition is detected or the master tries Interrupts to read data from this slave DMAC or DTC The function to be called when a Stop or error condition is detected data5 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable otherwise false 12C R_IIC_Create R_IIC_GetStatus R_IIC_SlaveSend R20UT0083EE010
121. R_TMR_ControlUnit uint8_t data1 Unit selection uint32_t data2 Configuration selection uint16_tdata3 Register value uint16_tdata4 Register value uint16 tdata5 Register value Description Modify a timer unit s counter and compare registers data1 The unit number n where n 0 or 1 data2 The channel settings to be modified If multiple selections are required use to separate each selection e Counter stop re start PDL_TMR_STOP or PDL_TMR_START Disable or re enable the counter clock source The counter or compare registers to be modified PDL_TMR_COUNTER Update the timer counter register TCNT PDL_TMR_TIME_CONSTANT_A Update the timer compare match A register TCORA PDL_TMR_TIME_CONSTANT_B Update the timer compare match B register TCORB data3 The 16 bit counter value This will be ignored if the register is not selected data4 The 16 bit compare match A value This will be ignored if the register is not selected data5 The 16 bit compare match B value This will be ignored if the register is not selected Return value True if all parameters are valid and exclusive otherwise false Category Timer TMR Reference R_TMR_CreateUnit R_TMR_ReadUnit Remarks For unit 0 the upper byte is the value for TMRO and the lower byte is the value for TMR1 For unit 1 the upper byte is the value for TMR2 and the low
122. Reset the EEPROM sub address to 0 using polling R_IIC_MasterSend L_TIC_STOP_DISABLI PROM_ADDRESS eprom_data_array_l L_NO_FUNC R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 36 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples Read data from the EEPROM on channel 1 using the DMAC read_eeprom_data Prepare the next data R_DMAC_Control PDL_DMAC_2 PDL_DMAC_SUSPEND L_DMAC_UPDATE L_NO_DATA L_NO_PTR ata_storage 5 PDL _DMAC_ENABLE DESTINATION PDL_DMAC_UPDAT D P D D d r DL_NO_PTR DL_NO_PTR DL_NO_DATA Read data from the EEPROM on channel 1 using the DMAC read_eeprom_data static void write_eeprom_data void bus_busy true Send data to the EEPROM on channel 1 using the DMAC R_IIC_MasterSend 1 PDL_IIC_DMAC_TRIGG EPROM_ADDRESS DL_NO_PTR PDL_NO_FUNC while bus_busy true Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 E 3 DL_NO_FUNC static void read_eeprom_data void bus_busy true Read data from the EEPROM on channel 1 using the DMAC R_IIC_MasterReceive 1 PDL_IIC_DMAC_TRIGG EPROM_ADDRESS DL_NO_PTR PDL_NO_FUNC
123. SOURCE_ADDRESS PLUS or PDL_DTC SOURCE ADDRESS MINUS After a data transfer leave the source address unchanged increment it or decrement it PDL_DTC_DESTINATION_ADDRESS_FIXED or PDL_DTC_ DESTINATION ADDRESS PLUS or PDL_DTC DESTINATION ADDRESS MINUS After a data transfer leave the destination address unchanged increment it or decrement it Transfer data size PDL_DTC_SIZE_8 or PDL_DTC_SIZE_16 or Select 1 2 or 4 bytes to be transferred in one PDL_DTC_CHAIN_O PDL_DTC SIZE 32 operation e Chain transfer control PDL_DTC_CHAIN_DISABLE or Disable PDL_DTC_CHAIN_CONTINUOUS or Enable continuous or Enable only when the transfer counter is 0 e Interrupt generation PDL_DTC_IRQ_COMPLETE or PDL_DTC_IRQ_TRANSFER Select inter rupt request generation when the transfer sequence completes or for every transfer e Transfer trigger selection Name Module Trigger cause PDL_DTC_TRIGGER_CHAIN None Chain transfer PDL_DTC_TRIGGER_CMT0 PDL_DTC_TRIGGER_CMT1 Compare match Compare match on channel n PDL_DTC_TRIGGER_CMT2 timer n 0 to 3 PDL_DTC_TRIGGER_CMT3 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 59 7tENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference Description 2 3 PDL_DTC_TRIGGER_IRQO
124. Set up a DMAC channel for IIC reception R_DMAC_Create 2 PDL_DMAC_SINGLE PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_REQUEST_IIC1_RX uint8_t RIIC1 ICDRR R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 35 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples ta_ storage L_NO_PTR L_NO_PTR L_NO_DATA iic_rx_dmac_end_handler 7 Y Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 1 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 0 0 0 0 100E3 300 lt lt 16 200 Y Enable the DMAC channels R_DMAC_Control PDL_DMAC_2 PDL_DMAC_3 _DMAC_ENABLE L_NO_DATA L_NO_PTR L_NO_PTR L_NO_DATA L_NO_PTR L_NO_PTR L_NO_DATA UUUUUOUUO U y Write the data into the EEPROM write_eeprom_data Prepare the next data for the EEPROM R_DMAC_Control PDL_DMAC_3 pP DL_DMAC_SUSPEND PDL_DMAC_ENABLE PDL_DMAC_UPDATE_SOURCE PDL_DMAC_UPDATE_COUNT PDL_DMAC_CL PDL_NO_DATA eprom_data_array_2 PDL_NO_PTR f DL_NO_PTR PDL_NO_PTR DL_NO_DATA Write the data into the EEPROM write_eeprom_data Clear the data storage area for i 0 i lt 20 i data_storage i 0x00
125. Set up a timer TMR unit in 16 bit count mode data1 The unit number n where n 0 or 1 data2 Configure the unit If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Counter clock source selection PDL_TMR_CLK_OFF or The clock input is disabled PDL_TMR_CLK_EXT_RISING or PDL_TMR_CLK_EXT_FALLING or PDL_TMR_CLK_EXT_BOTH or The external clock signal TMCIx x 1 or 3 for n 0 or 1 is used with rising falling or both edges detected PDL_TMR_CLK_PCLK_DIV_1 or PDL_TMR_CLK_PCLK_DIV_2 or PDL_TMR_CLK_PCLK_DIV_8 or PDL_TMR_CLK_PCLK_DIV_32 or PDL_TMR_CLK_PCLK_DIV_64 or PDL_TMR_CLK_PCLK_DIV_1024 or PDL_TMR_CLK_PCLK_DIV_8192 The internal clock signal PCLK 1 2 8 32 64 1024 or 8192 e Counter clearing PDL_TMR_CLEAR_DISABLE or Clearing is disabled PDL_TMR_CLEAR_CM_Aor Cleared after a compare match A occurs PDL_TMR_CLEAR_CM_B or Cleared after a compare match B occurs PDL_TMR_CLEAR_RESET_RISING or Cleared by a rising edge on the external reset pin TMRly PDL_TMR_CLEAR_RESET_HIGH Cleared when the external reset pin TMRly y 0 or 2 for n 0 or 1 is high e ADC trigger control PDL_TMR_ADC_TRIGGER_DISABLE or PDL_TMR_ADC_TRIGGER_ENABLE Disable or enable ADC conversion start requests on a compare m
126. Stop Start Pa 1 Busy SCL SDA NACK condition S ndition Arbitration lost Timeout b7 b6 b5 b4 b3 b2 bi b0 Transmission Mode Address detection 0 Not detected 1 detected 0 Active 0 Receive Slave 1 Idle de Transmit SMBus host Device ID General call 7 1 0 data3 The address for storing the number of bytes that are have been transmitted in the current transfer Specify PDL_NO_PTR if this information is not required aes ee for storing for the number of bytes that are have been received in the current transfer Specify PDL_NO_PTR if this information is not required True if all parameters are valid otherwise false 12C R_IIC_Create The flags are not modified by this function The event detection flags are cleared when a new transfer is started ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions tinclude r_pdl_definitions h void func void uintl6_t status_flags uint16_t tx_count Read the status of channel 0 R_IIC_GetStatus 0 amp status_flags tx_count PDL_NO_PTR R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 146 RENESAS Under development Preliminary Specification RX610 Group 4 2 18 Specifications in this preliminary version are subjec
127. T1 PDL_TMR_TMR2 or The channel n n 0 1 2 or 3 or unit n 0 or 1 to be data2 Configure the timer If multiple selections are required use to separate each selection The default settings are shown in bold e Period or frequency calculation PDL_TMR_PERIOD or The parameters data3 and data4 will contain either period PDL_TMR_FREQUENCY and pulse width or frequency and duty cycle e Output pin control PDL_TMR_OUTPUT_HIGH or Start with a high level or PDL_TMR_OUTPUT_LOW or low level output or PDL_TMR_OUTPUT_OFF no output on pin TMOn For 16 bit operation the pin shall be TMO2 when n 1 e ADC trigger control PDL_TMR_ADC_TRIGGER_OFF or requests TMR unit Disable or enable TMR triggered ADC conversion start PDL_TMR_ADC_TRIGGER_ON Applicable only for channels TMRO or TMR2 or either e Pulse DTC trigger control PDL_TMR_PULSE_DTC_TRIGGER_DISABLE or PDL_TMR_PULSE_DTC_TRIGGER_ENABLE Disable or enable activation of the DTC at the pulse width interval e Period DTC trigger control PDL_TMR_PERIOD_DTC_TRIGGER_DISABLE or PDL_TMR PERIOD DTC TRIGGER ENABLE Disable or enable activation of the DTC at the periodic interval data3 The period in seconds or frequency in Hz data4 The pulse width in seconds or duty cycle funct The function to be called at the pulse width interval Use PDL_NO_FUNC if not required
128. TC_Write R_INTC_Modify Remarks The Interrupt register tables are not contiguous This function does not check for gaps within these tables Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void uint8_t ipl Read the IPL bits R_INTC_Read PDL_INTC_REG_IPL 0 amp ipl R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 15 2tENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 7 R_INTC Write Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 16 Update an interrupt register bool R_INTC_Write uint8_t data1 Register selection uint8_t data2 Register number uint8_t data3 Register value Write the new value to an interrupt register data1 e The register to be updated PDL_INTC_REG_IPL or Select the current CPU interrupt priority level or PDL_INTC_REG_IR or Interrupt Request register or PDL_INTC_REG_ISELR or Interrupt Request Destination Setting register or PDL_INTC_REG_IER or Interrupt Request Enable register or PDL_INTC_REG_IPR Interrupt Priority register data2 The reg
129. U Timer Pulse Unit channel 2 Input capture or compare match A Input capture or compare match B Overflow Underflow PDL_INTC_VECTOR_TGI3A PDL_INTC_VECTOR_TGI3B PDL_INTC_VECTOR_TGI3C PDL_INTC_VECTOR_TGI3D PDL_INTC_VECTOR_TCI3V Timer Pulse Unit channel 3 Input capture or compare match A Input capture or compare match B Input capture or compare match C Input capture or compare match D Overflow PDL_INTC_VECTOR_TGI4A PDL_INTC_VECTOR_TGI4B PDL_INTC_VECTOR_TCI4V PDL_INTC_VECTOR_TCI4U Timer Pulse Unit channel 4 Input capture or compare match A Input capture or compare match B Overflow Underflow ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference Description 2 3 PDL_INTC_VECTOR_TGI5A PDL_INTC_VECTOR_TGI5B PDL_INTC_VECTOR_TCI5V PDL_INTC_VECTOR_TCI5U Timer Pulse Unit channel 5 Input capture or compare match A Input capture or compare match B Overflow Underflow PDL_INTC_VECTOR_TGI6A PDL_INTC_VECTOR_TGI6B PDL_INTC_VECTOR_TGI6C PDL_INTC_VECTOR_TGI6D PDL_INTC_VECTOR_TCI6V Timer Pulse Unit channel 6 Input capture or compare match A Input capture or compare match B Input capture or compare match C Input captur
130. UT_HIGH_CM_B or 1 is output if a compare match B occurs PDL_TMR_OUTPUT_INV_CM_B The output toggles if a compare match B occurs data4 The 16 bit counter value data5 The 16 bit compare match A value data6 The 16 bit compare match B value func1 The function to be called when an overflow occurs Use PDL_NO_FUNC if not required func2 The function to be called when a Compare match A occurs Use PDL_NO_FUNC if not required func3 The function to be called when a Compare match B occurs Use PDL_NO_FUNC if not required data7 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 func2 and func3 True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_Destroy R_TMR_ControlChannel R_TMR_ControlUnit R TMR_ReadChannel R_TM R_ReadUnit e If an input pin TMCIx or TMRIy is selected this function will configure the direction and input buffer control for that pin e If the output pin TMOy is made active this function will disable other output functions on that pin e If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function usage in 6 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has com
131. VA E AE ETE ATE E a ential 2 1 2 2 Control Fun tions Ssummary siede teieni aeaiia ea ia le edd ali evn i Sede 2 1 2 3 Clock Generation Circuit Driver ooonnnnnnncnnnnnnnnnnnnnnconnncccnncccnn arrancar 2 3 2 4 Interrupt Control Drivedi naaa cc 2 4 20 MO POrE DIVO A A A dCi 25 2 6 Port Function Control DAVOS si tocata dele ataa Eada 2 6 2 f MCU Operation DEE A aati daada ith daia A A 2 7 2 8 Low Power Consumption DIiver cccccccececeeeeeeeeeeeseeceeeeeceaeeeeeaeeseeeeecaaeeesaaeeseaeeseeeeesaaeeseaeeseeeeseaees 2 8 2 9 Bus Controller DIV ii a da dica tia said 2 9 2 10 DMA Controller Driver ccccccceccccesseceeseseeeeceeeeeeeceesaeeseeeeaeeesccsaeeeseesaeeeesecsaeeesseaeessseaeessseneeeessaaes 2 10 2 11 Data Transfer Controller Driver 0 cccccecsceeeeeeeeeneeeeeaeeeeeeeeceaeeeeaaeeseaeeseeeeesaeeeeeaeeseeeeeseaeeetaeeseaeeseaes 2 11 2 12 Timer Pulse Unit Driver comica aa 2 12 2 13 Programmable Pulse Generator Driver oonnccnncccnncconnccnnnoccnanccnnnnnnn anna nan cnn rca nn 2 13 2 14 8 01 TIMOR DIV tra Ada dear 2 14 2 152 Compare Match Timer Driver cerati pat 2 15 2 16 Watchdog Timer Driver siioni idie iad aoaiina aii iaa atoian aiad asie a dia Aia iai Eaa RAAS 2 16 2 17 Serial Communication Interface DriVeF oooonnnnnnnicnnnnconnnnnnaccnonccnnnrann nara nc crac 2 17 2 18 CRG Calculator DIVER nica ii ada da A TA 2 18 2 19 PG Bus Interface Driver vito da A dd db a is 2 19 2 20 10 bit Analog to Digita
132. XI3 SCI channel3 FStart of next data transfer PDL_INTC_VECTOR_TEI3 End of data transfer R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 9 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Description 3 3 PDL_INTC_VECTOR_ERI4 Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 10 PDL_INTC_VECTOR_RXI4 Error in data received Data received PDL_INTC_VECTOR_ICTEI1 PDL_INTC_VECTOR TX 4 SCI channel 4 Start of next data transfer PDL_INTC_VECTOR_TEI4 End of data transfer PDL_INTC_VECTOR_ERI5 Error in data received PDL_INTC_VECTOR_RXI5 SCI channel 5 Data received PDL_INTC_VECTOR_TXI5 Start of next data transfer PDL_INTC_VECTOR_TEI5 End of data transfer PDL_INTC_VECTOR_ERI6 Error in data received PDL_INTC_VECTOR_RXI6 SCI channel 6 Data received PDL_INTC_VECTOR_TXI6 j Start of next data transfer PDL_INTC_VECTOR_TEI6 End of data transfer PDL_INTC_VECTOR_ICEEIO 12C bus Transfer error or event generation PDL_INTC_VECTOR_ICRXIO interface Data received PDL_INTC_VECTOR_ICTXIO o Start of next data transfer PDL_INTC_VECTOR_ICTEIO End of data transfer PDL_INTC_VECTOR_ICEEI1 12C bus Transfer error or event generation PDL_I
133. _B_IC_ FALLING EDGE or PDL_TPU_B_IC_BOTH_EDGES or Input capture at TIOCBn or TIOCAn rising edge Input capture at TIOCBn or TIOCAn falling edge Input capture at TIOCBn or TIOCAn both edges See below for TIOCBn or TIOCAn pin selection PDL_TPU_B_IC_TPU_COUNT_CLK or Input capture at TPU n 1 count clock count up or count down Invalid if TPU n 1 uses PCLK 1 Valid for n 0 3 6 and 9 PDL_TPU_B_IC_TPU_CM_IC Input capture at TPU n 1 TGRC compare match or input compare Valid for n 1 4 7 and 10 e TGRB input capture input selection PDL_TPU_B_IC_TIOCB or PDL_TPU_B_IC TIOCA Input capture using pin TIOCBn or TIOCAn ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group Description 4 5 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 71 data5 4 Library Reference Configure the operation for general registers C and D valid for n 0 3 6 and 9 If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture output compare control fo r register TGRC PDL_TPU_C_OC_DISABLED or PDL_TPU_C_OC_LOW or PDL_TPU_C_OC_LOW_CM_HIGH or PDL_TPU_C_OC_LOW_CM_INV or PDL_TPU_C_OC_HIGH_CM_LOW or PDL_TPU_C_OC_HIGH or PDL_TPU_C OC HIGH_CM_INV or TIOCCn
134. _GetStatus Read the MCU status LPC Create Configure the MCU low power conditions Low Pomar LPC Control Select a low power consumption mode LPC_WriteBackup Write to the Backup registers Consumption Read from the Backup registers LPC_GetStatus Read the status flags Bus Controller BSC_Create Configure the external bus controller DD D FO FO D D D D D FO FO FO d d FO BSC_CreateArea Configure an external bus area R_BSC_Destroy Stop the Bus Controller R_BSC_Control Modify the External Bus Controller operation R_BSC_GetStatus Read the External Bus Controller status flags DMA Controller R_DMAC _ Create Configure the DMA controller R_DMAC_ Destroy Disable a DMA channel R_DMAC_Control Control the DMA controller R_DMAC_GetStatus Check the status of the DMA channel Data Transfer Controller R_DTC_Set Set the Data Transfer Controller options R_DTC_Create Configure the DTC for a transfer R_DTC_ Destroy Shutdown the Data Transfer Controller R_DTC_Control Control the Data Transfer Controller R_DTC_GetStatus Check the status of the Data Transfer Controller Timer Pulse Unit R_TPU_Create Configure a Timer Pulse Unit channel R_TPU_Destroy Shut down a timer pulse unit R_TPU_ Control Control a timer channel R_TPU_Read Read from timer channel
135. _INTC_CreateExtInterruptAall PDL_INTC_IRO3 PDL_INTC_FALLING PDL_INTC_B PDL_INTC_DTC_TRIGG IRQ3_handler 7 Y Start the DTC R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Y void IRO3_handler void uint8_t StatusValue uint32_t SourceAddr uint32_t DestAddr uint32_t TransferCount Read the status and current source address for the IRQ3 transfer R_DTC_Get Status dtc_irq3_transfer_data StatusValue amp SourceAddr DestAddr amp TransferCount y Normal transfer if StatusValue 0x00 Invert the port pin R_IO_PORT_Modify PDL_IO_ PORT 3 6 PDL_IO_PORT_XOR I Re enable IRQ3 as a DTC trigger R_DTC_Control PDL_DTC_TRIGGER_IRQ3 PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Figure 5 7 Example of DTC use R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 16 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 6 Timer Pulse Unit Figure 5 8 shows an example of Timer Pulse Unit usage Peripheral driver function prototypes include r_pdl_tpu h include r_pdl_cgc h include r_pdl_pfc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h
136. _INTC_REG_IER 0x09 0x50 PDL_INTC_OR ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 2 3 I O Port I O Port functions may operate on a complete port or on individual port pins The available definitions are listed below 1 0 port definitions PDL_IO_PORT_0 Port PO PDL_IO_PORT_1 Port P1 PDL_IO_ PORT 2 Port P2 PDL_IO_PORT_3 Port P3 PDL_IO PORT_4 Port P4 PDL_IO_PORT_5 Port P5 PDL_IO_PORT_6 Port P6 PDL_IO PORT_7 Port P7 PDL_IO_PORT_8 Port P8 PDL_IO_PORT_9 Port P9 PDL_IO PORTA Port PA PDL_IO_PORT_B Port PB PDL_IO PORT_C Port PC PDL_IO PORT_D Port PD PDL_IO_PORT_E Port PE PDL_IO_PORT_F Port PF PDL_IO PORT_G Port PG PDL_IO_PORT_H Port PH Note Ports PF to PH are available only on the 176 pin device I O port pin definitions PDL_IO PORT_0_0 Portpin P0o PDL_IO_PORT_0_1 Port pin PO PDL IO PORT 0 2 Port pin PO PDL_IO_PORT_0_3 Port pin POs PDL_IO_PORT_0_4 Port pin PO PDL_IO_PORT_0_5 Port pin POs PDL IO PORT_1_0 Port pin P1o PDL_IO_PORT_1_1 Port pin P1 PDL_IO_PORT_1_2 Port pin P12 PDL_IO_PORT_1_3 Port pin P13 PDL_IO_PORT_1_4 Port pin P14 PDL_IO PORT_1_5 Port pin P15 PDL_IO PORT_1 6
137. _LPC_CANCEL_NMI_DISABLE or PDL_LPC_CANCEL_NMI_FALLING or PDL_LPC_CANCEL_NMI_RISING Prevent or allow an edge on the IRQO A pin to cancel deep software standby mode Prevent or allow an edge on the IRQ1 A pin to cancel deep software standby mode Prevent or allow an edge on the IRQ2 A pin to cancel deep software standby mode Prevent or allow an edge on the IRQ3 A pin to cancel deep software standby mode Prevent or allow an edge on the NMI pin to cancel deep software standby mode ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Description 2 2 data2 Select the waiting times If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Software Standby waiting time PDL_LPC_STANDBY_64 or PDL_LPC_STANDBY_512 or PDL_LPC_STANDBY_1024 or PDL_LPC_STANDBY_2048 or PDL_LPC_STANDBY_4096 or Select the number of PCLK cycles that will elapse PDL_LPC_STANDBY_16384 or before the CPU resumes after exiting from PDL_LPC_STANDBY_32768 or software standby mode PDL_LPC_STANDBY_65536 or PDL_LPC_STANDBY_131072 or PDL_LPC_STANDBY_262144 or PDL_LPC_STANDBY_524288 e Deep Software Standby waiting time PDL_LPC_DEEP_STANDBY_64 or PDL_LPC_DEEP_STANDBY_512 or PDL_LPC_DEEP_STANDBY_1024
138. _crc h RPDL device specific definitions include r_pdl_definitions h void func void Write FOh into the CRC calculation register R_CRC_Write OxFO Y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 129 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 R_CRC_Read Synopsis Read the CRC calculation result Prototype bool R_CRC_Read uint8_t data1 Control uint16_t data2 Data storage location Description Reads and stores the CRC calculation result data1 Control the behaviour of the CRC unit The default setting is shown in bold Specify PDL_NO_DATA to use the default e Result register clearing PDL_CRC_CLEAR_RESULT or y PDL_CRC_RETAIN RESULT Clear or retain the value in the result register data2 The address of the location where the result shall be stored For the 8 bit polynomial the results are stored in the lower order byte Return value True Category CRC Reference R_CRC_Create R_CRC_Write Remarks None Program example RPDL definitions include r_crc h RPDL device specific definitions include r_pdl_definitions h void func void uint16_t CRCresult Read the CRC result and retain it R_CRC_Read PDL_CRC_RETAIN_RESULT amp
139. able or enable activation of the DMAC or DTC when a data byte is transmitted data3 The address of the sl data4 ave device Ignored if the Start condition is disabled The start address of the data to be sent If the DMAC or DTC shall be used to transfer the data specify PDL_NO_PTR data5 The number of bytes to be sent If the DMAC or DTC shall be used to transfer the data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Transfer method Parameter Pollin PDL_NO_FUNC This function will continue until the required number of 9 bytes has been sent or another event occurs Interrupts The function to be called when bus activity has stopped DMAC Either the function to be called when each byte is sent or PDL_NO_FUNC if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create data6 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value otherwise false R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 136 True if all parameters are valid exclusive and achievable and a normal transfer completed ENESAS Under development Preliminary Specification Specifications in this preliminary
140. abling the controller 4 Starting or stopping the controller 5 Reading the status flags and data transfer registers R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 11 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 12 Timer Pulse Unit Driver The driver functions support the use of the twelve 16 bit timers providing the following operations 1 Configuration for use including e Access to all control bits e Automatic interrupt control e Automatic I O pin configuration 2 Disabling channels that are no longer required and enabling low power mode 3 Control of a timer 4 Reading the status and registers of a timer Note The Clock Generation Circuit must be configured before configuring any timer channel R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 12 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 13 Programmable Pulse Generator Driver The driver functions support the use of the pulse generator providing the following operations 1 Configuring the generator for use 2 Disabling groups of outputs that are no longer required 3 Control of the generator during run time R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 13 RENESAS Under development Preliminary Specification RX610 Group Specificatio
141. ad 0 Flags PDL_NO_PTR amp General_A PDL_NO_PTR PDL_NO_PTR amp General_D R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 78 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 2 11 Programmable Pulse Generator 1 R_PPG_Create Synopsis Configure a PPG group Prototype bool R_PPG_Create uint32_t data1 Output pin selection uint16_t data2 Configuration selection uint8_t data3 Output values Description 1 2 Set up a 4 bit PPG group data1 Select the outputs to be enabled If multiple selections are required use to separate each selection Select only outputs within one group e Output pin selection Outputs are disabled by default PDL_PPG_POO PDL_PPG PO1 PDL PPG PO2 PDL_PPG_PO3 PDL_PPG_PO4 PDL_PPG_PO5 PDL_PPG_PO6 PDL_PPG_PO7 PDL_PPG_PO8 PDL_PPG_PO9 PDL_PPG_PO10 PDL_PPG_PO11 PDL_PPG_PO12 PDL_PPG_PO13 PDL_PPG_PO14 PDL_PPG_PO15 Group 0 Group 1 Unit 0 Group 2 Group 3 PDL_PPG PO16 PDL_PPG_PO17 PDL_PPG_PO18 PDL_PPG_PO19 PDL_PPG_PO20 PDL_PPG_PO21 PDL_PPG_PO22 PDL_PPG_PO23 PDL_PPG_PO24 PDL_PPG_PO25 PDL_PPG_PO26 PDL_PPG_PO27 PDL_PPG_PO28 PDL_PPG PO29 PDL_PPG_PO30 PDL_PPG_PO31 Group 4 Group 5 Unit 1 Group 6
142. ad the receive count R_DMAC_GetStatus 2 PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR amp Count 3 Count BUFFER_SIZE Count Which address was detected if status_flags 0x0001 0x0u for i 0 i lt Count i slave_data_storage_0 slave_0_ptr slave_data_received i slave_O_ptr if slave_0_ptr BUFFER_SIZE slave_0_ptr 0 status_flags amp 0x0002 0x0u i 0 i lt Count i slave_data_storage_l slave_l_ptr slave_data_received i slave_l_ptr if slave_l_ptr BUFFER_SIZE R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 47 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples slave_1_ptr 0 Reset the receive buffer DMAC channel R_DMAC_Control PDL_DMAC_2 DL_DMAC_SUSPI END PDL_DMAC_ENABLE DL_DMAC_UPDATE_DESTINATION PDL_DMAC_UPDAT R _DREO P P PDL_DMAC_CLEA PDL_NO_DATA PDL_NO_PTR slave_data_received BUFFER_SIZE PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA y reception_completed false Wait for the bus to become idle do R_IIC_GetStatus SLAVE_CHANNEL amp status_flags PDL_NO_PTR PDL_NO_PTR 3 while status_flags 0x8000 0x0u Re start monitoring the channel R_IIC_SlaveMonito
143. age 4 108 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 4 R_CMT_Control Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 109 Control CMT operation bool R_CMT_Control uint8_t data1 Channel selection uint16_t data2 Configuration selection float data3 Period frequency or register data Modify the operation of a CMT channel data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer channel To set multiple options at the same time use to separate each value e Counter stop re start PDL_CMT_STOP Disable the counter clock source PDL_CMT_START Enable the counter clock source Value change request PDL_CMT_PERIOD or The parameter data3 will contain the new period PDL_CMT_FREQUENCY or frequency PDL_CMT_CONSTANT or constant register CMCOR or PDL_CMT_COUNTER counter register CMCNT value data3 The new period frequency or register value This will be ignored if a change is not requested Data use Parameter type The timer period in seconds or float The timer frequency in Hz or float The value to be put in the register uint16_t True if all parameter
144. amp P PGE Create a a ld A E A Sut beces sun Jacuiladyals 4 79 Ri PPG DESITOY visita riada ita da a a ad ia ad atlas ida acia 4 81 RP PGC Omer ts 5 AS A A ad A dd ad dd Dad 4 83 S Di TIMET anae aa ia a A a duataiea Mol a Sa Aiea cites aa Eea 4 84 R TMR GreateChannel irana e i a e dd edadea ii 4 84 R TMR Create Ultra o bic 4 87 R TMR Crete POr Od O cicatrices 4 90 R TMR Creat One Snot eee arera e LR Era E AES RAEE AEAEE SE rana bara add 4 93 R TMR DeStOY ANTE E E E EEE EA O E E E NE erhepeceaieges 4 95 R TMR ConrolChanne h sne ere A AE a ra E AE a A RENEA EASE rara eras 4 96 ReTMRe Control nit escasa A AE E iba 4 97 Re TMReControlPeriogic i cccissexie T aa a a iia daria s 4 99 R TMR Read ONAE ect diia 4 101 ROTMR Read NiE irc doses 4 102 Compare Match TIMET erea radiata aaa eras 4 104 RuCMT Cre ate iii aia hee 4 104 ANA AAA AN 4 106 A A baad T E 4 108 BEG MT ECONO id O atic AS A a 4 109 REG ie Rea ii a id a ada 4 110 Watchdog TIME aii ais 4 111 REY A e eats A E aabtveste A A 4 111 ASWDT CONTO IU da des ves ta tat bee E Diada meat 4 113 RA D A EN a tet e tt E A A E E Ira dida 4 114 Serial Communication INterface oconcococonnnnccnnonoooononnnnnonnnononnnnononnnnnnnnnonnnnnnnnnnnananononannnnnns 4 115 SA OA 4 115 PLAS GIL DO StOY siii a 4 118 RESCIES A o A 4 119 RESCIR eee a esta det elle da o ello LAA 4 121 RESCIGon ola a AE e o e lee e do a e ea dde 4 123 RESCIVGOtStatus iia ina 4 125 CRE calculator aa ts adn de ces ad e ele de a
145. amples Shutdown unit 2 R_ADC_10_Destroy 2 Y void ADC3Handler void R_ADC_10_Read 3 adc3_result Y Figure 5 29 Example of ADC Conversion R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 51 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 6 RX specific notes 6 RX specific notes 6 1 Interrupts and processor mode The RX CPU has two processor modes supervisor and user The API driver functions will be executed by the CPU in user mode However any callback functions which are called by the API interrupt handlers will be executed by the CPU in supervisor mode This means that the privileged CPU instructions RTFI RTE and WAIT can be executed by the callback function and any function that is called by the callback function The user must 1 Avoid using the RTFI and RTE instructions These instructions are issued by the API interrupt handlers so there should be no need for the user s code to use these instructions 2 Use the wait intrinsic function with caution This instruction is used by some API functions as part of power management so there should be no need for the user s code to use this instruction More information on the processor modes can be found in 1 4 of the RX Family software manual 6 2 Interrupts and DSP instructions The accumulator ACC register is modified by the following
146. another channel configured for synchronous operation e Buffer operation valid for channels 0 3 6 and 9 PDL_TPU_BUFFER_AC_DISABLE or PDL_TPU_BUFFER AC ENABLE Disable or enable buffer operation for registers TGRA and TGRC PDL_TPU_BUFFER_BD_DISABLE or PDL_TPU_BUFFER_BD_ENABLE Disable or enable buffer operation for registers TGRB and TGRD e ADC trigger control PDL_TPU_ADC_TRIG_DISABLE or PDL_TPU_ADC_TRIG_ENABLE Disable or enable ADC conversion start requests on a TGRA input capture compare match R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 69 ENESAS Under development RX610 Group Preliminary Specification Specifications in this preliminary version are subject to change Description 3 5 data4 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 70 4 Library Reference Configure the operation for general registers A and B If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults Input capture output compare control for register TGRA PDL_TPU_A_OC_DISABLED or PDL_TPU_A_OC_LOW or PDL_TPU_A_OC_LOW_CM_HIGH or PDL_TPU_A_OC_LOW_CM_INV or PDL_TPU_A_OC_HIGH_CM_LOW or PDL_TPU_A_OC_HIGH or PDL_TPU_A_OC_HIGH_CM_INV or TIOCAn output disabled TIOCAn output low TIOCAn initial output low goes high at compare match
147. any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electron
148. ata7 The number of wait cycles for the first access during a normal or page read sequence CSRWAIT Valid between 0 and 31 data8 The number of wait cycles for the first access during a normal or page write sequence CSWWAIT Valid between 0 and 31 data9 The number of cycles that the CS signal is left asserted after the read strobe is negated CSROFF Valid between 0 and 7 data10 The number of cycles that the CS signal is left asserted after the write strobe is negated CSWOFF Valid between 0 and 7 data11 The number of cycles that the data output is left asserted after the write strobe is negated WDOFF Valid between 1 and 7 data12 The number of cycles before the read strobe is asserted RDON Valid between 0 and 7 data13 The number of cycles before the write strobe is asserted WRON Valid between 0 and 7 data1 4 The number of cycles before the write data is output WDON Valid between 1 and 7 data15 The number of cycles before the chip select is asserted CSON Valid between 0 and 7 True if all parameters are valid and exclusive otherwise false Bus Controller R_BSC_Create R_BSC_Destroy Ensure that function R_BSC_Create is called once before using this function The endian mode of the CPU is selected by the MDE pin low little endian high big endian e Port Function Control registers PFCRO and PFCR5 are modified by this function The cycle count parameters are not checked
149. atch A signal e Compare Match A DTC trigger control R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 87 PDL_TMR_CM_A_DTC_TRIGGER_DISABLE or PDL_TMR_CM_A_DTC_TRIGGER ENABLE Disable or enable activation of the DTC when a Compare Match A occurs e Compare Match B DTC trigger control PDL_TMR_CM_B_DTC_TRIGGER_DISABLE or PDL_TMR_CM_B_DTC_TRIGGER_ENABLE Disable or enable activation of the DTC when a Compare Match B occurs ENESAS Under development Preliminary Specification RX610 Group Description 2 2 Return value Category Reference Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 88 Specifications in this preliminary version are subject to change 4 Library Reference data3 Configure the output control If multiple selections are required use to separate each selection The default settings are shown in bold e Output control for pin TMOy y 0 or 2 for n 0 or 1 PDL_TMR_OUTPUT_IGNORE_CM_A or No change if a compare match A occurs PDL_TMR_OUTPUT_LOW_CM_A or 0 is output if a compare match A occurs PDL_TMR_OUTPUT_HIGH_CM_Aor 1 is output if a compare match A occurs PDL_TMR_OUTPUT_INV_CM_A The output toggles if a compare match A occurs PDL_TMR_OUTPUT_IGNORE_CM_B or No change if a compare match B occurs PDL_TMR_OUTPUT_LOW_CM_Bor 0 is output if a compare match B occurs PDL_TMR_OUTP
150. ation for a new calculation 2 Disabling the calculator and enabling low power mode 3 Writing data to be used for the calculation 4 Reading the calculation result R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 18 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 19 12C Bus Interface Driver The driver functions support the use of the two 12 modules providing the following operations 1 Configuration for use including e Automatic clock setting using transfer rate as an input e Automatic interrupt control e Automatic I O pin configuration 2 Disabling modules that are no longer required and enabling low power mode 3 Transmitting data in Master mode 4 Receiving data in Master mode 5 Completing the reception of data that has utilised the DMAC or DTC 6 Monitoring the bus and handling the reception of data in Slave mode 7 Transmitting data in Slave mode 8 Control of one or more units including bus lock up recovery support 9 Reading the status of a module Note The Clock Generation Circuit must be configured before configuring any I C module R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 19 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 20 10 bit Analog to Digital Converter Driver The driver functions
151. be stored Specify PDL_NO_PTR if it is not required data4 Where the current destination address shall be stored Specify PDL_NO_PTR if it is not required data5 Where the current transfer byte count shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Category DMA controller Reference R_DMAC_ Create Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 56 Ifa Transfer End Interrupt request flag is set to 1 the flag will be cleared to 0 by this function ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions tinclude r_pdl_definitions h void func void uint16_t StatusValue uint32_t SourceAddr Read the status and current source address for channel 2 R_DMAC_GetStatus 2 amp StatusValue amp SourceAddr PDL_NO_PTR PDL_NO_PTR R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 57 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 2 9 Data Transfer Controller 1 R_DTC_Set Synopsis Prototype Description Return value Categor
152. bject to change 4 Library Reference 4 R_IIC_MasterReceive Synopsis Prototype Description Read data from a slave device bool R_IIC_MasterReceive uint8_t data1 Channel selection uint16_t data2 Channel configuration uint16_t data3 Slave address uint8_t data4 Data start address uint16_tdata5 Receive threshold void func Callback function uint8_t data6 Interrupt priority level Read data over an 12C channel and store it data1 Select channel IICn where n 0 or 1 data2 Configure the channel The default setting is shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_IIC_DMAC_DTC_TRIGGER_DISABLE or PDL_IIC_DMAC_TRIGGER_ENABLE or PDL_IIC_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a data byte is received data3 The address of the slave device data4 The start address of the storage area for the expected data If the DMAC or DTC shall be used to handle the received data specify PDL_NO_PTR data5 The number of bytes to be received If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Return value Category Reference Transfer method Parameter Pollin PDL_NO_FUNC This funct
153. bject to change RX610 Group 5 Usage Examples 5 11 5 Slave mode with DMAC In the following example data is received using DMAC channel 2 and transmitted using DMAC channel 3 The slave will respond to one 7 bit address and one 10 bit address The same EEPROM address locations are then read out in two bursts DMAC channel 2 is used to handle the data transfer Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_dmac h RPDL device specific definitions include r_pdl_definitions h Callback prototype void slave_event_handler void IIC application definitions define SLAVE_CHANNEL 0 define MCU_ADDRESS_UPPER 0x0100 define MCU_ADDRESS_LOWER 0x12 define MCU_ADDRESS_0 0x12 define MCU_ADDRESS_1 0x0124 define BUFFER_SIZE 10 Global variables volatile bool transmission_completed volatile bool reception_completed volatile uint8_t slave_data_received BUFFER_SIZE 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 volatile uint8_t slave_data_storage_0 BUFFER_SIZE 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Ox00 0x00 0x00 volatile uint8_t slave_data_storage_1l BUFFER_SIZE 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 void main void uint16_t status_flags 0 uint32_t Count 0 uint32_t 1 uint32_t slave_0_pt
154. called before any use of this function e This function configures each I C pin that is required for operation lt also disables the alternative modes on those pins The 7 or 10 bit slave addresses should use the format b15 b8 b7 b1 bO z 7 bit address 3 b15 b11 b10 b1 bO 10 bit address The timing limits depend on the frequency of the internal reference clock IRC Transfer _ rate tise Fl fan UCBRH Dtirc UCBRL 1t ire The maximum transfer rate is given when ICBRH ICBRL 0 the minimum when ICBRH ICBRL 31 The absolute limits with zero rise and fall times are frcik MHz finc 50 125 32 8 feck 1 781 kbps to 25 0 Mbps 195 kbps to 6 25 Mbps 500 kbps to 16 0 Mbps 125 kbps to 4 00 Mbps froik 2 391 kbps to 12 5 Mbps 97 7 kbps to 3 13 Mbps 250 kbps to 8 00 Mbps 62 5 kbps to 2 00 Mbps frok 4 195 kbps to 6 25 Mbps 48 8 kbps to 1 56 Mbps 125 kbps to 4 00 Mbps 31 3 kbps to 1 00 Mbps froik 8 97 7 kbps to 3 13 Mbps 24 4 kbps to 781 kbps 62 5 kbps to 2 00 Mbps 15 6 kbps to 500 kbps froik 16 48 8 kbps to 1 56 Mbps 12 2 kbps to 391 kbps 31 3 kbps to 1 00 Mbps 7 81 kbps to 250 kbps froik 32 24 4 kbps to 781 kbps 6 10 kbps to 195 kbps 15 6 kbps to 500 kbps 3 91 kbps to 125 kbps froik 64 12 2 kbps to 391 kbps 3 05 kbps to 97 7 kbps 7 81 kbps to 250 kbps 1 95 kbps to 62 5 kbps froik 128 6 10 kbps to 195 kbps 1 53 kbps to 48 8 kbps 3 91 kbps to 125 kbps 977 bps to 31 3 kbps The actual ris
155. called when the number of received bytes reaches the threshold number Either the function to be called when each byte is received or DMAC PDL_NO_FUNC if the callback function specified in R_DMAC_ Create will be used DTC The function to be called at the interval specified in R_DTC_Create func2 The function to be called if a receive error occurs Specify PDL_NO_FUNC to ignore errors True if all parameters are valid and the operation completed False if a parameter was out of range SCI R_SCI_Create R_SCI_Control R_SCI_GetStatus ENESAS Under development Preliminary Specification RX610 Group Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 122 Specifications in this preliminary version are subject to change 4 Library Reference The maximum number of characters to be received is 65535 e Wait until a transmission on the same channel is complete before calling this function If a callback function is used please see the notes on callback function usage in 86 If polling mode is used the RXI flag will be used to manage the data reception If the SCI channel s control registers are directly modified by the user this function may lock up e If no error callback function func2 is specified the error flags are cleared automatically to allow the reception process to complete Callback functions are executed by the interrupt processing function This mea
156. channel AN14 Scan mode For unit O channels ANO to AN2 For unit 1 channels AN4 to AN6 For unit 2 channels AN8 to AN10 For unit 3 channels AN12 to AN14 PDL _ADC_10 CHANNELS OPTION 4 Single mode For unit 0 channel ANS For unit 1 channel AN7 For unit 2 channel AN11 For unit 3 channel AN15 Scan mode For unit O channels ANO to AN3 For unit 1 channels AN4 to AN7 For unit 2 channels AN8 to AN11 For unit 3 channels AN12 to AN15 ENESAS Under development RX610 Group Preliminary Specification Specifications in this preliminary version are subject to change Description 2 2 Scan mode 4 Library Reference PDL_ADC_10_MODE_ SINGLE or PDL_ADC_10_MODE_CONTINUOUS_SCAN or PDL_ADC_10 MODE ONE _CYCLE_SCAN Select single mode continuous scan mode or one cycle scan mode e Trigger selection PDL_ADC_10_TRIGGER_SOFTWARE or Software PDL_ADC_10_TRIGGER_TPU_UNITO or Timer TPU channels 0 to 5 PDL_ADC_10_TRIGGER_TPU_UNIT1 or Timer TPU channels 6 to 11 PDL_ADC_10_TRIGGER_TMR or Units O and 1 compare match A from TMR channel 0 Units 2 and 3 compare match A from TMR channel 2 PDL_ADC_10_TRIGGER_ADTRGO or PDL_ADC_10_TRIGGER_ADTRG1 or PDL_ADC_10_TRIGGER_ADTRG2 or PDL_ADC_10_TRIGGER_ADTRG3 or ADTRGO input pin valid for units O or 1 ADTRG1 input pin valid for unit 1 only ADTRG2 input pin valid for units 2 or
157. ci a deals 4 47 5 RUBS C2 GetStatus tars td A E a E E Ii 4 48 4 2 8 DMAG Ontrolle ts cc coi a a E 2 i dd Ads 4 49 1 RiDMAG Greate ta aaa 4 49 2 ReDMAG Destroy tise cee ae a ad Areata dee ha dat 4 52 3 R DMAGS Control nitne en Huta a due a Mie cc teed a a ewes ONG daii Eai 4 53 4 RuDMAG GetStatus avec os in n aiae ab din Gv en OAM ries 4 56 4 2 9 Data Transter Controller to a a dada il Ole 4 58 1 REDTOE Oi e de E A e a bs LE 4 58 2 O E A A a eea a Quedes Piece Selon e a Sauces a a clade ced 4 59 3 Ric DEG DESTOV citada a ani A dd ad daa dad 4 63 4 RA DTO CONTO E E EE A E E ai 4 64 5 R DTC GetStatus vanidad ba cdi 4 66 4 2 10 Timer Pulse Unit Vito a aaa io aida eduubsreecdeatlevvebilereecschsteud tesereetbense 4 68 1 A onesdcbevbesensestustishseavelsbevihl welt edvelivtvebitees cavebsvext eteceeeenss 4 68 gt A R R gt A on MawonANMooarnoaunwon aNawonaANonuauanwonAXMowonAaNManwonaNiownvnoananwnaXMwon aNawn lt UE A PB YS A A A SO an we THK wa Sr a A wa wee WH we ma DM WH o SKS Hew rw mk N o al gt E po R TPU DeSttO yc avid nutes A ceed eee lier been eae Gate a Aree ad 4 74 RET PU 2GOntrol essed Section A dt A de teu heals ela bt ted 4 75 RETPUS REA r PNG oP E a a a Dd 4 77 Programmable Pulse Generator ccccccceeeceesceceeeee cee eeeaaeeeeeeeeceaeeesaaeeeeaeeseeeeesaeeesaaeeseaeeeeaees 4 79 R
158. cted i p 1 High Smart card mode b7 to b6 b5 b4 b3 b2 b1 bO Error detection Trahsmitstatus RxD pin 0 Overrun Error signal Parity 0 voltage level 0 No error 0 No error 0 No error 0 Active 0 Low 1 Detected 1 Detected 1 Detected 1 Complete 1 High data3 The storage location for the last byte that was received Specify PDL_NO_PTR ifthis information is not required data4 The storage location for the number of characters that are have been transmitted in the current transmission Specify PDL_NO_PTR if this information is not required data5 The storage location for the number of characters that are have been received in the current reception process Specify PDL_NO_PTR if this information is not required Return value Category Reference Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 125 True if all parameters are valid and the operation completed false if a parameter was out of range SCI R_SCI_Send R_SCI_Receive The error flags are not modified by this function They are cleared when a new reception process is started ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions tinclude r_pdl_definitions h uint8_t Sta
159. ction PDL_SCI_PARITY_EVEN or PDL_SCI_PARITY_ODD Select even or odd parity bit Block transfer mode selection PDL_SCI_BLOCK_MODE_OFF or PDL_SCI BLOCK_MODE_ON Control Block transfer mode GSM mode selection PDL_SCI_GSM_MODE_OFF or PDL_SCI GSM_MODE_ON Control GSM mode SCKn pin output control Normal mode GSM mode PDL_SCI_SCK_OUTPUT_OFF or I O pin Not applicable PDL_SCI_SCK_OUTPUT_LOW or Not applicable Fixed low PDL_SCI_SCK_OUTPUT_ON or Outputs the bit clock PDL_SCI_SCK_OUTPUT_HIGH Not applicable Fixed high data3 The format must be either The transfer bit rate in bits per second If the on chip baud rate generator is selected the clock source and division values will be calculated using this value Or one selection from each of the following using to separate each selection e CKS selection PDL_SCI_PCLK_DIV_1 or PDL_SCI_PCLK_DIV_4 or PDL_SCI_PCLK_DIV_16 or PDL_SCI_PCLK_DIV_64 Select the internal clock signal PCLK 1 4 16 or 64 as the baud rate generator clock source e ABCS selection ignored for synchronous or smart card mode PDL_SCI_CYCLE_BIT_16 or PDL_SCI CYCLE BIT_8 Select 16 or 8 base clock cycles for one bit period b31tob24 b23 to b8 b7 b0 0 the transfer bit rate A value between 0x100 and OxFFFFO0 that is nearest to The BRR register value ENESAS
160. curs during this polling process the function will terminate If the 12C channel s control registers are directly modified by the user this function may lock up e Use R_IIC_GetStatus to determine if the transfer was successful Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t data_array 5 void func void Read 5 bytes from device OxAA on channel 1 using polling R_IIC_MasterReceive 1 PDL_NO_DATA OxAA data_array 5 PDL_NO_FUNC 0 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 139 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 5 R_IIC_MasterReceiveLast Synopsis Prototype Description Return value Category Reference Complete a DMAC or DTC based read process bool R_IIC_MasterReceiveLast uint8_t data1 Channel selection uint8_t data2 Data storage address Read one data byte with NACK and stop data1 Select channel IICn where n 0 or 1 data2 The storage location for the data byte True if all parameters are valid and the function completed otherwise false 12C R_IIC_MasterReceive Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010
161. d 10 PDL TPU CLK PCLK DIV 4096 or PCLK 4096 Valid for n 3 and 9 PDL_TPU_CLK_TCLKA or TCLKA A or TCLKA B pin input Valid for n 0 to 5 PDL_TPU_CLK_TCLKB or TCLKB A or TCLKB B pin input Valid for n 0 1 and 2 PDL_TPU_CLK_TCLKC or TCLKC A or TCLKC B pin input Valid for n 0 2 4 and 5 PDL_TPU_CLK_TCLKD or TCLKD A or TCLKD B pin input Valid for n 0 and 5 PDL_TPU_CLK_TCLKE or TCLKE pin input Valid for n 6 to 11 PDL_TPU_CLK_TCLKF or TCLKF pin input Valid for n 6 7 and 8 PDL_TPU_CLK_TCLKG or TCLKG pin input Valid for n 6 8 10 and 11 PDL_TPU_CLK_TCLKH or TCLKH pin input Valid for n 6 and 11 PDL_TPU_CLK_TPU The overflow underflow signal from TPU n 1 Valid for n 1 4 7 and 10 e Counter clock edge selection PDL_TPU_CLK_RISING or PDL_TPU_CLK_BOTH PDL_TPU_CLK_FALLING or The clock signal shall be counted on falling rising or both edges e Counter clearing PDL_TPU_CLEAR_DISABLE or Clearing is disabled PDL_TPU_CLEAR_CM_Aor Cleared after a TGRA compare match occurs PDL_TPU_CLEAR_CM Bor Cleared after a TGRB compare match occurs PDL_TPU_CLEAR_CM_C or Cleared after a TGRC compare match occurs Valid for n 0 3 6 and 9 PDL_TPU_CLEAR_CM_D or Cleared after a TGRD compare match occurs Valid for n 0 3 6 and 9 PDL_TPU_CLEAR_SYNC Cleared by counter clearing on
162. d 255 0 256 transfers data6 The block size for each transfer Valid between 0 and 255 0 256 units Ignored in normal or repeat mode Return value True if all parameters are valid and exclusive otherwise false Category Data Transfer Controller Reference R_DTC_Create Remarks e This function must be called in order to start the DTC R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 64 l ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_dtc h RPDL device specific definitions tinclude r_pdl_definitions h void func void Start the controller R_DTC_Control PDL_DTC_START PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA Re enable CMTO as a DTC trigger R_DTC_Control PDL_DTC_TRIGGER_CMTO PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_DATA i Update the destination address for CMTO triggered transfers R DIC Control PDL_DTC_STOP PDL_DTC_START PDL_DTC_UPDATE_DESTINATION dtc_cmt0_transfer_data PDL_NO_PTR 0x0000BBOO PDL_NO_DATA PDL_NO_DATA R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 65 l ENESAS Under development Preliminary Specification RX610 Group Specifications in
163. d APIs by peripheral function Table 4 1 Renesas Embedded API List Category Number Name Description Clock Generation Circuit e R_CGC_Set Configure the clock generation circuit Interrupt controller R_INTC_CreateExtInterrupt Configure an external interrupt pin R_INTC_CreateFastinterrupt Assign handlers for the fixed vector interrupts R_INTC_CreateExceptionHandlers Enable faster interrupt processing for one interrupt R_INTC_ControlExtInterrupt External interrupt control R_INTC_GetExtInterruptStatus Read the external interrupt status R_INTC_Read Read an interrupt register R_INTC_Write Update an interrupt register R_INTC_Modify Modify an interrupt register I O port R_IO_PORT_Set Configure an I O port R_IO_PORT_ReadControl Read an I O port s control registers IO PORT_ModifyControl Modify an I O port s control registers O PORT Read Read data from an I O port O PORT Write Write data to an I O port O PORT Modify Check the pin states on an I O port Modify the pin states on an I O port 1O_ PORT Compare LPC_ReadBackup O PORT Wait Wait for a match on an I O port Port F PFC Read Read a PFC register ah ar PFC_Write Write to a PFC register PFC_Modify Modify a PFC register MCU operation MCU_ Control Control the operation of the MCU MCU
164. d rele ld 4 127 Ri GR ICO ale sc rt cas o A toa li 4 127 MORC DESTOV Aia A LE A A Leak ade eas 4 128 RECREO Wilson A a a e eh a 4 129 EAS o MEE O O o OO 4 130 PGC BUSNie aCe a a e ao ls o e ld cedo o di EA ease 4 131 PANG Create ii A DO DA a DITA aaa Th ee es 4 131 RICAS MY a en o e A 4 135 REC Master SO iii A deen Thawed een E O AT ies 4 136 RIC M ster Rece ezoin A A Heine st 4 138 R 110 MasterReceliveldS Ei AA A neces die 4 140 Rill Slave MONO tt A ae IO tes 4 141 Rol SlaVveSend ii A A AS A ADS 4 143 RUC Controla LR IIS ea Ae ee es 4 144 REC iGetStatusssss ein A Mire etd Pa eee eet La 4 145 10 bit Analog to Digital Converter cccccceceeeneeeeeeeeeaaeeeeneeceaeeesaaeeeeaeeseeeeeseaaeeeeaeeenees 4 147 R ADC 10 Cra Joke Qe i ea ieee AAA ee 4 147 R ADC 10 DestrOV iii A deed Ale Av cda AA dads 4 150 RADO 10 Con Oli Saeed Maa ied eae He ee eee ees 4 151 R ADG 1 0 RedOne el al ee i ad SRA ees 4 152 10 bit Digital to Analog Converter ccceccceceeeeeeeeeeteeeeeaaeeeeeeeceaeeesaaeeseaaeseeeeeceaeeesnaeeseneees 4 153 REDACTOR id E oe Ahh heds eave elt aad eth Ge ead eee 4 153 R DAC TO DESITOY 220 steele ade a A nth a delenit aes radia athe 4 154 R DAG 10 WI A A th en ea a Le o 4 155 5 6 Usage Examples 2 0 A A a A cues adh ea Aah A a aa 5 1 Delis IMterruptcoOn Oli ns 5 2 52 WOR OM ies a in e e a tat ios e 5 4 5 31 BUS Controller cti A AA a ee 5 6 54 DMAcoOntollriiiiicii a A A AAA Ad AAA Ada 5 8 5 5
165. de on the next action Figure 5 21 An example of reading data from the EEPROM DO ome A ome EDEN Figure 5 22 The bus activity showing 4 bytes being transmitted by the EEPROM R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 33 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 5 Usage Examples 3 Repeated Start Send 1 byte to the EEPROM to update the lower address bits and do not stop R_IIC_MasterSend 1 PDL_IIC_STOP_DISABLE EEPROM_ADDRESS 0x37 1 PDL_NO_FUNC 0 Read data from the EEPROM A repeated start will occur R_IIC_MasterReceive 1 PDL_NO_DATA EEPROM _ADDRESS data_storage 2 PDL_NO_FUNC 0 Figure 5 23 Set the lower address to 37h and then read 2 bytes Slave address Memory address Slave address PR A a JA oe A Figure 5 24 The bus activity showing the Repeated Start condition when switching to the Read R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 34 process ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 11 2 Master mode with DMAC In the following example data is written to an EEPROM in two bursts DMAC channel 3 is used to handle the data transfer The same EEPROM address locations are then read out
166. der development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples OQ Pe OP OO eo OGO OGO i Initialise the system clocks and enable the BCLK output R_CGC_Set 12 5E6 100E6 50E6 25E6 PDL_CGC_BCLK_ i Write to external areas cs7_location_16 0xAA55 csl_location_8 OxAA Disable area CS1 R_BSC_Destroy 1 Y Figure 5 3 Example of Bus Controller use R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 7 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 4 DMA controller The following examples show the use of triggers by software IRQ pin edge detection and SCI transmission 1 Software and IRQ triggers Channel 0 will copy the string Renesas RX610 into the destination area when a falling edge occurs on pin IRQ3 B Channel 1 will copy the string Hello World into the destination area as soon as it is enabled PDL functions and definitions include r_pdl_dmac h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions P include r_pdl_definitions h Required for this example qu p include lt string h gt Callback function prototype v
167. device specific definitions include r_pdl_definitions h void func void uint8_t irq_status Read the IR flag and pin state for IRQ5 R_INTC_GetExtInterruptStatus PDL_INTC_IRQ5 irg_status y ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 6 R_INTC Read Synopsis Read an interrupt register Prototype bool R_INTC_Read uint8_t data1 Register selection uint8_t data2 Register number uint8_t data3 Data storage location Description Read an interrupt register and store the value data1 e The register to be read PDL_INTC_REG_IPL or Select the current CPU interrupt priority level or PDL_INTC_REG_IR or Interrupt Request register or PDL_INTC_REG_ISELR or Interrupt Request Destination Setting register or PDL_INTC_REG_IER or Interrupt Request Enable register or PDL_INTC_REG_IPR Interrupt Priority register data2 The register number IPL Ignored IR Between 16 and 253 10h to FFh ISELR Between 28 and 252 1Ch to FFh IER Between 2 and 15 02h to 1Fh IPR Between 0 and 148 00h to 8Fh data3 The location where the register s value shall be stored Return value True if all parameters are valid and exclusive otherwise false Category Interrupt control Reference R_IN
168. e Assigning an interrupt to be processed using the Fast Interrupt route Assigning handlers for the fixed exception interrupts Controlling an external interrupt input Reading the status of an external interrupt Reading an interrupt register Writing to an interrupt register Modifying an interrupt register R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Page 2 4 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 5 1 0 Port Driver The driver functions support the use of the I O port pins providing the following operations 1 Configuration for use 2 Reading the pin or port configuration 3 Modifying the pin or port configuration 4 Reading a pin or 8 bit port value 5 Writing to a pin or 8 bit port 6 Comparing a pin or 8 bit port with a supplied value 7 Modifying a pin or 8 bit port using a logical operation 8 Waiting until a pin or 8 bit port matches a supplied value R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Page 2 5 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 6 Port Function Control Driver The driver functions support access to the Port Function Control PFC registers which select the mode of operation for some I O pins The other driver functions modify the PFC registers automatically For peripherals tha
169. e RX610 Group 2 Driver 2 9 Bus Controller Driver The driver functions support the control of the external bus providing the following operations 1 Configuration of the controller 2 Configuration of the eight address space areas 3 Disabling an area that is not required 4 Controlling the bus controller 5 Reading the status of the controller R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 9 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 10 DMA Controller Driver The driver functions support the control of the Direct Memory Access DMA controller providing the following operations 1 Configuration for use including e Access to all control bits e Automatic interrupt control 2 Disabling DMA channels that are no longer required and enabling low power mode 3 Control of one or more channels 4 Reading the status and operation registers of a channel R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 10 RENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 2 Driver 2 11 Data Transfer Controller Driver The driver functions support the control of the Data Transfer Controller providing the following operations 1 Setting the central options 2 Configuration for use including support for chain transfers 3 Dis
170. e and fall times will not be zero Using the limits from the 12C specification Rise time rate lt 100 kbps 1000 ns 100 kbps lt rate lt 400 kbps 300 ns 400 kbps lt rate lt 1 Mbps 120 ns Fall time rate lt 400 kbps 300 ns 400 kbps lt rate lt 1 Mbps 120 ns Maximum rate 1 Mbps The achievable transfer rates are frcLk MHz IRC 50 12 5 32 8 PCLK 1 658 kbps to 1 Mbps 175 kbps to 1 Mbps 446 kbps to 1 Mbps 116 kbps to 1 Mbps PCLK 2 316 kbps to 1 Mbps 86 7 kbps to 1 Mbps 217 kbps to 1 Mbps 57 8 kbps to 1 Mbps PCLK 4 175 kbps to 1 Mbps 45 9 kbps to 1 Mbps 116 kbps to 1 Mbps 30 0 kbps to 806 kbps PCLK 8 86 7 kbps to 1 Mbps 23 7 kbps to 658 kbps 57 8 kbps to 1 Mbps 15 3 kbps to 446 kbps PCLK 16 45 9 kbps to 1 Mbps 12 0 kbps to 316 kbps 30 0 kbps to 806 kbps 7 73 kbps to 217 kbps PCLK 32 23 7 kbps to 658 kbps 6 06 kbps to 175 kbps 15 3 kbps to 446 kbps 3 89 kbps to 116 kbps PCLK 64 12 0 kbps to 316 kbps 3 04 kbps to 86 7 kbps 7 73 kbps to 217 kbps 1 95 kbps to 57 8 kbps PCLK 128 6 06 kbps to 175 kbps 1 52 kbps to 45 9 kbps 3 89 kbps to 116 kbps 975 bps to 30 0 kbps R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 133 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_iic h RPDL device
171. e enabled by default Specify O for no change PDL_BSC_AOBCO_DISABLE Disable the output of the AO BCO signal When disabled the pin can be used as an input only PDL_BSC_A1_DISABLE Disable the output of the A1 signal When disabled the pin can be used as an input only PDL_BSC_A2 DISABLE Disable the output of the A2 signal When disabled the pin can be used as an input only PDL_BSC_A3_DISABLE Disable the output of the A3 signal When disabled the pin can be used as an input only PDL_BSC_A4 DISABLE Disable the output of the A4 signal When disabled the pin can be used as an input only PDL_BSC_A5_DISABLE Disable the output of the A5 signal When disabled the pin can be used as an input only PDL_BSC_A6_DISABLE Disable the output of the A6 signal When disabled the pin can be used as an input only PDL_BSC_A7_DISABLE Disable the output of the A7 signal When disabled the pin can be used as an input only PDL_BSC_A8_ DISABLE Disable the output of the A8 signal ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Description 2 2 PDL_BSC_A9 DISABLE Disable the output of the A9 signal PDL_BSC_A10_DISABLE Disable the output of the A10 signal PDL_BSC_A11_DISABLE Disable the output of the A11 signal PDL_BSC_A12
172. e or compare match D Overflow PDL_INTC_VECTOR_TGI7A PDL_INTC_VECTOR_TGI7B PDL_INTC_VECTOR_TCI7V PDL_INTC_VECTOR_TCI7U Timer Pulse Unit channel 7 Input capture or compare match A Input capture or compare match B Overflow Underflow PDL_INTC_VECTOR_TGI8A PDL_INTC_VECTOR_TGI8B PDL_INTC_VECTOR_TCI8V PDL_INTC_VECTOR_TCI8U Timer Pulse Unit channel 8 Input capture or compare match A Input capture or compare match B Overflow Underflow PDL_INTC_VECTOR_TGI9A PDL_INTC_VECTOR_TGI9B PDL_INTC_VECTOR_TGI9C PDL_INTC_VECTOR_TGI9D PDL_INTC_VECTOR_TCI9V Timer Pulse Unit channel 9 Input capture or compare match A Input capture or compare match B Input capture or compare match C Input capture or compare match D Overflow PDL_INTC_VECTOR_TGI10A Input capture or compare match A PDL_INTC_VECTOR_TGI10B ae peed Input capture or compare match B PDL_INTC_VECTOR_TCI10V 10 gt Overflow PDL_INTC_VECTOR_TCI10U Underflow PDL_INTC_VECTOR_TGI11A Input capture or compare match A PDL_INTC_VECTOR_TGI11B Timer Pulse Input capture or compare match B PDL_INTC_VECTOR_TCI11V PDL_INTC_VECTOR_TCI11U Unit channel 11 Overflow Underflow PDL_INTC_VECTOR_CMIAO PDL_INTC_VECTOR_CMIBO PDL_INTC_VECTOR_OVIO 8 bit timer TMR channel 0 Compare match A Compare match B
173. eferences Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 39 Read the status flags bool R_LPC_GetStatus uinti6_t data Data pointer Read the registers that control module or CPU operation data The status flags shall be stored in the format below b15 b14 b8 0 No activity 1 An external interrupt has caused an exit from deep software standby mode 0 followed by an internal reset b7 b6 b4 b3 b2 bi bO Deep Software Standby cancel request detection 0 No activity 1 The exit from deep software standby was caused by a valid edge on pins IRQn A or NMI NMI 0 IRQ3 A IRQ2 A IRQ1 A IRQO A True Low Power Consumption control registers R_LPC_Create R_LPC_Control Ifa flag is set to 1 it shall be automatically cleared to O by this function RPDL definitions include r_pdl_lpc h RPDL device specific definitions include r_pdl_definitions h void func void uint1l6_t status_flags Find out what caused the exit from deep software standby R_LPC_GetStatus amp status_flags i ENESAS Under development RX610 Group 4 2 7 1 Preliminary Specification Specifications in this preliminary version are subject to change Bus Controller R_BSC _ Create Synopsis Prototype bool R_BSC_Create uint32_t data1 uint32_t data2 uint8_
174. el 0 R_IIC_SlaveSend 0 data_array 5 i R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 143 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 8 R_IIC_Control Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 Page 4 144 lC channel control bool R_IIC_Control 4 Library Reference uint8_t data1 Channel selection uint8_t data2 Control options Modify the operation of the selected 2C channel data1 Select channel IICn where n 0 or 1 data2 Control the channel If multiple selections are required use to separate each selection e Stop generation PDL_IIC_STOP Issue a Stop condition e NACK generation PDL_IIC_NACK Set the Acknowledge bit to the NACK state Pin control PDL_IIC_SDA_LOW or PDL_IIC_SDA HI Z Set the SDA pin to low level or high impedance PDL_IIC_SCL_LOW or PDL_IIC_SCL_HI_Z e Extra clock cycle generation Set the SCL pin to low level or high impedance PDL_IIC_CYCLE_SCL Generate an extra clock cycle on the SCL pin This can be used in Master mode to try and unlock a slave device that is holding the SDA signal low e Reset control PDL_IIC_ RESET Carr
175. el selection uint8 tdata2 Channel control Stops SCI transmission or reception data1 Select channel SCIn where n 0 to 6 data2 Control the channel If multiple selections are required use to separate each selection e Select the process to be stopped Stop the transmission process PDL_SCI_STOP_TX If a reception process is active the transmit output will not become idle until the reception process has stopped Stop the reception process If a transmission process is active the receive error flags PDL eee may be set erroneously These can be ignored and will be cleared when a new reception process is started The option PDL_SCI_STOP_TX_AND_RX can be used to select both processes If both processes are selected transmission and reception will stop immediately e Generate a Space or Mark signal when idle Set the idle output to Space logic 0 POE SOLO TEMES PASE This can be used to generate a Break condition PDL_SCI_OUTPUT_MARK Set the idle output to Mark logic 1 e Error flag control PDL_SCI_CLEAR_RECEIVE_ERROR_FLAGS Try to clear the receive error flags Manual SCK control PDL_SCI_GSM_SCK_STOP or Disable or enable the clock output can be used while GSM PDL_SCI_GSM_SCK_START mode is enabled True if all parameters are valid otherwise false SCI R_SCI_Send R_SCI_Receive R_SCI_GetStatus None EN
176. elopment Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 1 Introduction 1 Introduction The Renesas Peripheral Driver Library RPDL is a unified API for controlling the peripheral modules on the microcontrollers made by Renesas Electronics Renesas Peripheral Driver Library Peripherals supported by the RPDL Target MCU Figure 1 1 System configuration with all peripherals supported by RPDL User application Renesas Peripheral Driver Library Peripherals supported by the RPDL Target MCU Figure 1 2 System configuration with middleware taking direct control of some peripherals The library is packaged as a Abinary file containing all of the peripheral driver functions b Header files containing the information that the user needs to call any of the functions from their own application code and c Interrupt handlers supplied as source code For best use of this library It is required that the user will have the following documents as a minimum i The schematic ii The MCU hardware manual iii This RPDL API User s manual The binary file is produced using the Renesas RX C compiler It should be usable by another linker that conforms to the Renesas Application Binary Interface The coding standards and naming conventions are specified by Renesas The driver source code is tested for compliance with the MISRA C 2004 guidelines R20UT
177. er byte is the value for TMR3 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 97 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions tinclude r_pdl_definitions h void func void Load the unit 1 counter and constants R_TMR_ControlUnit 1 PDL_TMR_COUNTER PDL_TMR_TIME_CONSTANT_A PDL_TMR_TIME_CONSTANT_B OxAAFF 0x100 0x5600 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 98 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 8 R_TMR_ControlPeriodic 4 Library Reference Synopsis Control periodic operation Prototype bool R_TMR_ControlPeriodic uint8_tdata1 8 bit channel or 16 bit unit selection uint32_t data2 Configuration selection float data3 The new period or frequency float data4 The new pulse width or duty cycle Description Modify a periodic timer operation data1 PDL_TMR_TMRO or PDL_TMR_TMR1 or PDL_TMR_TMR2 or PDL_TMR_TMR3 or PDL_TMR_UNITO or PDL_TMR_UNIT 1 The channel n n 0 1 2 or 3 or unit n 0 or 1 to be configured data2 Select the options to be modified Use Peri
178. er control PDL_DMAC_TRIGGER_RESET If a peripheral is using a callback function and is also triggering the DMAC the trigger will need to be reset after each interrupt Specify this option and specify the trigger used for this channel when R_DMAC_ Create was called in parameter data3 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Description 2 2 The registers to be modified using the selected parameters The Transfer Source Address register PDL DMAC UPDATE SOURGE DMCSA using parameter data4 The Transfer Destination Address register PDL_DMAC_UPDATE_DESTINATION DMCDA using parameter data5 The Byte Count register DMCBC using PDL_DMAC_UPDATE_COUNT parameter data6 The Transfer Source Address reload POL DMAC UPDATE SOURCE RELOAD register DMRSA using parameter data7 The Transfer Destination Address reload PDL_DMAC_UPDATE_DESTINATION_RELOAD register MRDA using parameter data8 The Byte Count reload register DMRBO PDL_DMAC_UPDATE_COUNT_RELOAD using parameter data9 data3 The DMAC start trigger Specify PDL_NO_DATA if not required data4 The source address value Specify PDL_NO_PTR if not required data5 The destination address value Specify PDL_NO_PTR if not required data6 The number of
179. es of DMAC use 2 SCI transmission trigger DMAC Channel 3 will be used to transmit the string Renesas RX610 Then the string Hello World will be transmitted by polling PDL functions and definitions include r_pdl_dmac h include r_pdl_cgc h include r_pdl_intc h include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt Callback function prototype void DMAC3_transfer_end_handler void Data source and destination declarations const uint8_t source_string_1 Renesas RX610 const uint8_t source_string_2 Hello World Global flags volatile uint8_t sci_dma_transfer_complete volatile uint8_t break_required void main void Initialise the system clocks R_CGC_Set 12 5E6 1006 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 10 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples L_CGC_BCLK_DISABL Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 y Configure the RS232 port R_SCI_Create 1 PDL_SCI_RX_DISCONN ED PDL_SCI_8N1 115200 0 y Configure channel 3 R_DMAC_Create 3 PDL_DMAC_SINGLE PDL_DMAC_SOURC ESS PLUS PDL_DMAC_
180. evel detection is selected Disable or enable activation of the PDL_INTC_DMAC_DTC_TRIGGER_DISABLE or DMAC valid for n 0 to 3 or PDL_INTC_DMAC_TRIGGER_ENABLE or DTC valid for n 0 to 15 when a valid PDL_INTC_DTC_TRIGGER_ENABLE edge transition is detected on an IRQn pin func The function to be called when a valid condition is detected Specify PDL_NO_FUNC if no IRQn interrupt is required A function must be specified for the NMI pin data3 The IRQn interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func This value does not apply to the NMI pin and is ignored Return value True if all parameters are valid and exclusive otherwise false Category External interrupt Reference R_INTC_ControlExtInterrupt R_INTC_GetExtInterruptStatus R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 6 ztENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Remarks The selected interrupt pin is enabled automatically Port Function Control registers PFCR8 or PFCR9 are modified to select the IRQn pin e The appropriate I O port ICR and DDR registers are modified Please see the notes on callback function use in 86 e The NMI callback function should not return It should stop operati
181. executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions tinclude r_pdl_definitions h void func void Configure TMRO PCLK clear after a compare match A R_TMR_CreateChannel 0 PDL_TMR_CLK_PCLK_DIV_1 PDL_TMR_CLEAR_CM_A PDL_NO_DATA 0 199 99 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 86 RENESAS Under development RX610 Group Preliminary Specification Specifications in this preliminary version are subject to change 2 R_TMR_CreateUnit Synopsis Prototype uint8_t data1 uint32_t data2 uint8_t data3 uint16_t data4 uint16_t data5 uint16_t data6 void func1 void func2 void func3 uint8_t data7 Configure a timer TMR unit bool R_TMR_CreateUnit Channel selection Configuration selection Output control Register value Register value Register value Callback function Callback function Callback function Interrupt priority level 4 Library Reference Description 1 2
182. f the DTC PDL_TMR_PULSE_DTC_TRIGGER_ENABLE when the one shot period ends e Control the CPU during the one shot operation PDL_TMR_CPU_ON or Allow the CPU to run normally while the one shot operates Stop the CPU when the one shot timer starts del is al oe The CPU will re start when any valid interrupt occurs data3 The one shot time period in seconds func The function to be called when the one shot period ends Specify PDL_NO_FUNC for this function to wait for the timer to complete before returning You must always specify a function if PDL_TMR_CPU_OFF is selected to ensure that an interrupt will re start the CPU data4 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_Destroy ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 94 4 Library Reference Function R_CGC_Set must be called before any use of this function This function is an alternative to R_TMR_CreateChannel and R_TMR_CreateUnit This function stops the timer on completion so no other TMR function calls are required If an
183. fer for i 0 i lt BUFFER_SIZE i Tx_Data i uint8_t i 1 data_received false Set up the receive process no bus activity will occur R_SCI_Receive 3 PDL_NO_DATA Rx_Data transfer_size SCI3RxFunc R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 27 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples PDL_NO_FUNC Send data which will also receive data at the same time R_SCI_Send 3 PDL_NO_DATA Tx_Data transfer_size PDL_NO_FUNC y Ensure the receive interrupt has processed the last byte while data_received false Process the received data here SCI channel 3 receive complete handler void SCI3RxFunc void data_received true Figure 5 16 Example of Synchronous Transmission and Reception code R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 28 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 10 CRC calculator Figure 5 17 shows an example of CRC usage The payload and CRC checksum have been received from a remote unit The CRC calculator is used to check that the payload is correct Peripheral driver function prototypes include r_pdl_crc h RPDL device s
184. fications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_tmr h RPDL device specific definitions tinclude r_pdl_definitions h uint8_t Flags uint16_t Counter uint16_t CompareMatchA uint16_t CompareMatchB void func void Read the status flags and registers for TMR unit 0 R_TMR_ReadUnit 0 amp Flags amp Counter amp CompareMatchA amp CompareMatchB R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 103 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 2 13 Compare Match Timer 1 R_CMT_Create Synopsis Configure a CMT channel Prototype bool R_CMT_Create uint8_t data1 Timer channel selection uint16_t data2 Configuration selection float data3 Period frequency or register data void func Callback function uint8_t data4 Interrupt priority level Description Set up a Compare Match Timer channel and start the timer data1 The channel number n where n 0 1 2 or 3 data2 Configure the timer To set multiple options at the same time use to separate each value The default settings are shown in bold e Clock calculation The parameter data3 will specify the timer period PDL_CMT_PE
185. for validity Use the hardware manual to check these values ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions tinclude r_pdl_definitions h void func void Configure CS2 8 bit width no wait cycles R_BSC_CreateArea 2 PDL_BSC_WIDTH_8 0 0 0 0 0 0 0 0 1 0 0 1 0 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 45 l ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 3 R_BSC_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 46 Stop the External Bus Controller bool R_BSC_Destroy uint8_tdata Area selection Disable an external bus area data Select the external bus area CSn where n 0 to 7 to be disabled True Bus Controller R_BSC_CreateArea None RPDL definitions include r_pdl_bsc h RPDL device specific definitions include r_pdl_definitions h void func void Disable the CS4 area R_BSC_Destroy 4 ENESAS
186. g values refer to the section 4 2 Description of Each API The header files stdint h and stdbool h are included with the Renesas RX compiler Table 1 Data types Type Defined in Description Range bool stdbool h Boolean O false to 1 true float C Floating point 32 bits to uint8_t Unsigned 8 bits 0 to 255 uint16_t stdint h Unsigned 16 bits bt0 2 1 uint32 t Unsigned 32 bits 0 to 2 1 3 2 General definitions 3 2 1 PDL_NO_FUNC Used as a parameter when there is no applicable function 3 2 2 PDL_NO_PTR Used as a parameter when there is no applicable data location 3 2 3 PDL_NO_DATA Used as a parameter when there is no applicable data value 3 2 4 PDL_MCU_GROUP The family supported by this build of the driver library It is defined as RX610 A usage example is if PDL_MCU_GROUP RX610 error Wrong RPDL ndif 3 2 5 PDL_VERSION The version number of the RPDL library The number is stored in BCD format xx xx For example 0100h is v1 00 A usage example is const uint16_t rpdl_version_number PDL VERSION R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 3 1 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 Library Reference 4 1 API List by Peripheral Function Table 4 1 lists the Renesas Embedde
187. ge 4 92 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 4 R_TMR_CreateOneShot Synopsis Prototype Description Return value Category Reference R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 93 Configure and use a one shot timer bool R_TMR_CreateOneShot uint8_t data1 8 bit channel or 16 bit unit timer selection uint32_t data2 Configuration selection float data3 Period void func Callback function uint8_t data4 Interrupt priority level Set up a TMR timer channel or unit for one shot operation and start the timer data1 PDL_TMR_TMRO or PDL_TMR_TMR1 or PDL_TMR_TMR2 or The channel n n 0 1 2 or 3 or unit n n 0 or 1 to be PDL_TMR_TMR3 or configured PDL_TMR_UNITO or PDL_TMR_UNIT1 data2 Configure the timer Use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Output pin control For the duration of the one shot period generate a high level PDL_TMR_OUTPUT_HIGH or output PDL_TMR_OUTPUT_LOW or low level output or PDL_TMR_OUTPUT_OFF no output on pin TMOn For 16 bit operation the pin shall be TMO2 when n 1 DTC trigger control PDL_TMR_PULSE_DTC_TRIGGER_DISABLE or Disable or enable activation o
188. guring the MCU operation 6 Low Power Consumption These driver functions are used for selecting lower power consumption 7 Bus Controller These driver functions are used for configuring the external address bus data bus and chip select pins and handling any bus errors 8 DMA Controller These driver functions are used for configuring and controlling the transfer of data within the address space 9 Data Transfer Controller These driver functions are used for configuring and controlling the transfer of data triggered by peripheral interrupts 10 Timer Pulse Unit These driver functions are used for configuring and controlling the timers 11 Programmable Pulse Generator These driver functions are used for configuring and controlling the pulse generator outputs 12 8 bit Timer These driver functions are used for configuring and controlling the timers 13 Compare Match Timer These driver functions are used for configuring and controlling the timers 14 Watchdog Timer These driver functions are used for configuring and controlling the timer 15 Serial Communication Interface These driver functions are used to configure the serial channels and manage the transmission and or R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Page 2 1 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver reception of data across them 16 CR
189. hutdown IIC channel 1 R_IIC_Destroy 1 ENESAS 4 Library Reference Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 3 R_IIC_MasterSend Synopsis Write data to a slave Prototype uint8_t data1 uint16_t data2 uint16_t data3 4 Library Reference device bool R_IIC_MasterSena Channel selection Channel configuration Slave address uint8_t data4 Data start address uint16_t data5 void func uint8_t data6 Description Transmit data on the data1 Select channel IICn data2 Data count Callback function Interrupt priority level specified channel where n 0 or 1 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Start Repeated Start condition control PDL_IIC_START_ENABLE or Choose whether or not to issue a Start or Repeated Start PDL_IIC_START_DISABLE condition at the beginning of the transfer e Stop condition control PDL_IIC_STOP_ENABLE or Choose whether or not to issue a Stop condition at the end of PDL_IIC_STOP_DISABLE the transfer e DMAC DTC trigg er control PDL_IIC_DMAC_DTC_TRIGGER_DISABLE or PDL_IIC_DMAC_TRIGGER_ENABLE or PDL_IIC_DTC_TRIGGER_ENABLE Dis
190. ics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment commu
191. in PC2 PDL_IO_PORT_C_3 Port pin PCs PDL_IO PORT_C 4 Port pin PC PDL_IO PORT_C_5 Port pin PC PDL_IO PORT_C 6 Port pin PCs PDL_IO_PORT_C_7 Port pin PC7 PDL_IO PORT_D_O Port pin PDo PDL_IO_PORT_D_1 Port pin PD PDL IO PORT D 2 Port pin PD PDL_IO_PORT_D_3 Port pin PDs PDL IO PORT D 4 Port pin PD PDL_IO_PORT_D_5 Port pin PD PDL_IO PORT_D 6 Port pin PDs PDL_IO_PORT_D_7 Port pin PD PDL_IO PORT_E_0 Port pin PEo PDL_IO_PORT_E_1 Port pin PE PDL IO PORT E 2 Port pin PE PDL_IO_PORT_E_3 Port pin PEs PDL IO PORT E 4 Port pin PE PDL_IO_PORT_E 5 Port pin PEs PDL_IO PORT_E 6 Port pin PEs PDL_IO_PORT_E 7 Port pin PE PDL_IO PORT F 0 Port pin PF PDL_IO_PORT_F_1 Port pin PF PDL_IO_PORT_F_2 Port pin PF2 PDL_IO_PORT_F_3 Port pin PFs PDL IO PORT F4 Port pin PFa PDL_IO_PORT_F_5 Port pin PFs PDL_IO PORT_F_ 6 Port pin PFs PDL_IO PORT_G_O Port pin PGo PDL_IO PORT_G_1 Port pin PG PDL_IO_PORT_G 2 Port pin PG PDL_IO_PORT_G_3 Port pin PGs PDL IO PORT G4 Port pin PG PDL_IO_PORT_G_5 Port pin PGs PDL_IO PORT_G_6 Port pin PGs PDL_IO_PORT_G_7 Port pin PG PDL IO PORT_H_O Port pin PHo PDL_IO_PORT_H_1 Port pin PH PDL_IO_PORT_H_2 Port pin PH PDL_IO_PORT_H_3 Port pin PHs PDL IO PORT H 4 Port pin PH PDL_IO_PORT_H_5 Port pin PHs PDL_IO PORT_H 6 Port pin PHs PDL_IO_PORT_H_7 Port pin PH R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 19 Note Port pins PFx to PHx are available only
192. interrupt Further interrupts are prevented until the signal has returned to the high level Peripheral driver function prototypes include r_pdl_intc h include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t switch_swl_pressed volatile uint8_t irq2_low Callback function prototypes void IRQOHandler void void IRQOHandler void static void ReEnableIRQ2 void void main void uint8_t irq_status Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 y Configure the IRQO interrupt on pin IRQO A R_INTC_CreateExtInterrupt PDL_INTC_IROO PDL_INTC_FALLING PDL_INTC_A 7 IRQOHandler di Configure the IRQ1 interrupt on pin IRQ1 B R_INTC_CreateExtInterrupt PDL_INTC_IRO1 PDL_INTC_FALLING PDL_INTC_B 0 PDL_NO_FUNC i Configure the IRQ2 interrupt on pin IRQ2 A R_INTC_CreateExtInterrupt PDL_INTC_IRQ2 PDL_INTC_LOW PDL_INTC_A 7 IRO2Handler Y irq2_low false while 1 Poll the IRQ1 flag R_INTC_GetExtInterruptStatus PDL_INTC_IROQ1 amp irq_ status R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 2 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX61 610 Group 5 Usage Examples irq status amp 0x
193. interrupt can be processed until the callback function has completed e Ifthe channel is configured for phase counting mode the counter clock source setting is ignored e If buffer operation is selected for registers TGRA and TGRC input capture output compare is not valid for register TGRC If buffer operation is selected for registers TGRB and TGRD input capture output compare is not valid for register TGRD e If synchronous mode is required at least two channels must be enabled for synchronous operation ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_tpu h RPDL device specific definitions tinclude r_pdl_definitions h void func void Configure TPUO PCLK clear after a compare match A R_TPU_Create 0 0 PDL_TPU_CLK_PCLK_DIV_1 PDL_TPU_CLEAR_CM_A 0 199 99 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC 0 PDL_NO_FUNC PDL_NO_FUNC R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 73 l ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 2 R_TPU_Destroy Synopsis Disable a timer unit Prototype bool R_TPU_Destroy uint8_tdata Unit selection
194. ion are subject to change 4 Library Reference 2 R_MCU_GetStatus Synopsis Prototype Description Return value Functionality References Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 33 Read the MCU status bool R_MCU_GetStatus uinti6_t data Pointer to the variable where the status value shall be stored Read the status registers for the MCU data The status flags shall be stored in the format below b15 b14 b13 b12 b11 b10 b9 b8 Start up states User boot mode Boot mode External bus On chip ROM 0 0 Other mode 0 0 Other mode 00 16 bit O Disabled 0 Disabled 1 Boot mode 1 Boot mode 10 8 bit 1 Enabled 1 Enabled b7 b6 b2 b1 bO Endian Pin states O Little 0 1 Big MD1 MDO True MCU registers R_MCU_Control None RPDL definitions tinclude r_pdl_mcu h RPDL device specific definitions include r_pdl_definitions h void func void uintl6_t status Read the MCU status registers R_MCU_GetStatus amp status y ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 4 2 6 Low Power Consumption 1 R_LPC Create Synopsis Prototype
195. ion will continue until the required number of 9 bytes has been received or another event occurs Interrupts The function to be called when bus activity has stopped Either the function to be called when each byte is received or DMAC PDL_NO_FUNC if the callback function specified in R_DMAC_Create will be used DTC The function to be called at the interval specified in R_DTC_Create data6 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid exclusive and achievable otherwise false 12C R_IIC_Create R_IIC_GetStatus R_IIC_Control R_IIC_MasterReceiveLast R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 138 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Remarks If a callback function is specified please see the notes on callback function usage in 86 e If the previous transfer did not issue a Stop condition a Repeated Start condition shall be generated e If polling or interrupts are used for data reception the last byte to be read shall be completed with a NACK signal If the DMAC or DTC is used use R_IIC_MasterReceiveLast to read the last byte If polling mode is selected the status flags will be used to manage the data flow If an error oc
196. ions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or
197. is function The range of achievable bit rates is listed below Data clock ee freLk Mode source imit 50MHz 12 5 MHz 32MHz 8MHz Internal Minimum 95 24 61 15 Asynchronous Madum 3 125 000 781 250 2 000 000 500 000 External 1 562 500 390 625 1 000 000 250 000 internal Minimum 763 191 488 122 Synchronous Masini 6 250 000 1 562 500 4 000 000 1 000 000 External 8 333 333 2 083 333 5 333 333 1 333 333 Smart card Internal Minimum 3 0 75 2 0 5 Maximum 781 250 195 313 500 000 125 000 RPDL definitions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h void func void Configure SCIO for asynchronous R_SCI_Create 0 PDL_SCI_8N1 38400 1 Y Configure SCI1 for asynchronous R_SCI_Create 1 PDL_SCI_8N1 1 Y 8N1 8N1 38400 baud register values supplied E_BIT_16 PDL_SCI_PCLK_DIV_1 PDL_SCI_CYCLI 115200 amp Ox00FFFOO 0x50 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 2 R_SCI_Destroy Synopsis Shut down a SCI channel Prototype bool R_SCI_Destroy uint8 tdata Channel selection Description Stop data flow and shutdown the selected SCI channe
198. ister number IPL Ignored IR Between 16 and 253 10h to FFh ISELR Between 28 and 252 1Ch to FFh IER Between 2 and 15 02h to 1Fh IPR Between 0 and 143 00h to 8Fh data3 The value to be written to the register True if the parameter is within range otherwise false Interrupt control R_INTC_Read R_INTC_Modify This function uses an interrupt routine to modify the IPL bits If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up The Interrupt register tables are not contiguous This function does not check for gaps within these tables RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Set the IPL to 6 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 6 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 8 R_INTC_Modify Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 17 Modify an interrupt register bool R_INTC_Modify uint8_t data1 Register selection uint8_t data2 Number uint8_t data3 Modification value uin
199. l data Select channel SCIn where n 0 to 6 Return value True if all parameters are valid otherwise false Category SCI Reference R_SCI_Create Remarks e The SCI channel is put into the power down state Program example RPDL definitions include r_pdl_sci h RPDL device specific definitions tinclude r_pdl_definitions h void func void Shutdown SCI channel 1 R_SCI_Destroy 1 3 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 118 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 3 R_SCI_Send Synopsis Prototype Description Return value Category Reference Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 119 4 Library Reference Transmit data on a SCI channel bool R_SCI_Send uint8_t data1 Channel selection uint8_t data2 Channel configuration uint8_t data3 Data start address uint16 tdata4 Data count void func Callback function Transmit data on the specified serial channel data1 Select channel SCIn where n 0 to 6 data2 Control the transfer If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e DMAC DTC trigger control PDL_SCI_DMAC_DTC_TRI
200. l Converter Driver s ssssssssssssrssrrssirssirssirssirssirssrissinsstnsstnsstnnsstnnstnnsrnnsnn nt 2 20 2 21 10 bit Digital to Analog Converter Driver ccccccscceeeceeeeeeeeeeeeeeeeeeseeeeeseaeeesaaeseeeeeseaeeesaeeeseaeesseeeaas 2 21 3 TYPOS an ON uri A A A dd aia caia 3 1 31 DataSet 3 1 32 E E AA A NN 3 1 3 21 PDENO PUN Gini tt A a ati E a da 3 1 322 PDL NO PR A a eel aces AE DC 3 1 3 23 PDE NOSDATA conta td E ei ak dd ie a eve Aue en as 3 1 3 2 4 PDEIMGUMGROUP iis ccdecs Sete cadet wy A aaa a A a Macedon i EA T 3 1 3 2 5 PDL VERSION cat A A A A a A E Ll da dead 3 1 Aa Library Referencia Aine dica takes 4 1 4 1 API List by Peripheral FUNCTION creision e i aaa E 4 1 4 2 Description of Each API cee cceeeencecene cece aeeeeaae ence ceaeeeeaaesseaeesaaeeecaaeeseaaeseaeeseaeeesaesseaeeseaaesseaees 4 3 4 2 1 Clock Generation Circula A A Dents 4 4 1 AS A E NE a AN 4 4 4 2 2 Interrupt Control UNit ooonocnnnncnnnnlnnnnnnnonnocnnnccnnnrcnn nacer rra 4 6 1 R INTO CreateExtinler Ub cians ctaneiic ethers a dde a dd AA RdA dia ib 4 6 2 R_INTC_CreateFastinterrUpt ooococnonoccccnonoccconononccnnnnonccnnnnnnncnnononncnnnnn a nn nn nnnan nn rn nnannncnnn 4 8 3 R_INTC_CreateExceptionHandlerS oconcccnnnnninnnccnncccccncccnnccnn nc cnc 4 11 4 RAINTCO GontrolExtInterrupt c ia ai A s 4 12 5 R_INTC_GetExtinterruptStatusS oooonncccnnnnnnnccinnncnnnccnnncccn crac 4 14 6 RNTC Radna A A O O
201. l_pfc h RPDL device specific definitions include r_pdl_definitions h void func void Write data to register PFC1 R_PFC_ Write 1 OxFF R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 30 l ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 3 R_PFC_Modify Synopsis Modify a PFC register Prototype bool R_PFC_Modify uint8_t data1 PFC register selection uint8_t data2 Logical operation uint8_t data3 Modification value Description Write the value to a PFC register data1 Any value from 0 to 9 data2 e The logical operation to be applied to the register contents PDL_PFC_AND or PDL_PFC_OR or Select between AND 3 OR or Exclusive OR PDL_PFC_XOR data3 The value to be used for the modification Return value True if a valid register is specified otherwise false Functionality PFC registers References R_PFC_Read Remarks The PFC registers are modified by other driver functions Take care to not overwrite existing settings Program example RPDL definitions include r_pdl_pfc h RPDL device specific definitions tinclude r_pdl_definitions h void func void Set bit 7 in PFC1 to 1 R_PFC_Modify 1 PDL_PFC_OR 0x80 3
202. lity Please enter a number to select the device package 1 LQFP 144 pins 2 LFBGA 176 pins Select the device package option by pressing a number and then press Enter R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Page 1 2 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 1 Introduction Type the full path to the folder where you wish RPDL to be copied to and then press Enter BEE E Renesas RPDL R610 copy utility Please enter a number to select the device package i 2 1 LQFP 144 pins LFBGA 176 pins Please enter the path where you wish RPDL R616 to be installed ciimy_project_folder The utility will create a folder in the location that you specified and copy the files into the new folder ADE Renesas RPDL Rx618 copy utility Please enter a number to select the device package 1 LQFP 144 pins 2 LFBGA 176 pins i Please enter the path where you wish RPDL R610 to be installed c my_project_folder Creating the destination directory c my_project_folder RPDL Copying the generic files Copying the files for the LQFP144 package Finished Press any key to continue m Press any key to close the window R20UT0083EE0100 Rev 1 00 Jul 23 2010 IEN Page 1 3 AS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 1 Intr
203. lopment Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 7 R_IIC_SlaveSend Synopsis Write data to a master device Prototype bool R_IIC_SlaveSend uint8_t data1 Channel selection uint8_t data2 Data start address uint16_tdata3 Data count Description Transmit data on the specified channel data1 Select channel IICn where n 0 or 1 data2 The start address of the data to be sent data3 The number of bytes available to be sent Return value True if all parameters are valid exclusive and achievable otherwise false If this function is not called from the R_IIC_SlaveMonitor callback function it will complete when a stop condition is detected Category 12C Reference R_IIC_SlaveMonitor Remarks Use this function in conjunction with R_IIC_SlaveMonitor lf the master requires more data than is supplied and polling or interrupt based transfers are used this function shall loop back to the start of the data The transmitted byte count will also be reset to 0 Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h const uint8_t data_array 5 0x23 0x48 0x59 0x60 OxFE void func void Assign 5 bytes to be read by a master on chann
204. n Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 3 R_WDT_Read Synopsis Read the Watchdog timer status register Prototype bool R_WDT_Read uint8_t data A pointer to the data storage location Description Read and store the status flags data The timer status shall be stored in the following format b7 b1 bO 0 0 Not overflowed 1 Overflow has occurred Return value True if all parameters are valid otherwise false Category Watchdog Timer Reference R_WDT_Create Remarks Ifthe flag is set to 1 it shall be automatically cleared to 0 by this function Program example RPDL definitions include r_pdl_wdt h RPDL device specific definitions include r_pdl_definitions h uint8_t Flags void func void Read the timer values R_WDT_Read amp Flags Y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 114 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 2 15 Serial Communication Interface 1 R_SCI_Create Synopsis Prototype Description 1 3 R20UT0083EE0100 Rev 1 Page 4 115 SCI channel setup bool R_SCI_Create uint8_t data1 uint32_t data2 uint32_t data3 uint8_t data4 Set up the selected S
205. n or TIOCCn rising edge Input capture at TIOCDn or TIOCCn falling edge Input capture at TIOCDn or TIOCCn both edges See below for TIOCDn or TIOCCn pin selection PDL_TPU_D_IC_TPU_COUNT_CLK Input capture at TPU n 1 count clock count up or count down Invalid if TPU n 1 uses PCLK 1 TGRD input capture input selection PDL_TPU_D_IC_TIOCD or PDL_TPU_D_IC_TIOCC Input capture using pin TIOCDn or TIOCCn data6 The timer counter value data7 The register TGRA value data8 The register TGRB value data9 The register TGRC value ignored for n 0 3 6 or 9 data10 The register TGRD value ignored for n 0 3 6 or 9 func1 The function to be called when a TGRA event occurs Specify PDL_NO_FUNC if not required ENESAS Under development Preliminary Specification RX610 Group Description 5 5 Return value Category Reference Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 72 Specifications in this preliminary version are subject to change 4 Library Reference func2 The function to be called when a TGRB event occurs Specify PDL_NO_FUNC if not required func3 The function to be called when a TGRC event occurs Specify PDL_NO_FUNC if not required func4 The function to be called when a TGRD event occurs Specify PDL_NO_FUNC if not required data11 The interrupt priority level f
206. n with output and reset enable R_WDT_Create 1 PDL_WDT_PCLK_DIV_131072 PDL_WDT_RESET ENABLE PDL_NO_FUNC 0 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 112 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 2 R_WDT_Control Synopsis Control the Watchdog operation Prototype bool R_WDT_Control uint8 tdata Control selection Description Modify the operation of the Watchdog timer data Configure the timer channel To set multiple options at the same time use to separate each value e Counter stop PDL_WDT_STOP Disable the counter clock source e Counter update PDL_WDT_RESET_COUNTER Reset the counter Return value True if all parameters are valid and exclusive otherwise false Category Watchdog Timer Reference R_WDT_Create Remarks R_WDT_Create must be first be used to configure the timer Program example RPDL definitions tinclude r_pdl_wdt h RPDL device specific definitions tinclude r_pdl_definitions h void func void 1 Prevent the watchdog timer from overflowing R_WDT_Control PDL_WDT_RESET_COUNTER Y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 113 RENESAS Under development Preliminary Specificatio
207. nality I O port References R_IO_PORT_Set R_IO_PORT_Read Remarks e f an invalid port or pin is specified the operation of the function cannot be guaranteed Program example RPDL definitions include r_pdl_io_port h RPDL device specific definitions include r_pdl_definitions h void func void Set the output of port pin P05 R_IO_PORT_Write PDL_IO_PORT_0_5 0 Set the output of port 6 R_IO_PORT_Write PDL_IO_PORT_6 0x55 Y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 25 l ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 6 R_IO_PORT_Compare Synopsis Check the pin states on an I O port Prototype bool R_IO_PORT_Compare uint16_tdata1 Input port or port pin selection uint8_t data2 Comparison value void func Function pointer Description Read the input state of an I O port or I O port pin and call a function if a match occurs data1 Use either one of the following definition values from 4 2 3 One port definition or e One port pin definition data2 The value to be compared with Between 0x00 and OxFF for a port 0 or 1 for a pin func The function to be called if a match occurs Return value True if the parameters are valid otherwise false Functionality
208. nications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use condit
209. nitions h void func void Configure DMA channel 2 R_DMAC_Create 2 PDL_DMAC_ SOURCE_ADDRESS_PLUS PDL_DMAC_REQUEST_IROO Ox0000AA00 Ox0000BB0O 10 PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_FUNC 0 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 2 R_DMAC_Destroy Synopsis Shutdown the DMA controller Prototype bool R_DMAC_Destroy void No parameter is required Description Shutdown the DMAC module Return value True if the shutdown succeeded otherwise false Category DMA controller Reference R_DMAC_Create R_DMAC_Control Remarks e If all channels have been suspended the DMAC module will be disabled lf another peripheral is being used to trigger a DMA transfer stop the triggers from that peripheral using Control or Destroy for that peripheral before calling this function Program example RPDL definitions include r_pdl_dmac h RPDL device specific definitions tinclude r_pdl_definitions h void func void Shutdown the DMA controller R_DMAC_Destroy R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 52 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Gro
210. nnel bool R_SCI_Receive uint8_t data1 Channel selection uint8_t data2 Channel configuration uint8_t data3 Data start address uint16_t data4 Receive threshold void func Callback function void func2 Callback function Enable SCI reception and acquire any incoming data data1 Select channel SCIn where n 0 to 6 data2 Control the transfer The default settings are shown in bold Specify PDL_NO_DATA to use the defaults DMAC DTC trigger control PDL_SCI_DMAC_DTC_TRIGGER_DISABLE or PDL_SCI_DMAC_TRIGGER_ENABLE or PDL_SCI_DTC_TRIGGER_ENABLE Disable or enable activation of the DMAC or DTC when a data byte is received data3 The start address of the storage area for the expected data If the DMAC or DTC shall be used to handle the received data specify PDL_NO_PTR data4 The number of bytes that must be received before the function completes or the callback function is called If the DMAC or DTC shall be used to handle the received data specify PDL_NO_DATA func1 Specify PDL_NO_FUNC or a callback function name depending on the required transfer method Return value Category Reference R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 121 Transfer method Parameter Polli PDL_NO_FUNC This function will continue until the required number of olling bytes has been received Interrupts The function to be
211. ns in this preliminary version are subject to change 2 Driver 2 14 8 bit Timer Driver The driver functions support the use of the four 8 bit timers providing the following operations 1 2 8 9 Configuring a channel for use using register values which have been determined elsewhere Configuring two channels as a 16 bit pair using register values which have been determined elsewhere Configuration for as a periodic timer including Automatic clock setting using frequency or period as an input Automatic pulse width setting using pulse width or duty cycle as an input Automatic interrupt control I O pin control Automatic I O pin configuration Configuration for as a one shot timer including Automatic clock setting using pulse width as an input Automatic interrupt control CPU sleep option I O pin control Automatic I O pin configuration Automatic support for using two channels as a single 16 bit timer Disabling channels that are no longer required and enabling low power mode Control of a single timer channel Control of two timer channels when configured as one 16 bit channel Control of channels in periodic mode enabling pulse width modulation PWM output Reading the registers of a single timer channel 10 Reading the registers of a 16 bit timer channel pair Note The Clock Generation Circuit must be configured before configuring any timer channel R20UT0083EE0100 Rev 1 00 Jul
212. ns that no other interrupt can be processed until a callback function has completed While the receive operation is in progress R_SCI_GetStatus can be used to find out how many bytes have been received so far R_SCI_Control can be used to terminate the reception early PDL functions include r_pdl_sci h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t gSCIlReceiveBuffer 10 SCI channel 1 receive data handler void SCI1RxFunc void SCI channel 1 error handler void SCIlErrFunc void void func void uint8_t temp Put a Null character at the end of the string gSCIlReceiveBuffer 10 NULL Wait for 1 character to be received on channel 0 R_SCI_Receive 0 PDL_NO_DATA amp temp 1 PDL_NO_FUNC PDL_NO_FUNC Start the reception of 9 characters on channel 1 R_SCI_Receive 1 PDL_NO_DATA gSCIlReceiveBuffer 9 SCI1RxFunc SCI1ErrFunc ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 5 R_SCI_Control Synopsis Prototype Description Return value Category Reference Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 123 Control the SCI channel bool R_SCI_Control uint8_t data1 Chann
213. ntc h RPDL device specific definitions include r_pdl_definitions h Required for this example include lt string h gt Reserve an area for the DTC vector table Hpragma address dtc_vector_table 0x00015000 uint32_t dtc_vector_table 256 Reserve 16 bytes for the IRQ3 triggered transfer data area uint32_t dtc_irg3_transfer_data 4 void main void Initialise the system clocks R_CGC_Set 12 5E6 100E6 50E6 25E6 PDL_CGC_BCLK_DISABL Y Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Y Enable control of LEDO R_IO_PORT_Set DL_IO_PORT_3_6 DL_IO_PORT_OUTPUT Y Set the DTC options R_DTC_Set PDL_NO_DATA dtc_vector_table Configure the DTC for IRQ3 if R_DTC_Create PDL_DTC_BLOCK PDL_DTC_DESTINATION PDL_DTC_SOURCE_ADDRESS_PLUS PDL_DTC_DESTINATION_ADDRESS_PLUS X PDL_DTC_SIZE_8 PDL_DTC_IRQ_COMPL PDL_DTC_TRIGGER_IRQ3 dtc_irq3_transfer_data source_string_l destination_string_l 1 E R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 15 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples uint8_t strlen char source_string_1 while 1 Enable the SW3 interrupt R
214. ocess i The bits xxx represent the EEPROM memory address bits a10 a9 and a8 ii The first byte after the slave address is the EEPROM memory address bits a7 to a0 The EEPROM has a write cycle time of 5 ms The following examples illustrate the use of Master mode R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 30 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 1 Configuration and transmission Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h include r_pdl_intc h include r_pdl_cmt h RPDL device specific definitions include r_pdl_definitions h define EEPROM_ADDRESS 0xA0 void main void const uint8_t eeprom_data_array_1 5 0x00 0x01 0x02 0x03 0x04 uintl6_t status_flags 0 uint16_t TxChars uint16_t RxChars Initialise the system clocks R_CGC_Set 12 5E6 1006 50E6 PDL_NO_DATA PDL_CGC_BCLK_DISABLI y Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 y Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 1 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA 100E3 300 lt lt 16 200 y Send the lo
215. od or frequency calculation to separate each selection PDL_TMR_PERIOD or PDL_TMR_FREQUENCY The parameters data3 and data4 will contain either period and pulse width or frequency and duty cycle e Output pin control PDL_TMR_OUTPUT_ENABLE or PDL_TMR_OUTPUT_DISABLE Enable or disable the periodic output on pin TMOn For 16 bit operation the pin shall be TMO2 when n 1 ADC trigger control PDL_TMR_ADC_TRIGGER_OFF or PDL_TMR_ADC_TRIGGER_ON Disable or enable periodic ADC conversion start requests Applicable only for channels TMRO or TMR2 or units 0 or 1 e Counter stop start PDL_TMR_STOP or PDL_TMR_START Disable or re enable the counter clock source data3 The new period or frequency This will be ignored if a timing change is not requested data4 The new pulse width or duty cycle Return value Category Timer TMR Reference R_TMR_CreatePeriodic Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 99 This will be ignored if a timing change is not requested True if all parameters are valid and exclusive otherwise false See the remarks for R_TMR_CreatePeriodic ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include
216. oduction 1 1 3 Include the new directory Use the key sequence Alt B R to open the RX Standard Toolchain window Select the C C tab Use the key sequence S to show the included file directories Click on the Add button In the Add include file directory window enter the details as shown Add include file directory Relative to Project directory y Cancel Sub Directory RPDL Click on OK to close the window Click on the Add button In the Add include file directory window enter the details as shown Add include file directory Relative to Project directory v Sub Directory ee Click on OK to close the window Click on OK to return to the main HEW window R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Page 1 4 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 1 Introduction 1 1 4 Include the new source files Use the key sequence Alt P A to open the Add files to project lt your project window Double click on the RPDL folder From the Files of type drop down list select C source file C Select all of the files as shown below Add files to project rpdl_lib_test Interrupt_4DC_10 c Interrupt_not_RPDL c Interrupt_BS5C c Interrupt_SCTI c E Interrupt_CMT c E Interrupt_TMR c Interrupt_DMAC c In
217. oid DMACO_transfer_end_handler void Data source and destination declarations const uint8_t source_string_1 Renesas RX610 const uint8_t source_string_2 Hello World volatile uint8_t destination _string_1 volatile uint8_t destination_string_2 void main void uint16_t StatusValue uint32_t SourceAddr uint32_t DestAddr uint32_t ByteCount Initialise the system clocks R_CGC_Set 12 5E6 1006 50E6 256 PDL_CGC_BCLK_DISABLI Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Enable control of LEDO R_IO_PORT_Set PDL_IO_PORT_3_6 PDL_IO_PORT_OUTPUT 0 0 0 y Configure channel 0 R_DMAC_Create 0 PDL_DMAC_CONS E PDL_DMAC_SOURCE_ADDRESS_PLUS R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 8 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_REQUEST_IRO3 source_string_l destination_string_l strlen char source_string_1 PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA DMACO_transfer_end_handler 7 Configure channel 1 R_DMAC_Create 1 PDL_DMAC_CONSECUTIVE PDL_DMAC_SOURCI ESS PLUS PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_REQUEST_SW source_string_2 destination_string_
218. on or reset the system e If the NMI interrupt fails to initialise this function will return false Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h Declaration of callback function void CallBackFunc void void func void Configure the IRQO interrupt on pin IRQO A R_INTC_CreateExtInterrupt PDL_INTC_IRQO PDL_INTC_FALLING PDL_INTC_A CallBackFunc 7 y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 7 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 2 R_INTC_CreateFastinterrupt Synopsis Enable faster interrupt processing for one interrupt Prototype bool R_INTC_CreateFastinterrupt uint8_t data The interrupt to be selected Description 1 3 data Choose the interrupt vector to be processed using the fast interrupt process R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 8 Name Module Interrupt cause PDL_INTC_VECTOR BUSERR External bus Error illegal access or timeout PDL_INTC_VECTOR_FIFERR PDL_INTC_VECTOR FRDY Flash memory Error Ready PDL_INTC_VECTOR_CMTO PDL_INTC_VECTOR_CMT1 PDL_INTC_VECTOR_CMT2 PDL_INTC_VECTOR_CMT3 Compare match timer Compare match
219. on the 176 pin device ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 1 RIO PORT Set Synopsis Configure an I O port Prototype bool R_IO_PORT_Set uint16_tdata1 Port pin selection uint8_t data2 Configuration Description Set the operating conditions for I O port pins data1 Select the port pins to be configured from 84 2 3 Do not use any whole port definitions Multiple pins on the same port may be specified using to separate each pin data2 Choose the pin settings Use to separate each selection If no selection is made the control setting will be left unchanged Direction control PDL_IO_PORT_INPUT or PDL_IO PORT OUTPUT Input or output e Input buffer control PDL_IO_PORT_INPUT_BUFFER_ON or PDL_IO_PORT_INPUT_BUFFER_OFF On or off e Input pull up resistor control PDL_IO_PORT_PULL_UP_ON or PDL_IO_PORT_PULL_UP_OFF On or off Valid for ports A to E e Output type control PDL_IO_PORT_OPEN_DRAIN or NMOS open drain or CMOS push pull output PDL_LIO_PORT_CMOS Valid for ports 2 and C Return value True if all parameters are valid and exclusive otherwise false Functionality I O port References R_IO_PORT_ModifyControl R_IO_PORT_ReadControl Remarks Ensu
220. or PDL_LPC_DEEP_STANDBY_2048 or PDL_LPC_DEEP_STANDBY_4096 or Select the number of PCLK cycles that will elapse PDL_LPC_DEEP_STANDBY_16384 or before the CPU resumes after exiting from deep PDL_LPC_DEEP_STANDBY_32768 or software standby mode PDL_LPC_DEEP_STANDBY_65536 or PDL_LPC_DEEP_STANDBY_131072 or PDL_LPC_DEEP_STANDBY_262144 or PDL_LPC_DEEP_STANDBY_524288 Return value True if all parameters are valid and exclusive otherwise false Functionality Low Power Consumption control registers References R_LPC_Control Remarks None Program example RPDL definitions tinclude r_pdl_lpc h RPDL device specific definitions tinclude r_pdl_definitions h void func void 1 Allow a falling edge on IRQO A to cancel deep software standby R_LPC_Create PDL_LPC_CANCEL_IRQO_FALLING PDL_LPC_STANDBY_64 PDL_LPC_DEEP_STANDBY_1024 y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 35 l ENESAS Under development RX610 Group Preliminary Specification Specifications in this preliminary version are subject to change 2 R_LPC Control Synopsis Select a low power consumption mode Prototype bool R_LPC_Control uint16_t data Mode selection Description Transition to one of the low power modes data Mode selection e Mode selection PDL_LPC_MODE_SLEEP or PDL_LPC_MODE_SOFTWAR
221. or TGRx events Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for all parameters func1 func2 func3 and func4 func5 The function to be called when an overflow occurs Specify PDL_NO_FUNC if not required func6 The function to be called when an underflow occurs Specify PDL_NO_FUNC if not required data12 The interrupt priority level for overflow or underflow events Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for both parameters func5 and func6 True if all parameters are valid and exclusive otherwise false Timer Pulse Unit e If an external clock input pin TCLKx or I O pin TIOCxn is made active this function will configure that pin for input or output and disable other functions on that pin The external clock inputs TCLKA TCLKB TCLKC and TCLKD are allocated to pins TCLKA A TCLKB A TCLKC A and TCLKD A by default To select the B group of pins use API function R_PFC_Modify 5 PDL_PFC_OR 0x08 to write 1 to bit TCLKS in register PFCR5 before calling this function Note that these clock inputs are used by channels 0 to 5 e If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function usage in 6 Acallback function is executed by the interrupt processing function This means that no other
222. or compare match A Input capture or compare match B Input capture or compare match C Input capture or compare match D PDL_DTC_TRIGGER_TGI4A Timer Pulse Unit Input capture or compare match A PDL_DTC_TRIGGER_TGI4B channel 4 Input capture or compare match B PDL_DTC_TRIGGER_TGI5A Timer Pulse Unit Input capture or compare match A PDL_DTC_TRIGGER_TGI5B channel 5 Input capture or compare match B PDL_DTC_TRIGGER_TGI6A PDL_DTC_TRIGGER_TGI6B PDL_DTC_TRIGGER_TGI6C PDL_DTC_TRIGGER_TGI6D Timer Pulse Unit channel 6 Input capture or compare match A Input capture or compare match B Input capture or compare match C Input capture or compare match D PDL_DTC_TRIGGER_TGI7A Timer Pulse Unit Input capture or compare match A PDL_DTC_TRIGGER_TGI7B channel 7 Input capture or compare match B PDL_DTC_TRIGGER_TGI8A Timer Pulse Unit Input capture or compare match A PDL_DTC_TRIGGER_TGI8B channel 8 Input capture or compare match B PDL_DTC_TRIGGER_TGI9A PDL_DTC_TRIGGER_TGI9B PDL_DTC_TRIGGER_TGI9C PDL_DTC_TRIGGER_TGI9D Timer Pulse Unit channel 9 Input capture or compare match A Input capture or compare match B Input capture or compare match C Input capture or compare match D PDL_DTC_TRIGGER_TGI10A Timer Pulse Unit Input capture or compare match A PDL_DTC_TR
223. orrected the cross reference and modified the second remark 4 106 Updated the func parameter description 1 00 Jul 23 2010 4 109 Added counter control to R_CMT_Control 4 119 Updated the descriptions and remarks for DMAC and DTC usage 4 121 Updated the descriptions and remarks for DMAC and DTC usage 4 136 Updated the descriptions and remarks for DMAC and DTC usage 4 138 Updated the descriptions and remarks for DMAC and DTC usage 4 141 Updated the descriptions and remarks for DMAC and DTC usage 4 148 Added clarification for the data alignment 4 153 Added clarification for the data alignment R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Revision History 2 Renesas Peripheral Driver Library User s Manual RX610 Group Publication Date Rev 1 00 Jul 23 2010 Published by Renesas Electronics Corporation ENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadias
224. osite to that of the CPU e Write access mode PDL_BSC_WRITE_BYTE or PDL_BSC_ WRITE SINGLE Select byte strobe or single write strobe mode External wait control PDL_BSC_WAIT_DISABLE or Disable or enable external wait control using the PDL_BSC_WAIT_ENABLE WAIT pin e Page access control PDL_BSC_PAGE _ READ DISABLE or Disable or enable page read accesses using PDL_BSC_PAGE_READ_NORMAL or normal access compatible mode or PDL_BSC_PAGE_READ_CONTINUOUS continuous assertion mode PDL_BSC_PAGE_WRITE_DISABLE or PDL BSC PAGE WRITE ENABLE Disable or enable page write accesses data3 The number of read recovery cycles RRCV Valid between 0 and 15 data4 The number of write recovery cycles WRCV Valid between 0 and 15 data5 The number of wait cycles used for second and subsequent accesses during a page read sequence CSPRWAIT Valid between 0 and 7 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 43 7tENESAS Under development Preliminary Specification RX610 Group Description 2 2 Return value Category Reference Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 44 Specifications in this preliminary version are subject to change 4 Library Reference data6 The number of wait cycles used for second and subsequent accesses during a page write sequence CSPWWAIT Valid between 0 and 7 d
225. ounter clock source selection PDL_TMR_CLK_OFF or The clock input is disabled PDL_TMR_CLK_EXT_RISING or PDL_TMR_CLK_EXT_FALLING or ee ee PDL TMR CLK EXT BOTH or elect rising falling or both edges detected PDL_TMR_CLK_PCLK_DIV_1 or PDL_TMR_CLK_PCLK_DIV_2 or PDL_TMR_CLK_PCLK_DIV_8 or f PDL TMR CLK PCLK DIV 32 or Whe ae signal PCLK 1 2 8 32 64 PDL_TMR_CLK_PCLK_DIV_64 or PDL_TMR_CLK_PCLK_DIV_1024 or PDL_TMR_CLK_PCLK_DIV_8192 or PDL_TMR_CLK_TMR1_OVERFLOW or The overflow signal from TMR n 1 PDL_TMR_CLK_TMR3_ OVERFLOW or Valid for n 0 or 2 PDL_TMR_CLK_TMRO_CM_A or The compare match A signal from TMR n 1 PDL_TMR_CLK_TMR2_CM_A Valid for n 1 or 3 e Counter clearing PDL_TMR_CLEAR_DISABLE or Clearing is disabled PDL_TMR_CLEAR_CM_Aor Cleared after a compare match A occurs PDL_TMR_CLEAR_CM_B or Cleared after a compare match B occurs PDL_TMR_CLEAR_RESET_RISING or Cleared by a rising edge on the external reset pin TMRIn PDL_TMR_CLEAR_RESET_HIGH Cleared when the external reset pin TMRIn is high ADC trigger control PDL_TMR_ADC_TRIGGER_DISABLE or PDL_TMR_ADC_TRIGGER_ENABLE Disable or enable ADC conversion start requests on a compare match A signal Only applicable for channels TMRO or TMR2 e Compare Match A DTC trigger control PDL_TMR_CM_A_DTC_TRIGGER_DISABLE or PDL_TMR_
226. output disabled TIOCCn output low TIOCCn initial output low goes high at compare match TIOCCHn initial output low toggles at compare match TIOCCHn initial output high goes low at compare match TIOCCn output high TIOCCn initial output high toggles at compare match PDL_TPU_C_IC_RISING_EDGE or PDL_TPU_C_IC_FALLING_EDGE or PDL_TPU_C_IC_BOTH_EDGES or Input capture at TIOCCn rising edge Input capture at TIOCCn falling edge Input capture at TIOCCn both edges PDL_TPU_C_IC_TPU_COUNT_CLK Input capture at TPU n 1 count clock count up or count down Invalid if TPU n 1 uses PCLK 1 TIOCCn input capture pin selection PDL_TPU_C_IC SHARED or PDL_TPU_C_IC_ SEPARATE Input capture is shared with output compare or uses the adjacent pin Input capture output compare control fo r register TGRD PDL_TPU_D_OC DISABLED or PDL_TPU_D_OC LOW or PDL_TPU_D_OC_LOW_CM HIGH or PDL_TPU_D_OC_LOW_CM_INV or PDL_TPU_D_OC_HIGH_CM_LOW or PDL_TPU_D_OC_HIGH or PDL_TPU_D_OC_HIGH_CM_INV or TIOCDn output disabled TIOCDn output low TIOCDn initial output low goes high at compare match TIOCDn initial output low toggles at compare match TIOCDn initial output high goes low at compare match TIOCDn output high TIOCDn initial output high toggles at compare match PDL_TPU_D_IC_RISING_EDGE or PDL_TPU_D_IC_FALLING EDGE or PDL_TPU_D_IC_BOTH EDGES or Input capture at TIOCD
227. output pin TMOn is enabled this function will disable other output functions on that pin If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function usage in 86 If no callback function is specified this function waits for the CMIB flag to indicate that the one shot time delay is complete If the timer s control registers are directly modified by the user this function may lock up A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed The timer period limits depend on the peripheral module clock PCLK fecik MHz Equation 50 12 5 8 1 Tmn e 20ns 80ns 125ns Jrcrx 92 Tmax_CHANNEL 41 9ms 167 7ms 262ms Jre 92 Tmax_UNIT 10 78 42 9s 67 1s FrcLk include r_pdl_tmr h RPDL device specific definitions tinclude r_pdl_definitions h void func void Output a pulse and wait for 40ms R_TMR_CreateOneShot PDL_TMR_TMRO PDL_TMR_OUTPUT_ON 40E 3 PDL_NO_FUNC 0 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 5 R_TMR_Destroy Synopsis Disable a TMR timer unit Prototype bool R_TMR_Destroy uint8_tdata Unit selection
228. ow Power Consumption Microcontroller Unit Non Maskable Interrupt N type MOS Metal Oxide Semiconductor Most Significant Bit Peripheral Driver Generator Port Function Control Programmable Pulse Generator Pulse Width Modulation Random Access Memory Read Only Memory Renesas Peripheral Driver Library Serial Communications Interface System Management Bus Timer Pulse Unit Watchdog Timer ENESAS 1 Introduction Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 Driver 2 1 Overview This library provides a set of peripheral function control programs peripheral drivers for Renesas microcontrollers and allows the peripheral driver to be built into a user program 2 2 Control Functions summary This library has the following control functions available as peripheral drivers 1 Clock Generation Circuit These driver functions are used to configure the multiple internal clock signals 2 Interrupt These driver functions are used for configuring the external interrupt pins handling fixed interrupts and controlling the interrupt priority 3 1O Port These driver functions are used to configure the I O pins and provide data read write compare and modify operations 4 Port Function These driver functions are used for configuring the I O pin optional functions 5 MCU Operation These driver functions are used for confi
229. pecific definitions include r_pdl_definitions h void main void uintl6_t cre result Configure the CRC to use the CCITT polynomial LSB first R_CRC_Create PDL_CRC_POLY_CRC_CCITT PDL_CRC_LSB_FIRST Y Write the payload data R_CRC_Write OxFO Y Write the first half of the CRC checksum R_CRC_Write Ox8F Y Write the second half of the CRC checksum R_CRC_ Write 0xF7 Read the CRC calculation result R_CRC_Read PDL_NO_DATA amp Result y Shutdown the CRC unit R_CRC_Destroy Y Figure 5 17 Example of CRC calculation R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 29 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 11 12C Bus Interface In the following examples the bus activity will be illustrated using the following format Sms WW A Oa oan am 0 ATP A Acknowledge SDA held low A Not Acknowledge SDA released high S Start condition P Stop condition Sr Repeated Start condition R Read SDA released high W Write SDA held low Figure 5 18 I C bus activity notation 5 11 1 Master mode In this example an EEPROM device has been connected to channel 1 The EEPROM responds to the 7 bit slave address 1010xxxb During a read process the bits xxx can be any value During a write pr
230. pleted ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example include r_pdl_tmr h RPDL device specific definitions tinclude r_pdl_definitions h void func void Configure TMR unit 0 PCLK clear after a compare match A R_TMR_CreateUnit 0 PDL_TMR_CLK_PCLK_DIV_1 PDL_TMR_CLEAR_CM_A 0 0 199 99 PDL_NO_FUNC PDL_NO_FUNC PDL_NO_FUNC 0 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 89 l ENESAS Under development RX610 Group Preliminary Specification Specifications in this preliminary version are subject to change 3 R_TMR_CreatePeriodic Synopsis Select periodic operation Prototype bool R_TMR_CreatePeriodic 4 Library Reference uint8_t data1 8 bit channel or 16 bit unit selection uint32_t data2 Configuration selection float data3 Period or frequency float data4 Pulse width or duty cycle void func1 Callback function void func2 Callback function uint8_t data5 Interrupt priority level Description 1 2 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 90 data1 Set up a TMR timer channel or unit for periodic operation and start the timer PDL_TMR_TMRO or PDL_TMR_TMAR1 or PDL_TMR_TMR3 or configured PDL_TMR_UNITO or PDL_TMR_UNI
231. r SLAVE_CHANNEL PDL_IIC_RX_DMAC_TRIGGER_ E PDL _IIC_TX _DMAC_TRIGG PDL_NO_PTR PDL_NO_DATA slave_event_handler 7 void slave_event_handler void uintl6_t status_flags 0 R_IIC_Get Status SLAVE_CHANNEL amp status_flags PDL_NO_PTR PDL_NO_PTR Y NACK and Stop detected end of transmission to the master if status_flags amp 0x1800 0x1800 if transmission_completed false transmission_completed true else The main loop has failed to process the last transfer in time R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 48 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples Stop detected else if status_flags amp 0x1800 0x0800 if reception_completed false reception_completed true else The main loop has failed to process the last transfer in time nop Figure 5 28 An example of IIC Slave operation using two DMAC channels R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 49 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 5 12 Analog to Digital Converter Figure 5 29 shows an example of ADC usage ADC unit 2 is polled until the conve
232. r 0 uint32_t slave_l_ptr 0 Configure the clocks R_CGC_Set 12 5E6 100E6 50E6 PDL_NO_DATA PDL_CGC_BCLK_DISABLE y Set up a DMAC channel for IIC reception R_DMAC_Create 2 PDL_DMAC_SINGLE PDL_DMAC_DESTINATION_ADDRESS_PLUS PDL_DMAC_REQUEST_IICO_RX uint8_t amp RIICO ICDRR slave_data_received BUFFER_SIZE PDL_NO_PTR R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 45 l ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples L_NO_PTR L_NO_DATA L_NO_FUNC Y Set up a DMAC channel for IIC transmission R_DMAC_Create 3 PDL_DMAC_SINGLE PDL_DMAC_SOURCE_ADDRESS_PLUS PDL_DMAC_REQUEST_IICO_TX slave_data_storage_0 uint8_t RIICO ICDRI BUFFER_SIZE PDL_NO_PTR PDL_NO_PTR PDL_NO_DATA PDL_NO_FUNC 0 Y Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create SLAVE_CHANNEL PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_IIC_SLAVE_OQ_ENABLE 7 PDL_IIC_SLAVE_1 MCU_ADDRESS_0 MCU_ADDRESS_1 PDL_NO_DATA 100E3 300 lt lt 16 200 Y Enable the DMAC channels R_DMAC_Control PDL_DMAC_2 PDL_DMAC_3 _DMAC_ENABLE L_NO_DATA L_NO_PTR L_NO_PTR L_NO_DATA
233. r e g timer TMR RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void Stop ADC unit 0 and start ADC unit 1 R_ADC_10_Control PDL_ADC_10_0_OFF PDL_ADC_10_1_ON Y ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 4 R_ADC_10 Read Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 152 Read the ADC conversion results bool R_ADC_10_Read uint8_t data1 ADC unit selection uint16_t data2 Pointer to the buffer where the converted values are to be stored Reads the conversion values for an ADC unit data1 Select the ADC unit 0 1 2 or 3 to be read data2 Specify a pointer to a variable or array where the results shall be stored True if a valid unit is selected otherwise false ADC R_ADC_10 Create R_ADC_10_Control Between 1 and 4 conversion results will be read and stored The number depends on the settings for Input channel selection and Scan mode when R_ADC_10_Create is used to configure the ADC unit e The 10 bit data alignment is controlled using the R_ADC_10_Create function Ensure that
234. r port pin selection uint8_t data2 Control register and logical operation selection uint8_t data3 Modification value Description Modifying the operation of an I O port or I O port pin data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 Select the register to be modified and the logical operation using to separate the selections e The control register to be modified PDL_IO_PORT_DIRECTION or Data direction register PDL_IO_PORT_INPUT_BUFFER or Input buffer control register PDL_IO_PORT_PULL_UP or Pull up MOS control register Valid for ports A to E PDL_IO_PORT_TYPE Open drain control register Valid for ports 2 or C e The logical operation to be applied to the control register PDL_IO_PORT_AND or PDL_IO_PORT_OR or Select between AND amp OR or Exclusive OR PDL_IO_PORT_XOR E to be used for the modification Between 0x00 and OxFF for a port 0 or 1 for a pin Return value True if all parameters are valid and exclusive otherwise false Functionality I O port References R_IO_PORT_Set R_IO_PORT_ReadControl Remarks Ensure that the specified functions are valid for the selected port pin The data direction and input buffer registers may be modified by other driver Create functions Take care to not overwrite existing settings
235. re that the specified functions are valid for the selected port pin The data direction and input buffer registers may be modified by other driver Create functions Take care to not overwrite existing settings Program example RPDL definitions tinclude r_pdl_io_port h RPDL device specific definitions tinclude r_pdl_definitions h void func void Set up port P93 as an input port with the pull resistor on R_IO_PORT_Set PDL_IO_PORT_9_3 PDL_IO_PORT_INPUT PDL_IO_PORT_INPUT_BUFFER_ON PDL_TO_PORT_PULL_UP_ON R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 20 ztENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 R_IO PORT_ReadControl Synopsis Prototype Description 4 Library Reference Read an I O port s control register bool R_IO_ PORT_ReadControl uint16_t data1 uint8_t data2 Port or port pin selection Control register selection uint8_t data3 Data storage location data1 Use either one of the following definition values from 4 2 3 One port definition or One port pin definition data2 Select the register to be read PDL_IO_PORT_DIRECTION or Data direction register PDL_IO_PORT_INPUT_BUFFER or Input buffer control register Read an I O port pin control setting PDL_
236. read false void slave_event_handler void R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 43 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples uintl6_t status_flags 0 uint16_t tx count 0 uint16_t rx_count 0 Read the channel status R_IIC_GetStatus 0 status_flags amp tx_count rx_count Slave address 0 detected with a Read if status_flags 0x0047 0x0041 Assign 5 bytes to be read by a master R_IIC_SlaveSend 0 mcu_data_array 5 Slave address 1 detected with a Read else if status_flags amp 0x0047 0x0042 Assign 5 bytes to be read by a master R_IIC_SlaveSend 0 slave_data_storage 5 NACK and Stop detected else if status_flags amp 0x1800 0x1800 all_data_sent true Stop detected else if status_flags amp 0x1800 0x0800 all_data_read true do R_IIC_GetStatus 0 amp status_flags PDL_NO_PTR PDL_NO_PTR while status_flags 0x8000 0x0u else Process any other conditions here Figure 5 27 Configure the I C channel and write 3 data bytes to the first locations R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 44 RENESAS Under development Preliminary Specification Specifications in this preliminary version are su
237. red True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Create The start address of the transfer data area is the same as that declared in R_DTC_Create ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_dtc h RPDL device specific definitions tinclude r_pdl_definitions h Declared in the R_DTC_Create example extern uint32_t dtc_cmt0_transfer_datal void func void uint8_t StatusValue uint32_t SourceAddr Read the status and current source address for the CMTO transfer R_DTC_GetStatus dtc_cmt0_transfer_data amp StatusValue amp SourceAddr PDL_NO_PTR PDL_NO_PTR PDL_NO_PTR R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 67 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 2 10 Timer Pulse Unit 1 R_TPU_Create Synopsis Prototype Description 1 5 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 68 Configure a Timer Pulse Unit channel bool R_TPU_Create uint8_t data1 uint32_t data2 uint32_t data3 uint32_t data4 uint32_t data5 uint16_t data6 uint16_t data7 uint16_t data8 uint16_t data9
238. red if slave address 1 detection is disabled data6 Slave address 2 Ignored if slave address 2 detection is disabled data7 Transfer rate control Either The maximum bit rate in bits per second For Master mode the clock division values will be calculated using a 50 duty cycle For Slave mode the rate will be used to calculate the clock stretching period Or b31 b30 b13 b12 b8 b7 b5 b4 bO 4 i Bit rate high level register i Bit rate low level register ICBRH value ICBRL value R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 132 2tENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change Description 3 3 data8 Rise and fall time compensation If the transfer rate is specified in bits per second the high level and low level durations can be adjusted to allow for application dependent rise and fall times If unsure use 0 b31 b16 4 Library Reference b15 bO The SCL rise time in nanoseconds Valid from 0 to 65535 The SCL fall time in nanoseconds Valid from 0 to 65535 Return value True if all parameters are valid exclusive and achievable otherwise false Category 12C Reference R_IIC_Destroy Remarks Function R_CGC_Set must be
239. rrupt priority level is lower than the interrupt priority level This operation will not work for a level sensitive interrupt if the input signal is still low External interrupt True if all parameters are valid and exclusive otherwise false R_INTC_CreateExtInterrupt R_INTC_GetExtInterruptStatus The NMI pin was enabled during R_INTC_CreateExtInterrupt and cannot be disabled an MCU design feature e When disabling an IRQn pin the Interrupt Request flag will be cleared automatically Acallback function may be called once more if a valid event occurs just before the interrupt pin is disabled R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 12 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Disable the IRQ1 interrupt pin and clear the flag R_INTC_ControlExtInterrupt PDL_INTC_IRQ1 PDL_INTC_DISABLE PDL_INTC_CLEAR_IR_FLAG Y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 13 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 5 R_INTC_GetExtinterruptStatus Synopsis
240. rs data3 The one shot time period in seconds func The function to be called when the one shot period ends If you specify PDL_NO_FUNC this function will wait for the timer to complete before returning You must always specify a function if PDL_CMT_CPU_OFF is selected to ensure that an interrupt will re start the CPU data4 The interrupt priority level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func True if all parameters are valid and exclusive otherwise false Compare Match Timer None ENESAS Under development RX610 Group Preliminary Specification Specifications in this preliminary version are subject to change 4 Library Reference Remarks Function R_CGC_Set must be called before any use of this function Function R_CMT_Create is not required e Ifa callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function use in 86 A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed The timing limits depend on the peripheral module clock PCLK feck MHZ Equation 50 12 5 32 8 8 Tun 2 160ns 640ns 250ns 1us freux 92 Tmax 671ms 2 68s 1 05s 4 19s Freire
241. rsion are subject to change RX610 Group 4 Library Reference 4 R_LPC_ReadBackup Synopsis Read from the Backup registers Prototype bool R_LPC_ReadBackup uint8_t data1 Data pointer uint8_t data2 Data count Description Read data from the backup registers data1 The storage area for the data read from the backup area data2 The number of bytes to be read from the backup area Valid from 1 to 32 Return value True if all parameters are valid otherwise false Functionality Low Power Consumption control registers References R_LPC_WriteBackup Remarks eric R_PDL_LPC_BACKUP_AREA_SIZE specifies the number of bytes that are available Program example RPDL definitions tinclude r_pdl_lpc h RPDL device specific definitions tinclude r_pdl_definitions h void func void uint8_t data_to_restore R_PDL_LPC_BACKUP_AREA SIZE Read data from the backup registers R_LPC_ReadBackup data_to_restore R_PDL_LPC_BACKUP_AREA_SIZE R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 38 l ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 5 R_LPC_GetStatus Synopsis Prototype Description Return value Functionality R
242. rsion is complete Interrupts are enabled for ADC unit 3 which operates in the one cycle scan mode Peripheral driver function prototypes include r_pdl_adc_10 h include r_pdl_cgc h include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h volatile uint8_t adc2_result volatile uint8_t adc3_result 4 void ADC3Handler void void main void Initialise the system clocks R_CGC_Set 12 5E6 100E6 50E6 25E6 PDL_CGC_BCLK_DISABLE Y Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 Configure ADC unit 2 for single scan on pin AN9 polled R_ADC_10_Create 2 PDL_ADC_10_MODE_SINGLE PDL_ADC_10 CHANNELS OPTION_2 50E6 0 5E 6 PDL_NO_FUNC 0 Y Configure ADC unit 3 for one cycle scan on pins AN12 to AN15 interrupts R_ADC_10_Create 3 PDL_ADC_10_MODE E E SCAN PDL_ADC_10_CHANNELS_OPTION_4 50E6 0 5E 6 ADC3Handler 6 Y Start conversions on ADC units 2 and 3 R_ADC_10_Control PDL_ADC_10_2 ON PDL_ADC_10_3_ON Read the level on AN9 R_ADC_10_Read 2 g ade2_result di R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 50 2tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Ex
243. rther configuration should be required Simply build the project R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Page 1 8 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Gro up 1 Introduction 1 2 Document structure The drivers are summarised in section 2 and explained in detail in section 4 Section 5 provides usage examples Section 6 provides details which are specific to the RX CPU R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 1 9 RENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 1 3 Acronyms and abbreviations ADC API BCD Bit BSC CMT CGC CMOS CPU CRC DAC DMA DMAC DSP DTC EEPROM GSM HEW lC INTC 1 0 kB LSB R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 1 10 Analog to Digital Converter Application Programming Interface Binary Coded Decimal Binary digit Bus State Controller Compare Match Timer Clock Generation Circuit Complementary MOS Central Processing Unit Cyclic Redundancy Check Digital to Analog Converter Direct Memory Access DMA Controller Digital Signal Processing Data Transfer Controller Electrically Eraseable and Programmable ROM Global System for Mobile communications High performance Embedded Workbench Inter Integrated Circuit Interrupt Controller Input Output Kilo Byte 1024 bytes Least Significant Bit L
244. s are valid and exclusive otherwise false Compare Match Timer R_CMT_Create R_CMT_Create must be first be used to configure the channel e The Stop operation is executed at the start of this function The Start operation is executed at the end Therefore both options can be selected together with a value change in one function call RPDL definitions include r_pdl_cmt h RPDL device specific definitions tinclude r_pdl_definitions h void func void Change channel 2 to Ims period R_CMT_Control Un r DL_CMT_PERIOD E 3 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 5 R_CMT_Read Synopsis Read CMT channel status and registers Prototype bool R_CMT_Read uint8_t data1 Channel selection uint8_t data2 A pointer to the data storage location uint16_t data3 A pointer to the data storage location Description Read and store the counter value and status flag data1 The channel number n where n 0 1 2 or 3 data2 The compare match status flag shall be stored in the following format Specify PDL_NO_PTR if the flag is not to be read b7 b1 bO 0 0 Idle 1 Compare match condition detected data3 A pointer to where the counter value shall be stored Specify PDL_NO_PT
245. s in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable
246. sive otherwise false Category Bus Controller Reference R_BSC_CreateArea Remarks e Multiple chip select signals can be output from one I O pin Pin CSO CS1 CS2 CS3 CS4 CS5 CS6 CS7 P60 CSO CS4 A CS5 B P61 CS1 CS2 B CS5 A CS6 B CS7 B P62 CS2 A CS6 A P63 CS3 A CS7 A P64 CS4 B P70 CS3 B P71 CS4 C CS5 C CS6 C CS7 C PC5 CS5 D PC6 CS6 D PC7 CS4 D CS7 D e Port Function Control registers PFCR1 to PFCR5 and the appropriate I O port DDR and ICR registers are modified by this function The external bus is enabled by this function Call this function before using function R_BSC_CreateArea Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 41 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference Program example RPDL definitions include r_pdl_bsc h RPDL device specific definitions tinclude r_pdl_definitions h Bus error handler void BusErrorFunc void void func void Select CS2 B all address signals enable interrupts and register the callback function R_BSC_Create PDL_BSC_CS2_B 0 PDL_BSC_ERROR_ILLEGAL_ADDRESS_ENABLE PDL_BS
247. specific definitions include r_pdl_definitions h Reserve an area for the DTC vector table Hpragma address dtc_vector_table uint32_t dtc_vector_table 256 void func void 0x00015000 Configure the controller R_DTC_Set PDL_DTC_ADDRESS_SHORT dtc_vector_table ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 2 R_DTC_Create Synopsis Prototype Description 1 3 Configure the Data Transfer Controller for a transfer bool R_DTC_Create uint32_t data1 uint32_t data2 void data3 void data4 uint16_t data5 uint8_t data6 Configuration selection Transfer data start address Source start address Destination start address Transfer count Block size Configure DTC activation for one source data1 Configuration selections 4 Library Reference If multiple selections are required use to separate each selection The default settings are shown in bold Transfer mode selection PDL_DTC_NORMAL or Normal or PDL_DTC_REPEAT or Repeat or PDL_DTC_BLOCK Block mode PDL_DTC_SOURCE or PDL_DTC_DESTINATION If Repeat or Block mode is selected select the source or destination side to be the Repeat or Block area Address direction selection PDL_DTC_SOURCE_ADDRESS FIXED or PDL_DTC_
248. specific definitions include r_pdl_definitions h void func void Select I C mode at 100kHz 100ns rise and fall times R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA PDL_NO_DATA 100E3 100 lt lt 16 100 Y Select I C mode with two slave addresses R_IIC_Create 1 PDL_IIC_MODE_IIC PDL_IIC_SLAVE_0O_ENABLE 7 PDL_IIC_SLAVE_1_ENABLE_7 0x0020 0x0056 PDL_NO_DATA 100E3 300 lt lt 16 200 Y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 134 RENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 2 R_IIC_Destroy Synopsis Prototype Description Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 135 Disable an 2C channel bool R_IIC_Destroy uint8 tdata Channel selection Shut down the selected 12 module data Select channel IICn where n 0 or 1 True if the parameter is valid otherwise false 12C R_IIC_Create The I C module is put into the power down state RPDL definitions include r_pdl_iic h RPDL device specific definitions tinclude r_pdl_definitions h void func void S
249. support the use of the four ADC units providing the following operations 1 Configuration for use including e Automatic clock setting using sampling time as an input e Automatic interrupt control e Automatic I O pin configuration 2 Disabling units that are no longer required and enabling low power mode 3 Control of one or more units including e CPU sleep option 4 Reading the conversion results of one or more units with support for polling or interrupts Note The Clock Generation Circuit must be configured before configuring any ADC unit R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 20 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 21 10 bit Digital to Analog Converter Driver The driver functions support the use of the DAC module providing the following operations 1 Configuring a channel for use including e Independent or linker operation e Data alignment 2 Disabling channels that are no longer required and enabling low power mode 3 Writing data to a channel R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 21 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 3 Types and definitions 3 Types and definitions 3 1 Data types This section describes the data types used in this library For details about the settin
250. t are not supported by the driver library these functions support 1 Reading from a PFC register 2 Writing to a PFC register 3 Modifying a PFC register R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Page 2 6 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 7 MCU Operation Driver The driver functions support access to the registers which select the mode of operation for the microcontroller These functions support 1 Controlling the on chip ROM and RAM 2 Reading the MCU status flags R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Page 2 7 Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 2 Driver 2 8 Low Power Consumption Driver The driver functions support access to the registers which select the lower power modes of operation for the microcontroller These functions support 1 Configuring the state while in standby mode and the activity that can be used to resume operation Selecting one of the low power modes Writing data to the backup memory area Reading data from the backup memory area Determining the cause of the exit from the lowest power mode R20UT0083EE0100 Rev 1 00 Jul 23 2010 RENESAS Page 2 8 Under development Preliminary Specification Specifications in this preliminary version are subject to chang
251. t data3 void func uint8_t data4 Description 1 2 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 40 Control the external bus controller Configure the external bus controller 4 Library Reference Configuration Configuration Configuration Callback function Interrupt priority level Configure the I O pins error detection and register the callback function If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults data1 Chip select pin selection only required for each external memory area that is enabled PDL_BSC_CS2 Aor PDL_BSC_CS2 B Select pin CS2 A or CS2 B PDL_BSC_CS3_A or PDL_BSC_CS3 B Select pin CS3 A or CS3 B PDL_BSC_CS4 Aor PDL_BSC_CS4 Bor PDL_BSC_CS4 Cor PDL_BSC_CS4 D Select pin CS4 A CS4 B CS4 C or CS4 D PDL_BSC_CS5 Aor PDL_BSC_CS5 Bor PDL_BSC_CS5 Cor PDL_BSC_CS5 D Select pin CS5 A CS5 B CS5 C or CS5 D PDL_BSC_CS6 Aor PDL_BSC_CS6_Bor PDL_BSC_CS6_Cor PDL_BSC_CS6_D PDL_BSC_CS7_Aor PDL_BSC_CS7_Bor PDL_BSC_CS7_Cor PDL_BSC_CS7_D Select pin CS6 A CS6 B CS6 C or CS6 D Select pin CS7 A CS7 B CS7 C or CS7 D e Strobe pin control PDL_BSC_WR1BC1_ENABLE or PDL_BSC_WR1BC1_ DISABLE Enable or disable the WR1 BC1 output data2 e Address output control The signals ar
252. t to change 10 bit Analog to Digital Converter 1 R_ADC 10 Create Synopsis Prototype Description 1 2 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 147 Configure an ADC unit bool R_ADC_10_Create uint8_t data1 ADC unit selection uint32_t data2 ADC configuration uint32_t data3 float data4 void func uint8_t data5 Callback function Interrupt priority level Set the ADC s mode and operating condition data1 Select the ADC unit 0 1 2 or 3 to be configured data2 Conversion options To set multiple options at the The default settings are shown in bold Specify P Input channel selection 4 Library Reference ADC conversion clock frequency ADC input sampling time same time use to separate each value DL_NO_DATA to use the defaults PDL_ADC_10_ CHANNELS OPTION_1 or Any mode For unit 0 channel ANO For unit 1 channel AN4 For unit 2 channel AN8 For unit 3 channel AN12 PDL_ADC_10_CHANNELS_OPTION_2 or Single mode For unit 0 channel AN1 For unit 1 channel AN5 For unit 2 channel AN9 For unit 3 channel AN13 Scan mode For unit 0 channels ANO and AN1 For unit 1 channels AN4 and AN5 For unit 2 channels AN8 and AN9 For unit 3 channels AN12 and AN13 PDL_ADC_10_CHANNELS_OPTION_3 or Single mode For unit 0 channel AN2 For unit 1 channel AN6 For unit 2 channel AN10 For unit 3
253. t8_t data4 Logical operation Write the new value to the IPL bits in the Processor Status Word register data1 e The register to be updated PDL_INTC_REG_IR or Select the Interrupt Request register or PDL_INTC_REG_ISELR or Interrupt Request Destination Setting register or PDL_INTC_REG_IER or Interrupt Request Enable register or PDL_INTC_REG_IPR Interrupt Priority register data2 The register number IR Between 16 and 253 10h to FFh ISELR Between 28 and 252 1Ch to FFh IER Between 2 and 15 02h to 1Fh IPR Between 0 and 143 00h to 8Fh data3 The value to be used by the logical operation data4 e The logical operation to be applied to the register contents PDL_INTC_AND or PDL_INTC_OR or Select between AND amp OR or Exclusive OR PDL_INTC_XOR True if the parameter is within range otherwise false Interrupt control R_INTC_Read R_INTC_Write This function uses an interrupt routine to modify the IPL bits If the user has disabled interrupts cleared the I bit in the PSW register in their own code this function will lock up The Interrupt register tables are not contiguous This function does not check for gaps within these tables RPDL definitions include r_pdl_intc h RPDL device specific definitions include r_pdl_definitions h void func void Set bits 6 and 4 in IERO9 to 1 R_INTC_Modify PDL
254. ta void bus_busy true Read data from the EEPROM on channel 1 using the DTC R_IIC_MasterReceive 1 P DL_IIC_DTC_TRIGG EPROM_ADDRESS DL_NO_PTR PDL_NO_FUNC di while bus_busy true void iic_tx_dtc_end_handler void uintl6_t status_flags 0 Wait for the transmission to complete R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 41 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples R_IIC_GetStatus 1 amp status_flags PDL_NO_PTR PDL_NO_PTR while status_flags amp 0x0080u 0x0u Issue a Stop condition on channel 1 R_IIC_Control 1 PDL_IIC_STOP bus_busy false void iic_rx_dtc_end_handler void uint32_t DestAddr 0 Read the next destination address for the current transfer R_DTC_GetStatus dtc_iicl_rx transfer_data PDL_NO_PTR PDL_NO_PTR DestAddr PDL_NO_PTR PDL_NO_PTR Read one more byte with NACK condition on channel 1 and stop R_IIC_MasterReceiveLast 1 uint8_t DestAddr y bus_busy false Figure 5 26 An example of write data to and reading data from an EEPROM using two DMAC channels R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 42 ENESAS Under development Preliminary Specification Specifications in this preliminary
255. ta3 A pointer to where the counter value shall be stored Specify PDL_NO_PTR if it is not required data4 Where the compare match A value shall be stored Specify PDL_NO_PTR if it is not required data5 Where the compare match B value shall be stored Specify PDL_NO_PTR if it is not required True if all parameters are valid and exclusive otherwise false Timer TMR R_TMR_CreateChannel R_TMR_ControlChannel Ifthe status flags are read any flag that has been set to 1 shall be automatically cleared to 0 by this function include r_pdl_tmr h RPDL device specific definitions tinclude r_pdl_definitions h uint8_t Flags uint8_t Counter uint8_t CompareMatchA uint8_t CompareMatchB void func void Read the status flags and registers for TMRO R_TMR_ReadChannel 0 amp Flags amp Counter amp CompareMatchA amp CompareMatchB ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 10 R_TMR_ReadUnit Synopsis Prototype Description Return value Category Reference Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 102 Read from timer unit registers bool R_TMR_ReadUnit uint8_t data1 Unit selection uint8_t data2 A pointer to the data storage location uint16_t data3 A pointer
256. terrupt_TPU c El Interrupt_IIC c E Interrupt_WDT c E Interrupt_INTC c File name Interrupt WDT c Interrupt_ADC_10 c Inter Add Files of type C source file C 7 Cancel MV Relative Path I Hide Project Files Click on Add Click on OK to return to the main HEW window Page 1 5 Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 1 Introduction 1 1 5 Avoid conflicts with standard project files If the files intprg c or vecttbl c are included in the project remove or exclude them 1 Removal Use the key sequence Alt P R to open the Remove Project Files window Select the files and click on Remove Remove Project Files Project files OK C WorkSpace rpe C WorkSpace rpe Cancel C WworkS pace rpe C WorkSpace rpe Remove C WorkSpace rpe C WorkSpace rpe C WorkSpace rpe Remove All C WorkSpace rpe C WorkSpace rpe C workSpace rpe C workSpace rpe C WorkSpace rpe C WorkSpace rpe C workSpace rpe C WorkS pace rpe C WworkSpace rp Page 1 6 Under development Preliminary Specification RX610 Group 2 Specifications in this preliminary version are subject to change 1 Introduction Exclusion Select the two files and use the key sequence Alt B to exclude them 3 rpdl_lib_test High performance Embedded Workshop File Edit View Project
257. to prevent overflow 6 Reading the timer status and counter register Note The Clock Generation Circuit should be configured before configuring this timer R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 16 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 17 Serial Communication Interface Driver The driver functions support the use of the seven serial communication channels providing the following operations 1 Configuration for use including e Automatic baud rate clock calculations e Automatic interrupt control e Automatic I O pin configuration 2 Disabling channels that are no longer required and enabling low power mode 3 Transmitting data with polling or interrupt mode automatically selected 4 Receiving data with polling or interrupt mode automatically selected 5 Control the channel operation 6 Reading the status flags Note The Clock Generation Circuit must be configured before configuring any serial channel R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 2 17 RENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 2 Driver 2 18 CRC Calculator Driver The driver functions support the CRC calculator providing the following operations 1 Configuration for use including e Polynomial selection e Bit order selection e Prepar
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259. trol PDL_DTC_UPDATE_SOURCE PDL_DTC_UPDATE_COUNT dtc_iicl_tx_transfer_data eeprom_data_array_2 PDL_NO_PTR 8 PDL_NO_DATA dF Write the data into the EEPROM write_eeprom_data Clear the data storage area for i 0 i lt 20 i data_storage i 0x00 Reset the EEPROM sub address to 0 using polling R_IIC_MasterSend 1 PDL_IIC_STOP_DISABL EPROM_ADDRESS eeprom_data_array_l R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 40 7tENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 1 PDL_NO_FUNC 0 Y Read data from the EEPROM on channel 1 using the DTC read_eeprom_data Prepare the next data R_DTC_Control PDL_DTC_UPDATE_DESTINATION PDL_DTC_UPDAT1 dtc_iicl_rx transfer _data PDL_NO_PTR data_storagel 5 5 PDL_NO_DATA Read data from the EEPROM on channel 1 using the DTC read_eeprom_data static void write_eeprom_data void bus_busy true Send data to the EEPROM on channel 1 using the DTC R_IIC_MasterSend 1 PDL_IIC_DTC_TRIGG EEPROM_ADDRESS PDL_NO_PTR 0 PDL_NO_FUNC 0 Y while bus_busy true Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot 0 r E 3 DL_NO_FUNC static void read_eeprom_da
260. tusValue uint16_t TxChars uint16_t RxChars void func void Read the status of SCI channel 0 R_SCI_GetStatus 0 amp StatusValue PDL_NO_PTR amp TxChars amp RxChars R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 126 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 4 2 16 CRC calculator 1 R_CRC_Create Synopsis Configure the CRC calculator Prototype bool R_CRC_Create uint8_t data Configuration Description Enable the CRC and set the operating conditions data Calculation options To set multiple options at the same time use to separate each value e Polynomial selection PDL_CRC_POLY CRC 8or oa xX aXe PDL_CRC POLY CRC 16 or xt xa xP 4 PDL CRC POLY CRC CCITT X X 4 x 4 1 Bit order PDL_CRC_LSB _FIRST or PDL_CRC_MSB_FIRST Select LSB or MSB first operation Return value True if all parameters are valid and exclusive otherwise false Functionality CRC References Remarks gt None Program example RPDL definitions include r_pdl_crc h RPDL device specific definitions tinclude r_pdl_definitions h void func void Set up the CRC in 8 bit mode with LSB first R_CRC_Create PDL_CRC_POLY_CRC_8 PDL_CRC_LSB_FIRST y
261. ty level Select between 1 lowest priority and 7 highest priority This parameter will be ignored if PDL_NO_FUNC is specified for parameter func Return value Functionality ADC References R_ADC_10_ Destroy R ADC_10_Read R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 148 ENESAS True if all parameters are valid and exclusive otherwise false Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group Remarks 4 Library Reference This function configures the selected pin s for ADC operation by setting the direction to input and turning off the input buffer The port control settings for any ADC pins that subsequently become inactive are not modified This function brings the selected converter unit out of the power down state Interrupts are enabled automatically if a callback function is specified Please see the notes on callback function usage in 86 A callback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed Function R_CGC_Set must be called before any use of this function The available values for the conversion clock are PCLK 8 4 2 or 1 If the desired frequency is not an exact match the actual frequency will be the next highest frequency The timing limits depend on the peripheral module
262. ulse Generator Reference R_PPG_Create Remarks None Program example RPDL definitions tinclude r_pdl_ppg h RPDL device specific definitions tinclude r_pdl_definitions h void func void Load the next output values on group 6 R_PPG_Control PDL_PPG_GROUP_6 0x07 i R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 83 ztENESAS Under development RX610 Group Preliminary Specification Specifications in this preliminary version are subject to change 4 2 12 8 bit Timer 1 R_TMR_CreateChamnel Synopsis Configure a timer TMR channel Prototype bool R_TMR_CreateChannel uint8_t data1 Channel selection uint32_t data2 uint8_t data3 uint8_t data4 uint8_t data5 uint8_t data6 Register value Register value Register value void func Callback function void func2 Callback function void func3 Callback function uint8_t data7 Description 1 2 Set up an 8 bit timer TMR channel R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 84 data1 4 Library Reference Configuration selection Configuration selection Interrupt priority level The channel number n where n 0 1 2 or 3 data2 Configure the channel If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e C
263. up 3 Synopsis Prototype Description 1 2 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 53 R_DMAC_Control Control the DMA controller bool R_DMAC_Control Channel number Control options Trigger selection uint8_t data1 uint16_t data2 uint8_t data3 4 Library Reference void data4 Source address void data5 Destination address uint32_t data6 Transfer byte count void data7 Source reload address void data8 Destination reload address uint32_t data9 data1 Channel selection If multiple selections are required use to separate each selection Transfer byte reload count Change the state of a DMA controller channel PDL_DMAC_0 PDL_DMAC_1 PDL_DMAC_2 PDL_DMAC_3 or PDL_DMAC_ALL The channel to be controlled data2 Control the channel operation If multiple selections are required use to separate each selection Enable suspend control PDL_DMAC_ENABLE Enable re enable DMA transfers PDL_DMAC_SUSPEND Suspend DMA transfers Software trigger control PDL_DMAC_START Start a DMA transfer Transfer end detection flag control PDL_DMAC_CLEAR_DREQ Clear the transfer request flag Transfer end detection flag control PDL_DMAC_CLEAR_TEDF Clear the flag This flag is cleared automatically if a callback function is enabled Trigg
264. ut data1 4 Library Reference Disable selection To set multiple options at the same time use to separate each value PDL_DAC_10_CHANNEL_O Disable channel 0 PDL_DAC_10_CHANNEL_1 Disable channel 1 Return value Category DAC Reference R_DAC_10 Create Remarks Program example RPDL definitions include r_pdl_dac_10 h True if the parameter is valid otherwise false RPDL device specific definitions include r_pdl_definitions h void func void Shut down both DAC channels R_DAC_10_Destroy PDL_DAC_10_CHANNEL_O PDL_DAC_10_CHANNEL_1 y R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 154 ztENESAS Once both channels are disabled the module is put into the power down state Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 3 R_DAC_10 Write Synopsis Write data to a DAC channel Prototype bool R_DAC_10_Control uint8_t data1 Channel selection uint16_tdata2 Output value uint16_t data3 Output value Description Write data to the selected DAC channel s data1 Select the DAC channel output to be modified PDL_DAC_10_CHANNEL_0 Select channel 0 PDL_DAC_10_CHANNEL_1 Select channel 1
265. velopment RX610 Group Preliminary Specification Specifications in this preliminary version are subject to change 4 Library Reference Remarks Function R_CGC_Set must be called before any use of this function e If a callback function is specified this function will enable the relevant CPU interrupt Please see the notes on callback function use in 6 Acallback function is executed by the interrupt processing function This means that no other interrupt can be processed until the callback function has completed The timing limits depend on the frequency of the peripheral module clock PCLK feck MHz Equation 50 12 5 32 8 8 Periodmin 160ns 640ns 250ns 1 0us Jre 9 Periodmax 671ms 2 68s 1 05s 4 19s Frcix fmax La 6 25 MHz 1 56 MHz 4 0 MHz 1 0 MHz fmin dei 1 49Hz 0 37Hz 0 95 Hz 0 24 Hz f the requested period is not a multiple of the minimum period the actual time period will be more than the requested time period Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 105 RPDL definitions include r_pdl_cmt h RPDL device specific definitions tinclude r_pdl_definitions h void func void Configure CMT channel 0 for 10ys operation R_CMT_Create 0 PDL_CMT_PERIOD 10E 6 PDL_NO_FUNC 0 i Configure CMT channel 1 for 1kHz operation R_CMT_Create
266. version are subject to change RX610 Group 4 Library Reference Category 12C Reference R_IIC_Create R_IIC_GetStatus Remarks If a callback function is specified please see the notes on callback function usage in 6 e If the Start condition is enabled and the previous transfer did not issue a Stop condition a Repeated Start condition shall be generated e If the Start condition is disabled the slave address will not be transmitted If polling mode is selected this function will monitor the status flags to manage the data flow If an error occurs during this polling process the function will terminate If the 12C channel s registers are modified directly by the user this function may lock up Use R_IIC_GetStatus to determine if the transfer was successful If the transfer has ended prematurely use R_IIC_Control to issue a Stop condition Program example RPDL definitions include r_pdl_iic h RPDL device specific definitions include r_pdl_definitions h const uint8_t data_array 5 0x23 0x48 0x59 0x60 OxFE void func void Send 5 bytes to device 0x0A0 on channel 1 using polling R_IIC_MasterSend 1 PDL_NO_DATA Ox0A0 data_array 5 PDL_NO_FUNC 0 R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 137 ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are su
267. version are subject to change RX610 Group 5 Usage Examples 5 11 4 Slave mode In this example the MCU behaves as a slave device on channel 0 It will respond to 7 bit address 0001001b or 10 bit address 0010010010b Peripheral driver function prototypes include r_pdl_iic h include r_pdl_cgc h tinclude r_pdl_intc h include r_pdl_cmt h RPDL device specific definitions tinclude r_pdl_definitions h void slave_event_handler void const uint8_t mcu_data_array 10 0x00 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80 Ox5A volatile bool all_data_read volatile bool all_data_sent volatile uint8_t slave_data_storage 10 void main void Initialise the system clocks R_CGC_Set 12 5E6 100E6 50E6 PDL_NO_DATA PDL_CGC_BCLK_DISABLE Set the CPU s Interrupt Priority Level to 0 R_INTC_Write PDL_INTC_REG_IPL PDL_NO_DATA 0 i Select I C mode at 100kHz 300ns rise time 200ns fall time R_IIC_Create 0 PDL_IIC_MODE_IIC PDL_IIC_INT_PCLK_DIV_8 PDL_IIC_SLAVE_0_ ENABLE _7 PDL_IIC_SLAVE_1 0x12 0x0124 PDL_NO_DATA 100E3 300 lt lt 16 200 3 all_data_read false Monitor the channel Any data received will be stored in the receive buffer R_IIC_SlaveMonitor 0 PDL_NO_DATA slave_data_storage 10 slave_event_handler 7 while all_data_
268. wer address and 3 bytes to the EEPROM using polling if R_IIC_MasterSend 1 PDL_NO_DATA EEPROM_ADDRESS eprom_data_array_l r DL_NO_FUNC e 4 P 0 false Read the channel and transfer status R_IIC_GetStatus 1 status_flags amp TxChars PDL_NO_PTR 3 Review the flags and transmit count to decide on the next action R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 31 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples else Wait for 5ms while the EEPROM updates R_CMT_CreateOneShot E 3 DL_NO_FUNC Figure 5 19 Configure the I C channel and write 3 data bytes to the first locations R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 5 32 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 5 Usage Examples 2 Reception Ses W vergas Baa baa ba P Figure 5 20 The bus activity showing 4 bytes being transmitted to the EEPROM Read data from the EEPROM using polling if R_IIC_MasterReceive 1 PDL_NO_DATA EEPROM_ADDRESS data_storage 4 PDL_NO_FUNC 0 false Read the channel and transfer status R_IIC_GetStatus 1 amp status_flags PDL_NO_PTR RxChars 3 Review the flags and transmit count to deci
269. y Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 58 Set the Data Transfer Controller options bool R_DTC_Set 4 Library Reference uint8_t data1 Configuration options uint32_t data2 Vector table base address Set the global options for the Data Transfer Controller data1 Configuration selections If multiple selections are required use to separate each selection The default settings are shown in bold Specify PDL_NO_DATA to use the defaults e Chain transfer control PDL_DTC_CHAIN_AFTER_REPEAT_DISABLE or Disable or enable chain transfer after a PDL_DTC_CHAIN_AFTER_REPEAT_ENABLE repeat transfer completes e Read skip control PDL_DTC_READ_SKIP_DISABLE or PDL_DTC_READ_SKIP_ENABLE Disable or enable skipping of transfer data read when the vector numbers match e Address size control PDL_DTC_ADDRESS FULL or PDL_DTC_ ADDRESS SHORT Select 32 bit full or 24 bit short address mode data2 The first address of the area of on chip RAM where the DTC vector table shall be stored The address must be on a 4 kB boundary i e have the format xxxxx000h True if all parameters are valid and exclusive otherwise false Data Transfer Controller R_DTC_Create e Call this function once before calling R_DTC_Create RPDL definitions include r_pdl_dtc h RPDL device
270. y out an internal reset of the 12 module the settings are preserved True if all parameters are valid 2C R_IIC_Create None RPDL definitions include r_pdl_iic h exclusive and achievable otherwise false RPDL device specific definitions include r_pdl_definitions h void func void Issue a Stop condition on channel 0 R_IIC_Control 0 PDL_IIC_STOP 00 Jul 23 2010 ENESAS Under development Preliminary Specification Specifications in this preliminary version are subject to change RX610 Group 4 Library Reference 9 R_IIC_GetStatus Synopsis Prototype Description Return value Category Reference Remarks R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 145 Read the status for an 12C channel bool R_IIC_GetStatus uint8_t data1 Channel selection uint16_t data2 Status flags uint16_t data3 Transmitted bytes uinti6_t data4 Received bytes Read the status registers for the selected 12C channel data1 Select channel IICn where n 0 or 1 data2 The status flags shall be stored in the format below Specify PDL_NO_PTR if this information is not required b15 b14 b13 b12 b11 b10 b9 b8 Bus state Pin level Event detection 0 Not detected 1 detected 0 Idle
271. ype Description Return value Category Reference Remarks Program example R20UT0083EE0100 Rev 1 00 Jul 23 2010 Page 4 150 Shut down an ADC unit bool R_ADC_10_Destroy uint8 tdata ADC unit selection Put the ADC into the Power down state with minimal power consumption data Select the ADC unit 0 1 2 or 3 to be shut down True if a valid unit is selected otherwise false ADC R_ADC_10 Create e This function waits for the ADST flag to indicate that the converter has stopped If the ADC unit s control registers are directly modified by the user this function may lock up RPDL definitions include r_pdl_adc_10 h RPDL device specific definitions include r_pdl_definitions h void func void Shut down ADC unit 1 R_ADC_10_Destroy 1 Y ENESAS Under development Preliminary Specification RX610 Group Specifications in this preliminary version are subject to change 4 Library Reference 3 R_ADC_10_Control Synopsis Prototype Description Return value Category Reference Start or stop an ADC unit bool R_ADC_10_Control uint16_t data Conversion unit control Controls start stop operation of the specified ADC data To select multiple units at the same time use to separate each value e On off control

RX610 Group Peripheral Driver Library User`s Manual

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