XC878CLM Series Errata Sheet
Contents
1. Table 8 Module Register SFR Products Address P Affected T2CCU CCTCON C6 0 1 XC878 COSHDW C0 0 2 XC878 COCON C0 0 3 XC878 CCOL C1 0 2 XC878 CCOH C2 0 2 XC878 CC1L C3 0 2 XC878 CC1H C4 0 2 XC878 CC2L C5 0 2 XC878 CC2H C6 0 2 XC878 CC3L C1 0 3 XC878 C2 0 3 XC878 CC4L C3 0 3 XC878 0 3 878 CCSL C5 0 3 XC878 CC5H C6 0 3 XC878 CCU6 CC63SRL 0 0 CC63SRH 0 0 MCMOUTSL 0 0 MCMOUTSH 0 0 CC60SRL FA 0 0 All CC60SRH FB 0 0 All CC61SRL FC 0 0 All XC878CLM Series AC 22 38 Rel 1 2 17 01 2013 infineon Errata Sheet Functional Deviations Table 8 Module Register SFR RMA Products Address P Affected 6 CC61SRH FD 0 0 cont d CC62SRL 0 0 All CC62SRH FF 0 0 T12PRL 9C 0 1 T12PRH 9D 0 1 T13PRL 0 1 T13PRH 9F 0 1 T12DTCL A4 0 1 T12DTCH Ady 0 1 All TCTROL A64 0 1 TCTROH AT 0 1 T12MSELL 9A 0 2 12 5 0 2 IENL 9C 0 2 All IENH 9D 0 2 All INPL 9E 0 2 9F 0 2 All PSLR A64 0 2 MCMCTR AT 0 2 TCTR2L FA 0 2 TCTR2H 0 2 All MODCTRL 0 2 MODCTRH FD 0 2 TRPCTRL FE 0 2 TRPCTRH FF 0 2 All PISELOL 9E 0 3 PISELOH2. 0 3 PISEL2 0 3 878 1 5 23 38 1 2 17 01 2013 infineon Errata Sheet Functional Deviations Table 8 Module Register SFR RMA Products Address P Affected 6 T13L FC 0 3 contd T43H FD 0 3 All CMPSTATH FF 0 3 GLOBCTR 0 0 PRAR CC 0 0 LCBR CD 0 0 INPCRO CE 0 0 ETRCR CF 0 0 CHCTRO 0 1 All CHCTR1 CB 0 1 All CHCTR2 CC 0 1 CHCTR3 CD 0 1 CHCTR4 CE 0 1 CHCTR5 CF 0 1 CHCTR6 D2 0 1 All CHCTR7 0 1 RCRO 0 4 All RCR1 CB 0 4 All RCR2 CC 0 4 RCR3 CD 0 4 CHINPR CD 0 5 EVINPR 0 5 CRCR1 0 6 CRPR1 CB 0 6 All CRMR1 CC 0 6 QMRO CD 0 6 878 1 Series AC 24 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations For example in the sample code below there are two MOV direct direct instructions that write the value of one register into another All the source and destination registers in these two instructions are from the direct address range 80 to FF The P1 DATA register is not one of the affected registers listed in the table above and therefore it is written with the correct value of the CC60SRL register On the other hand the CC60SRH register is one of the affected regis
3. higher than 0 3V When is not powered on the current over a GPIO pin has to be limited such way that Vipp 0 3V This prevents the supply of the device via the ESD diode between the GPIO pin and XC878CLM Series AC 35 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Application Hints However for applications with strict low power down current requirements it is mandatory that no active voltage source is supplied at any GPIO pin when Vppp is not powered on PM XC8 H001 Clock source selection before entering power down mode There are two oscillator sources available in the clock system on chip oscillator and external oscillator via XTAL pad When external oscillator is selected to be the clock source CON OSCSS 1 the XTAL pad will not be shut down automatically during power down mode If optimal power down current is required on chip oscillator should be chosen as the clock source before entering power down mode Note SAK product variant does not support power down mode PM XC8 H002 SAK product variant does not support power down mode Power down mode is not available in the SAK product variant It is only supported in SAF and SAX product variants The profile of these variants is described in Table 11 Table 11 Temperature Profile Variant Type Temperature Profile C SAF 40 to 85 SAX 40 to 105 SAK 40 to 125 SYS 8 001 Usage of the Bit Protec
4. TXENO TXENI is set in the message object control register of any message object Workaround After reallocating message object m write the value one to one of the bits MSGVAL TXENO 1 of the message object control register of any message object in order to retrigger transmit acceptance filtering XC878CLM Series AC 10 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations For frame reception make sure that there is another message object in the list that can receive the message targeted to n in order to avoid data loss e g a message object with an acceptance mask 0 and PRI 3 as last object of the list MultiCAN 1 044 RxFIFO Base SDT If a receive FIFO base object is located in that part of the list that is used for the FIFO storage container defined by the top and bottom pointer of this base object and bit SDT is set in the base object CUR pointer points to the base object then MSGVAL of the base object is cleared after storage of a received frame in the base object without taking the setting of MOFGPRn SEL into account Workaround Take the FIFO base object out of the list segment of the FIFO slave objects when using Single Data Transfer MultiCAN 1 045 ovrE Unexpected Interrupt When a gateway source object or a receive FIFO base object with MOFCRn OVIE set transmits a CAN frame then after the transmission an unexpected interrupt is gener
5. a result of a single data transfer MOFCR SDT 1 in the message object then the problem does not occur problem only occurs if MSGVAL of a message object is cleared via CPU XC878CLM Series AC 19 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations Workaround Do not clear MOCTR MSGVAL of any message object during CAN operation Use bits MOCTR RXEN MOCTR TXENO instead to disable reenable reception and transmission of message objects MultiCAN TC 038 Cancel TXRQ When the transmit request of a message object that has won transmit acceptance filtering is cancelled by clearing MSGVAL TXRQ TXENO or 1 the CAN bus is idle and no writes to MOCTR of any message object are performed then MultiCAN does not start the transmission even if there are message objects with valid transmit request pending Workaround To avoid that the CAN node ignores the transmission take a dummy message object that is not allocated to any CAN node Whenever a transmit request is cleared set of the dummy message object thereafter This retriggers the transmit acceptance filtering process or whenever a transmit request is cleared set one of the bits TXRQ TXENO which is already set again in the message object for which the transmit request is cleared or in any other message object This retriggers the transmit acceptance filtering process SYS XC8 001 MOV direct
6. of message objects or Take a dummy message object that is not allocated to any CAN node Whenever a transmit request is cleared set MOCTRm TXRQ of the dummy message object thereafter This retriggers the transmit acceptance filtering process MultiCAN 1 043 Dealloc Previous Obj Assume two message objects m and n message object n MOCTRm PNEXT i e n is the successor of object m in the list are allocated If message m is reallocated to another list or to another position while the transmit or receive acceptance filtering run is performed on the list then message object n may not be taken into account during this acceptance filtering run For the frame reception message object n may not receive the message because n is not taken into account for receive acceptance filtering The message is then received by the second priority message object in case of any other acceptance filtering match or is lost when there is no other message object configured for this identifier For the frame transmission message object n may not be selected for transmission whereas the second highest priority message object is selected instead if any If there is no other message object in the list with valid transmit request then no transmission is scheduled in this filtering round If in addition the CAN bus is idle then no further transmit acceptance filtering is issued unless another CAN node starts a transfer or one of the bits MSGVAL
7. 01 2013 Infineon Errata Sheet Application Hints 19 2k x 4095 24M 8 26 2 bits If the maximum number of bits in the BRK field exceeded the internal counter will overflow which results in baudrate detection error Therefore the user is advised to choose the appropriate BGSEL value for the required baudrate detection range The calculated value above does not consider sample error and transmission error nevertheless it can be used as a guideline MultiCAN AI HO05 TxD Pulse upon short disable request If a CAN disable request is set and then canceled in a very short time one bit time or less then a dominant transmit pulse may be generated by MultiCAN module even if the CAN bus is in the idle state Example for setup of the CAN disable request PMCON1 CAN DIS 1 then PMCON1 CAN DIS 0 Workaround Set all INIT bits to 1 before requesting module disable MultiCAN AI H007 Alert Interrupt Behavior in case of Bus Off The MultiCAN module shows the following behavior in case of a bus off status REC 0x1 0 1 BOFF INIT 0 0 0 0 ALERT INIT 0 60 0 1 EWRN BOFF INIT 0 60 or REC 0x60 EWRN Figure 5 Alert Interrupt Behavior in case of Bus Off XC878CLM Series AC 33 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Application Hints When the threshold for error warning EWRN is reached default value of Error War
8. C62 3 Input of Capture Compare Channel 2 P5 5 CCUG XC8 H002 CCUG PM event in center aligned mode After detecting a period match PM A in centre aligned mode T12 counts down from PM 1 as shown below 0x201 0x200 0x200 PMA PMB Ox1FF Ox1FF is al Ox1FE Ox1FE Figure 3 Counting sequence of T12 center aligned mode This means a second PM event PM B will occur during the counting down If ADC is triggered externally via ETRx2 T12PM it will be triggered twice in succession Depending on how real time the application code is running as well XC878CLM Series AC 30 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Application Hints as the T12 count rate and ADC conversion rate the application could observe two ADC interrupts once at PM A and once at PM B To avoid triggering twice the ADC interrupts it is suggested to use ETRx6 from multi channel mode instead of ETRx2 as the trigger source for ADC Additional initialization are as follows Configure MCMCTR SWSEL 101 Transfer on T12 period match Configure MCMCTR SWSYN 00 Direct transfer Write to MCMOUTSTL CF To enable multi Channel PWM pattern on CC6x and COUT6x Note Independent of the external trigger the CCUG internal triggers based T12 PM e g T12 PM interrupt or shadow transfer are only activiated once while T12 is counting up EVR XC8 H002 Enhancement for Noise Immunity During power up the EV
9. Cinfineon Errata Sheet Rel 1 2 17 01 2013 Device XC878CLM Series Marking Step AC Package PG LQFP 64 This Errata Sheet describes the deviations from the current user documentation The module oriented classification and numbering system uses an ascending sequence over several derivatives including already solved deviations So gaps inside this enumeration can occur This Errata Sheet covers the following devices XC878CM 13 16FF e XC878CLM 13 16FF Table 1 Current Documentation XC878CLM User s Manual V1 1 Apr 2009 XC87xCLM Data Sheet V1 5 Mar 2011 Each erratum identifier follows the pattern Module Arch TypeNumber Module subsystem or peripheral affected by the erratum e Arch microcontroller architecture where the erratum was firstly detected Architecture Independent detected on module level CIC Companion ICs TC TriCore 32 bit X XC1xx 2000 16 bit XC8 XC800 8 bit none C16x 16 bit Type none Functional Deviation P Parametric Deviation H Application Hint D Documentation Update XC878CLM Series AC 1 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Number ascending sequencial number within the three previous fields As this sequence is used over several derivatives including already solved deviations gaps inside this enumeration can occur Note Devices marked with EES or ES are engineering samples which may not be completely tested in all f
10. R functionality may be affected due to injected noise from any functional pin In order to enhance the noise immunity the external reset pin RESET must be asserted until VDDC reaches 0 9 VDDC The delay of external reset can be realized by an external capacitor at RESET pin This capacitor value must be selected so that VRESET reaches 0 4 V but not before VDDC reaches 0 9 VDDC A typical application example is shown in Figure 4 A 220 nF capacitor is connected to VDDP pin VDDC pin and RESET pin In addition it is also essential to put it as close as possible to the chip XC878CLM Series AC 31 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Application Hints 3 3V 5V po eeeeceeee VSSP VDDP VDDC VSSC RESET Figure4 Noise Immunity Enhancement Circuitry FLASH XC8 H004 Disable TRAP When Calling ROM Flash Routine User code has to disable TRAP by clearing EO TRAP_EN bit before any CALL to ROM Flash routines and to restore the bit after that LIN XC8 H001 LIN BRK field detection logic Based on the hardware implementation the maximum number of bits in the BRK field must follow the formula 4095 Maximum number of bits in BRK field Baud Rate x _ Sample Frequency PCLK Sample Frequency 8x2 BGSEL For example if LIN baudrate is 19 2kbps BGSEL 0 and CPU frequency is 24MHz the maximum number of bits in BRK field would be XC878CLM Series AC 32 38 Rel 1 2 17
11. ated on the interrupt line as given by MOIPRm RXINP ofthe message object referenced by m MOFGPRn CUR Workaround Do not transmit any CAN message by receive FIFO base objects or gateway source objects with bit MOFCRn OVIE set MultiCAN 1 046 Transmit FIFO base Object position If a message object n is configured as transmit FIFO base object and is located in the list segment that is used for the FIFO storage container defined by XC878CLM Series AC 11 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations MOFGPRn BOT and MOFGPRn TOP but not at the list position given by MOFGPRn BOT then the MultiCAN uses incorrect pointer values for this transmit FIFO Workaround The transmit FIFO works properly when the transmit FIFO base object is either at the bottom position within the list segment of the FIFO MOFGPRn BOT n or outside of the list segment as described above MultiCAN TC 025 RXUPD behavior When a CAN frame is stored in a message object either directly from the CAN node or indirectly via receive FIFO or from a gateway source object then bit MOCTR RXUPD is set the message object before the storage process and is automatically cleared after the storage process Problem description When a standard message object MOFCR MMC receives a CAN frame from CAN node then it processes its own RXUPD as described above correct In addition to that it also sets and clears bit RXUPD in the m
12. direct instruction might cause a wrong value to be written to the destination register The MOV direct direct instruction hex code 85 that access registers direct address ranging from 80 to does not write the correct value of the source register to the destination register if the destination register is a register listed in the table below The source register can be any register from the direct address range 80 to FF XC878CLM Series AC 20 38 Rel 1 2 17 01 2013 infineon Errata Sheet Functional Deviations Table 8 Module Register SFR RMA Products Address P Affected SCU IRCONO B4 0 0 XC88x XC878 IRCON1 B5 0 0 XC88x XC878 IRCON2 B6 0 0 XC88x XC878 IRCONS3 B4 0 3 All IRCON4 B5 0 3 NMISR BC 0 0 XC88x XC878 FDCON E9 0 0 XC88x XC878 PMCONO B4 0 1 XC88x XC878 OSC CON B6 0 1 XC88x XC878 PLL CON B7 0 1 XC88x MISC CON E9 0 1 XC88x XC878 WDT WDTCON BB 1 XC88x XC878 CORDIC CD STATC AO 1 XC88x XC878 MDU MDUSTAT B0 1 XC88x XC878 SSC CONH AB 0 Operating Mode UART1 SCON C8 1 XC88x XC878 FDCON CC 1 XC88x XC878 T2 T2CON CO 0 All 21 2 CO 1 XC88x XC878 OCDS MMCR2 E9 1 MMCR F1 1 All MMSR F2 1 MMICR FA 1 878 1 Series AC 21 38 Rel 1 2 17 01 2013 infineon Errata Sheet Functional Deviations
13. e request The answer message is arbitrated against the winner of transmit acceptance filtering without the remote answer with a respect to the CAN arbitration rules and not taking the PRI values into account If the remote answer is not sent out immediately then it is subject to further transmit acceptance filtering runs which are performed correctly Workaround Set MOFCRn FRREN 1g and MOFGPRn CUR to this message object to disable the immediate remote answering MultiCAN 1 041 Dealloc Last Obj When the last message object is deallocated from a list then a false list object error can be indicated Workaround Ignore the list object error indication that occurs after the deallocation of the last message object or Avoid deallocating the last message object of a list MultiCAN 1 042 Clear MSGVAL during transmit acceptance filtering Assume all CAN nodes are idle and no writes to MOCTRn of any other message object are performed When bit MOCTRn MSGVAL of a message object with valid transmit request is cleared by software then MultiCAN may not start transmitting even if there are other message objects with valid request pending in the same list XC878CLM Series AC 9 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations Workaround Do not clear MOCTRn MSGVAL of any message object during CAN operation Use bits MOCTRn RXEN MOCTRn TXENO instead to disable reenable reception and transmission
14. erefore if the error occurs between the selection for transmission and the real start of frame transmission the message is actually never sent Workaround In case the transmission shall be guaranteed it is not suitable to use the STT mode In this case MOFCRn STT shall be O XC878CLM Series AC 34 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Application Hints MultiCAN TC H004 Double remote request Assume the following scenario A first remote frame dedicated to a message object has been received It performs a transmit setup TXRQ is set with clearing NEWDAT MultiCAN starts to send the receiver message object data frame but loses arbitration against a second remote request received by the same message object as the first one NEWDAT will be set When the appropriate message object data frame triggered by the first remote frame wins the arbitration it will be sent out and NEWDAT is not reset This leads to an additional data frame that will be sent by this message object clearing NEWDAT There will however not be more data frames than there are corresponding remote requests remote CAN Bus request remote data data request loss of arbitration data MultiC AN object clear clear set clear NEWDAT NEWDAT NEWDAT by HW by HW by HW Figure6 Loss of Arbitration PIN XC8 H001 Current over GPIO pin must not source
15. essage object referenced by pointer MOFGPR CUR wrong behavior Workaround The foreign RXUPD pulse can be avoided by initializing MOFGPR CUR with the message number of the object itself instead of another object which would be message object 0 by default because MOFGPR CUR points to message object 0 after reset initialization of MultiCAN MultiCAN TC 026 MultiCAN Timestamp Function The timestamp functionality does not work correctly XC878CLM Series AC 12 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations Workaround Do not use timestamp MultiCAN TC 027 MultiCAN Tx Filter Data Remote Message objects of priority class 2 MOAR PRI 2 are transmitted in the order as given by the CAN arbitration rules This implies that for 2 message objects which have the same CAN identifier but different DIR bit the one with DIR 1 send data frame shall be transmitted before the message object with DIR 0 which sends a remote frame The transmit filtering logic of the MultiCAN leads to a reverse order i e the remote frame is transmitted first Message objects with different identifiers are handled correctly Workaround None MultiCAN TC 028 SDT behavior Correct behavior Standard message objects MultiCAN clears bit MOCTR MSGVAL after the successful reception transmission of a CAN frame if bit MOFCR SDT is set Transmit Fifo slave object MultiCAN clears bit MOCTR MSGVAL after the successful recep
16. ifferent than expected Table 7 Errata Sheet Functional Deviations Bit timing mode NFCR CFSEL according to spec Value to be written to NFCR CFSEL instead Measurement 0015 Mode is missing not implemented in MultiCAN Whenever recessive edge transition from 0 1 is monitored on the receive input the time measured in clock cycles between this edge and the most recent dominant edge is stored in CFC 010 0115 Whenever dominant edge is received as a result of a transmitted dominant edge the time clock cycles between both edges is stored in CFC 011 100 Whenever a recessive edge is received as a result of a transmitted recessive edge the time clock cycles between both edges is stored in CFC 100 0015 Whenever a dominant edge that qualifies for synchronization is monitored on the receive input the time measured in clock cycles between this edge and the most recent sample point is stored in CFC Workaround None XC878CLM Series AC 18 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations MultiCAN TC 037 Clear MSGVAL Correct behaviour When MSGVAL is cleared for a message object in any list then this should not affect the other message objects in any way Message reception wrong behaviour Assume that a received CAN message is about to be stored in a message object A which can be a standa
17. ill be performed on the CD STATC register and the error bit will be cleared by the time the CPU performs the final read As a result the CPU does not capture the correct error status There is no problem if the CORDIC is clocked at the same frequency as PCLK Workaround The following workarounds can be used to avoid incorrect data fetching from the STATC register The PUSH dir and POP dir instructions can be used to read the CD STATC register in all conditions The following one machine cycle MOV instruction can be used to read the CD STATC register when the CORDIC is clocked at two times of PCLK MOV dir MultiCAN 1 040 Remote frame transmit acceptance filtering error Correct behaviour Assume the MultiCAN message object receives a remote frame that leads to a valid transmit request in the same message object request of remote answer then the MultiCAN module prepares for an immediate answer of the remote request The answer message is arbitrated against the winner of transmit acceptance filtering without the remote answer with a respect to the priority class MOARn PRI Wrong behaviour XC878CLM Series AC 8 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations Assume the MultiCAN message object receives a remote frame that leads to a valid transmit request in the same message object request of remote answer then the MultiCAN module prepares for an immediate answer of the remot
18. mit value Gateway Destination Fifo slave object Correct operation of the SDT feature Workaround Standard message object Set pointer MOFGPR CUR to the message number of the object itself Transmit FIFO Do not set bit MOFCR SDT in the transmit FIFO base object Then SDT works correctly with the slaves but the FIFO deactivation feature by CUR reaching a predefined limit SEL is lost MultiCAN TC 029 Tx FIFO overflow interrupt not generated Specified behaviour After the successful transmission of a Tx FIFO element a Tx overflow interrupt is generated if the FIFO base object fulfils these conditions Bit MOFCR OVIE 1 AND MOFGPR CUR becomes equal to MOFGPR SEL XC878CLM Series AC 14 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations Real behaviour A Tx FIFO overflow interrupt will not be generated after the transmission of the Tx FIFO base object Workaround If Tx FIFO overflow interrupt needed take the FIFO base object out of the circular list of the Tx message objects That is to say just use the FIFO base object for FIFO control but not to store a Tx message List X base object MO s dol WOLLOd TxFiFo Figure 1 FIFO structure XC878CLM Series AC 15 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations MultiCAN TC 030 Wrong transmit order when CAN error at start of CRC transmission The priority order defined by acceptance filte
19. ning Level EWRN 0x60 then the EWRN interrupt is issued The bus off BOFF status is reached if TEC 255 according to CAN specification changing the MultiCAN module with REC and TEC to the same value 0 1 setting the INIT bit to 15 and issuing the BOFF interrupt The bus off recovery phase starts automatically Every time an idle time is seen REC is incremented If REC 0x60 a combined status EWRN BOFF is reached The corresponding interrupt can also be seen as a pre warning interrupt that the bus off recovery phase will be finished soon When the bus off recovery phase has finished 128 times idle time have been seen on the bus EWRN and BOFF are cleared the ALERT interrupt bit is set and the INIT bit is still set MultiCAN TC H002 Double Synchronization of receive input The MultiCAN module has a double synchronization stage on the CAN receive inputs This double synchronization delays the receive data by 2 module clock cycles If the MultiCAN is operating at a low module clock frequency and high CAN baudrate this delay may become significant and has to be taken into account when calculating the overall physical delay on the CAN bus transceiver delay etc MultiCAN TC H003 Message may be discarded before transmission in STT mode If MOFCRn STT 1 Single Transmit Trial enabled bit TXRQ is cleared TXRQ 0 as soon as the message object has been selected for transmission and in case of error no retransmission takes places Th
20. pt 11 MultiCAN_AI 046 Transmit FIFO base Object position 11 MultiCAN TC 025 RXUPD behavior 12 MultiCAN TC 026 MultiCAN Timestamp Function 12 MultiCAN TC 027 MultiCAN Tx Filter Data Remote 13 MultiCAN TC 028 SDT behavior 13 MultiCAN TC 029 Tx FIFO overflow interrupt not generated 14 MultiCAN TC 030 Wrong transmit order when CAN error at 16 start of CRC transmission MultiCAN TC 031 List Object Error wrongly triggered 16 MultiCAN TC 032 MSGVAL wrongly cleared in SDT mode 17 MultiCAN TC 035 Different bit timing modes 17 MultiCAN TC 037 Clear MSGVAL 19 MultiCAN TC 038 Cancel TXRQ 20 SYS XC8 001 MOV direct direct instruction might 20 cause a wrong value to be written to the destination register SYS XC8 003 Brownout Reset New 26 T2CCU XC8 003 T2CCU Capture Functions 26 UART XC8 002 Bits FDEN and FDM in UART1 FDCON 26 SFR cannot be Written by Read Modify Write Instructions XC878CLM Series AC 4 38 Rel 1 2 17 01 2013 infineon Errata Sheet History List Change Summary Table 5 Deviations from Electrical and Timing Specification ACIDC ADC Short Description Chg Pg Deviation Table 6 Application Hints Hint Short Description Chg Pg ADC XC8 H001 Arbitration mode when using external 29 trigger at the selected input line REQTR BROM XC8 H001 SYSCONO RMAP handling in ISR 29 CCU6 XC8 H001 Pin Configuration of CCU6 Function
21. rd message object FIFO base FIFO slave gateway source or gateway destination object If during of the storage action the user clears MOCTR MSGVAL of message object B in any list then the MultiCAN module may wrongly interpret this temporarily also as a clearing of MSGVAL of message object A The result of this is that the message is not stored in message object A and is lost Also no status update is performed on message object A setting of NEWDAT MSGLST RXPND and no message object receive interrupt is generated Clearing of MOCTR MSGVAL of message object B is performed correctly Message transmission wrong behaviour Assume that MultiCAN is about to copy the message content of a message object A into the internal transmit buffer of the CAN node for transmission If during of the copy action the user clears MOCTR MSGVAL of message object B in any list then the MultiCAN module may wrongly interpret this also as a clearing of MSGVAL of message object A The result of this is that the copy action for message A is not performed bit NEWDAT is not cleared and no transmission takes place clearing MOCTR MSGVAL of message object B is performed correctly In case of idle CAN bus and the user does not actively set the transmit request of any message object this may lead to not transmitting any further message object even if they have a valid transmit request set Single data transfer feature When the MultiCAN module clears MSGVAL as
22. reset without powering off the device boot up via User Mode affects certain IRAM data The affected IRAM address ranges are 1 00 07 Workaround None CD XC8 001 Set and Clear of Error Bit in CORDIC Linear Vectoring Mode In linear vectoring mode the Error bit of register CD STATC is set immediately on detecting overflow When detected between iterations the Error status is not held internally till the end of the calculation As the Error bit is defined such that it is cleared on any read access to the register e g JB BSY SW checking of the Error bit only at the end of calculation may miss to detect an overflow error condition Workaround Especially in linear vectoring mode if the error condition setting of Error bit must be detected any read access should be done on the whole CD STATC register e g MOV and the Error bit checked in all read instances XC878CLM Series AC 7 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations CD XC8 002 Data Fetch to CD STATC Register may capture an incorrect error status The error bit STATC ERROR is defined such that the bit is cleared on any read access to the register Therefore it is necessary to perform a data fetch on the register and check for the error bit in order not to lose the error status However if CORDIC is clocked at two times PCLK and the execution time of the read instruction is more than one machine cycle multiple read accesses w
23. ring specified in the message objects define the sequential order in which these messages are sent on the CAN bus If an error occurs on the CAN bus the transmissions are delayed due to the destruction of the message on the bus but the transmission order is kept However if a CAN error occurs when starting to transmit the CRC field the arbitration order for the corresponding CAN node is disturbed because the faulty message is not retransmitted directly but after the next transmission of the CAN node Figure 2 Workaround None MultiCAN TC 031 List Object Error wrongly triggered If the first list object in a list belonging to an active CAN node is deallocated from that list position during transmit receive acceptance filtering happening during message transfer on the bus then list object error may occur NSRx LOE 1 which will cause that effectively no acceptance filtering is performed for this message by the affected CAN node As a result forthe affected CAN node the CAN message during which the error occurs will not be stored in a message object This means that although the message is acknowledged on the CAN bus its content will be ignored XC878CLM Series AC 16 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations the message handling of an ongoing transmission is not disturbed but the transmission of the subsequent message will be delayed because transmit acceptance filtering has
24. s 30 CCU6 XC8 H002 CCU6 PM event in center aligned mode 30 EVR XC8 H002 Enhancement for Noise Immunity 31 FLASH XC8 H004 Disable TRAP When Calling ROM Flash 32 Routine LIN XC8 H001 LIN BRK field detection logic 32 MultiCAN AI H005 TxD Pulse upon short disable request 33 MultiCAN AI H007 Alert Interrupt Behavior in case of Bus New 33 Off MultiCAN TC H002 Double Synchronization of receive input 34 MultiCAN TC H003 Message may be discarded before 34 transmission in STT mode MultiCAN TC H004 Double remote request 35 PIN XC8 H001 Current over GPIO pin must not source 35 Vppp higher than 0 3V PM XC8 H001 Clock source selection before entering 36 power down mode PM 8 002 SAK product variant does not support 36 power down mode SYS XC8 H001 Usage of the Bit Protection Scheme 36 XC878CLM Series AC 5 38 Rel 1 2 17 01 2013 Infineon Errata Sheet History List Change Summary Table 6 Application Hints cont d Hint Short Description Chg Pg SYS XC8 H002 External Clock switching routine after a 37 WDT reset SYS XC8 H003 Effective write for Read Modify Write New 37 instructions of two bytes one machine cycle T2 XC8 H003 Accessing Timer 21 registers 38 XC878CLM Series AC 6 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations 2 Functional Deviations BROM XC8 006 IRAM data is corrupted after any warm reset After any warm reset i e
25. s No of CCLK cycles without wait states INC dir 05 DEC dir 15 ANL dir A 52 ORL dir A 42 XRL dir A 62 XCH A dir C5 CLR bit C2 NO DM DM DM 1 Applicable also to Flash memory with parallel read feature XC878CLM Series AC 37 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Application Hints Table 12 Mnemonic Hex Code Bytes No of CCLK cycles without wait states SETB bit D2 2 2 CPL bit B2 2 2 T2 XC8 H003 Accessing Timer 21 registers To access Timer 21 registers T2 page needs to be setup by clearing bit field T2 PAGE PAGE to 000p XC878CLM Series AC 38 38 Rel 1 2 17 01 2013
26. ters and therefore it is written with the wrong value of the register Sample Code interrupt MUL A B MOV CC60SRL A MOV P1 DATA CC60SRL MOV CC60SRH B RETI Workaround Instead of using the MOV direct direct instruction use other instructions or an intermediate variable to write to the targeted register For example the two MOV direct direct instructions in the earlier sample code can be replaced with MOV direct A instructions hex code F5 Both the P1 DATA and CC60SRH registers will now be written with the correct source register values Sample Code interrupt MUL A B MOV CC60SRL A MOV Pl DATA XCH A B MOV CC60SRH A RETI XC878CLM Series AC 25 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations SYS XC8 003 Brownout Reset Brownout reset may not be triggered when the core supply voltage VDDC drops below operating limit It is recommended to use an external voltage detector and perform a power on reset when the core supply voltage drops below 2 2V minimum Workaround None T2CCU XC8 003 T2CCU Capture Functions Capture mode 1 is the only T2CCU capture mode in XC878 AC step Capture mode 0 of T2CCU is not functioning In mode 1 a capture will occur upon writing to the low byte of the corresponding channel capture register CCxL Workaround None UART XC8 002 Bits FDEN and FDM in UART1 FDCON SFR cannot be Writ ten by Read Modify Write Instruc
27. tion Scheme When the bit protection scheme is enabled bit field PASSWD PASS should always be used to open and close write access to the protected bits The scheme should be disabled only if it is not required in the application XC878CLM Series AC 36 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Application Hints In the unlikely event that the scheme is enabled again after disabling it while the write access is still open the write access will remain open until the count of 32 CCLK cycles is completed SYS XC8 H002 External Clock switching routine after a WDT reset When a WDT reset happens the clock system will not be reset If user needs to run the clock switching routine after WDT reset the bit field OSC CON OSCSS should be clear to 0 before activating the routine SYS XC8 H003 Effective write for Read Modify Write instructions of two bytes one machine cycle When read modify write instructions requiring 2 bytes and 1 machine cycle equivalent to 2 CCLK cycles for execution such as INC dir are executed from memories without any wait states the actual write to the destination is delayed by the internal bus for up to one CCLK cycle This means that even though the CPU completes the instruction execution after 2 CCLK cycles the write through the internal bus may take effect only after a further CCLK cycle The list of affected read modify write instructions is shown below Table 12 Mnemonic Hex Code Byte
28. tion transmission of a CAN frame if bit MOFCR SDT is set After a transmission MultiCAN also looks at the respective transmit FIFO base object and clears bit MSGVAL in the base object if bit SDT is set in the base object and pointer MOFGPR CUR points to MOFGPR SEL after the pointer update Gateway Destination Fifo slave object MultiCAN clears bit MOCTR MSGVATL after the storage of a CAN frame into the object gateway FIFO action or after the successful transmission of a CAN frame if bit MOFCR SDT is set After a reception MultiCAN also looks at the respective FIFO base Gateway source object and clears bit MSGVAL in the base XC878CLM Series AC 13 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Functional Deviations object if bit SDT is set in the base object and pointer MOFGPR CUR points to MOFGPR SEL after the pointer update Problem description Standard message objects After the successful transmission reception of a CAN frame MultiCAN also looks at message object given by MOFGPR CUR If bit SDT is set in the referenced message object then bit MSGVAL is cleared in the message object CUR is pointing to Transmit FIFO slave object Same wrong behaviour as for standard message object As for transmit FIFO slave objects CUR always points to the base object the whole transmit FIFO is set invalid after the transmission of the first element instead after the base object CUR pointer has reached the predefined SEL li
29. tions The bits FDEN and FDM UART1 FDCON SFR are not updated when written with the read modify write instructions listed in the table below Table 9 Affected Read Modify Write Instructions Hex Code INC dir 05 DEC dir 15 ANL dir 52 ANL dir data 53 ORL dir A 42 ORL dir data 43 XC878CLM Series AC 26 38 Rel 1 2 17 01 2013 infineon Errata Sheet Table 9 Functional Deviations Affected Read Modify Write Instructions Hex Code XRL dir A 62 XRL dir data 63 A dir C5 DJNZ dir rel D5 Workaround Use MOV instructions except MOV dir dir Hex Code 85 when writing to the bits FDEN and FDM in UART1 FDCON SFR XC878CLM Series AC 27 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Deviations from Electrical and Timing Specification 3 Deviations from Electrical and Timing Specification XC878CLM Series AC 28 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Application Hints 4 Application Hints ADC XC8 H001 Arbitration mode when using external trigger at the se lected input line REQTR If an external trigger is expected at the selected input line REQTR to trigger a pending request the arbitration mode should be set PRAR ARBM 1 where the arbitration is started by pending conversion request This selection will minimize the jitter between asynchronous external trigger with respect to the arbiter and the start of the con
30. to be started again message objects with pending transmit request might not be transmitted at all due to failed transmit acceptance filtering Workaround EITHER Avoid deallocation of the first element on active CAN nodes Dynamic reallocations on message objects behind the first element are allowed OR e Avoid list operations on a running node Only perform list operations if CAN node is not in use e g when NCRx INIT 1 MultiCAN TC 032 MSGVAL wrongly cleared in SDT mode When Single Data Transfer Mode is enabled MOFCRn SDT 1 the bit MOCTRn MSGVAL is cleared after the reception of a CAN frame no matter if it is a data frame or a remote frame In case of a remote frame reception and with MOFCR FRREN the answer to the remote frame data frame is transmitted despite clearing of MOCTRn MSGVAL incorrect behaviour If however the answer data frame does not win transmit acceptance filtering or fails on the CAN bus then no further transmission attempt is made due to cleared MSGVAL correct behaviour Workaround To avoid a single trial of a remote answer in this case set MOFCR FRREN 1g and MOFGPR CUR this object MultiCAN TC 035 Different bit timing modes Bit timing modes NFCRx CFMOD 10g do not conform to the specification XC878CLM Series AC 17 38 Rel 1 2 17 01 2013 infineon When the modes 001 100 are set in register NFCRx CFSEL the actual configured mode and behaviour is d
31. unctional and electrical characteristics therefore they should be used for evaluation only The specific test conditions for EES and ES are documented in a separate Status Sheet XC878CLM Series AC 2 38 Rel 1 2 17 01 2013 Infineon Errata Sheet History List Change Summary 1 History List Change Summary Table 2 History List Version Date Remark 1 0 11 09 2009 1 1 26 05 2010 Table 3 Errata fixed in this step Errata Short Description Chg T2CCU XC8 001 External Trigger of ADC when CCT of T2CCU Fixed overflows Table 4 Functional Deviations Functional Short Description Chg Pg Deviation BROM XC8 006 data is corrupted after any warm 7 reset CD XC8 001 Set and Clear of Error Bitin CORDIC Linear 7 Vectoring Mode CD XC8 002 Data Fetch to CD STATC Register may 8 capture an incorrect error status MultiCAN AI 040 Remote frame transmit acceptance 8 filtering error MultiCAN_AI 041 Last Obj 9 XC878CLM Series AC 3 38 Rel 1 2 17 01 2013 infineon Errata Sheet History List Change Summary Table 4 Functional Deviations cont d Functional Short Description Chg Pg Deviation MultiCAN_AI 042 Clear MSGVAL during transmit 9 acceptance filtering MultiCAN 1 043 Dealloc Previous Obj 10 MultiCAN 1 044 RXFIFO Base SDT 11 MultiCAN 1 045 OVIE Unexpected Interru
32. version The jitter can only be minimized while no other conversion is running and no higher priority conversion can cancel the triggered conversion In this case a constant delay no jitter has to be taken into account between the trigger event and the start of the conversion BROM XC8 H001 SYSCONO RMAP handling in ISR The ISR has to handle SYSCONO RMAP correctly when Flash user routines provided in the Boot ROM are used together with the interrupt system Any ISR with the possibility of interrupting these user routines has to do the following in the interrupt routine save the value of the RMAP bit at the beginning restore the value before the exit This is to prevent access of the wrong address map upon return to the Flash user routine since the RMAP bit may be changed within the interrupt routine The critical point is when Flash user routines sets RMAP to 1 and the interrupt occurs that needs RMAP at 0 in the ISR Please note that NMI is an interrupt as well XC878CLM Series AC 29 38 Rel 1 2 17 01 2013 Infineon Errata Sheet Application Hints CCU6 XC8 H001 Pin Configuration of CCU6 Functions Table 10 shows the updated pin configuration of CCU6 pins 878 Table 10 Updated CCU6 Pin Configuration CCU6 Functions Pin Symbol CCPOSO 0 CCU6 Hall Input 0 P5 4 CCPOS1_0 CCU6 Hall Input 1 P5 3 60 3 Input of Capture Compare Channel 0 P5 3 CC61 3 Input of Capture Compare Channel 1 P5 4 C
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