MAX24104 15Gbps Quad Linear Equalizer
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1. MAX24104 General Description The MAX24104 restores high frequency signal level at the decision feedback equalizer DFE receiver for high loss backplane and cable channels This permits the DFE receiver to meet BER goals At 15Gbps the MAX24104 can operate in channels with FR4 and cable HF loss of more than 30dcB at 7 5GHz The linear transfer function is transparent to Adaptive DFE equalizers permitting DFE adaptation to track temperature and changing channel conditions Together with the DFE integrated into Serializer Deserializer SERDES the device adds increased mar gin rather than full signal regeneration Unlike conven tional equalizers with limiting output stages the device preserves the linear channel characteristics allowing the DFE to operate linearly over the entire channel This permits extending total channel reach and or improving signal to noise ratio SNR The device typically compen sates for up to 19dB of the total loss in a long channel effectively reducing the channel length seen by the DFE receiver The device has four channels and is packaged in a space saving 4mm x 6 5mm FCLGA package Applications e 1Gbps to 15Gbps High Speed Backplanes and Cables e 12 5Gbps Quad XAUI Interconnect e 14Gbps 16G Fiber Channel e 12Gbps SAS III Typical Application Circuit 15Gbps Quad Linear Equalizer Benefits and Features e Low Power Consumption Reduces Operating Cost Single 2 5V Supply e 131mW2. 1 2 RX1P RX1N Differential Channel 1 Input CML 3 6 9 VCCR Positive Receive Power Supply 2 5V Filter each pin with a 0 1uF capacitor to GND 4 5 RX2P RX2N Differential Channel 2 Input CML 7 8 RX3P RX3N Differential Channel 3 Input CML 10 11 RX4P RX4N Differential Channel 4 Input CML J3 I2C_EN 12C Enable Input LVCMOS Hardwire low for pin control Hardwire high for 12C control User must select mode of operation before power on reset 13 VCCP Positive Power Supply 2 5V Filter each pin with a 0 1uF capacitor to GND 14 LDO_DIG Compensation capacitor pin for internal LDO Bypass pin with a 0 22uF capacitor to GND 15 SCL Analog 12C Serial Interface Clock Input Use external 4 7kQ pullup to Vcc 16 SDA Analog 12C Serial Interface Data Input and Output Use external 4 7kQ pullup to Vcc 17 PGM_OUT Cascadable 12C Output LYCMOS See the Slave Address Configuration section www maximintegrated com Maxim Integrated 10 MAX24104 15Gbps Quad Linear Equalizer Pin Description continued PIN NAME FUNCTION 18 19 TX4N TX4P Differential Channel 4 Output CML 20 23 26 VCCT Positive Transmit Power Supply 2 5V Filter each pin with a 0 1uF capacitor to GND 21 22 TX3N TX3P Differential Channel 3 Output CML 24 25 TX2N TX2P Differential Channel 2 Output CML 27 28 TX1N TX1P Differential Channel 1 Output CML 29 PGM_IN Cascadable 12C Input Has 30kQ pulldown see the 2C Address Configuration section Power
3. During the acknowledge cycle the direction of the SDA line is reversed and the slave pulls SDA low to return a 0 ACK to the master The MAX24104 interprets the first data byte as a register address This is used to set an internal memory pointer Subsequent data bytes within the same transaction will then be written to the memory location addressed by the pointer The pointer is auto incremented after each byte There is no limit to the number of bytes which may be written in a single burst to the internal registers of the MAX24104 ADDRESS 15Gbps Quad Linear Equalizer Read Transaction In a read transaction the slave address byte is success fully acknowledged by the slave and the type bit is set high After the ACK the slave returns a byte from the loca tion identified by the internal memory pointer This pointer is then auto incremented The slave then releases SDA so that the master can ACK the byte If the slave receives an ACK then it will send another byte The master identi fies the last byte by sending a NACK to the slave The master then issues a STOP to terminate the transaction Thus to implement a random access read transaction a write must first be issued by the master containing a slave address byte and a single data byte the register address This sets up the memory pointer A read is then sent to retrieve data from this address Figure 8 Device Addressing www maximintegrated com Maxim Integr
4. 1 61 1 96 typical Ta 40 C 1 62 3 60 FGx 1 0 11 1 68 FGx 1 0 10 0 14 FGx 1 0 01 1 36 Flat Gain 100MHz EQx 3 0 a 1000 TXAx 1 0 10 GNe FGx 1 0 00 2 87 dB n Ta 85 C 3 24 1 72 Variation around Ta 25 C 251 12 85 typical Ta 40 C 2 59 3 67 TXAx 1 0 11 1000 1370 1dB Compression Point y TXAx 1 0 10 1280 aN Output Swing at 100MHz 1dB_OUT TXAx 1 0 01 1040 PR TXAx 1 0 00 920 TXAx 1 0 11 1000 1dB Compression Point TXAx 1 0 10 940 Output Swing Note 5 at V1dB_OUT mVp p 7 5GHz TXAx 1 0 01 700 TXAx 1 0 00 600 100MHz to 7 5GHz FGx 1 0 11 06 isle est seu Noi y EQx 3 0 0000 Figure 3 y nput Referred Noise m P NOISE 400MHz to 7 5GHz FGx 1 0 11 ae RMS EQx 3 0 1010 Figure 3 100MHz to 7 5GHz FGx 1 0 11 08 Output Referred Noise 7 EQx 3 0 0000 Figure 3 l aay Note 3 NOISE 400MHz to 7 5GHz FGx 1 0 11 E ee BMS www maximintegrated com Maxim Integrated 3 MAX24104 15Gbps Quad Linear Equalizer Electrical Characteristics continued Typical values are at Vecer Vect Vccp 2 5V Ta 25 C See Figure 1 for typical supply filtering Note 2 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS HIGH SPEED I O Input Common Mode Voltage Vicm 2 10 V DC differential resistance 100 Input Resistance RIN AC common mode single ended 50 Q resist
5. Down Enable Pin LVCMOS Three state pin to program the power mode of the part at startup For high and open see Table 5 for settings Set low for reset Reset 30 ENABLE disables all communication to the chip along with resetting the registers to their default states zi APPLICATION Application Select Input LVCMOS Select between channel cases short and long Set low or open for long Set high for short 3 OUTPUT_LEVEL Output Level Control LVCMOS Three state pin to program the output level of all channels See Table 4 for settings Be EQ PEAKING Equalization Control Pin LVCMOS Three state pin to program the equalization level of all channels See Table 2 for settings z FLAT_GAIN Gain Adjust Control Pin LVCMOS Three state pin to program the flat gain level of all channels See Table 3 for settings Exposed Pad Internally connected to GND Ground reference for power supplies three EP state and other low speed pins Connect EP to a large ground plane to maximize thermal performance www maximintegrated com Maxim Integrated 11 MAX24104 Functional Diagram 15Gbps Quad Linear Equalizer 4 CHANNELS EQUALIZER 500 500 RX1P RX1N LANE 1 OF 4 FLAT GAIN OUTPUT BUFFER A A CONTROL EQ_PEAKING FLAT GAIN OUTPUT LEVEL Detailed Description The MAX24104 is
6. a 4 channel linear equalizer EQ func tioning up to 15Gbps Each channel has a programmable equalization network and programmable flat gain adjust All controls for equalization gain output enable disable etc are individually programmed through the on chip programming block The programming block can be con trolled either through pin controls or the 12C serial bus APPLICATION Pin Control The placement range of a linear equalizer is limited by its dynamic range and noise performance To allow the widest placement range the MAX24104 has two optimi zations The two cases are Short and Long Channels By selecting the case based on channel loss as shown in Table 1 the best dynamic range and noise operating points can be selected for the application www maximintegrated com Input Termination The input termination consists of two 500 resistors form ing a differential termination between the input pins The excellent return loss minimizes reflections in a channel Table 1 APPLICATION Pin Control CHANNEL LENGTH Short Channel OdB to 18dB channel loss before MAX24104 Long Channel 18dB to 33dB channel loss before MAX24104 INPUT LEVEL High Low Open Maxim Integrated 12 MAX24104 Receive Equalizer For the MAX24104 the input data goes into a selectable equalization stage The receive equalizer is designed to compensate losses up to 19dB at 7 5GHz The select able equalizatio
7. and EQ Placement in Channel Calculator Several simple Microsoft Excel spreadsheet tools are available to assist in the application of the MAX24104 Linear EQs Please visit www maximintegrated com to access the latest version of these spreadsheets I2C Interface The SDA and SCL pins are referred to as the slave 12C The slave 12C provides external access to the register set within the MAX24104 Typically an MCU is connected to the slave 12C Framing and Data Transfer An individual transaction is framed by a START condition and a STOP condition A START condition occurs when a bus master pulls SDA low while SCL is high A STOP condition occurs when the bus master allows SDA to tran sition low to high when SCL is high Within the frame the master has exclusive control of the bus The MAX24104 supports Repeated START conditions whereby the mas ter may simultaneously end one frame and start another without releasing the bus by replacing the STOP condition with a START condition Within a frame the state of SDA only changes when SCL is low A data bit is transferred on a low to high transition Vour txa Flatgain vgc Peak Gain eq a UPDATE 15Gbps Quad Linear Equalizer of SCL Data is arranged in packets of 9 bits The first 8 bits represent data to be transferred most significant bit MSB first The last bit is an acknowledge bit from the slave The recipient of the data holds SDA low during the ninth clock cycle of
8. swing after pre emphasis e g long CID LF content Note that 0 5Vp _p fits easily under the 1dB Compression line If the Source Tx were to have higher LF swing driving linear EQ into nonlinearity the linear EQ flat gain control can be used to attenuate input signal level as needed to maintain linearity For example Maximum Linear EQ Flat Gain setting Linear EQ Output Level setting 1dB compression dBV Source Tx Level dBV Source Tx Pre Emphasis De emphasis dB User System Margin dB For example Linear EQ Output Level setting 1dB compression dBV 3dBV Source Tx Level dBV 0dB Source Tx Pre Emphasis De emphasis dB 6dB User System Margin 2dB Then Maximum Linear EQ Flat Gain setting 3 0 6 2 1dB There are three Flat Gain settings available lower than 1dB They are 3dB 1 5dB 0dB Step 2 Maintain EQ Linearity at High Frequency Nyquist A linear equalizer when placed too close to a Source Tx is vulnerable to nonlinear compression at high frequency Nyquist especially if the EQ peaking gain is higher than the preceding channel loss The 1dB compression specification gives maximum output level that guarantees linear operation As a function of the EQ settings the mini mum placement distance from the Source Tx is calculated as follows see Position 1 in Figure 5 www maximintegrated com 15Gbps Quad Linear Equalizer Minimum Distance Nyquist Loss from Source Tx dB S
9. 0 0 0 0 0 ACCESS RW RW RW RW RW RW RW RW REGCONT14 Selects channel settings for channels 1 4 from pin control or I C accessible registers 0 pin control equalizer peaking flat gain and output amplitude 1 12C accessible registers CH1OFF Disables channel 1 0 enabled 1 disabled CH2OFF Disables channel 2 0 enabled 1 disabled CH30FF Disables channel 3 0 enabled 1 disabled CH4OFF Disables channel 4 0 enabled 1 disabled www maximintegrated com Maxim Integrated 23 MAX24104 Exposed Pad Package The exposed pad of the MAX24104 package incorpo rates features that provide a very low thermal resistance path for heat removal from the IC The exposed pad on the MAX24104 must be soldered to the circuit board for proper thermal performance and correct electrical grounding For more information on exposed pad pack ages refer to Maxim Application Note 862 HFAN 08 1 Thermal Considerations of QFN and Other Exposed Paddle Packages Interface Schematics MAX24104 Figure 12 CML Equivalent Input Structure www maximintegrated com 15Gbps Quad Linear Equalizer Layout Considerations Circuit board layout and design can significantly affect the performance of the MAX24104 Use good high frequency design techniques including minimizing ground induc tance and using controlled impedance transmission lines on the data s
10. 0 0 0 0 0 ACCESS RW RW RW RW RW RW RW RW EQ2 3 0 Sets the equalizer peaking for channel 2 See Table 6 for values FG2 1 0 Sets the flat gain for channel 2 See Table 7 for values TXA2 1 0 Sets the output amplitude for channel 2 See Table 8 for values www maximintegrated com Maxim Integrated 22 MAX24104 Register 03h Lower I2C Address Channel 3 15Gbps Quad Linear Equalizer BIT 7 6 5 4 3 2 1 0 NAME EQ3 3 EQ3 2 EQ3 1 EQ3 0 FG3 1 FG3 0 TXA3 1 TXA3 0 DEFAULT VALUE 0 0 0 0 0 0 0 0 ACCESS RW RW RW RW RW RW RW RW EQ3 3 0 Sets the equalizer peaking for channel 3 See Table 6 for values FG3 1 0 Sets the flat gain for channel 3 See Table 7 for values TXA3 1 0 Sets the output amplitude for channel 3 See Table 8 for values Register 04h I2C Address Channel 4 BIT 7 6 5 4 3 2 1 0 NAME EQ4 3 EQ4 2 EQ4 1 EQ4 0 FG4 1 FG4 0 TXA4 1 TXA4 0 DEFAULT VALUE 0 0 0 0 0 0 0 0 ACCESS RW RW RW RW RW RW RW RW EQ4 3 0 Sets the equalizer peaking for channel 3 See Table 6 for values FG4 1 0 Sets the flat gain for channel 3 See Table 7 for values TXA4 1 0 Sets the output amplitude for channel 3 See Table 8 for values Register 05h 12C Address Channel 1 4 Controls BIT 7 6 5 4 3 2 1 0 NAME Reserved Reserved Reserved REGCONT14 CH1OFF CH2O0FF CH30FF CH40FF DEFAULT VALUE 0 0 0
11. 0 TXAx 1 0 11 FGx 1 0 10 0 2 4 6 8 10 0 2 4 6 8 10 FREQUENCY GHz Maxim Integrated 8 MAX24104 15Gbps Quad Linear Equalizer Typical Operating Characteristics continued Typical values are at Vecer Vect Vcc_pc 2 5V Ta 25 C unless otherwise noted MAX24104 SINGLE ENDED OUTPUT AFTER 18in FR4 AT INPUT EQx 3 0 1110 FGx 1 0 01 TXAx 1 0 11 10 3Gbps 50mV div 20ps div SINGLE ENDED OUTPUT FROM BERT SOURCE 12Gbps toc10 100mVidiv 20ps div MAX24104 SINGLE ENDED OUTPUT AFTER 18in FR4 AT INPUT EQx 3 0 1110 FGx 1 0 01 TXAx 1 0 11 12Gbps toc12 2 he a Re Ree SRR SER 50mV div 20ps div www maximintegrated com MAX24104 SINGLE ENDED OUTPUT AFTER 18in FR4 AT INPUT EQx 3 0 1110 FGx 1 0 01 TXAx 1 0 11 13 5Gbps 50mV div 20ps div SINGLE ENDED OUTPUT FROM BERT SOURCE AFTER 18in FR4 12Gbps toc11 100mV div soo mvs 20ps div MAX24104 SINGLE ENDED TIME DOMAIN OUTPUT VS EQUALIZATION LEVEL FGx 1 0 01 TXAx 1 0 11 WITH 18in FR4 AT 1Gbps toc13 62mV div 100ps div Maxim Integrated 9 MAX24104 15Gbps Quad Linear Equalizer Pin Configuration TOP VIEW 33 EQ_PEAKING Pin Description PIN NAME FUNCTION
12. 1 9 5 12 0 13 8 17 0 1010 8 9 11 4 13 2 16 4 1001 8 4 10 8 12 6 15 7 1000 7 9 10 2 11 9 15 1 0111 7 5 9 7 11 4 14 6 j 0110 7 0 9 1 10 8 13 9 0101 6 5 8 5 10 1 13 2 0100 5 6 7 5 9 1 12 1 0011 4 8 6 5 8 0 10 9 0010 3 8 5 4 6 7 9 5 0001 2 7 4 0 5 2 7 9 0000 1 8 2 6 3 4 6 0 Table 7 FLAT_GAIN Bit Control FGx 1 0 FLAT GAIN UNITS 11 1 68 10 0 14 01 1 36 a 00 2 87 Table 8 OUTPUT_LEVEL Bit Control TXAx 1 0 OUTPUT LEVEL UNITS 11 1000 10 940 01 700 MARP 00 600 Maxim Integrated 21 MAX24104 15Gbps Quad Linear Equalizer Register Map Table 9 Register Configuration ADDRESS 2C ADDRESS 00h Reserved read only 01h Channel 1 02h Channel 2 03h Channel 3 04h Channel 4 05h Channel 1 4 Controls 06h Reserved 07h Reserved 08h Reserved 3Ch 12C address Register 01h 12C Address Channel 1 BIT 7 6 5 4 3 2 1 0 NAME EQ1 3 EQ1 2 EQ1 1 EQ1 0 FG1 1 FG1 0 TXA1 1 TXA1 0 DEFAULT VALUE 0 0 0 0 0 0 0 0 ACCESS RW RW RW RW RW RW RW RW EQ1 3 0 Sets the equalizer peaking for channel 1 See Table 6 for values FG1 1 0 Sets the flat gain for channel 1 See Table 7 for values TXA1 1 0 Sets the output amplitude for channel 1 See Table 8 for values Register 02h I2C Address Channel 2 BIT 7 6 5 4 3 2 1 0 NAME EQ2 3 EQ2 2 EQ2 1 EQ2 0 FG2 1 FG2 0 TXA2 1 TXA2 0 DEFAULT VALUE 0 0 0
13. 10 Frequency Hz Maxim Integrated 16 MAX24104 15Gbps Quad Linear Equalizer MAX24104 10 3Gbps Linear EQ Calculate Placement Range in Channel ASIC TX T TX HF Level Nyquist dBVpp L TX LF Level long CID dBVpp D TX De Emphasis dB L T D Loss A Entry Box in Yellow ASIC TX SETTINGS T Tx HF Level mVpp i dBVpp 0 00 D Tx De Emphasis dB 3 0 STEP 1 Make sure that L Tx LF Level is less than EQ LF compression level L Tx LF Level mVpp dBVpp 3 00 LINEAR EQ CL LF 1dB Compr Level dBVpp CH HF 1dB Compr Level dBVpp n Noise dBVpp BER P Peaking Gain HF re LF dB F Flat Gain LF dB LINEAR EQ Placement Range Pull Down Box in Pink Pull Down LINEAR EQ SETTINGS P Peaking Gain HF reLF dB _ 15 F Flat Gain LF dB io Input Ref Mult Output Ref n Refer d Noise mVrms mVpp dBVpp CL LF 1dB Compress mVpp dBVpp RESULTS Keeps Nyquist 010101 level below EQ HF compression level A Farthest from Rx dB lt Over PVT lt CH Output Ref N M Keeps Nyquist above DFE IRN to meet BER and constrain RJ gen Figure 7 EQ Placement Calculator www maximintegrated com CH HF 1dB Compress mVpp dBVpp L 12 0 m Margin dB Nyquist above n dBVpp BER recommend gt 16dB for RJ lt 0 10Ulpp recommend gt 12dB for RJ lt 0 16Ulpp EQ PLACEMENT Loss Nyauist Keeps Nyqui
14. E VLAUNCH measured at source source HF 1200 mVp_p Frequency Voltage i pre emphasis swing can be higher Source Rise Fall Time Test source 10 to 90 26 ps Source Common Mode DC 200MHz 150 mVp p Noise Supply Noise DC 1MHz 50 mVp p Electrical Characteristics Typical values are at Vecer Vect Vccp 2 5V Ta 25 C See Figure 1 for typical supply filtering Note 2 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IccR Total supply TXAx 1 0 00 204 275 Supply Current lect current with all 4 mA locp channels enabled TXAx 1 0 11 250 305 Supply Current During mA Power Down a www maximintegrated com Maxim Integrated 2 MAX24104 15Gbps Quad Linear Equalizer Electrical Characteristics continued Typical values are at Vocr Vect Vecp 2 5V Ta 25 C See Figure 1 for typical supply filtering Note 2 EQx 3 0 1010 Figure 3 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Beyond steady state supply current Inrush Current with supply ramp up time less than lt 10 200us Residual Deterministic Jitter DJ ei sro soi linear 9 S Notes 3 4 RX p pSp p range EQx 3 0 1110 18 5 EQx 3 0 1001 15 7 Peaking Gain pe Compensation at 7 5GHz GN EQx 3 0 0101 13 2 JB relative to 100MHz F Ta 85 C 3 67 0 82 100mVp p Sine Wave Input jati p p Si ve Input Variation around Ta 25 C
15. FRA MAX24104 OSCILLOSCOPE OR IT ERROR DETECTOR SMA Va CONNECTORS 2in lt L lt 30in iN SMA L 2in CONNECTORS FR4 4 0 lt ER lt 44 tand 0 022 Figure 2 Receiver Test Setup Points Labeled A B and D are Referenced for AC Parameter Test Conditions www maximintegrated com Maxim Integrated 6 MAX24104 15Gbps Quad Linear Equalizer MAX24104 LOWPASS RX_ TX_ FILTER POWER METER GIGATRONICS 8652A WITH 80301A HEAD 10MHz to 18GHz BALUN PSPL 5315A RX_ TX 200kHz TO 17GHz Figure 3 Noise Test Configuration 4 PORT VECTOR NETWORK ANALYZER N52454 AGGRESSOR SIGNAL MAX24104 0dBm RX1 TX1 RX1 TX1 RX2 TX2 VICTM VICTIM OUTPUT INPUT zo Figure 4 Channel lsolation Test Configuration www maximintegrated com Maxim Integrated 7 MAX24104 Typical Operating Characteristics 15Gbps Quad Linear Equalizer Typical values are at Vecer Vect Vcc_pc 2 5V Ta 25 C unless otherwise noted DETERMINISTIC JITTER vs EQUALIZATION SETTING FREQUENCY GHz www maximintegrated com DETERMINISTIC JITTER vs EQUALIZATION SETTING toc02 1dB Comp
16. PGM_OUT The PGM_IN pin on the first MAX24104 in the chain can be tied low or left unconnected because the PGM_IN pin has an internal pulldown resistor SDA DIRECTION lt _ FROM SLAVE DIRECTION TO SLAVE Figure 10 Read Transaction www maximintegrated com FROM SLAVE TO SLAVE _ gt TO SLAVE 5 FROM SLAVE Maxim Integrated 19 MAX24104 I2C Address Configuration The new features of this interface compared to a conven tional 12C interface are e The daisy chain PGM_IN and PGM_OUT pins e A device_address register 7 bits 7 1 Bit O in this register is used as a 12C read write bit e An internal write_once bit At power up the write_once bit will be set to 1 and the device 12C address will be set to its default value A2h All MAX24104 devices will respond to read and writes to this slave address until a write to register 3Ch is performed The required 12C address of device 1 7 bit 15Gbps Quad Linear Equalizer address x 2 is then assigned by writing to pgm_register 3Ch at 12C address A2h All devices accept the new address value for example 10h Each device then starts to increment it on SCL edges while PGM_IN is high The program_reset signal ripples down the chain fixing the 12C address such that device N has an I2C address of address 2 2 x N 1 for example device 1 at 10h devic
17. Per Channel typ at 700mVp p Output e Lower Power Lower Cost and Smaller Board Footprint than CDR Solutions e Linear Performance for Greater System Flexibility e 1Gbps to 15Gbps Linear Equalization e Increases High Frequency Signal Level to Help Rx DFE Achieve BER Goals e Selectable Output Linear Swing from 700mVp p to 1000mVp p e Input Return Loss Better than 16dB Up to 7 5GHz e Adjustable Features for Greater Flexibility e Selectable EQ Peaking Spanning 6dB to 19dB at 7 5GHz e Selectable Flat Gain Spanning 2 9dB to 1 7dB e Integration Allows Greater Design Flexibility e 12C Daisy Chain for Addressing Up to 63 ICs e Plug and Play Set Control Pins All Channels Set the Same or Independent Control of Each Channel through 12C Bus e Transparent to Link Training OOB and Idle and Data Rate and Coding Agnostic 4mm x 6 5mm FCLGA Package MAX24104 BACKPLANE Ordering Information appears at end of data sheet For related parts and recommended products to use with this part refer to 19 7346 Rev 1 4 15 www maximintegrated com MAX24104 related maxim integrated MAX24104 15Gbps Quad Linear Equalizer Absolute Maximum Ratings Power Supply Voltage cccsscccccssseeeeeessseeeeees 0 5V to 4 0V Output CUrrent cccccceeceeteeeeeseeeessseeeeeeeeee 90mA to 90mA DC Input Voltage Applied all control pins except SDA Operating Junction Temperat
18. VEL APPLICATION LOW OPEN APPLICATION HIGH High EQx 3 0 1110 EQx 3 0 1001 Open EQx 3 0 1001 EQx 3 0 0101 dB Low EQx 3 0 0101 EQx 3 0 0011 Table 3 FLAT_GAIN Pin Control refer to Table 7 CONTROL PIN LONG CHANNEL SHORT CHANNEL inie INTPUT LEVEL APPLICATION LOW OPEN APPLICATION HIGH High FGx 1 0 11 FGx 1 0 10 Open FGx 1 0 10 FGx 1 0 01 dB Low FGx 1 0 01 FGx 1 0 00 Table 4 OUTPUT_LEVEL Pin Control refer to Table 8 CONTROL PIN PUT LEVEL OUTPUT AMPLITUDE UNITS High TXAx 1 0 11 Open TXAx 1 0 10 mVp p Low TXAx 1 0 01 Table 5 ENABLE and Reset Pin Control CONTROL PIN INPUT LEVEL 12C CONTROL MODE PIN CONTROL MODE ENABLE I2C_EN high I2C_EN low High Upon POR or reset power down all channels Power down all channels Open Upon POR or reset power on all channels Power on all channels Low www maximintegrated com Reset POR Reset POR Maxim Integrated 13 MAX24104 Applications Information Linear Equalizer EQ Placement and Use in 3 Steps Placement of linear equalizers in lossy channels is bounded by output linearity and input noise IRN See Figure 5 Although placement is quite flexible it is important to maintain linear operation with sufficient SNR hence the boundary conditions stated in the following two sections Tx1Vp p W 6dB PE POSITION 1 15Gbps Quad Linea
19. a data packet to acknowledge ACK the byte Leaving SDA left open on the ninth bit signals a not acknowledged NACK condition The interpretation of the acknowledge bit by the sender depends on the type of transaction and the nature of the byte being received SDA is bidirectional so that the master may send data bytes during write transactions and the slave may send data bytes during reads Device Addressing The first byte to be sent after a START condition is a slave address byte The first seven bits of the byte contain the target slave address MSB first The eighth bit indicates the transaction type 0 write 1 read Each slave interface on the bus is assigned a 7 bit slave address If no slave matches the address broadcast by the master then SDA will be left open during the acknowledge bit and the master receives a NACK The master must then assert a STOP condition If a slave identifies the address then it acknowledges it by pulling SDA low The master then proceeds with the transaction identified by the type bit The two wire interface of the MAX24104 decodes slave addresses ranging from OOh to 3Fh MAX24104 FREQUENCY RESPONSE MAX24104 TXA2 VGC3 EQ15 TXA2 VGC2 EQ7 TXA1 VGC1 EQ3 TXAO VGCO EQO Figure 6 Frequency Response Plotting Microsoft Excel is a registered trademark of Microsoft Corp www maximintegrated com 1E
20. ance 10MHz to 7 5GHz Differential gt 16 Input Return Loss S11 dB 1GHz to 7 5GHz Common mode gt 10 DC differential resistance 100 Output Resistance Rout AC common mode single ended 50 Q resistance Pulse Response Ringing 3 Intra Pair Skew 2 ps Inter Pair Skew 4 ps 10MHz to 7 5GHz Differential gt 13 Output Return Loss S22 dB 1GHz to 7 5GHz Common Mode gt 8 100MHz to 7 5GHz Figure 4 Channel Isolation Vcoup Note 6 40 dB LVCMOS I O eo 0 7 x Vcc Input Logic High Voltage VIH Vec 03 V Input Logic Low Voltage VIL 0 3 03x V Vcc M Vcc Output Logic High Voltage VOH At lop 200A 02 V Output Logic Low Voltage VoL At lo 200A 0 2 V Open State Current Tolerance Hiz 5 uA VIH MIN lt Vin lt ViH MAx all other 225 Input Logic High Current lH CMOS pins uA VIHMIN lt Vin lt Vin mMax PGM_IN 120 VIL MIN y VIN lt VIL MAX all other 225 Input Logic Low Current liL CMOS pins uA VIL MIN lt Vin lt ViL MAX PGM_IN 18 www maximintegrated com Maxim Integrated 4 MAX24104 15Gbps Quad Linear Equalizer Electrical Characteristics continued Typical values are at Voce Vect Vccp 2 5V Ta 25 C See Figure 1 for typical supply filtering Note 2 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 12C CHARACTERISTICS SDA SCL Note 7 Low Level Input Voltage VIL 09x V Vcc High Level Input Voltage Wid ee v Vcc Input Hysteresis Vuys 200 mV Inpu
21. ated 18 MAX24104 I2C Access Destination The MAX24104 does not provide any security level on the I2C serial bus Accesses to unimplemented registers in the device are discarded in the case of a write and return an unpredictable value in the case of a read During burst mode accesses destination addresses are tested on a byte by byte basis Slave Address Configuration The slave address of the MAX24104 I2C can be set using an initialization procedure involving PGM_IN and PGM_OUT in conjunction with the standard 12C signals This procedure facilitates the assignment of a large num ber of slave addresses enabling several MAX24104s to be controlled by a single 12C serial bus and commands All transactions on the 12C bus follow standard protocol allowing simple firmware development 15Gbps Quad Linear Equalizer There is little difference between a normal 12C serial bus and the MAX24104 solution except that there is a new signal which controls the programming of the device addresses This signal is daisy chained through all of the devices on the 12C bus via the PGM_IN and the PGM_ OUT pins The programming of device addresses is done as a single parallel write to all devices 1 to N The 12C bus is the usual SCL and bidirectional SDA with the pullup The program_reset signal is a single bit passed through each device as a flying enable The input pin for this signal is PGM_IN and the corresponding output pin is
22. e 2 at 12h and device 3 at 14h HOST MCU E MAX24104 1 2 MAX24104 MAX24104 MAX24104 N 1 N PGM_IN PGM_OUT PGM_IN PGM_OUT PGM_IN PGM_OUT PGM_IN PGM_OUT Figure 11 Slave Address Configuration www maximintegrated com Maxim Integrated 20 MAX24104 Startup Sequence In this example a chain of MAX24104s are loaded with the required 12C slave address 1 Power up the devices 2 Write 12C sequence lt A2h ack 3Ch ack address and 0 ack gt 3 The first device is now accessible at its given address 4 By accessing the first device the SCL pin is tog gled and hence the program_reset signal is propa gated through the devices using the PGM_IN and PGM_OUT pins For long chains a number of access es may be needed before all devices have an assigned address since each access results in 27 SCL transi tions and hence 13 devices are allocated an address To reset the slave address requires a power cycle or setting the ENABLE pin low www maximintegrated com 15Gbps Quad Linear Equalizer Programming Tables Table 6 EQ_PEAKING Bit Control EQ PEAKING GAIN EQx 3 0 AT AT AT AT UNITS 4GHz 5 15GHz 6GHz 7 5GHz 1111 11 3 14 0 15 9 19 0 1110 10 8 13 5 15 4 18 5 1101 10 4 13 0 14 9 18 0 1100 9 9 12 5 14 3 17 5 101
23. ignals Power supply decoupling should also be placed as close to the Vcc pins as possible There should be sufficient supply filtering Always connect all Vccs to a power plane Take care to isolate the input from the output signals to reduce feed through MAX24104 Figure 13 CML Equivalent Output Structure Maxim Integrated 24 MAX24104 Ordering Information PART TEMP RANGE PIN PACKAGE MAX24104ELT 40 C to 85 C 34 FCLGA EP MAX24104ELT T 40 C to 85 C 34 FCLGA EP Denotes a lead Pb free ROoHS compliant package EP Exposed pad T Tape and reel Chip Information PROCESS SiGe BiCMOS www maximintegrated com 15Gbps Quad Linear Equalizer Package Information For the latest package outline information and land patterns footprints go to www maximintegrated com packages Note that a or in the package code indicates RoHS status only Package drawings may show a different suffix character but the drawing pertains to the package regardless of RoHS status PACKAGE PACKAGE OUTLINE LAND TYPE CODE NO PATTERN NO 34 FCLGA EP L344A6F 1 21 0888 90 0466 Maxim Integrated 25 MAX24 104 15Gbps Quad Linear Equalizer Revision History REVISION REVISION PAGES NUMBER DATE DESCRIPTION CHANGED 0 10 14 Initial release 1 4 15 Revised Ordering Information 25 For pricing delive
24. n can be controlled using commands sent over the 12C serial bus or pin control With pin control the equalization setting has three available compensation levels and all the channels are controlled globally See Table 2 for details With the 12C serial bus the equaliza tion has 16 settings and each channel can be adjusted independently Gain Stage The MAX24104 data path goes through a wideband flat gain stage With pin control the flat gain can be adjusted globally from 2 9dB to 1 7dB as shown in Table 3 With 15Gbps Quad Linear Equalizer I2C control the flat gain can be adjusted independently for each channel Output Stage The MAX24104 data path transitions from the gain stages into a linear output buffer with selectable output levels With pin control the output levels can be adjusted globally as shown in Table 4 With 12C control the output levels can be adjusted independently for each channel Power Saving The MAX24104 features a power down enable input ENABLE pin to shut down the device and reduce sup ply current at startup Set high to power down the output stage of all channels Set open to power up all channels Set low for reset Reset disables all communication to the chip along with resetting the registers to their default states Table 2 EQ PEAKING Pin Control refer to Table 6 CONTROL PIN LONG CHANNEL SHORT CHANNEL iiie INPUT LE
25. ource Tx Level dBV Linear EQ Peaking Gain dB Linear EQ Flat Gain dB Linear EQ Output Level setting 1dB Compression level dBV User System Margin dB For example Source Tx Level 0dBV Linear EQ Peaking Gain 14dB Linear EQ Flat Gain 0dB Linear EQ Output Level setting 1dB Compression Point 3dBV User System Margin 2dB Then Minimum Distance Nyquist Loss from Source Tx 0 14 0 3 2 19dB Step 3 Keep Nyquist Level Sufficiently Above Noise Floor The amplitude of the Nyquist sequence 10101010 must be maintained sufficiently above noise floor to achieve BER goals Hence Nyquist level at input to the Linear EQ needs to be sufficiently above the Linear EQ self noise IRN input referred noise This sets the maximum Nyquist channel loss preceding the Linear EQ e g farthest placement from Source Tx see Position 2 in Figure 5 Maximum Distance Nyquist Loss from Source Tx dB Source Tx Level which is Nyquist level dBV Linear EQ IRNpp at BER goal dBV Margin required to reduce RJ creation User System Margin dB For example Source Tx Level OdBV Linear EQ IRNpp at BER goal 0 5mVrms x 15 9 at BER 1E 15 dBV 43dB Margin required to reduce RJ creation to 0 2Ulpp at BER 10dB User System Margin 3dB Then Maximum Distance Nyquist Loss from Source Tx 0 43 10 3 30dB Maxim Integrated 15 MAX24104 Tools Frequency Response Plotting
26. r Equalizer Definitions dBV is defined as dB relative to 1Vp_p differential Hence the Tx level of 1Vp p is OdBV and a Tx level of 0 5Vp _p is 6dBV Source Tx Level dBV is the total measured Tx Vp p including pre emphasis Desired Margin is a user decision regarding margin needed to account for all system min max variations including source Tx MAX24104 and ASIC receiver POSITION 2 oO NEAR EQ OUTPUT REFERRED 1dB COMPRESSION LEVEL VP P ee EES Litt titi DESIGN MARGIN TOTAL GAIN AT NYQU DFE IRN AT BER 24B E15 8 12 CHANNEL LOSS dB PLACEMENT RANGE IN LOSSY CHANNEL Figure 5 Linear Equalizer Placement www maximintegrated com SLICER Maxim Integrated 14 MAX24104 Step 1 Maintain EQ Linearity at Low Frequency LF The source Tx low frequency LF amplitude needs to be considered to keep linear EQ within its linear range The source Tx low frequency LF amplitude is the differential peak peak amplitude after any pre emphasis has fully set tled e g the level of long CID continuous identical digits sequences The primary controls over LF levels in Linear EQ are the Used ASIC Source Tx pre emphasis or de emphasis and the Linear EQ Flat Gain MAX24104 Figure 5 shows a typical example with ASIC Source Tx having 6dB pre emphasis with 1Vp p peak swing and 0 5Vp p
27. ression 7 5GHz Nyquist toc03 0 25 a 0 35 5 of 0 30 3dB Loss Linear TXAx 1 0 11 0 20 Range Operation S 0 a z 0 25 S m ui Brg TXAx 1 0 00 E 046 16 7dB Loss Li E S 4 v oss neat 5 0 20 16 7dB Loss Linear Ee e 3dB Loss Linear Range Operation 2 Range Operation a 2 Range Operation 2 0 15 0 10 5 10 d oa a l E 0410 5 7 a 2 0 05 15 0 05 Data Rate 10 3Gbps TXAx 1 0 10 FGx 1 0 10 Data Rate 15Gbps TXAx 1 0 10 FGx 2 0 10 EQx 3 0 0111 FGx 1 0 10 0 00 20 0000 0010 0100 0110 1000 1010 1100 1110 0000 0010 0100 0110 1000 1010 1100 1110 30 25 20 15 10 5 EQUALIZATION SETTING EQxx 3 0 EQUALIZATION SETTING EQxx 3 0 INPUT AMPLITUDE dBV 1dB COMPRESSION 100MHz Nyquist FREQUENCY RESPONSE 10 0 fords 30 toc05 5 0 TXAx 1 0 11 wv le N z FGx 1 0 10 amp 0 0 FGx 1 0 01 Q TXAx 1 0 00 50 ao al Ss z 10 0 3 x 1 0 00 P 5 3 15 0 20 0 EQx 3 0 0111 FGx 1 0 10 3 0 0000 25 0 25 20 45 10 5 0 5 10 0 2 4 6 8 10 INPUT AMPLITUDE dBV FREQUENCY GHz FREQUENCY RESPONSE FREQUENCY RESPONSE WITH 18in of FR4 25 toc06 5 toc07 EQxx 3 0 1111 FR4 with EQx 3 0 20 EQxx 3 0 0111 15 F EQxx 3 0 0100 ao a 2 2 z 10 z 5 5 5 Ay EQxx 3 0 0010 0 EQxx 3 0 0000 TXAx 1 0 11 FGxx 1 0 1
28. ry and ordering information please contact Maxim Direct at 1 888 629 4642 or visit Maxim Integrated s website at www maximintegrated com Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product No circuit patent licenses are implied Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time The parametric values min and max limits shown in the Electrical Characteristics table are guaranteed Other parametric values quoted in this data sheet are provided for guidance Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products Inc 2015 Maxim Integrated Products Inc 26
29. st 010101 level above above EQ IRN input referred noise to meet BER and constrain RJ gen 28 08 B Nearest to Rx dB gt 6 02 26 08 OverPVT gt 8 02 n output N Keeps EQ ORN output ref noise below DFE IRN input ref noise including channel loss on noise 3 gt C Longest Channel dB lt 45 02 dB 77 Over PVT lt 43 02 T F P N M Keeps Nyquist 010101 level sufficiently above DFE IRN input referred noise to meet BER and constrain RJ generation dB dB ASIC RX N Input Referred Noise dABVpp BER MEASUREMENT DEFINITIONS HF 0101010101 Sq Wave Nyquist LF Long CID Sq Wave 100MHz Peaking Gain Gain HF relative to LF Noise BW 10MHz to Nyquist Entry Box in Yellow ASIC RX SETTINGS N Input Ref Noise dBVrms Vpp 7 9 dBVpp 42 0 M Margin dB Nyquist 010101 Vpp above N Vpp BER recommend gt 16dB for RJ lt 0 10Ulpp recommend gt 12dB for RJ lt 0 16Ulpp BER Target 1E xx where xx Vpp Vrms Multiplier 15 85 for BER in 1E 12 to 1E 17 range If using Typical specs add Margin for PVT Variation 2a Maxim Integrated 17 MAX24104 Write Transaction In a write transaction the address byte is successfully acknowledged by the slave and the type bit is set low After the first acknowledge the master sends a single data byte All signaling is controlled by the master except for the SDA line during the acknowledge bits
30. t Capacitance CiN 10 pF Input Leakage Current lin 1 uA ISINK 3mA 0 4 Output Low Voltage SDA VoL V ISINK 6mA 0 6 SCLK Clock Frequency fscik 400 kHz Note 2 The MAX24104 is 100 production tested at Ta 25 C and T 85 C Specification at Ta 40 C is guaranteed by design or characterization unless otherwise noted Note 3 Guaranteed by design and characterization Note 4 Measured with circuit board loss optimized for best DJ Residual jitter is the difference in deterministic jitter between the reference data source and device output DJRESIDUAL DJOUTPUT DJSOURCE The deterministic jitter at the output of the transmission line must be from media induced loss Measured at point D in Figure 2 Test Pattern 66 Zeroes 1010 PRBS7 66 ones 0101 Inverted PRBS7 Note 5 The output voltage range in which a linear relationship between the input and output maintains less than or equal to 1dB compression Note 6 Measured using a vector network analyzer VNA N5245A with 15dBm power level applied to the adjacent input The VNA detects the signal at the output of the victim channel All other inputs and outputs are terminated with 50Q Note 7 Refer to UM10204 2C bus specification and user manual Rev 03 19 June 2007 www maximintegrated com Maxim Integrated 5 MAX24104 15Gbps Quad Linear Equalizer Figure 1 Recommended Supply Filtering SIGNAL SOURCE XL RECEIVE TEST SETUP PCB
31. ure ccccesseeeesseeees 125 C ANG SCL cacrdaccasetesscsegenedevaycesennedeesiaiaee 0 5V to Vcc 0 3V Storage Temperature Range cceeeeeeees 40 C to 150 C DC Input Voltage Applied SDA SCL 0 5V to 4 0V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Package Thermal Characteristics Note 1 FCLGA Junction to Case Thermal Resistance 0 Jc 06 10 C W Junction to Ambient Thermal Resistance Oya EIA JESD51 2 standard ceeeeeeeeeees 29 C W Note 1 Package thermal resistances were obtained using the method described in JEDEC specification JESD51 7 using a four layer board For detailed information on package thermal considerations refer to www maximintegrated com thermal tutorial Operating Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Vccr Supply Voltage VectT 2 312 2 5 2 75 V Vccp Operating Ambient Ta 40 25 85 C Temperature Data Rate 1 15 Gbps Source Data Coding and DC balanced NRZ 8B10B or 66 CID CID Scrambled PRBS31 Differential Source Diff Low LF Baseline without P
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