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SAB 80C515A,83C515A-5 - Users Manual

1. The reset value of XPAGE is 00x XPAGE can be set and read by software Figures 3 2 to 3 4 show the dependencies of XPAGE and Port 2 addressing in order to explain the differences in accessing XRAM ext RAM or what is to do when Port 2 is used as an I O port Semiconductor Group 3 9 SIEMENS Memory Organization XRAM Write to Port 2 Page Address 02112 pg Port 0 Address Data iis Figure 3 2 Write Page Address to 2 MOV P2 pageaddress will write the page address to Port 2 and XPAGE Register When external RAM is to be accessed in the XRAM address range F800 FFFFy XRAM has to be disabled When additional external RAM is to be addressed in an address range lt XRAM 800 XRAM may remain being enabled and there is no need to overwrite XPAGE by a second move Semiconductor Group 3 10 SIEMENS Memory Organization Port 0 Write to XPAGE Port 2 K gt Address Data XRAM Address 0 Data 2113 Figure 3 3 Write Page Address to XPAGE The page address is only written to XPAGE register Port 2 is available for addresses or I O Data See figure 3 4 to see what happens when Port 2 is used as I O Port Semiconductor Group SIEMENS Memory Org
2. 3 1 3 1 Program Memory ROM Protection 3 2 3 2 E A 3 3 3 3 Special Function Registers 3 3 3 4 Architecture of the XRAM 3 8 3941 Accesses XRAM iis doa 3 8 3 4 2 Control of XRAM in the SAB 80 515 3 14 3 4 3 Behaviour of PortO and 2 3 15 4 a ita A a Sot weet 4 1 4 1 Additional Hardware Power Down Mode in the SAB 80C515A 4 1 4 2 Hardware Power Down Reset Timing 4 4 4 3 Fast Internal Reset after Power On 4 8 5 On Chip Peripheral Components 5 1 5 1 10 Bit A D Converter 5 3 5 2 New Baud Rate Generator for Serial 5 8 5 3 Fall 5 11 5 3 1 Programmable Watchdog Timer 5 12 5 3 2 Oscillaior Watchdog Unit 5 us 5 17 6 Devices 5 6 1 Semiconductor Group 1 1 SIEMENS Introduction 1 Introduction SAB 80C515A is a superset of the high end microcontroller SAB 806515 While maintaining all a
3. Parameter Symbol Limit values Unit 18 MHz clock Variable clock 1 3 5 MHz 18 MHz min max min max External Data Memory Characteristics RD pulse width 233 100 ns WR pulse width 233 100 ns Address hold after 81 2 30 ns ALE RD to valid data in fRLDV 128 150 DATA hold after RD tRHDX 0 0 5 ns Data float after RD tRHDZ 51 60 ns ALE to valid data 294 8 150 5 Address to valid tAVDV 335 91510 165 ins data in ALE to WR or RD fLLWL 217 50 50 ns WR or RD high to WHLH 96 40 40 ns ALE high Address valid to WR tAVWL 41 130 ns Data valid to WR tQvwx 45 ns transition Data setup before WR tqvwH 150 ns Data hold after WR WHQX 40 ns Address float after RD az 0 0 ns Semiconductor Group 6 48 SIEMENS SAB 80C515A 83C515A 5 5 Port 0 2 MCTO1497 Program Memory Read Cycle ALE PSEN uw y TRLRH RD hw lax See AO A7 M 0 7 Ri Data In 7777 N trom 5 tayoy Port 2 2 0 2 7 or 8 15 from DPH 8 15 from PCH 00791 Data Memory Read Cycl
4. ene uw dua eoe YM GH lt lt lt INVHX juo ejeq uA O I lt 2d 0d quo lt sng lt 0d e sng od e O I ed e sng lt 0d e sng od e sng od e dovdx pesn 1 pesn 1 pesn 5 pesn 1 pesn 5 pesn 5 2 2 2 araoe INVHX lt lt lt lt lt lt gt IH sng lt 0d e sng od e sng od e sng lt 0d e sng od e sng lt 0d e dOVdX XAOW pesn si pesn si WWHX 9 1 pesn si WWHX 9 9 pesn s 2 9 pesn si Avux o ssouppe eno INVHX eje q HAM ejeq HAW Auo ejeq HA 5 9 lt 9 0 sngc zd od e 24 04 sng zd od e lt sng ed od e pesn 1 pesn 1 pesn 5 pesn 1 pesn 1 pesn 5 SSoJppe
5. ROM Verification Mode 2 Semiconductor Group 6 54 SIEMENS SAB 80C515A 83C515A 5 Compare Result Logic SAB 83C515A 5 ALE Reset Adr Counter IH Reset Compare ROM 01570 Application Example for Verifying the Internal ROM with ROM Verify Mode 2 Semiconductor Group 6 55 SIEMENS SAB 80C515A 83C515A 5 0 2 50 9 Test Points 0 2 Vog 0 1V 0 45V 00697 AC Inputs during testing are driven at 0 5 V for a logic 1 and 0 45 V for a logic 0 Timing measure ments are made at ViHmin for a logic 1 and for a logic 0 AC Testing Input Output Waveforms Timing Reference Points Vo 0 1V 00606 For timing purposes port pin is no longer floating when 100 mV change from load voltage occurs and begins to float when 100 mV change from the loaded V level occurs gt 20 mA AC Testing Float Waveforms XTAL1 XTAL1 MQFP 80 Pin 37 MQFP 80 Pin 37 P LCC 68 Pin 40 P LCC 68 Pin 40 XTAL2 XTAL2 MQFP 80 Pin 36 External Oscillator MQFP 80 Pin 36 P LCC 68 Pin 39 Signal P LCC 68 Pin 39 10 incl stray capacitance Crystal Oscillator Mode Driving from External Source Recommended Oscillator Circuits Semiconductor Group 6 56
6. the lower 128 bytes of RAM including four register banks containing eight registers each the upper 128 byte of RAM the 128 byte special function register area 1 8 area which is accessed like external RAM MOVX instructions implemented on chip at the address range from F800 to FBFFy Special Function Register SYSCON controls whether data is read from or written to XRAM or external RAM A map of the internal data memory is shown figure 2 The overlapping address spaces of the standard internal data memory 256 byte are accessed by different addressing modes see User s Manual SAB 80C515 The stack can be located anywhere in the internal data memory Architecture of the XRAM The contents of the XRAM is not affected by a reset or HW Power Down After power up the contents is undefined while it remains unchanged during and after a reset or HW Power Down if the power supply is not turned off The additional On Chip RAM is logically located in the external data memory range at the upper end of the 64 Kbyte address range 800 Nevertheless when is enabled the address range F800 to FFFF is occupied This is done to assure software compatibility to 80C517A It is possible to enable and disable only by reset the XRAM If itis disabled the device shows the same behaviour as the parts without XRAM i e all MOVX accesses use the external bus to physically external data memory Sem
7. the lower 128 bytes of RAM including four register banks containing eight registers each the upper 128 byte of RAM the 128 byte special function register area a1Kx8 area which is accessed like external RAM MOVX instructions implemented on chip at the address range from F800 to Special Function Register SYSCON controls whether data is read from or written to XRAM or external RAM 3 3 Special Function Registers All registers except the program counter and the four general purpose register banks reside in the special function register area The special function registers include arithmetic registers pointers and registers that provide an interface between the CPU and the on chip peripherals There are also 128 directly addressable bits within the SFR area All special function registers are listed in table 3 1 and table 3 2 In table 3 1 they are organized in numeric order of their addresses In table 3 2 they are organized in groups which refer to the functional blocks of the 80C515A Semiconductor Group 3 3 SIEMENS Memory Organization Table 3 1 Special Function Register Address Register Contents Address Register Contents after Reset after Reset 80H Po Ady P2 81 SP 07 Aly reserved XXH 2 82 DPL 00H A2y reserved XXH 2 83H DPH 00H A3H reserved XXH 2 84H WDTL A4y reserved XXH 2 85 WDTH A5y reserved XXH 2 86H WDTREL 00H A6H reserved XXH 2 87H
8. 80 515 80 535 MCB02302 Figure 2 1 Block Diagram of the SAB 80C515A 83C515A 5 Semiconductor Group 2 2 SIEMENS Memory Organization 3 Memory Organization According to the SAB 8051 architecture the SAB 80C515A has separate address spaces for program and data memory Figure 3 1 illustrates the mapping of address spaces FFFF y FFFFy indirectly addressable unused FCOOW ext XMAPO 1 ext FBFEH int XMAPO 0 indirect direct iu F800 edd 8000 7 SFR 4 80H ext EA 0 7FH int RAM 119 Wu S Code Space external Data Space internal Data Space 002280 Figure 3 1 Semiconductor Group 3 1 SIEMENS Memory Organization 3 1 Program Memory ROM Protection The SAB 83C515A 5 has 32 Kbyte of on chip ROM while the SAB 80C515A has no internal ROM The program memory can externally be expanded up to 64 Kbyte Pin EA determines whether program fetches below address 8000H are done from internal or external memory As a new feature the SAB 83C5154A 5 offers the possibility of protecting the internal ROM against unauthorized access This protection is implemented in the ROM Mask Therefore the decision ROM Protection yes or has to be made when delivering the ROM Code Once enabled there is no way of disabling the ROM Protection Effect The access to internal ROM done by an externally fetched MOVC instruction
9. 650 uA 2 current ports 1 2 3 4 5 Input leakage current 100 0 45 lt Vin lt Voo port 0 EA 6 HWPD 150 0 45 lt ViN TA 100 C Input low current to RESET 12 10 100 Vin 0 45 V for reset Input low current XTAL2 113 15 Vin 0 45 V Input low current PE SWD 20 Vin 0 45 V Pin capacitance Cio 10 pF 1 MHz 25 Power supply current Active mode 12 MHz loc 26 mA 5 9 Active mode 18 MHz 35 mA 5 Idle mode 12 MHz 11 8 mA 5 gt Idle mode 18 MHz lec 14 2 mA 25V Slow down mode 12 MHz 9 mA 5 9 Slow down mode 18 MHz 10 mA 5 9 Power Down Mode Ipp 50 2 5 5 V9 Notes see page 43 Semiconductor Group 6 44 SIEMENS SAB 80C515A 83C515A 5 Notes for page 44 1 gt m 2 Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vo of ALE and ports 1 3 4 and 5 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation In the worst case capacitive loading gt 100 pF the noise pulse on ALE line may exceed 0 8 V In such cases it may be desirable to qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input Capacitive loading
10. DCy ADCONO 08 2 MX 1 MX 0 2 1 0 ADDATH ADDATL Single 09 DAH Continous Mode A D Converter P4 0 ADST Write to ADDATL internal Bus Shaded areas are not used ADC functions ZA Bit MX3 in SFR ADCON1 must not be set 01565 Figure 3 Block Diagram A D Converter Semiconductor Group 6 26 SIEMENS SAB 80C515A 83C515A 5 Timers Counters SAB 80C515A contains three 16 bit timers counters wich are useful in many applications for timing and counting the input clock for wach timer counter is 1 12 of the oscillator frequency in the timer operation or can be taken from an external clock source for the counter operation maximum count rate is 1 24 of the oscillator frequency Timer Counter 0 and 1 These timers counters can operate in four modes Mode 0 8 bit timer counter with 32 1 prescaler Mode 1 16 bit timer counter Mode 2 8 timer counter with 8 bit auto reload Mode 3 Timer counter 0 is configured as one 8 bit timer counter and one 8 bit timer Timer counter 1 in this mode holds its count External inputs INTO and INT1 can be programmed to function as a gate for timer counters 0 and 1 to facilitate pulse width measurements Timer Counter 2 Timer counter 2 of the 80C515A is a 16 bit timer counter with several additional features It offers a 2 1 prescaler a selectable gate function and c
11. Watchdog Port 0 Bi 22 gt m EA gt Timer 0 d UR Port 1 MM Port 1 8 Bit EN Ea Timer 2 e SEn Compare Capture Unit Port 4 ER Port 4 K gt 8 Bit Serial Port Port 5 Baud Rate ws 8 Bit Generator 24 Interrupt ANO AN7 8 Bit 45 AN MU S amp H XTAL1 XTAL2 Port 3 8 Bit gt lt m RS VAREF VAGND 7 Z2 Enhancements to the Ext Start 2 80C515 80C535 MCB01563 Figure 1 Block Diagram Semiconductor Group 6 11 SIEMENS SAB 80C515A 83C515A 5 Functional Description The SAB 80C515A is based on 8051 architecture It is a fully compatible member of the Siemens SAB 8051 80C51 microcontroller family being an significantly enhanced SAB 80 515 The SAB 80C515A is therefore code compatible with the SAB 80C515 Having an 8 bit CPU with extensive facilities for bit handling and binary BCD arithmetics the SAB 80C515A is optimized for control applications With a 18 MHz crystal 58 of the instructions are executed in 666 67 ns While maintaining all architectural and operational characteristics of the SAB 806515 the SAB 80C515A incorporates more on chip RAM A new 10 bit A D Converter is implemented as well as an oscillator watchdog unit Also the maximum operating frequen
12. 00 reserved _ XX42 7 00 7 reserved 8 T2CON 00 P4 1 OFF C9 reserved reserved XX4 9 00 reserved XX CRCH 00 reserved XX4 TL2 00 reserved 9 CDy TH2 004 EDy reserved XX4 reserved XXy 9 EE reserved XX CFy reserved XXy EFy reserved 1 Bit addressable special function registers 2 X means that the value is indeterminate and the location is reserved Semiconductor Group SIEMENS SAB 80C515A 83C515A 5 Table 2 Special Function Register cont d Address Register Contents Address Register Contents after Reset after Reset FO B F84 P51 OOF reserved F94 reserved XX4 9 F24 reserved 9 reserved 9 reserved XX4 FB4 F44 reserved XXH FCy F5 reserved 9 reserved FE F7 reserved FFy 1 Bit addressable special function registers 2 X means that the value is indeterminate and the location is reserved Semiconductor Group 6 22 SIEMENS SAB 80C515A 83C515A 5 Table 3 Special Function Registers Functional Blocks Block Symbol Address _ after Reset CPU ACC Accumulator OE0 1 004 B B Register 00 Data Pointer High Byte 83 00 DPL Data Pointer Low Byte 824 004 PSW Program Status Word Register ODO 00 SP
13. to select these modes by software the voltages applied at port 6 pins can be converted to digital values using the A D converter and at the same time the pins can be read via SFR P6 It must be noted however that the results in port P6 bits will be indeterminate if the levels at the corresponding pins are not within their Vj specifications Furthermore it is not possible to use port P6 as an output port Special function register is located at address In Hardware Power Down Mode the port pins and several control lines enter a floating state For more details see the section about Hardware Power Down Mode Semiconductor Group 6 33 SIEMENS SAB 80C515A 83C515A 5 Power Saving Modes The SAB 80C515A provides due to Siemens ACMOS technology four modes in which power consumption can be significantly reduced The Slow Down Mode The controller keeps up the full operating functionality but is driven with one eight of its normal operating frequency Slowing down the frequency remarkable reduces power consumption The Idle Mode The CPU is gated off from the oscillator but all peripherals are still supplied with the clock and continue working The Software Power Down Mode Operation of the SAB 80C515A is stopped the on chip oscillator and the RC oscillator are turned off This mode is used to save the contents of the internal RAM with a very low standby current and is fully compatible to the Power Down
14. 10 15 Ta 01070 for the SAB 80C515A 83C515A 5 40 to 85 for the SAB 80C515A T3 83C515A 5 T3 C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Parameter Symbol Limit values Unit 18 MHz clock Variable clock 1 3 5 MHz 18 MHz min max min max Program Memory Characteristics ALE pulse width 71 2 40 ns Address setup to ALE tAVLL 26 30 5 Address hold after ax 26 30 ns ALE to valid 122 100 ns instruction ALE to PSEN 31 cicL 25 ns PSEN pulse width 132 3 35 ns PSEN to valid 92 3 75 ns instruction in Input instruction hold 0 0 2 ns after PSEN Input instruction float tpxiz 46 10 ns after PSEN Address valid after 48 8 ns PSEN Address to valid taviv 218 60 5 instruction in Address float to PSEN tAzpL 0 0 ns Interfacing the 80C515A to devices with float times up to 45 ns is permissible This limited bus contention will not cause any damage to port 0 drivers Semiconductor Group 6 47 SIEMENS SAB 80C515A 83C515A 5 AC Characteristics cont d
15. 2 is used as general purpose I O or as page address is made by the external system design From the device s point of view it cannot be decided whether the Port 2 data is used externally as address or as data Hence a special page register is implemented into the 80C515A to provide the possibility of accessing the XRAM also with the MOVX Ri instructions i e XPAGE serves the same function for the XRAM as Port 2 for external data memory Semiconductor Group 6 15 SIEMENS SAB 80C515A 83C515A 5 Special Function Register XPAGE Addr 914 XPAGE The reset value of XPAGE is 00 XPAGE can be set and read by software The register XPAGE provides the upper address byte for accesses to XRAM with MOVX Ri instructions If the address formed from XPAGE Ri is less than the XRAM address range then an external access is performed For the SAB 80C515A the contents of XPAGE must be greater or equal than 8 in order to use the XRAM Of course the XRAM must be enabled if it shall be used with MOVX Ri instructions Thus the register XPAGE is used for addressing of the XRAM additionally its contents are used for generating the internal XRAM select If the contents of XPAGE is less than the XRAM address range then an external bus access is performed where the upper address byte is provided by P2 and not by XPAGE Therefore the software has to distinguish two cases if the MOVX Ri instructions
16. 5 2 67 9 33 16 0 75 5 33 18 66 16 8 2 0 2 0 7 0 16 1 0 4 0 14 0 18 8 16 1 125 3 555 12 4 Semiconductor Group 5 3 SIEMENS On Chip Peripheral Components internal Bus P6 08 0 ADCONO D84 2 MX 1 MX 0 2 1 0 ADDATH ADDATL D94 DAH L Single Continous Mode Port 6 A D Converter fosc Speo x VaREF VAGND P4 0 ADST Write to ADDATL internal Bus 777 Shaded areas are not used in ADC functions n 2 Bit MX3 must not be set MCB02279 Figure 5 2 10 Bit A D Converter Semiconductor Group 5 4 SIEMENS On Chip Peripheral Components Special Function Registers ADCONO ADCON1 MSB LSB Bit No 7 6 5 4 3 2 1 0 BD ADEX BsY ADM MX ADCONO MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr ADCL MX3 MX2 MX1 0 ADCON 1 These bits not used in controling A D converter functions in the 80C515A Bit Function ADEX Internal external start of conversion When set the external start of conversion by P4 0 ADST is enabled BSY Busy flag This flag indicates whether a conversion is in progress BSY 1 The flag is cleared by hardware when the conversion is finished ADM A D Conversion mode When set a continuous co
17. A D ADCONO A D Converter Control Register 0 8 00H Converter ADCON1 A D Converter Control Register 1 00006 ADDATH A D Converter Data Register High Byte 00H ADDATL A D Converter Data Register Low Byte 00H Interrupt IENO Interrupt Enable Register 0 A8y 00H System IEN1 Interrupt Enable Register 1 00H IPO Interrupt Priority Register 0 0 9 00H Interrupt Priority Register 1 OB9y4 XX00 0000p IRCON Interrupt Request Control Register 00H TCON Timer Control Register 88 00H T2CON 2 Timer 2 Control Register 00H Compare CCEN Comp Capture Enable Reg 00H Capture CCH1 Comp Capture Reg 1 High Byte 00H Unit CCU CCH2 Comp Capture Reg 2 High Byte 0C5H 00H CCH3 Comp Capture Reg 3 High Byte 0C7H 00H CCL1 Comp Capture Reg 1 Low Byte 0C2y 00H 12 Comp Capture Reg 2 Low Byte 0 4 00H CCL3 Comp Capture Reg 3 Low Byte 00H CRCH Com Rel Capt Reg High Byte OCBy 00H CRCL Com Rel Capt Reg Low Byte 00H TH2 Timer 2 High Byte 0CDH 00H TL2 Timer 2 Low Byte 0CCH 00H T2CON 2 Control Register 8 00H XRAM XPAGE Addr Reg for extended onchip 91H 00H SYSCON XRAM Control Reg OB1y XXXX XX01 p 3 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X m
18. Mode of the SAB 80C515 The Hardware Power Down Mode Operation of the SAB 80C515A is stopped the on chip oscillator and the RC oscillator are turned off The pin HWPD controls this mode Port pins and several control lines enter a floating state The Hardware Power Down Mode is new in the SAB 80C515A and is independent of the state of pin PE SWD which enables only the software initiated power reduction modes Hardware Enable for Software controlled Power Saving Modes A dedicated pin PE SWD of the SAB 80C515A allows to block the Software controlled power saving modes Since this pin is mostly used in noise critical application it is combined with an automatic start of the Watchdog Timer PE SWD V logic high level Using of the power saving modes is not possible The watchdog timer starts immediately after reset The instruction sequences used for entering of power saving modes will not affect the normal operation of the device E SWD V logic low level All power saving moes can be activated by software The watchdog timer can be started by software at any time When left unconnected pin PE SWD is pulled high by a weak internall pull up This is done to provide system protection on default The logic level applied to pin PE SWD can be changed during program execution to allow or to block the use of the power saving modes without any effect on the on chip watchdog circuitry Semiconductor Group 6 34 SIEMENS SAB 80C515
19. PCON 00H reserved XXH 2 88 TCON 00H IENO 00H 89H TMOD 00H IPO 00H TLO 00H AAH SRELL 9 8By TL1 00H ABH reserved XXH 2 8CH THO 00H ACH reserved XXH 2 TH1 00 reserved XXH 2 reserved XXH 2 reserved XXH 2 8Fy reserved XXH 2 AFH reserved XXH 2 90H P1 P3 91H XPAGE 00H BiH SYSCON XXXXXX01 p 92H reserved XXy B24 reserved XXH 9 93H reserved XXH 2 reserved XXH 2 944 reserved XXH 3 B44 reserved XXH 2 95H reserved XXH 3 B5H reserved XXH 2 96H reserved XXH 2 reserved XXH 2 97H reserved XXH 2 B7y reserved XXH 2 98H SCON 00H B8y IEN1 00H 99H SBUF XXH 2 9 XX000000p reserved XXH 2 SRELH XXXXXX 1 1p 9By reserved XXH 2 BBH reserved XXH 2 9CH reserved XXH 3 BCH reserved XXH 2 9DH reserved XXH 2 BDH reserved XXH 2 reserved XXH 2 reserved XXH 9 reserved XXH 2 BFH reserved XXH 2 1 Bit addressable Special Function Register 2 X means that the value is indeterminate and the location is reserved Semiconductor Group SIEMENS Memory Organization Table 3 1 Special Function Register cont d Address Register Contents Address Register Contents after Reset after Reset IRCON 00H ACC 00H 1 00H Ely reserved XXH 2 CCL1 00H E24 reserved XXH 2 CCH1 00H reserved XXH 12 00H 4
20. SIEMENS SAB 80C515A 83C515A 5 a Q Bok RE LO x 10 co Mox ox x d oui 4 Choo bobo ddidddndd zzizddddc m 80 75 70 65 61 RESET f o 60 1 P5 7 N C P0 7 AD7 VAREF P0 6 AD6 VAGND P0 5 AD5 P6 7 AIN7 5 P0 4 AD4 P6 6 AING 55 1 P0 3 AD3 P6 5 5 P0 2 AD2 P6 4 AINA 1 AD1 P6 3 AIN3 P0 0 ADO P6 2 AIN2 110 80 515 80 515 5 N C P6 1 50 N C P6 0 AINO EA N C ALE N C PSEN P3 0 RXDO 115 N C P3 1 TXDO 45 P2 7 A15 P3 2 INTO 2 6 A14 P3 3 2 5 1 4 2 4 12 P3 5 T1 20 417 P2 3 11 21 25 30 35 40 3358888845332 SESE QHESSSBSose ratte S on XX qw amp 5 izzzz a Rue N C pins must be connected Pin Configuration P MQFP 80 Semiconductor Group 6 5 SIEMENS SAB 80C515A 83C515A 5 Pin Definitions and Functions Symbol Pin Input 1 Function P LCC 68 P MQFP 80 Output 4 0 4 7 1 3 5 9 72 74 Port 4 76 80 is an 8 bit bidirectional port with internal pull up resistors Port 4 pins that have 1 s writ ten to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs port 4 pins being externally pulled low will source current in the DC characteristics because of the intern
21. Stack Pointer 814 074 A D ADCONO A D Converter Control Register O 0084 00 Converter ADCON1 Converter Control Register1 ODC OXXX 0000g 9 ADDATH Converter Data Reg High Byte 009 004 ADDATL A D Converter Data Reg Low Byte 0 00 Interrupt ENO Interrupt Enable Register 0 1 00 System IEN1 Interrupt Enable Register 1 0B8 1 00 IPO Interrupt Priority Register 0 OAS 00 IP1 Interrupt Priority Register 1 0B9 00 0000p IRCONO Interrupt Request Control Register OCO 7 00 TCON 2 Timer Control Register 88 1 00 2 2 2 Control Register 0C8y 004 Compare CCEN Comp Capture Enable Reg 0C1u 00 Capture CCH1 Comp Capture Reg 1 High Byte 0C3 004 Unit CCH2 Comp Capture Reg 2 High Byte 0 5 00 CCU CCH3 Comp Capture Reg High Byte 0 7 00 CCL1 Comp Capture Reg 1 Low Byte 0 2 004 CCL2 Comp Capture Reg 2 Low Byte 0C4 00 Comp Capture Reg Low Byte 0 6 00 CRCH Com Rel Capt Reg High Byte OCBy 00 CRCL Com Rel Capt Reg Low Byte OCA 00 2 Timer 2 High Byte TL2 Timer 2 Low Byte 004 T2CON Timer 2 Control Register 0C8 00 XRAM XPAGE Page Address Register for 91 00 ded Chip RAM SYSCON Control Register 0 1 XXXX XX01g 9 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belon
22. T2CON 5 0 P1 0 INT3 CCO we T2CON 6 9 Compare 1 P1 1 INT4 CC1 Y 2 P1 2 INT5 CC2 Y Pa Compare 3 P1 3 INT6 CC3 Y PA 00081 Figure 5 Interrupt Request Sources Semiconductor Group 6 31 SIEMENS 80C515A 83C515A 5 IP1 0 1 0 0 Level 3 Level 2 Level 1 Level 0 m M zm E m N m e m e N Cx m X m 2 V Da e Da Da A 7 gt gt a 7 EN Figure 6 Interrupt Priority Level Structure Semiconductor Group Interrupt Request Vector Priority Control Locations 500082 6 32 SIEMENS SAB 80C515A 83C515A 5 Ports The SAB 80C515A has six 8 bit I O ports and one input port Port 0 is an open drain bidirectional I O port while ports 1 to 5 are quasi bidirectional I O ports with internal pull up resistors That means when configured as inputs ports 1 to 5 will be pulled high and will source current when externally pulled low Port 0 will float when configured as input Port 0 and port 2 can be used to expand the program and data memory externally During an access to external memory port 0 emits the low order address byte and reads writes the data byte while port 2 emits the high order address byte In this function 0
23. alt output alt output last output last output P6 1 1 1 function EA active input2 PE SWD active input pull up disabled 2 XTAL1 active output XTAL2 disabled input function 1 PSEN high high low low floating output ALE high high low low active supply pins VAGND RESET active input must be high 1 Applied voltage range at pin Vss lt lt Vin Vss OF Vin 3 Semiconductor Group Vss lt lt gt VAGND SIEMENS SAB 80C515A 83C515A 5 Serial Interface The SAB 80C515A has a full duplex and receive buffered serial interface It is functionally identical with the serial interface of the SAB 8051 Table 6 shows possible configurations and the according baud rates Table 6 Baud Rate Generation Mode 8 Bit fosc 12 MHz 1 MHz syn fosc 16 MHz 1 33 MHz OUS fosc 18 MHz 1 5 MHz channel derived from fosc Mode Mode 1 8 Bit fosc 12 MHz 1 Baud 62 5 kBaud 183 Baud 375 kBaud fosc 16 MHz 1 Baud 83 kBaud 244 Baud 500 kBaud fosc 18 MHz 1 Baud 93 7 kBaud 2375 Baud 562 5 kBaud derived from Timer 1 10 Bit Baudrate Generator Mode Mode 2 Mode 3 9 Bit fosc _12 MHz 187 5 1 Baud 183 Baud 75 kBaud UART 375 kBaud 62 5 kBaud fosc 16 MHz 250 Baud 1 Baud 244 Baud 500 kBaud 500 kBaud 83 3 kBaud fosc 18 MHz 281 2 kBaud 1
24. has the same instruction set as the industry standard 8051 microcontroller A pocket guide is available which contains the complete instruction set in functional and hexadecimal order Furtheron it provides helpful information about Special Function Registers Interrupt Vectors and Assembler Directives Literature Information Title Ordering No Microcontroller Family SAB 8051 Pocket Guide B158 H6497 X X 7600 Semiconductor Group 6 42 SIEMENS 80C515A 83C515A 5 Absolute Maximum Ratings Ambient temperature under bias Storage temperature Voltage pins with respect to ground Vss Voltage on any pin with respect to ground Vss Input current on any pin during overload condition Absolute sum of all input currents during overload condition Power dissipation 40 to 85 65 to 150 0 5 Vto6 5V 0 5 to 0 5 V 10mA to 10 mA 100 1W Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for longer periods may affect device reliability During overload conditions gt or Vin lt theVoltage on pins with respect to ground Vss must not exeed the
25. initialization is done when pin PE SWD Pin 4 is held high during RESET The 80C515A then starts program execution with the WDT running Since pin PE SWD is only sampled during Reset the WDT cannot be started externally during normal operation Software initialization is done by setting bit SWDT in SFR A refresh of the watchdog timer is done by setting bits WDT SFR IENO and SWDT consecutively This double instruction sequence has been implemented to increase system security When a watchdog timer reset occurs the watchdog timer keeps on running but a status flag WDTS SFR is set This flag can also be cleared by software Figure 7 shows the block diagram of the programmable Watchdog Timer Oscillator Watchdog The unit serves three functions Monitoring of the on chip oscillator s function The watchdog monitors the on chip oscillator s frequency if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit the internal clock is supplied by the RC oscillator and the device is forced into reset if the failure condition disappears i e the on chip oscillator has again a higher frequency than the RC oscillator the part executes a final reset phase of appr 0 25 ms in order to allow the oscillator to stabilize then the oscillator watchdog reset is released and the part starts program execution again Restart from the Hardware Power Down Mode If the Hardware Power Down Mode is
26. is disabled Nevertheless an access from internal ROM to external ROM is possible To verify the read protected ROM Code a special ROM Verify Mode is implemented This mode also can be used to verify unprotected internal ROM ROM Protection ROM Verification Mode Restrictions see Characteristics no ROM Verification Mode 1 standard 8051 Verification Mode ROM Verification Mode 2 yes ROM Verification Mode 2 standard 8051 Verification Mode is disabled externally applied MOVC accessing internal ROM is disabled Semiconductor Group 3 2 SIEMENS Memory Organization 3 2 Data Memory The data memory space consists of an internal and an external memory space The SAB 80C515A contains another 1 of On Chip RAM additional to the 256 Bytes internal RAM of the base type SAB 80C515 This RAM is called XRAM eXtended RAM in this document External Data Memory Up to 64 Kbyte external data memory can be addressed by instructions that use 8 bit or 16 bit indirect addressing For 8 bit addressing MOVX instructions in combination with registers RO and 1 can be used A 16 bit external memory addressing is supported by a 16 bit datapointer Registers XPAGE and SYSCON are controlling whether data fetches at addresses F800 to FBFFy done from internal XRAM or from external data memory nternal Data Memory The internal data memory is divided into four physically distinct blocks
27. is not an open drain port but uses a strong internal pull up FET Ports 1 3 and 4 are provided for several alternate functions as listed below Port Symbol Function P1 0 INT3 CCO External interrupt input compare 0 output capture 0 input P1 1 INT4 CC1 External interrupt 4 input compare 1 output capture 1 input P1 2 INT5 CC2 External interrupt 5 input compare 2 output capture 2 input P1 3 INT6 CC3 External interrupt 6 input compare 3 output capture 3 input P1 4 INT2 External interrupt 2 input P1 5 T2EX Timer 2 external reload trigger input P1 6 CLKOUT System clock output P1 7 T2 Timer 2 external count or gate input P3 0 RxD Serial port s receiver data input asynchronous data input output synchronous P3 1 TxD Serial port s transmitter data output asynchronous or clock output synchronous P3 2 INTO External interrupt 0 input timer 0 gate control P3 3 INT 1 External interrupt 1 input timer 1 gate control P3 4 TO Timer 0 external counter input 5 1 Timer 1 external counter input P3 6 WR External data memory write strobe 7 External data memory read strobe P4 0 ADST A D Converter external start of conversion The SAB 80C515A has one dual purpose input port The ANx lines of port 6 in the SAB 80C515 can individually be used as analog or digital inputs Reading the special function register P6 allows the user to input the digital values currently applied to the port pins It is not necessary
28. of it also belong to other functional blocks 3 X means that the value is indeterminate and the location is reserved Semiconductor Group 6 24 SIEMENS SAB 80C515A 83C515A 5 A D Converter In the SAB 80C515A a new high performance high speed 8 channel 10 bit A D Converter ADC is implemented Its successive approximation technique provides 7 us conversion time fosc 16 MHz The conversion principle is upward compatible to the one used in the SAB 80C515 The main functional blocks are shown in figure 3 The comparator is a fully differential comparator for a high power supply rejection ratio and very low offset voltages The capacitor network is binary weighted providing genuine10 bit resolution The table below shows the sample time T s and the conversion time T c which are dependend Oh f osc and a new prescaler f osc MHz Prescaler f Apc MHz Sample Time Conversion Time incl sample time Ts us Tc us 12 8 1 5 2 67 9 3 16 0 75 5 33 18 66 16 8 2 0 2 0 7 0 16 1 0 1 0 14 0 18 8 16 1 125 3 55 12 4 The ADC is clocked f with f 8 Because of the ADC s maximum clock frequency of 2 MHz the prescaler divide by 2 has to be enabled set Bit ADCL in SFR ADCON 1 when the oscillator frequency is higher than 16 MHz Semiconductor Group 6 25 SIEMENS SAB 80C515A 83C515A 5 internal Bus P6 DBy i Jos Je
29. terminated the oscillator watchdog has to control the correct start up of the on chip oscillator and to restart the program The oscillator watchdog function is only part of the complete Hardware Power Down sequence however the watchdog works identically to the monitoring function Fastinternal reset after power on In this function the oscillator watchdog unit provides a clock supply for the reset before the on chip oscillator has started In this case the oscillator watchdog unit also works identically to the monitoring function Semiconductor Group 6 40 SIEMENS SAB 80C515A 83C515A 5 Figure 8 shows the block diagram of the oscillator watchdog unit It consists of an internal RC oscillator which provides the reference frequency for the frequency comparator ee WDT Reset Request WOTH 0 9 wss Hardware Power Down HWPD External HW Reset PE SWD WDT SWDT MCB01495 Control Logic meos Figure 7 Block Diagram of the Programmable Watchdog Timer Frequency fa lt fi Comparator Delay int Reset RC Fre Oscillator 3MHz 1 0 0 9 On Chi Oscillator w T qq pq XTAL2 OL int Clock 2 Oo MCB01569 Figure 8 Functional Block Diagram of the Oscillator Watchdog Semiconductor Group 6 41 SIEMENS SAB 80C515A 83C
30. the SAB 80C515A 83C515A 5 contains more on chip RAM ROM Furthermore a new 10 bit A D Converter is implemented as well as extended security mechanisms The SAB 80C515A is identical with the SAB 83C515A 5 except that it lacks the on chip program memory The SAB 80C515A 83C515A 5 is supplied in 68 pin plastic leaded chip carrier package P LCC 68 The essential enhancements to the SAB 80C515 are see also figure 2 1 Additional 1KByte RAM on chip 8 Channel 10 bit A D Converter New baud rate generator for the Serial Channel Oscillator Watchdog Unit Improved functionality of the Watchdog Timer Hardware controlled Power Down Mode High speed operation of the device up to 18 MHz crystal frequency Semiconductor Group 2 1 SIEMENS Fundamental Structure 7 7 7 Oscillator RAM Watchdog 256x8 1 8 ZN SAB Osc amp 85 515 5 Timing only Vss 2 Port 0 gt 8 Bit amm A Timer 2 Lid Capture Unit 5 gt Port 4 gt 8 Bit Serial Port Port 5 Generator 22 Interrupt Bod ANO AN7 PEN Port 6 S Port 6 8 Bit gt VAREF VAGND 2 ZZ Enhancements to the Ext Start
31. 0 0784 P LCC 68 external memory 18 MHz ext temperature 40 to 85 83C515A 5N18 T3 Q67120 DXXXX P LCC 68 with mask programmable ROM 18 MHz ext temperature 40 to 85 80C515A M18 T3 067120 0851 80 for external memory 18 MHz ext temperature 40 to 85 83C515A 5M18 T3 Q67120 DXXXX P MQFP 80 with mask programmable ROM 18 MHz ext temperature 40 to 85 Notes Versions for extended temperature range 40 to 110 on request The ordering number of ROM types DXXXX extension is defined after program release verification of the customer Semiconductor Group 6 2 SIEMENS SAB 80C515A 83C515A 5 XTAL1 ue XTAL2 Port 1 8 Bit V AREF Port 2 VAGND 8 Bit SAB Port 3 Port 6 80C515A Bp 8 8it 83 515 5 Port 4 HWPD 8 Bit PE SWD aa DI i ALE RESET PSEN 101562 Logic Symbol Semiconductor Group 6 3 SIEMENS SAB 80C515A 83C515A 5 The pin functions of the SAB 80C515A are identical with those of the SAB 80C515 with following exception Pin 80 515 80 515 68 HWPD 1 P0 4 ADST P4 0 4 PE SWD PE 80 515 83 515 5 RxD P3 0 TxD P3 1 INTO P3 2 INT P3 3 T0 P3 4 T1 P3 5 vc Ks MCP01561 XTAL2 XTAL1 P2 0 P2 1 P2 2 CCO INT3 P1 0 0 Pin Configuration P LCC 68 Semiconductor Group 6 4
32. 2 2 2 2 2 INVHX euo 9 gt Hilda sngc zd od e sng zd od e sngc zd od e sng zd od e sng ezd od e sng ed od e Hldd XAOW LX OL 00 LX OL 00 OdVINX ld VINX OdVINX LdVINX 3 0 3 16 Semiconductor Group SIEMENS System Reset 4 System Reset 41 Additional Hardware Power Down Mode in the SAB 80C515A The SAB 80C515A has an additional Power Down Mode which can be initiated by an external signal at a dedicated pin This pin is labeled HWPD and is a floating input line active low This pin substitutes one of the Vcc pins of the base types SAB 80C515 PLCC68 Pin68 Because this new power down mode is activated by an external hardware signal this mode is referred to as Hardware Power Down Mode in opposite to the program controlled Software Power Down Mode Pin PE SWD has no control function for the Hardware Power Down Mode it enables and disables only the use of all software controlled power saving modes Idle Mode Software Power Down Mode The function of the new Hardware Power Down Mode is as follows The pin HWPD controls this mode If it is on logic high level inactive the part is running in the normal operating modes If pin HWPD gets active low level the part ent
33. 2K x8 ROM SAB 83C515A 5 only ROM e genuine 10 bit A D converter with 8 Protection available multiplexed inputs 256 x 8 on chip RAM Full duplex serial interface with e additional 1 x 8 on chip RAM XRAM programmable Baudrate Generator e Superset of SAB 80C51 architecture e Functionally compatible with SAB 80C515 1 us instruction cycle time at 12 MHz Extended power saving modes 666 ns instruction cycle time at 18 MHz Fast Power On Reset 256 directly addressable bits Six ports 48 I O lines 8 input lines Boolean processor Three temperature ranges available 64 Kbyte external data and program memory 0 to 70 T1 addressing 4010 85 3 Three 16 bit timer counters 4010 1109 4 Versatile fail safe provisions e Plastic package P LCC 68 The pin functions of the SAB 80C515A are identical with those of the SAB 80C515 with following exceptions SAB 80C515A SAB 80 515 Pin 68 HWPD Pin 1 P4 0 ADST 4 0 Pin 4 PE SWD PE Semiconductor Group 1 2 SIEMENS Fundamental Structure 2 Fundamental Structure The SAB 80C515A 83C515A 5 is a high end member of the Siemens SAB 8051 microcontroller family It is designed in Siemens ACMOS technology and based on the SAB 8051 architecture ACMOS is a technology which combines high speed and density characteristics with low power consumption or dissipation While maintaining all the SAB 80C515 features and operating characteristics
34. 5 0014 josey QdMH 95 GS 75 S 25 5 95 GS 75 65 05 15 95 GS 75 S 05 5 95 GS 75 55 05 5 95 65 Timing Diagram of Entering Hardware Power Down Mode Figure 4 1 4 5 Semiconductor Group System Reset SIEMENS stl yg sri gj EMERI 44 51 19592 294109 se 9 2x20 9 GAMH ueeMjeq 99 ppd si 294 71440 50 4 2 0 dn DJS 404011950 98 2040111950 9149 00 10101 250 LL uo 0 gt l u Jo OWJON JeMog jasoy 394 7950 79 250 22 QQ 504 910515 10014 a Zd Zd 95 SS 75 FS 65 15 95 Timing Diagram of Leaving Hardware Power Down Mode Figure 4 2 4 6 Semiconductor Group System Reset SIEMENS 60500194 40102990 OWION lt 2159 2 jesey puJeju SUEDE diu3 ug Jesay 394 7980 794 7250 spod 9594 OdMH OdMH 4 Zd Zd Zd Zd 95 SS 7 5 65 S 95 GS 75 65 05 15 95 SS 75 FS 65 15 95 GS YS 5 65 15 95 SS Timing Diagram of Hardware Power Down Mode HWPD Pin is active for only one Cycle Figure 4 3 4 7 Semiconductor Gr
35. 515A 5 Fast internal reset after power on The SAB 80C515A can use the oscillator watchdog unit for a fast internal reset procedure after power on Normally members of the 8051 family like the SAB 80C515 enter their default reset state not before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 1 ms During this time period the pins have an undefined state which could have severe effects e g to actuators connected to port pins In the SAB 80C515A the oscillator watchdog unit avoids this situation After power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 ms In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip rather than the on chip oscillator s output This allows correct resetting of the part and brings also all ports to the defined state Delay time between power on and correct reset state Typ 18 us Max 34 us Instruction Set The SAB 80C515A 83C515A 5
36. A 83C515A 5 Requirements for Hardware Power Down Mode There is no dedicated pin to enable the Hardware Power Down Mode The control pin PE SWD has no control function in this mode It enables and disables only the use of software controlled power saving modes Software Controlled Power Saving Modes All of these modes are entered by software Special function register PCON power control register address is 87 is used to select one of these modes Slow Down Mode During slow down operation all signal frequencies that are derived from the oscillator clock are divided by eight also the clockout signal and and the watchdog timer count The slow down mode is enabled by setting bit SD The controller actually enters the slow down mode after a short synchronisation period max 2 machine cycles The slow down mode is disabled by clearing bit SD Idle Mode During idle mode all peripherals of the SAB 80C515A except for the watchdog timer are still supplied by the oscillator clock Thus the user has to take care which peripheral should continue to run and which has to be stopped during Idle The procedure to enter the Idle mode is similar to the one entering the power down mode The two bits IDLE and IDLS must be set by two consecutive instructions to minimize the chance of unintentional activating of the idle mode There are two ways to terminate the idle mode The idle mode can be terminated by activating any enabled inte
37. AB 80C515A 83C515A 5 is a high end member of the Siemens SAB 8051 microcontroller family It is designed in Siemens ACMOS technology and based on the SAB 8051 architecture ACMOS is a technology which combines high speed and density characteristics with low power consumption or dissipation While maintaining all the SAB 80C515 features and operating characteristics the SAB 80C515A 83C515A 5 contains more on chip RAM ROM Furthermore a new 10 bit A D Converter is implemented as well as extended security mechanisms The SAB 80C515A is identical with the SAB 83C515A 5 except that it lacks the on chip program memory SAB 80 515 83C515A 5 is supplied in a 68 pin plastic leaded chip carrier package P LCC 68 and in a 80 pin plastic metric quad flat package P MQFP 80 Versions for extended temperature range 40 to 110 C are available on request Semiconductor Group 6 1 08 95 SIEMENS SAB 80C515A 83C515A 5 SAB 80 515 80 535 Oscillator Watchdog zn 8 HW Power Down Mode Slow Down Mode Analog ROM Digital 24k x 8 Input ROM Protection available Shaded areas meaning improved functionality 01560 Ordering Information Type Ordering Package Description Code 8 Bit CMOS microcontroller SAB 80C515A N18 Q67120 C0581 P LCC 68 external memory 18 MHz SAB 83C515A 5N18 Q67120 DXXXX P LCC 68 with mask programmable ROM 18 MHz 80C515A N18 T3 06712
38. Baud 275 Baud 562 5 kBaud 562 5 kBaud 93 7 kBaud derived from fosc 2 Timer 1 10 Bit Baudrate Generator Semiconductor Group 6 38 SIEMENS SAB 80C515A 83C515A 5 The Serial Interface can operate in 4 modes Mode 0 Mode 1 Mode 2 Mode 3 Shift register mode Serial data enters and exits through R x D T x D outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at 1 12 of the oscillator fre quency 8 bit UART variable baud rate 10 bit are transmitted through T x D or received through R x D a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into RB80 in special function register SCON The baud rate is variable 9 bit UART fixed baud rate 11 bit are transmitted through T x D or received through R x D a start bit 0 8 data bits LSB first a programmable 9th and a stop bit 1 On transmission the 9th data bit TB80 in SCON can be assigned to the value of 0 or 1 For example the par ity bit P in the PSW could be moved into TB80 or a second stop bit by setting TB80 to 1 On reception the 9th data bit goes into RB80 in special function register SCON while the stop bit is ignored The baud rate is programmable to either 1 32 or 1 64 of the oscillator frequency 9 bit UART variable baud rate 11 bit are transmitted through T x D or received through R x D a start bit 0 8 data bits LSB firs
39. H 1 0 SRELL Baud Rate Clock Phase 2 CLK 37 242 10 Bit Timer Overflow MCT02119 Figure 5 4 Baud Rate Generator for the Serial Interface Semiconductor Group 5 8 SIEMENS On Chip Peripheral Components Special Function Register SORELH SORELL MSB LSB Bit No 7 6 5 4 3 2 1 0 OBA msb SRELH MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr 156 SRELL shaded areas are not used for programming the baudrate timer Bit Function SRELH 0 1 Reload value Upper two bits of the timer reload value SRELL 0 7 Reload value Lower 8 bit of timer reload value Reset value of SRELL is 009 SRELH contains XX11p Semiconductor Group 5 9 SIEMENS On Chip Peripheral Components Figure 5 5 shows a block diagram of the options available for baud rate generation of Serial Channel It is a fully compatible superset of the functionality of the 80C515 The new baud rate generator can be used in modes 1 and 3 of the Serial Channel It is activated by setting bit BD ADCON 7 This also starts the baud rate timer When Timer1 shall be used for baud rate generation bit BD must be cleared In any case bit SMOD PCON 7 selects an additional divider by two The default values after reset in registers SRELL and SRELH provide a baud rate of 4 8 kBaud with SMOD 0 or 9 6 kBaud with SMOD 1 at 12 MHz oscillator frequenc
40. OIN pue zd Od 10 L eigen 6 19 Semiconductor Group SIEMENS SAB 80C515A 83C515A 5 Special Function Registers All registers except the program counter and the four general purpose register banks reside in the special function register area The special function registers include arithmetic registers pointers and registers that provide an interface between the CPU and the on chip peripherals There are also 128 directly addressable bits within the SFR area All special function registers are listed in table 2 and table 3 In table 2 they are organized in numeric order of their addresses In table 3 they are organized in groups which refer to the functional blocks of the SAB 80C515A Table 2 Special Function Register Address Register Contents Address Register Contents after Reset after Reset 80H PO OFF 98 SOCON 7 004 81 SP 074 99 SBUF Xx 2 824 DPL 00 reserved 9 8 00 9By reserved XX4 844 WDTL 9Cy reserved 2 85 WDTH 9 reserved 864 WDTREL 004 reserved 9 87 00 reserved XX4 88 TCON A0 P2 1 OFF 89 TMOD 004 Aly reserved 9 8 TLO 00 A24 reserved XXy 9 8By TL1 00 reserved XXy 2 8 THO 00 A4y reserved XXy 9 8Dy TH1 00 Ady reserved XXy 2 8Ey reserved 9 reserved XXy 9 8Fy reserved 7 reserved 90H P1 OFFy 8 IENO 7 00 91 X
41. OM Verification Characteristics 25 C 5 5V 10 1596 Vss Parameter Symbol Limit values Unit min max ROM Verification Mode 1 Standard Verify Mode for not Read Protected ROM Address to valid data fAVQV 48 tci cL ns ENABLE to valid data fELQV 48 tci cL ns Data float after ENABLE teyoz 0 48 tci cL ns Oscillator frequency 4 6 2 P1 0 P1 7 P2 0 P2 6 Port 0 Address Data feray 1 0 1 7 0 7 2 0 2 6 8 14 0 0 0 7 00 07 ROM Verification Mode 1 Semiconductor Group Data Out tugz 001498 Inputs PSEN Vs ALEEA RESET Mi 6 53 SIEMENS SAB 80C515A 83C515A 5 ROM Verification Mode 2 New Verify Mode for Protected and not Protected ROM 55 S4 55 S5 3L 5555 51 2 S4 55 S 92 54 S P2 P2 Pi P2 P2 P1P2 P2 P2 P2 P2 1 sample RESET RESET int ROM Code ROM Code ROM Code adr 0000 adr 0001H adr 0002H l 1 499 Y RESET State Increment Address counter for external ROM Inputs E ALE forced to low level a weak pull down resistor approx 400 during RESET activ ROM Code Port 0 00 07 Outputs Port 3 5 shows all 1024 cycles low level for one cycle when compared ROM Code was not alright
42. PAGE xx A9 IPO 00 924 reserved XX4 SRELL 009 934 reserved XX4 reserved 944 reserved reserved XX4 954 reserved XX4 reserved XX4 96 reserved XX4 reserved XX4 974 reserved XX4 reserved 1 Bit addressable special function registers 2 X means that the value is indeterminate and the location is reserved Semiconductor Group 6 20 SIEMENS SAB 80C515A 83C515A 5 Table 2 Special Function Register cont d Address Register Contents Address Register Contents after Reset after Reset BO P3 1 OFF PSW 1 00 SYSCON XXXX XX01g D1y reserved XX B24 reserved D2y reserved reserved reserved XX B4 reserved 9 D44 reserved 5 reserved D54 reserved XX B64 reserved XX4 reserved XX4 B74 reserved XXy D7y reserved XX B84 1 D84 ADCONO 00 00 0000 2 D9 ADDATH 00 BA SRELH XXXX 11 2 DAy ADDATL 004 reserved XXy 9 DBy P6 XX BC reserved XX4 DV ADCVON1 XXXX 000062 reserved XXy 9 reserved XX BE reserved XX4 DEy reserved XXH BF reserved 2 reserved XX C0 IRCON 00 EO ACC 00 reserved 2 CCL1 00 E24 reserved XX4 2 C34 CCH1 0014 E3 reserved 2 CCL2 00 E44 reserved XX4 5 00 5 reserved C6
43. SIEMENS Microcomputer Components SAB 80C515A 83C515A 5 8 Bit CM OS Single Chip M icrocontroller Family Addendum to User s M anual SAB 80515 80C515 08 95 SAB 80 515 83 515 5 Addendum Revision History Current Version 08 95 Previous Version 11 92 Page Subjects major changes since last revision 3 6 CCH4 CCL4 deleted 3 16 Table supplemented MOVX Ri EA 1 00 5 4 Falling edge for P4 0 ADST in figure 5 2 added 5 10 Formula for SREL added 6 1 New release of SAB 80 515 83C515A 5 data sheet inserted Edition 08 95 Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 Siemens AG 1995 All Rights Reserved Attention please As far as patents or other rights of third parties are concerned liability is only assumed for components not for applications processes and circuits implemented within components or assemblies The information describes the type of component and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Siemens Office Semicond
44. al pull up resistors P4 also contains the external A D converter control pin The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The sec ondary function assigned to port 6 ADST P4 0 external A D converter start pin PE SWD 4 75 Power saving mode enable Start Watch dog Timer A low level on this pin allows the software to enter the power down idle and slow down mode In case the low level is also seen during reset the watchdog timer function is off on de fault Use of the software controlled power saving modes is blocked when this pin is held on high level A high level during reset performs an automatic start of the watchdog timer im mediately after reset When left unconnected this pin is pulled high by a weak internal pull up resistor RESET 10 1 Reset pin A low level on this pin for the duration of two machine cycles while the oscillator is running resets the SAB 80C515A A small internal pullup resistor permits power on reset using only a capacitor connected to Vss VAREF1 11 3 Reference voltage for the A D converter VAGND 12 4 Reference ground for the A D converter Semiconductor Group 6 6 SIEMENS 80C515A 83C515A 5 Pin Definitions and Functions cont d Pin P LCC 68 Symbol Pin P MQFP 80 Input 1 Output O Function P6 7 P6 0 13 20 5 12 Port 6 is an 8 bit unidirectio
45. anization Port 0 Address Data XRAM Write 1 0 Data to Port 2 gt 0 Data 1 MCB02114 Figure 3 4 Use of Port 2 as I O Port At a write to Port 2 XRAM address in XPAGE register will be overwritten because of the concurrent write to Port 2 and XPAGE register So whenever XRAM is used and the XRAM address differs from the byte written to Port 2 latch it is absolutely necessary to rewrite XPAGE with page address Example I O Data at Port 2 shall be 0 A Byte shall be fetched from at address 0 830 MOV RO 304 MOV P2 0 P2 shows MOV XPAGE 0 8 P2 still shows but is addressed MOVX A RO the contents of XRAM at OF830j is moved to accu Semiconductor Group 3 12 SIEMENS Memory Organization The register XPAGE provides the upper address byte for accesses to XRAM with MOVX Ri instructions If the address formed from XPAGE and Ri is less than the XRAM address range then an external access is performed For the SAB 80C515A the contents of XPAGE must be greater or equal than F8H in order to use the XRAM Of course the XRAM must be enabled if it shall be used with MOVX Ri instructions Thus the register XPAGE is used for addressing of the XRAM additionally its contents are used for generating the internal XRAM select If the contents of XPAGE is less than the XRAM address range then an external bus access is pe
46. atches one of the stored values an appropriate output signal is generated and an interrupt is requested Two compare modes are provided Mode 0 Upon a match the output signal changes from low to high It goes back to low level when timer 2 overflows Mode 1 The transition of the output signal can be determined by software A timer 2 overflow causes no output change Semiconductor Group 6 28 SIEMENS SAB 80C515A 83C515A 5 P15 T2EX N 3 co lt 5 gt lt a 21 Interrupt Request FOSC 12 e P1 0 INT3 16 Bil 16 Bit 16 Bit 16 Bit S e 1 2 1 5 1 e e P1 3 INT6 CC3 Q v Capture CCL2 CCH2 CCL1 CCH1 CRCL CRCH MCB00079 Figure 4 Block Diagram of Timer Counter 2 A CCL3 CCH3 Semiconductor Group 6 29 SIEMENS SAB 80C515A 83C515A 5 Interrupt Structure The SAB 80C515A has 12 interrupt vectors with the following vector addresses and request flags Table 4 Interrupt Sources and Vectors Source Request Flags Vector Address Vector IEO 00034 External interrupt 0 TFO 000B Timer 0 interrupt IE1 0013 External interrupt 1 TF 1 001By Timer 1 interrupt RI TI 0023 Serial port interrupt TF2 EXF2 002By Timer 2 interrupt IADC 0043 A D converter interr
47. by 16 prescaler see figure 12 WDTREL 6 Seven bit reload value for the high byte of the watchdog timer to This value is loaded to the WDT when a refresh is triggered by a consecutive WDTREL O setting of bits WDT and SWDT Reset value of WDTREL is 00 Immediately after start see next section for start procedure the Watchdog Timer is initialized to the reload value programmed to WOTREL O WDTREL 6 After an external HW reset or power on reset or HW Power Down register WDTREL is cleared to 00 The lower seven bits of WOTREL can be loaded by software at any time Examples given for 12 and 18 MHz oscillator frequency WDTREL Time out Period Comments 00H 65 535 ms 43 690 ms This is the default value and coincides with the watchdog period of the SAB 800515 115 0 735 maximum time period 512 us 341 us minimum time period Semiconductor Group 5 13 SIEMENS On Chip Peripheral Components Starting the Watchdog Timer There are two ways to start the Watchdog Timer depending on the level applied to the pin PE SWD Power Down Modes enable Start Watchdog Timer 4 This pin serves two functions new for the SAB 80C515A because it is also used for disabling the software initiated power saving modes For details concerning software initiated power saving modes see User s Manual SAB 80C515 Automatic Start of the Watchdog Timer The automatic start of the Watchdog Timer dir
48. cesses use external memory via the external bus In this case the 80C515A does not use the additional On Chip RAM and is compatible with the types without XRAM Semiconductor Group 6 17 SIEMENS SAB 80C515A 83C515A 5 is hardware protected by an latch An unintentional disabling of XRAM could be dangerous since indeterminate values would be read from external bus To avoid this the XMAP bit is forced to 1 only by reset Additionally during reset an internal capacitor is loaded So after reset state XRAM is disabled Because of the load time of the capacitor XMAPO bit once written to 0 that is discharging capacitor cannot be set to 1 again by software On the other hand any distortion software hang up noise is not able to load this capacitor too That is the stable status is XRAM enabled The only way to disable XRAM after it was enabled is a reset The clear instruction for should be integrated in the program initialization routine before XRAM is used In extremely noisy systems the user have redundant clear instructions The control bit XMAP1 is relevant only if the XRAM is accessed In this case the external RD and WR signals at P3 6 and P3 7 are not activated during the access if XMAP1 is cleared For debug purposes it might be useful to have these signals and the addresses at Ports 0 2 available This is performed if XMAP1 is set The behaviour of Port 0 and P2 durin
49. cy of 18 MHz is higher than at the SAB 806515 With exception of the ROM sizes both parts are identical Therefore the therm SAB 80C515A refers to both versions within this specification unless otherwise noted Memory Organisation According to the SAB 8051 architecture the SAB 80C515A has separate address spaces for program and data memory Figure 2 illustrates the mapping of address spaces FFFF H indirectly addressable 1 Int XMAPO 0 indirect direct jt addr SFR 80 2 7Fy int RAM 0000 v Code Space external Data Space internal Data Space 001564 Figure 2 Semiconductor Group 6 12 SIEMENS SAB 80C515A 83C515A 5 Program Memory Code Space The SAB 83C515A 5 has 32 Kbyte of on chip ROM while the SAB 80C515A has no internal ROM The program memory can externally be expanded up to 64 Kbyte Pin EA determines whether program fetches below address 8000 are done from internal or external memory As a new feature the SAB 83C515A 5 offers the possibility of protecting the internal ROM against unauthorized access This protection is implemented in the ROM Mask Therefore the decision ROM Protection no has to be made when delivering the ROM Code Once enabled there is no way of disabling the ROM Protection Effect access to internal ROM done by an externally fetched MOVC instruction is disabled N
50. defined state see figure 4 4 The time period from power on until reaching the reset state at the ports derives from the following terms RC oscillator start up lt 2us synchronization of the RC oscillators divider by 5 lt 6T synchronization of the state and cycle counters 6T reset procedure till correct port states are reached lt 12T Delay between power on and correct reset state Typ 18 us 34us Semiconductor Group 4 8 SIEMENS System Reset After the on chip oscillator finally has started the oscillator watchdog detects the correct function then the watchdog still holds the reset active for a time period of 768 cycles of the RC oscillator in order to allow the oscillation of the on chip oscillator to stabilize figure 4 4 Subsequently the clock is supplied by the on chip oscillator and the oscillator watchdog s reset request is released figure 4 4 However an externally applied reset still remains active figure 4 4 and the device does not start program execution figure 4 4 V before the external reset is also released Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up The reasons are as follows Termination of Hardware Power Down Mode a HWPD signal is overridden by reset Termination of Software Power Down Mode Reset of the status flag OWDS that is set by the oscil
51. dundant clear instructions The control bit XMAP1 is relevant only if the is accessed In this case the external RD and WR signals at P3 6 and P3 7 are not activated during the access if 1 is cleared For debug purposes it might be useful to have these signals and the Ports 0 2 available This is performed if 1 is set 3 4 3 Behaviour of PortO and Port2 The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register SYSCON and on the state of pin EA The table 3 3 lists the various operating conditions It shows the following characteristics a Use of PO and P2 pins during the MOVX access Bus The pins work as external address data bus If internal XRAM is accessed the data written to the XRAM can be seen on the bus in debug mode I 0 The pins work as Input Output lines under control of their latch b Activation of the RD and WR pin during the access C Use of internal or external XDATA memory The shaded areas describe the standard operation as each 80C51 device without on chip XRAM behaves Semiconductor Group 3 15 Memory Organization SIEMENS XAOW unna 10 6 6 91421 K IUe LG09 01 pesn 1 pesn 1 2 pesn s 2 pesn s NvHX 9 2 pesn s NVHX 9 pesn s NvHX 9
52. e Semiconductor Group 6 49 SIEMENS SAB 80C515A 83C515A 5 2 0 2 7 or 8 15 from 8 15 from PCH 00792 Data Memory Write Cycle Semiconductor Group 6 50 SIEMENS SAB 80C515A 83C515A 5 AC Characteristics cont d Parameter Symbol Limit values Unit Variable clock Frequ 3 5 MHz to 18 MHz min max External Clock Drive Oscillator period 55 6 285 ns High time CHCX 20 ns Low time tCLCX 20 tcLCL CHCX ns Rise time 20 ns Fall time 20 5 Oscillator frequency l teic 3 5 18 MHz 0 2 Vc 0 1V MCT00793 External Clock Cycle Semiconductor Group 6 51 SIEMENS SAB 80C515A 83C515A 5 AC Characteristics cont d Parameter Symbol Limit values Unit 18 MHz clock Variable clock 1 t 3 5 MHz 18 MHz min max min max System Clock Timing ALE to CLKOUT tLLSH 349 40 l ns CLKOUT high time SHSL 71 2 740 ns CLKOUT low time 516 10 40 ns a low to ALE 16 96 40 40 ns 9 CLKOUT Programm Memory Access Data Memory Access RD WR 00794 System Clock Timing Semiconductor Group 6 52 SIEMENS SAB 80C515A 83C515A 5 R
53. e are a Read and a Write instruction from and to XRAM which use one of the 16 bit DPTR for indirect addressing The instructions are MOVX A DPTR Read MOVX QDPTR Write Normally the use of these instructions would use a physically external memory However in the SAB 80C515A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM address space gt F800j Semiconductor Group 3 8 SIEMENS Memory Organization Accesses to XRAM using the Registers RO R1 The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8 bit address indirect addressing with registers RO or R1 The instructions are MOVX A Ri Read MOVX Ri A Write In application systems either a real 8 bit bus with 8 bit address is used or Port 2 serves as page register which selects pages of 256 Byte However the distinction whether Port 2 is used as general purpose I 0 or as page address is made by the external system design From the device s point of view it cannot be decided whether the Port 2 data is used externally as address as 1 0 data Hence a special page register is implemented into the SAB 80C515A to provide the possibility of accessing the XRAM also with the MOVX Ri instructions i e XPAGE serves the same function for the XRAM as Port 2 for external data memory Special Function Register XPAGE MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr 91H XPAGE
54. eans that the value is indeterminate and the location is reserved Semiconductor Group 3 6 SIEMENS Memory Organization Table 3 2 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset Ports PO Port 0 80H OFFY 1 Port 1 2 2 AOp Port 3 OFFy 4 4 OFFy 5 Port 5 OFFy P6 Port 6 Analog Digital Input DBy Power Save Power Control Register 87H 00H Modes Serial ADCONO A D Converter Control Reg 0D84 00 Channels 2 Power Control Register 87H 00H SBUF Serial Channel Buffer Reg 994 OXXy 9 SCON Serial Channel Control Reg 98H 00H SRELL Serial Channel Reload Reg low byte AAH SRELH Serial Channel Reload Reg high byte XXXX XX11p Timer 0 TCON Timer Control Register 88 00H Timer 1 THO Timer 0 High Byte 8CH 00H TH1 Timer 1 High Byte 00H TLO Timer 0 Low Byte 8AH 00H TL1 Timer 1 Low Byte 8By 00H TMOD Timer Mode Register 89H 00H Watchdog IENO 2 Interrupt Enable Register 0 A8y 00H IEN1 2 Interrupt Enable Register 1 B8y 00H IPO 9 Interrupt Priority Register 0 00H IP12 Interrupt Priority Register 1 B9H XX00 0000p WDTREL Watchdog Timer Reload Reg 86H 00H 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to o
55. ectly after an external reset or a Hardware Power Down HWPD PLCC68 pin 60 new for 80C515A is a hardware start initialized by strapping pin 4 PE SWD to In this case the power saving modes Software power down mode and idle mode are disabled and cannot be started by software If pin PE SWD is left unconnected a weak pull up transistor ensures the automatic start of the Watchdog Timer The self start of the Watchdog Timer by a pin option has been implemented to provide high system security in electrically noisy environments Note The automatic start of the Watchdog Timer is only performed if PE SWD is held at high level while HESET or HWPD is active A positive transition at these pins during normal program execution will not start the Watchdog Timer Furthermore when using the hardware start the Watchdog Timer starts running with its default time out period The value in the reload register WDTREL however can be overwritten at any time to set any time out period desired Software Start of the Watchdog Timer The Watchdog Timer can also be started by software This method is compatible to the start procedure in the 80C515 Setting of bit SWDT in SFR IEN1 starts the Watchdog Timer Using the software start the time out period can be programmed before Watchdog Timer starts running Note that once started the Watchdog Timer cannot be stopped by anything but an external hardware reset at pin 10 RESET with a l
56. eeps the part in reset and supplies the internal clock from the RC oscillator Finally when the on chip oscillator has started the oscillator watchdog releases the part from reset with oscillator watchdog status flag set When automatic start of the watchdog was enabled PE SWD connected to the Watchdog Timer will start too with its default reload value for time out period The Reset pin overrides the Hardware Power Down function i e if reset gets active during Hardware Power Down it is terminated and the device performs the normal resetfunction Thus pin Reset has to be inactive during Hardware Power Down Mode function Thus pin Reset has to be inactive during Hardware Power Down Mode Semiconductor Group 6 36 SIEMENS 80C515A 83C515A 5 Table 5 Status of all pins during Idle Mode Power Down Mode and Hardware Power Down Mode Pins Idle Mode Power Down Mode Hardware Power Last instruction Last instruction Down executed from executed from internal external internal external Status ROM ROM ROM ROM PO Data float Data float P1 Data Dat Data Data floating alt outputs alt outputsa last outputs last outputs P2 Data Address Data Data P3 Data Data Data Data outputs alt outputs alt outputs last output last output P4 Data Data Data Data disabled alt outputs outputs last outputs last output P5 Data Data Data Data input
57. eriod the converter is susceptable to spikes and noise at the analog input which may cause wrong codes at the digital outputs Therefore RC filtering at the analog inputs is recommended see figure below Conversion of the sampled analog voltage takes place between the 4th an 14th clock cycle R Analog Input Te 80 515 83C515A 5 1000 1 100 nF ceramic MCB02307 Figure 5 3 Recommended RC Filtering at the Analog Inputs Semiconductor Group 5 7 SIEMENS On Chip Peripheral Components 5 2 New Baud Rate Generator for Serial Channel The Serial Channel has a new baud rate generator which provides greater flexibility and better resolution It substitutes the 80C515 s baud rate generator at the Serial Channel which provides only 4 8 kBaud or 9 6 kBaud at 12 MHz crystal frequency Since the new generator offers greater flexibility it is often possible to use it instead of Timer1 which is then free for other tasks Figure 5 3 shows a block diagram of the new baud rate generator for the Serial Channel It consists of a free running 10 bit timer with fosc 2 input frequency On overflow of this timer there is an automatic reload from the registers SRELL address and SRELH address The lower 8 bits of the timer are reloaded from SRELL while the upper two bits are reloaded from bit 0 and 1 of register SRELH The baud rate timer is reloaded by writing to SRELL SREL
58. ermore the status flag OWDS 0 7 is set if the oscillator watchdog was active The status flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog The flag OWDS can be set or cleared by software An external reset request however also resets OWDS and WDTS Semiconductor Group 5 19 SIEMENS High Performance SAB 80C515A 83C515A 5 8 Bit CMOS Single Chip Microcontroller Preliminary SAB 83C515A 5 Microcontroller with factory mask programmable ROM SAB 80C515A Microcontroller for external ROM e SAB 80C515A 83C515A 5 up to 18 MHz operation frequency e 32 Kx 8 ROM SAB 83C515A 5 only ROM Protection available e 256 x 8 on chip RAM Additional 1 K x 8 on chip RAM XRAM Superset of SAB 80C51 architecture 1 us instruction cycle time at 12 MHz 666 ns instruction cycle time at 18 MHz 256 directly addressable bits Boolean processor 64 Kbyte external data and program memory addressing Three 16 bit timer counters Versatile fail safe provisions Twelve interrupt vectors four priority levels selectable Genuine 10 bit A D converter with 8 multiplexed inputs Full duplex serial interface with programmable Baudrate Generator Functionally compatible with SAB 80C515 Extended power saving mode Fast Power On Reset Seven ports 48 I O lines 8 input lines Two temperature ranges available 0 to 70 C T1 40 to 85 C Plastic packages P LCC 68 and P MQFP 80 The S
59. ers the Hardware Power Down Mode as mentioned above this is independent of the state of pin PE SWD HWPD is sampled once per machine cycle If it is found active the device starts a complete internal reset sequence This takes two machine cycles all pins have their default reset states during this time This reset has exactly the same effects as a hardware reset i e especially the watchdog timer is stopped and its status flag WDTS is cleared In this phase the power consumption is not yet reduced After completion of the internal reset both oscillators of the chip are disabled the on chip oscillator as well as the oscillator watchdog s RC oscillator At the same time the port pins and several control lines enter a floating state as shown in table 4 1 In this state the power consumption is reduced to the power down current Ipp Also the supply voltage be reduced Table 4 1 also lists the voltages which may be applied at the pins during Hardware Power Down Mode without affecting the low power consumption Semiconductor Group 4 1 SIEMENS System Reset Table 4 1 Status of all Pins During Hardware Power Down Mode Pins Status Voltage Range at Pin During HW Power Down PO P1 P2 P3 P4 P5 6 Floating outputs Disabled input function Vss lt Vin lt Active input Vin Voc or Vin Vas PE SWD Active input Pull up resistor Vin Voc Ot Vin Vss Disabled during HW po
60. evertheless an access from internal ROM to external ROM is possible To verify the read protected ROM Code a special ROM Verify Mode is implemented This mode also can be used to verify unprotected internal ROM ROM Protection ROM Verification Mode Restrictions see AC Characteristics no ROM Verification Mode 1 standard 8051 Verification Mode ROM Verification Mode 2 yes ROM Verification Mode 2 standard 8051 Verification Mode is disabled externally applied MOVC accessing internal ROM is disabled Semiconductor Group 6 13 SIEMENS SAB 80C515A 83C515A 5 Data Memory Data Space The data memory space consists of an internal and an external memory space The SAB 80C515A contains another 1 Kbyte on On Chip RAM additional to the 256 bytes internal RAM of the base type SAB 80C515 This RAM is called XRAM extended in this document External Data Memory Up to 64 Kbyte external data memory can be addressed by instructions that use 8 bit or 16 bit indirect addressing For 8 bit addressing instructions in combination with registers RO and R1 can be used A 16 bit external memory addressing is supported by a 16 bit datapointer Registers XPAGE and SYSCON are controlling whether data fetches at addresses F800 to are done from internal XRAM or from external data memory Internal Data Memory The internal data memory is divided into four physically distinct blocks
61. g a MOVX access depends on the control bits in register SYSCON and on the state of pin EA The table 1 lists the various operating conditions It shows the following characteristics a Use of PO and P2 pins during the MOVX access Bus The pins work as external address data bus If internal XRAM is accessed the data written to the XRAM can be seen on the bus in debug mode 0 The pins work as Input Output lines under control of their latch b Activation of the RD and WR pin during the access C Use of internal or external XDATA memory The shaded areas describe the standard operation as each 80C51 device without on chip XRAM behaves Semiconductor Group 6 18 80 515 83 515 5 SIEMENS 608 01 pee pesn 2 pon pesn WWHX 9 pesn WWHX 9 9 9 iat HM AH a q obed 0 1 lt geg HM CH 9 0 1 lt eeg eed ppe sng od e 5 9 0 e 0 l4 Zd 0d e sng od e Sna8 ced od e snae ed od e WVHX pesn pesn pesn pesn pesn pesn SI 2 SI 1 2 SI 2 s xe o s 1 2 s 1
62. g to other functional blocks 3 X means that the value is indeterminate and the location is reserved Semiconductor Group SIEMENS SAB 80C515A 83C515A 5 Table 3 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset Ports PO Port 0 80 OFFy 1 Port 1 90 OFF P2 Port 2 OAO 1 OFF P3 Port 3 1 OFF P4 Port 4 OE8 OFF P5 Port 5 8 OFF P6 Port 6 Analog Digital Input ODBy Pow Sav M Power Control Register 87 00 Serial ADCONO 2 A D Converter Control Reg 00 Channels PCON 2 Power Control Register 87 SBUF Serial Channel Buffer Reg 99 0XX 3 SCON Serial Channel Control Reg 98 00 SRELL Serial Channel Reload AAH D94 low byte SRELH Serial Channel Reload Reg XXXX XX1 1p 3 high byte Timer 0 TCON Timer Control Register 88 1 THO Timer 0 High Byte 8 00H 1 Timer 1 High Byte 8Dy 00 TLO Timer 0 Low Byte 00 TL1 Timer 1 Low Byte 8 00H TMOD Timer Mode Register 89 00 Watchdog IENO 2 Interrupt Enable Register 0 004 IEN1 2 Interrupt Enable Register 1 0B8 1 00 IPO 2 Interrupt Priority Register 0 OAS 00 2 Interrupt Priority Register 1 OB9y XX00 0000pg WDTREL Watchdog Timer Reload Reg 86 00 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits
63. ger input CLKOUT P1 6 system clock output T2 P1 7 counter 2 input XTAL2 39 36 XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits Semiconductor Group 6 8 SIEMENS SAB 80C515A 83C515A 5 Pin Definitions and Functions cont d Pin P MQFP 80 Pin P LCC 68 Symbol Input 1 Output O Function XTAL1 40 37 XTAL1 Output of the inverting oscillator amplifier To drive the device from an external clock source XTAL2 should be driven while XTAL 1 is left unconnected There are no require ments on the duty cycle of the external clock signal since the input to the internal clok king circuitry is divided down by a divide by two flip flop Minimum and maximum high and low times and rise fall times specified in the AC characteristics must be taken into account P2 0 P2 7 41 48 38 45 I O Port 2 is an 8 bit bidirectional I O port with internal pullup resistors Port 2 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 2 pins being externally pulled low will source current in the DC characteristics because of the internal pullup resistors Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this app
64. iconductor Group 6 14 SIEMENS SAB 80C515A 83C515A 5 Accesses to XRAM Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM Note reset occurs during a write operation to the effect XRAM depends on the cycle which the reset is detected at MOVX is 2 cycle instruction Reset detection at cycle 1 new value will not be written to XRAM The old value is not affected Reset detection at cycle 2 The old value in XRAM is overwritten by the new value Accesses to XRAM using the DPTR There are a Read and a Write instruction from and to XRAM which use one of the 16 bit DPTR for indirect addressing The instructions are MOVXA QDPTR Read MOVX A Write Normally the use of these instructions would use a physically external memory However in the SAB 80C515A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM address space DPTR gt F800 Accesses to XRAM using the Registers RO R1 The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8 bit address indirect addressing with registers RO or R1 The instructions are MOVX A Ri Read MOVX Ri A Write In application systems either a real 8 bit bus with 8 bit address is used or Port 2 serves as page register which selects pages of 256 byte However the distinction whether Port
65. l Components 5 3 1 Programmable Watchdog Timer To protect the system against software upset the user s program has to clear the watchdog within a previously programmed time period If the software fails to do this periodical refresh of the Watchdog Timer an internal hardware reset will be initiated The software can be designed such that the watchdog times the if the program does not work properly It also times out if a software error is based on hardware related problems The Watchdog Timer in the SAB 80C515A is a 15 bit timer which is incremented by a count rate of either foycre 2 32 fosc 12 That is the machine clock is divided by a series of arrangement of two prescalers a divide by two and a divide by 16 prescaler see figure 5 6 The latter is enabled by setting bit WDTREL 7 WDT Reset Request IPO 049 External HW Reset O n External HW Power Down PE SWD a WDTREL 02281 Control Logic 5 fenos coas _______ 08 Figure 5 6 Block Diagram of the Programmable Watchdog Timer Semiconductor Group 5 12 SIEMENS On Chip Peripheral Components Special Function Register WDTREL Address 0864 7 6 5 4 3 2 1 0 086 Watchdog Timer Reload Register WDTREL Bit Function WDTREL 7 Prescaler select bit When set the watchdog timer is clocked through an additional divide
66. l operating modes If pin HWPD gets active low level the part enters the Hardware Power Down Mode this is independent of the state of pin PE SWD HWPD is sampled once per machine cycle If it is found active the device starts a complete internal reset sequence The watchdog timer is stopped and its status flag WDTS is cleared exactly the same effects as a hardware reset In this phase the power consumption is not yet reduced After completion of the internal reset both oscillators of the chip are disabled At the same time the port pins and several control lines enter a floating state as shown in table 5 In this state the power consumption is reduced to the power down current IPD Also the supply voltage can be reduced Table 5 also lists the voltages which may be applied at the pins during Hardware Power Down Mode without affecting the low power consumption Termination of HWPD Mode This power down state is maintained while HWPD is held active If HWPD goes to high level inactive state an automatic start up procedure is performed First the pins leave their floating condition and enter their default reset state as they had immediately before going to float state Both oscillators are enabled The oscillator watchdog s RC oscillator starts up very fast typ less than 2 ms Because the oscillator watchdog is active it detects a failure condition if the on chip oscillator hasn t yet started Hence the watchdog k
67. lator watchdog during the power up sequence The external reset signal must be hold active at least until the on chip oscillator has started and the internal watchdog reset phase is completed An external reset time of more than 50 us should be sufficient in typical applications If only a capacitor at pin Reset is used a value of less than 100 nF provides the desired reset time Semiconductor Group 4 9 System Reset SIEMENS 90620124 se o 2 89 250 Aq DUBIsjesay aouenbes sl Jo esnpoeq j8sey sr gj dA jesay ul 1010 1250 Jo 1104 9149 0 UQ JeMod i 4104 0 J858 10 19S0 9Y 22019 josey jepun spod 4 10 Power on of the SAB 80 515 Semiconductor Group Figure 4 4 SIEMENS On Chip Peripheral Components 5 On Chip Peripheral Components Digital Port Circuitry To realize the Hardware Power Down Mode with floating Port pins the SAB 80C515A 83C515A 5 the standard port structure used in the 8051 Family is modified figure 5 1 The FETs p4 p5 and n2 are added During Hardware Power Down this FETs disconnect the port pins from internal logic Vec e us 21 p2
68. lication it uses strong internal pullup resistors when issuing 1 s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 issues the contents of the P2 special function register 49 47 The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations It is activated every six oscillator periods except during external data memory accesses The signal remains high during internal program execution ALE 50 48 The Address Latch enable output is used for latching the address into external memory during normal operation It is activated every six oscillator periods except during an external data memory access Semiconductor Group 6 9 SIEMENS 80C515A 83C515A 5 Pin Definitions and Functions cont d Symbol Pin P LCC 68 Pin P MQFP 80 Input 1 Output O Function EA 51 49 External Access Enable When held high the SAB 80C515A executes instructions from the internal ROM as long as the PC is less than 32768 When held low the SAB 80C515A fetches all instructions from external program memory For the SAB 80C515A this pin must be tied low P0 0 P0 7 52 59 52 59 I O Port 0 is an 8 bit open drain bidirectional I O port Port 0 pins that have 1 s written to them float and in that state can be used as high impedance inputs Port 0 is also the
69. llator s frequency if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit the internal clock is supplied by the RC oscillator and the device is brought into reset if the failure condition disappears i e the on chip oscillator has a higher frequency than the RC oscillator the part executes a final reset phase of appr 0 5 ms in order to allow the oscillator to stabilize then the oscillator watchdog reset is released and the part starts program execution again Restart from the Hardware Power Down Mode If the Hardware Power Down Mode is terminated the oscillator watchdog has to control the correct start up of the on chip oscillator and to restart the program The oscillator watchdog function is only part of the complete Hardware Power Down sequence however the watchdog works identically to the monitoring function The Hardware Power Down Mode is discussed in detail in section 4 1 4 2 Fast internal reset after power on In this function the oscillator watchdog unit provides a clock supply for the reset before the on chip oscillator has started In this case the oscillator watchdog unit also works identically to the monitoring function The power on is described in section 4 3 Note The oscillator watchdog unit is always enabled Semiconductor Group 5 17 SIEMENS On Chip Peripheral Components Detailed Description of the Oscillator Watchdog Unit Figure 5 8 shows the block diagram of the osci
70. llator watchdog unit It consists of an internal RC oscillator which provides the reference frequency for the comparison with the frequency of the on chip oscillator RC Oscillator Rc f OWE 415 c Enable 22 Frequency f Delay B Comparator Int XTAL1 Reset PO 0A9 4 XTAL2 0 0 Z i Int Clock MCS02247 Figure 5 8 Oscillator Watchdog Unit Special Function Register IPO Address Bit LSB 7 6 5 4 3 2 1 0 0864 OWDS WDTS 1 0 5 0 4 0 2 0 1 0 0 These bits are not used for Watchdog Timer Bit Function OWDS Oscillator watchdog timer status flag Set by hardware when an oscillator watchdog reset occurred Can be cleared and set by software Reset value of IPO is 00 Semiconductor Group 5 18 SIEMENS On Chip Peripheral Components The frequency coming from the RC oscillator is divided by 5 and compared to the on chip oscillator s frequency If the frequency coming from the on chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition the oscillation at the on chip oscillator could stop because of crystal damage etc In this case it switches the input
71. multiplexed low order address and data bus during accesses to external program and data memory In this application it uses strong internal pullup resistors when issuing 1 s Port 0 also outputs the code bytes during program verification in the SAB 80C515A External pullup resistors are required during program verification 5 7 5 0 60 67 68 60 67 69 I O Port 5 is an 8 bit bidirectional I O port with internal pullup resistors Port 5 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 5 pins being externally pulled low will source current jj in the DC characteristics because of the internal pullup resistors Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the SAB 80C515A A low level for a longer period will force the part to Power Down Mode with the pins float ing see table 5 37 32 33 Supply voltage during normal idle and power down operation 38 34 35 Ground 0 V 2 13 14 23 46 50 51 68 70 71 Not connected These pins of the P MQFP 80 package must not be connected Semiconductor Group 6 10 SIEMENS SAB 80C515A 83C515A 5 7 7 Oscillator ROM wu 299697 2568 1Kx8 SAB OSC amp 83C515A 5 Timing only
72. nal input port to the A D converter Port pins can be used for digital input if voltage levels simultaneously meet the specifications high low input voltages and for the eight multiplexed analog inputs P3 0 P3 7 21 28 15 22 I O Port 3 is an 8 bit bidirectional I O port with internal pullup resistors Port pins that 1 5 written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 3 pins being externally pulled low will source current in the DC characteristics because of the internal pullup resistors Port 3 also contains the interrupt timer serial port and external memory strobe pins that are used by various options The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 3 as follows RxD P3 0 serial port s receiver data input asynchronous or data input output Synchronous TxD P3 1 serial port s transmitter data output asynchronous or clock output synchronous INTO P3 2 interrupt 0 input timer 0 gate control input NT1 P3 3 interrupt 1 input timer 1 gate control input P3 4 counter 0 input 1 P3 5 WR P3 6 counter 1 input the write control signal latches the data byte from port 0 into the external data memory RD P3 7 the read contr
73. nversion is selected If cleared the converter stops after one conversion MX2 Select 8 input channels of the ADC Bits to MX2 can be written or read either in ADCONO or in ADCON1 ADCL ADC Clock When set fosc 16 Has to be set when fosc gt 16 MHz The reset value of ADCONO ADCON1 is 00 Semiconductor Group SIEMENS On Chip Peripheral Components Special Function Register ADDATH ADDATL MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr msb ADDAT MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr ODAH Ibs ADDATL These bits are not used for conversion result The reset value of and ADDATL is The registers OD9 4 and ADDATL contain the 10 bit conversion result The data is read as two 8 bit bytes Data is presented in left justified format i e the msb is the most left hand bit in a 16 bit word To get a 10 bit conversion result two READ operations are required Otherwise ADDAT contains the 8 bit conversion result Semiconductor Group 5 6 SIEMENS On Chip Peripheral Components A D Converter Timing After a conversion has been started by a write to ADDATL external start by P4 0 ADST or in continuous mode the analog input voltage is sampled for 4 clock cycles The analog source must be capable of charging the capacitor network of appr 50 pF to full accuracy in this time During this p
74. of the internal clock system to the output of the RC oscillator This means that the part is being clocked even if the on chip oscillator has stopped or has not yet started At the same time the watchdog activates the internal reset in order to bring the part in its defined reset state The reset is performed because clock is available from the RC oscillator This internal watchdog reset has the same effects as an externally applied reset signal with the following exceptions The Watchdog Timer Status flag WDTS 0 6 is not reset the Watchdog Timer however is stopped and bit OWDS is set This allows the software to examine error conditions detected by the Watchdog Timer even if meanwhile an oscillator failure occurred The oscillator watchdog is able to detect a recovery of the on chip oscillator after a failure If the frequency derived from the on chip oscillator is again higher than the reference the watchdog starts a final reset sequence which takes typ 1 ms Within that time the clock is still supplied by the RC oscillator and the part is held in reset This allows a reliable stabilization of the on chip oscillator After that the watchdog toggles the clock supply back to the on chip oscillator and releases the reset request If no external reset is applied in this moment the part will start program execution If an external reset is active however the device will keep the reset state until also the external reset request disappears Furth
75. ol signal enables the external data memory to port 0 Semiconductor Group 6 7 SIEMENS SAB 80C515A 83C515A 5 Pin Definitions and Functions cont d Symbol P LCC 68 Pin P MQFP 80 Input 1 Output O Function 7 29 36 24 31 I O Port 1 is 8 bit bidirectional I O port with internal pullup resistors Port 1 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 1 pins being externally pulled low will source current in the DC characteristics because of the internal pullup resistors The port is used for the low order address byte during program verification Port 1 also contains the interrupt timer clock capture and compare pins that are used by various options The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate except when used for the compare functions The secondary functions are assigned to the port 1 pins as follows P1 0 interrupt 3 input compare 0 output capture 0 input INT4 CC1 P1 1 interrupt 4 input compare 1 output capture 1 input INT5 CC2 P1 2 interrupt 5 input compare 2 output capture 2 input INT6 CC3 P1 3 interrupt 6 input compare 3 output capture 3 input INT2 P1 4 interrupt 2 input 2 P1 5 timer 2 external reloadtrig
76. ompare capture and reload functions Corresponding to the 16 bit timer register there are four 16 bit capture compare registers one of them can be used to perform a 16 bit reload on a timer overflow or external event Each of these registers corresponds to a pin of port 1 for capture input compare output Figure 4 shows a block diagram of timer counter 2 Reload A 16 bit reload can be performed with the 16 bit CRC register consisting of CRCL and CRCH There are two modes from which to select Mode 0 Reload is caused by a timer 2 overflow auto reload Mode 1 Reload is caused in response to a negative transition at pin T2EX P1 5 which can also request an interrupt Semiconductor Group 6 27 SIEMENS SAB 80C515A 83C515A 5 Capture This feature permits saving of the actual timer counter contents into a selected register upon an external event or a software write operation Two modes are provided to latch the current 16 bit value of timer 2 registers TL2 and TH2 into a dedicated capture register Mode 0 Capture is performed in response to a transition at the corresponding port 1 pins CCO to Mode 1 Write operation into the low order byte of the dedicated capture register causes the timer 2 contents to be latched into this register Compare In compare mode the 16 bit values stored in the dedicated compare registers are compared to the contents of the timer 2 registers If the count value in the timer 2 registers m
77. on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0 9 specification when the address lines are stabilizing Ipp Software Power Down Mode is measured under following conditions EA RESET Port0 XTAL1 N C XTAL2 Vas PE SWD Vas HWPD V ss Varet all other pins disconnected Ipp Hardware Power Down Mode independent of any particular pin connection Icc active mode is measured with XTAL2 driven with CH CHCL 5 ns ViL Vss 0 5 0 5 XTAL1 N C EA PE SWD Voc Voc HWPD Voc RESET all other pins are disconnected would be slightly higher if a crystal oscillator is used ap pr 1 mA Icc Idle mode is measured with all output pins disconnected and with all peripherals dis abled XTAL2 driven with 5 ns 0 5 V 0 5 V XTALI N C RESET HWPD PortO Port6 EA PE SWD all other pins are disconnected slow down mode is measured with all output pins disconnected and with all peripherals disabled XTAL2 driven with CLCH CHCL 5 ns V ss 0 5 0 5 XTAL1 RESET HWPD EA PE SWD Vas all other pins disconnected Max at othe
78. oup SIEMENS System Reset 4 3 Fast Internal Reset after Power On The SAB 80C515A can use the oscillator watchdog unit for a fast internal reset procedure after power on Figure 4 4 shows the power on sequence under control of the oscillator watchdog Normally the devices of the 8051 family like the SAB 80C515 enter their default reset state not before the on chip oscillator starts The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 1ms During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins In the SAB 80C515A the oscillator watchdog unit can avoid this situation In this case after power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 microseconds In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on chip oscillator s output This allows correct resetting of the part and brings also all ports to the
79. ow level on pin 4 PE SWD or a hardware power down at pin 60 HWPD independently of level at PE SWD Semiconductor Group 5 14 SIEMENS On Chip Peripheral Components Refreshing the Watchdog Timer At the same time the Watchdog Timer is started the 7 bit register WDTH is preset by the contents of WDTREL O to WDTREL 6 Once started the Watchdog Timer cannot be stopped by software but be refreshed to the reload value only by first setting bit WDT IENO 6 and by the next instruction setting SWDT IEN1 6 Bit WDT will automatically be cleared during the second machine cycle after having been set This double instruction refresh of the Watchdog Timer is implemented to minimize the chance of an unintentional reset of the watchdog unit The reload register WDTREL can be written at any time as already mentioned Therefore a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the Watchdog Timer Thus a wrong reload value caused by a possible distortion during the write operation to WDTREL can be corrected by software Watchdog Reset and Watchdog Status Flag WDTS If the software fails to clear the watchdog in time an internally generated watchdog reset is entered at the counter state 7FFCH The duration of the reset signal then depends on the prescaler selection either 8 or 128 cycles This internal reset differs from an external one in so far as the Watchdog Timer is not disabled and bit WDTS is
80. p3 p4 e i 2 Port _ 0 5 Input Data Read Pin 1 HWPD MCB02252 Figure 5 1 Port Structure Semiconductor Group 5 1 SIEMENS On Chip Peripheral Components P1 and p3 are not active during Hardware Power Down 1 is activated only for two oscillator periods if a 0 1 transition is programmed to the port pin not possible during HWPD P3 is turned off during reset state also HWPD For detailed description of the port structure please refer to the SAB 80C515 80C535 User s Manual Semiconductor Group 5 2 On Chip Peripheral Components SIEMENS 5 1 10 Bit A D Converter In the SAB 80C515A a new high performance high speed 8 channel 10 bit A D Converter is implemented Its successive approximation technique provides 7 us conversion time fosc 16 MHz The conversion principle is upward compatible to the one used the SAB 806515 The major components are shown in figure 5 1 The comparator is a fully differential comparator for a high power supply rejection ratio and very low offset voltages The capacitor network is binary weighted providing 10 bit resolution The table below shows the sample time 7 and the conversion time including Ts which depend fosc and the selected prescaler see also Bit ADCL in SFR ADCON 1 fos MHz Prescaler MHz Ts us us incl Ts 12 8 1
81. r frequencies is given by active mode cc 1 5 fosc 8 idle mode cc 0 4 fosc 7 where fosc is the oscillator frequency in MHz Icc values are given in mA and measured at 5 V Semiconductor Group 6 45 SIEMENS SAB 80C515A 83C515A 5 A D Converter Characteristics 5 10 15 20V VAREF 5 VAGND 0 2 V Oto 70 C for the SAB 80 515 83 515 5 T a 40 to 85 for the SAB 80C515A T3 83C515A 5 T3 Parameter Symbol Limit values Unit Test condition min typ max Analog input capacitance 25 70 pF Sample time Ts 4tcy Jus 2 inc load time Conversion time To 14 toy Jus 9 inc sample time Total unadjusted error TUE 2 LSB Vangr Voc VaGND Vss Varer Supply current IREF 20 1 so ADCL DCL Ne 8 2 fosc tcv fane fosc 8 2 This parameter specifies the time during the input capacitance C can be charged discharged by the external source It must be guaranteed that the input capacitance is fully loaded within this time 4 is 2 us at the fogc 16 MHz After the end of the sample time Ts changes of the analog input voltage have no effect on the conversion result 9 This parameter includes the sample time 14TCY is 7 us at fosc 16 MHz Semiconductor Group 6 46 SIEMENS SAB 80C515A 83C515A 5 AC Characteristics 5
82. rchitectural and operational characteristics of the SAB 80C515 the SAB 80C515A incorporates more on chip RAM A new 10 bit A D Converter is implemented as well as an oscillator watchdog unit Also the operating frequency is higher than at the SAB 80C515 XRAM SAB gt Oscillator Watchdog HW Power Down CPU 1 0 Mod B0C51 Core ode 0 Slow Down zm Mode ROM 8k x 8 ROM Protection available Port 5 SS 0 Analog 1 0 1 0 ROM Digital 2 x 8 Input ROM Protection available Shaded areas meaning improved functionality 01560 80C515A 83C515A 5 Semiconductor Group 1 1 SIEMENS Introduction The SAB 80C515A is available in two different versions ROMless Version SAB 80C515A Although this part is called ROMless there is an internal ROM of 2 KByte for Test and Loader Software ROM Version SAB 83C515A 5 This part has 32 KByte on chip ROM With exception of the ROM sizes both parts are identical Therefore the term SAB 80C515A refers to both versions within this specification unless otherwise noted This manual describes only the new features of the SAB 80C515A in addition to the features of the SAB 80C515 80C535 For reference to the SAB 80C515 the user s manual should be used Listed below is a summary of the main features of the SAB 80C515A SAB 80C515A 83C515A 5 up to 12 interrupt vectors four priority levels 18 MHz operation frequency selectable e 3
83. reserved XXH 2 CCH2 00H 5 reserved XXH CCL3 00H reserved XXH 2 C7y CCH3 00H E7y reserved XXH T2CON 00H E8y P4 reserved XXH 2 E9H reserved XXH CAH CRCL 00H EAH reserved XXH 2 CBH CRCH reserved XXH CCH TL2 00H ECH reserved XXH 2 CDH TH2 00H EDH reserved XXH CEH reserved XXH 2 EEH reserved XXH 2 CFH reserved XXH 2 EFH reserved XXH DOW PSW 1 00H 00 Diy reserved XXH reserved XXH 2 reserved XXH 2 F2y reserved XXH 2 D3y reserved XXH F3H reserved XXH D4y reserved XXH 2 reserved XXH 2 D5y reserved XXH 5 reserved XXH reserved XXH 2 F6H reserved XXH 2 D7y reserved XXH F7H reserved XXH D84 ADCONO 00H F8y P5 D9H ADDATH 00H 9 reserved XXH DAH ADDATL 00H FAH reserved XXH 2 DBH P6 XXH FBH DCH 1 XXXX0000g 2 DDH reserved XXH FDH DEH reserved XXH 2 FEH DFH reserved XXH FFH 1 Bit addressable Special Function Register 2 X means that the value is indeterminate and the location is reserved Semiconductor Group SIEMENS Memory Organization Table 3 2 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC Accumulator 00H B B Register 00H DPH Data Pointer High Byte 83H DPL Data Pointer Low Byte 82 00H PSW Program Status Word Register 00 SP Stack Pointer 81H 07H
84. rformed where the upper address byte is provided by P2 and not by XPAGE Therefore the software has to distinguish two cases if the MOVX Ri instructions with paging shall be used a Access to XRAM The upper address byte must be written to XPAGE or P2 both writes selects the XRAM address range b Access to external memory The upper address byte must be written to P2 XPAGE will be loaded with the same address in order to deselect the XRAM The behaviour of Port2 and the RD WR signals depends on the state of pin EA and on the control bits XMAPO and in register SYSCON Semiconductor Group 3 13 SIEMENS Memory Organization 3 4 2 Control of XRAM in the SAB 80C515A There are two control bits in register SYSCON which control the use and the bus operation during accesses to the additional On Chip RAM XDATA range XRAM Special Function Register SYSCON MSB LSB Bit No 7 6 5 4 3 2 1 0 Addr 0B1 yy XMAP1 XMAPO SYSCON Bit Function XMAPO Global enable disable bit for XRAM memory 0 The access to XRAM XDATA memory is enabled 1 The access to RAM is disabled All MOVX accesses are perfor med by the external bus This bit is hardware protected XMAP1 Control bit for RD WR signals during accesses to this bit has no effect if XRAM is disabled XMAPO 1 or if addresses outside the XRAM address range are
85. rrupt This interrupt will be serviced and the instruction to be executed following the RETI instruction will be the one following the instruction that set the bit IDLS The other way to terminate the idle mode is a hardware reset Since the oscillator is still running the hardware reset must be held active only for two machine cycles for a complete reset Normally the port pins hold the logical state they had at the time idle mode was activated If some pins are programmed to serve their alternate functions they still continue to output during idle mode if the assigned function is on The control signals ALE and PSEN hold at logic high levels see table 5 Semiconductor Group 6 35 SIEMENS SAB 80C515A 83C515A 5 Software Power Down Mode The power down mode is entered by two consecutive instructions directly following each other The first instruction has to set the flag PDE power down enable and must not set PDS power down set The following instruction has to set the start bit PDS Bits PDE and PDS will automatically be cleared after having been set The instruction that sets bit PDS is the last instruction executed before going into power down mode The only exit from power down mode is a hardware reset The status of all output lines of the controller can be looked up in table 5 Hardware Controlled Power Down Mode The pin HWPD controls this mode If it is on logic high level inactive the part is running in the norma
86. s first a failure and then a recovering of the oscillator during normal operation Therefore also the oscillator watchdog status flag is set after restart from Hardware Power Down Mode When automatic start of the watchdog was enabled PE SWD connected to the Watchdog Timer will start too with its default reload value for time out period SWD Function of the PE SWD Pin is sampled only by a hardware reset Therefore at least one Power On Reset has to be performed Semiconductor Group 4 3 SIEMENS System Reset 4 2 Hardware Power Down Reset Timing Following figures are showing the timing diagrams for entering figure 4 1 and leaving figure 4 2 the Hardware Power Down Mode If there is only a short signal at pin HWPD i e HWPD is sampled active only once then a complete internal reset is executed Afterwards the normal program execution starts again figure 4 3 Note Delay time caused by internal logic is not included The Reset pin overrides the Hardware Power Down function i e if reset gets active during Hardware Power Down it is terminated and the device performs the normal reset function Thus pin Heset has to be inactive during Hardware Power Down Mode Semiconductor Group 4 4 System Reset SIEMENS 0 c019A uoljduinsuoy 0104990 gt lt eouenbeg pie DUON S efus E IR in 250 diu5 uo i 5110 9404
87. set Figure 5 6 shows a block diagram of all reset requests in the SAB 80C515A and the function of the watchdog status flag The WDTS is a flip flop which is set by a Watchdog Timer reset and can be cleared by an external hardware reset Bit WDTS allows the software to examine from which source the reset was activated The bit WDTS can also be cleared by software SETB Instructions have to be used Semiconductor Group 5 15 SIEMENS On Chip Peripheral Components OWD Reset Request WDT Reset Request SET SET IPO 049 Internal Reset jowos wors Synchro CLEAR nisator RESET External HW Reset Request External HW Power Down Request Y Internal Bus MCA02278 Figure 5 7 Watchdog Status Flags and Reset Requests Special Function Register IPO Address 9 Bit No MSB LSB 7 6 5 4 3 2 1 0 0864 OWDS WDTS 1 0 5 0 4 0 2 IPO 1 0 0 These bits are not used for Watchdog Timer Bit Function WDTS Watchdog timer status flag Set by hardware e when a Watchdog Timer reset occurred Can be cleared and set by software Reset value of IPO is 00 Semiconductor Group 5 16 SIEMENS On Chip Peripheral Components 5 3 2 Oscillator Watchdog Unit The unit serves three functions Monitoring of the on chip oscillator s function The watchdog supervises the on chip osci
88. t a programmable 9th and a stop bit 1 In fact mode 3 is the same as mode 2 in all respects except the baud rate The baud rate in mode 3 is vari able Variable Baud Rates for Serial Interface Variable baud rates for modes 1 and 3 of serial interface can be derived from either timer 1 or a new dedicated Baudrate Generator The baud rate is generated by a free running 10 bit timer with programmable reload register 2 SMOD fosc 64 21 SREL Mode 1 3 baud rate The default value after reset in the reload registers SRELL and SRELH provides a baud rate of 4 8 kBaud SMOD 0 or 9 6 kBaud SMOD 1 at 12 MHz oscillator frequency This guaran tees full compatibility to the SAB 80C515 Semiconductor Group 6 39 SIEMENS SAB 80C515A 83C515A 5 Fail Safe Units The SAB 80C515A offers enhanced fail safe mechanisms which allow an automatic recovery from software upset or hardware failure a programmable watchdog timer WDT with variable time out period from 512 us up to appr 1 1 s 12 MHz Upward compatible to 80C515 watchdog timer an oscillator watchdog OWD which monitors the on chip oscillator and forces the microcontroller into reset state in case the on chip oscillator fails it also controls the restart from the Hardware Power Down Mode and provides the clock for a fast internal reset after power on Programmable Watchdog Timer The WDT can be activated by hardware or software Hardware
89. ther functional blocks 3 X means that the value is indeterminate and the location is reserved Semiconductor Group SIEMENS Memory Organization 3 4 Architecture of the XRAM The contents of the XRAM is not affected by a reset or HW Power Down After power up the contents is undefined while it remains unchanged during and after a reset or HW Power Down if the power supply is not turned off The additional On Chip RAM is logically located in the external data memory range at the upper end of the 64 KByte address range 800 FBFF Nevertheless when XRAM is enabled the address range F800 to FFFFy is occupied This is done to assure software compatibility to SAB 80C517A It is possible to enable and disable only by reset the XRAM If it is disabled the device shows the same behaviour as the parts without XRAM i e all MOVX accesses use the external bus to physically external data memory 3 4 1 Accesses to XRAM Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM Note If a reset occurs during a write operation to XRAM the effect on XRAM depends on the cycle which the reset is detected at MOVX is a 2 cycle instruction Reset detection at cycle 1 The new value will not be written to XRAM The old value is not affected Reset detection at cycle 2 The old value in XRAM is overwritten by the new value Accesses to XRAM using the DPTR Ther
90. uctor Group Siemens AG is an approved CECC manufacturer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of transport For packing material that is returned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs in curred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the express written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support device or system or to affect its safety or effectiveness of that device or system 2 Life support devices or systems are intended a to be implanted in the human body or b to support and or maintain and sustain hu man life If they fail it is reasonable to assume that the health of the user may be endangered SIEMENS SAB 80C515A 83C515A Table of Contents Page 1 coun ie vee 1 1 2 Fundamental Structure 2 1 3 Memory Organization
91. upt IEX2 004By External interrupt 2 IEX3 0053 External interrupt 3 IEX4 005 External interrupt 4 IEX5 0063 External interrupt 5 IEX6 006B External interrupt 6 Each interrupt vector can be individually enabled disabled The minimum response time to an interrupt request is more than 3 machine cycles and less than 9 machine cycles if no other interrrupt of the same or a higher priority level is in process Figure 5 shows the interrupt request sources External interrupts 0 and 1 can be activated by a low level or a negative transition selectable at their corresponding input pin external interrupts 2 and 3 can be programmed for triggering on a negative or a positive transition The external interrupts 3 or 6 are combined with the corresponding alternate functions compare output and capture input on port 1 For programming of the priority levels the interrupt vectors are combined to pairs Each pair can be programmed individually to one of four priority levels by setting or clearing one bit in special function register IPO and one in IP1 Figure 6 shows the priority level structure Semiconductor Group 6 30 SIEMENS SAB 80C515A 83C515A 5 P3 2 INTO TIMER 0 Overflow P3 3 INT1 TIMER 1 Overflow Receiver SERIAL PORT Transmitter TIMER 2 Overflow P1 5 T2EX INI EXEN2 A D Converter u P1 4 INT2 Interrupt Control
92. used for MOVX accesses XMAP1 0 The signals RD and WR are not activated during accesses to XRAM XMAP1 1 Ports 0 2 and the signals RD and WR are activated during accesses to XRAM Reset value of SYSCON is 01 The control bit XMAPO is a global enable disable bit for the additional On Chip RAM XRAM If this bit is set the XRAM is disabled all MOVX accesses use external memory via the external bus In this case the 80C515A can t use the additional On Chip RAM and is compatible with the types without XRAM Semiconductor Group 3 14 SIEMENS Memory Organization A hardware protection is done by an unsymmetric latch at XMAPO bit A unintentional disabling of XRAM could be dangerous since indeterminate values could be read from external bus To avoid this the XMAP bit is forced to 1 only by reset Additional during reset an internal capacitor is loaded So the reset state is a disabled XRAM Because of the load time of the capacitor XMAPO bit once written to 0 that is discharging capacitor cannot be set to 1 again by software On the other hand any distortion software hang up noise is not able to load this capacitor too That is the stable status is XRAM enabled The only way to disable XRAM after it was enabled is a reset The clear instruction for the XMAPO bit should be integrated in the program initialization routine before XRAM is used In extremely noisy systems the user may have re
93. values defind ed by the absolute maximum ratings DC Characteristics 5 10 15 0 T a 0 to 70 for the SAB 80 515 T a 40 to 85 C for the SAB 80C515A T3 Parameter Symbol Limit Values Unit Test condition min max Input low voltage Vu 0 5 0 2 exept HWPD 0 1 Input low voltage EA Vint 0 5 0 2 V 0 3 Input low voltage Vito 0 5 0 2 HWPD RESET 0 1 Input high voltage exept Vin 0 2 0 5 XTAL2 HWPD 0 9 Input high voltage to XTAL2 0 7 0 5 V Input high voltage to RESET 2 0 6 0 5 HWPD Semiconductor Group 6 43 SIEMENS SAB 80C515A 83C515A 5 DC Characteristics cont d Parameter Symbol Limit Values Unit Test condition min max Output low voltage VoL 0 45 V 1 6 mA ports 1 2 3 4 5 Output low voltage Voti 2 0 45 V 3 2 mA ports 0 ALE RESET Output high voltage 2 4 V 80 uA ports1 2 3 4 5 0 9 10 uA Output high voltage 2 4 V 800 uA port 0 in external bus mode 0 9 V 80 ALE PSEN Logic 0 input current Iy 10 70 2 ports 1 2 3 4 5 Logical 1 to 0 transition In 65
94. wer down XTAL 1 Active output pin may not be driven XTAL 2 Disabled input function Vas lt PSEN ALE Floating outputs Vas Vin Disabled input function for test modes only Reset Active input must be at high level if Vin HWPD is used Viret ADC reference supply input Vss lt Vin lt Semiconductor Group SIEMENS System Reset The power down state is maintained while pin HWPD is held active If HWPD goes to high level inactive state an automatic start up procedure is performed First the pins leave their floating condition and enter their default reset state as they had immediately before going to float state Both oscillators are enabled While the on chip oscillator with pins XTAL1 and XTAL2 usually needs a longer time for start up if not externally driven with crystal approx 1 ms the oscillator watchdog s RC oscillator has a very short start up time typ less than 2 microseconds Because the oscillator watchdog is active it detects a failure condition if the on chip oscillator hasn t yet started Hence the watchdog keeps the part in reset and supplies the internal clock from the RC oscillator Finally when the on chip oscillator has started the oscillator watchdog releases the part from reset after it performed a final internal reset sequence and switches the clock supply to the on chip oscillator This is exactly the same procedure as when the oscillator watchdog detect
95. with paging shall be used a Access to XRAM The upper address byte must be written to XPAGE or P2 both writes selects the XRAM address range b Access to external memory The upper address byte must be written to P2 XPAGE will be loaded with the same address in order to deselect the XRAM Semiconductor Group 6 16 SIEMENS SAB 80C515A 83C515A 5 Control of XRAM in the SAB 80C515A There are two control bits in register SYSCON which control the use and the bus operation during accesses to the additional On Chip RAM XRAM Special Function Register SYSCON Addr 1 XMAP1 SYSCON Bit Function Global enable disable bit for XRAM memory 0 The access to On Chip XDATA memory is abled 1 The access to XRAM is disabled All MOVX accesses are performed by the external bus reset state 1 Control bit for RD WRsignals during accesses to XRAM this bit has no effect if XRAM is disabled XMAPO 1 or if addresses exceeding the XRAM address range are used for MOVX accesses 1 0 The signals RD and WR are not activated during accesses to XRAM 1 1 The signals RD and WR are activated during accesses to XRAM Reset value of SYSCON is XXXX XX01B The control bit XMAPO is a global enable disable bit for the additional On Chip RAM XRAM If this bitis set the XRAM is disabled all MOVX ac
96. x9 2 0 0 O le 2d 0 O le 2d 0 l4 Zd ppe sng od e sng od e sng od e 0 e sng od e sng od e INVHX gt pesn WWHX 2 pesn pesn s WWHX 2 pesn s WWHX 2 s 9 pesn s WWHX 9 s 9 q geg HM CH q HM OH 4 eeg eed sng 2ed od 5 9 lt 0 e 0 l4 Zd 0d e sng ed od e 5 8 2 0 WVHX Hida pesn pesn pesn pesn pesn pesn s 9 9 s 9 s 9 s 2 s jxe 9 q q q q q ssaippe sng zd od e sng zd od e sng zd od e sng zd od e sng zd od e sng zd od e WVHX gt OL 00 OL 00 Od VINX ld VINX Od VINX Ld VINX 0 Hldao XAOW XA
97. y This guarantees full compatibility to the SAB 80C515 Timer 1 Overflow ADCONO 7 PCON 7 Baud Rate BD SMOD ee 2 M Generator Mode 13 rani _ 2 06072 On Clock 2 MCB02248 Figure 5 5 Block Diagram of Baud Rate Generation for Serial Interface If the new baud rate generator is used the baud rate of the Serial Channel in Mode 1 and 3 can be determined as follows 25 x oscillator frequency Mode 1 3 baud rate with SREL SRELH 1 0 SRELL 7 0 64 x 216 SREL MOD 25 x fosc 64 x baud rate SREL 2 Semiconductor Group 5 10 SIEMENS On Chip Peripheral Components 5 3 Fail Save Mechanisms The SAB 80C515A offers two on chip peripherals which ensure an automatic fail save reaction in cases where the controller s hardware fails or the software hangs up Programmable Watchdog Timer WDT with variable time out period from 512 us to approx 1 1 seconds at 12 MHz The SAB 80C515A s WDT is compatible to the SAB 80C515 s WDT which is not programmable An Oscillator Watchdog OWD which monitors the on chip oscillator and forces the microcontroller into the reset state if the on chip oscillator fails This unit is new in with respect to the SAB 806515 Semiconductor Group 5 11 SIEMENS On Chip Periphera

SAB 80C515A,83C515A-5 - Users Manual

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