PCL-836 Multifunction counter- timer and digital I/O add
Contents
1. PCL 836 Multifunction counter timer and digital I O add on card for PC XT AT and compatibles Copyright This documentation is copyrighted 1997 by Advantech Co Ltd All rights are reserved Advantech Co Ltd reserves the right to make improvements in the products described in this manual at any time without notice No part of this manual may be reproduced copied translated or transmitted in any form or by any means without the prior written permission of Advantech Co Ltd Information provided in this manual is intended to be accurate and reliable However Advantech Co Itd assures no responsibility for its use nor for any infringe ments of the rights of third parties which may result fron its use Acknowledgments PC LabCard is a trademark of Advantech Co Ltd IBM and PC are trademarks of International Business Machines Corporation All brand and product names appearing in this document are registered trade marks or trademarks of their respective holcers Part No 2003836010 2nd Edition Printed in Taiwan May 1997 Contents ee 1 PsP STETOCMICE TON cu atelier 2 1 Z Key Features su ba a i ua a 2 3 Applications serene Bk Sle Boe es SS a 2 l A SPC Sunia a 3 1 5 Block Diagram oooooooooooooooooooo o 4 installati cccccccccansssnaanaaasnannnrrrsrrrrrrrrraasassansunuunarennrrerrrrrrs J Ze LIME MET as tia io 6 2 2 Switch and Jumper Settings oooooooooo 62. 2 After the I O q rations have been done the user has to call Device Close to close this device PCL 836 User s Manual DeviceClose This function resets the PCL 836 to default status Prototype ULONG DeviceClose USHORT DeviceNumber Parameters DeviceNumber The board number of the PCL 836 from 0 9 Returned value 0 Success 1 Invalid device number 4 Lost base address Example error code DeviceClose 3 Chapter 6 PCL 836 Software Driver 33 34 CounterConfig This function configures the counter mode of a specified conter rototype SHORT CounterConfig SHORT DeviceNumber SHORT Counter SHORT CounterEdge FLOAT MaxInFreq ehe Parameters DeviceNumber The board number of PCL 836 from 0 9 Counter he counter number of PCL 836 from 0 5 CounterEdge The cont 0 for positive edge 1 for negative ee MaxInFreq The maximum input frequency of the counter The driverwill automatically set the filter clock according to fMaxInFreq If fVaxInFreg is set to zero the driver will disable the filter function The maximum frequency is 312 kHz Returned value Example error code CounterConfig 3 5 0 1000 Enables the filter function and the maximum input frequency is 1 kHz error _code ComterConfig 3 5 0 0 Disables filter function PCL 836 User s Manual CounterEvent Start This function starts the count
3. by performing a latch operation under the read back command by setting the SC1 and SCO to be advantage of operating several 1 1 and NT 0 This method has the L counters at the same time A suose quent read operation on the sel value PCL 836 User s Manual lected counter will retrieve the held CHAPTER PCL 836 Software Driver The utility disk that came with your PCL 836 card includes same C library files These Libraries were developed using Turbo C and you should ke able to develop your own C applications using these files The source code for the programming Library can also be found on the flogy disk This enables you to reompile the Libraries using any Campiler though same modifications may be necessary Function call descriptions 32 This section gives detailed descriptions of the functions available in the libary files DeviceOpen This function sets the device nunber and base address of the PCL 836 This enables the use of multiple PCL 836 cards Prototype ULONG DeviceOpen USHORT DeviceNumber USHORT BaseAd cess Parameters DeviceNumber The board number of PCL 836 from 0 9 BaseAddress The base address of PCL 836 Returned value 0 success 1 Invalidbase address 2 Invalid device number 3 Device is busy Example error_code DeviosOpen 3 0x200 note 1 The user has to call the DeviceQpen function before the other finc tias
4. Connector Pin Assignments There is one DB 37 connector and two 20 pin male connectors on the PCL 836 The connector CN3 is a counter I O interface while the connector CN1 and CN2 are digital output and digital input respectively CNI Digital output CN2 Digital input CN3 Counter signals and interrupt The following diagrams illustrate the pin assignment of each connec tor Legend GATE Gate of counter CLK Input of counter clock OUT Output of counter PWM PWM out Fout Frequency out DO Digital output DI Digital input INTEN Interrupt enable INT Interrupt input GND Ground Connector CN3 Counter signals and Interrupt Signals cLko o een ar OUTO CLKI 3 o o H GND GATE1 4 o 9 aes OUTI ciko 0 a GND gate 65 0 2 go OUT ciks Lo 9 Fog GND GATES 8 o O fp OUTS GIA o 2 Fog GND GATE4 107 o pg outi ciks H o 2 Mio GND GATES 2 o 9 a OUTS int H o GND pwmo 14 o 132 INTEN pwm2 15 o 9 Ta EMM FouTo 16 o 9 GND Four 12 o Hil FOUTI FOUT4 18 o O ES FOUT3 sv 19 o o ST Fouts K PCL 836 REV A1 D TYPE 37PIN PIN ASSIGNMENT 8 PCL 836 User s Manual Connector CN1 Digital Output DIO DD DI4 DI6 DI8 DI10 DI12 DI14 GND 5V DO1 DO3 DOS DO7 DO9 DO11 DO13 DO15 GND 12V DI DI3 DIS DI7 DI9 DIL DI13 DI15 GND 12V Chapter 1 General Information 2 4 Hardware Installation 10 Warning TURN OFF your PC power supply whenever insta
5. In this mode the counter s clock input direct input from connector and the maximum input frequency can be up to 10 MHz e External clock with digital filter In this mode the counter s clock input is passed through the digital filter and the maximum input frequency depends upon the filter clock Internal clock In this mode the counter s clock input is connected to chip 1 or 2 Fout e PWM mode In this mode the counter is configured for PWM function Frequency output control register BASE 24 D7 D6 D5 D4 D3 D2 DI DO X X Fat6 Fats Fot 4 Fot3 Far2 Fot 1 Control the frequency output Dn 0 frequency output is off 3 state Dn 1 Frequency output is on 14 PCL 836 User s Manual 3 3 Digital Input Output The PCL 836 suffers 16 bits of TTL compatible digital input and output These digital input output ports are at address BASE 16 and BASE 17 The data format of each port is as following Read Operation Base Address 16 D I low byte Base Address 17 D I high byte Write Operation Base Address 16 D O low byte Base Address 17 D O high byte D7 D6 D5 D4 D3 DI7 DI6 DIS DI4 DIS D7 D6 D5 D4 D3 DI15DI14DI13DI12DI11 D7 D6 D5 D4 D3 D07 D06 DO5 D04 D03 D7 D6 D5 D4 D3 D2 DI2 D2 DI10 D2 DO2 D2 DI DI1 D1 DI9 D1 DO1 D1 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO DIO DO DI8 DO DOO DO DO8 Chapter 3 Register Structure and Format 15 Oper
6. error code FreqoutReset 3 5 42 PCL 836 User s Manual DioReadPortByte This function reads the current digital input value from the specified digital I Oport Prototype ULONG DioReadPortByte USHORT DeviceNumber USHORT Port USHORT Value Parameters DeviceNumber The board number of PCL 836 from 0 9 Port The port number of PCL 836 from 0 1 Value The cata of digital input Returned value 0 Success 1 Invalid device number 4 Lost kase address 9 Invalid port channel Example error_code DicReadPortByte 3 0 amp Value Chapter 6 PCL 836 Software Driver 43 44 DioWritePortByte This function writes digital cutout data to the specified digital port Prototype ULONG DioWritePortByte USHORT DeviceNumber USHORT Port U U SHORT Mask SHORT State Parameters DeviceNumber The board number of PCL 836 from 0 9 Pat he port number of PCL 836 from 0 1 Mask Specifies which bit s of data shouldbe sent to the digital output port and which bits remain unchanged State Newdigital logic state Returned value 0 Success 1 Invalid device number 4 Lost base address 5 Invalid counter number Example rror code DiditritePortByte 3 0 0x0F State Note The previous state of the digital port shouldbe stored with the configu PCL 836 User s Manual DioReadBit This function retums the bit state of digital input fromthe specified digi
7. frequency synthesis Coincidence alarms e Frequency measurements F V conversion amp pulse accumulation Period and pulse duration measurement Time delay measurement Periodic interrupt generation 2 PCL 836 User s Manual 1 4 Specifications Programmable Counters Counters Six independent 16 bit counters e Modes Three programmable counter modes Programeble digital noise filter 1 6 psec to 52 428 msec Usable pins Clock Gate and Out for each counter Progranmable time based output 153 Hz to 5 MHz 3 independent PWM outputs Input Output TIL compatible Interruot IRD 2 3 4 5 6 7 10 11 12 15 Jumper select Digital Input Output 16 TTL input Channels ogical level 0 0 8 Vmax ogical level 1 2 4 Vmin 16 TTL output Channels Logical level 0 0 5 V max 8 0 ma Logical level 1 2 4 Vmin 60 4 mA General e Connector 37 pin D SUB connector for counter I O 20 pin mle flat cable comector for digital 1 0 e Dimension 185 mm x 100 nm The PCL 836 generates high frequency signals which may cause EMI Electramagnetic Interference problems Use of Advantech s shielded 37 pin D SUB cable or another well shielded cable avoids these problems Chapter 1 General Information 3 1 5 Block Diagram 4 PCL 836 User s Manual Installation CHAPTER 2 1 Initial Inspection Y
8. 0 0 1 1 progranmable one shot X 1 0 2 Rate generator X 1 1 3 Square wave rate generator l 0 0 4 Software triggered strabe 1 0 1 5 Hardware triggered strobe BCD Select binary or BCD counting BCD Type 0 Binary counter 16 bits 1 Binary coded decimal BCD counter If the module is set to be binary the count can be any number from 0 up to 65535 If the module is set tobe BCD binary coded decimal the count can be set as any number fram 0 to 9999 If both LI and SO bits are set to 1 the conter control register is in read back command The data format of the control register then becomes BASE D7 D6 D5 D4 D3 D2 DI DO 1 1 CNT STA Q d CO x Chapter 5 Programmable Timer Counter 25 26 Legend CNT 0 latch count of selected counter s STA 0 latch status of selected counter s C2 Cl and CO Select counter for a read back operation C2 1 select counter 2 C1 1 select counter 1 CO 1 select counter 0 Tf SCl and SCO are both set to 1 and STA is set to 0 the counter read write register selected by C2 to CO contains a retum status byte The data fomat of the counter read write register then becares BASE D7 D6 DS D4 D3 D2 DI DO OUT NC RWI RWO M2 M1 MO BCD Legend OUT Counter output current state NC Null cant indicates when the last count written to the counter register has been loaded into the counting element PCL 836 User s Manual 5 3 Counter Operating Mode
9. 2 3 Connector Pin AssignmentS oooooooooo o 8 2 4 Hardware Installation oooooooooooooo 10 Register Structure and Format uucacccccanasasessrrrssasas 11 3 1 Port Address Map oooooooooooooooooo o 12 PCL 836 I O Port Address Map ooooooooo e 13 3 2 Counter control register format BASE 18 23 14 3 3 Digital Input Output A a od 15 Oporauon_ rg ili ili 11 4 1 Counter Modes ooooooooooooooooooo o 18 4 2 Di ital NOS IEA aaa a 19 4 3 Pulse width modulation PWM function 21 y Programmable TIMEr COUNTEr usuusu ZO D l The TEST 8204 a id dia 24 5 2 Counter Read Write and Control Registers 24 5 3 Counter Operating Modes oooooooooo o 21 5 3 1 Mode 0 Stop on terminal count 21 5 3 2 Mode 1 Programmable One Shot 21 5 3 3 Mode 2 Rate generator ooooooooooo ooo 21 5 3 4 Mode 3 Square wave generator ooooo ooo 28 5 3 5 Mode 4 Software triggered strdbe LL 28 5 3 6 Mode 5 Hardware triggered strabe 28 5 4 Counter operations oooooooooooooooo o 29 5 4 1 Read Write Operation LL 29 5 4 2 Counter read back command LL 29 5 4 3 Comter latch gerti Lucana eae quae ew wea 30 6 PCL 836 Software Driver eesmeezennannnzenmzenmonnj 9 1 Function call descriptions oooooooooooooo 32 DEVECEODEN uam e eee ae e rn 32 Deyi losin ae ia rea b eo ea Bee 33 COUNES
10. ICONETO Leila ali elena E A GOUME STE vent Stare a L a A U eg ta 35 CounterEventReadi i Mugi qa ee ra li aa ate 36 COMES rE SCAT E sa ae a lea SI COUNTEFEFSGRSAGi Ling a paella te 38 COMIECEPUISESTArE A A o A a 39 CONNESFRESSE e itato sele yes te ei jacta ase 40 Regine Caldiero ea rad BS 41 EFOGOUERSS6E Lie e ae een da 42 Di R agPortByter due deo Maas ot AS eta eee al 43 DIE MEIESPOLEBYEe ace Lei e bb a a asal a a Oe 44 DIOREAOBIE acca tect Oa ater ee ope ee ae dere 45 DIOWTIESBIE pale bates Wicd urban Rha ol a a 46 DioGetlurtentiOBVE aisi aloe era 47 DIOGSECULTOEDOBIE seie ie e Meee She See 48 Introduction CHAPTER 1 1 Introduction The PCL 836 is a multifunction counter timer and digital 1 0 add on card for IBM PC XT AT and compatibles It provides six 16 bit down counters a 10 MHz crystal oscillator timebase with divider and general purpose 16 bit TTL input and output ports Four Intel 8254 or compatible counter timer chips are used for all counting and timing functions 1 2 Key Features 6 independent 16 bit counters e 10 MHz maximum input frequency 10 MHz on board timebase Binary or BCD counting Programmable frequency output Complex duty cycle outputs One shot or continuous outputs 16 bit TIL digital input 16 bit TIL digital output Jumper selectable interrupt level 1 3 Applications e Event counting for pulse output devices Programmable
11. SE 00 0x00 Set Fout 0 frequency value in high byte The filter sample clock Fout 10 MHz 10 1 MHz The filter sample clock is 1 MHz and the period is 1ms thus 1x 7 7 ms The minimum clock input high low period must be gt 7 ms For more detailed information about how to program the digital noise filter refer to the example program on the utility disk 20 PCL 836 User s Manual 4 3 Pulse width modulation PWM function The PWM function is very widely used in today s applications The PCL 836 provides 3 PWM output channels When the PWM function is enabled the PCL 836 will combine two counters as a PWM channel and the counter in chip 3 must be programmed in mode 5 the counter in chip 4 must be programmed in mode 2 and the counter in chip 1 must be programmed in mode 3 The PWM period and duty cycle are decided by the value we assign to the counters in chip 3 chip 4 and chip 1 ES Clock In Counter 0 Out PWM negative period Po N S d PWM Fout 0 function EWM PWM base clock A out N control logic a Clock In Counter 3 Out PWM cycle period N p TJ negative period xl jt Lal Cycle period Example Config PWM output 1 1 Write the value 03H to BASE 18H for set ting counter 0 in PWM mode 2 Program the counter 0 in 8254 operating mode 5 3 Program counter 0 value for PWM negative period 4 Write the value 03H to BASE 21H for set ting counter 3 in PWM mode 5 Program th
12. ation CHAPTER The PCL 836 is a multifunction counter timer and digital I O add on card for IBM PC XT AT and compatibles There are four 8254 counter chips and 16 channels of TTL input output on board and each 8254 counter chip has 3 multifunction counters Two counter chips chip 1 and chip 2 are for the digital noise filter s sampling clock or frequency out and the others chip 3 and chip 4 are for the counters For each counter clock input pin in chip 3 and chip 4 the PCL 836 features a Schmitt trigger and a digital noise filter for noise immunity 4 1 Counter modes 18 The PCL 836 has six multifunction counters Users can program each counter in a different mode for their applications e Event counter Digital one shot e Programmable rate generator e Square wave generator etc For more information about programming the 8254 counter chip refer to chapter 5 or consult 8254 chip product documentation Counters 0 1 and 2 are located in 454 chip 3 and counters 3 4 and 5 are located in 8254 chip 4 PCL 836 User s Manual 4 2 Digital noise filter Noise immunitv is the most important requirement for reliable counter operation The PCL 836 conditions the clock input signals with a Schmitt trigger and a programming digital filter This filter reduces dips and spikes by sampling the clock input with a programmable filter sampling clock The filter output waveforms change only when an input has the same value for sev
13. ations are in pairs and to keep track of the byte order 5 4 2 Counter read back command The 8254 counter read back command allows users to check the count value progranmed mode and the current states of the OUT pin and Null Count flag of the selected counter s The command is written into the control word register and has the format shown in section 5 2 The read back command may be used to latch multiple counter output latches by setting the CNT bit 0 and selecting the desired counter s The single command is functionally equivalent to several counter latch commands one for each counter latched The read back command can also be used to latch status information of selected counter s by setting the STA bit 0 Status must be latched to be read the status of a counter is accessed by a read fran that counter The counter status format is shown in section 5 2 Chapter 5 Programmable Timer Counter 29 30 5 4 3 Counter latch operation Tt is often cesirable to read the value of a counter without disturbing the count in progress Usually the method used is the counter latch am mand method which allows the user to read the latched count value of the selected canter The 8254 supports the counter latch qoeration in two ways The first way is to set the RWI and RWO to be 0 0 which latches the count of the selected counter in a 16 01 t hold register The second approach is
14. base or start address BASE is selected by the DIP switch SW1 Each device on the PCL 836 has its own I O location as follows PC AT users should note that all ports are 8 bits one byte wide and should perform byte oriented read write operations rather than word 16 bits operations When performing consecutive byte transfers to the same I O port on the PC AT the PC AT Technical Reference Manual recommends the following coding in assembly language This is required to allow sufficient recovery time for the AT I O circuit OUT IO_ADDR AL write low byte JMP NEXT delay NEXT MOV AL AH fetch high byte OUT IO_ADDR AL write high byte PCL 836 User s Manual PCL 836 I O Port Address Map BASE 11 N U BASE 15 N U BASE 16 D I low byte BASE 17 D I high byte BASE 21 Counter 3 control register BASE 22 Counter 4 control register BASE 23 Counter 5 control register Note N U not used 8254 chip 1 and chip 2 are clock generators 8234 chip 3 and chip 4 are counters Chapter 3 Register Structure and Format 13 3 2 Counter control register format BASE 18 23 D7 D6 D5 DA D3 D2 DI DO Counter mode X X X X X 0 0 EBteraldadwittotdigita filter XX XX x 0 1 Bteralclckwithdigital filter X X X X X X 1 0 Ttereldak X X X X X X 1 1 PWM mode D2 controls the external clock D2 0 count the positive edge D2 1 count the negative edge e External clock without digital filter
15. ch position to ON for logic 0 and to OFF for logic 1 The various base address settings are illustrated as follows all el el e A9 A8 A7 AG AS 6 PCL 836 User s Manual I O address switch position Hex 1 2 3 4 5 AQ A8 A7 A6 A5 200 1 0 0 0 0 220 1 0 0 0 1 240 1 0 0 1 0 280 1 0 1 0 0 3E0 1 1 1 1 dl Factory setting Chose a base address that is not in use by another I O device A conflict with another device using the same I O location will usually cause the PCL 836 and other devices to malfunction The factory setting address is hex 240 which is usually kept free as it is reserved for the PC prototype board Jumper name JP1 IRQ X 15 12 11 10 7 6 5 4 3 2 0000000000 ooo0oo0oo0oo0oo0o o0 o0o0O The jumper JP1 is for selecting the interrupt level Avoid using a level that is being used by another device Interrupt is enabled by setting the Interrupt Enable CN3 pin 32 to logic low The positive edge on the Interrupt input CN3 pin 13 will then generate an interrupt if the 8259 interrupt controller on the system board is enabled Using the interrupt implies that the user has installed an interrupt service routine and interrupt vectors to the service routine and enabled the 8259 mask register for the level selected Itis not possible to set up an interrupt service routine using BASIC It is usually necessary to use assembly language Chapter 1 General Information 7 2 3
16. d low for N 1 2 counts 5 3 5 Mode 4 Software triggered strobe After the mock is set the output will be high When the count is loaded the counter will begin counting On terminal count the output will go low for one input clock period and will then go high again If the count register is reloaded during counting the new count will be loaded on the next CLK pulse The count will be inhibited while the GATE input is low 5 3 6 Mode 5 Hardware triggered strobe The counter will start counting after the rising edge of the trigger input and will go low for one clock period when the terminal count is reached The counter is retriggerable 28 PCL 836 User s Manual 5 4 Counter operations 5 4 1 Read Write Operation For each counter the type of read write operation operating mode and counter type must all be properly specified in the control byte and the control byte must be written before the initial count is written Since the control byte register and all three counter read write registers have separate addresses and each control byte specifies the counter that it agolies to through SCI and SCO no instructions on the operating sequence are required Any progranming sequence following the 8254 convention is acosptable There are three types of counter operation read load LSB read load MSB and read load LSB followed by MB It is important to ensure your read write oper
17. e affected but the subse quent period will reflect the value The gate input when low will force the output high When the gate input goes high the counter will start fromthe initial count Therefore the gate input can be used to synchronize the counter When this mode is set the output will remain high until the count register is loaded and the output can also be synchronized by software Chapter 5 Programmable Timer Counter 27 5 3 4 Mode 3 Square wave generator Mock 3 is similar to mode 2 exosot that the output will remain high until one half of the count has been completed for even numbers and will go low for the other half of the count This is accomplished by decreasing the counter by two on the falling edge of each clock pulse When the counter reaches the terminal count the state of the output is changed the counter is reloaded with the full count and the whole process is repeated Tf the cant is od and the output is high the first clock pulse after the count is loaded decrements the count by 1 Subsequent clock pulses decrement the count by 2 After time out the output goes low and the full cout is reloaded The first clock pulse following the reload decrements the counter by 3 Subsequent clock pulses decrement the count by two until time out then the whole process is repeated In this way if the count is odd the output will be high for N 1 2 counts an
18. e counter 3 in 8254 operating mode 2 Chapter 4 Operation 21 22 6 Program counter 3 value for PWM one cycle period 7 Program the Fout 0 in 8254 operating mode 2 for PWM base clock 8 Program the Fout 0 output frequency value Program in C outportb BASE 18 0x03 Set counter 0 in PWM mode outportb BASE 11 0x3A Set counter 0 in 8254 operating mode 5 outportb BASE 08 OxFA Set low byte value for PWM negative period outportb BASE 08 0x00 Set high byte value for PWM negative period outportb BASE 21 0x03 Set counter 3 in PWM mode outportb BASE 15 0x34 Set counter 3 in 8254 operating mode 2 outportb BASE 08 0xE8 Set low byte value for PWM a cycle period outportb BASE 08 0x03 Set high byte value for PWM a cycle peri od outportb BASE 03 0x34 Set Fout 0 in 8254 operating mode 2 for PWM base clock outportb BASE 00 0x0A Set Fout 0 fre quency value in low byte outportb BASE 00 0x00 Set Fout 0 fre quencv value in high bvte The PWM base clock Fout 0 10Mhz 10 1Mhz For instance if the Fout 0 is programmed as a 1 mHz clock output and the counter 0 value is 250 the counter 3 value is 1000 then The period of the PWM output will be FO Rena 1000 ms The negative period will be 250 X 1ms Programmable Timer Counter CHAPTER 5 1 The Intel 8254 The PCL 836 uses 4 Intel 8254 programmabl
19. e interval timer counters The 8254 is a very popular timer counter device consisting of three independent 16 bit down counters Each counter has a clock input control gate and an output It can be programmed to have a count from 2 up to 65535 5 2 Counter Read Write and Control Registers 24 The 8254 programable interval timer uses four registers for each chip The functions of each register are as follows BASE 0 4 8 12 Counter 0 Read Write BASE 1 5 9 13 Counter 1 Read Write BASE 2 6 10 14 Counter 2 Read Write BASE 3 7 11 15 Counter Control Word Since the 8254 counter uses a 16 bit structure each section of read write data is split into the least significant byte LSB and the most significant byte MSB It is important to ensure that your read write operations are in pairs and to keep track of the byte order The data format of the control register is BASE D7 D6 D5 D4 D3 D2 DI DO SC1 SCO RWI RWO M2 M1 MO BCD Legend SCI amp SCO Select counter SC1 SCO Counter 0 0 0 0 1 1 il 0 2 al il R ead back command PCL 836 User s Manual RWL amp RWO Select the Read Write operation RW1 RWO Cperation 0 0 canter latch 0 1 Read Write LSB 1 0 Read Write MSB 1 T Read Write LSB first then MSB M2 M and MO Select the operating mode M2 M1 MO Mode 0 0 0 0 interrupts terminal count
20. en consecutive sampling edges The filter thus rejects noise or pulses shorter than seven sampling clock periods You can optimize noise immunity by selecting a lower sampling frequency that is compatible with the highest input rate that you expect For high speed clock input users can disable the digital filter for their applications Each counter has its own noise filter Users can program different filter sampling rates for different clock event inputs When the noise filter is enabled the 8254 s chip 1 and chip 2 have to set it in square wave mode to provide the digital noise filter s sampling clock n gt e ea Digital gt e noise Counter E i U p el Filter sampling clock JUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUL Filter sampleing clock input 4 noise Counter clock input before filter Counter clock input after filter noise be filtered Example Enable the PCL 836 counter 0 digital noise filter 1 Write 01H to BASE 18H to enable counter 0 digital noise filter 2 Program counter 0 in 8254 operating mode 2 3 Program Fout 0 in 8254 operating mode 2 4 Set the Fout frequency value Chapter 4 Operation 19 program in C outportb BASE 18 0x01 Enable counter 0 digital filter outportb BASE 11 0x34 Set counter 0 in 8254 operating mode2 outportb BASE 03 0x34 Set Fout 0 in 8254 operating mode 2 outportb BASE 00 0x0A Set Fout frequency value in low byte outportb BA
21. er counting Prototype ULONG CounterEventStart USHORT DeviceNumber USHORT Counter Parameters DeviceNumber The board number of PCL 836 from 0 9 Counter The counter number of PCL 836 fram 0 5 Returned value 0 Success 1 Invalid device nunber 4 Lost base address 5 Invalid counter channel Example error_code CounterEventStart 3 5 Chapter 6 PCL 836 Software Driver 35 CounterEventRead This function retums the counter value Prototype ULONG CounterEventRead USHORT DeviceNumber USHORT Counter USHORT Overflow ULONG Count Parameters DeviceNumber The board number of PCL 836 from 0 9 Counter he counter number of PCL 836 from 0 5 Overflow The status of counter overflow 1 for 32bit counter overflow otherwise 0 Count he counter value Returned value 0 Success 1 Invalid device number Oo Invalid counter chanel 4 Lost base address Example error_code CounterEventRead 3 5 amp Overflow amp Count 36 PCL 836 User s Manual CounterFregStart This function omfigures the specified counter for frequency masure ment then starts the frequency measurement Prototype ULONG CounterFregStart USHORT DeviceNumber USHORT Counter Parameters DeviceNumber Counter Returned value 0 Success E ul Example The board number of PCL 836 from 0 9 he counter number
22. lling or removing the PCL 836 or connecting and disconnecting cables Installing the card in your computer 1 Turn off the computer and all peripheral devices such as printers and monitors 2 Disconnect the power cord and any other cables from the back of the computer Turn the system unit so the back of the unit faces you 3 Remove the system unit cover see your computer user s guide if necessary 4 Locate the expansion slots at the rear of the unit and choose an unused slot 5 Remove the screw that secures the expansion slot cover to the system unit Save the screw to secure the interface card retaining bracket 6 Carefully grasp the upper edge of the PCL 836 card Align the hole in the retaining bracket with the hole on top of the expansion slot and align the gold striped edge connector with the expansion slot socket Press the board firmly into the socket 7 Replace the screw in the expansion slot retaining bracket 8 Attach necessary accessories DB 37 pin cable or connector adapter etc to the interface card according to your application require ments 9 Replace the system unit cover Connect the cables you removed in step 2 Turn on the computer Hardware installation is now complete Proceed to install the software driver PCL 836 User s Manual CHAPTER Register Structure and Format 3 1 I O Port Address Map 12 The PCL 836 uses 32 consecutive addresses in the PC I O address space The
23. of PCL 836 from 0 5 Invalid device number 4 Lost base address Invalid channel nunber error code ConnterFreostart 3 5 Chapter 6 PCL 836 Software Driver 37 38 CounterFreqRead This function reads the frequency measurement Prototype ULONG CounterFregRead USHORT DeviceNumber USHORTCounter USHORT FregLevel FLOAT Freg Parameters DeviceNumber he board number of PCL 836 from 0 9 Counter he counter number of PCL 836 from 0 5 Freglevel Hz 0 MAX 1Hz 65 kHz 1 MAX10 kHz 650 kHz 2 MAX100 kHz 6500 kHz Freg The frequency value Returned value 0 Success 1 Invalid device number 4 Lost base address 5 Invalid counter number Example error_code CounterFreoRead 3 5 MAX1_65 kHz Freq PCL 836 User s Manual CounterPulseStart This function starts the pulse width modulation PAM output Prototype ULONG CounterPulseStart USHORT DeviceNumber USHORT Counter float Period float UsCycle Parameters DeviceNumber The board number of PCL 836 from 0 9 Counter The counter number of PCL 836 fran 0 2 Period The total period in ms UpCycle The first 1 2 cycle length in ms Returned value 0 Success 1 Invalid device number 4 Lost base address 5 Invalid counter channel 6 Invalid input parameter 8 Invalid frequency range Example error code CounterPulseStart 3 1 0 5 0 01 Chapter 6 PCL 836 Software Driver 39 Co
24. ou should find the PCL 836 card and this user s manual inside the shipping container The PCL 836 has been inspected and tested both physically and electronically before shipment It should be free of marks and scratches and in perfect working order upon receipt Check the unit for any signs of shipping damage when unpacking If there is any damage to the unit or if it fails to meet specifications notify our service department or your local sales representative immediately Call the carrier and retain the shipping carton and packing material for inspection by the carrier We will arrange to repair or replace the unit Remove the PCL 836 interface card from its protective packaging Keep the anti vibration package Whenever you are not using the card store it in the package for protection Discharge any static electricity that may have built up within your body by touching an unpainted surface on the back of your computer system before you handle the board You should avoid contact with materials that create static electricity such as plastic vinyl and Styrofoam The board should be handled only by the edges to avoid static electric discharge that could damage the integrated circuits on the PCL 836 2 2 Switch and Jumper Settings There is one DIP switch SW 1 and one jumper JP1 on the PCL 836 for the selection of the I O address and interrupt level Switch name SW1 The DIP switch SWI is used to set base I O address Set the swit
25. rt Port number of PCL 836 from 0 1 Value 8 bit digital data of specified ougout port Returned value 0 Success 1 Invalid device number Lost base address malid input parameter malidport damel HS D I I Ke Example error code DioGetCurrentDcByte 3 0 amp Value Chapter 6 PCL 836 Software Driver 47 48 DioGetCurrentDOBit This function retums digital output data from the specified digital I O pat Prototype ULONG DioGetCurrentDOBit USHORT DeviceNumber USHORT Port USHORT Bit USHORT State Parameters DeviceNumber Board number of PCL 836 from 0 9 Port Port number of PCL 836 fran 0 1 Bit Shit digital data of specified astout port 0 7 State Bit cata fromthe specified port Returned value 0 Success 1 Invalid device nunber 4 Example error DioGetCurrentDOBit 3 0 5 amp State PCL 836 User s Manual
26. s 5 3 1 Mode 0 Stop on terminal count The output will initially he low after setting this mode of operati After the count is loaded into the selected count register the output will remain low and the counter will count When the terminal count is reached the cutout will go high and remain high until the selected counter is reloaded with the mode or a new count is loaded The counter continues to decrement after terminal count has been reached Rewriting a counter register during counting generates the following results 1 Write the first byte st s the current counting 2 Writing the second byte starts the new count 5 3 2 Mode 1 Programmable One Shot The output will go low on the count following the rising edge of the gat input The output will go high on the terminal count If anew cout value is loaded while the atat is low it will not affect the duration of the me shet pulse until the following trigger The current count can ke read at any time without affecting the one shot pulse The one shot is retriggerable thus the cutout will remain low for the full cout after any rising eche at the gate ipt 5 3 3 Mode 2 Rate generator The output will ke low for one period of the input clock The period from one output pulse to the next equals the number of input counts in the counter register If the counter register is reloaded between output pulses the present period will not k
27. tal T Oport Prototype ULONG DioReadBit ULONG DeviceNumber USHORT Port USHORT Bit USHORT State Parameters DeviceNumber The board number of PCL 836 from 0 9 Part The port number of PCL 836 from 0 1 Bit The bit number from 0 7 State The bit data read fromthe specifiedport 0 or 1 Return value 0 Success 1 Invalid device number 4 Lost base address 6 Invalid Inout parameter 9 Invalid port channel Example error code DicReacBit 3 0 5 amp State Chapter 6 PCL 836 Software Driver 45 46 DioWriteBit This function writes the bit state of digital output to the specified digital T Oport Prototype ULONG DioWriteBit ULONG DeviceNumber USHORT Port USHORT Bit USHORT State Parameters DeviceNumber he board number of PCL 836 from 0 9 Pat The port number of PCL 836 from 0 1 Bit The bit number from 0 7 State The bit data read fromthe specified port 0 or 1 Returned value 0 Success 1 Invalid device number 4 Example error code DidiriteBit 3 0 5 1 Note The previous state of the digital port shouldbe stored with the configu PCL 836 User s Manual DioGetCurrentDOByte This function retums the digital output data fromthe specified digital 1 Oport Prototype ULONG DioGetCurrentDOByte USHORT DeviceNumber USHORT Port USHORT Value Parameters DeviceNumber Board number of PCL 836 from 0 9 Pa
28. unterReset This function resets the counter to power on state Prototype ULONG CounterReset USHORT DeviceNumber USHORT Counter Parameters DeviceNumber The board number of PCL 836 from 0 9 Counter The counter number of PCL 836 from 0 5 Returned value 0 Success 1 Invalid device number 4 Lost base address 5 Invalid counter number Example ror CounterReset 3 5 40 PCL 836 User s Manual Freqout Start This function configures the specified counter for frequency output then starts freqrency atat Prototype ULONG FreqOutStart USHORT DeviceNumber USHORT Counter E LOAT Fout Parameters DeviceNumber The board number of PCL 836 from 0 9 Counter The counter number of PCL 836 fra 0 5 Fout The frequency of output in Hz from 153 Hz 5MHz Returned value 0 Success 1 Invalid device number Lost base address HS ul Invalid counter number Invalid frequency range 00 Example error FreoPutStart 3 5 10000 Chapter 6 PCL 836 Software Driver 41 FreqOutReset This function stops the frequency fram the specified counter Prototype ULONG FreqOutReset USHORT DeviceNumber USHORT Counter Parameters DeviceNumber The board number of PCL 836 from 0 9 Counter The counter number of PCL 836 from 0 5 Returned value 0 Success 1 Invalid device number 4 Lost base address 5 Invalid counter number Example
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