ADSST-SALEM-3T Powerful Energy Meter Chipset
Contents
1. Parameter Nominal Value Nominal Voltage Phase to Neutral Vn Vun 230V 41 Maximum Voltage Phase to Neutral 300 V Nominal Current IN 5A Maximum Current Imax Imax 20 A Frequency Fu 50 Hz 60 Hz 10 Temperature 23 42 C Table 11 Maximum Error Power and Energies Current Voltage PF Min Typ Max Unit 0 01 In lt I lt 0 05 In Vu 1 0 0 1 0 2 0 05 In lt I lt Imax Vn 1 0 0 1 0 2 0 02 In lt I lt 0 1 In Vw 0 5 Lagging 0 15 0 35 0 8 Leading 0 15 0 35 0 05 In lt I lt Imax Vn 0 5 Lagging 0 1 0 2 0 8 Leading 0 1 0 2 Table 12 Unbalanced Load Error Current Voltage PF Min Typ Max Unit 0 05 In lt I lt Imax Vn 1 0 0 15 0 2 0 1 In lt I lt Imax Vn 0 5 Lagging 0 15 0 2 Table 13 Voltage Variation Error Voltage Current PF Min Typ Max Unit Vn 10 0 05 In lt 1 lt Imax 1 0 0 05 0 1 Vu 10 0 1 In lt I lt Imax 0 5 Lagging 0 05 0 1 Table 14 Frequency Variation Errors Frequency Current PF Min Typ Max Unit fn 10 0 05 In lt I lt Imax 1 0 0 05 0 1 fy 10 0 1 In lt I lt Imax 0 5 Lagging 0 05 0 1 Table 15 Harmonic Distortion Error Current Current Min Typ Max Unit 10 of 3 Harmonic 0 05 In lt I lt Imax 0 05 0 1 Table 16 Reverse Phase Sequence Error Current Voltage Min Typ Max Unit 0 1 In Vn 0 05 Rev 0 Page 18 of 24 ADSST SALEM 3T Table 17 Voltage Unbalance Error Current V2. this pin and are clocked on the negative edge of SCLK SDI is ignored when SE is low Rev 0 Page 15 of 24 ADSST SALEM 3T Pin No Mnemonic Function 18 SE SPORT Enable Asynchronous input enable pin for the SPORT When SE is set low by the DSP the output pins of the SPORT are three stated and the input pins are ignored SCLK is also disabled internally in order to decrease power dissipation When SE is brought high the control and data registers of the SPORT are at their original values before SE was brought low however the timing counters and other internal registers are at their reset values 19 AGND1 Analog Ground Connection 20 AVDD1 Analog Power Supply Connection 21 VINP6 Analog Input to the Positive Terminal of Input Channel 6 22 VINN6 Analog Input to the Negative Terminal of Input Channel 6 23 VINP5 Analog Input to the Positive Terminal of Input Channel 5 24 VINN5 Analog Input to the Negative Terminal of Input Channel 5 25 VINP4 Analog Input to the Positive Terminal of Input Channel 4 26 VINN4 Analog Input to the Negative Terminal of Input Channel 4 27 VINP3 Analog Input to the Positive Terminal of Input Channel 3 28 VINN3 Analog Input to the Negative Terminal of Input Channel 3 GROUNDING AND LAYOUT A minimum etch technique is generally best for ground planes Since the analog inputs to the ADSST 73360LAR are differential most of the voltages in the analog modulator are common mode voltage
3. Table 7 Current Summary AVDD DVDD 3 3 V Digital Current Conditions Max mA SE MCLKON Comments ADCs Only On 25 1 Yes REFOUT Disabled REFCAP Only On 1 0 0 No REFOUT Disabled REFCAP and REFOUT Only On 3 5 0 No All Sections On 26 5 1 Yes REFOUT Enabled All Sections Off 1 0 1 Yes MCLK Active Levels Equal to 0 Vand DVDD All Sections Off 0 05 0 No Digital Inputs Static and Equal to 0 V or DVDD The above values are in mA and are typical values unless otherwise noted MCLK 16 384 MHz SCLK 16 384 MHz Rev 0 Page 13 of 24 ADSST SALEM 3T ABSOLUTE MAXIMUM RATINGS ADSST 73360LAR Ta 25 C unless otherwise noted Table 8 Parameter Rating AVDD DVDD to GND 0 3 V to 4 6 V AGND to DGND 0 3 V to 0 3 V Digital UO Voltage to DGND 0 3 V to DVDD 0 3 V Analog I O Voltage to AGND 0 3 V to AVDD Operating Temperature Range 0 C to 70 C Storage Temperature Range 65 C to 150 C Maximum Junction Temperature 150 C Thermal Impedance Ou SOIC 75 C W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge
4. Avoid running digital lines under the device for they will couple noise onto the die The analog ground plane should be enabled to run under the ADSST 73360LAR to avoid noise coupling The power supply lines to the ADSST 73360LAR should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply lines Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs Traces on opposite sides of the board should run at right angles to each other This will reduce the effects of feed through through the board A microstrip technique is by far the best but is not always possible with a double sided board In this tech nique the component side of the board is dedicated to ground planes while signals are placed on the other side Good decoupling is important when using high speed devices All analog and digital supplies should be decoupled to AGND and DGND respectively with 0 1 uF ceramic capacitors in parallel with 10 uF tantalum capacitors To achieve the best from these decoupling capacitors they should be placed as close as possible to the device ideally right up against it In systems where a common supply voltage is used to drive both the AVDD and DVDD of the ADSST 73360LAR it is recommended that the system s AVDD supply be used This supply should have
5. inches Rev 0 Page 20 of 24 ADSST SALEM 3T ORDERING GUIDE Part Number Temperature Range Processors Included Package ADSST EM 3040 0 C to 70 C ADSST 2185MKST 300 ST 100 ADSST 73360LAR RW 28 ADSST EM 3041 25 C to 85 C ADSST 2185MBST 266 ST 100 ADSST 73360LAR RW 28 1 For developer s kit order ADSST SALEM 3T DK Rev 0 Page 21 of 24 ADSST SALEM 3T NOTES Rev 0 Page 22 of 24 ADSST SALEM 3T NOTES Rev 0 Page 23 of 24 ADSST SALEM 3T NOTES 2004 Analog Devices Inc All rights reserved Trademarks and regis ANALOG tered trademarks are the property of their respective owners www ana l 0 g com osaa Aad DEVICES Rev 0 Page 24 of 24
6. ondary side of the CT Since the ADSST 73360LAR is a unipolar ADC the ac potential and current signals have to be offset by some dc level The reference design has a dc offset of 2 5 V This limits the peak to peak signal range of potential and current to 3 28 V p p or 1 16 V rms Potential Section The selection of the potential divider circuit should be such that it can e Handle high surge voltages e Have minimum VA burden e Give approximately 1 V peak headroom to accommodate overvoltages Current Section The selection of CT ratio and burden resistance should be such that it can e Handle the complete dynamic range for the current signal input e Give approximately 1 V peak headroom to accommodate loads with high crest factors The reference design has a CT with a turns ratio of 1 2500 and burden resistance of 82 Q This generates 0 656 V rms or 0 928 V peak at 20 A current This leaves enough margin for current pulses or low crest factor loads such as SMPS The maximum current can be up to 32 768 A Rev 0 Page 17 of 24 ADSST SALEM 3T ACCURACY OF REFERENCE DESIGN USING THE ADSST SALEM 3T CHIPSET Overall Accuracy Power and Energy Measurement The accuracy figures are measured under typical specified conditions unless otherwise indicated Table 10 Test Conditions for Reference Design Using au Metal CT of Class 0 5 Accuracy
7. sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Rev 0 Page 14 of 24 E ESD SENSITIVE DEVICE ADSST SALEM 3T PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS ADSST 73360LAR NC NO CONNECT 03738 0 005 Figure 7 ADSST 73360LAR Pin Configuration RW 28 PIN FUNCTION DESCRIPTIONS Table 9 Pin No Mnemonic Function 1 VINP2 Analog Input to the Positive Terminal of Input Channel 2 2 VINN2 Analog Input to the Negative Terminal of Input Channel 2 3 VINP1 Analog Input to the Positive Terminal of Input Channel 1 4 VINN1 Analog Input to the Negative Terminal of Input Channel 1 5 REFOUT Buffered Output of the Internal Reference which has a nominal value of 1 2 V 6 REFCAP Reference Voltage for ADCs A bypass capacitor to AGND2 of 0 1 uF is required for the on chip reference The capacitor should be fixed to this pin The internal reference can be overdriven by an external reference connected to this pin if required 7 AVDD2 Analog Power Supply Connection 8 AGND2 Analog Ground Substrate Connection 9 DGND Digital Ground Substrate Connection 10 DVD
8. simultaneously acquire voltage and current samples on all three phases and to perform mathematically intensive computations to calculate various instantaneous parameters and perform harmonic analysis The Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners chipset can be interfaced to any general purpose microproces sor to develop state of the art tri vector or polyphase energy metering solutions with a wide range of basic currents from 1 A to 30 A By incorporating a comprehensive data set of parame ters including instantaneous measurements accumulated parameters and harmonic analysis data the ADSST SALEM 3T chipset meets high end energy metering requirements The abil ity to easily configure the chipset for various parameters makes it a very flexible solution The phase and nonlinearity compensation for current transformers is done in software patent pending without having to use any passive components in the circuit for compensation thus minimizing variations in accuracy with temperature and time
9. the recommended analog supply decoupling between the AVDD pins of the ADSST 73360LAR and AGND and the recommended digital supply decoupling capacitors between the DVDD pin and DGND Rev 0 Page 16 of 24 POWER UP INITIALIZATION AND DATA FROM THE ADSST SALEM 3T The ADSST SALEM 3T EV boot loads the code from the nonvolatile flash memory as shown in the block diagram of a functional meter in Figure 1 The configuration and calibra tion data also gets loaded from the nonvolatile memory For further details on boot loading refer to the ADSST SALEM 3T DK Developer s Kit User Manual The user manual also describes various commands for instantaneous and computed parameters VOLTAGE AND CURRENT SENSING Figure 9 shows the input section for the voltage and current sections Based on the voltage and current values the GUI software in the ADSST SALEM 3T DK computes the values of resistors R1 R2 and R3 The closest available values to those calculated by the GUI software should be selected and used VOLTAGE INPUT PHASE VOLTAGE R1 TO ADC CHANNEL R2 NEUTRAL CURRENT INPUT TO ADC CHANNEL PHASE R3 CURRENT NEUTRAL 03738 0 007 Figure 9 Input Section ADSST SALEM 3T The ADSST 73360LAR has a peak to peak input range of Vrer Vrer X 0 6525 to Vrer Vrer X 0 6525 for Vrer 2 5 V this is 0 856 V to 4 14 V p p This limit defines the resistance network on the potential circuits and the burden resistance on the sec
10. 3738 0 008 Figure 3 Functional Block Diagram Rev 0 Page 4 of 24 Efficient data transfer is achieved with the use of five internal buses e Program Memory Address PMA Bus Program Memory Data PMD Bus e Data Memory Address DMA Bus e Data Memory Data DMD Bus e Result R Bus The byte memory and I O memory space interface supports slow memories and I O memory mapped peripherals with pro grammable wait state generation External devices can gain control of external buses with bus request grant signals BR BGH and BGO One execution mode go mode enables the ADSST 218x to continue running from on chip memory Nor mal execution mode requires the processor to halt while buses are granted ADSST SALEM 3T The ADSST 218x can respond to 11 interrupts There are up to six external interrupts one edge sensitive two level sensitive and three configurable and seven internal interrupts generated by the timer the serial ports SPORTs the byte DMA port and the power down circuitry There is also a master RESET signal The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation Serial Ports The ADSST 218x incorporates two complete synchronous serial ports SPORTO and SPORT1 for serial communications and multiprocessor communication Package Description The ADSST 218x is av
11. ANALOG DEVICES Powerful Energy Meter Chipset ADSST SALEM 3T FEATURES High accuracy Supports IEC 60687 61036 and ANSI C12 1 12 20 Suitable for class0 5 and class0 2 meter Full four quadrant measurement of parameters SPI compatible serial interface Pulse output with programmable pulse constant as pulses kWh or Wh pulse Programmable duty cycle for pulse output Embedded calibration routines for gain and dc offset Software based phase and nonlinearity compensation for current transformers 15 kHz sampling frequency UART mode enables a PC to directly access all computed parameters Flags to indicate tamper conditions Single 3 0 V supply Developer s kit to accelerate design process See Ordering Guide for separate ordering number GENERAL DESCRIPTION The ADSST SALEM 3T energy meter chipset consists of an efficient ADSST 218x digital signal processor DSP a fast and accurate 6 channel 16 bit ADSST 73360LAR sigma delta ana log to digital converter ADC and metering software Two chipset versions are available to support differing ranges of operating temperature The ADSST EM 3040 chipset is rated at 0 C to 70 C for commercial applications while the ADSST EM 3041 chipset operates at 25 C to 85 C for industrial use LCD DISPLAY SPI BUS RESISTOR E E BLOCK BUTTONS ADSST EM 3040 03738 0 001 Figure 1 Block Diagram of a Functional Meter The ADC and DSP are interfaced to
12. D Digital Power Supply Connection 11 RESET Active Low Reset Signal This input resets the entire chip resetting the control registers and clearing the digital circuitry 12 SCLK Output Serial Clock whose rate determines the serial transfer rate to from the ADSST 73360LAR It is used to clock data or control information to and from the serial port SPORT The frequency of SCLK is equal to the frequency of the master clock MCLK divided by an integer number that is the product of the external master clock rate divider and the serial clock rate divider 13 MCLK Master Clock Input MCLK is driven from an external clock signal 14 SDO Serial Data Output of the ADSST 73360LAR Both data and control information may be output on this pin and are clocked on the positive edge of SCLK SDO is in three state when no information is being transmitted and when SE is low 15 SDOFS Framing Signal Output for SDO Serial Transfers The frame sync is one bit wide and it is active one SCLK period before the first bit MSB of each output word SDOFS is referenced to the positive edge of SCLK SDOFS is in three state when SE is low 16 SDIFS Framing Signal Input for SDI Serial Transfers The frame sync is one bit wide and it is valid one SCLK period before the first bit MSB of each input word SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low 17 SDI Serial Data Input of the ADSST 73360LAR Both data and control information may be input on
13. General Description of the ADSST 218x DSP nenn 4 RE 15 Architecture Overview ENEE 4 Pin Function Descriptions ENNEN 15 ADSST 218x Common Mode Pins ENEE 6 Grounding and Layout ENEE 16 Ee 7 Power Up Initialization and Data from the ADSST SALEM E 17 RESET T E 7 Voltage and Current Sensing ENEE 17 Recommended Operating Conditions en 7 ADSST 218x Electrical Characteristics cccccccscscscsesesesesesesesees 8 Accuracy of Reference Design Using the ADSST SALEM 3T Chipset ENEE 18 Absolute Maximum Ratings ADSST 218X 0 E 9 i Outline Dimensions we 20 ESD Cation En 9 EE 21 Pin Confeuraton ADSST 318s EEN 10 REVISION HISTORY 7 04 Revision 0 Initial Version Rev 0 Page 2 of 24 EASY CALIBRATION The ADSST SALEM 3T chipset has highly advanced calibration routines embedded into the software Ease of calibration is the key feature in this chipset By sending specific commands to the ADSST SALEM 3T chipset the dc offsets and gains for all volt age and current channels can be calibrated automatically Active and reactive power calibration is also available for fine tuning the errors The meter and calibration constants are stored in an external flash memory and the lock unlock calibration feature enables protection of the calibration constants The ability to upgrade the firmware residing in the flash memory makes the meter adaptable to future needs EFFECTIVE PHASE COMPENSATION The ADSST SALEM 3T chipset employs an algor
14. Hz 0 01 Degrees fin 60 Hz Rev 0 Page 12 of 24 ADSST SALEM 3T Parameter Min Typ Max Unit Test Conditions FREQUENCY RESPONSE ADC Typical Output Frequency Normalized to fs 0 0 dB 0 03125 0 1 dB 0 0625 0 25 dB 0 125 0 6 dB 0 1875 1 4 dB 0 25 2 8 dB 0 3125 4 5 dB 0 375 7 0 dB 0 4375 9 5 dB gt 0 5 lt 12 5 dB LOGIC INPUTS Vinx Input High Voltage Voo 0 8 Von V Vint Input Low Voltage 0 0 8 V l Input Current 10 uA Cw Input Capacitance 10 pF LOGIC OUTPUT Vox Output High Voltage Voo 0 4 Von V lout lt 100 pA Vo Output Low Voltage 0 0 4 V lour lt 100 pA Three State Leakage Current 10 10 uA POWER SUPPLIES AVDD1 AVDD2 2 7 3 6 V DVDD 2 7 3 6 V IDD See Table 7 Operating temperature range is as follows 40 C to 85 C Therefore Tmn 40 C and Tmax 85 C Test conditions Input PGA set for 0 dB gain unless otherwise noted 3At input to sigma delta modulator of ADC Guaranteed by design 5Overall group delay will be affected by the sample rate and the external digital filtering The ADC s input impedance is inversely proportional to DMCLK and is approximated by 4 x 10 DMCLK 7Frequency response of the ADC measured with input at audio reference level the input level that produces an output level of 0 dBm0 with 38 dB preamplifier bypassed and input gain of 0 dB Test Conditions no load on digital inputs analog inputs ac coupled to ground
15. ORS PROGRAM PROGRAM SEQUENCER MEMORY 16K x 24 BIT PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS MEMORY 16K x 16 BIT This takes place while the processor continues to e Receive and transmit data through the two serial ports e Receive and or transmit data through the internal DMA port e Receive and or transmit data through the byte DMA port e Decrement timer ARCHITECTURE OVERVIEW The ADSST 218x instruction set provides flexible data moves and multifunction one or two data moves with a computation instructions Every instruction can be executed in a single proc essor cycle The ADSST 218x assembly language uses an algebraic syntax for ease of coding and readability A compre hensive set of development tools supports program development Figure 3 is the functional block diagram of the ADSST 218x The processor contains three independent computational units the ALU the multiplier accumulator MAC and the shifter The computational units process 16 bit data directly and have provisions to support multiprecision computations FULL MEMORY MODE r PROGRAMMABLE EXTERNAL vo ADDRESS gt AND BUS l l l l EXTERNAL DATA l BYTE DMA CONTROLLER PROGRAM MEMORY DATA DATA MEMORY DATA ARITHMETIC UNITS ADSP 2100 BASE ARCHITECTURE SERIAL PORTS l EXTERNAL l DATA l l ol Nis BUS TIMER l l INTERNAL I DMA PORT HOST MODE 0
16. T SALEM 3T ABSOLUTE MAXIMUM RATINGS ADSST 218X Table 5 Rating Parameter Min Max Internal Supply Voltage Vopr 0 3 V 3 0 V External Supply Voltage Vooext 0 3 V 4 0 V Input Voltage 0 3V 4 0 V Output Voltage Swing 0 5 V Vovext 0 5 V Operating Temperature Range 0 C 70 C Storage Temperature Range 65 C 150 C Applies to bidirectional pins D0 D23 RFSO RFS1 SCLKO SCLK1 TFSO TFS1 A1 A13 PFO PF7 and input only pins CLKIN RESET BR DRO DR1 PWD 2Applies to output pins BG PMS DMS BMS IOMS CMS RD WR PWDACK AO DTO DT1 CLKOUT FL2 FLO BGH Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only functional operation of the device at these or any other conditions above those indicated in the operational sec tions of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the i human body and test equipment and can discharge without detection Although this product features WARNING Cl proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy el electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance ESD SENSITIVE DEVICE degrad
17. The ADSST SALEM 3T measures and computes a large num ber of parameters essential for high end metering Table 1 Parameter Each Phase Total RMS Voltage v RMS Current Active Power Apparent Power Inductive Reactive Power Capacitive Reactive Power SISI SISI SIS Power Factor Frequency Positive Active Energy Negative Active Energy Apparent Energy Positive Inductive Reactive Energy Negative Inductive Reactive Energy Positive Capacitive Reactive Energy Negative Capacitive Reactive Energy s Isisisisisisisisisisisisis Hol PA RR EE Voltage Magnitude and Phase for All Odd Harmonics up to 21 Order Current Magnitude and Phase for All Odd Harmonics up to 21 Order Xx Xx The ADSST SALEM 3T offers some excellent features that make the final meter cost effective and easy to manufacture One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved ADSST SALEM 3T TABLE OF CONTENTS asetaltlatatigttoee EE 3 General Description of the ADSST 73360LAR ADC Effective Phase Compensation ENEE 3 Specifications ADSST 73360LAR en Absolute Maximum Ratings ADSST 73360LAR en 14 EaseptHleeien eene 3 BC aen 14 Quadrant and Other Conventions cccessssssssssssseseseeeeeeeeees 3 Pin Configuration and Pin Function Descriptions
18. ailable in a 100 lead low profile quad flat package LQFP refer to Figure 5 Rev 0 Page 5 of 24 ADSST SALEM 3T ADSST 218X COMMON MODE PINS Table 2 Pin Name No of Pins 1 0 Function BG 1 O Bus Grant Output BGH 1 O Bus Grant Hung Output BMS 1 O Byte Memory Select Output BR 1 l Bus Request Input CMS 1 O Combined Memory Select Output DMS 1 0 Data Memory Select Output TOMS 1 Oo Memory Select Output PMS 1 O Program Memory Select Output RD 1 O Memory Read Enable Output RESET 1 Processor Reset Input WR 1 O Memory Write Enable Output IRQ2 1 Edge or Level Sensitive Interrupt Request PF7 1 0 Programmable I O Pin IRQL1 1 Level Sensitive Interrupt Requests PF6 1 0 Programmable I O Pin IRQLO 1 Level Sensitive Interrupt Requests PF5 1 0 Programmable I O Pin IRQE 1 Edge Sensitive Interrupt Requests PF4 1 0 Programmable I O Pin MODE A 1 Mode Select Input Checked only during RESET PFO 1 0 Programmable I O Pin during Normal Operation MODE B 1 l Mode Select Input Checked only during RESET PF1 1 0 Programmable I O Pin during Normal Operation MODE C 1 Mode Select Input Checked only during RESET PF2 1 0 Programmable I O Pin during Normal Operation MODE D 1 l Mode Select Input Checked only during RESET PF3 1 0 Programmable I O Pin during Normal Operation CLKIN XTAL 2 Clock or Quartz Crystal Input CLKOUT 1 O Processor Clock Output EZ Port 9 1 0 For Emulatio
19. ation or loss of functionality Rev 0 Page 9 of 24 ADSST SALEM 3T PIN CONFIGURATION ADSST 218X lt n oa W W Ww W s 88 B8 nr oO aaa 2 Ss kes zac Dt ZS omg torr a eas res SPEZE SQL S5IRNaRZSEES si st d d oo oo OLA gt oo HU AAAA Oo oo O A4 IAD3 4 D15 asnapa 2 Ken Di GND TS IDENTIFIER D13 AG IADS 4 D12 A7 IAD6 5 GND A8 IAD7 D11 A9 IAD8 69 D10 Agape 8 68 D9 A11 IAD10 EN VpDEXT A12 IAD11 10 66 GND A13 IAD12 65 D8 GND 64 D7 IWR CLKIN ADSST 218x 63 D6 IRD SE TOP VIEW SS DSAL Vopr Not to Scale pais CLKOUT 160 GND GND 59 Vppint VDDINT 58 D3 ACK WR D2 IAD15 RD 56 D1 IAD14 BMS 155 DO IAD13 DMS 22 54 BG PMS 23 53 EBG SlSlklgisielslsislgdklSilslslslslallslsisilslslsis N 1 ono ooo c H jH Im w E TRELRTERSBSeLS kljs E2 gibis 5 zE oo eo wt gaa Heer a o lo a P zz Oz Ee E e oe E GC o Du Hop D ue e i 3 eks sa 9 D d o lec D ola alo gt Dm o ot x O Ole H D E Foe 03738 0 009 Figure 5 Pin Configuration for ADSST 218x in 100 Lead LQFP Rev 0 Page 10 of 24 GENERAL DESCRIPTION OF THE ADSST 73360LAR ADC The ADSST 73360LAR is a 6 channel input analog front end processor for general purpose applications including industrial power metering or multichannel analog inputs It features six 16 bit A D conversion channels each of which provides 76 dB signal to noise ratio over a dc to 4 kHz signal bandwidth Each channel also
20. features an input programmable gain amplifier PGA with gain settings in eight stages from 0 dB to 38 dB SIGNAL CONDITIONING SIGNAL SE CONDITIONING PGA SIGNAL e CONDITIONING PG A REFCAP REFERENCE REFOUT SIGNAL Se CONDITIONING POA VINN4 a SIGNAL Ge CONDITIONING POA O SIGNAL akan CONDITIONING PG A VINP1 ia SIGNAL PGA VINN1 a CONDITIONING KEES SIGNAL VINN2 LC CONDITIONING MINES ia SIGNAL VINN3 o CONDITIONING VINP4 IT SIGNAL CONDITIONING VINP5 SIGDAL VINN5 CONDITIONING VINES SIGNAL VINN6 CONDITIONING ADSST 73360LAR ADSST SALEM 3T The ADSST 73360LAR is particularly suitable for industrial power metering as each channel samples synchronously ensur ing that there is no phase delay between the conversions The ADSST 73360LAR also features low group delay conversions on all channels An on chip reference voltage is included with a nominal value of 1 2 V The ADSST 73360LAR is available in a 28 lead SOIC package pecmaron gt pecmaror gt sous SERIAL vo PORT out pecmaron gt pecmaron gt 03738 0 004 Figure 6 ADSST 73360LAR Functional Block Diagram Rev 0 Page 11 of 24 ADSST SALEM 3T SPECIFICATIONS ADSST 73360LAR AVDD 2 7 V to 3 6 V DVDD 2 7 V to 3 6 V DGND AGND 0 V fmc x 16 384 MHz fsc x 8 192 MHz fs 8 kHz Ta Tmn to Tmax unless otherwise noted Table 6 Paramete
21. ithm patent pending for phase compensation The ADSST SALEM 3T chipset based meter which is very effective and user friendly can be calibrated for phase compensation at three current points to cover the complete current range This also reduces the cost of the end product by reducing the cost of the sensing elements i e current transformers ACTIVE EXPORT a REACTIVE SIN 1 REACTIVE EXPORT ACTIVE COS 1 180 180 ABS REACTIVE IMPORT P Q QUADRANT SC QUADRANT IV QUADRANT II QUADRANT III REACTIVE SIN 1 90 d 270 ABS ADSST SALEM 3T EASE OF DESIGN Designing a complete meter using the ADSST SALEM 3T is very easy with the ADSST SALEM 3T DK developer s kit The kit in the UART mode enables a user to evaluate and test the computational element by connecting to a PC without building the complete hardware QUADRANT AND OTHER CONVENTIONS The metering data computed by the ADSST SALEM 3T chipset uses the following conventions for various parameters e Figure 2 gives the quadrant conventions used by the chipset e Import means power delivered from the utility to the user e Export means power delivered by the user to the utility e Total means total of all three phases Import and export are with reference to consumption U I Magnitude of voltage and current P Active Power U x I x cos Q Reactive Power U x I x sin KU Phase a
22. n Use Fl FO Flag In Flag Out FLO FL1 FL2 3 O Output Flags GND 10 Power and Ground 1RQ1 0 Edge or Level Sensitive Interrupts PWD 1 l Power Down Control Input SPORTO 5 1 0 Serial Port I O Pins SPORT 5 1 0 Serial Port I O Pins PWDACK 1 O Power Down Control Output Vopext 4 l External Voo 2 5 V or 3 3 V Power LQFP Vopext 7 l External Voo 2 5 V or 3 3 V Power Mini BGA Vopint 2 Internal Voo 2 5 V Power LQFP Vopint 4 Internal Voo 2 5 V Power Mini BGA Interrupt flag pins retain both functions concurrently If IMASK is set to enable the corresponding interrupts the DSP will vector to the appropriate interrupt vector address when the pin is asserted either by external devices or set as a programmable flag SPORT configuration determined by the DSP System Control register Software configurable Rev 0 Page 6 of 24 CLOCK SIGNALS Either a crystal or a TTL compatible clock signal can clock the ADSST 218x If an external clock is used it should be a TTL compatible signal running at half the instruction rate The signal is connected to the processor s CLKIN input When an external clock is used the XTAL input must be left unconnected Because the ADSST 218x includes an on chip oscillator circuit an external crystal may be used The crystal should be connected across the CLKIN and XTAL pins with two capacitors connected as shown in Figure 4 The capacitor values are dependent on the crystal type a
23. nal the use of an exter nal Schmitt trigger is recommended RECOMMENDED OPERATING CONDITIONS Table 3 Parameter Min Max Unit Von 2 37 2 63 V Voppr 2 37 3 60 V Vineur Vi 0 3 Vin 3 6 V Tame 0 70 C The ADSST 2185x is 3 3 V tolerant always accepts up to 3 6 V max Vin but voltage compliance on output Von depends on the input Vopext because Vou MAX Vooexr MAX This applies to bidirectional pins D0 D23 RFSO RFS1 SCLKO SCLK1 TFSO A1 A13 PFO PF7 and input only pins CLKIN RESET BR DRO DR1 PWD Rev 0 Page 7 of 24 ADSST SALEM 3T ADSST 218X ELECTRICAL CHARACTERISTICS Table 4 Parameter Test Conditions Min Typ Max Unit Vin High Level Input Voltage Voont Max 1 5 V Vin High Level CLKIN Voltage Voont Max 2 0 V Vu Low Level Input Voltage Von Min 0 7 V Von High Level Output Voltage 3 Vopext Min lon 0 5 mA 2 0 V Voneer 3 0 V lon 0 5 MA 2 4 V Vooext Min lon 100 HAD Vopext 0 3 V Vo Low Level Output Voltage gt Vpopext Min lo 2 MA 0 4 V l High Level Input Current Voont Max Vin 3 6 V 10 yA l Low Level Input Current Von Max Vin 0 V 10 yA lozu Three State Leakage Current Vue Max Vin 3 6 V8 10 uA loz Three State Leakage Current Vpopext Max Vin 0 V8 10 uA loo Supply Current Idle Voopnrt 2 5 V tck 15 ns 9 mA Von 2 5 V tx 13 3 ns 10 mA loo S
24. nd should be specified by the crystal manufacturer A parallel resonant fundamental frequency microprocessor grade crystal should be used A clock output CLKOUT signal is generated by the processor at the processor s cycle rate This can be enabled and disabled by the CLKODIS bit in the SPORTO autobuffer control register RRR CLKIN XTAL CLKOUT DSP 03738 0 003 Figure 4 External Crystal Connections ADSST SALEM 3T RESET The RESET signal initiates a master reset of the ADSST 2185x The RESET signal must be asserted during the power up sequence to assure proper initialization RESET during initial power up must be held long enough to enable the internal clock to stabilize If RESET is activated any time after power up the clock continues to run and does not require stabilization time The power up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid Von is applied to the processor and for the internal phase locked loop PLL to lock onto the specific crystal frequency A minimum of 2000 CLKIN cycles ensures that the PLL has locked but does not include the crystal oscillator start up time During this power up sequence the RESET signal should be held low On any subsequent resets the RESET signal must meet the minimum pulse width specification trsp The RESET input contains some hysteresis however if an RC circuit is used to generate the RESET sig
25. ngle from the standpoint of I with respect to U always positive in counterclockwise direction Phase U L1 0 Abs L2 240 Abs L3 120 Abs ACTIVE IMPORT 90 90 ABS ACTIVE CAPACITIVE LEAD ACTIVE COS 1 0 9 0 ABS ACTIVE INDUCTIVE LAG o 03738 0 002 Figure 2 Quadrant Conventions Rev 0 Page 3 of 24 ADSST SALEM 3T GENERAL DESCRIPTION OF THE ADSST 218X DSP The ADSST 218x is a single chip microcomputer optimized for digital signal processing DSP and other high speed numeric processing applications The DSP combines the ADSP 2100 family base architecture three computational units data address generators and a pro gram sequencer with two serial ports a 16 bit internal DMA port a byte DMA port a programmable timer flag I O exten sive interrupt capabilities and on chip program and data memory The ADSST 218x is fabricated in a high speed low power CMOS process Every instruction can execute in a single proc essor cycle The ADSST 218x s flexible architecture and comprehensive instruction set enable the processor to perform multiple opera tions in parallel In one processor cycle the ADSST 218x can e Generate the next program address e Fetch the next instruction e Perform one or two data moves e Update one or two data address pointers e Perform a computational operation POWER DOWN CONTROL MEMOR Y DATA ADDRESS GENERAT
26. oltage Min Typ Max Unit In Vn 15 V 0 1 0 2 Table 18 Starting Current Min Typ Max Unit 0 07 0 1 of In Rev 0 Page 19 of 24 ADSST SALEM 3T OUTLINE DIMENSIONS 1 60 MAX e 0 75 16 00 BSC SQ k 14 00 BSC SQ E 100 76 0 60 1 75 0 45 KE PIN 1 SEATING PLANE TOP VIEW 12 00 PINS DOWN REF 10 1 45 Bi sit 1 40 F 20 1 35 Gg WS 7 YI v H 3 5 25 51 Foe 26 50 015 SEATING 0 05 0 08 MAX 0 27 PLANE COPLANARITY 0 50 BSC gt al 0 22 VIEWA 0 17 ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS 026BED Figure 10 100 Lead Low Profile Quad Flat Package LQFP ST 100 Dimensions shown in millimeters LV 18 10 0 7126 17 70 0 6969 i H ny 6 28 15 7 60 0 2992 7 40 0 2913 4 ai 10 65 0 4193 10 00 0 3937 DH oad DH E 2 65 0 1043 0 75 0 0295 S 2 35 0 0825 sees 0 30 0 0118 0 10 0 0039 D sl je wie L 8 el ke COPLANARITY 700 0 51 0 0201 BEATING 0 33 0 0130 0 1 27 0 0500 0 10 0 31 0 0122 0 20 0 0079 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 11 28 Lead Standard Small Outline Package SOIC Wide Body RW 28 Dimensions shown in millimeters and
27. r Min Typ Max Unit Test Conditions REFERENCE REFCAP Absolute Voltage Vrercap 1 08 1 2 1 32 V REFCAP TC 50 ppm C 0 1 uF Capacitor Required from REFCAP to AGND2 REFOUT Typical Output Impedance 130 Q Absolute Voltage Vrerout 1 08 1 2 1 32 V Unloaded Minimum Load Resistance 1 kQ Maximum Load Capacitance 100 pF ADC SPECIFICATIONS Maximum Input Range at VIN 1 578 V p p Measured Differentially 2 85 dBm Nominal Reference Level at VIN 1 0954 V p p Measured Differentially 0 dBm0 6 02 dBm Absolute Gain PGA 0 dB 1 3 0 6 dB 1 0 kHz PGA 38 dB 0 8 0 8 dB 1 0 kHz Signal to Noise Distortion PGA 0 dB 76 dB 0 Hz to 4 kHz fs 8 kHz PGA 0 dB 71 76 dB 0 Hz to 2 kHz fs 8 kHz fin 60 kHz PGA 38 dB 58 dB 0 Hz to 4 kHz fs 64 kHz Total Harmonic Distortion PGA 0 dB 80 71 dB 0 Hz to 2 kHz fs 8 kHz fin 60 kHz PGA 38 dB 64 dB 0 Hz to 2 kHz fs 64 kHz fin 60 kHz Intermodulation Distortion 78 dB PGA 0 dB Idle Channel Noise 68 dB PGA 0 dB fs 64 kHz SCLK 16 MHz Crosstalk ADC to ADC 95 dB ADC1 at Idle ADC2 to ADC6 Input Signal 60 Hz DC Offset 30 30 mV PGA 0 dB Power Supply Rejection 55 dB Input Signal Level at AVDD and DVDD Pins 1 0 kHz 100 mV p p Sine Wave Group Delai 25 us 64 kHz Output Sample Rate 50 us 32 kHz Output Sample Rate 95 us 16 kHz Output Sample Rate 190 us 8 kHz Output Sample Rate Input Resistance at VIN 3 25 kos DMCLK 16 384 MHz Phase Mismatch 0 15 Degrees fin 1 k
28. s The excellent common mode rejection of the part will remove common mode noise on these inputs The analog and digital supplies of the ADSST 73360LAR are independent and separately pinned out to minimize coupling between analog and digital sections of the device The digital filters on the encoder section provide rejection of broadband noise on the power supplies except at integer multiples of the modulator sampling frequency The digital filters also remove noise from the analog inputs provided the source does not saturate the analog modulator However because the resolution of the ADSST 73360LAR s ADC is high and the noise levels from the ADSST 73360LAR are so low care must be taken with regard to grounding and layout The printed circuit board that houses the ADSST 73360LAR should be designed in such a way that the analog and digital sections are separated and confined to certain sections of the board The ADSST 73360LAR pin configuration offers a major advantage in that its analog and digital interfaces are connected on opposite sides of the package This facilitates the use of ground planes that can be easily separated as shown in Figure 8 ANALOG GROUND DIGITAL GROUND 03738 0 006 Figure 8 Ground Plane Layout as it gives the best shielding Digital and analog ground planes should be joined in only one place If this connection is close to the device it is recommended to use a ferrite bead inductor as shown in Figure 9
29. upply Current Dynamic Von 2 5 V tex 13 3 ns Tams 25 C 35 mA Vpont 2 5 V tek 15 ns Tame 25 C 38 mA loo Supply Current Power Down Von 2 5 V Tams 25 C in Lowest Power Mode 100 mA C Input Pin Capacitance 6 Vin 2 5 V fin 1 0 MHz Tams 25 C 8 pF Co Output Pin Capacitance 1213 Vin 2 5 V fin 1 0 MHz Tame 25 C 8 pF Bidirectional pins DO D23 RFSO RFS1 SCLKO SCLK1 TFSO TFS1 A1 A13 PFO PF7 Input only pins RESET BR DRO DR1 PWD 3Input only pins CLKIN RESET BR DRO DR1 PWD Although specified for TTL outputs all ADSP 2186 outputs are CMOS compatible and will drive to Vovext and GND assuming no dc loads Guaranteed but not tested Three statable pins AO A13 DO D23 PMS DMS BMS IOMS CMS RD WR DTO DT1 SCLKO SCLK1 TFSO TEST RFSO RFS1 PFO PF7 80 V on BR Idle refers to ADSST 218x state of operation during execution of IDLE instruction Deasserted pins are driven to either Voo or GND lop measurement taken with all instructions executing from internal memory 50 of the instructions are multifunction Types 1 4 5 12 13 14 30 are Type 2 and Type 6 and 20 are idle instructions Vin 0 V and 3 V For typical figures for supply currents refer to the Power Dissipation section Applies to LQFP package type 13Output pin capacitance is the capacitive load for any three stated output pin Rev 0 Page 8 of 24 ADSS
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