POST Error Code
Contents
1. ad Oo as as et Oo Oo Eoh Oo ss Oo el O Oo fe Oo Oo E Oo Ee eE SEEE Oo Oo NAID A DS o indicating the address line or bits that failed For example 2C 0002 means address line 1 bit one set has failed 2E 1020 means data bits 12 and 5 bits 12 and 5 set have failed in the lower 16 bits Note that error 30 cannot occur on 386SX systems because they have a 16 rather than 32 bit bus The BIOS also sends the bitmap to the port 80 LED display It first displays the checkpoint code followed by a delay the high order byte another delay and then the low order byte of the error It repeats this sequence continuously P801 Debug Card 15 AMI POST Error Code AMIBIOS 071596 VERSION 6 24 CHECK PONT LIST Following is checkpoint list in AMIBIOS in order of execution Check point Description Uncompressed INIT code checkpoints Description NMI IS Disabled CPU ID saved ae Init code Checksum verification starting To do DMA INIT Keyboard controller BAT test start memory refresh and going to 4GB flat mode To start Memory sizing To comeback to real mode Execute OEM patch Set stack E000 ROM enabled Init code is copied to segment 0 and control to be transferred to segment 0 Control is segment 0 To check lt CTRL gt lt HOME gt key and verify main BIOS checksum D3 D4 D5 If either lt CTRL gt lt HOME gt is pressed or main BIOS checksum is bad go to check point E0 else go to check2. and execute CMOS setup Returned form CMOS setup program and screen is cleared About to do programming after setup Programming after setup complet Going to display power on screen message irst screen message displayed lt WAIT gt message displayed etup options programming after CMOS setup about to start oing to hard disk controller reset ard disk controller reset done Floppy setup to be done next loppy setup complet Hard disk setup to be done next it of different BUSes optional ROMs form C800 to start Going to do any init before C800 optional ROM control Any Init before C800 optional ROM control is over Optional ROM check and control will be done next T Optional ROM control is done About to give control to do any required processing after optional ROM returns control and enable external cache Any initialization required after optional ROM test over Going to setup timer data area and printer base address Return after setting timer data area and printer base address Going to set the RS 232 base address Return after RS 232 base address Going to do any initialization before Coprocessor is over Required initialize the Coprocessor next Coprocessor initialized Going to do any initialization after Coprocessor test Initialization after Coprocessor test is complete Going to check exit Keyboard keyboard ID and num lock Keyboard ID command to be Going to display complete Soft error disp
3. Ss gt 1 2 O O i SSS else ood od Id NO CRIN oT gt gt gt gt gt gt gt eRe wW 2 gt 1 ABI Ne Sa S wW D gt w w w w w Q olaga SSS EY afale wJ SJN Slo EE on Do C7h P801 Debug Card Description Determine number of ATA drives optional Initialize hard disk controllers nitialize local bus hard disk controllers ump to UserPatch2 uild MPTABLE for multi processor boards nstall CD ROM for boot lear huge ES segment register ix up Multi Processor table Search for option ROMs One long two short beeps on checksum failure S a z JE janr PJE ale Kea Qjo 5 g ae e O HE C 6 So Initialize note dock optional Initialize note dock late 14 POST hex d ees orce check optional Redirect Int 13h to Memory Technologies Devices such as ROM RAM PCMCIA and serial disk Q o w Q o0 5 ele ee Q zs gt The following are for boot block in Flash ROM AIQIQ giez ieg ie S BY QO N SST S oS m n gt Check force recovery boot Checksum BIOS ROM ti J gt Go to BIOS Set Huge Segment Initialize Multi Processor z oO a gt tH gt If the BIOS detects error 2C 2E or 30 base 512K RAM error it displays an additional word bitmap oxx tot tot ot Gd ed ips gs gt ps N D E OW 5 PTj K a Beeps ho i er E 2
4. but we will not be responsible for any misusing of the product Therefore we strongly urge you to read the manual first before using the product Award http www award com Phoenix http www phoenix com AMI http www ami com P801 Debug Card 22
5. checkpoints are output to post 80h as WORD to identify the routines under execution These are WORD checkpoints the LOW BYTE of checkpoint is the system BIOS checkpoint from where the control is passed to the different BUS routines and the HIGH BYTE of checkpoint is the indication of which routine is being executed in different BUSes The details of HGH BYTE of these checkpoints are as follow HIGH BYTE XY The upper nibble x indicates the function is being executed x can 0 to 7 0 fun 0 disable all devices on the BUS concerned 1 fun 1 static devices init on the BUS concerned 2 fun 2 output device init on the BUS concerned 3 fun 3 input device init on the BUS concerned 4 fun 4 IPL device init on the BUS concerned 5 fun 5 general device init on the BUS concerned 6 fun 6 error reporting for the BUS concerned 7 fun 7 add on ROM init for all BUSes the lower nibble Y indicates the BUS on which the different routines are being executed Y con be from 0 to 5 0 Generic DIM Device initialization Manager 1 On board system devices 2 ISA devices 3 EISA devices 4 ISA PnP devices 5 PCI devices P801 Debug Card 21 Notice Dear Customer Thank you for purchasing the P801 PC Debug Card Please read user s manual thoroughly before you install and use the debug card The product that you have purchased comes with two year warranty
6. point D7 D7 To pass control to Interface Module Main BIOS runtime code is to be decompressed D8 Control to be passed to main BIOS in shadow RAM Boot Block Recovery Code Check Points On Board Floppy Controller if any is intialzed El To star base 512K memory test E2 To initialize interrupt vector table E6 To enable floppy and timer IRQ enable internal cache ED Initialize floppy drive EE Start looking for a diskette in drive A and read 1st sector of the diskette EF loppy read error FO Fl F2 F3 F4 F5 FB FC FD FF AMIBOOT ROM file not present in root directory Start reading FAT table and analyze FAT to find the cluster occupied by AMIBOOT ROM file tart reading AMIBOOT ROOM file cluster by cluster lt AMIBOOT ROM file not of proper size Disable internal cache Detect Flash type present Erase Flash Program Flash FF _ Flash program successful BIOS is restart Runtime code is uncompressed in F000 shadow ram 06 POST code tobe uncompressed _ o Z o 08 e FO tart searching AMIBOOT ROM file in root directory CPU init and CPU data area init to be done CMOS checksum calculation to be done next P801 Debug Card 16 POST hex Any initialization before Keyboard BAT to be done next KB controller I B free To issue the BAT command to Keyboard controller To init CMOS if Init CMOS is every boot is set or lt END gt key
7. 2 Initialize L2 cache for P6 class CPU amp program CPU with proper cacheable range 3 Initialize the APIC for P6 class CPU 4 On MP platform adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical Ah h h h Fh Ah h h h Oh Reserved Initialize USB Keyboard amp Mouse Reserved est all memory clear all extended memory to 0 ear password according to H W jumper Optional eserved Display number of processors multi processor platform Reserved 57h 1 Display PnP logo 2 Early ISA PnP initialization Assign CSN to every ISA PnP device Reserved Initialize the combined Trend Anti Virus code Reserved 5 Optional Feature Show message for entering AWDFLASH EXE from FDD optional 5Ch Reserved B 5D 1 Initialize Init_Onboard_Super_IO o 2 Initialize Init_Onbaord_AUDIO Reserved 6 Okay to enter Setup utility i e not until this POST stage can users es enter the CMOS setup utility Reserved Reserved Reset keyboard if Early_Reset_KB is not defined Reserved Initialize PS 2 Mouse Reserved 67h Prepare memory size information for function call INT 15h ax E820h Reserved Turn on L2 cache Reserved P801 Debug Card POST hex 6B Program chipset registers according to items described in Setup amp Auto configuration table D 1 Assign resources to all ISA PnP devices E 2 Auto assign ports to onboard COM ports if the correspondin
8. P801 PC Debug Card User s Manual TRADEMARK All products and company names are trademarks or registered trademarks of their respective holders These specifications are subject to change without notice Copyright Notice This document is copyrighted 2002 All rights are reserved The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice No part of this manual may be reproduced copied translated or transmitted in any form or by ny means without the prior written poms 00 of the original manufacturer Information provided in his manual is intended to be accurate and reliable However the original manufacturer assumes no responsibility for its use nor for any mnngements upon the rights of third parties which may result rom its use Acknowledgements Award trademarks of Award software Inc Phoenix trademarks of Phoenix Technologies Ltd AMI trademarks of American Megatrends Inc All other product names or trademarks are properties of their respective owners P801 Debug Card 1 P801 2 LED OO CBI uj ia SaR i i psor LS l O ers e PCIRST P901 M Via MADE IN TAIWAN P801 Debug 80 Port Card P801 4 LED OO CBI uj we 2 lt a bea psor O ag PCIRST porRsre n sea a aS MADE IN TAIWAN P801 Debug 80 Port Card P801 M4LED C0 cel ui ae SAR poo enoencaaceenenas
9. g P801 Debug 80 Port Card P801 M V1 1 MADE IN TAIWAN L P801 Debug Card reverse side VECS PCIRST P801 Display Daughter Board P801 II I S Ni VOCS a e PCI RST i caz P801 M V1 1 P801 Debug 80 Port Card 1 On board Display DP1 DP2 2 Optional DP3 DP4 on the reverse side or pin header on front side 3 PCI RST VCC 5V VCC 12V VCC 3VSB LED Display 4 P801 board will be to detect PCICLK some board P4 have to disable BIOS manual item Frequency Voltage Control Auto Detect PCI CLK AWARD POST Enor Code SOFTWARE BIO S6 00 Revision 10 NOTE EISA POST codes are typically output to port address 300h ISA POST codes are output to port address 80h CFh COh Early chipset initialization Disable shadow RAM Disable L2 cache socket 7 or below Program basic chipset registers Detect memory Auto detection of DRAM size type and ECC Auto detection of L2 cache socket 7 or below Expand compressed BIOS code to DRAM Call chipset hook to copy BIOS back to E000 amp F000 shadow RAM Initial Superio_Early_Init switch 1 Blank out screen 2 Clear CMOS error flag 1 Clear 8042 interface 2 Initialize 8042 self test 08h 1 Test special keyboard controller for Winbond 977 series Super VO chips 2 Enable keyboard interface 09h Reserved P801 Debug Card 3 POST hex Ah 1 Disable PS 2 mouse interface optio
10. g item in Setup is set to AUTO 1 Initialize floppy controller 2 Set up floppy related fields in 40 hardware 70h Jih 72h Reserved o O 73h Reserved J4h Reserved S fE 75h Detect amp install all IDE devices HDD LS120 ZIP CDROM h h h h Optional Feature Enter AWDFLASH EXE if AWDFLASH EXE is found in floppy drive ALT F2 is pressed h h h h Detect serial ports amp parallel ports F Detect amp install co processor hit HDD write protect TF Switch back to text mode if full screen logo is supported If errors occur report errors amp wait for keys n If no errors occur or F1 key is pressed to continue Clear EPA or customization logo E8POST ASM _ starts 2h 8 1 Call chipset power management hook i 2 Recover the text fond used by EPA logo not for full screen logo 3 If password is set ask for password 85h 1 USB final Initialization OS ee NET PC Build SYSID Structure 89h 1 Assign IRQs to PCI devices 2 Set up ACPI table at top of the memory P801 Debug Card 7 POST hex 8Bh 1 Invoke all ISA adapter ROMs 8Ch 8Dh 1 Enable Disable Parity Check according to CMOS setup 2 APM Initialization Enable L2 cache Program Daylight Saving Program boot up speed Chipset final initialization Power management final initialization Clear screen amp display summary table Program K6 write allocation Program P6 class write combining 1 Bui
11. ialize Initialize floppy disk controller and any drives Floppy Drive Controller Initialize Hard Initialize hard disk controller and drives Controller Detect amp _ Initialize any serial and parallel posts also game port Parallel Ports 45 Detect amp Initialize math coprocessor Coprocessor 46 Reserved Reserved 4D 4E Manufacturing Reboot if Manufacturing POST Loop pin is set Otherwise POST Loop or display any messages I e any non fatal error that were Display detected during POST Messages jand enter setup 4F Security Ask password security optional Check 50 3 50 Write CMOS Write all CMOS values back to RAM and clear screen 5 Pre boot Enable parity checker Enable NMI Enable cache before boot Enable 52 Initialize Initialize any option ROMs present from C8000h to EFFFFh Option ROMs NOTE When FSCAN option is Enabled ROMs initialize form C8000h to E7FFFh 5 Initialize Time Initialize time value in 40h BIOS area Fi aa co Bl ie list cca Protect 61 Setup Boot Set system speed for boot PON pee ee Num Lock Set low stack Boot via INT 19h BO Spurious If interrupt occurs in protected Bl Unclaim If unmasked NMI occurs display Press F1 to disable F1 NMI NMI F2 reboot El Setup Pages El Page 2 etc EF The information in this document is subject to change without notice and should not be considered as a commitment by Award Although Award will
12. is Pressed Going to disable DMA and Interrupt controllers Video display is disable and port B is initialized Chipset init about to start Memory Refresh line is toggling Going to check 15us ON OFF time Read 8042 input port and disable Megakey GreenPC feature Make necessary Going for monochrome mode and color mode setting Different BUSes init system static output devices to start if present To look for optional video ROM and give control To give control for any setup required before optional video ROM check To give control to do any processing after video ROM returns control If EGA VGA not found then do Display memory R W test Any initialization before setting video mode to be done EGA VGA not found Display memory R W test about to begin Display memory R W test or retrace checking failed To do alternate Display memory R W test Display mode set Going to display the power on message Display different BUSes initialization error messages please see Appendix for details of different BUSes New cursor position read and saved To display the Hit lt DEL gt message To prepare the descriptor tables 42 To enter in virtual mode for memory test 43 To enable interrupts for diagnostics mode Display memory R W test passed About to look for the retrace checking Alternate Display memory R W test passed To look for the alternate Display retrace checking Video display checking over Dis
13. isplayed memory size for relocation shadow 4 4 Memory test above 1M to follow 5 Memory testing initialization above 1M complete O lessee mean seein o OOOO 5 Memory size information is saved CPU registers are saved O feadmoepayi nmt o nR Line and disable parity NMI Going to adjust memory size depending on relocation shadow 0 O F k Hit lt DEL gt message cleared lt WAIT gt message displayed DMA 2 base register test passed To program DMA unit 1 and 2 DMA unit 1 and 2 programming over To initialize 8259 interrupt controller Extended NMI sources enabling is Progress Memory size adjusted or relocation shadow Going to clear Hit lt DEL gt message 7 Keyboard test started clearing output buffer checking for stuck key to issue keyboard reset command a Keyboard reset error stuck key found To issue keyboard controller 4 5 7 8 9 C D F 1 2 3 4 7 8 9 2 5 F 81 interface test command P801 Debug Card 18 POST hex Description Keyboard controller interface test over To write command byte and Init circular buffer Command byte written Global data init done To check for Lock key Lock key checking over To check for memory size mismatch with CMOS Memory size check done To display soft error and Check for password or bypass setup Password checked About to do programming before setup Programming before setup complete To uncompress SETUP code
14. ith power on BIOS defaults ia default Initialization 1 Memory OEM specific Test to size on board memory resence Test p Early shadow OEM Specific Early shadow enable for fast boot C6 Cache External cache size detection test presence Early chip set initialization memory presence test OEM chip set memory __ routines Clear low 64k of memory Test first 64k memory arly Cache Cyrix CPU initialization Cache Initialization Initialization A Initialize first 120 interrupt vectors with SPURIOUS INT H DLR Vector Table and initialize INT 00b 1Fh according to INT TBL Test CMOS Test CMOS RAM Chceksum if bad or insert key pressed load RAM Checksum C Initialize Detect type of keyboard controller optional Set NUM COCK P Sies of ideo in use Pawe sie Video adage s Video of video in use Detect and Initialize Video Adapter E Test Video Test video memory write sign on message to screen Setup hea Memory _ shadow RAM Enable shadow According to Setup ne Controller 0 10 Tes DMA BIOS checksum test keyboard detect and initialization ss ep page registers P801 Debug Card 9 POST hex 14 Test Timer Test 8254 Timer 0 Counter 2 Coomera PREM 15 Test 8259 1 Verify 8259 channel 1 masked interrupts by alternately turning oe MASK Bits _ off and on the interrupt lines Test Stuck Turn off interrupt then verify no interrupt is on 8259 Test 8259 Force an interrupt and verify the Inte
15. lay complete Going to set keyboard typematic rate Keyboard typematic tate set To program memory WAIT STATES Going to enable parity NMI NMI and parity enable Going to do any initalization Required before giving control to optional ROM at E000 Initialization before E000 ROM control voer A Returned form E000 ROM control Going to do any initialization required after E000 optional ROM control is over P801 Debug Card 19 82 83 84 85 87 88 8B 8C 8F 91 95 97 9A 9C 9E A2 A3 A4 AS A7 A8 9 AA Initialization after E000 optional ROM control is over ompi depay te yem eongoa n O To uncompress DMI data and execute DMI POST init BO System configuration is displayed C Going to copy any code to specific area Copying of code to specific area done Going to give control to INT 19 boot loader AMI POST Enor Code AMIBIOS 071596 VERSION 6 24 CHECK PONT LIST APPENDIX The system BIOS gives control to the different BUSes at checkpoints to do Various tasks on the different BUSes CHECK POINT DESCRIPTION OF CHECK POINT POST hex 2A Different BUSes init system start output devices to start if present 3 9 39 Display different BUSes initialization error messages Init of different BUSes optional ROMs from C800 to start Different BUSes init input IPL general devices to start if present 8 5 P801 Debug Card 20 While control is inside the different BUS routines
16. ld MP table 2 Build amp update ESCD 3 Set CMOS century to 20h or 19h 4 Load CMOS time into DOS timer tick 5 Build MSIRQ routing table FFh Boot attempt INT 19h AWARD POST Enror Code SOFTWARE BIOS4 51G Revision 10 NOTE EISA POST codes are typically output to port address 300h ISA POST codes are output to port address 80h POST hex CO Tum off OEM specific cache control chipset Cache Processor Processor status IFLAGS Verification Test Tests the following processor status fllages Carry zero sign overflow The BIOS sets each flag verifies they are set then turns each flag off and verifies it is off 2 Processor Read Write Verify all CPU registers except ss sp andbp Test2 with date pattern FF and 00 P801 Debug Card 8 POST hex 3 Disable NMI PIE AIE UEI SQWV Disable Video parity checking DMA Reset mach coprocessor Clear all page registers CMOS shutdown byte Initialize timer 0 1 and 2 including set EISA timer to a known state Initialize DMA controllers 0 and 1 Initialize interrupt controllers 0 and Initialize EISA extended registers Test Memory RAM must be periodically refreshed to keep the memory from Refresh decaying This function is working properly Toggle 5 Blank video keyboard controller initialization Initialize 7 Test CMOS Verifies CMOS is working correctly detects bad battery Interface and Battery Status BE Chipset Programming chipset Register w
17. make every effort to inform users of substantive errors Award disclaims all liability for any loss or damage resulting from the use of this document or any hardware or software described herein including without limitation contingent special or incidental liability Copyright 1999 by Award Software International Inc All rights reserved P801 Debug Card 11 Code oloo OAIN DIS SS gt So Oololo SNE D Do Q y ojlo slg a gt BIL QIN O a gt NINN elelele SSIS Oe 2 3 gt gt S gt gt N o0 a gt Q MIs sep E N rT gt Q WW W G2 Go Vo Go Go J ZLS eY 5o SISS P A g P wo a P r a POST Error Code BIO S4 00 Release 6 x C Beeps SSS Werfy Real Mode SSCS sable Nor Maskabie interrupt NMI S e SSCS initialize system hardware sable shadow and execute code from the ROM nate chipset with initial POST valus TT JsetnPOstfag SSS initialize CPU registers OOOO Finnabie CPU cache SSS initialize caches to inital POST values intatize 70 component SSS ina Tinta o Eo iniiai Tina 1 2 2 3 BIOS ROM checksum POST hex Initialize the local bus IDE initialize cache before memory Auto sae 8254 timer inigalizaon SSS 8337 DMA controller initialization Reset Programmable Interrupt Controller e ES segment registert046B Auto size DRAM Initialize POST Memory Manager ___ etear 512 kB ba
18. nal 2 Auto detect ports for keyboard amp mouse followed by a port amp interface swap optional 3 Reset keyboard for Winbond 977 series Super I O chips Bh OCh Reserved OCh eserved 0 OB OD Reserved OE OF Reserved 10h Auto detect flash type to load appropriate flash R W codes into the ne run time area in F000 for ESCD amp DMI support Reserved Use walking 1 s algorithm to check out interface in CMOS circuitry Also set real time clock power status and then check for override Reserved 14h Program chipset default values into chipset Chipset default ae values are MODBINable by OEM customers eserved 16h Initial onboard clock generator if Early_Init_Onboard_Generator Ce is defined See also POST 26h eserved 18h Detect CPU information including brand SMI type Cyrix or ee Intel and CPU level 586 or 686 Reserved Reserved 1 B Initial interrupts vector table If no special specified all H W interrupts are directed to SPURIOUS_INT_HDLR amp S W interrupts to SPURIOUS_soft_HDLR h h Test FOOOh segment shadow to see whether it is R W able or not If test fails keep beeping the speaker h 1Ch Reserved Initial EARLY_PM_INIT switch eserved Load keyboard matrix notebook platform M initialization notebook platform Reserved 23h 1 Check validity of RTC value e g a value of 5Ah is an invalid value for RTC minute 2 Load CMOS settings into BIOS stack If CMOS checksum fails use defa
19. play mode to be set next Different BUSes init input IPL general devices to start if present please see Appendix for details of different BUSes 0C 0E OF 10 i 12 13 14 19 TA 23 24 25 27 28 2A 2B 2C 2D 2E 2F 30 31 32 34 37 38 39 3A 40 42 43 P801 Debug Card 17 POST hex 44 To initialized data to check memory wrap around at 0 0 Data initialized Going to check for memory wrap around at 0 0 Co and finding the total system memory size Memory wrap around test done Memory size calculation over About to go for writing patterns to test memory 4 Patterns to be tested written in extended memory Loe Going to write patterns in base 640K memory Going to findout amount of memory below 1M memory 4 Amount of memory below 1M found and verified ae Going to findout amount of memory above 1M memory 4B Amount of memory above 1M found and verified at Check for soft reset and going to clear memory below 1M for sort reset If power on go to check point 4Eh 4 Memory below 1M cleared SOFT RESET Going to clear a er ee Memory above 1M cleard SOFT RESET Going to save the memory size Go to check point 52h 4E Memory test started NOT SOFT RESET about to display the first eo ee 64K memory size Memory size display started This will be updated during memory test Going for sequential and random memory test 50 Memory testing initialization below 1M complete at Going to adjust d
20. rrupt occurred Interrupt Functionality Test Stuck Verify NMI can be cleared NMI Bits Parity IO Check Display CPU Display CPU clock clock F Set EISA If EISA non volatile memory checksum is good execute Mode EISA initialization if not execute ISA tests an clear EISA node flag Test EISA Configuration Memory Integrity checksum a communication Interface 0 Enable Slot O Initialize slot 0 system board Enable Slots Initialize slots 1 through 15 1 15 Size Base and size base memory form 256k to 640k and extended memory Extended above IMB Memory Test Base and Test base memory from 256k to 640k and extended memory Extended above 1MB Using various patterns NOTE This test is skipped in EISA mode and can be skipped with ESC key in ISA mode Test EISA If EISA Mode flag is set then test EISA memory found is slots Initialization NOTE This test is skipped in ISA mode and can be skipped with ESC key in ISA mode Setup Enabled Setup Enabled Initialize amp Detect if mouse is present initialize mouse install interrupt stall Mouse vectors 1A N ia b 2 1E i _20 N N olm T 31 Ww W ef el see e e e 5 lt 5 Ke Setup Cache nitialize cache controller Controller Reserved Chipset Program chipset registers with setup values Initialization Display Display virus protect disable or Enable BF 40 P801 Debug Card 10 41 Init
21. seRAM SSCS Enable cache before system BIOS shadow Test CPU bus clock frequency fWarmstartshutdown _ o S O Shadow system BIOSROM _ o O fAmosizecache o Oo fe O POST device initialization Initialize Phoenix Dispatch Manager P801 Debug Card 12 POST hex Code Beeps S O QuietBoot start optional Shadow video BIOS ROM 2 2 3 1 IENEN ENENENEN QSS RS a ieg SS gt gt P ee P 5 a Nn D AJ NI Ee on D y Nn Nn 3 Nn o0 ey Mu On Doin EE gt ON N D O D 2 nN o gt a gt DIN oo as Enable external and CPU caches Setup System Management Mode SMM area nN O D Display external L2 cache size Load custom defaults optional alalale a Oy Z Display possible high address for UMB recovery D Display error messages Check for configuration errors Check for keyboard errors alul alan JIAIcSIN 5 o D 5 Set up hardware interrupt vectors o0 o0 eg Disable onboard Super I O ports and IRQs Late POST device initialization Detect and install external RS232 ports o0 m gt P801 Debug Card 13 Display shadow area message Initialize Intelligent System Monitoring Initialize coprocessor if present OO CO CO CO Niu BI Ww oo gt 8Ah OO CO O 00 POST hex Code T O oo 00 o0 S Q DIS o gt a O O 0 O OM OTN O nN E O O oo
22. ult value instead Prepare BIOS resource map for PCI amp PnP use If ESCD is valid take into consideration of the ESCD s legacy information 25h Early PCI Initialization Enumerate PCI bus number Assign memory amp I O resource Search for a valid VGA device amp VGA BIOS and put it into C000 0 P801 Debug Card 4 POST hex 26h 1 If Early_Init_Onboard_Generator is not defined Onboard clock generator initialization Disable respective clock resource to empty PCI amp DIMM slots 2 Init onboard PWM 3 Init onboard H W monitor devices Initialize INT 09 buffer 1 Program CPU internal MTRR P6 amp PID for 0 640K memory address 2 Initialize the APIC for Pentium class CPU 3 Program early chipset according to CMOS setup Example onboard IDE controller 4 Measure CPU speed 2Ah 2Bh 2Ch Reserved Invoke Video BIOS R 2 2 2 2Ch 2 2 2 9h Ah Bh Dh 1 Initialize double byte language font Optional 2 Put information on screen display including Award title CPU type CPU speed full screen logo 30h Ah h Dh h 0 2 4 eserved eserved 30h 33h Reset keyboard if Early_Reset_KB is defined e g Winbond 977 cd series Super I O chips See also POST 63h Serv P801 Debug Card 5 POST hex Description 49h 1 Calculate total memory by testing the last double word of each 64K page 2 Program write allocation for AMD K5 CPU Reserved E D 4 1 Program MTRR of M1 CPU
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