XC6SLX150 X2 Coprocessor Module User Manual
Contents
1. The XC6SLX150 X2 Coprocessor Module will be supplied un programmed You will need a programming cable to program the XC6SLX150 X2 Coprocessor Module for example the Enterpoint Prog2 parallel port programming cable or the Enterpoint Prog3 USB port programming cable You will also need a programming adapter for the Enterpoint programming cables because the JTAG connector on the module is a 6x2 1 27mm header The Xilinx toolset required to program the XC6SLX150 X2 Coprocessor Module depends upon the Spartan6 devices fitted to the board If your XC6SLX150 X2 Coprocessor Module is fitted with LX150 devices standard version it will require the full Xilinx toolset to build a design If you have a custom version fitted with an LX75 device or smaller it is supported by the free ISE Webpack ISE Version11 1 SP4 or later is required available from Xilinx This provides all the tools to enter and build a design Using this tool in conjunction with your programming cable you will also be able to program the Spartan 6s and the supporting SPI Flash that are on the XC6SLX150 X2 Coprocessor Module ISE Webpack can be obtained directly from the Xilinx website at http www xilinx com ise Registration will be necessary to complete the download The full ISE toolset can also be purchased from the Xilinx website Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 5 FPGAs The XC6SLX150 X2 Coprocessor Module supports Spartan 6 devices in2. point d ASIC Design XC6SLX150 X2 Coprocessor Module User Manual Issue 1 0 Foreword PLEASE READ THIS ENTIRE MANUAL BEFORE PLUGGING IN OR POWERING UP YOUR XC6SLX150 X2 Coprocessor MODULE Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 1 PLEASE TAKE SPECIAL NOTE OF THE WARNINGS WITHIN THIS MANUAL Trademarks Spartan 6 ISE Webpack EDK COREGEN Xilinx are the registered trademarks of Xilinx Inc San Jose California US Contents Foreword 2 Trademarks 2 Introduction 3 XC6SLX150 X2 Coprocessor Module 4 FPGA 6 CPLD 7 SPI FLASH 9 DIL HEADERS 11 OSCILLATOR 14 POWER CONNECTIONS 15 BATTERY 17 POWER REGULATORS 18 PROGRAMMING XC6SLX150 X2 Coprocessor Module 19 MECHANICAL 23 Medical and Safety Critical Use 24 Warranty 24 Support 24 Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 2 Introduction The Enterpoint XC6SLX150 X2 Coprocessor Module is a Spartan 6 FPGA based module offering a highly powerful flexible and low cost approach to extending the performance and processing power of our range of development boards It can be plugged into our Raggedstone2 Raggedstone3 or Broaddown series boards It can also be used as a stand alone module using its 0 linch pitch header pins to interface to a user s power circuit gi S HEADER TOP oo CE 20 66 wwwenterpoint co uk OO c 2011 Enterpoin
3. Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 17 POWER REGULATORS The XC6SLX150 X2 Coprocessor Module has one voltage regulators supplying 1 2V WARNING REGULATORS CAN BECOME HOT IN NORMAL OPERATION ALONG WITH THE BOARDS THERMAL RELIEF PLEASE DO NOT TOUCH OR PLACE HIGHLY FLAMABLE MATERIALS NEAR THESE DEVICES WHILST THE XC6SLX150 X2 Coprocessor MODULE IS IN OPERATION A Micrel MIC22950 regulator supplies 1 2V with a maximum current available of 10A This is used for the core voltage of the FPGAs Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 Programming XC6SLX150 X2 Coprocessor Module The programming of the FPGA and SPI Flash parts on the XC6SLX150 X2 Coprocessor Module is achieved using the JTAG interface The JTAG connector on the XC6SLX150 X2 Coprocessor Module is a 1 27mm pitch 6x2 header and will require an adapter to be used with standard Enterpoint or Xilinx programming cables The pinout of the JTAG connector is shown below Top layer PCB trackwork showing JTAG connector pinout The JTAG signals are routed to the following pins on the CPLD These signals can be routed to pins on the DIL headers by loading a suitable build into the CPLD if you wish to program the Coprocessor module from the host board JTAG SIGNAL CPLD PIN TDI 11 TDO 12 TCK 13 TMS 10 The Spartan 6 series needs to be programmed using ISE 11 or higher Versions of ISE prior to 11 do not support Spa
4. OV 3 3V CONTROL4 CPLD 61 5 IO_L34P_0 FPGA1 B10 OV 3 3V IO_L14P_2 FPGAI AAI8 6 IO_L34N_0 FPGAI A10 OV 3 3V IO_L14N_2 FPGA1 AB18 7 IO_L8P_0 FPGA1 CH OV 3 3V IO_L48P_2 FPGAI Y7 8 IO_L8N_0 FPGA1 A9 OV 3 3V IO_L48N_2 FPGA1 AB7 9 IO_L6P_0 FPGAI B8 OV 3 3V I0_L49P_2 FPGAI AA6 IO_L6N_0 FPGA1 A8 OV 3 3V IO_L49N_2 FPGAI AB6 IO_L5P_0 FPGA1 C7 OV 3 3V IO_L57N_2 FPGAI AA4 IO_L5N_0 FPGA1 A7 OV 3 3V IO_L57N_2 FPGAI AB4 IO_L4P_0 FPGAI B6 OV 3 3V IO_L64N_2 FPGA1 AA2 IO_L4N_0 FPGA1 A6 OV 3 3V IO_L64N_2 FPGAI AB2 CSO_SPI 2 PIN N CPLD 16 OV 3 3V CSO_SPI_1_PIN_N CPLD 58 WRITE _2 U14 OV 3 3V WRITE_1 U14 DIN_FLASH2 AA20 OV 3 3V DIN_FLASHI AA20 DOUT_FLASH2 AB20 OV 3 3V DOUT FLASH AB20 CCLK_FLASH2 Y21 OV 3 3V CCLK_FLASHI Y21 HOLD 2 U13 OV 3 3V HOLD_1 U13 IO_L37P_0 FPGA2 B12 OV 3 3V I0_L31P_2 FPGA2 AAI2 IO_L37N_0 FPGA2 Al2 OV 3 3V IO_L31P_2 FPGA2 AB12 IO_L35P_0 FPGA2 Cll OV 3 3V IO_L32P_2 FPGA2 Y11 IO_L35N_0 FPGA2 All OV 3 3V I0_L32P_2 FPGA2 ABI1 IO_L34P_0 FPGA2 B10 OV 3 3V IO_L41P_2 FPGA2 AA10 IO_L34N_0 FPGA2 A10 OV 3 3V IO_L41N_2 FPGA2 AB10 IO_L8P_0 FPGA2 C9 OV 3 3V I0_L43P_2 FPGA2 Y9 IO_L8N_0 FPGA2 A9 OV 3 3V IO_L43N_2 FPGA2 AB9 IO_L6P_0 FPGA2 B8 OV 3 3V IO_L45P_2 FPGA2 AAN IO_L6N_0 FPGA2 A8 OV 3 3V IO_L45N_2 FPGA2 AB8 It should be noted that the pins on the XC6SLX150 X2 Coprocessor Module should be treated with respect The XC6SLX150 X2 Coprocessor Module is usually supplied with an extra row of pin socket headers to protect the row of pin
5. high M1 low PROG_B high and to route each CSO_B signal from the SPI flash device to the CSO_B pin of its FPGA ie link from pin 1 output to pin 39 input and pin 31 output to pin 49 input The DONE and INIT_B signals on each FPGA are pulled up by fixed resistors The following VHDL code achieves this Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 LIBRARY IEEE USE IEEE STD_LOGIC_1164 ALL USE IEEE STD_LOGIC_ARITH ALL USE IEEE STD_LOGIC_UNSIGNED ALL ENTITY TOPLEVEL IS PORT CSO_B_FPGAI IN STD LOGIC CS FROM FPGAI CSO_B_FPGA2 IN STD_LOGIC CS FROM FPGA2 CSO_SPI_1_N OUT STD_LOGIC CS TO SPI FLASH 1 CSO_SPI_2_N OUT STD_LOGIC CS TO SPI FLASH 2 MO_FPGAI OUT STD_LOGIC MO_FPGA2 OUT STD_LOGIC M1_FPGAI OUT STD LOGIC M1_FPGA2 OUT STD_LOGIC PROG_B_FPGAI OUT STD_LOGIC PROG_B_FPGA2 OUT STD_LOGIC END TOPLEVEL ARCHITECTURE A0 OF TOPLEVEL IS BEGIN MO_FPGAI lt 1 MO_FPGA2 lt 1 M1_FPGAI ss OU M1_FPGA2 lt 0 CSO_SPI_2_N lt CSO_B_FPGA2 CSO_SPI_I1_N lt CSO_B_FPGAI PROG_B_FPGAI lt 1 PROG_B_FPGA2 lt 1 END AO In order to route the JTAG signals to the DIL headers Right hand side pins 1 to 4 the following lines will need to be added Add to the PORT declaration TMS OUT STD_ LOGIC TCK OUT STD LOGIC TDO IN STD LOGIC TDI OUT STD LOGIC CONTROLI IN STD LOGIC CONTROL2 OUT STD LOGIC CONTROL3 IN STD LOGIC CON
6. it is used in any medical or safety critical application Warranty The XC6SLX150 X2 Coprocessor Module comes with a 90 day return to base warranty Do not attempt to solder connections to the XC6SLX150 X2 Coprocessor Module Enterpoint reserves the right not honour a warranty if the failure is due to soldering or other maltreatment of the XC6SLX150 X2 Coprocessor Module Outside warranty Enterpoint offers a fixed price repair or replacement service We reserve the right not to offer this service where a XC6SLX150 X2 Coprocessor Module has been maltreated or otherwise deliberately damaged Please contact support if you need to use this service Other specialised warranty programs can be offered to users of multiple Enterpoint products Please contact sales on boardsales enterpoint co uk if you are interested in these types of warranty Support Please check our online FAQ page for this product first before contacting support Telephone and email support is offered during normal United Kingdom working hours GMT or GMT 1 9 00am to 5 00pm Telephone 44 0 121 288 3945 Email Support enterpoint co uk Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 24
7. IL headers on the pins shown in the table below so that the devices can be accessed from a host board The SPI flash for FPGAI routes to the right side header pins the SPI flash for FPGA2 routes to the left side header pins Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 9 After the FPGAs have configured each SPI Flash can be accessed via the following pins of the FPGA Oo TT TT CCLK Y21 19 DOUT AB20 20 WRITE U9 16 DIN AA20 17 CSO_B T5 15 HOLD U13 18 The flash device CSO_B signal is routed to the CPLD and must be routed to this pin by a suitable build in the CPLD The flash memory can be programmed directly via the JTAG interface see section below PROGRAMMING XC6SLX150 X2 Coprocessor Module or from the host board Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 10 DIL HEADERS i K ry Ef ote os a ZE Sas d Bis e BEE d a ual Se PIN TER LA e i S e eo e 2 en cor 2 ER ns ES eo e to ec ee ee ee ee ee ee ee ce ee CR ee LEFT DIL neri n RIGHT HEADER EL ee DIL HEADER Sp Sa ee EA ee eer ee ee ee ee e L 4 ee TE LA LE s es ee ee tt o t gt Seu ae AA es ee S to L TIT k 1N 30 INNER ROW INNER ROW OUTER ROW OV 33V OUTER ROW The DIL Headers provide a simple mechanical and electrical interface for connection to the module Th
8. SLX150 X2 Coprocessor Module The module is protected by a 2 6A resettable fuse on the 5v feed NOT CONNECTED OV Alternatively the 3 3V supply can be used to supply power for the FPGA core voltage It should be noted that if a demanding build is loaded into the FPGAs the current drawn by the module may exceed the fuse rating on the host board If this option is chosen it is necessary to connect a zero ohm link on the back of the XC6SLX150 X2 Coprocessor Module see below If you subsequently use the 5v input connector you must remember to remove this zero ohm link Extreme care should be taken when soldering to the back of the module Enterpoint Ltd will not accept responsibility for damage to the module due to poor soldering technique Care should be taken not to exceed 3 3v input as this can cause damage to the XC6SLX150 X2 Coprocessor Module Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 16 BATTERY HOLDER ZERO OHM LINK SITE BATTERY A battery holder is supplied on the underside of the XC6SLX150 X2 Coprocessor Module that can take a nominal 4 8mm diameter 1 5mm thick rechargeable coin cell battery providing 1V to 3 6V e g Panasonic ML414S ZT We do not normally supply the battery to avoid shipping issues with batteries It is connected to pin R17 of the FPGAs and recharges from the 3 3V supply Vgarr is required to maintain the battery backed RAM AES key when VCCaux is not applied to the FPGA Enterpoint
9. TROL4 IN STD_LOGIC Add to the Architecture TCK lt CONTROLI PIN HAS THE TCK SIGNAL CONTROL2 lt TDO PIN 2 HAS THE TDO SIGNAL TDI lt CONTROL PIN 3 HAS THE TDI SIGNAL TMS lt CONTROLA PIN4 HAS THE TMS SIGNAL Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 SPI FLASH MEMORY H d Tak A eis yeast E BD d D vm i H Oh mum a a 2000464808408 0 0804898000888 900468 it dii 2 Ep ese0eeen 204202000 aowi e WW e ei H iw ti Le FPGAI gt D EN e LE S e 5 e SPI FLASH FOR e SPI FLASH FOR FPGA2 FPGAI FPGA2 PTT E e deepeeegepgegegegegeeegeg eegoe EINN The XC6SLX150 X2 Coprocessor Module maybe fitted with either the Micron Numonyx M25P128 or the Winbond 25Q128BV SPI flash memory device The M25P128 will operate in single bit wide mode whereas the Winbond 25Q128BV can operate in single dual or quad modes The SPI flash devices configure the FPGAs when the module is powered up provided a suitable bitstream mcs file is programmed into the device Each device has a capacity of 128Mbits with a single configuration bitstream each XC6SLX150 taking 4 1Mbits Any remaining space can be used for alternative configurations or code and data storage For further information concerning these flash memory devices please consult www micron com or www winbond com The SPI flash memory signals are routed to the D
10. artan 6 and choose Add SPI BPI Flash Navigate to your programming file mcs and click OPEN Use the next dialogue box to select SPI flash and M25P128 or W25Q128BV Data width should be set appropriately The flash memories should appear as shown below Right click device to select operations ww enn me Jerch xc9572xl xc6slx150 xc6slx150 cpli jed X2_fpgal_s6x15 x2_fpga2 s6x15 TDO JTAG chain with configuration files assigned and SPI Flash memory added Right click on the icon representing each flash memory and choose Program to load your programs into the devices It is recommended that options to Verify and Erase before programming are chosen Otherwise all defaults can be accepted The programming operation will take some time at least 3 or 4 minutes per device Depending upon the memory device and the settings used when generating the bitfiles using ISE it will take up to 20 seconds for an XC6LX150 to configure upon power up In order to decrease this time the following process can be followed 1 In the main ISE menu right click Generate Programming file Choose Properties 2 On the left hand side of the Process Properties Dialogue box choose Configuration Options Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 21 3 The first item on the menu which appears on the right hand side of the dialogue box is Configuration Rate The default setting is 2 Increase th
11. er pins as shown below DI ma rma mS E WU e to ee eegggegeggeeggegegeegeegeg eegee LL Li e ka e E e e e e gt M e gt gt bd COLUMN OF 30 COLUMN OF 30 OV CONTACTS 3 3V CONTACTS The user can supply 3 3v to the module on any or all of the right hand side inner header pins and OV on any or all of the left hand side inner header pins This can be achieved by plugging the module into the Enterpoint Raggedstone2 or 3 or Broaddown series development boards which all have sockets with appropriate power connections for this module and resettable fuses to limit the current A user can also provide 3 3V and OV from another source onto these pins The pins are arranged on a 0 linch pitch 2 54mm to facilitate this The horizontal distance between the OV pins and the 3 3V pins in 1 4inches Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 15 The 5v feed is used to generate the 1 2V core voltage for the FPGAs There are 2 options for supplying 5V to the XC6SLX150 X2 Coprocessor Module There is a 4 pin connector on the module which accepts connectors usually seen in PCs to connect power to HDD or CD DVD drives The pinout of the connector suits these connectors and the module requires 5v and Ov The 4 terminal usually 12v in a PC is unconnected on the module Care should be taken not to exceed 5V input as this can cause damage to the XC6
12. ere are twenty I O on the left side of the module 20 IO on the right hand side of the module giving a total of 40 I O available A further 8 IO are routed from the DIL header pins to the CPLD Control 1 8 The maximum signal voltage on the GPIO is 3 3v The DIL Headers can support 20 pairs of LVDS signalling The Spartan 6 FPGA can terminate any of these pairs LVDS termination on individual signal pairs is a programmable option that can be set in build constraints for the FPGA when using the ISE toolset The LVDS pairs are shown in the table below along with FPGA pin numbers Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 11 The DIL Headers will also support the use of crude prototype circuits using stripboard or other prototype materials The DIL Header connectors are arranged on a standard 0 1inch 2 54mm pitch The horizontal pitch of the DIL Headers is 1 6 inches between the outer rows of the headers The inner pins of the header form continuous power strips The right hand side header has an inner column of 3 3V pins The LHS header has an inner column of DGND OV LEFT COLUMN RIGHT COLUMN OUTER PINS INNER INNER OUTER PINS FUNCTION _ _S6 PIN PINS PINS FUNCTION S6 PIN 1 CONTROLS CPLD 22 ON 3 3V CONTROLI CPLD 64 2 CONTROL6 CPLD 24 OV 3 3V CONTROL2 CPLD 63 3 CONTROL7 CPLD 25 OV 3 3V CONTROL3 CPLD 62 4 CONTROLS CPLD 27
13. is number The maximum value we suggest is 22 Choose Apply and OK 4 Generate the program file as normal Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 22 MECHANICAL ARRANGEMENT The Dimensions on the drawings below are millimetres mm All sizes quoted are subject to manufacturing tolerances and should only be used as a general guide 0000 x E o o o o o o el o 2 o o o o o o o o 00000000000000000000 m 3 3 U The socket pins on the DIL headers are arranged on a 2 45mm 0 Linch pitch The maximum height of the components on the upper side of the module measured from the lower surface of the PCB is less than 10mm When the XC6SLX150 X2 Coprocessor Module is plugged into a Raggedstone2 development board using doubled header pins the total height from the underside of the Raggedstone to the top of the XC6SLX150 X2 Coprocessor Module components is approximately 25mm Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 23 Medical and Safety Critical Use XC6SLX150 X2 Coprocessor Modules are not authorised for the use in or use in the design of medical or other safety critical systems without the express written person of the Board of Enterpoint If such use is allowed the said use will be entirely the responsibility of the user Enterpoint Ltd accepts no liability for any failure or defect of the XC6SLX150 X2 Coprocessor Module or its design when
14. nally This latter option enables a host board to initiate reconfiguration of the FPGAs on the XC6SLX150 X2 Coprocessor Module The JTAG signals are also available to be routed from the CPLD to the DIL headers if required A suitable build must be loaded into the CPLD before the FPGAs will configure from their SPI flash memory devices There are 8 Control signals which connect between the CPLD and 8 of the DIL header pins The connections to the CPLD are shown below DD SIGNALNAME CONNECTS TO PRP sIGNALNAME CONNECTS TO 1 CSOSPLIN SPI FLASHPI 47 DONE_FPGAI FPGAI PIN Y22 10 TMS_DR TMS 49 CSO B FPGA2 FPGA2PINTS Il TDLDR TDI 50 INIT_B_FPGAI FPGAI PIN T6 12 TDO_DR TDO 51 Mi_FPGA2 FPGA2 PIN U15 13 TCK_DR TCK 52 INIT_B_FPGA2 FPGA6 PIN T6 15 CLOCK 25MHZ OSCILLATOR 56 PROG_B_FPGA2 FPGA2 PIN AAI 16 CSO SPI2 PIN N LHSPINIS 57 PROG B_ FPGAI FPGAI PIN AAI 22 CONTROLS LHS PIN 1 58 CSO SPLI PIN N RHSPIN15 24 CONTROL6 LHS PIN 2 59 MO_FPGA2 _ FPGA2 PIN AA22 25 CONTROL7 LHS PIN 3 60 DONE FPGA2 FPGA2 PIN Y22 27 CONTROLS LHS PIN 4 61 CONTROL4 RHS PIN 4 31 CSO SPL2N SPP FLASHPI 62 CONTROL3 RHS PIN 3 39 CSO B FPGAI FPGAI PINTS 63 CONTROL2 RHS PIN 2 45 Mi_FPGAI FPGAI PIN U15 64 CONTROL RHS PIN 1 46 MO_FPGAI FPGAI PIN AA22 In order to enable each FPGA to configure from its SPI Flash memory device at startup it is necessary to set MO
15. rtan 6 The full version of the Xilinx tools is required to program the XC6SLX150 2FGG484C The free Webpack version of ISE is sufficient to support the smaller versions of the FPGA There is a single JTAG chain on the XC6SLX150 X2 Coprocessor Module The JTAG chain allows the programming of the CPLD both Spartan 6s and the two SPI Flash memory devices Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 19 Using iMPACT Boundary Scan the JTAG chain appears like this Right click device to select operations va ka tog xc9S72xl xc6sik150 xc6sik150 JTAG chain following Boundary scan The first device is the CPLD the second is FPGA the third is FPGA2 1 Programming the CPLD The xc9572x1 CPLD has its own internal storage for configuration data Use your programming tools to generate a suitable jed file to achieve your desired functionality Right click the the icon representing the Spartan 6 FPGA and choose Assign New Configuration File Navigate to your jed file and choose OPEN The Jed file name will appear under the CPLD as shown below Right click device to select operations ee xc9572xl xc6six150 xc6slx150 cpli jed x2_fpga1_s6ik15 x2_fpga2 s6x15 JTAG chain with configuration files assigned Right click the icon representing the CPLD and choose Program Depending on your version of IMPACT you may need to respond to a programming properties dialogue box by clicking OK The Spar
16. s which are soldered into the board This means that if a pin is broken this extra row of headers can be Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 12 replaced easily and cheaply Enterpoint can supply extra pins socket headers if required Contact boardsales enterpoint co uk Enterpoint does not accept responsibility if the header pins on the module have been damaged due to poor handling Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 13 OSCILLATOR The oscillator on the XC6SLX150 X2 Coprocessor Module is an ASEM 25MHz oscillator The oscillator is situated as shown below and is connected to each FPGA on PIN AB13 ou TTT CTT CC ooo CES EES EK EK int Hike 222 tii a MEAN eseoaeen CX TIVE bucht Wi e L psen LE ef Rath ee pa pe eee208000e00e ore SE KN OSCILLATOR OT ew oe e4240042000700090 eeseeecooveeeoosvseaseovoeeoe CU MM dt The Spartan 6 has PLLs and DCMs to produce multiples divisions and phases of the clock for specific application requirements Please consult the Spartan 6 datasheet available from the Xilinx website at http www xilinx com if multiple clock signals are required Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 14 POWER CONNECTIONS The XC6SLX150 X2 Coprocessor Module requires input voltages of 5v and 3 3v in order to operate 3 3V must be connected to the inner right row of head
17. t Lid 66 Enterpoint s Raggedstone2 development board with XCGSLX150 X2 Coprocessor Module The aim of this manual is to assist in using the main features of the XC6SLX150 X2 Coprocessor Module There are features that are beyond the scope of the manual Should you need to use these features then please email support enterpoint co uk for detailed instructions The x 2 Coprocessor Module currently comes with two SLX150 2FGG484C Spartan 6 Other variants may be offered at a later date or as an OEM product Please contact out us on boardsales enterpoint co uk should you need further information We can offer a PCB design service to interface with this product should you require a function not covered by our current range of development boards Typical turn around for this service is 6 8 weeks depending upon complexity quantity ordered and availability of components Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 3 XC6SLX150 X2 Coprocessor Module 7 re pr JTAG POWER H ONNECTOR CONNECTOR HP LL FUSE ce t CH VOLTAGE ce z REGULATOR oo 3 ec E JE CPLD as uu ee Oe D Y e FPGAI D e LEFT DIL eg ia RIGHT HEADER e IS DIL HEADER 2 e L y SP FLASH FOR 2 SPI FLASH FOR FPGAI LR FPGA2 FPGA2 RTE PPPTTLILLLILILLESLLLEE 2 a d t XSLX150 x 2 Coprocessor Module Back View Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011
18. tan 6 will program This process is very quick typically a few seconds 2 Programming the FPGAs directly Direct JTAG programming of the Spartan 6 FPGAs is volatile and the FPGAs will lose their configuration every time the board power is cycled For sustained use of an FPGA design programming the design into the Flash memory is recommended see 2 and 3 below Direct JTAG programming using bit files is useful for fast temporary programming during development of FPGA programs Right click the icon representing the Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 20 Spartan 6 FPGA and choose Assign New Configuration File Navigate to your bit file and choose OPEN The next dialogue box will offer to add a flash memory and you should decline Right click the icon representing the Spartan 6 FPGA and choose Program On the next dialogue box ensure that the Verify box is not checked If it is you should uncheck it failure to do this will result in error messages being displayed Click OK The Spartan 6 will program This process is very quick typically a few seconds 3 Programming the SPI flash memory using Boundary Scan Once the SPI Flash memories have been programmed the Spartan 6 devices will automatically load from the Flash memories at power up Generation of suitable Flash memory files mcs can be achieved using ISE iMPACT s Prom File Formatter Right click on the icon representing each Sp
19. the FGG484 package This module is normally available with commercial grade 2 speed devices fitted in the XC6SLX150 size Should you have an application that needs a different size of FPGA industrial specification parts or faster speed grades please contact sales for a quote at boardsales enterpoint co uk The FPGA PROG_B CSO_B INIT_B DONE and M 0 1 signals are routed to the CPLD and can be routed from the CPLD to the DIL header pins if required so that configuration of the FPGAs can be controlled by a host board Similarly the CSO_B signals from the SPI flash memory devices are routed to the CPLD Some of these signals require pullup resistors to be implemented in the CPLD program The FPGAs are interconnected by 38 routes which are shown below T2 T21 H1 H22 T1 T22 G3 G20 R3 R20 G1 G22 R1 R22 F2 F21 P2 P21 F1 F22 P1 P22 E3 E20 N3 N20 E1 E22 N1 N22 D2 D21 M2 M21 D1 D22 M1 M22 C3 C20 L3 L20 C1 C22 L1 L22 B2 B21 K2 K21 B1 B22 K1 K22 U3 U20 J3 J20 U1 U22 J1 J22 V2 V21 M3 M20 V1 V22 L4 L19 W3 W20 H2 H21 WI W22 Enterpoint Ltd XC6SLX150 X 2 Manual Issue 1 0 7 9 2011 6 CPLD The XC6SLX150 X2 Coprocessor Module has an XC9572XL 10VQG64 CPLD which can be used to control the FPGA configuration signals or to route these signals to a host board so that they can be controlled exter
Download Pdf Manuals
Related Search