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1. A video source 15 input through an analog composite port VEEK which generates a digital output in ITU BT656 format A number of common video functions are performed on this input stream in the FPGA These functions include clipping chroma resampling motion adaptive deinterlacing color space conversion picture in picture mixing and polyphase scaling The input and output video interfaces on the VEEK are configured and initialized by software running on a Nios II processor Nios II software demonstrates how to control the clocked video input clocked video output and mixer functions at run time is also provided The video system is implemented using the SOPC Builder system level design tool This abstracted design tool provides an easy path to system integration of the video processing data path with a NTSC or PAL video input VGA output Nios II processor for configuration and control The Video and Image Processing Suite MegaCore functions have common open Avalon ST data interfaces and Avalon Memory Mapped Avalon MM control interfaces to facilitate connection of a chain of video functions and video system modeling In addition video data is transmitted between the Video and Image Processing Suite functions using the Avalon ST Video protocol which facilitates building run time controllable systems and error recovery Figure 4 9 shows the Video and Image Processing block diagram SOPC YO MS sng wasis
2. flash controller wv Offset Ox0 Validate Nios II system ID before software download x Progam Tt Figure 5 2 Programming Flash settings 41 Terasic VEEK User Manual www terasic com www terasic com 6 Appendix 6 1 Revision History Change Log Initial Version Preliminary 6 2 Copyright Statement Copyright 2011 Terasic Technologies All rights reserved 42 VEEK User Manual www terasic com www terasic com
3. VEEK User Manual p Video amp Embedded Evaluatio www terasic com Copyright 2003 2011 Terasic Technologies Inc All Rights Reserved CONTENTS CHAPTER 1 INTRODUCTION OF THE VEEKerccoorowooreorowoorowoo co co o o o o co co o o o o co co co o o co c oo o o o 3 MMe IPI 7 LO 8 2 Gea Na Na Nan aa aa Na Sr irad AN iadair 9 ALA BA ANDI OIG INA Ka AN PN an DA 9 2 2 BLOCK DIAGRAM OF THE aini 10 CHAPTER 3 USING THE VEBEN eoo mama an Gin 11 3 1 CONFIGURING THE CYCLONE IV 0 000000000000 11 ONTRODDBR des cde foe ea des dane EE 14 3 5 USING THES LCD TOUCH SCREEN MODULE BER ROME 15 3 4 USING 5 MEGAPIXEL DIGITAL IMAGE SENSOR 0 00000000000 0000 16 CHAPTER 4 VEEK DEMONSTRATIONS 18 4 1 SYSTEM REQUIREMENTS 18 A AFACTORY CONFIGURATIO N 18 DEMO 19 AAV EEK PICTURE VIEWER bu Rn baba af bul ve do ER 23 4 5 VIDEO AND IMAGE PROCESSING ccccsccse
4. yamg sng WajsAs La Figure 4 9 VIP Example SOPC Block Diagram Key Components 21 Terasic VEEK User Manual www terasic com www terasio com B Demonstration Source Code e Project directory VIP e Bitstream used VEEK VIP sof e Nios II Workspace VIPNSoftware B Demonstration Batch File Demo Batch File Folder VIPldemo batch The demo batch file includes the following files e Batch File VEEK VIP bat VEEK VIP bashrc e FPGA Configure File VIP sof Nios II Program VEEK VIP elf B Demonstration Setup e Connect a DVD player s composite video output yellow plug to the Video IN RCA jack J12 of the VEEK board The DVD player has to be configured to provide NTSC output or PAL output e Connect the VGA output of the VEEK board to a VGA monitor both LCD and CRT type of monitors should work e Load the bit stream into FPGA note e Run the Nios Il and choose VEEK_VIP Software as the workspace Click on the Run button note e Press and drag the video frame box will result in scaling the playing window to any size as shown in Figure 4 10 Q Note 1 Execute VEEK_VIP demo_batch VEEK VIP bat will download sof and elf files 2 You may need additional Altera VIP suite Megacore license features to recompile the project Figure 4 11 illustrates the setup for this demonstration 28 Terasic VEEK User Manual www terasic com www terasic com Figure 4 10 Th
5. 9 USB to SD Card Adapter Two 1 pin Headers Figure 1 2 VEEK kit package contents is information of how to get help if you encounter any problem e Terasic Technologies 886 3 550 8800 e Email support terasic com e Tel www terasic com Chapter 2 VEEK Architecture This chapter describes the architecture of the VEEK including block diagram and components 2 1 Layout and Components The picture of the VEEK is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the locations of the connectors and key components 5 Megapixel Digital Camera 8 LCD Touch Panel Figure 2 1 VEEK PCB and component diagram top view Terasic VEEK User Manual www terasic com www terasic co m NTSC PAL Ethernet o 10 100 1000M 28MHz USB ee Oscillator Porti usa Device Ethernet Host In In Out In Out CEN m y 12V DC Power Supply Connector mi p EA a A r PS Port 1 ABEL okie eee o 2 Triple 8 bit VGA DAC Power ON OFF Switch we foe 1 m m wirds m 2 nues her m ca Gigabit Ethernet Altera USB Blaster Controller chipset mu 11 Gol deb Tua AMT z USB Host Slave Controller yw ya pom attenal Expansion Header ESL n H with Protection Diodes Altera EPCS64 Configuration Device 4 i
6. TV in Connector o TV decoder NTSC PAL SECAM Remote Control o Infrared receiver module Terasic VEEK User Manual www terasic com www teresic com e Power o Desktop DC input o Switching and step down regulators LM3150MH B LCD touch screen module e Equipped with an 8 inch Amorphous TFT LCD Thin Film Transistor Liquid Crystal Display module e Module composed of LED backlight e Support 18 bit parallel RGB interface e Converting the X Y coordination of touch point to its corresponding digital data via the Analog Devices AD7843 A D converter Table 1 1 shows the general physical specifications of the LTC Note Table 1 1 General physical specifications of the LCD Item Specification Unit LCD size 8 inch Diagonal Resolution 800 x3 RGB x 600 dot Dot pitch 0 0675 W x 0 2025 H mm Active area 162 0 W x 121 5 H mm Module size 183 0 W x 141 0 H x 7 2 D mm Surface treatment Anti Glare Color arrangement RGB stripe Interface Digital B 5 Megapixel digital image sensor module e Superior low light performance e High frame rate e Low dark current e Global reset release which starts the exposure of all rows simultaneously e Bulb exposure mode for arbitrary exposure times e Snapshot mode to take frames on demand e Horizontal and vertical mirror image e Column and row skip modes to reduce image size without reducing field of view e Column and row binning modes to improve image quality when resizing e Simple
7. output lt your software name gt flash boot SOPC_KIT_NIOS2 components altera_nios2 boot_loader_cfi srec nios2 elf objcopy I srec O binary your software name gt flash your software name gt _SW bin 3 You may pad a compress option for saving binary image space because the Cyclone IV E series support the decompress feature while loading hardware image from EPCS device 4 The command will use the default HAL boot loader and link it to the text section 5 You can also use the tool bin demo batch to convert your sof and elf to bin Copy your example sof and your example elf to the bin demo batch folder rename them to test sof test elf execute the test bat then the final test HW bin and test SW bin are your target files 39 VEEK User Manual www terasic com www teresic com 5 4 Restoring the Factory Image This section describes some details about the operation of restoring the Application Selector factory image Combining factory recovery binary files In the factory settings you need to program Application Selector binary files to EPCS Before programming you should combine application selector software binary file and hardware binary file together by executing the instructions below e Copy both the VEEK Selector sof and VEEK Selector elf files into a common directory relying on your choice This directory is where you will convert the files e On your host PC lau
8. to 3 3V domains B Block Diagram of the Bus Controller Figure 3 6 gives the block diagram of the connection setup from the HSMC connector to the bus controller on the Max II 240 to the touch screen module To provide maximum flexibility for the user all connections are established through the HSMC connector Thus the user can configure the Cyclone IV E FPGA on the VEEK to implement any system design ros ANU S RYAN Touch 3 3V 4 2 5V 3 3V pane EPM240 Figure 3 6 Block Diagram of the Bus Controller 14 Terasic VEEK User Manual www terasic com www terasic com 3 3 Using the 8 LCD Touch Screen Module The VEEK features an 8 inch Amorphous TFI LCD panel The LCD Touch Screen module offers resolution of 800x600 to provide users the best display quality for developing applications The LCD panel supports 18 bit parallel RGB data interface VEEK 15 also equipped with an Analog Devices AD7843 touch screen digitizer chip The AD7843 is 12 bit analog to digital converter ADC for digitizing x and y coordinates of touch points applied to the touch screen The coordinates of the touch points can be read through the serial port interface on the AD7843 To display images on the LCD panel correctly the RGB color data along with the data enable and clock signals must act according to the timing specification of the LCD touch panel as shown in Table 3 1 Table 3 2 gives the pin assignment information of th
9. Altera Quartus II 10 0 and NIOS II EDS 10 0 or later edition on the host computer e Install the USB Blaster driver software You can find instructions in the tutorial Getting Started with Altera s DE2 115 Board tut inittalDE2 115 pdf which is available on the DE2 115 system CD e Copy the entire demonstrations folder from the VEEK system CD to your host computer 4 2 Factory Configuration The VEEK development kit comes preconfigured with a default utility that boots up on power on and allows users to quickly select load and run different Ready to Run demonstrations stored on an SD Card using the VEEK touch panel Figure 4 1 gives a snapshot of the default application selector interface Note Every demonstration consists of a FPGA hardware image and an application software image When you select a demonstration the application selector copies the hardware image to EPCS device and software image to flash memory and reconfigures the FPGA with your selection For more comprehensive information of the application selector factory configuration please refer to chapter 5 Terasic VEEK User Manual www terasic com www terasic com Altera VEEK Application Selector 1 VEEK Pic 2 VEEK_VIP 3 VEEK Camera 4 VEEK Starter Figure 4 1 Application selector interface Q Note Please insert the supplied SD Card from this demonstration 4 3 VEEK Starter Demonstration VEEK starter demonstration takes user the initial experienc
10. Television System Committee NTSC or Phase Alternation Line PAL format and picture in picture mixing with a background layer The video stream is output in high definition resolution 800x600 on the HSMC daughter card part of the VEEK example design demonstrates a framework for rapid development of video and image processing systems using the parameterizable MegaCore functions that are available in the Video and Image Processing Suite Available functions are listed in Table 4 2 This demonstration needs the Quartus II license file includes the VIP suite feature Table 4 2 VIP IP cores functions IP MegaCore Description Function Frame Reader Reads video from external memory and outputs it as a stream Control Synchronizes the changes made to the video stream in real time between two Synchronizer functions Switch Allows video streams to be switched in real time Color Space Converts image data between a variety of different color spaces such as RGB to Converter YCrCb Chroma Resampler Changes the sampling rate of the chroma data for image frames for example from 4 2 2 to 4 4 4 or 4 2 2 to 4 2 0 2D FIR Filter Implements 3 x 3 5 x 5 or 7 x 7 finite impulse response FIR filter on an image data stream to smooth or sharpen images Alpha Blending Mixes and blends multiple image streams useful for implementing text overlay Mixer and picture in picture mixing Scaler A sophisticated polyphase scaler that allows
11. bus bit 1 2 5 LCD B2 PIN V22 LCD blue data bus bit 2 2 5V LCD B3 PIN V25 LCD blue data bus bit 3 2 5 LCD B4 PIN L28 LCD blue data bus bit 4 2 5V LCD B5 PIN J26 LCD blue data bus bit 5 2 5V LCD DEN PIN P25 LCD RGB data enable 2 5V TOUCH PENIRQ N PIN L22 AD7843 pen interrupt 2 5V TOUCH DOUT 121 AD7843 serial interface data out 2 5 TOUCH BUSY PIN U26 AD7843 serial interface busy 2 5V TOUCH DIN PIN U25 AD7843 serial interface data 2 5V TOUCH CS N PIN T26 AD7843 serial interface chip select input 2 5V TOUCH DCLK PIN T25 AD7843 interface clock 2 5V 3 4 Using 5 Megapixel Digital Image Sensor Module The VEEK 1s equipped with a 5 Megapixel digital image sensor module that provides an active imaging array of 2 592H x 1 944 V It features low noise CMOS imaging technology that achieves CCD image quality In addition it incorporates sophisticated camera functions on chip such as windowing column and row skip mode and snapshot mode The sensor can be operated in its default mode or programmed by the user through a simple two wire serial interface for frame size exposure gain settings and other parameters Table 3 3 contains the pin names and descriptions of the image sensor module Table 3 3 Pin assignment of the CMOS sensor Signal Name FPGA Pin No Description Standard CAMERA PIXCLK PIN J27 Pixel clock 2 5V CAMERA DO PIN F26 Pixel data bit 0 2 5V CAMERA_ D1 E26 Pixel data bit 1 2 5V CAMERA_ D2 PIN_G25 Pixel data bi
12. easy to convert your own Nios II design into an application which is loadable by the Application Selector utility All you need 1s a hardware image a SOF file and a software image which runs on that hardware a Nios II ELF file The only restrictions are e The hardware designs must contain a CFI Flash controller 1 e The SOF file must contain a Nios II CPU whose reset address 15 set to CFI Flash at offset e Before compiling the software make sure you have set your software s program memory text section in Flash memory under the System Library Properties Nios II IDE page or through BSP Editor Nios II SBT for Eclipse utility 2 Once you have your working SOF and ELF file pair perform the following steps to convert them to a loadable application selector compatible application e Copy both the SOF and ELF files into a common directory relying on your choice This directory is where you will convert the files e your host PC launch a Nios II Command Shell from Start gt Programs gt Altera gt Nios II version gt EDS gt Nios II Command Shell e From the command shell navigate to where your SOF file is located and create your hardware binary file using the following commands e Convert sof file into flash file sof2flash epcs input your example sof output your example HW flash 37 38 Terasic VEEK User Manual www terasic com www terasic com e Convert flash file into binary
13. two wire serial interface e Programmable controls gain frame rate frame size exposure Table 1 2 shows the key parameters of the CMOS sensor Note 6 Terasic VEEK User Manual www terasic com www terasic com Table 1 2 Key performance parameters of the CMOS sensor Parameter Active Pixels Pixel size Color filter array Shutter type Maximum data rate master clock Full resolution Frame rate VGA mode ADC resolution Responsivity Pixel dynamic range SNRMAX Power Supply Voltage Value 2592Hx1944V 2 2umx2 2um RGB Bayer pattern Global reset release GRR 96Mp s at 96MHz Programmable up to 15 fps Programmable up to 70 fps 12 bit 1 4V lux sec 550nm 70 1dB 38 1dB 3 3V 1 7V 3 1V Q Note for more detailed information of the LCD touch panel and CMOS sensor module please refer to their datasheets respectively 1 1 About the Kit The kit contains all users needed to run the demonstrations and develop custom designs as shown in Figure 1 2 The system CD contains technical documents of the VEEK which includes component datasheets demonstrations schematic and user manual www terasic com Terasic VEEK User Manual w teresic com 1 2 Getting Help Q VEEK USB Cable Power Supply Q VEEK Quick Start Guide Altera Complete Design Suite DVD for Windows DE2 115 amp VEEK System CD Remote Controller Q 2GB SD Card Two Wire Strips black and red
14. VGA output of the VEEK board to a VGA monitor both LCD and CRT type of monitors should work e Load the bit stream into FPGA note e Run the Nios Il and choose VEEK VIP Camera WSoftware as the workspace Click on the Run button note e The system enters the FREE RUN mode automatically Press KEY 0 on the DE2 115 board to reset the circuit e Press KEY 2 to stop run you can press KEY 3 again to switch back to FREE RUN mode and you should be able to see whatever the camera captures on the VGA display e Press and drag the video frame box will result in scaling the playing window to any size as shown in Figure 4 10 Q Note 1 Execute VEEK VIP CameraMemo batclNVEEK VIP CameraA bat will download sof and elf files 2 You may need additional Altera VIP suite Megacore license features to recompile the project Figure 4 15 illustrates the setup for this demonstration 34 Terasic VEEK User Manual www terasic com VGA Out VGA LCD CRT Monitor b E 13 ree TT epo PM mp 5 2 2 4 J Tam T7 45 21 E LL tii A Ew A ob hb bade So mim 7 Figure 4 15 Setup for the VEEK VIP Camera demonstration 35 Terasic VEEK User Manual www terasic com www terasic com Chapter 5 Application Selector The applic
15. Viewer bashrc e FPGA Configure File VEEK Picture Viewer sof Nios II Program VEEK Picture Viewer elf B Demonstration Setup e Format your SD Card into FAT16 format e Place the jpg image files to the subdirectory of the SD Card For best display result the image should have a resolution of 800x600 or the multiple of that e Insert the SD Card to the SD Card slot on the VEEK e the bitstream into the FPGA on the VEEK board 24 124 51 Terasic User Manual www terasic com A DTE RYAN e Run the Nios II Software under the workspace VEEK Picture ViewerNSoftware Note e Touch the play button will proceed to display the next image Figure 4 8 gives a screen shot of the VEEK picture viewer demonstration Table 4 1 shows the instructions for running the demonstration Figure 4 8 VEEK picture viewer demonstration Table 4 1 Touch panel displayed information Display information Implication Press the play button to display the next buffered image gt Loading Indicates the loading progress 57 1 Note execute the VEEK Picture Viewer bat under VEEK Picture ViewerMemo batch will automatically download the sof and elf file 25 VEEK User Manual www terasic com www terasic com 4 5 Video and Image Processing The Video and Image Processing VIP Example Design demonstrates dynamic scaling and clipping of a standard definition video stream in either National
16. ation selector utility is the default code that powers on the FPGA and offers a graphical interface on LCD allowing users to select and run different demonstrations resides on SD Card 5 1 Ready to Run SD Card Demos You can find several Ready to Run SD Card demos in your SD Card root directory as well as 1n the System CD under VEEK Factory RecoveryM pplication Selector folder Figure 5 1 shows the photograph while the Application Selector 1s loading an 1mage Altera VEEK Application Selector 1 VEEK Pic 2 VEEK VIP 3 VEEK Camera 4 VEEK Starter Figure 5 1 Application selector loading image Also you can easily convert your own applications to be loadable by the application selector For more information see Creating Your Own Loadable Applications section 5 3 If you have lost the contained files in the SD Card you could find them on the VEEK System CD under the VEEK Factory Recovery folder 36 5 VEEK User Manual www terasic com www rasic com 5 2 Running the Application Selector e Connect power to the VEEK board e Insert the SD Card with applications into the SD Card socket of VEEK e Switch on the power SW18 1 e Scroll to select the demonstration to load using the side bar e Tap on the Load button to load and run a demonstration 2 Q Note 1 If the board is already powered the application selector will boot from EPCS and a splash screen will appear while the application
17. atures of the board are listed below DE2 115 Development Board Cyclone IV EP4CE115 FPGA o 114 480 LEs o 432 M9K memory blocks o 3 888 Kbits embedded memory o 4 PLLs Configuration o On board USB Blaster circuitry o JTAG and AS mode configuration supported o EPCS64 serial configuration device Memory Devices o 128MB SDRAM o 2MB SRAM o 8MB Flash with 8 bit mode o 32Kbit EEPROM Switches and Indicators o 18 switches and 4 push buttons o 18 red and 9 green LEDs o Eight 7 segment displays Terasic VEEK User Manual www terasic com www terasic co m Audio o 24 bit encoder decoder CODEC o Line in line out and microphone in jacks Display o 16x2 LCD module On Board Clocking Circuitry o Three 50MHz oscillator clock inputs o SMA connectors external clock input output SD Card Socket o Provides SPI and 4 bit SD mode for SD Card access Two Gigabit Ethernet Ports o Integrated 10 100 1000 Gigabit Ethernet High Speed Mezzanine Card HSMC o Configurable I O standards voltage levels 3 3 2 5 1 8 1 5V USB Type A and B o Provide host and device controller compliant with USB 2 0 o Support data transfer at full speed and low speed o PC driver available 40 Expansion Port o Configurable I O standards voltage levels 3 3 2 5 1 8 1 5V VGA out Connector o VGA DAC high speed triple DACs DB9 Serial Connector RS232 port with flow control PS 2 Connector o PS 2 connector for connecting a PS2 mouse or keyboard
18. ccecceccecceccecceccescceccscceccescsceecescesscsccescscascescesccsscsccescuscescescesscssctscscaseeeees 26 4A O VEEK CAMERA APN Nan m se Gain cata 29 4 7 VIDEO AND IMAGE PROCESSING FOR CAMERA ccccccsccecceccesceccscosccecesccsscsscesccscesccecesscsscsscscescescessesscsscescescesceses 32 1 Terasic User Manual www terasic com www terasic com AN DTE RYAN CHAPTER 5 APPLICATION 36 SITJPADYIORUN SDCARD DEMOS 4 4 5 VIE AUS 36 SARUN THE APPLICATION SELECTOR ne nabi 37 5 3 APPLICATION SELECTOR DETAILS scccccceccecceccecccscoccceccsccescuccceccecceccsccsecsecasccscceceescsscsscseceecesccscesscsscnscascesceeceess 37 5 4 RESTORING THE FACTORY IMAGE 2 0 000000000000 40 CHAPTER6 Rn nmm nmm ehem 42 CI REVBION HISTORY gan NN na M MEME EM CIMA EE oe annie eee EE IMMER 42 OA COPYRIGHT STATEMENT ererek 42 2 Terasic VEEK User Manual www terasic com 1 Introduction of the VEEK VEEK FPGA Development Kit is a comprehensive design environment with everything embedded developers need to create processing based systems The VEEK delivers an integrated platform that includes hardware design tools intellectual property IP and referenc
19. custom scaling and real time updates of both the image sizes and the scaling coefficients Deinterlacer Converts interlaced video formats to progressive video format using a motion adaptive deinterlacing algorithm Also supports bob and weave algorithms Test Pattern Generates a video stream that contains still color bars for use as a test pattern Generator Clipper Provides a way to clip video streams and can be configured at compile time or at run time Color Plane Changes how color plane samples are transmitted across the Avalon ST Sequencer interface This function can be used to split and join video streams giving control over the routing of color plane samples Frame Buffer Buffers video frames into external RAM This core supports double or triple buffering with a range of options for frame dropping and repeating 2D Median Filter Provides a way to apply 3 x 3 5 x 5 or 7 x 7 pixel median filters to video images Gamma Corrector Allows video streams to be corrected for the physical properties of display devices Clocked Video These two cores convert the industry standard clocked video format BT 656 to Input Output Avalon ST video and vice versa These functions allow you to fully integrate common video functions with video interfaces processors and external memory controllers The example design uses an Altera Cyclone IV E EPACEIT15F29 featured VEEK board 26 TTjasiC Terasic VEEK User Manual www terasic com
20. e LCD touch panel Table 3 1 LCD timing specifications Parameter Symbol Min Ew Max Unit CLK Frequency FCPH 39 79 MHz CLK Period FCPH 25 13 Ns CLK Pulse Duty FCWH 40 50 60 DE Period FDEH TDEL 1000 1056 TCPH DE Pulse Width FDH 800 TCPH DE Frame Blanking FHS 10 28 110 FDEH TDEL DE Frame Width FEP 600 FDEH TDEL OEV Pulse Width TOEV 150 TCPH OKV Pulse Width TCKV 133 TCPH DE internal STV Time T1 4 TCPH DE internal CKV Time T2 40 TCPH DE internal OEV Time T3 23 TCPH DE internal POL Time T4 157 TCPH STV Pulse Width 1 TH Note THS THA lt TH Table 3 2 Pin assignment of the LCD touch panel Signal Name FPGA Pin No Description Standard LCD_DIM PIN_P27 LCD backlight enable 2 5V LCD_NCLK PIN_V24 LCD clock 2 5V LCD RO PIN V26 LCD red data bus bit 0 2 5V LCD R1 PIN R27 LCD red data bus bit 1 2 5V 15 Terasic VEEK User Manual www terasic com LCD R2 PIN R28 LCD red data bus bit 2 2 5V LCD R3 PIN U27 LCD red data bus bit 3 2 5V LCD R4 PIN U28 LCD red data bus bit 4 2 5V LCD R5 PIN V27 LCD red data bus bit 5 2 5V LCD GO 21 LCD green data bus bit 0 2 5V LCD G1 PIN R21 LCD green data bus bit 1 2 5 LCD G2 PIN R22 LCD green data bus bit 2 2 5V LCD G3 PIN R23 LCD green data bus bit 3 2 5V LCD G4 PIN T21 LCD green data bus bit 4 2 5 LCD G5 PIN T22 LCD green data bus bit 5 2 5V LCD BO PIN V28 LCD blue data bus bit 0 2 5V LCD B1 PIN U22 LCD blue data
21. e SD Card must be located in a top level directory named Application Selector Under the Application Selector directory each application is located in its own subdirectory The name of that subdirectory is important because the application selector utility uses that name as the title of the application when displaying it in the main menu The subdirectory 37 Terasic VEEK User Manual www terasic com www teresic com names can be anything so long as they adhere to the file system long name rules Spaces are permitted CFI Flash CFI flash is used to store the software binary files of applications All software binary files used by the application selector contain a boot copier which is pre ended by the Nios2 elf objcopy utility during file conversion process described in the Creating Your Own Loadable Applications section The boot copier copies the software code to program memory before running it The Application software binary file is stored in flash at load time to an offset 0x0 EPCS Device EPCS is used to store both the binary file of the Application Selector both hardware and software image itself as well as hardware binary files of applications which are being loaded The Application Selector binary file is permanently stored in EPCS device at offset 0 0 Hardware binary files for the applications being loaded get written to EPCS at load time to an offset 0x400000 Creating Your Own Loadable Applications It is
22. e VIP demonstration running result Video In CVBS Output 25 DVD Player Figure 4 11 Setup for the VEEK VIP demonstration 4 6 VEEK Camera Application This demonstration shows a digital camera reference design using the 5 Megapixel CMOS sensor 8 inch LCD modules on the VEEK The CMOS sensor module sends the raw image data to FPGA on DE2 115 Board the FPGA on the board 1s handling image processing part and converts the data to RGB format to display on the LCD module The I2C Sensor Configuration module 1s used to configure the CMOS sensor module Figure 4 12 shows the block diagram of the demonstration 29 5 VEEK User Manual www terasic com www terasic com AN DTE RYAN As soon as the configuration code is downloaded into the FPGA the I2C Sensor Configuration block will initial the CMOS sensor via I2C interface The CMOS sensor is configured as follow e Row and Column Size 800 600 e Exposure time Adjustable Pix clock MCLK 2 25 2 50MHz e Readout modes Binning According to the settings we can calculate the CMOS sensor output frame rate is about 44 4 fps After the configuration The CMOS sensor starts to capture and output image data streams the CMOS sensor Capture block extracts the valid pix data streams based on the synchronous signals from the CMOS sensor The data streams are generated in Bayer Color Pattern format So it s then converted to RGB data stream
23. e designs for developing embedded software and hardware platform 1n a wide range of applications The fully integrated kit allows developers to rapidly customize their processor and IP to best suit their specific application The VEEK features the DE2 115 development board targeting the Cyclone IV E FPGA as well as a LCD multimedia color touch panel and a 5 Megapixel digital image sensor module VEEK is preconfigured with FPGA hardware reference design including several Ready to Run demonstration applications stored on the provided SD Card Software developers can use these reference designs as their platform to quickly architect develop and build complex embedded systems By simply scrolling through the demo of your choice on the LCD multimedia color touch panel you can evaluate numerous processor system designs The all in one embedded solution offered on the VEEK in combination of the LCD touch panel and digital image module provide embedded developers the ideal platform for multimedia applications with unparallel processing performance Developers can benefit from the use of FPGA based embedded processing system such as mitigate design risk and obsolescence design reuse reducing bill of material BOM costs by integrating powerful graphics engines within the FPGA and lower cost Figure 1 1 shows a photograph of the VEEK Terasic VEEK User Manual www terasic com www terasic com Figure 1 1 The VEEK overview The key fe
24. e of embedded system integrating a LCD Touch Panel This demonstration consists of two sub item Touch and Color pattern generator The Touch segment draws a circle on where you touch the screen and updates its coordinates on the top left corner The pattern generator can be treated as an upgrade version of the LCD test program The software successively generates different color patterns after a fixed time delay Users could use it to quickly investigate any flaw of the LCD Figure 4 2 shows the hardware system block diagram of this demonstration The system is clocked by an external 50MHz Oscillator Through the internal PLL module the generated 100M Hz clock 15 used for Nios II processor and other components and there also a 40MHz pixel clock for the video pipeline and 10MHz for low speed peripherals The Nios II CPU runs the application software and controls all the peripherals A scatter gather DMA 16 used to transfer pixel data from the video buffer to the video pipeline 19 5 Terasic VEEK User Manual www terasic com www oqe Figure 4 2 Block diagram of the VEEK Starter demonstration Figure 4 3 illustrates the software structure of this demonstration The touch panel s SPI HAL block responds to the bottom hardware requests and interface to upper layers The SGDMA HAL allocates required frame descriptor buffers to specified memory address and is responsible of handli
25. em is implemented using the SOPC Builder system level design tool This abstracted design tool provides an easy path to system integration of the video processing data path with a NTSC or PAL video input VGA output Nios II processor for configuration and control The Video and Image Processing Suite MegaCore functions have common open Avalon ST data interfaces and Avalon Memory Mapped Avalon MM control interfaces to facilitate connection of a chain of video functions and video system modeling In addition video data is transmitted between the Video and Image Processing Suite functions using the Avalon ST Video protocol which facilitates building run time controllable systems and error recovery Figure 4 14 shows the Video and Image Processing block diagram Nios Il processor suge sng uejs s Figure 4 14 VIP Camera Example SOPC Block Diagram Key Components 33 TagasiC Terasic VEEK User Manual www terasic com www terasic com B Demonstration Source Code e Project directory VEEK VIP Camera e Bitstream used VEEK VIP Camera sof e Nios II Workspace VIP Camera Software B Demonstration Batch File Demo Batch File Folder VIP CameraMemo batch The demo batch file includes the following files e Batch File VEEK VIP Camera bat VEEK VIP Camera bashrc e FPGA Configure File VEEK VIP Camera sof e Nios II Program VIP Camera elf B Demonstration Setup e Connect the
26. file nios2 elf objcopy I srec O binary your example HW flash your example HW bin e From the command shell navigate to where your ELF file is located and create your software binary file using the following command nios2 elf objcopy O binary your example elf your example SW bin 4 5 e Create a new subdirectory and name it what you would like the title of your application to be shown as in the application selector e Using an SD Card reader copy the directory onto an SD Card into a directory named Application Selector The directory structure on the SD Card should look like this Application SelectorxName of Application elf names SW bin sof name HW bin e Place the SD Card in the VEEK board and switch on the power The Application Selector will start up and you will now see your application appear as one of the selections Q 1 not need a CFI Flash controller when your design does not contain a Nios II processor or you store your software code within the on chip memory and use the initialization file 2 If you would like to use other memories such as SRAM or SDRAM as the program memory you may need to perform two steps to convert your elf file into bin file to make the software properly run on VEEK The commands seem to look like this elf2flash basezflash base address end address resetzflash base address Input lt your software name gt elf
27. i TE HET As Altera 60 nm Cyclone IV E FPGA with 115K LEs LCD 16x2 Module SOMHz Oscillator e 64MB SDRAM x2 T CES NNNM ape 2MB SRAM FLASH 7 segment Displays apg o PE l Ext Clock Out Programming Mode Switch i um SMA Ext Clock In OPTED TTD DOPOU 4 FULL IR Receiver vd ud e eeu gt 18 Slide Switches 18 Red LEDs 4 Push buttons 8 Green LEDs Figure 2 2 VEEK PCB and component diagram bottom view 2 2 Block Diagram of the VEEK Figure 2 3 gives the block diagram of the VEEK board To provide maximum flexibility for the user all connections are made through the Cyclone IV E FPGA device Thus the user can configure the FPGA to implement any system design HSMC DE2 115 ANU S RYA Cyclone IV LCD Touch Panel lt Figure 2 3 Block Diagram of VEEK 10 Terasic VEEK User Manual www terasic com Chapter 3 Using the VEEK This section describes the detailed information of the components connectors and pin assignments of the VEEK 3 1 Configuring the Cyclone IV E FPGA VEEK board contains a serial configuration device that stores configuration data for the Cyclone IV E FPGA This configuration data is automatically loaded from the configuration device into the FPGA every time while power is applied to the board Using the Quartus II software 1t 1s possible to reconfigure the FPGA at any time a
28. ic com www terasic com Figure 4 6 VEEK Starter Pattern sub item 4 4 VEEK Picture Viewer This demonstration shows a simple picture viewer implementation using Nios II based SOPC system It reads JPEG images stored on SD Card and displays them the LCD The Nios II CPU decodes the images and fills the raw result data into frame buffers in SDRAM The VEEK will show the image the buffer being displayed points to When users touch the LCD Touch Panel it will proceed to display the next buffered image until there is no filled buffer and enter the Loading phase Figure 4 7 shows the block diagram of this demonstration The Nios II CPU here takes a key roll in the demonstration It is responsible of decoding the JPEG images and coordinates the works of all the peripherals The touch panel handling program uses the timer as a regular interrupter and periodically updates the pen state and sampled coordinates 23 VEEK User Manual www terasic com www teresic com 50MHz SD Socket Figure 4 7 Block diagram of the picture viewer demonstration Demonstration Source Code e Project directory VEEK Picture Viewer e Bitstream used VEEK Picture Viewer sof e Nios II Workspace VEEK Picture ViewenSoftware B Demonstration Batch File Demo Batch File Folder VEEK Picture ViewerNdemo batch The demo batch file includes the following files e Batch File VEEK Picture Viewer bat VEEK Picture
29. illustrates the AS configuration set up To download a configuration bit stream into the EPCS64 serial configuration device perform the following steps e Ensure that power is applied to the VEEK board e Connect the supplied USB cable to the USB Blaster port on the VEEK board e Configure the JTAG programming circuit by setting the RUN PROG slide switch SW 19 to the PROG position The EPCS64 chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the pof filename extension e the programming operation is finished set the RUN PROG slide switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCS64 device to be loaded into the FPGA chip 13 Terasic VEEK User Manual www terasic com www teresic com AN USB Blaster Circuit Quartus ll FROSIRUN AS Mode Auto Power on NDTE2YA Programmer MAX II Config Config EPM 240 e GUARTUS LI Figure 3 5 The AS configuration scheme 3 2 Bus Controller VEEK comes with a bus controller using the Max II EPM240 that allows user to access the touch screen module through the HSMC connector This section describes its structure in block diagram form and its capabilities B Bus Controller Introduction The bus controller provides level shifting functionality from 2 5 V HSMC
30. is placed on pinl and pin3 of JP3 To prevent any changes to the bus controller Max II 240 described in later sections users should not adjust the jumper on JP3 11 Terasic VEEK User Manual www terasic com www terasic com ANU S RYA USB Embedded Blaster Connector 3 TDO t TDI 2 USB EPM240 2 PHY TDI TDO Cyclone IV JP3 Figure 3 1 JTAG Chain JP3 Figure 3 2 The JTAG chain configuration header B Configuring the FPGA in JTAG Mode Figure 3 3 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone IV E FPGA perform the following steps e Ensure that power is applied to the VEEK board e Configure the JTAG programming circuit by setting the RUN PROG slide switch SW19 to the RUN position See Figure 3 4 e Connect the supplied USB cable to the USB Blaster port on the VEEK board The FPGA can now be programmed by using the Quartus II Programmer module to select configuration bit stream file with the sof filename extension 12 Terasic VEEK User Manual www terasic com www terasic co m RYA USB Blaster Circuit PROG RUN Quartus II TETTE Programmer MAX II JTAG UART ANU S RYA 240 TEUER OUARTUS II ow Cyclone IV RUN Figure 3 3 The JTAG chain configuration scheme SW19 Figure 3 4 The RUN PROG switch SW19 is set to JTAG mode B Configuring the EPCS64 in AS Mode Figure 3 5
31. lector project into a local directory of your choice The VEEK Selector project is placed in VEEK Demonstrations VEEK_ Selector e Power on the VEEK board with the USB cable connected to the USB Blaster port e Download the VEEK Selector sof to the board by using either JTAG or AS programming Run the Nios II and choose VEEK_Selector Software as the workspace e Choose Tools gt Flash Programmer to open the flash programmer Choose Program a file into memory choose your VEEK Selector bin file See Figure 5 2 e Click Program Flash to start program VEEK Selector bin to EPCS in the board e When program finish power on again Q You can also use VEEK Selector batch to generate selector bin and restore the original binary file by executing the VEEK Selector bat under the VEEK Factory Recovery WEEK Selector batch folder Flash Programmer Program project to flash memory on target board Program flash with tPad Selector bin using script D tPad Selector Software tPad Selector Debug tpad_selector_programmer sh Hm o 2 3X Name tPad Selector programmer type filter text Connection Flash Programmer Target Hardware tPad Selector prog Additional nios2 flash programmer arguments Load JDI File Additional sof2flash arguments Program FPG configuration data into hardware image region of flash memory Memory Offset v Program a file into flash memory END tPad Selector bin Memory
32. nch a Nios II Command Shell from Start gt Programs gt Altera gt Nios II version gt EDS gt Nios II Command Shell e From the command shell navigate to where your SOF file is located and create your hardware binary file using the following command commands listed below e Convert VEEK Selector sof file into VEEK Selector HW flash file sof2flash epcs inputZVEEK Selector sof output VEEK Selector HW flash e Convert flash file into bin file nios2 elf objcopy I srec binary VEEK Selector HW flash VEEK Selector HW bin e From the command shell navigate to where your ELF file is located and create your software bin image using the following command commands listed below e Convert VEEK Selector elf into VEEK Selector SW flash elf2flash epcs after VEEK Selector HW flash inputZVEEK Selector elf outputZ VEEK Selector SW flash e Convert VEEK Selector SW flash into VEEK Selector SW bin nios2 elf objcopy I srec O binary VEEK Selector SW flash Selector SW bin e Combine VEEK Selector HW bin and VEEK Selector SW bin using the following command cat VEEK Selector HW bin Selector SW bin gt VEEK Selector bin e generated VEEK Selector bin is our target binary file 40 VEEK User Manual www terasic com www teresic com Restoring the original binary file e To restore the original contents of the Application Selector perform the following steps e Copy VEEK Se
33. nd it 1s also possible to change the non volatile data that is stored in the serial configuration device Both types of programming methods are described below 1 programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone IV E FPGA The FPGA will retain this configuration as long as power 15 applied to the board the configuration information will be lost when the power is turned off 2 5 programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera 564 serial configuration device It provides non volatile storage of the bit stream so that the information 15 retained even when the power supply to the VEEK board is turned off When the board s power is turned on the configuration data the 564 device 1s automatically loaded into the Cyclone IV E FPGA B JTAG Chain on VEEK Board To use JTAG interface for configuring FPGA device the JTAG chain on the VEEK must form a close loop that allows Quartus II programmer to detect the FPGA device Figure 3 1 illustrates the JTAG chain on the VEEK board Shorting and pin2 on can disable the JTAG signals on the HSMC connector that will form a close JTAG loopback on DE2 115 See Figure 3 2 Thus only the on board FPGA device Cyclone IV E will be detected by Quartus II programmer By default a jumper
34. ng frame buffer update issue Figure 4 3 Software stack of the VEEK Starter demonstration YadasiC Terasic VEEK User Manual www terasic com B Demonstration Source Code e Project directory VEEK Starter e Bitstream used VEEK Starter sof e Nios II Workspace VEEK_Starter Software Demonstration Batch File Demo Batch File Folder VEEK Starter demo_ batch The demo batch file includes the following files e Batch File VEEK Starter bat VEEK Starter bashrc e FPGA Configure File VEEK Starter sof e Nios II Program VEEK Starter elf B Demonstration Setup e Make sure Quartus II and Nios are installed on your PC e Power on the DE2 115 board e Connect USB Blaster to the DE2 115 board and install USB Blaster driver if necessary e Execute the demo batch VEEK Starter bat under the batch file folder VEEK Starterdemo batch e After Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e From on the touch panel tap any icon of the main interface and start the experience as shown in Figure 4 4 Figure 4 5 and Figure 4 6 e Under each sub item touch the Exit button on the left bottom corner will lead you back to the main interface 21 Terasic User Manual www terasic com www terasic com i Figure 4 4 Main interface of the VEEK Starter demonstration Figure 4 5 The VEEK Starter Touch sub item 22 Tasic Terasic VEEK User Manual www teras
35. ormat and picture in picture mixing with a background layer The video stream 15 output high definition resolution 800x600 on the HSMC LTC daughter card part of the VEEK example design demonstrates a framework for rapid development of video and image processing systems using the parameterizable MegaCore functions that are available in the Video and Image Processing Suite Available functions are listed in Table 4 2 This demonstration needs the Quartus II license file includes the VIP suite feature These functions allow you to fully integrate common video functions with video interfaces processors and external memory controllers The example design uses an Altera Cyclone IV E EP4CE115F29 featured VEEK board A video source 15 input through the CMOS sensor on VEEK which generates a digital output in RGB format A number of common video functions are performed on this input stream in the FPGA These functions include clipping chroma resampling motion adaptive deinterlacing color space conversion picture in picture mixing and polyphase scaling 32 VEEK User Manual www terasic com www terasic com ANU S RYAN The input and output video interfaces on the VEEK are configured and initialized by software running on a Nios II processor Nios II software demonstrates how to control the clocked video input clocked video output and mixer functions at run time is also provided The video syst
36. s by the RAW2RGB block After that the Multi Port SDRAM Controller acquires and writes the RGB data streams to the SDRAM which performs as a frame buffer The Multi Port SDRAM Controller has two write ports and read ports also with 16 bit data width each The writing clock is the same as CMOS sensor pix clock and the reading clock is provided by the LCD Controller which is 40MHz Finally the LCD controller fetches the RGB data from the buffer and displays it on the LCD panel continuously Because the resolution and timing of the LCD is compatible with SVGA 800 600 the LCD controller generates the same timing and the frame rate can achieve about 25 fps CMOS RAW2RGB Controller Capture CMOS Sensor li Pa 7 Configuration Mult Port SDRAM SDRAM tPad Figure 4 12 Block diagram of the digital camera design 30 Terasic VEEK User Manual www terasic com www terasic com B Demonstration Source Code e Project directory VEEK Camera Bit stream used VEEK Camera sof B Demonstration Batch File Demo Batch File Folder CameraMemo batch The demo batch file includes the following files Batch File VEEK Camera bat e FPGA Configure File VEEK Camera sof Demonstration Setup e Load the bit stream into FPGA by execute the batch file VEEK Camera bat under VEEK Camera demo_batch folder e The system enters the FREE RUN mode automatically Press KE Y 0 on the DE2 115 board to re
37. selector searches for applications on the SD Card 2 The application will begin loading and a window will be displayed showing the progress Loading will take between 2 and 30 seconds depending on the size of the application 5 3 Application Selector Details This section describes some details about the operation of the application selector utility SD Card The Application Selector uses the SD Card for storing applications The SD Card must be formatted with the FAT 16 file system and can be any capacity up to 2GB Long file names are supported The Nios II CPU access the SD Card through an SD Card SPI controller Application Files Each loadable application consists of two binary files all stored on the SD Card The first binary file represents the software portion of the example and must be derived from an ELF file as described in the section of this document titled Creating Your Own Loadable Applications This binary file can be named anything supported by the 16 file system the only restriction being that the name must end with _SW bin The second binary file represents the hardware portion of the example and must be derived from a SOF file as described in the section of this document titled Creating Your Own Loadable Applications This file can be named anything supported by the FAT 16 file system the only restriction being that the name must end with HW bin SD Card Directory Structure All loadable applications on th
38. set the circuit e Press KEY 2 to take a shot of the photo you can press KE Y 3 again to switch back to FREE RUN mode and you should be able to see whatever the camera captures on the LCD display e User can use the SW 0 and KEY 1 to set the exposure time for brightness adjustment of the image captured When SW 0 is set to Off the brightness of image will be increased as KE Y 1 is pressed longer If SW 0 is set to On the brightness of image will be decreased as KEY 1 is pressed shorter Q Note execute the VEEK Camera bat under VEEK CameraMemo batch will automatically download the sof file Table 4 3 summarizes the functional keys of the digital camera Figure 4 13 gives a run time photograph of the demonstration Table 4 3 The functional keys of the digital camera demonstration Component Function Description 0 Reset circuit KEY 1 Set the new exposure time use with SW 0 KEY 2 Trigger the Image Capture take a shot KEY 3 Switch to Free Run mode 31 VEEK User Manual www terasic com Extend the exposure time SW O On Shorten the exposure time HEX 7 0 Frame counter Display ONLY Figure 4 13 Screen shot of the VEEK camera demonstration 4 7 Video and Image Processing for Camera The Video and Image Processing VIP for Camera Example Design demonstrates dynamic scaling and clipping of a standard definition video stream in RGB f
39. t 2 2 5V 16 www terasic com Terasic VEEK User Manual CAMERA D3 CAMERA D4 CAMERA D5 CAMERA D6 CAMERA D7 CAMERA D8 CAMERA D9 CAMERA D10 CAMERA D11 CAMERA STROBE CAMERA LVAL CAMERA FVAL PIN G26 PIN H25 PIN H26 PIN K25 PIN K26 PIN L23 PIN L24 PIN M25 PIN M26 PIN G28 PIN K27 PIN K28 CAMERA RESET NPIN M28 CAMERA SCLK PIN K22 CAMERA TRIGGER PIN H23 CAMERA SDATA CAMERA XCLKIN Terasic VEEK User Manual www terasic com PIN H24 PIN G23 Pixel data bit 3 Pixel data bit 4 Pixel data bit 5 Pixel data bit 6 Pixel data bit 7 Pixel data bit 8 Pixel data bit 9 Pixel data bit 10 Pixel data bit 11 Snapshot strobe Line valid Frame valid Image sensor reset Serial clock Snapshot trigger Serial data External input clock 17 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V www terasic com 4 VEEK Demonstrations This chapter gives detailed description of the provided bundles of exclusive demonstrations implemented on VEEK These demonstrations are particularly designed or ported for VEEK with the goal of showing the potential capabilities of the kit and showcase the unique benefits of FPGA based SOPC systems such as reducing BOM costs by integrating powerful graphics and video processing circuits within the FPGA 4 1 System Requirements To run and recompile the demonstrations you should Install

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