WPC1.1-Compatible A5/A11 Wireless Power Transmitter
Contents
1. 0 GP vo General Purpose Input Output Configured as an input 8 om 10 GeneralPurposelmputOuput 100 89 wo 11 SD wo A 2 pp vO USBDataPositwelmput 14 RESET Active high Reset Pin 4uFtoLDOBV and 100kohm ko OD 8 VBUS SNS VBUS OVP sense point amp supply for OVP circuitry 8 mw 11 1 7 7 OOOO 17 REFGND og Signal Ground Connection Comneotlo AGND 18 REGN PWR 8 000 te mmm o SV EDO Outpt uF Capacitor to GND 20 Lops o 2 5V LDO Output 1uF Capacitor to GND a 00285 PWR 25ViDOlpu gt 22 wan PWR 5 inverter Driver Stage Input Supply 28 OVPSEL __ Selects 3 OVP thresholds tie to GND float tie to LDOSV L2 5 5 7 e BST2 1 Bootstrappin for SW2 Bridge Node 26272829 PGND2 GND Power Grown SS 30319235 sw o FullBrdge SwitchNode2 O O o 34353637 wv 1 FulH Bridge Power Supply Input 38394041 sw o j HBrdgeSwitchNodet 46 Bootstrap pinforSW2 Bridge Node 47 GATE 0 ImushFETGateDiverNode 3 3 3 48 ISNS AVG Scaled average input current sense signal used for FOD Adjust cap to GND for fitering 49 Sen Input Current Sense Negative Input so ISNSPIN Input Current Sense Positive Input 5 smem O Shield outputf2. Version 0 8 13 Product Datasheet 4 5 V Min ADAPTOR LZ VBUS SNS IDTP9038 25 ma 45V 25m0 15A 4 46 V C To Inverter mI IDC 1 5 4 46 5 Q 45 mA 4 23 V LDOSV LDO2P5V_IN BAND Ciposv T LDO2P5V Zus ee To IC Demonstration Purposes Only For Dem IDC 45 mA i Not All Connections Shown ections Not To Scale Figure 8 Input Voltage Support Range UVLO The GATE pin and associated MOSFET shown in Fig 8 provide protection for the IDTP9038 from input over voltage events and control current inrush Both of these features are described in subsequent sections of this document FULL BRIDGE MOSFET DRIVE AND MOSFET CURRENT SENSE The IDTP9038 incorporates an integrated full bridge inverter Each half bridge contains a high side current sense block that is used for control and for peak current protection For EMI reduction purposes the switching rising and falling rates of the internal MOSFETSs are limited INPUT OVER VOLTAGE PROTECTION AND SLEW RATE CONTROL The IDTP9038 is powered from a VBUS input which may be subjected to voltages above 5 5V under normal operation The IDTP9038 is required to support voltages as high as 27 V on this input An external OVP MOSFET is used to isolate pins that would be damaged by a 27 V transient on the VBUS input The OVP MOSFET has a second function limiting inrush current f
3. 2 BJ ATE 5327 Aen Ae d KR gan we 1 ala 1 Bo L m L 52 a BAVZ TER i 9 aod ll f Red L 586 5 NE 3K 0405 aa O4 LE ke LB Le NW E Iech 10 13 1 22 CH y a cu JRI rs a T u Pe ad e 337 sk um mie ab 0402 890123 Gi Go a DO SEN 1 G C 55 4 DO HOT 70111 AT E 0412 TF DA DC connector A XR m 1 5 38 at Ki ES oca Integrated Device Technology Inc co HOD FOMENTE IDT INC NA TEIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO Integrated Device Technology Inc IDT USE OK DISCLOSURE MITECUO TEE WEITTEMN OF AN OFFICERE OF LIDT 15 FORBI DIEM DO NOT MODIFY THE VOLTAGE SPECIFICATION OF ANY CAPACITOR KE IC 2013 Integrated Device Technology Inc tion Schemat ica Appl 15 iminary Figure 9 IDTP9038 Prel Version 0 8 IDTP9038 IDT Product Datasheet Components Selection Table 8 Component List oa 2 foci 2F 0803161622615 1206 5111 NP NP 10202 5 1 Loser CI6OBXBR1H682KOB0AA 0603 0 8 4 C0C21C22 C25 j 100F X C3216C0G1H104160MM 1 1200 1 C8 J iF 01005075110262 02 0603 DIODE 23 1 D6 ide BAVZIW7F 90023 29 31
4. 40 to 85 C unless otherwise noted Typical values are at 25 C unless otherwise noted Conditions Notes UA c 19 5 p p UA a M N 5 gt e o UA 300 100 Input 5 Vv ws v kHz kHz kHz US ns Js US ns US pF pF V V P NOTE 1 10m0 1 or better sense resistor amp 10 Q 1 input filter resistors are required to meet the FOD specification NOTE 2 This current is the sum of the input currents for REG_IN IN ISNSP_IN ISNSN_IN and EN_B NOTE 3 For IC operation only do not externally load NOTE 4 Guaranteed by Design Version 0 8 5 O 2013 Integrated Device Technology Inc IDT IDTP9038 Product Datasheet PIN CONFIGURATION amp DESCRIPTION TANDA TANDA TANDA 1159 31179 DAV SNSI NI NSNSI NI dSNSI TQ13lHS LLI Y LLI cc Figure 1 TQFN 56 7mmx7mm O 2013 Integrated Device Technology Inc Version 0 8 IDT IDTP9038 Product Datasheet Table 5 Pin Descriptions 1 p __ Signal Ground Connection 2 Irtemalyconnected donotconnet 4 eros General Purpose InputOutput OOOO 5 804 10 General Purpose Input Output Configured as an output 6 eros vo General Purpose Input Output Configured as an output 7 oe vo General Purpose Input Output Configured as an input
5. IDT Product Datasheet d 6 05 EH AD 1 0 85 011000011101011 Y 775605 E s NOTES 1 ALL DIMENSION ARE IN mm ANGLES IN DEGREES 2 TOP DOWN VIEW AS VIEWED ON PCB 3 COMPONENT OUTLINE SHOW FOR REFERENCE IN BLACK 4 LAND PATTERN IN BLUE NSMD PATTERN ASSUMED 5 LAND PATTERN RECOMMENDATION PER IPC 7351B GENERIC REQUIREMENT FOR MOUNT DESIGN AND LAND PATTERN REVISIONS a UC m mem zen sl A 2 78 sunl cu caca TER TITLE ND NDESE CUTLINE 7 0 x 70 mm 7 0 40 mm PITCH DFN Figure 12 VFQFN 56 7mmx7mm Pacakge Outline Drawing POD Page2 O 2013 Integrated Device Technology Inc 23 Revision 0 8 IDTP9038 IDT Product Datasheet ORDERING GUIDE Table 10 Ordering Summary PART NUMBER PACKAGE AMBIENT TEMP SHIPPING CARRIER RANGE IDTP9038 0NDGI P9038 0NDGI NDG56 VEQFN 56 7x7x0 85 40 C to 85 C Tray 1 IDTP9038 ONDGI8 P9038 ONDGI NDG56 VEQFN 56 7x7x0 85 40 C to 85 C Tape and reel Version 0 8 24 2013 Integrated Device Technology Inc
6. 1 Jo TA 2068878 39 3 828 847 548 lT 7 hh Nr 06 0600 0 40 2 a A 1M 880366105 06003 44 1 8 1006 tRP2GEMOX 40D 45 1 8408 101 7882871910196 805 46 1 R4 dK 680 36101539 608 47 82 0 ERFBGEYOROV 12 ERJ 8GEYOROOV ESA lr E 49 1 5 A ESTA 0600 0 0 50 1 Ra 0 CRCWO60300051A 0608 51 2 R amp R uewe OH 53 6 R53R54R57R62R63R66_ 1 11 1 0 NP NPD 54 2 R58R59 0 085 PGND1 GND1 PGND2 IO2 GND2 PGND3 103 PGNDA SW1 RES1 LC1 101 DMD1 SW2 SHLD2 I2CRL DMD3 59 18 VFOD VBUSNS RSNSP RSNSN ISNSV ISNSP ISNSN ISNS 30AWG 30AWG GATE Version 0 8 16 O 2013 Integrated Device Technology Inc le 025 y 1 IDTP9038 External Components The IDTP9038 requires a minimum number of external components for proper operation see the BOM in Table 8 A complete design schematic compliant to the WPC Qi standard is given in Figure 9 It includes WPC Qi LED and buzzer signaling and an EEPROM for loading IDTP9038 firmware PC Communication The IDTP9038 includes an IC block which can support either 12C Master or 12C Slave operation
7. After power on reset POR the IDTP9038 will initially acts as an Master for the purpose of uploading firmware from an external memory device such as an EEPROM The 1C Master mode on the IDTP9038 does not support multi master mode and it is important for system designers to avoid any bus master conflict until the IDTP9038 has finished any firmware uploading and has released control of the bus as IC Master After any firmware uploading from external memory is complete and when the IDTP9038 begins normal operation the IDTP9038 is normally configured by the firmware to be exclusively in I C Slave mode For maximum flexibility the IDTP9038 tries to communicate with the first address on the EEPROM at 300kHz If no ACK is received communication is attempted at the other addresses at 100kHz EEPROM The IDTP9038 EVK uses an external EEPROM memory chip pre programmed with a standard start up program that is automatically loaded when 5V power is applied The IDTP9038 uses IC master address 0x52 to access the EEPROM The IDTP9038 slave address is 0x39 The EEPROM can be reprogrammed to update the start up program using the IDT Windows GUI see the IDTP9038 Qi Demo Board User Manual for complete details A serial 8Kbyte 8Kx8 64Kbits external EEPROM is sufficient If the standard firmware is not suitable for the application custom EEPROM options are possible IDT will provide the appropriate image in the format best suited to the
8. DTP9038 Where Pomax Maximum Power Dissipation W Oya Package Thermal Resistance C W Tumax Maximum Device Junction Temperature C Ta Ambient Temperature C The maximum recommended junction temperature T max for the IDTP9038 device is 125 C The thermal resistance of the 56 pin NDG package NDG56 is optimally 0 a 25 5 C W Operation is specified to a maximum steady state ambient temperature Ta of 85 C Therefore the maximum recommended power dissipation is Pomax 125 C 85 C 25 5 C W 1 57 Watt Revision 0 8 21 Product Datasheet Thermal Overload Protection The IDTP9038 integrates thermal overload shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fault conditions This circuitry will shut down or reset the device if the die temperature exceeds 140 C To allow the maximum load current on each regulator and resonant transmitter and to prevent thermal overload it is important to ensure that the heat generated by the IDTP9038 is dissipated into the PCB The package exposed paddle must be soldered to the PCB with multiple vias evenly distributed under the exposed paddle and exiting the bottom side of the PCB This improves heat flow away from the package and minimizes package thermal gradients Special Notes NDG VFQFN 56 Package Assembly Note 1 Unopened Dry Packaged Parts have a one year shelf life Note 2 The HIC indic
9. FAST LEDi Green ON BLINKSLOW ON OFF OF Pu am mm mam LED1 Green ON BLINKSLOW ON OFF OFF Standby LEDs ON plus LED2 Red ON OFF OFF ON j BLINK FAST FOD LEDi Green ON BLINKSLOW ON OFF OF Standby LEDs ON plus LED2 Red ON OFF OFF ON BLINK FAST LEDi Green ON BLINKSLOW ON OFF OF PRA i xm NL on AA Pull Up Standby LEDs OFF _LED1 Green OFF BLINKSLOW oy OFF OF PRA im MM ERO i LED1 Green BLINK SLOW o OFF OFF Standby LEDs OFF plus LED2 Red OFF OFF OFF ON BLINK FAST LED1 Green BLINK SLOW ON OFF OF Standby LEDs OFF plus LED2 Red OFF OFF OFF ON BLINK FAST LED1 Green BLINKSLOW ON 08 or Standby LEDs OFF plus LED2 Red OFF OFF OFF ON BLINK FAST Buzzer Action Power Transfer Indication The IDTP9038 supports audible notification when the device operation successfully reaches the Power Transfer state The duration of the power transfer indication sound is 400ms The latency between reaching the Power Transfer state and sounding the buzzer does not exceed 500ms Additionally the buzzer sound is concurrent within O 2013 Integrated Device Technology Inc le 025 y i DT IDTP9038 250ms of any change to the LED configuration indicating the start of power transfer Buzzer Action No Power Transfer Due to Foreign Object Detected FOD Power transfer will fail to in
10. IDTP9038 Either a ground plane or grounded copper shielding can be added beneath the ferrite shield for a reduction in radiated electrical field emissions The coil ground plane shield must be connected to the IDTP9038 ground plane by a single trace Resonance Capacitors The resonance capacitors must be COG type dielectric and have a DC rating to 100V The highest efficiency combination is four 100nF in parallel to get the lowest ESR The part numbers are shown in Table 8 PCB Layout Considerations For optimum device performance and lowest output phase noise the following guidelines must be observed Please contact IDT for Gerber files that contain the recommended board layout As for all switching power supplies especially those providing high current and using high switching frequencies layout is an important design step If layout is not carefully done the regulator could show instability as well as EMI problems Therefore use wide and short traces for high current paths All input decoupling capacitors eg the 0 1uF decoupling capacitor on LDO2P5V IN must be mounted on the component side of the board as close as possible to the O 2013 Integrated Device Technology Inc IDTP9038 Product Datasheet pins intended to be decoupled Keep PCB traces to each VDD pin and to ground vias as short as possible To optimize board layout place all components on the same side of the board Route any unrelated signal traces awa
11. IDTP9038 can be externally reset by pulling the RESET pin to a logic high above the Vu level The RESET pin is a dedicated high impedance active high digital input and its effect is similar to the power up reset function Because of the internal low voltage monitoring scheme the use of the external RESET pin is not mandatory H desired a manual external reset scheme can be added by connecting 5V to the RESET pin through a simple switch When RESET is HIGH the microcontrollers registers are set to the default configuration When the RESET pin is released to a LOW the microcontroller starts loading and executing the code from the external EEPROM If the particular application requires the IDTP9038 to be disabled this can be accomplished with the EN pin When the EN pin is pulled high the device is suspended and placed in low current sleep mode If pulled low the device is active The current into EN is approximately equal to v EN zv 300k or close to zero if V EN is less than 2V SYSTEM FEEDBACK CONTROL For the full description of the communication and control protocol used by the IDTP9038 please refer to the WPC website I EN Note 1 Refer to the WPC specification at http www wirelesspowerconsortium com for the most current information O 2013 Integrated Device Technology Inc Product Datasheet IDTP9038 IDT APPLICATIONS INFORMATION i Gn FD A EM Fiber ACOA Si TODO
12. INPUT g INPUT wl Gate Swi Control Generators CURRENT VOLTAGE Drive E ME SEL 2 moo DETECT i BST2 Si Kessel HS WMT La Current Frequency Non Sense SW2 Synthesizer Overlap PWM2 Logic Gate I Ga Drive amp e REFGND E zi L PGND2 E L l FULL BRIDGE L EPAD PA INVERTER ze 8 L de CLOCK GPIO1 ADC TEMP gt GPIO 0 e mm GEN DETECT x tl gt T T T LEDs Las M EE Buzzers ISNS Thermistors Y Y Y y M d SHIELD2 A 1 DEMODULATOR 58 MSHIELD1 Mm RAM ROM MCU i N uo 1 RESET DIGITAL g SDA Figure 2 IDTP9038 Internal Block Diagram Version 0 8 8 2013 Integrated Device Technology Inc IDT IDTP9038 Product Datasheet TYPICAL PERFORMANCE CHARACTERISTICS IDTP9038 System Efficiency vs RX IOUT IDTP9038 A5 Demo Board V1p0 V 5V Figure 3 Efficiency vs RX Output Current VIN 5V Table 6 IDTP9038 Die Temperature No Load vs RX IOUT 5A T 25C Input Voltage Temp C No Load Temp C Full Load Temp 4 9 34 7 37 2 50V 25 Version 8 9 O 2013 Integrated Device Technology Inc IDTP9038 IDT Product Datasheet 2 Lat E Abee bee doeet ZA 10 0MS s 1 8015 20M poin
13. Threshold Rising 5 c ermal shutdown Threshold Falling Wm Microcontroller fan oar TTT CH Late Tw d 1 EN o Iw 03 Va 63V 25 General Purpose Inputs Outputs GPIO 15 Input Leakage 1 la 8mA 05 RESET 15 T DP DM CHARGER DETECTION Source DP and DM Voltage EF Vos 8 Source Output Source Vor or Vom between 0 5V and 0 7V UA Vom_src Current DP and DM Voltage m EF Source Output Sink Vor or Vom at 2 2 V UA Current Version 0 8 4 2013 Integrated Device Technology Inc IDT IDTP9038 Product Datasheet Table 4 Device Characteristics Continued 5V EN OV Ceus 1UF Ceveass 40uF Coil Symbol Description IDP_SINK Current Sink IDM_SINK VDAT_REF Data detect voltage VDP DM_LGCHI Logic High Logic Low RDP_DWN Pull down Resistance Input Capacitance Dm pin Switch Open Dp pin Switch Open ILK Input Leakage Dm pin Switch Open V 5 0 Dp pin Switch Open V 5 0 SCL SDA 12C Interface 222585 Clock Frequency IDTP9038 as Slave A Hold Time Repeated Ge START Condition Data Hold Time I2C bus devices Clock Low Period Clock High Period START Condition Bus Free Time Between tur STOP and START Condition Capacitive Load for Each i Bane es SCL SDA Cain Capacitance TS roe Ww DA 8778172717 1 Outpt g Deeg A5 Cour_11 400nF Ta
14. altitude and other unlisted variables Table 3 ESD Information TEST MODEL All pins 500 PINS RATINGS UNITS Version 0 8 2 2013 Integrated Device Technology Inc IDT IDTP9038 Product Datasheet SPECIFICATION TABLE Table 4 Device Characteristics Vin 5V EN OV Cisus 1UF Ceveass 40uF Coil A5 Cour 11 400nF Ta 40 to 85 C unless otherwise noted Typical values are at 25 C unless otherwise noted Symbol Description Conditions Notes Min Typ Max Input Supplies amp NES Ge power up sequence complete No coil Operating Input Current 175kHz switching at SW1 SW2 LDOSV 33 45 LDO2P5V After power up sequence complete No coil med no switching at SW1 SW2 7 12 ping LDO2P5V Ge Input Current After power up sequence complete 15 pinging Average including pinging Sleep Mode Input Current EN REG IN 6 9V BY wo lIN REGIN NOTE 2 By ZS A u ick EMEN VREGIN_UVLO Protection Trip Points Falling 34 Nb Hysteresis Full Bridge PWM Generators To 8016 o O A AA Pe Duty cycle Vrec 4 5V 6 9V 10 80 vo Full Bridge Inverter Over Current Protection Vin 5V cycle by cycle protection 3 15 Trip Point Range programmable Range Over Current Protection 1 Units gt o o Input OVP Inrush Control and Current Limit Vaus rising OVP_SEL pin
15. application The IDTP9038 contains an internal ROM that can be modified to match application requirements Please contact IDT sales for more information Revision 0 8 Product Datasheet Overview of Standard GPIO Usage There are 7 GPIO s on the IDTP9038 transmitter IC of which four are available for use as follows e GPIO2 This pin can be connected to an external thermister the voltage of which is digitized by the IDTP9038 s ADC e GPIO3 Green LED B to indicate standby power transfer and power complete see Table 9 e GPIO4 AC or DC buzzer optional with resistor options for different buzzer configurations e GPIO6 Red LED A to indicate standby fault conditions and FOD warnings Table 9 lists how the red and green LEDs can be used to display information about the IDTP9038 s operating modes The table also includes information about external resistors or internal pull up down options to select LED modes Eight of the ten LED modes those associated with advanced charging modes are currently designated as Future modes All GPIOs are configured as inputs during the boot process and then reconfigured according to Table 9 LED FUNCTIONS The two GPIOs used to drive LEDs indicate through various on off and illumination options the state of charging and some possible fault conditions A red LED indicates various Fault and FOD Foreign Object Detection states The green LED indicates Power Transfer and Char
16. ation about the WPC communication protocol can be found at the WPC website Communication can be made more robust by running traces from Shield1 and Shield2 along the HPF trace ANALOG TO DIGITAL CONVERTER ADC The ADC is the main functional block which the MCU uses for IC protection including Foreign Object Detection also digitizes several internal and external voltages and currents for overall system control and improved demodulation functionality USB DP DM FUNCTIONALITY The IDTP9038 implements USB D D detection derived from the BCS1 2 specification The type of USB port powering the IDTP9038 is recognized and stored in internal registers for use by firmware or for customer specific functions FOREIGN OBJECT DETECTION AND INPUT OVER CURRENT PROTECTION The IDTP9038 makes precision measurements of the input voltage and input current which are sampled by the internal ADC and processed in firmware for WPC 1 1 Foreign Object Detection FOD compliance Two external pins ISNS_AVG and VSNS_AVG are provided for filtering the input current sense and input voltage sense signals respectively The input current sense signal is generated from the ISNSP IN and ISNSN IN pins This input current sense signal is filtered with an internal 50142 resistor and an external capacitor on the ISNS AVG pin 1nF Typical Version 0 8 14 500 us to prevent ADC aliasing of the resulting measurements EXTERNAL CHIP RESET and EN The
17. ator card for newly opened Dry Packaged Parts should be checked If there is any moisture content the parts must be baked for minimum of 8 hours at 125 C within 24 hours of the assembly reflow process O 2013 Integrated Device Technology Inc IDT IDTP9038 Product Datasheet EPAD OPTION LASER MARK FOR PIM 1 IDENTIFICATION IN THIS AREA COMMON DIMENSION pono wi Non Tw A 80 0 90 1 00 A1 0 00 0 02 0 05 A2 0 65 0 70 Fm 0 20 REF E 700 bse D2 se cenn ornon SEE EPAD OPTION 0 40 bse ET Figure 11 VFQFN 56 7mmx7mm Package Outline Drawing POD Page 1 LOCATION ON EPAD FIN 1 ID UUUUUUUUUUUUU E A PINI ID 0 20 R LALL DIMENSIONS ARE IN MILLIMETERS ZDE THICKNESS ALLOWABLE IS 0 305 mm MAOMUML 012 INCHES MAXIMUM JSJDIMENSIOMING amp TOLERANCES CONFORM TO ASME 114 54 1994 4 THE FIN 1 IDENTIFIER MUST BE PLACED OM THE TOP SURFACE OF THE PACKAGE EY USING IHHCENTATICA MARK DER OTHER FEATURE OF PACKAGE BODY SHAPE AND SE OF THES FEATURE E OPTIONAL BE PACKAGE WARFAGE MAX 0 08 mem FAPPUED FOR EXPOSED PAD AMD TERMINALS EXCLUDE EMBEDCING PART OF EXPOSED PAD FROM MEASURING BAPPUED ONLY TO TERMINALS 70 x 7 0 ma BODY EE WWE ND NDGS6 PACKAGE OUTLINE 0 40 mm PITCH OFN Packages 2013 Integrated Device Technology Inc 22 Version 0 8 IDTP9038
18. d 9 DT WPC1 1 Compatible Jg Ad A11 Wireless Power Transmitter Product Preview Features Integrated 5V WPC 1 1 compliant Transmitter for AN or A11 type coils Conforms with WPC Specification 1 1 Operates from 5V supplies 4 5V to 6 9V Easy to Use with Reduced Parts Count 8W Power Transfer Solution Integrated Full Bridge Inverter for Optimal Coil Drive Ensures Low EMI RFI Emissions Demodulates and Decodes Communication Packets from WPC compliant Receivers Implements Closed Loop Power Transfer Control Optional Proprietary Back Channel Communication Security and Encryption up to 64 bit USB Interface Supports High Current Charging with D D detection Master Slave H Interface Safety Features Over Current Over Voltage and Over Temperature Protection Fully Integrated Programmable WPC1 1 Compliant Multilayer Foreign Object Detection FOD Power Good and Fault Condition Detection with LED Indicator outputs Applications Charging Mats or Pads Public Facilities Shops Libraries Airports Schools Office Furniture Personal Computer Docks Portable Instruments Package 7x7 56 VFQFN See page 22 Ordering Information See page 24 Version 0 8 IDTP9038 Description The IDTP9038 is a WPC compliant Wireless Power Transmitter for A5 and A11 designs operating from 5V supplies which conforms with WPC Specification 1 1 Operating in the WPC compliant mode the integrated full bridge inverter supports 8W
19. ge Complete state information Upon power up the two LEDs together may optionally indicate the Standby State and remain in this state until another of the defined Operational States occurs As shown in Figure 10 one or two resistors configure the defined LED option combinations The DC voltage set in this way is read one time during power on to determine the LED configuration To avoid interfering with the LED operation the useful DC voltage range must be limited to not greater than 1Vdc O 2013 Integrated Device Technology Inc IDTP9038 Product Datasheet LDO2P5V_OUT IDTP9038 o To ADC LED Mode Resistor Configuration GPIO3 Resistor to set Rb options Figure 10 IDTP9038 LED Resistor Options LED Pattern Operational Status Definitions Table 9 IDTP9038 LED Resistor Optioning LED Control LED Select Option Resistor Value Description R1 R2 R3 R5 R7 R1 R8 are created using combination of two 1 resistors Designates Future Option Buzzer Function An optional buzzer feature is supported on GPIO4 The default configuration is an AC buzzer The signal is created by toggling GPIO4 active high active low at a 2kHz frequency Version 0 8 LED amp Color 18 IDT Not all options supported shaded rows are for future development Operational Status Standby Warning PEN DIE O_O ae Pull Down StandbyLEDsON LED2 Red ON OFF BLINK
20. grounded 67 715 VBUS Over Voltage Veus rising OVP SEL pin 220k 5 to GND 58 83 Protection Trip Point EE Hysteresis 0 Kark 5V Gate cap Ant D Delay from input OVP to VGATE Pull down Time Gate cap 4nF 400 w GATE p r pull down Vous VIN 4V to VIN leuc GATE Leakage VBUS_SNS 0V REG_IN 5V VGATE 10V 4 H Input Average Current Sense REGIN REGIN GEN Input Range ISNSP_IN ISNSN_IN LE AEN iN ISEN Measured Current sense ace accuracy Vrecin 4 5 10 7 2V Isensr 1 5A Note 1 3 Version 0 8 3 O 2013 Integrated Device Technology Inc IDTP9038 IDT Product Datasheet Table 4 Device Characteristics Continued Vin 5V EN OV Cisus 1p F Ceveass 40uF Coil A5 Cour 11 400nF Ta 40 to 85 C unless otherwise noted Typical values are at 25 C unless otherwise noted Symbol Description Conditions Notes Min Typ Max Units Analog to Digital Converter N mmm ER 1 8 Ta une 59900892 OT apu Coke ME e LP 2 LDO2P5V Note 3 wo 1 06066 TO Vor Outputvotage oosa 38 8 0 1 9 5 mM LDO5V Note 3 w muews 8 o Vor Oupoot 9 V ETICO d 1 17 9 Thermal Shutdown T a
21. itiate or will be terminated for safety reasons when a major FOD situation is detected Should this event occur the buzzer will sound in the following repeating sequence For 30 seconds 400ms ON 800ms OFF repeat Next 30 seconds on off patterns Off silence but no change to LED The pattern is repeated while the error condition exists The buzzer is synchronized with the FOD LED such that the 400ms ON tone corresponds with the red LED illumination and 800ms OFF no sound corresponds with the red LED being off Decoupling Bulk Capacitors As with any high performance mixed signal IC the IDTP9038 must be isolated from system power supply noise to perform optimally In general a decoupling capacitor of 0 1uF must be connected between each power supply and the PCB ground plane as close to these pins as possible For optimum device performance the decoupling capacitor must be mounted on the component side of the PCB The value of the capacitors will decrease due to capacitance to applied voltage characteristics of the commonly used ceramic dielectrics For example a 22uF X R 6 3V capacitors value can actually be Gut when operating at 5V depending on the manufacturer Typically 10V or 16V rated capacitors are required The recommended external components are shown in Table 8 Ceramic capacitors in the 10uF 44uF and 1uF range must be used at the REG IN IN and INV5V IN pins respectively These power stage input capacitors m
22. itioning type of transmitter has an array of coils that gives limited spatial freedom to the end user whereas a magnetically guided type of transmitter helps the end user align the receiver to the transmitter with a magnetic attraction The amount of power transferred to the mobile device is controlled by the receiver The receiver sends communication packets to the transmitter to increase power decrease power or maintain the power level The communication is purely digital and communication 1 s and 0 s ride on top of the power link that exists between the two coils To conserve power the transmitter places itself in a very low power sleep mode unless it detects the presence of a receiver Once a receiver is detected the transmitter exits sleep mode and begins the power transfer per the WPC specification INPUT SUPPLIES AND UNDER VOLTAGE LOCKOUT The IDTP9038 receives a VBUS input voltage that is filtered and limited to generate an input rail REG IN which powers the IC and its inverters and to which the majority of the input bulk decoupling capacitance is attached The REG IN rail has a nominal operating range of 4 5V to 6 9V with over voltage protection OVP limiting the voltage up to 85V This voltage range is measured at the VBUS input to the system The actual voltage at REG IN will be lower than that at VBUS due to the voltage drop in the OVP MOSFET The REG IN UVLO enables and disables IDTP9038 s power inverters
23. lacement of the IDTP9038 IC package in proximity to other heat generating devices in a given application design The ambient temperature around the power IC will also have an effect on the thermal limits of an application The main factors influencing Du in the order of decreasing influence are PCB characteristics die package attach thermal pad size and internal package construction Board designers should keep in mind that the package thermal metric Du combines with the characteristics of the PCB itself upon which the VFQFN is mounted Changing the design or configuration of the PCB impacts the overall thermal resistivity and thus the board s heat sinking efficiency Implementation of integrated circuits in low profile and fine pitch surface mount packages typically requires special attention to power dissipation Many system dependant issues such as thermal coupling airflow added heat sinks and convection surfaces and the presence of other heat generating components affect the power dissipation limits of a given component Three basic approaches for performance are listed below 1 Improving the power dissipation capability of the PCB design 2 Improving the thermal coupling of the component to the PCB 3 Introducing airflow into the system enhancing thermal First the maximum power dissipation for a given situation must be calculated Poma Tuma 1 9 2013 Integrated Device Technology Inc IDT I
24. orHPFpin 8 mp _ High Pass Fiter Input for Demodulator ss SHELD2 0 Shield output for HPF pin 3 3 3 3 3 8 op signalGround Connection 55 iss o High side current ISNS Output Signal 85 op Signal Ground Connection 25 GND Exposed Pad ConnectioGND Version 0 8 T 2013 Integrated Device Technology Inc IDTP9038 IDT Product Datasheet INTERNAL BLOCK DIAGRAM IN bres 10mQ 1 0 3V 6 9V 0 2 da eA 40uF Minimum _ Exc k e L 2 Se z Fe ue O 3 O Fz z z 8 E Z lt 1 zi 5 o 8 A gt 62 2 2 lt E 9 Q 9 z z z z i 4 9g 9 49 2 8 9 2 VBUS_SNS E WM WM a E a a a 2 BST e a d HS E Current E VBUS OVP sh Bias amp Reference
25. power transfer utilizing the IDTP902X Receiver family and ensures efficient switching with EMI RFI emissions that are better than the requirements of the WPC specification An embedded microcontroller provides extensive control amp application flexibility In addition to implementing the WPC specified device identification and a closed loop control protocol which constantly adjusts transmitted power the IDTP9038 features a proprietary back channel communication mode compatible with other IDT Wireless Power products providing secure authentication with data encryption using a Secure Hash Algorithm SHA of up to 64 bits Featuring programmable multi layer Foreign Object Detection and built in Over Current Over Voltage and Over Temperature Protection the IDTP9038 is extremely easy to use and provides a complete WPC compliant solution with minimum external parts count requiring significantly less board space and lower total solution cost than competing products It is available in a compact 7mm x 7mm VQFN package A complete Evaluation kit is available with an easy to use GUI interface which allows users to quickly verify system performance and implement WPC compliant designs with minimal effort Wireless Interface Control Reflection 2013 Integrated Device Technology Inc IDTP9038 IDT Product Datasheet ABSOLUTE MAXIMUM RATINGS These absolute maximum ratings are stress ratings only Stresses greater than those lis
26. rom the VBUS line to 150 mA during startup This is necessary due to the USB inrush specification and the large total effective capacitance 40uF on the REG IN and IN pins of the IC The IDTP9038 monitors the VBUS SNS pin for OVP events and shuts off the OVP MOSFET should one be detected In order to protect the VBUS line from regulator induced OVP events the REG IN pin is also monitored for over voltage faults The OVP trip threshold can be configured via a single pin to one of 3 preprogrammed Over Voltage Protection set points as shown in Table 7 O 2013 Integrated Device Technology Inc IDTP9038 IDT Product Datasheet Table 7 VBUS OVP Threshold Selection OVP_SEL pin connection OVP threshold 220kQ to ground The output impedance of the VSNS AVG pin is approximately 33kOhms A capacitor on the VSNS_AVG pin provides filtering for input voltage measurements It is recommended that matching large time constants be used on VSNS_AVG and ISNS_AVG signals on the order of Floating A secondary over voltage protection with a 9 5V threshold is implemented on REG_IN for cases where the OVP MOSFET is bypassed The IC is disabled until the REG_IN voltage drops below 8V DEMODULATION Power transfer from the IDTP9038 to a WPC compliant wireless power receiver is controlled by the receiver Communication packets are superimposed on the power link between the two devices and are demodulated by the IDTP9038 Further inform
27. sed to remove the heat due to device power dissipation The following general guidelines will be helpful in designing a board layout for lowest thermal resistance PC board traces with large cross sectional areas remove more heat For optimum results use large area PCB patterns with wide and heavy 2 oz copper traces In cases where maximum heat dissipation is required use double sided copper planes connected with multiple vias Thermal vias are needed to provide a thermal path to the inner and or bottom layers of the PCB to remove the heat generated by device power dissipation Version 0 8 20 IDT Where possible increase the thermally conducting surface area s openly exposed to moving air so that heat can be removed by convection or forced air flow if available Power Dissipation Thermal Requirements The IDTP9038 is offered in a VFQFN 56L package The maximum power dissipation capability is 1 57W limited by the dies specified maximum operating junction temperature T of 125 C The junction temperature rises with the device power dissipation based on the package thermal resistance The package offers a typical thermal resistance junction to ambient Oya of 25 5 C W when the PCB layout and surrounding devices are optimized as described in the PCB Layout Considerations section The techniques as noted in the PCB Layout section need to be followed when designing the printed circuit board layout as well as the p
28. ted below Table 1 and Table 2 may cause permanent damage to the device Functional operation of the IDTP9038 at absolute maximum ratings is not implied Exposure to absolute maximum rating conditions for extended periods may affect long term reliability Table 1 Absolute Maximum Ratings Summary All voltages are referred to ground Pins Rating Units VBUS_SNS 0 3 to 27 V EN IN REG IN SW1 SW2 ISNSN IN ISNSP IN 0 3 to 12 5 GPIO 6 0 SCL SDA RESET DP DM NC NC1 NC2 NC3 SHIELD2 LDOSV 031055 LDO2P5V_IN INV5V_IN VFOD_SNS ISNS HPF OVP SEL ISNS V BST1 BST2 GND REFGND PGND1 PGND2 Table 2 Package Thermal Information SYMBOL DESCRIPTION Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Thermal Resistance Junction to Board Operating Junction Temperature Ambient Operating Temperature Storage Temperature Lead Temperature soldering 10s 40 to 125 40 to 85 55 to 150 Note 1 The maximum power dissipation is Pomax Tumax Ta 64 where Tumax is 125 C Exceeding the maximum allowable power dissipation will result in excessive die temperature and the device will enter thermal shutdown Note 2 This thermal rating was calculated on JEDEC 51 standard 4 layer board with dimensions 3 x 4 5 in still air conditions Note 3 Actual thermal resistance is affected by PCB size solder joint quality layer count copper thickness air flow
29. ts 0v 68 500 11 Dec 2013 04 39 04 Figure 4 Inrush Current Limit Operation 5 Dec 2013 05 10 49 Figure 5 System Startup with RX IOUT21A Version 0 8 10 2013 Integrated Device Technology Inc IDT IDTP9038 Product Datasheet SIMPLIFIED APPLICATION DIAGRAM EN Csw1 Cour 71 Z1 eh Cisns 1 Cisns_AVG 0 CVSNS_AVG E Figure 6 Typical Application Circuit 4 5 V to OVP Version 0 8 11 2013 Integrated Device Technology Inc IDTP9038 IDT Product Datasheet SIMPLIFIED SYSTEM APPLICATION DIAGRAM Transmitter Receiver Inverter E Modulation Modulation BUCK5VR UNIV Y LDO2P5V_IN lt gt GPIO 6 lt gt GPIO 5 WP lt gt lt gt GPIO SCL lt gt 5 SDA lt gt D Figure 7 Typical System Application Circuit Version 0 8 12 O 2013 Integrated Device Technology Inc b bay ay IDTP9038 Description of the Wireless Power Charging System A wireless power charging system has a base station with one or more transmitters that make power available via DC to AC inverter s and transmit the power over a strongly coupled inductor pair to a receiver in a mobile device WPC transmitter may be a free positioning or magnetically guided type A free pos
30. ust be located as physically close as possible to the related power pins and power ground PGND Ceramic capacitors are recommended for their low ESR and small profile Also ceramic capacitors are inherently more capable than tantalum capacitors and are able to withstand input current surges from low impedance sources such as batteries used in portable devices Use of ceramic capacitors is important for proper LDO operation because they have been designed to function with very low ESR capacitors These capacitors must be located as Revision 0 8 Product Datasheet physically close as possible to the related pins LDOSV LDO2P5V and the ICs quiet ground EP ADC Considerations The GPIO pins can be configured to connect internally to the successive approximation ADC through the ADC s input multiplexer The ADC has a limited input range so attention must be paid to the maximum VIN 2 44V 0 01uF decoupling capacitors to REF GND can be added to the GPIO inputs to minimize noise WPC TX A5 and A11 Coils The SW pins connect to a series resonance circuit comprising a WPC Type A5 or A11 coil and a series resonant capacitor as shown in Figure 9 The coil serves as the primary winding in a loosely coupled transformer the secondary of which is the coil connected to the power receiver IDTP9020 or another The power transmitter coil is mounted on a ferrite shield per the WPC specification The coil assembly can be mounted next to the
31. y from the IDTP9038 The NDG56 7 0 mm x 7 0 mm x 0 85mm 56L package has an inner thermal pad which requires blind assembly It is recommended that a more active flux solder paste be used such as Alpha OM 350 solder paste from Cookson Electronics http www cooksonsemi com Please contact IDT for Gerber files that contain recommended solder stencil design The package center exposed pad EP must be reliably soldered directly to the PCB The center land pad on the PCB set 1 1 with EP must also be tied to the board ground plane primarily to maximize thermal performance in the application The ground connection is best achieved using a matrix of plated through hole PTH vias embedded in the PCB center land pad for the NDG56 The PTH vias perform as thermal conduits to the ground plane thermally a heat spreader as well as to the solder side of the board On the solder side of the board these thermal vias embed in a copper fill having the same dimensions as the center land pad on the component side Recommendations for the via finished hole size and array pitch are 0 3mm to 0 33mm and 1 3mm respectively Layout and PCB design have a significant influence on the power dissipation capabilities of power management ICs This is due to the fact that the surface mount packages used with these devices rely heavily on thermally conductive traces or pads to transfer heat away from the package Appropriate PC layout techniques must then be u
Download Pdf Manuals
Related Search