Home

ABEL Design Manual

1. 10 Chapter 1 ABEL HDL Overview 20 cc cece eee cece eee eee 11 Programmable Design in isoDesignExpert 12 What is Programmable Designing 12 WhatisABEL HDL a 14 Overview of Design 15 APO E FEAE AA AA 15 Project Sources naana 16 DESIGN MISTATGIY AA AA ee AAA 17 Design Compilation 17 le nb A AA 17 Device Programming 17 Chapter 2 ABEL HDL Hierarchical Designs 18 Why Use Hierarchical Design 19 Approaches to Hierarchical Design 19 Creating a new Hierarchical Design 19 TODO WA DESiGN arca narrar A RA AO A ee hehe 20 LOAN e234 AG Aa Pe KG GP AAWGNHHA oo eed bens cede en deen 20 Inside out Mixed Design 20 Specifying a Lower level Module 20 Chapter 3 Compiling ABEL HDL Designs 23 Overview of ABEL HDL Compiling 24 LET a ate KG oe KAMAG wa Pe BA KA
2. 42 Pin to pin Language Features 43 Device independence vs Architecture independence 43 SignalAttributes 43 Sonal Bd ASIA A 43 Pin to pin vs Detailed Descriptions for Registered Designs 44 Using for Pin to pin Descriptions 0 0 cc eee 44 Resolving Ambiguities 44 Detailed Circuit Descriptions 45 Detailed Descriptions Designing for Macrocells 45 Examples of Pin to pin and Detailed Descriptions 47 Pin to pin Module Description 47 Detailed Module Description 47 Detailed Module with Inverted Outputs 48 When to Use Detailed Descriptions 50 Using for Alternative Flip flop Types 50 Using Active low Declarations 51 FOY ND pre ceo heb 848s ERE eke EEA EEE OSE od Wa 53 Polarity Control with IStype 53 Using Istype neg pos and dc to Control Equation and Device Polarity 53
3. E CMOS GAL ispGAL ispLSI pDS pLSI Silicon Forest and UltraMOS are registered trademarks of Lattice Semiconductor Corporation Project Navigator is a trademark of Data I O Corporation ABEL HDL is a registered trademark of Data I O Corporation Microsoft Windows and MS DOS are registered trademarks of Microsoft Corporation IBM is a registered trademark of International Business Machines Corporation Lattice Semiconductor Corporation 5555 NE Moore Ct Hillsboro OR 97124 503 268 8000 December 1999 ABEL Design Manual 2 Limited Warranty Lattice Semiconductor Corporation warrants the original purchaser that the Lattice Semiconductor software shall be free from defects in material and workmanship for a period of ninety days from the date of purchase If a defect covered by this limited warranty occurs during this 90 day warranty period Lattice Semiconductor will repair or replace the component part at its option free of charge This limited warranty does not apply if the defects have been caused by negligence accident unreasonable or unintended use modification or any causes not related to defective materials or workmanship To receive service during the 90 day warranty period contact Lattice Semiconductor Corporation at Phone 1 800 LATTICE Fax 408 944 8450 E mail applications latticesemi com If the Lattice Semiconductor support personnel are unable to solve your problem over the phone we will prov
4. For Help press Fl Time 0 0 na Mode Unit Delay Wa Figure 3 13 Simulator Control Panel Window 3 From the Simulator Control Panel click the Run icon or select Simulate gt Run The simulator runs from the initial time until the time value defined in the Run to Time field 4 Select Tools gt Waveform Viewer after the simulator stops The Waveform Viewer opens with the signals and their waveforms Figure 3 14 m Waveform Viewer AND FF File Edit View Object Tools Options Jump Help CLK INPUT 1 INPUT 2 OUTPUT Q Figure 3 14 Waveform Viewer Window ABEL Design Manual 35 Overview Of ABEL HDL Compiling If you keep the View gt Show Waveforms menu item checked in the Simulator Control Panel the Waveform Viewer will be invoked during the simulation process for you to monitor the simulation results The Waveform Viewer works like a logic analyzer You can display any signal in the design group signals into buses and display them in a choice of radices You can also jump between times place cursors and measure delta times and do other typical logic analyzer tasks For more information on selecting waveforms to view in the Waveform Viewer refer to the Design Verification Tools User Manual ABEL Design Manual 36 Chapter4 ABEL HDL Design Considerations This chapter covers the following topics Overview of ABEL HDL Design Considerations Hierarchy in ABEL HDL Hierarchical Design Considerations Node
5. Lattice a u u u a Corporation ABEL Design Manual Version 8 0 Technical Support Line 1 800 LATTICE or 408 428 6414 DSNEXP ABL DM Rev 8 0 1 Copyright This document may not in whole or part be copied photocopied reproduced translated or reduced to any electronic medium or machine readable form without prior written consent from Lattice Semiconductor Corporation The software described in this manual is copyrighted and all rights are reserved by Lattice Semiconductor Corporation Information in this document is subject to change without notice The distribution and sale of this product is intended for the use of the original purchaser only and for use only on the computer system specified Lawful users of this product are hereby licensed only to read the programs on the disks cassettes or tapes from their medium into the memory of a computer solely for the purpose of executing them Unauthorized copying duplicating selling or otherwise distributing this product is a violation of the law Trademarks The following trademarks are recognized by Lattice Semiconductor Corporation Generic Array Logic ISP ispANALYZER ispATE isp CODE ispDCD ISODOWNLOAD ispDS ispDS isoEXPERT ispGDS ispGDX isoHDL ispJTAG isoSmartFlow ispStarter isoSTREAM ispSVF isp TA isoTEST isoTURBO isoVECTOR ispVerilog isoVHDL isoVM Latch Lock LHDL pDS RFT and Twin GLB are trademarks of Lattice Semiconductor Corporation
6. ABEL HDL and Truth Tables Using X in Truth tables conditions Don t Care used on the left side in Truth tables have no optimization purpose they only serve as a shortcut to write several conditions in one single line Be careful when using X in conditions This can lead to overlapping conditions which look not consistent see example below Due to the way the compiler work this type of inconsistency is not checked nor reported In fact only the ON set condition is taken into account the OFF set condition is ignored The following example illustrates this MODULE DEMO3 TITLE Example 4 TROUES Ay By LE spans Output OuL pin ISE Pe Com Equivalence X S AA Treuth lable CAB CI gt Out LO Osc OS bh TONO CEO IN Ci PO 53S Je ANI NG ex Te ES LO Os 11 gt dase Z4 TA Tncompat ble iyd gt 07 y ALS incompatibles END ki Result Out AA AB LOS F ee E L1 is in fact ignored Out is active high therefore only line L4 is taken into account Likewise L5 intersects L3 but is ignored since it is not in the ON set for Out Globally only L2 L3 and L4 are taken into account as we can check in the resulting equation without any error reported ABEL Design Manual 80 ABEL HDL and Truth Tables Using X on the right side The syntax allows to use X as a target value for an output In this case the condition is simply ignored n NOTE This is not the method to specify optimizable don t care
7. Collapsing Pin to pin Language Features Pin to pin vs Detailed Descriptions for Registered Designs Using Active low Declarations Polarity Control Flip flop Eguations Feedback Considerations Dot Extensions Using Don t Care Optimization Exclusive OR Equation State Machines Using Complement Arrays ABEL HDL and Truth Tables ABEL Design Manual 3 Overview Of ABEL HDL Design Considerations Overview of ABEL HDL Design Considerations This chapter discusses issues you need to consider when you create a design with ABEL HDL The topics covered are listed below Hierarchy in ABEL HDL Hierarchical Design Considerations Node Collapsing Pin to Pin Architecture independent Language Features Pin to Pin Vs Detailed Descriptions for Registered Designs Using Active low Declarations Polarity Control Istypes and Attributes Flip flop Equations Feedback Considerations Using Dot Extensions DCSET Considerations and Precautions Exclusive OR Equations State Machines Using Complement Arrays ABEL HDL and Truth Tables Hierarchy in ABEL HDL You use hierarchy declarations in an upper level ABEL HDL source to refer to instantiate an ABEL HDL module To instantiate an ABEL HDL module In the lower level module optional 1 Identify lower level I O Ports signals with an INTERFACE statement In the top level source 2 Declare the lower level module with an INTERFACE declaration 3 Instantiate the lower level m
8. Detailed One bit Synchronous Circuit with Inverted Qout This version of the design will result in exactly the same fuse pattern as indicated in Figure 4 5 As written this design assumes the existence of an inverted output for the signal Qout This is why the Qout D and Qout Q signals are reversed from the architecture independent version of the design presented earlier The inversion operator applied to Qout D does not correspond directly to the inversion found on each output of a P16R8 The equation for Qout D actually refers to the D input of one of the GAL16LV8 s flip flops the output inversion found in a P16R8 is located after the register and is assumed rather than specified To implement this design in a device that does not feature inverted outputs the design description must be modified The following example shows how to write this detailed design ABEL Design Manual 58 Feedback Considerations Dot Extensions module detail2 Clk ise Toggle Zs Ena Jet OGUE 19 istype reg_D equations QOuUt D Qout Q Toggle Oout Cik Clik QOUuUt OF lEna test_vectors ClLk Ena Toggle seal Ng 7 NG Ne Ne Ne NG Ls Bos nG Cha Me woe 0 Hor 0 OHOP 0100 00 PRRPRPRPRPREO OWE OPO O oe Figure 4 7 Detail One bit Synchronous Circuit with non inverted Qout ABEL Design Manual 59 Using Don t Care Optimization Using Don t Care
9. Identifiers in state machines 65 Inside out design 20 Instantiation 38 Interface submodule 39 Istype and polarity control 54 J JK flip flop and 50 emulation of 63 L Linking modules merging feedbacks 41 post linked optimization 41 Lower level sources 39 instantiating 38 M Mixed design 20 N Node collapsing 42 combinational 40 complement arrays 75 dangling 40 registered 40 removing redundant 41 selective collapsing 42 O Off set 60 One bit changes 72 On set 60 in Truth Tables 78 Optimization and DCSET 61 of XORs 62 post linked 41 reducing product terms 72 Output enables 39 ABEL Design Manual 84 Index p pin2pin abl 57 Pin to pin descriptions 44 and flip flops 54 example 47 resolving ambiguities 44 Polarity control 53 active levels 53 Ports declaring lower level 39 Post linked Optimization 41 Powerup state 67 Preset built in example 48 Product terms reducing 72 Programmable designing 12 Programmable polarity active levels for devices 53 Project sources 16 Properties 31 Q Q11 abl 47 Q12 abl 47 Q13 abl 48 Q15 abl 49 Q17 abl 49 R Redundant nodes 41 Registered design descriptions 44 Registered nodes 40 Registers bit values in state machines 72 cleared state in state machines 67 powerup states 67 Reset example inverted architecture 49 example non inverted architecture 49 resolving ambiguities 49 S Selective collapsing 42 sequence abl 66 Simulation 17
10. Identify States Use Symbolic State Descriptions Use Identifiers Rather Than Numbers for States A state machine has different states that describe the outputs and transitions of the machine at any given point Typically each state is given a name and the state machine is described in terms of transitions from one state to another In a real device such a state machine is implemented with registers that contain enough bits to assign a unique number to each state The states are actually bit values in the register and these bit values are used along with other signals to determine state transitions As you develop a state diagram you need to label the various states and state transitions If you label the states with identifiers that have been assigned constant values rather than labeling the states directly with numbers you can easily change the state transitions or register values associated with each state When you write a state diagram you should first describe the state machine with names for the states and then assign state register bit values to the state names For an example see Figure 4 12 for a state machine named sequence This state machine is also discussed in the design examples Identifiers A B and C specify the states These identifiers are assigned a constant decimal value in the declaration section that identifies the bit values in the state register for each state A B and C are only identifiers
11. Lala y 0 i 0 Falo 1 4 am Ln 18 Col 35 2a e WA Rec Off No Wrap DOS OWA NUM Figure 3 6 Sample ABEL HDL Source File ana_ff2 ab1 11 Select File gt Save from the Text Editor to save the ABEL HDL source file 12 Select File gt Exit to exit the Text Editor ABEL Design Manual 28 Overview Of ABEL HDL Compiling After creating the ABEL HDL source file the Project Navigator updates the Sources window to include the new ABEL HDL source notice the ABEL HDL source icon The Project Navigator also updates the Processes window to reflect the steps necessary to process this source file Design Compliation In general compiling involves every process after Design Entry that prepares your design for simulation and implementation These processes include compiling and optimizing steps which can be done at the level of a single module or for the entire design However which processes are available for your design depends entirely on which device architecture you want to implement your design This chapter discusses some of the general considerations and processes used in ABEL HDL compiling For more information about design considerations refer to Chapter 4 ABEL HDL Design Considerations Keeping Track of Process Auto update Figure 3 7 shows the Project Naviagor window for the and ff2 ABEL HDL module gt ispDesignExpert Project Navigator C JS5PTOOLS4ISPSYS4ERAMPLE Miel E3 File View Source Process Opt
12. OX Ka e Wa Ps o sz db 5g UU 5 Well Br AN y hs Paang a Ob G5 O e Th NE TB NON yo TA og ko De De 7 Wow hh IA Ba O YA akas O 0 0 0 0 5 C 0 0 end Figure 4 12 Using Identifiers for States ABEL Design Manual H OO O 4 oe eed mg Na 66 State Machines Powerup Register States lf a state machine has to have a specific starting state you must define the register powerup state in the state diagram description or make sure your design goes to a known state at powerup Otherwise the next state is undefined Unsatisfied Transition Conditions D Type Flip Flops For each state described in a state diagram you specify the transitions to the next state and the conditions that determine those transitions For devices with D type flip flops if none of the stated conditions are met the state register shown in the following figure is cleared to all Os on the next clock pulse This action causes the state machine to go to the state that corresponds to the cleared state register This can either cause problems or you can use it to your advantage depending on your design D type Register with False inputs NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM NO PRODUCT TERM LOGIC 0 INI gt FO mag A e Figure 4 13 D type Register with False Inputs You can use the clearing behavior of D type flip flops to eliminate some conditions in
13. On Je SETI OFT State Machines Figure 4 15 DCSET compatible State Machine Description Continued ABEL Design Manual 1 State Machines Number Adjacent States for One bit Change You can reduce the number of product terms produced by a state diagram by carefully choosing state register bit values Your state machine should be described with symbolic names for the states as described above Then if you assign the numeric constants to these names so the state register bits change by only one bit at a time as the state machine goes from state to state you will reduce the number of product terms required to describe the state transitions As an example take the states A B C and D which go from one state to the other in alphabetical order The simplest choice of bit values for the state register is a numeric sequence but this is not the most efficient method To see why examine the following bit value assignments The preferred bit values cause a one bit change as the machine moves from state B to C whereas the simple bit values cause a change in both bit values for the same transition The preferred bit values produce fewer product terms State Simple Preferred Bit Values Bit Values B 01 01 C 10 11 D 11 10 If one of your state register bits uses too many product terms try reorganizing the bit values so that state register bit changes in value as few times as possible as the state machine moves from state to state O
14. Optimization Use Dont Care optimization to reduce the amount of logic required for an incompletely specified function The DCSET directive used for logic description sections and ISTYPE attribute dc used for signals specify don t care values for unspecified logic Consider the following ABEL HDL truth table truth_table ES 1 Sle AAO Fr 3 Ap C0 kO Og Oe OJT IE O O le KS Wy O dL o Oe la ells LO O ay AE e ey Ag Ala ESO di Ab LIT des chy hg MG bl dl Id JE ds AY dl Ol la Le Ng Op Aa a O O Kal Tr Ug O a des O Ng lg bd Oy O5 OT 07 07 O UG This truth table has four inputs and therefore sixteen 24 possible input combinations The function specified however only indicates eight significant input combinations For each of the design outputs f3 through f0 the truth table specifies whether the resulting value should be 1 or 0 For each output then each of the eight individual truth table entries can be either a member of a Set of true functions called the on set or a set of false functions called the off set Using output f3 for example the eight input conditions can be listed as on sets and off sets as follows maintaining the ordering of inputs as specified in the truth table above ON SET OT TES OCT Set Ob Ts Or 1 1 1 OL O 20 20 1 1 1 1 000 1 1 1 1 O O 20 le ab L g O L OU g The remaining eight input conditions that do not appear in either the on set or off set are said to be members of th
15. Using invert and buffer to Control Programmable Inversion 54 FID TOD COUO APAT PA TRA POE APAT 54 Feedback Considerations Dot Extensions 55 Dot Extensions and Architecture Independence 56 Dot Extensions and Detail Design Descriptions 58 Using Dont Care Optimization 60 EXE EN aa ee ABA KIDH ANA AA NMA ANUAI AUZE ee ee ee 62 Optimizing KOR Devices 62 Using KOR Operators in Equations 62 Using Implied XORs in Equations o ooocoocooo eee 62 Using XORs for Flip flop Emulation 63 JK Flip Flop Emulation nnnsananasanananan 63 ABEL Design Manual 5 State Machines anna 65 Use Identifiers Rather Than Numbers for States 65 Powerup Register States 67 Unsatisfied Transition Conditions 67 ASEO PA ATA ESE ES 67 FIGONS A AP 68 Precautions for Using Don t Care Optimization 68 Number Adjacent States for One bitChange 72 Use State Register Outputs to Iden
16. circuitry of Figure 4 1 The following figure illustrates this concept JK Allo fiog Emulation O Alio Flog with XQ ANDE Preset 3 Clear gt Q Opa R ADA 3 T 2 gt Clock GQ so Gh amp ak amp Integrated C imutt in Digtal Electro mics Apad uma ard Can Port John Whiley amp Sons 1973 agen Figure 4 11 JK Flip flop Emulation D Flip flop with KOR ABEL Design Manual 64 State Machines State Machines A state machine is a digital device that traverses a predetermined sequence of states State machines are typically used for seguential control logic In each state the circuit stores its past history and uses that history to determine what to do next This section provides some guidelines to help you make state diagrams easy to read and maintain and to help you avoid problems State machines often have many different states and complex state transitions that contribute to the most common problem which is too many product terms being created for the chosen device The topics discussed in the following subsections help you avoid this problem by reducing the number of required product terms The following subsections provide state machine considerations Use Identifiers Rather Than Numbers for States Powerup Register States Unsatisfied Transition Conditions D Type Flip Flops Unsatisfied Transition Conditions Other Flip Flops Number Adjacent States for a One bit Change Use State Register Outputs to
17. device For more information on simulation refer to the Design Verification Tools User Manual Device Programming After the compiler produces a fusemap of your finished design the integrated ISP Download System in ispDesignExpert enables you to download the JEDEC device programming file to an ispLSI device using an isoDOWNLOAD cable See the ISP Daisy Chain Download User Manual for more details ABEL Design Manual 17 Chapter2 ABEL HDL Hierarchical Designs isoDesignExpert supports full hierarchical design Hierarchical structuring permits a design to be broken into multiple levels either to clarify its function or permit the easy reuse of lower level sources For instance a large complex design does not have to be created as a single module By using hierarchical design each component or piece of a complex design could be created as a separate module A design is hierarchical when it is broken up into modules For example you could create a top level ABEL HDL describing a design In the ABEL HDL file you could interface to lower level modules that describe pieces of the design The module represented by the ABEL HDL interface is said to be at one level below the ABEL HDL file in which the INTERFACE statement appears Regardless of how you refer to the levels any design with more than one level is called a hierarchical design In isoDesignExpert there is no limit to the number of hierarchical levels a design can contain Thi
18. end vectors edited State FO KA ps 4 OLLU NS Ske ole Or ye SEL Ji nge sling 0 A Uses Complement Array O O O O O O O O O Clocking is Inhibited until Htrgh to Low Using Complement Arrays Input amp CPLO amp POZO iCles TO TO ABUSO POO amp Claes Th COZ o BIO RORO Calas se NO OS Ec PIO POOK ACE MS To 2 E UPA SO IPOD NGA TA EOS amp EPI Oro POO 6 Clee TI CO G BliO o ABUSO GF Lele TG TO Y amp PL0 amp POLO amp les NT CO 36 a IPLOG IPO e GT NG TO O COMP Clear Clock TFANs1TION Preset high Preset low COMP forces to State 0 Clear Figure 4 17 Transition Equations for a Decade Counter The second equation performs a transition from state 1 to state 2 by setting the P1 register and resetting the PO register The R dot extension is used to define the reset input of the registers In state 2 the FO register remains set maintaining the high output The third equation again sets the PO register to achieve state 3 PO and P1 both set while the fourth equation resets PO and P1 and sets P2 for state 4 and SO ON ABEL Design Manual 76 ABEL HDL and Truth Tables Wraparound of the counter from state 9 to state 0 is achieved by means of the complement array node node 49 The last equation defines state 0 P3 P2 P1 and PO all reset as equal to COMP that is node 49 at a logic low When this equation is processed the fuses are blown As a
19. entered in the ABEL HDL source file This is because the equations were simple Boolean equations that did not require any advanced compiling in order to be processed Using Properties and Strategies For many processes such as the compiling and optimizing steps shown above there are processing options you can specify These options include compiler options such as custom arguments or processing changes and optimization options such as node collapsing You can use properties to specify these options Properties The properties available at any given time depend on the following conditions m The selected type of source file in the Sources window for example ABEL HDL m The selected process in the Processes window ABEL Design Manual 31 Overview Of ABEL HDL Compiling To see how properties are set 1 Highlight the ABEL HDL source file in the Sources window by clicking on the and ff2 ABEL HDL source 2 Highlight do not double click Compile Logic in the Processes window 3 Click the Properties button below the Processes window The Properties dialog box Figure 3 9 appears with a menu of properties This properties menu is specific to the Compile Logic process for an ABEL HDL source Properties Normal ABEL Properties eee Sale panded EJ Generate Listing List Expanded Undo Module Arguments Compile Control Definitions Defaults Advanced Retain Redundant Logic TAF False Help None ABEL
20. from lower level outputs that are not being used in the top level source For example when you use a 4 bit counter as a 3 bit counter The most significant bit of the counter is unused and can be removed from the design to save device resources This step also removes trivial connections In the following example if out 1 is a pin and t1 is a node outl tl tl a80 would be mapped to outl a86 Merging Feedbacks Linking multiple modules can produce signals with one or more feedback types such as FB and Q You can tell the optimizer to combine these feedbacks to help the fitting process Post linked Optimization If your design has a constant tied to an input you can re optimize the design Re optimizing may further reduce the product terms count For example if you have the equation Que A0 a IL ll HAEDO as and i0 is tied to 1 the resulting equation would be simplified to out 11 ABEL Design Manual 41 Hierarchical Design Considerations Hierarchical Design Considerations The following considerations apply to hierarchical design Prevent Node Collapsing Use the signal attribute keep to indicate that the combinational node should not be collapsed removed For example the following ABEL HDL source uses the keep signal attribute MODULE subl TITLE Sub module 1 ay DE PLEN d DIN 7 e node istype keep Equations e a 5 b dq gg a 6 END Node Collapsing All combinational node
21. of the line L4 the result is not intuitive The output is O only for the listed cases L1 L2 L3 and is 1 for all other cases even if dc or pos is used When line L4 is restored then the output equation becomes Out A 8 B amp C because we fall in the general situation where the ON set is not empty Registered Logic in Truth tables Truth Tables can specify registered outputs In this case the assignment become gt instead of gt For more information refer to the ABEL HDL Reference Manual ABEL Design Manual 82 Symbols attribute and polarity control 54 collapse selective collapsing 42 neg and polarity control 53 D 56 FB 55 PIN 55 Q 55 alternate flip flop types 50 DCSET example 61 with state machines 68 xor 62 collapse collapsing nodes 42 Keep collapsing nodes 42 A ABEL HDL enter an ABEL HDL description 25 enter logic description 27 enter test vectors 28 overview 14 properties 31 strategies 32 ABEL HDL Compiling 24 Active low declarations 51 actlow1 abl 52 actlow2 abl 51 Attributes and architecture independence 43 Architecture independence attributes 43 dot extensions 43 56 dot extensions example 57 resolving ambiguities 44 Arrays complement 75 Index Attributes collapsing nodes 42 in lower level sources 39 Auto update 29 B Bottom up design 20 C Collapsing nodes 42 selective 42 Combinational nodes 40 Compilation 17 Complement arr
22. output and define the clocking function for the output ABEL Design Manual 27 Overview Of ABEL HDL Compiling Specifying Test Vectors The method for testing ABEL HDL designs is to use test vectors Test vectors are sets of input stimulus values and corresponding expected outputs that can be used with the functional and timing simulator Test vectors can be specified in two ways They can be specified in the ABEL HDL source or they can be specified in an external Test Vector file abv When you specify the test vectors in the ABEL HDL source the system will create a dummy ABV file design vectors that points to the ABEL HDL source containing the vectors As the test vectors in this sample is very short we just add them to the ABEL HDL source file To add the test vectors to the ABEL HDL source file 10 Type the following test vectors before the END statement in the and ff2 ab1 file Test vectors CIk input 1 input 2 gt output 9 Lo y 0 i 0 gt Us Pai 0 i 0 gt O more 0 l gt Os katad 1 y 1 gt if Figure 3 6 shows the complete ABEL HDL source file e Text Editor and ff2 abl File Edit View Templates Tools Options Window Help x BEE MODULE and ff TITLE And gate and flip flop input _l input_ Clk pin output a pin itype reg Equations output a input 1 amp input_z output g clk Clk Test yectors CIk input 1 input Z 5 output g 0 gt 0
23. predetermined device attributes to imply signal attributes If you do not specify signal attributes or other information such as the dot extensions which are described later your design might not operate consistently if you later transfer it to a different target device Device independence vs Architecture independence The requirement for signal attributes does not mean that a complex design must always be specified with a particular device in mind You may still have to understand the differences between GAL devices and ispLSI devices but you do not have to specify a particular device when describing your design Attributes and dot extensions help you refine your design to work consistently when moving from one class of device architecture to another for example from devices having inverted outputs to those with a particular kind of reset preset circuitry However the more you refine your design using these language features the more restrictive your design becomes in terms of the number of device architectures for which it is appropriate Signal Attributes Signal attributes remove ambiguities that occur when no specific device architecture is declared If your design does not use device related attributes either implied by a DEVICE statement or expressed in an ISTYPE statement it may not operate the same way when targeted to different device architectures See Pin Declaration Node Declaration and Istype in the A
24. representing it The schematic Figure 2 3 must be named AND sch The nets in the lower level schematic correspond to the pin names schematics or pine names ABEL HDL in the upper level module MODULE andl TITLE andl gate Instantiated by nandi Simple hierarchy example The pins must match the Symbol pins schematic or interface names ABEL HDL in the upper level module IN1 IN2 OUT1 pin EQUATIONS OUT1 INI TEST VECTORS Figure 2 4 Lower level ABEL HDL Module for AND1 Interface eo TIP It is best to create the lowest level sources first and then import or create the higher level sources ABEL Design Manual 22 Chapter3 Compiling ABEL HDL Designs This chapter provides information on what the ispEKPERT Compiler functions during compiling ABEL HDL designs It covers the following topics m Design Entry m Design Compilation m Design Simulation ABEL Design Manual 23 Overview Of ABEL HDL Compiling Overview of ABEL HDL Compiling Design Entry In ispDesignExpert when you create an ABEL HDL module and import that module into a design this is called design entry Design entry for ABEL HDL modules is primarily a function of the Project Navigator and a Text Editor used to enter the ABEL HDL code The following sections use a sample to describe how to enter the design in a project Creating a Design Using ABEL HDL Sources Follow the steps to describe the design using ABEL HDL To
25. result as to declare Out of type dc But DCSET must be used with care when multiple outputs are defined they all become dc MODULE DEMO1 TITLE Example 2 h SEROUS Pa By E POS QUEDUE QUE pas Sty oe Com UE Trach Table CLA BG gt 006 1 DON gt Te f TE a 1y YP L 05 A is gt De J7 LA ligal OO AL 200 END Resulting Reduced Equation Out B ABEL Design Manual 78 ABEL HDL and Truth Tables Influence of Signal polarity We will see now with example 3 how the polarity of the signal may influence the truth table In this example Out1 and Out2 are strictly equivalent For Out1 note that the ON set is the O values The third line L3 is ignored MODULE DEMO2 TITLE Example 3 5 AOU eS Fon Bpo pa QUEPut Outlpin istype com neg Out2pin istype com neg Out3pin istype com neg BEWARE Truth_ Table CLAS Bol gt Toul OUT Ques 5 PO Oy Ll iL 308 i O ee Osii gt F O i O az gpl e Ly 0 errs END Resulting Equations huji KOGEL AE WAM Tey li Of Guth OU IA EJ BUT Out3 A amp B C lt lt what you wanted For active low outputs one must be careful to specify 1 for the active state if the Output appears without the exclamation point 0 must be used when output is defined in the table header We recommend the style used for Out1 For Out3 line used is L3 L1 and L2 are ignored ABEL Design Manual 79
26. start a new project and set up a new directory for this tutorial 1 Start isoDesignExpert The Project Navigator window appears 2 Select File gt New Project The Create New Project dialog box Figure 3 1 appears Create New Project Save IN 3 tutor w Project Mame and ff2 syn Save as lupe Project File syn Cancel Project Type Schematicv amp BEL ka Figure 3 1 Create New Project Dialog Box 3 Select Schematic ABEL in the Project Type field This specifies the design source in ispDesignExpert 4 Navigate to a directory where you want to save your project files enter a project name and ff2 syn in the Project Name field 5 Click Save to exit the Create New Project dialog box The Project Navigator displays the new project with the defalut device isoLSI5384E 125LB388 ABEL Design Manual 24 Overview Of ABEL HDL Compiling To change the name of the project 1 Double click on the project notebook icon or project name Untitled that appears at the top of the Sources in Project window The Project Properties dialog box Figure 3 2 appears Project Properties AND gate with a flip flop Cancel Help Figure 3 2 Project Properties Dialog Box 2 Enter a descriptive title AND gate with a flip flop in the Title field 3 Click OK to save the change 4 Select File gt Save from the Project Navigator to save the changes to your new project To enter the ABEL HDL description 1 Select S
27. states See example 2 for such an example Example 6 shows that gt X states are not optimized if DC type or DCSET are not used These lines are ALWAYS ignored MODULE DEMO6 TITLE Example b o LAPUES Ar By CG PY Output Qutpin istype com Equivalence X X Truth_Table A B C gt UE OO gt D KAA ee aS Pos s0 e ox TS oS MAD KI Se AA END li BS AS OUt AKDA B 4 IC fh MICO tetype CON DOC Que Bs They are in fact of no use except maybe as a way to document that output does not matter ABEL Design Manual 81 ABEL HDL and Truth Tables Special case Empty ON set There is a special case which is unlikely to happen but may sometimes occurs Consider this example MODULE DEMOS TITLE Example 5 Inputs Ar B C pin OMEPUTL Outpin istype com pos Truth Table A B C gt Out lO Us 1 Os Oe dg gt 05 llO 01 gt 03 0 0 0 gt 1 changes everything END Without the last line LA Out A 6 B amp C A amp BE C NAK IB C ff WITH L4 Out 14 ID amp 1C What we obtain is slightly unexpected This table should produce Out 0 as the result We enumerated only OFF conditions and the polarity is POS or default so unlisted cases should also turn into zeroes One reason to build such a table could be when multiple outputs are defined and when Out needs to be shut off for whatever reason In the absence
28. to state zero To simplify the following description of the equations in Figure 4 17 node 49 and the complement array feedback are temporarily ignored The first equation states that the FO output register is set to provide the counter output and the PO register is set when registers PO P1 P2 and P3 are all reset counter at state zero and the clear input is low The complemented outputs of the registers with the clear input low form product term 0 Product term 0 sets register PO to increment the decade counter to state 1 and sets register FO to provide an output at pin 18 ABEL Design Manual 75 module DECADE title Decade Counter Michael Holley Data I O Corp Present State POA Pa BZ AN DAR pita Pia Pila Pz decade device F10 5 SAM AA e O A pin 256 16719 P3 PO node 40 4373 COMP node 49 PO P3sa PO STYPE req sr buriter State P3 P2 P1 P0 Hy ity Kgs ee MU Ge eles equations PL BZ ely PO PO lap PR EO Si El MI Els OLE PUE Next State EOS COMP PO LPS oO COMP Plis IA PSO COMP POS PaO e COMP Powe pe eke ORI UBO COME PUSO PEO Eu COMP SAI E PIO 26 COMP PUSS APPS SO amp COMP P3 S P2 R P1 R P0 R P3 0 COMP BOSS BOO Ue PI RP BPE RPO After Preset test_vectors MECA PAGA ll gt O 4 bak EE Ck gt CK O D O QO o 0 gt LACK Op de st See
29. your state diagram and some product terms in the converted design by leaving the cleared register state transition implicit If no specified transition condition is met the machine goes to the cleared register state This behavior can also cause problems if the cleared register state is undefined in the state diagram because if the transition conditions are not met for any state the machine goes to an undefined state and stays there To avoid problems caused by this clearing behavior always have a state assigned to the cleared register state Or if you do not assign a state to the cleared register state define every possible condition so some condition is always met for each state You can also use the automatic transition to the cleared register state by eliminating product terms and explicit definitions of transitions You can also use the cleared register state to satisfy illegal conditions ABEL Design Manual 67 State Machines Other Flip flops If none of the state conditions is met in a state machine that employs JK RS and T type flip flops the state machine does not advance to the next state but holds its present state due to the low input to the register from the OR array output In such a case the state machine can get stuck in a state You can use this holding behavior to your advantage in some designs Precautions for Using Don t Care Optimization When you use don t care optimization you need to avoid certain design p
30. BEL HDL Reference Manual for more information Signal Dot Extensions Signal dot extensions like attributes enable you to more precisely describe the behavior of a circuit that may be targeted to different architectures Dot extensions remove the ambiguities in equations Refer to Feedback Considerations Dot Extensions on page 55 and Language Structure in the ABEL HDL Reference Manual for more information ABEL Design Manual 43 Pin to pin vs Detailed Descriptions for Registered Designs Pin to pin vs Detailed Descriptions for Registered Designs You can use ABEL HDL assignment operators when you write high level eguations The operator specifies a combinational assignment where the design is written with only the circuit s inputs and outputs in mind The assignment operator specifies a registered assignment where you must consider the internal circuit elements such as output inverters presets and resets related to the memory elements typically flip flops The semantics of these two assignment operators are discussed below Using for Pin to pin Descriptions The implies that a memory element is associated with the output defined by the equation For example the equation Ol 101 Preset implies that Q1 will hold its current value until the memory element associated with that signal is clocked or unlatched depending on the register type This equation is a pin to pin description of the out
31. Compatibility List Double click the selected item to cycle through possible choices or use the combo box in the edit region for a list Figure 3 9 Properties Dialog Box 4 In the Properties dialog box select the Generate Listing property 5 Click on the arrow to the right of the text box at the top of the properties menu and select the Expanded option from the list 6 Click on the Close button to accept the setting and exit the Properties dialog box To get information on a property 1 Click on a property in the Properties Dialog box 2 Press the Help button Strategies Another way to set options in your project is to use strategies A strategy is a set of properties processing options that you have specified for some or all of the sources in your project Strategies can be useful as your processing requirements change depending on factors such as size and speed tradeoffs in synthesis or whether your design is being processed for simulation or final implementation With strategies you do not have to modify the properties for every source in the design if you want to change the processing options Strategies allow you to set up properties once then associate a strategy with a source to which you want to apply the properties You can create new strategies that reflect different properties for the entire project and then associate one or more custom strategies with the sources in your project ABEL Design Manual 32 O
32. G kA KA hdd BAM UNAWEKA pee 24 Creating a Design Using ABEL HDL Sources 24 Design Compliation 29 Keeping Track of Process Auto update 29 Compiling an ABEL HDL Source File 30 Using Properties and Strategies 31 Bo A AA 34 ABEL Design Manual 4 Chapter 4 ABEL HDL Design Considerations 37 Overview of ABEL HDL Design Considerations 38 mea dia rr AA EEE AA KAA ee EE 38 Instantiating a Lower level Module in an ABEL HDL Source 39 Identifying I O Ports in the Lower level Module 39 Declaring Lower level Modules in the Top level Source 40 Instantiating Lower level Modules in Top level Source 40 Hierarchy and Retargeting and Fitting 41 giclee as AA 41 MergingFeedbacks 41 Post linked Optimization 41 Hierarchical Design Considerations 42 Prevent Node Collapsing 42 ple Bee LO AA AA ea ee eT a ee eee ee eee TET 42 Selective Collapsing
33. O Y6 Vertical bars indicate options that are mutually exclusive you can select only one For example ENP UE OUEPUT BED Titles of chapters or sections in chapters in this manual are shown in quotation marks For example See Chapter 1 Introduction Indicates a special note Indicates a situation that could cause loss of data or other problems Indicates a special hint that makes using the software easier Indicates a menu option leading to a submenu option For example File gt New ABEL Design Manual Related Documentation Related Documentation In addition to this manual you might find the following reference material helpful isoDesignExpert User Manual isoDesignExpert Tutorial ABEL HDL Reference Manual Schematic Entry User Manual Design Verification Tools User Manual isoLSI Macro Library Reference Manual ISOLSI 5K 8K Macro Library Supplement ISP Daisy Chain Download User Manual isoEXPERT Compiler User Manual VHDL and Verilog Simulation User Manual These books provide technical specifications for the LSC device families and give helpful information on device use and design development ABEL Design Manual 10 Chapter1 ABEL HDL Overview This chapter covers the following topics m Programmable Design in ispDesignExpert m Overview of Design ABEL Design Manual 11 Programmable Design in isoDesignExpert Programmable Design in ispDesignExpert What is Programmable Designing
34. Programmable designing is creating a design that can be implemented into a programmable device PLDs Programmable Logic Devices and CPLDs Complex PLDs are a few examples of programmable devices Figure 1 1 shows an example Design This design has lower level ABEL HDL files not shown MODULE twocnt TITLE two counters having a race Demonstrates ability to use multiple levels of ABEL HDL Hierarchy and to collapse lower level module nodes into upper level modules For example each counter has four REGISTER nodes and this module has four COMBINATORIAL pins The lower level registers are correctly flattened into the top level combinatorial outputs No dot extensions are used allowing the system to determine the best feedback path to use This design uses the advanced fit properties REMOVE REDUNDANT NODES and MERGE EQUIVALENT FEEDBACK NODES COW stamos e SS A AA PUES clk enl enaly IST Pia Outputs Ap Ap el a0 Dor 028 Dl BO PIN E OV OVZ pin istype reg buffer Submodule declarations herent interface clk rst en gt gy G2 Gly G0 Submodule instances enel f nct ional block haerant cnuZ functional block Nieren Figure 1 1 Example of a Top level ABEL HDL source for a Design ABEL Design Manual 12 Programmable Design in isoDesignExpert Equations CHUI el clk ene CIR clk ent Lee cel CneZ rst rst Gisele en cnt2 en en2 Hach counter may be enabled independ
35. Sources ABEL HDL 16 device 16 graphic waveform stimulus 16 project notebook 16 schematic 16 test vector 16 Verilog HDL 16 Verilog test fixture 16 VHDL 16 VHDL test bench 16 SR flip flop and 50 State machine example 66 DCSET 70 no DCSET 68 State machines and DCSET 61 68 cleared register state 67 design considerations 65 identifiers in 65 identifying states 72 illegal states 67 powerup register states 67 reducing product terms 72 using state register outputs 72 State registers 72 Strategies 32 symbolic state descriptions 74 T T flip flop and equations 54 Top down design 20 traffic abl 68 traffic1 abl 70 Transferring designs 43 Transition conditions 67 Tristate outputs 39 Truth Tables ABEL HDL 77 X x1 abl 62 x2 abl 62 XORs and operator priority 63 example 62 flip flop emulation 63 implied 62 optimization of 62 ABEL Design Manual 85
36. alues A symbolic state description is shown below module SM ip 076 LOCK pin w TAPUCS a reset s reset DIN reset inputs py pin istype com simple outputs sregl state register TONO states equations sregl clk clock state diagram sregl state S0 GOCO sh wrth sx y 0 state Sl if a b then 52 with x y State 52 x a 0 Y dy 1f a then S1 else Stave e g t SO with 4 ds y 0 async reset S0 a reset sync reset S0 s reset end Figure 4 16 Symbolic State Description Symbolic state descriptions use the same syntax as non symbolic state descriptions the only difference is the addition of the STATE REGISTER and STATE declarations and the addition of symbolic synchronous and asynchronous reset statements Symbolic Reset Statements In symbolic state descriptions the SYNC RESET and ASYNC RESET statements specify synchronous or asynchronous state machine reset logic For example to specify that a state machine must asynchronously reset to state Start when the Reset input is true you write ASYNC RESET Start Reset ABEL Design Manual 74 Using Complement Arrays Symbolic Test Vectors You can also write test vectors to refer to symbolic state values by entering the symbolic state register name in the test vector header in the output sections and the symbolic state names in the test vectors as output values Using Complement Arrays The complement array is a unique feature found i
37. an fit it The feedback path is specified to be from the register itself and the CLK equation specifies that the memory element is clocked rather than latched ABEL Design Manual 44 Pin to pin vs Detailed Descriptions for Registered Designs Detailed Circuit Descriptions In contrast to a pin to pin description the same circuit can be specified in a detailed form of design description in the following manner Ol Chk Clock Register clocked from input OLD 101 0 Preset D type f f used for register In this form of the design specifying the D input to a D type flip flop and specifying feedback directly from the register restricts the device architectures in which the design can be implemented Furthermore the equations describe only the inputs to and feedback from the flip flop and do not provide any information regarding the configuration of the actual output pin This means the design will operate quite differently when implemented in a device with inverted outputs versus a device with non inverting outputs To maintain the correct pin behavior using detailed equations one additional language element is required a buffer attribute or its complement an invert attribute The buffer attribute ensures that the final implementation in a device has no inversion between the specified D type flip flop and the output pin associated with Q1 For example add the following to the declarations section Q1 pin isty
38. an up counter with active low outputs The first example inverts the signals explicitly in the equations and in the test vector header while the second example uses an active low declaration to accomplish the same thing ABEL Design Manual 52 Polarity Control Polarity Control Automatic polarity control is a powerful feature in ABEL HDL where a logic function is converted for both non inverting and inverting devices A single logic function may be expressed with many different equations For example all three equations below for F1 are equivalent 1 Fl A B 2 F1l A B Sy IPI TA Bs In the example above equation 3 uses two product terms while equation 1 requires only one This logic function will use fewer product terms in a non inverting device than in an inverting device The logic function performed from input pins to output pins will be the same for both polarities Not all logic functions are best optimized to positive polarity For example the inverted form of F2 equation 3 uses fewer product terms than equation 2 IF E2 AA BV G C DI 2 TE A Eh E ADD YA ABG YA ABG DIZ 3 IF2 IA IB IC 1D Programmable polarity devices are popular because they can provide a mix of non inverting and inverting outputs to achieve the best fit Polarity Control with Istype In ABEL HDL you control the polarity of the design equations and target device in the case of program
39. ant to override the values given in the instantiated module otherwise the instantiated module must exactly match the lower level interface statement See Interface top level in the ABEL HDL Reference Manual for more information Instantiating Lower level Modules in Top level Source Use a FUNCTIONAL BLOCK declaration in an top level ABEL HDL source to instantiate a declared lower level module and make the ports of the lower level module accessible in the upper level source You must declare sources with an INTERFACE declaration before you instantiate them To instantiate the module declared above add an interface declaration and signal declarations to your top level declarations and add port connection equations to your top level equations as shown in the source fragment below DECLARATIONS lowl FUNCTIONAL BLOCK lower zed0 zed7 pin upper level inputs atop pin istype reg buffer upper level output d3 d0 pin istype reg buffer upper level ouputs EOUATIONS atop lowl a wire this source s outputs d3 d0 lowl d3 d0 to lower level inputs fowl 20 27 ZeA0 2cA1 wire this source s inputs to lower level outputs See Functional block in the ABEL HDL Reference Manual for more information ABEL Design Manual 40 Hierarchy in ABEL HDL Hierarchy and Retargeting and Fitting Redundant Nodes When you link multiple sources some unreferenced nodes may be generated These nodes usually originate
40. arify its function or permit the easy reuse of functional blocks For instance a large complex design does not have to be created as a single module By using hierarchical designing each component or piece of a complex design could be created as a separate module Figure 1 3 shows a two level hierarchy For more information on hierarchical designing refer to Chapter 2 ABEL HDL Hierarchical Designs Design Compilation After design entry you can compile your design using the isbEXPERT Compiler The compiler first verifies designs for correct syntax then optimizes and parittions designs and fits logic and performs place and route to map the logic to specific devices it finally generates a JEDEC fusemap file used to program the device and a netlist file for post route simulation The compiler gathers all compilation results and writes this information to the isoEXPERT Compiler report that can be read using Process gt View from the Project Navigator lf an error occurs the compiler stops and issues the auto make log file automake 109 in the Report Viewer Using the log file information you can change your design and recompile it Design Simulation In ispDesignExpert functional and timing simulation is available using ABEL HDL Test Vector abv files or Waveform Description Language wd1 files The functional and timing simulator and Waveform Viewer enable you to verify your design before implementing it into a specific
41. ays 75 example 76 D D flip flop unsatisfied transition conditions 67 Dangling nodes 40 dc and polarity control 53 dc abl 61 Dc set 60 and optimization 61 decade abl 76 Declarations active low 51 Design hierarchy 17 Design Overview compilation 17 device programming 17 hierarchy 17 projects 15 simulation 17 sources 16 Dot extensions and detail descriptions 58 Detail descriptions 45 and macrocells 45 example dot extensions 58 59 example inverting 48 example non inverting 47 when to use 50 ABEL Design Manual 83 Index detail1 abl 58 detail2 abl 59 Device programming 17 Devices programmable polarity 53 Don t Care X on left side of Truth Table 80 on right side of Truth Table 81 Detail descriptions and dot extensions 58 Dot extensions D 56 FB 55 PIN 55 Q 55 and architecture independence 43 56 and architecture independence example 57 and feedback 55 example detail 58 59 no 55 E Emulation of flip flops 63 Equation polarity 53 Equations for flip flops 54 XOR 62 F Feedback and dot extensions 55 merging 41 Flip flops and dot extensions 54 detail descriptions 50 D type 67 emulation with XORs 63 state diagrams 50 using with 50 H Hierarchical design abstract 19 advantages of 19 approaches to 19 bottom up 20 defined for ABEL HDL 20 mixed 20 philosophy 19 symbols in 20 techniques 19 top down 20 Hierarchical levels defined 18 Hierarchy 17 38 modular design 18 19
42. bviously the choice of optimum bit values for specific states can require some tradeoffs you may have to optimize for one bit and in the process increase the value changes for another The object should be to eliminate as many product terms as necessary to fit the design into the device Use State Register Outputs to Identify States Sometimes it is necessary to identify specific states of a state machine and signal an output that the machine is in one of these states Fewer equations and outputs are needed if you organize the state register bit values so one bit in the state register determines if the machine is in a state of interest Take for example the following sequence of states in which identification of the Cn states is required ABEL Design Manual 72 State Register Bit Values State Name Q3 B 0 C1 1 C2 1 C3 1 D 0 Q2 0 0 1 1 1 Q1 DO State Machines This choice of state register bit values allows you to use Q3 as a flag to indicate when the machine is in any of the Cn states When Q3 is high the machine is in one of the Cn states Q3 can be assigned directly to an output pin on the device Notice also that these bit values change by only one bit as the machine cycles through the states as is recommended in the section above ABEL Design Manual 73 State Machines Using Symbolic State Descriptions Symbolic state descriptions describe a state machine without having to specify actual state v
43. diagrams n NOTE You also need to specify istype invert or buffer when you use detailed syntax Using for flip flop types other than D type is only possible if register synthesis features are available to convert the generated equations into equations appropriate for the alternative flip flop type specified Since the use of register synthesis to convert D type flip flop stimulus into JK or SR type stimulus usually results in inefficient circuitry the use of for these flip flop types is discouraged Instead you should use the J and K extensions for JK type flip flops or the S and R extensions for SR type flip flops and use a detailed description method including invert or buffer attributes to describe designs for these register types There is no provision in the language for directly writing pin to pin equations for registers other than D type State diagrams however may be used to describe pin to pin behavior for any register type ABEL Design Manual 50 Using Active low Declarations Using Active low Declarations In ABEL HDL you can write pin to pin design descriptions using implied active low signals Active low signals are declared with a operator as shown below SOL pin aShyoe req lf a signal is declared active low it is automatically complemented when you use it in the subsequent design description This complementing is performed for any use of the signal itself including as an i
44. dule 01 51 ol pin istype reg buffer Clock Preset pun equations OCRE Cl ok Q1 AP Preset Q1 c LOTO test Vectors CLOCK Preset gt OL L ws E vee G E a AA O T 2 107 A 4 be il ee a A O gt Oc lb Gag 34 PL Ads E do qJ gt HE end The equation for Q1 still uses the assignment operator and FB for a pin to pin description of Q1 s behavior but the use of AP to describe the reset function requires consideration of different device architectures The AP extension like the Dand Q extensions is associated with a flip flop input not with a device output pin If the target device has inverted outputs the design will not reset properly so this ambiguous reset behavior is removed by using the buffer attribute which reduces the range of target devices to those with non inverted outputs Using ASET instead of AP can solve this problem if the fitter being used supports the ASET dot extension Versions 5 and 7 of the design above and below are unambiguous but each is restricted to certain device classes module 01 71 ol pan istype reg invert Clock Preset ping equations Ol Chk Clock QO1 AR Preset Q1 101 fb test vectors TeClock Preset gt OL i a iy E lAs de E o wy NO o Qs ds E e gy O 1e gt s 0s eee 3 do Ji o Ja MA E dt Se aS end ABEL Design Manual 49 Pin to pin vs Detailed Descriptions for Registered Designs When to Use Detailed Descript
45. e a circuit like the one illustrated in the following figure Figure 4 5 Since the GAL16LV8 features inverted outputs the design equation is automatically modified to take the feedback from Q bar instead of Q Dot Extensions and Archteciure Independence Circuit 2 lt Ejala or E H 4 SHE E TT e E y e A grogi Figure 4 5 Dot Extensions and Architecture independence Circuit 2 ABEL Design Manual 57 Feedback Considerations Dot Extensions Dot Extensions and Detail Design Descriptions You may need to be more specific about how you implement a circuit in a target device More complex device architectures have many configurable features and you may want to use these features in a particular way You may want a precise powerup and preset operation or in some cases you may need to control internal elements The circuit previously described using architecture independent dot extensions could be described for example using detailed dot extensions in the following ABEL HDL source file module detaill al device MPIGA C1k pin 1 Toggle pan 2 Ena pan MLS COTE pin 19 istype reg_D equations POOUCsD Oout 0 amp Toggle Oout CLK Clk Oout OE Ena test_vectors k Ena Toggle Ng 7 Ng AO DB O hRERRPRRRPRRRO ON BS a SC a ee No Ng No Ng PEO SLEEP RB LO OE AS na 7 l 7 l l l 7 Figure 4 6
46. e dc set as follows for f3 dc set of f3 0 0 PRU E O ONO O ADO A E Aa O ES O AO OE po o ke ABEL Design Manual 60 Using Don t Care Optimization Expressed as a Karnaugh map the on set off set and dc set would appear as follows with ones indicating the on set zeroes indicating the off set and dashes indicating the dc set lf the don t care entries in the Karnaugh map are used for optimization the function for f3 can be reduced to a single product term f3 12 instead of the two 13 13 4 12 amp liO 12 4 11 4 10 otherwise required The ABEL HDL compiler uses this level of optimization if the DCSET directive or ISTYPE dc is included in the ABEL HDL source file as shown below module dc so Ay AAO pin o a le pim SEE de com bay H DOHHHHOOH e A q E ES A A O TOCA table H Baha Oo ANN NNNSN YN ES O 0 0 1 je it 1 0 l 7 l l 7 l 7 l Figure 4 8 Source File Showing Don t Care Optimization This example results in a total of four single literal product terms one for each output The same example with no istype dc results in a total of twelve product terms For truth tables Don t Care optimization is almost always the best method For state machines however you may not want undefined transition conditions to result in unknown states or you may want to use a d
47. ed to the higher level source For example a lower level pin with an invert attribute affects the higher level signal wired to that pin it affects the pin s preset reset preload and power up value Output Enables OE Connecting a lower level tristate output to a higher level pin results in the output enable being specified for the higher level pin If another OE is specified for the higher level pin it is flagged as an error Since most tristate outputs are used as bidirectionals it might be important to keep the lower level OE ABEL Design Manual 39 Hierarchy in ABEL HDL Buried Nodes Buried nodes in lower level sources are handled as follows Dangling Nodes Lower level nodes that do not fanout are propagated to the higher level module and become dangling nodes Optimization may remove dangling nodes Combinational nodes Combinational nodes in a lower level module become collapsible nodes in the higher level module Registered nodes Registered nodes are preserved with hierarchical names assigned to them Declaring Lower level Modules in the Top level Source To declare a lower level module you match the lower level module s INTERFACE statement with an INTERFACE declaration For example to declare the lower level module given above you would add the following declaration to your upper level source declarations bower interface fa d3 d0 gt z0 727 4 You could specify different default values if you w
48. efault state determined by the type of flip flops used for the state register for state diagram simplification When using dont care optimization be careful not to specify overlapping conditions specifying both the on set and dc set for the same conditions in your truth tables and state diagrams Overlapping conditions result in an error message For state diagrams you can perform additional optimization for design outputs if you specify the dcstate attribute If you enter dcstate in the source file all state diagram transition conditions are collected during state diagram processing These transitions are then complemented and applied to the design outputs as don t cares You must use dcstate in combination with dcset or the dc attribute ABEL Design Manual 61 Exclusive OR Eguations Exclusive OR Eguations Designs written for exclusive OR KOR devices should contain the xor attribute for architecture independence Optimizing XOR Devices You can use XOR gates directly by writing equations that include XOR operators or you can use implied XOR gates XOR gates can minimize the total number of product terms required for an output or they can emulate alternate flip flop types Using XOR Operators in Equations If you want to write design equations that include KOR operators you must either specify a device that features XOR gates in your ABEL HDL source file or specify the Xor attribute for all output signals that wil
49. ent of the other This module may be used as a Sub module for a higher level design as these counters may be cascaded by feeding the ovoutputs to the en inputs of the next stage OVl Clk elk ov2 clk cik ovl a3 a2 amp al la0 enl look ahead carry overflow ov2 b3 b2 amp bl amp b0 en2 TINOLCATOT as Ct OS A2 CEL OZ al CA ebak a0 Chit GOs DS FERNET D2 CNCA GA D1 CHEZ ql bo ENCA OO test vectors TC Elk rsty en ls ern 0 0 0 do aca Li OS OZ O Ly DUO Vi OZ Ko Ka Dr Kie Br Kr Ng NG Kg OR Figure 1 1 Example of a Top level ABEL HDL source for an Design Continued ABEL Design Manual 13 Programmable Design in isoDesignExpert What is ABEL HDL ABEL HDL is a hierarchical logic description language ABEL HDL design descriptions are contained in an ASCII text file in the ABEL Hardware Description Language ABEL HDL For example the following ABEL HDL code describes a one bit counter block MODULE obcb TITLE One Bit Counter Black INPUTS clk TSC Cl pia 3 Outputs CO pin istype com a pin istype reg Equations g clk GLK G 2 lgb CL Est toggle if carry in and not reset q fb amp ci amp rst hold if not carry in and not reset 0 rst go to 0 if reset co q fb ci Carry out is carry in and q 1 END For detailed information about the ABEL HDL language refer to the ABEL HDL Reference Manual and the o
50. flip flop emulation If you are using an XOR device that has outputs featuring an XOR gate and D type flip flops you can write your design as if you were going to be implementing it in a device with T type flip flops The KOR gates and D type flip flops emulate the specified T type flip flops When using XORs in this way you should not use the xor attribute for output signals unless the target device has XOR gates JK Flip Flop Emulation You can emulate JK flip flops using a variety of circuitry found in programmable devices When a T type flip flop is available you can emulate JK flip flops by ANDing the Q output of the flip flop with the K input The Q output is then ANDed with the J input Figure 4 9 illustrates the circuitry and the Boolean expression JK Ailofiog Emulatbon Using T FRO TIOO Freset Qo td amp I kK Q 07771 Figure 4 9 JK Flip flop Emulation Using T Flip flop ABEL Design Manual 63 Exclusive OR Eguations You can emulate a JK flip flop with a D flip flop and an KOR gate This technique is useful in devices such as the GAL20VP8 The circuitry and Boolean expression is shown in Figure 4 10 T Anp Noo Emuiatbon Using O Alo NJop Preset Clear O FF 1 z E OR 793 3 3 ig gt re 8 F ob Clock Q T 0 Figure 4 10 T Flip flop Emulation Using D Flip flop Finally you can also emulate a JK flip flop by combining the D flip flop emulation of a T flip flop Figure 4 10 with the
51. hematics at increasingly higher levels Bottom up design is ideal for projects in which the top level behavior cannot be defined until the low level behavior is established Inside out Mixed Design Inside out design is a hybrid of top down and bottom up design combining the advantages of both You start wherever you want in the project building up and down as required isoDesignExpert fully supports the mixed approach to design This means that you can work bottom up on those parts of the project that must be defined in hardware first and top down on those parts with clear functional definitions Specifying a Lower level Module The following steps outline how to specify a lower level module in a design module 1 Ina Text Editor open your ABEL HDL file File Open or create a new ABEL HDL file File gt New 2 Inthe ABEL HDL file use the INTERFACE and FUNCTIONAL BLOCK keywords to instantiate lower level files gt TIP You can also use the INTERFACE keyword in lower level files to link to upper level ABEL HDL modules not upper level schematics You can place multiple instances of the same interface in the same design by using the FUNCTIONAL BLOCK statement Refer to the ABEL HDL Reference Manual for more information ABEL Design Manual 20 Specifying a Lower level Module 3 The interface must have same names as the pin names ABEL HDL in the lower level module Figure 2 2 Figure 2 3 and Figure 2 4 show o
52. ide you with instructions on returning your defective software to us The cost of returning the software to the Lattice Semiconductor Service Center shall be paid by the purchaser Limitations on Warranty Any applicable implied warranties including warranties of merchantability and fitness for a particular purpose are hereby limited to ninety days from the date of purchase and are subject to the conditions set forth herein In no event shall Lattice Semiconductor Corporation be liable for consequential or incidental damages resulting from the breach of any expressed or implied warranties Purchaser s sole remedy for any cause whatsoever regardless of the form of action shall be limited to the price paid to Lattice Semiconductor for the Lattice Semiconductor software The provisions of this limited warranty are valid in the United States only Some states do not allow limitations on how long an implied warranty lasts or exclusion of consequential or incidental damages so the above limitation or exclusion may not apply to you This warranty provides you with specific legal rights You may have other rights which vary from state to state ABEL Design Manual 3 Table of Contents UA i A AI 7 ANALIS IMTS MUA ka BA oo heehee oo oo LNG NG GB rara eo ARA RD 8 Where to Look for Information 8 Documentation Conventions 9 Related Documentation
53. ions Although the pin to pin description is preferable there will freguently be situations when you must use a more detailed description If you are unsure about which method to use for various parts of your design examine the design s requirements If your design requires specific features of a device such as register preset or unusual flip flop configurations detailed descriptions are probably necessary If your design is a Simple combinational function or if it matches the generic macrocell in its requirements you can probably use simple pin to pin descriptions Using for Alternative Flip flop Types In ABEL HDL you can specify a variety of flip flop types using attributes such as istype reg D and reg_JK However these attributes do not enforce the use of a specific type of flip flop when a device is selected and they do not affect the meaning of the assignment operator You can think of the assignment operator as a memory operator The type of register that most closely matches the assignment operator s behavior is the D type flip flop The primary use for attributes such as istype reg_D reg_JK and reg_SR is to control the generation of logic Specifying one of the reg_ attributes for example istype reg_D instructs the AHDL compiler to generate equations using the D extension regardless of whether the design was written using D or some other method for example state
54. ions Window Tools Help Strategy Normal Sources in Project Processes for Current Source E AND gate with a flip lop Hierarchy Browser EJ ispLS11016E 100L J44 a Compile Logic and ff wectors wa Check Syntax and ff and ff2 abl 2 Compiler Listing 2 Compiled Equations il Verilog Test Fixture Declarations FE HOL Test Bench Template a Reduce Logic 2 Reduced Equations Double click to open the selected source Double click the item in the list or select the Yew to view the report New Open Stan View Properties Ready Figure 3 7 Project Naviagtor Window with and ff2 syn Loaded ABEL Design Manual 29 Overview of ABEL HDL Compiling There are more processes required for an ABEL HDL source file than for a schematic because the ABEL HDL source file requires compilation and optimization before you can run a simulation And the Project Navigator knows what processes are required to generate a simulation file from an ABEL HDL source you can double click on the end process you want The auto update feature automatically runs any processes required to complete the process you request Device related processes such as mapping the selected ABEL HDL source file to a JEDEC file will be available in the Processes for Current Source window after you select a device for the design Compiling an ABEL HDL Source File The Project Navigator s auto updating reprocesses sources when they are needed to perform the proces
55. l be implemented with KOR gates This preserves one top level XOR operator for each design output For example module X1 Q1 pah ISTYPEe COM KXOT 4 Ap DE pia equations Ol a 418s Cy end Also when writing equations for XOR PALs you should use parentheses to group those parts of the equation that go on either side of the XOR This is because the XOR operator and the OR operator have the same priority in ABEL HDL See example octalf abl Using Implied XORs in Equations High level operators in equations often result in the generation of XOR operators If you specify the XOR attribute these implied XORs are preserved decreasing the number of product terms required For example module X2 DIO2 LAU pin istype req xor lock pin count 54 500 3 equations COU teas CLOCK COUNC YO COU KB lt b LE end This design describes a simple four bit counter Since the addition operator results in XOR operators for the four outputs the xor attribute can reduce the amount of circuitry generated ABEL Design Manual 62 Exclusive OR Eguations The high level operator that generates the XOR operators must be the top level lowest priority operation in the equation An equation such as count count FB 1 reset does not result in the preservation of top level KOR operators since the 4 operator is the top level operator Using XORs for Flip flop Emulation Another way to use XOR gates is for
56. mable polarity devices in two ways m Using Istype neg pos and dc m Using Istype invert and buffer Using Istype neg pos and dc to Control Equation and Device Polarity The neg pos and dc attributes specify types of optimization for the polarity as follows ABEL Design Manual 53 Flip flop Equations neg Istype neg optimizes the circuit for negative polarity Unspecified logic in truth tables and state diagrams becomes a 0 pos Istype pos optimizes the circuit for positive polarity Unspecified logic in truth tables and state diagrams becomes al dc Istype dc uses polarity for best optimization Unspecified logic in truth tables and state diagrams becomes don t care X Using invert and buffer to Control Programmable Inversion An optional method for specifying the desired state of a programmable polarity output is to use the invert or buffer attributes These attributes ensure that an inverter gate either does or does not exist between the output of a flip flop and its corresponding output pin When you use the invert and buffer attributes you can still use automatic polarity selection if the target architecture features programmable inverters located before the associated flip flop The invert and buffer attributes do not actually control device or equation polarity they only enforce the existence or no
57. n pin to pin descriptions are written in ABEL HDL the generic macrocell shown above is synthesized from whatever type of macrocell actually exists in the target device ABEL Design Manual 46 Pin to pin vs Detailed Descriptions for Registered Designs Examples of Pin to pin and Detailed Descriptions Two eguivalent module descriptions one pin to pin and one detailed are shown below for comparison Pin to pin Module Description module 01 1 Od pin istype reg Clock Preset pin equations Ql cik Clocks Q1 101 fb Preset test vectors Clock Preset gt OL o Mora le GG O IH eee Oe Ib Gan vi O PP Ja A op OF 203 lO LL LEN 7 LL es TL end Detailed Module Description module 01 2 Ql pin istype reg_D buffer Clock Preset Din equations OU si Clock Q1 D 01 0 Preset test vectors Clock Preset gt Ol LA 4 lt Les de be AU 4 O T gt 03 ik es 5 O T gt T EE y O J gt 0 ME Ad L J gt T L SEN y J xy Hr end The first description can be targeted into virtually any device if register synthesis and device fitting features are available while the second description can be targeted only to devices featuring D type flip flops and non inverting outputs To implement the second detailed module in a device with inverting outputs the source file would need to be modified as shown in the following section ABEL Design Manual 47 Pin to pin vs Detailed Descri
58. n some logic sequencers This section shows a typical use ending counter sequence You can use transition equations to express the design of counters and state machines in some devices with JK or SR flip flops A transition equation expresses a state of the circuit as a variation of or adjustment to the previous state This type of equation eliminates the need to specify every node of the circuit you can specify only those that require a transition to the opposite state An example of transition equations is shown in Figure 4 17 a source file for a decade counter having a single clock input and a single latched output This counter divides the clock input by a factor of ten and generates a 50 duty cycle squarewave output In addition to its registered outputs this device contains a set of buried or feedback registers whose outputs are fed back to the product term inputs These nodes must be declared and can be given any names Node 49 the complement array feedback is declared as COMP so that it can be entered into each of the equations In this design the complement array feedback is used to wrap the counter back around to zero from state nine and also to reset it to zero if an illegal counter state is encountered Any illegal state and also state 9 will result in the absence of an active product term to hold node 49 at a logic low When node 49 is low product term 9 resets each of the feedback registers so the counter is set
59. n the following Figure 4 3 This circuit toggles high when the Toggle input is forced high and low when the Toggle is low The circuit also contains a three state output enable that is controlled by the active low Enable input Dot Extensions and Arcteciure Independence Circuit T GOUT Figure 4 3 Dot Extensions and Architecture independence Circuit 1 The following simple ABEL HDL design describes this simple one bit synchronous circuit The design description uses architecture independent dot extensions to describe the circuit in terms of its behavior as observed on the output pin of the target device Since this design is architecture independent it will operate the same disregarding initial powerup state irrespective of the device type ABEL Design Manual 56 Feedback Considerations Dot Extensions module pin2pin C1k Toggle Ena LEs OGUE 19 istype reg equations Qout f IQout FB 6 Toggle Qout CLK Clk gout OR Ena kuza Na test_vectors ClLk Ena Toggle e 0 14 0 7 Q Q Ng NG Ng NG Ng NG Ng ba Ons Ga ES me 0 Tor 0 PRRPRPRPRPREO OWE OPO O NG l 7 7 7 l 7 ey l 7 l 7 l 7 l Figure 4 4 Pin to pin One bit Synchronous Circuit module pin2pin If you implement this circuit in a simple GAL16LV8 device either by adding a device declaration statement or by specifying the P16R8 in the Fuseasm process the result will b
60. ne upper level ABEL HDL module and different ways to implement the lower level modules MODULE nandl TITLE Hierarchical nand gate Instantiates an and gate and a not gate Els AG OL PEN The following code defines the interfaces components andl and notl Andl corresponds to the lower level module ANDI vhd ANDI ABI or ANDI SCH For component AND1 the INI IN2 and OUTI interface names correspond to INI IN2 and OUT1 in the lower level module andl INTERPACE CIN INZ OUTIL not LL NTE RE ACE CENT gt OUTIS The following code defines the instances for the interfaces using the functional block statement For the andl interface there is one instance named my and my and functional block andl my nok Tuncuronal block NGELI EQUATIONS my_and IN1 11 my and IN2 12 my NOC LNI andinst OUTL Ol mMY_nOt QUTI Figure 2 2 Top level ABEL HDL Module for NANDI ie Figure 2 3 Lower level Schematic for AND1 Interface ABEL Design Manual 21 Specifying a Lower level Module lf you are in a lower level schematic you can click the Use Data From This Block button in the New Block Symbol dialog box Add gt New Block Symbol to automatically create a functional block symbol for the current schematic The name of the lower level schematic must match the Block Name schematic or the interface name ABEL HDL in the upper level module This associates the lowe level module with the symbol
61. nexistence of an inverter between a flip flop and its output pin The polarity of devices that feature a fixed inverter in this location and a programmable inverter before the register cannot be specified using invert and buffer Flip flop Equations Pin to pin equations using the assignment operator are only supported for D flip flops ABEL HDL does not support the assignment operator for T SR or JK flip flops and has no provision for specifying a particular output pin value for these types If you write an equation of the form OL SS as and the output Q1 has been declared as a T type flip flop the ABEL HDL compiler will give a warning and convert the equation to Clack des ABEL Design Manual 54 Feedback Considerations Dot Extensions Since the T input to a T type flip flop does not directly correspond to the value you observed on the associated output pin this equation will not result in the pin to pin behavior you want To produce specific pin to pin behavior for alternate flip flop types you must consider the behavior of the flip flop you used and write detailed equations that stimulate the inputs of that flip flop A detailed equation to set and hold a T type flip flop is shown below OlT POLO Feedback Considerations Dot Extensions The source of feedback is normally set by the architecture of the target device If you don t specify a particular feedback path the design may ope
62. nline help of isoDesignExpert An online version of the ABEL HDL Reference Manual is provided in the ispDesignExpert CD accessible by selecting Help Manuals from the ispDesignExpert Project Navigator ABEL Design Manual 14 Overview of Design Overview of Design With ispDesignExpert you can create and test designs that will be physically implemented into Programmable devices ispDesignExpert uses the Project Navigator interface Figure 1 2 as the front end to all the design tools which creates an integrated design environment that links together design simulation and place and route tools The Sources in Project Window Sources window The Processes for Current Source Window shows all the design files associated with a project Processes window Aa ispDesignE xpert Project Navigator C AISPTOOLSA ISPSYS EXAMPLES IS Ma ES File View Source Process Options Window Tools Help Strategy Normal Sources in Project Processes for Current Source E Clock Design G Update All Schematic Files El notes wri a Link Design iso 511032EF 100LJ84 Linked Equations bry clock well G Reduce Logic 2 clocktop abv is EDIF Netlist Pi clocktop clocktop sch A Constraint Manager E2 control control sch 4 Compile Design HOLAS hours abl isi JEDEC File FA sseq sseg abl E Compiler Report MINUTES minutes abl Ca Timing Analysis Ay sseq sseg abl Timing Explorer AYPRESCLA presclr abl E Maximum Frequency Re
63. nput as an output and in test vectors Complementing is also performed if you use the fb dot extension on an active low signal The following three designs for example operate identically Design 1 Implied Pin to Pin Active low module act_low2 gQ ql pin istype reg CLOCK pin reset DIN equations Gb oO se ik Clock Laly a0 lt lqL aq0l rB 1 6 reset test vectors clock reset gt al q0 a MN SR LOs O Me Eds y Od Pe P10 e ES A Mi I Sake GA NG E y Dl A e An se a E OP G gt Oo O NG b WG O NE T me E Gad dd gt CC a O NG end ABEL Design Manual 51 Using Active low Declarations Design 2 Explicit Pin to Pin Active low module act Llowl qo gl pin istype reg CLOCK pan reset pin equations O17G0 selk clock Vigil oo A4 bel G0 B 1 a treset test vectors clock reset gt ql q0 i Ga ge al dis Pa O JE ku OL di e5 ON LNG Ls e E MES hh O A Gg Oo WE Los dle E E Oo lp POL als Ei e o as A Je Mos 1 5 0 Come ie end Design 3 Explicit Detailed Active low module act Llow3 uy E pin istype reg_d buffer CLOCK pan reset pias equations fod oO clk Cc loe oq ye0 4D 35 COOL O Os de lt amp NFESEL test_vectors clock reset gt ql q0 Gg y Ad gt ds Ons Lao We MELO Ad a bas Wr all Dh Ho WG Laag O ii 5h Mk 5 ds E Ga ge AA LO O he bees O Jp ak O Ak NG Le E UF 0 1 end Both of these designs describe
64. odule with FUNCTIONAL BLOCK declarations Hierarchy declarations are not required when instantiating an ABEL HDL module in a schematic For instructions on instantiating lower level modules in schematics refer to your schematic reference ABEL Design Manual 38 Hierarchy in ABEL HDL Instantiating a Lower level Module in an ABEL HDL Source Identifying I O Ports in the Lower level Module The way to identify an ABEL HDL module s input and output ports is to place an INTERFACE statement immediately following the MODULE statement The INTERFACE statement defines the ports in the lower level module that are used by the top level source You must declare all input pins in the ABEL HDL module as ports and you can specify default values of O 1 or Don t care You do not have to declare all output pins as ports Any undeclared outputs become No Connects or redundant nodes Redundant nodes can later be removed from the designs during post link optimization The following source fragment is an example of a lower level INTERFACE statement module lower interface a 0 d3 d0 7 gt z0O z7 title example of lower level interface statement This statement identifies input a d3 d2 d1 and d0 with default values and outputs z0 through z7 For more information see Interface lower level in the ABEL HDL Reference Manual Specifying Signal Attributes Attributes specified for pins in a lower level module are propagat
65. on Chapter 1 ABEL HDL Overview Provides an overview of ABEL HDL designs Chapter 2 ABEL HDL Hierarchical Designs Discusses the hierarchical structure in ABEL HDL designs Chapter 3 Compiling ABEL HDL Designs Provides information on the compiling of ABEL HDL designs Chapter 4 ABEL HDL Design Considerations Discusses the design considerations in ABEL HDL designs ABEL Design Manual 8 Documentation Conventions Documen tation Conventions This user manual follows the typographic conventions listed here Convention Italics Bold COU pek FONE Bold Courier Quotes v NOTE A CAUTION TIP gt Definition and Usage Italicized text represents variable input For example design l1 This means you must replace design with the file name you used for all the files relevant to your design Valuable information may be italicized for emphasis Book titles also appear in italics The beginning of a procedure appears in italics For example To run the functional simulation Valuable information may be boldfaced for emphasis Commands are shown in boldface For example Select File gt Open from the Waveform Viewer Monospaced Courier font indicates file and directory names and text that the system displays For example The C isptools ispsys config subdirectory contains Bold Courier font indicates text you type in response to system prompts For example SET YBUS Y
66. ource gt New to create a new design source The New Source dialog box Figure 3 3 appears New Source Schematic ABEL EJ Dk ABEL Test Vectors Cancel Schematic User Document Verilog Test Fisture Help VHDL Test Bench Waveform Stimulus Figure 3 3 New Source Dialog Box 2 Select ABEL HDL Module in the New field 3 Click OK to close the dialog box The Text Editor loads and the New ABEL HDL dialog box Figure 3 4 appears prompting you for a module name file name and title ABEL Design Manual 25 Overview Of ABEL HDL Compiling e Text Editor Al ES File View Templates Tools Optons Help BEE New ABEL HDL Source Module Name and tff File Name and fiZ ab Browse Title r gate with a flip flop PL PHP E Reo f E Nf Cancel Figure 3 4 New ABEL HDL Source Dialog Box 4 In the Module Name field enter and ff 2 5 In the File Name field enter and ff2 ab1 the file extension can be omitted The module name and file name should have the same base name as demonstrated above The base name is the name without the 3 character extension If the module and file names are different some automatic functions in the Project Navigator might fail to run properly 6 If you like enter a descriptive title AND gate with a flip flop in the Title text box 7 When you have finished entering the information click the OK button You now have a template ABEL HDL source file as shown in Figu
67. panded Define Strategies Dialog Box There is a shortcut method to associate a source with a strategy from the Project Navigator Highlight a source and use the Strategy drop down list box in the toolbar to associate an existing strategy with the selected source Design Simulation The following section briefly discusses simulation and waveform viewing For further information on simulation refer to the Design Verification Tools User Manual To simulate the design 1 Highlight the test vector file abv in the Sources window In this tutorial as the test vectors are specified in the ABEL HDL module the and ff2 vectors in the Sources window is actually a dummy test vector file that links to the test vectors in the and ff2 ab1 file Double click on the Functional Simulation process in the Processes window The Project Navigator builds all of the files needed to simulate the design and then runs the functional simulator The Simulator Control Panel Figure 3 13 appears after a successful compiling of the test vectors ABEL Design Manual 34 Overview of ABEL HDL Compiling Simulator Control Panel AND FF e ls pp Step Interval Run to Time 1000 0 ns UTC Simulator Version 1 1 Copyright fc 1998 1999 by Lattice Semiconductor Corporation Initializing mapping data Initializing mapping data successfully ticksize 100 ps stepsize 100000 ps mode unit Loading netlist Loading netlist successfully
68. pe buffer Detailed Descriptions Designing for Macrocells One way to understand the difference between pin to pin and detailed description methods is to think of detailed descriptions as macrocell specifications A macrocell is a block of circuitry normally but not always associated with a device s I O pin Figure 4 1 illustrates a typical macrocell associated with signal Q1 Detailed Macrocel O1 ap 11 0 O1 clk Q1 ar ama Q1 pin 101 pin Figure 4 1 Detailed Macrocell ABEL Design Manual 45 Pin to pin vs Detailed Descriptions for Registered Designs Detailed descriptions are written for the various input ports of the macrocell shown in the figure above with dot extension labels Note that the macrocell features a configurable inversion between the Q output of the flip flop and the output pin labeled Q1 If you use this inverter or select a device that features a fixed inversion the behavior you observe on the Q1 output pin will be inverted from the logic applied to or observed on the various macrocell ports including the feedback port Q1 q Pin to pin descriptions on the other hand allow you to describe your circuit in terms of the expected behavior on an actual output pin regardless of the architecture of the underlying macrocell Figure 4 2 illustrates the pin to pin concept Pin fo oin Macrocel i C1 Pi pe adi ans ee O a KP NG EO a es Qt Figure 4 2 Pin to pin Macrocell Whe
69. port Ay seccntr seccntr abi E Setup Hold Report Double click to choose a different device Double click the item in the list or select the Start button to start the process Select the Properties button to start the property editor New Open Start View Properties Log Ready Figure 1 2 isoDesignExpert Project Navigator Projects In isoDesignExpert a single design is represented by a single project that is created and modified using the Project Navigator The project contains all the logical descriptions for the design In addition the project can contain documentation files and test files A project represents one design but you have the option of targeting your design to a specific device When you switch the target device the processes and design flow in the Project Navigator changes to one that is appropriate for the new target device ABEL Design Manual 15 Overview of Design Project Sources In ispDesignExpert a project design consists of one or more source files Each type of source is identified by an icon and name in the Sources in Project window The Sources in Project window is the large scrollable window on the left side of the Project Navigator display The Sources in Project window lists all of the sources that are part of the project design In addition to the sources that describe the function of the design every project contains at least two special types of so
70. ptions for Registered Designs Detailed Module with Inverted Outputs module 01 3 ol pin istype reg D invert Clock Preset pin equations Ols CLK Clock OLD 01 0 Preset test vectors PeLock Preset gt OL E Gee y L dx E E LES y 0 Y gt 05 las ng O ll gt gt Es y O 5 ec E G f lt 5 Ng JC y bo aa ase end In this version of the module the existence of an inverter between the output of the D type flip flop and the output pin specified with the invert attribute has necessitated a change in the equation for Q1 D As this example shows device independence and pin to pin description methods are preferable since you can describe a circuit completely for any implementation Using pin to pin descriptions and generalized dot extensions such as FB CLK and OF as much as possible allows you to implement your ABEL HDL module into any one of a particular class of devices For example any device that features enough flip flops and appropriately configured I O resources However the need for particular types of device features Such as register preset or reset might limit your ability to describe your design in a completely architecture independent way lf for example a built in register preset feature is used in a simple design the target architectures are limited Consider this version of the design ABEL Design Manual 48 Pin to pin vs Detailed Descriptions for Registered Designs mo
71. put signal Q1 The equation describes the signal s behavior in terms of desired output pin values for various input conditions Pin to pin descriptions are useful when describing a circuit that is completely architecture independent Language elements that are useful for pin to pin descriptions are the assignment operator and the CLK OE FB CLR ACLR SET ASET and COM dot extensions described in the ABEL HDL Reference Manual These dot extensions help resolve circuit ambiguities when describing architecture independent circuits Resolving Ambiguities In the equation above Q1 Q1 Preset there is an ambiguous feedback condition The signal Q1 appears on the right side of the equation but there is no indication of whether that fed back signal should originate at the register come directly from the combinational logic that forms the input to the register or come from the I O pin associated with Q1 There is also no indication of what type of register should be used although register synthesis algorithms could theoretically map this equation into virtually any register type The equation could be more completely specified in the following manner OLE Clock Register clocked from input Q1 Q1 FB Preset Reg feedback normalized to pin value This set of equations describes the circuit completely and specifies enough information that the circuit will operate identically in virtually any device in which you c
72. r is generated if the output enable is not constantly enabled m PIN Extension l a signal is specified with the PIN extension for example count count pin 1 the pin feedback path will be used If the specified device does not feature pin feedback an error will be generated Output enables frequently affect the operation of fed back signals that originate at a pin m Q Extension Signals specified with the Q extension for example count d count q 1 will originate at the Q output of the associated flip flop The fed back value may or may not correspond to the value you observe on the associated output pin if an inverter is located between the Q output of the flip flop and the output pin as is the case in most registered PAL type devices the value of the fed back signal will be the complement of the value you observe on the pin ABEL Design Manual 55 Feedback Considerations Dot Extensions m D Extension Some devices allow feedback of the input to the register To select this feedback use the D extension Some device kits also support COM for this feedback refer to your device kit manual for detailed information Dot Extensions and Architecture Independence To be architecture independent you must write your design in terms of its pin to pin behavior rather than in terms of specific device features such as flip flop configurations or output inversions For example consider the simple circuit shown i
73. ractices The most common design technique that conflicts with this optimization is mixing equations and state diagrams to describe default transitions For example consider the design shown in the following figure module TRAFFIC title Trati Signal Controller CIk SenA SenB pin PR Bin NG Preset control GA YA RA pin Lorel GB YB RB ban LLys Node numbers are not required if fitter is used Dosw node 31 34 istype reg sr buffer COMP node 43 Hali Oks X Count Define Set and Reset inputs to traffic light flip flops GreenA GA S GA R YellowA Loy RedA LS R ia 7 7 7 YellowB Sop NAIG RedB RIN On A 0 OT TE y 1 7 7 7 GreenB so GB Ba 7 test vectors edited eguations GB YB RB GA YA RA AP PR AP PR GB YB RB CLK Clk GA YA RA CLK Clk 0 AP 0 CLK Clk S S Figure 4 14 State Machine Description with Conflicting Logic ABEL Design Manual 68 State Machines Use Complement Array to initialize or restart ESPESA COMP Be Ms Pek GreenA YellowA RedA COMP On Off Off GreenB YellowB RedB COMP Off Off On state_diagram Count State 0 if SenA 6 SenB then O with COM 1 1f SenA SenB then 4 with COMP 1 if SenA SenB then 1 with COMP 1 State 1 goto 2 with COMP 1 State 2 goto 3 with COMP 1 State 3 goto 4 with COM 1 State 4 GreenA Off Yello
74. rate differently in different device types Specifying feedback paths with the FB Q or PIN dot extensions eliminates architectural ambiguities Specifying feedback paths also allows you to use architecture independent simulation The following rules should be kept in mind when you are using feedback m No Dot Extension A feedback signal with no dot extension for example count count 1 results in pin feedback if it exists in the target device If there is no pin feedback register feedback is used with the value of the register contents complemented normalized if needed to match the value observed on the pin m FB Extension A signal specified with the FB extension for example count count fb 1 results in register feedback normalized to the pin value if a register feedback path exists If no register feedback is available pin feedback is used and the fuse mapper checks that the output enable does not conflict with the pin feedback path If there is a conflict an error is generated if the output enable is not constantly enabled m COM Extension A signal specified with the COM extension for example count count com 1 results in OR array pre register feedback normalized to the pin value if an OR array feedback path exists If no OR array feedback is available pin feedback is used and the fuse mapper checks that the output enable does not conflict with the pin feedback path If there is a conflict an erro
75. re 3 5 ABEL Design Manual 26 Overview Of ABEL HDL Compiling e Text Editor and f2 abl a OF ES E File Edit View Templates Tools Options Window Help IP x HAEE MODULE and_tt2 TITLE And gate and flip flop END T Ln Cald WIR eo Dif No wrap DOS INS NUM Figure 3 5 Template ABEL HDL Source File For detailed syntax on ABEL HDL language refer to the ABEL HDL Reference Manual To enter the logic description 8 Add declarations for the three inputs two AND gate inputs and the clock and the output by entering the following statements in the ABEL HDL source file If a TITLE statement exists in the template file enter these statements after the TITLE statement LOPut dl inp t_ 2 Clk pin output q pin istype reg These two statements declare four signals input_1 input_2 CIk and output 9 ABEL HDL does not have an explicit declaration for inputs and outputs whether a given signal is an input or an output depends on how it is used in the design description that follows The signal output_g is declared to be type reg which implies that it is a registered output pin The actual behavior of output q however is specified using one or more equations 9 To describe the actual behavior of this design enter two equations in the following manner Equations OUtput g input L amp inp t 2 OUEPUE g clk Cilk These two equations define the data to be loaded on the registered
76. result the ICOMP signal is true to generate product term 9 and reset all the buried registers to zero ABEL HDL and Truth Tables Truth Tables in ABEL HDL represent a very easy and straightforward description method well suited in a number of situations involving combinational logic The principle of the Truth Table is to build an exhaustive list of the input combinations referred to as the ON set for which the output s become s active The following list summarizes design considerations for Truth Tables Following the list are more detailed examples m The OFF set lines in a Truth Table are necessary when more than one output is assigned in the Truth Table In this case not all Outputs are fired under the same conditions and therefore OFF set conditions do exist m OFF set lines are ignored because they represent the default situation unless the output variable is declared dc In this case a third set is built the DC set and the Output inside it is assigned proper values to achieve the best logic reduction possible m f output type dc or dcset is not used and multiple outputs are specified in a Truth table consider the outputs one by one and ignore the lines where the selected output is not set m Don t Cares X used on the right side of a Truth Table have no optimization effect m When dealing with multiple outputs of different kind avoid general settings like DCSET which will affect all your outputs Use ist
77. rol GA YA RA pan 15 GB YB RB pia alles SIRO 0 node 31 34 istype reg sr buffer Hy Ly CR X a ah UG Gg BY Count SSI NIE Define Set and Reset inputs to traffic light flip flops GreenA GA S GA YellowA OL Png RedA a BAD GreenB Bi RedB Ba On 5 0 OLE ga Ad test vectors edited R li l7 l7 YellowB Dp Ba Els l7 li li equations GB YB RB GA YA RA PR GB YB RB Cik YA RA CES CLK S S J Ey Jl a Jha 0 AP PR ge Clk Figure 4 15 DCSET compatible State Machine Description ABEL Design Manual 70 DCSET state diagram end State State State State State State State State State State State State State State State State COUNT LOs ss be Eo tA LO 1f SenA if SenA 1f SenA GOCO As GOCO 2 goto 4 GreenA YellowA GOGO 257 YellowA RedA RedB GreenB Goto 83 Gocco Us goto 0 if SenA 1f SenA 1f SenA JOGO L07 goto Lil goto 12 GreenB YellowB GOLO 154 YellowB RedB RedA GreenA Goto 0 goto U Power Up RedA YellowA GreenA RedB YellowB GreenB Coco Oy 4 SenB amp SEenB SenB then 0 then 4 Chen 13 Or Om ULTI On OT On amp SenB amp SenB SenB then 8 LERNER LA then 9 E ON 7 ULTI Om OIT On and preset state OTT OLT O 3
78. s are collapsible by default Nodes that are to be collapsed or nodes that are to be preserved are flagged through the use of signal attributes in the language The signal attributes are Istype keep Do not collapse this node collapse Collapse this node Collapsing provides multi level optimization for combinational logic Designs with arithmetic and comparator circuits generally generate a large number of product terms that will not fit to any programmable logic device Node collapsing allows you to describe equations in terms of multi level combinational nodes then collapse the nodes into the output until it reaches the product term you specify The result is an equation that is optimized to fit the device constraints Selective Collapsing In some instances you may want to prevent the collapsing of certain nodes For example some nodes may help in the simulation process You can specify nodes you do not want collapsed as Istype keep and the optimizer will not collapse them ABEL Design Manual 42 Pin to pin Language Features Pin to pin Language Features ABEL HDL is a device independent language You do not have to declare a device or assign pin numbers to your signals until you are ready to implement the design into a device However when you do not specify a device or pin numbers you need to specify pin to pin attributes for declared signals Because the language is device independent the ABEL HDL compiler does not have
79. s chapter covers the following topics m Why Use Hierarchical Design m Approaches to Hierarchical Design m Specifying a Lower level Module in an ABEL HDL Module ABEL Design Manual 18 Why Use Hierarchical Design Why Use Hierarchical Design The primary advantage of hierarchical design is that it encourages modularity For instance a careful choice of the circuitry you select to be a module will give you a module that can be reused Another advantage of hierarchical design is the way it lets you organize your design into useful levels of abstraction and detail Approaches to Hierarchical Design Hierarchical designs consists of ONE top level The lower level modules can be of any supported source ABEL HDL sources and are represented in the top level module by a place holder You can create the top level module first or create it after creating the lower level modules Figure 2 1 illustrates a two level hierarchical project Sources in Project ABL bE FSSR bhtRAM 2 Project Title Bl designbk wei EJ ispLSI61920M 0LM208 im psbk abw 8 RM12PS6K rm12ps6k abl PA P3SREXT6 pssr8x16 abl ARAM 2 rarn12 ab Top level ABEL HDL Source Lower level ABEL HDL Sources Figure 2 1 Example of a Hierarchical Project in the Project Navigator Creating a new Hierarchical Design Hierarchical entry is a convenient way to enter a large design one piece at atime It is also a way of organizing and struc
80. s you request You do not need to worry about when to recompile ABEL HDL source files However you can compile an individual source file by highlighting the file in the Sources window and double clicking on Compile Logic in the Processes window Alternatively you can double click on a report in the Processes window and compile automatically To compile an ABEL HDL file and view the report 1 Highlight a ABEL HDL source file and ff2 ab1 in the Sources window 2 Double click Compiled Equations in the Processes window The source file is compiled and the resulting compiled equations are displayed in the Report Viewer Figure 3 8 If the ABEL HDL file contains syntax errors the errors are displayed in a view window and an error indication appears in the Processes window ABEL Design Manual 30 Overview of ABEL HDL Compiling VYA Report Viewer and ff2 eqi File Edit View Options Window Help 1splles1gnEx pert 8 0 Design and ft created Mon Dec 06 10 57 45 1999 Title And gate and flip flop Fan in Fan out Type Name attributes Pin output g REG Pin output q Best P Term Total Total Pins Total Nodes Average P Tern Qutput Equations output_q input 1 4 input 2 output g C Clk Reverse Polarity Equations loutputog C 1C1k into 23 RO ec0f No Wap DOS INS NUM Figure 3 8 Compiled Equations for and ff2 In this example the compiled equations are identical to the equations that you
81. they do not indicate the bit pattern of the state machine Their declared values define the value of the state register sreg for each state The declared values are 0 1 and 2 ABEL Design Manual 65 module Seguence title State machine example CAO pin 14 15 istype reg clock enab start hold reset pin raid A E helt Pin 17 istype reg in Bin C pin 12413 Stype com sreg q1 q0 7 State Values A 0 B Ls O Ag equations Po oO Rate aci clocks q1 390 halt oe enab state_diagram sreg State Machines 0 H O o OO O O Li Li Le Ld xo xo xo xo xo Na State A Hold In state A until start 18 active in B 0 in G s Uy IF start reset THEN B WITH halt 0 ELSE A WITH Dalt gt alt to State B Advance to state C unless reset is active in B 1 or hold is active Turn on halt indicator in_C 0 LE Ceset IF reset THEN A WITH halt 1 ELSE IP hold THEN Bs NITE halt 03 ELSE E WITH Batt YA 05 State Cs Go back to A unless hold is active in_B 0 Reset overrides hold in C 13 IF hold 4 1teset THEN C WITH halt 4 0 ELSE A WITH halt 0 test vectors clock enab start reset hold 5 sreg halt in B in C be e e a Og ih IE ao MR O keu De e e Doa AA De UD a Ue Est y D LE qa Wo 5 A ls Bs 0D 3 Ls E De 0 5 e Disk Ep UN a HO EE ays De E Os ox IK o O e O Be 05 WAA y OT Bra OL bs kao Na Ds At o O 15G As os Ds kae Die xx Ub 5
82. tify States 72 State Register Bit Values 73 Using Symbolic State DescriptionS 74 Symbolic Reset Statements 74 Symbolic Test Vectors 75 Using Complement ArrayS 75 ABEL HDL and Truth Tables 77 Basic Syntax SimpleEkamples 78 Influence of Signal polarity 79 Using X in Truth tables conditions 80 LISTO e CT Ne TON IIo ob PAG aserrada ude be KS deidad 81 Special case Empty ON Set 82 Registered Logic in Truthtables 82 ABEL Design Manual 6 Preface This manual provides information on ABEL HDL design sources hierarchical structure compiling and design considerations It is assumed that you have a basic understanding of ABEL HDL design ABEL Design Manual What is in this Manual What is in this Manual This manual contains the following information m Introduction to ABEL HDL design m Hierarchical design in ABEL HDL m ABEL HDL compiling m ABEL HDL design considerations Where to Look for Informati
83. turing your design and the design process The choice of the appropriate methodology can speed the design process and reduce the chance of design or implementation errors There are three basic approaches to creating a multi module hierarchical design m Top down m Bottom up m Inside out mixed Regardless of the approach you choose you start from those parts of the design that are clearly defined and move up or down to those parts of the design that need additional definition The following sections explain the philosophy and techniques of each approach ABEL Design Manual 19 Specifying a Lower level Module Top down Design In top down design you do not have to know all the details of your project when you start You can begin at the top with a general description of the circuit s functionality then break the design into modules with the appropriate functions This approach is called stepwise refinement you move in order from a general description to modularized functions and to the specific circuits that perform those functions In a top down design the uppermost schematic usually consists of nothing but Block symbols representing modules plus any needed power clocking or support circuitry These modules are repeatedly broken down into simpler modules or the actual circuitry until the entire design is complete Bottom up Design In bottom up design you start with the simplest modules then combine them in sc
84. urces the project notebook and the device E Project Notebook The project notebook is where you enter the title and name of the project You can also use the project notebook to keep track of external files such as document files that are related to your project E Device The device is a source that includes information about the currently selected device The supported sources are ABEL HDL module ab1 schematic module sch VHDL module vhd Verilog HDL module v test vector file abv graphic waveform stimulus wd1 VHDL test bench vhd Verilog test fixture t f Figure 1 3 shows the sources as they appear in the Project Navigator The top level ABEL HDL file RM12PS6K contains INTERFACE statements that instantiate links to the lower level ABEL HDL files PSSR8X16 and RAM12 Sources in Project B ABL EK PSSRSX16 RAM12 lt _ Project Title El desiqnBk wri EJ ispLSI6192DM 0LM208 tm 2psbk aby ABEL HDL Test Vectors AYRM12PS6K rm12ps6k abl Top level ABEL HDL File AYPSSRSX1 6 pssr8x16 abl ARAM 2 rarn12 ab Targeted Device __Lower level ABEL HDL Files Figure 1 3 Sources in a Design Project ABEL Design Manual 16 Overview of Design Design Hierarchy When designs can be broken into multiple levels this is called hierarchical designing ispDesignExpert supports full hierarchical design which permits you to create a design that is divided into multiple levels either to cl
85. verview Of ABEL HDL Compiling To see how strategies work 1 Select Source gt Strategy from the Project Navigator The Define Strategies dialog box Figure 3 10 appears w Define Strategies Strategy Associated Sources Normal Default Strategy isp 511018E 100L 44 i Cancel and ff Mew Delete Rename Associate gt gt Use As Default Help Figure 3 10 Define Strategies Dialog Box 2 Click the New button the New Strategy dialog box Figure 3 11 appears amp New Strategy New Strategy Name fast Cancel Copy From Strategy Help Figure 3 11 New Strategy Dialog Box 3 Enter a name for the strategy in the New strategy Name field 4 Click the OK button The new strategy appears in the Strategy drop down list box in the Define Strategies dialog box To assoclate a source with a new strategy 1 Select a strategy in the Strategy field of the Define Stratigies dialog box 2 Click the Associate button 3 Highlight the ABEL HDL source and ff in the Source to Associate with Strategy field 4 Click the Associate with Strategy button The and ff2 source appears in the Associated Sources list box Figure 3 12 ABEL Design Manual 33 Overview Of ABEL HDL Compiling Define Strategies Associated Sources and ff Hew Delete Rename Use As Default Source to Associate with Strategy IspL51107 656 1 001144 Associate Wath Sat and ff Figure 3 12 Ex
86. wA On Goce S With COMP Es SCALE os YellowA Off RedA On RedB OLE GreenB On goto 8 with COMP 1 State 8 if SenA amp SenB then 8 with COMP 1 1f SenA SenB then 12 with COMP 1 1f SenA SenB then 9 with COMP 1 State 9 goto 10 with COMP T State 10 goto 11 with COM 1 State 11 Goto 12 WITH COMP 1 State 17x GreenB Off YellowB On GOCO Lo Wath COMP 17 State 13 YellowB Off RedB On RedA OT is GreenA On goto O with COMP 1 end Figure 4 14 State Machine Description with Conflicting Logic Continued ABEL Design Manual 69 State Machines This design uses the complement array feature of the Signetics FPLA devices to perform an unconditional jump to state 0 0 0 0 If you use the DCSET directive the equation that specifies this transition 5327 514 S0 AR COMP KILLA NG will conflict with the dc set generated by the state diagram for S3 R S2 R S1 R and S0 R If equations are defined for state bits the DCSET directive is incompatible This conflict would result in an error and failure when the logic for this design is optimized To correct the problem you must remove the DCSET directive so the implied dc set equations are folded into the off set for the resulting logic function Another option is to rewrite the module as shown below module TRAFFIC1 title Traffic Signal Controller Clk SenA SenB pin Ala PR pin Lo Preset cont
87. ype DC on outputs for which this reduction may apply m Beware of Outputs for which the ON set might be empty As a general guideline it is important not to rely on first impression or simple intuition to understand Truth tables The way they are understood by the compiler is the only possible interpretation This means that Truth Tables should be presented in a clear and understandable format should avoid side effects and should be properly documented commented ABEL Design Manual 77 ABEL HDL and Truth Tables Basic Syntax Simple Examples In this example the lines commented as L1 and L2 are the ON set Lines L3 and L4 are ignored because Out is type default meaning 0 for unspecified combinations The resulting equation does confirm this MODULE DEMO1 TITLE Example 1 Inputs Ba By O PEN OU OUL QUE pin met yoe com s Truth Table Clay By QUE OL 01 gt te 4f HI lola SS 14 JJ B2 O Op gt O ge L3 1 0 0 gt O L4 END Resulting Reduced Equation Out A amp BE IC A amp BEC Example 2 differs from example 1 because Out is now type COM DC optimizable dont care In this case the lines commented as L1 and L2 are the ON set L3 and L4 are the OFF set and other combinations become dont care DC set meaning O or 1 to produce the best logic reduction As a result in this example the equation is VERY simple DCSET instruction would have produced the same

ABEL Design Manual

Contents

Download Pdf Manuals

Related Search

Related Contents