Home

R-IN32M3-EC Series User`s Manual

1. P12 P12 output mode P12 input mode INTPZ6 gt P13 P13 output mode P13 input mode INTPZ7 CCS WDTZ CCM WDTENZ P14 P14 output mode P14 input mode SMSCK P15 P15 output mode P15 input mode SMSI P16 P16 output mode P16 input mode SMSO P17 P17 output mode P17 input mode SMCSZ P20 P20 output mode P20 input mode RXDO CCM LINKERRZ P21 P21 output mode P21 input mode TXDO CCM ERRZ P22 P22 output mode P22 input mode INTPZ8 CATI2CCLK CCS_IOTENSU P23 P23 output mode P23 input mode INTPZ9 CATI2CDATA CCS SENYUO P24 P24 output mode P24 input mode INTPZ10 ETHSWSECOUT CCS SENYU1 P25 P25 output mode P25 input mode WDTOUTZ CCS ERRZ P26 P26 output mode P26 input mode TIN1 TOUT1 CCM RUNZ CCS RUNZ P27 P27 output mode P27 input mode TINO TOUTO Remark m 0to7 n 0to7 R18UZ0003EJ0301 Dec 25 2014 Page 188 of 203 R IN32M3 EC User s Manual 8 Port function 2 3 Pin PMCmn 0 port mode PMCmn 1 control mode nam PFCEmn 0 PFCEmn 1 e PMmn 0 PMmn 1 PFCmn 0 PFCmn 1 PFCmn 0 PFCmn 1 output port input port P30 P30 output mode P30 input mode RXD1 P31 P31 output mode P31 input mode
2. CSISCK1 UO CSI1 serial clock port P35 Hi Z CSISI l CSI1 serial data input port P36 With internal pull up CSISO1 O CSI1 serial data output port P37 resistor CSICS10 CSICS11 O CSI1 chip select 0 1 port P72 P73 Low Hi Z SCLO UO I2CO serial clock port P60 SDAO UO 12CO serial data port P61 SCL1 UO I2C1 serial clock port RPOO Hi Z SDA1 UO I2C1 serial data port RPO1 With internal pull up CRXDO CANO receive data port P53 resistor 5V Tolerant buffer CTXDO O CANO transfer data port P54 CRXD1 CAN1 receive data port P55 5V Tolerant buffer CTXD1 O CAN1 transfer data port P56 R18UZ0003EJ0301 Page 19 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 Signals by function 2 1 14 CC Link Signals Intelligent device station Pin Name UO Function Shared Active Level during reset amp Port Level after reset CCM LINKERRZ O Link error LED control port P20 Low Hi Z CCM ERRZ O Error LED control port P21 Low CCM_RUNZ O RUN LED control port P26 Low CCM_MDINO l Mode setting switch input port P62 P6 CCM MDIN3 5 CCM SNINO I Station No setting switch port P70 P7 CCM_SNIN7 7 CCM_LNKRUNZ O Link RUN LED control port P50 Low Hi Z CCM_RDLEDZ O Receive data LED control port P51 Low With internal pull up CCM_SDLEDZ O Transfer data LED control port RPOO Low resistor CCM_IRZ O Interr
3. 2 3 7 CC Link Master Signal Intelligent device station Remote device station Pin Name IO Interface Recommended connection when not in use CCM CLK80M j1 input Buffer 3 3V Connect to GND Trace Pin Name Interface Recommended connection when not in use TRACECLK Output Buffer 3 3V 69A TRACEDATA 3 0 R18UZ0003EJ0301 Page 29 of 203 Dec 25 2014 R IN32M3 EC User s Manual 3 Memory Maps FFFF FFFFH Cortex M3 System level area 12M E000 0000H kisoj DFFF FFFFH Reserved 4400 0000H 43FF FFFFH Bitband alias area 32Mbyte 4200 0000H Reserved System area 4008 0000H iCode dCode area 400F CO00H CC Link Slave 400F BOOOH area 4Kbyte 400F AFFFH GC Link Master lO 400F A000H area 4Kbyte 400F 9FFFH I GG Link Master memory 400F 8000H area 8Kbyte Reserved 400E 3000H 400E 2FFFH Ether CAT area 12Kbyte 400E 0000H 400B 0000H Reserved 400A FFFFH AHB Peripheral registers 4008 0000H area 192Kbyte 4007 FFFFH APB Peripheral registers 4000 0000H area 512Kbyte Reserved 22FF FFFFH bitband alias area 16Mbyte 2200 0000H 2008 0000H 2007 FFFFH Data RAM area 512Kbyte 2000 0000H LFFF FFFFH External memory area 256Mbyte 1000 0000H OFFF FFFFH Buffer memory area 128Mbyte 0800 0000H 040C 0000H Reserved 0408 FFERM Instruction RAM mirror 0400 0000H area 768Kbyte 03FF FFFFH Serial Flash ROM are
4. 6 15 4 Watchdog Status Process Data register WDS_DATA This register indicates watchdog status of process data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value WDS DATA 0 S lt 4006 0440H 0000H A ECAT o 6 0o a 0 0 0 0 0 0 0 0 R R PDI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ack Bit positon 0 WDSTAPD Watchdog Status of Process Data triggered by SyncManagers 0 Watchdog Process Data expired 1 Watchdog Process Data is active or disabled Reading this register clears AL Event Request 0x0220 6 R18UZ0003EJ0301 Page 82 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 15 5 This register counts Process data watchdog timeout Watchdog Counter Process Data register WDC DATA 7 6 5 4 3 2 1 0 Address WDC DATA WDCNTPD 400E 0442H ECAT RM clr RAMW clr R W clr R MW cr R W clr R W clr Bic RAM clr PDI R R R R R R R R Bit position Bit name Function WDCNTPD Watchdog Counter Process Data counting is stopped when OxFF is reached Counts if Process Data Watchdog expires Cleared if one of the Watchdog counters 0x0442 0x0443 is written 6 EtherCAT Slave Controller function Initial Value 00H 6 15 6 Watchdog Counter PDI register WDC PDI This register counts PDI watchdog timeout PDI R R 7 6 5 4 3 2 1 0 Address WDC_PDI WDCNTPDI 400E 0443H ECAT RM clr RAW clr R W clr R MW cr RMW clr R W clr Bic RAM clr R R R R R R Bit p
5. 140 Register 6 Auto Negotiation Expansion Reetater 141 Register 7 Auto Negotiation Next Page Transmit Regester 142 Register 16 Silicon Revision Register 143 Register 17 mode control status Register ernrvrnrvrnrvnnrnrernvnnnnnnvnnnvrrvvrrvevenrveraverarernevrneveernessvessvesveese 144 Register 18 Specialinoderepister s sr GG GU SIGLO UN Ou Oa 146 Repister 9 Reserved sn rsono an sn a ee EA 147 Register 20 Reserved sus saina kus i LS i sn A saba A tube ldu 147 Repister 21 Keeper ss ku sian eseo dere 148 Repist r 22 Reserved srini sis sss sss sB EB SISAS p A a aa 148 Register 23 BER counter Register 149 Register 24 FEQ monitor Register ronrronrrornrernnvrnvvrnnnrernnennnnnvennvnrvvrrverenaverarerarvrarvrnsveesvensvennvesnvesvsesnn 150 Register 25 Diagnostic control Status Register rrnrrnnrnrnrnvnvnvnnvnrnvrrvvrrnrrrnrreraverarernevreevrervessvessvesveese 151 Register 26 Diagnostic counter register siisii sssonissrissie troska siks tE o risene PSESE stess pasip p PaaS ESEE 152 Register 27 Special control Status instruction register sesrernrrnvrrnvrrvvrrnvvrnrvenaveravernevrarvrerveervessvernveree 153 Register 28 Reserved sss sio aso ss is ia kea Dee lo a iu lln 154 Register 29 Interrupt Factor Register AA 155 Register 30 Interrupt Factor Mask Regtoter A 156 Register 31 PHY special control Status register eseeeeseeeeesesereresreeeserrrsstrreresrenresrerrsserrrsresrenresre 1
6. Caution Latch input is available though value indicates SYNC output Use chip level pin multiplex function in order to switch SYNC output to LATCH input and versa vice R18UZ0003EJ0301 Page 73 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 12 5 6 EtherCAT Slave Controller function Extended PDI Configuration register EXT PDI CONFIG This register indicates extended PDI configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value Q EXT_PDI_ 0 0 0 0 0 0 0 0 0 0 0 0 0 400E 0152H H CONFIG a 00E 015 00 lt x G ECAT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDI 0 0 0 0 0 0 0 0 0 o Bit position Bit name Function 1 0 DATABUSWID Data Bus Width W This LSI indicates 0 4 Byte 0 4 Byte 1 1 Byte 2 2 Byte 3 Reserved R18UZ0003EJ0301 Page 74 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 13 Interrupts Registers 6 13 1 ECAT Event Mask register ECAT_EVENT_MASk ECAT event request ECAT interrupt is used to transmit the slave event to EtherCAT master This register is used to set mask to each event of ECAT event request register This register and ECAT event request register are ANDed and it is used as interrupt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value Evel EVENT ECATEVMASK MASK 400E 0200H 0000H ECAT RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PI RR R R R R R R R R R R R R R R 15 0 ECATEVMASK ECA
7. Watchdog Counter Process Data Watchdog Counter PDI LED signals RUN LED signal ERR LED signal STATE LED and STATE RUN LED signal LINK ACT LED signals Port Error LED PERR RUN ERR LED Override O O O O O O O O O O O O O O O O R18UZ0003EJ0301 Page 43 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function Features Functions 3 3 Support Process Data Interface PDI Digital I O SPI slave 8b 16b sync async UC On chip bus O General Purpose I O Write Protection Active register write protection 0x0000 0x0FFF O Active ESC write protection 0x0000 0x2FFF O ESC Reset ESC reset from master or PDI O R18UZ0003EJ0301 Dec 25 2014 Page 44 of 203 R IN32M3 EC User s Manual 6 5 EtherCAT register list 1 Peripheral Function Registers Register name 6 EtherCAT Slave Controller function Shortcut bits Address EtherCAT PHY offset address setting CATOFFADD 32 BASE 0620H EtherCAT operation mode setting CATEMMD 32 BASE 0624H EtherCAT reset CATRESET 32 BASE 0628H 2 ESC Information Registers Register name Shortcut bits Address Type TYPE 8 400E 0000H Revision REVISION 8 400E 0001H Build BUILD 1 400E 0002H FMMUs supported FMMU_NUM 8 400E 0004H SyncManagers supported SYNC_MANAGER 8 400E 0005H RAM Size RAM_SIZE 8 400E 0006H P
8. R18UZ0003EJ0301 Page 70 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 12 2 ESC Configuration register ESC CONFIG This register indicates ESC configuration 7 6 5 4 3 2 1 0 Address Initial Value a o o gt O 4 ESC CONFIG o ai o E E 4 gt 400E 0141H OCH o D D a lt x gt lt D I Si a N a gt Z Z Z Z O O Z DI Li Li Mi Mi Q A Li Q ECAT R R R R R R R R PDI R R R R R R R R Bit position Bit name Function Enhanced Link port 3 Port3 is not available on this LSI 0 disabled if bit 9 0 1 enabled Enhanced Link port 2 Port2 is not available on this LSI 0 disabled if bit 9 0 1 enabled Enhanced Link port 1 0 disabled if bit 9 0 1 enabled Enhanced Link port 0 0 disabled if bit 9 0 1 enabled DCLATCH Distributed Clocks Latch In Unit Fixed to 1 in this LSI 0 disabled power saving 1 enabled DCSYNC Distributed Clocks SYNC Out Unit Fixed to 1 in this LSI 0 disabled power saving 1 enabled ENLALLP Enhanced Link detection all ports 0 disabled if bits 15 12 0 1 enabled at all ports DEVEMU Device emulation control of AL status 0 AL status register has to be set by PDI 1 AL status register will be set to value written to AL control register R18UZ0003EJ0301 Page 71 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 12 3 PDI Configuration register PDI CONFIG This regi
9. sng uonaung AIEMPIBH Oct mt lnia mi LYOd LY OYNA epo 1 NdO epo d Cd weysag 140 LA NI RI JIAN EIN XO110 O3 EINGENI Y Page 4 of 203 R18UZ0003EJ0301 Dec 25 2014 1 Overview R IN32M3 EC User s Manual Pin Placement Top View 1 4 Page 5 of 203 R18UZ0003EJ0301 Dec 25 2014 R IN32M3 EC User s Manual 2 Signals by function 2 Signals by function 2 1 Signals by function 2 1 1 Ethernet Signal 1 Media Interface Pin Name UO Function Active Level during reset amp Level after reset PO RX P PHYO Receive data PO RXN PHYO Receive data S Pi RX P PHY1 Receive data S Pi RXN I PHY1 Receive data PO_TX_P O PHYO Transmit data PO_TX_N O PHYO Transmit data P1_TX_N O PHY1 Transmit data S PO SDN l PHYO 100BASE FX Signal Detect Low PHY1 100BASE FX Signal Detect PHY1 100BASE FX Signal Detect PHYO 100BASE FX Receive data PO RD N PHYO 100BASE FX Receive data Pi RD P PHY1 100BASE FX Receive data Pi RDN PHY1 100BASE FX Receive data PO TD OUT P PHYO 100BASE FX Transmit data PO TD OUT N PHYO 100BASE FX Transmit data P1 TD OUT P PHY1 100BASE FX Transmit data Pl TD OUT N PHY1 100BAS
10. R18UZ0003EJ0301 Dec 25 2014 Reserved Write 0 and ignore reading Page 145 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 11 Register 18 Special mode register a PHY Address wl Q E 12H MR18 RESERVED o Ba PHY_MODE 3 0 PHY_ADD 4 0 9 Initial Value x lt Cc E OOEOH RW R R Bit Name 15 11 RESERVED Bit Position RW RW RW NASR RW RW RW NASR NASR NASR NASR NASR NASR NASR NASR NASR RW RW RW RW Function Reserved Write 0 and ignore reading RW RW 10 FX_MODE RESERVED Enable Disable setting in 100BASE FX mode When enable the 100BASE FX mode PHY_MODE Bit 8 5 of register 18 must be 0011 or 0010 0 Invalid 10BASE T 100BASE TX mode 1 Valid Reserved Write 0 and ignore reading PHY_MODE 3 0 Set PHY operate mode PHY MODE 3 0 Speed Duplex Auto negotiation 0000 10BASE T Half duplex 0001 10BASE T Duplex PHY ADD 4 0 0010 100BASE TX FX Half duplex Invalid Enable CRS of sending and receiving 0011 100BASE TX FX Duplex Invalid Enable CRS of sending 0100 100BASE T Half duplex Valid Enable CRS of sending and receiving 0101 100BASE T Repeater mode Half duplex Valid Enable CRS of receiving 0110 PowerDown Mode For testing Both sides Full duplex Force by parallel detection Enable quick auto negot
11. Bit position Function 7to0 PFCmn Specify whether to use alternate functions 1 and 3 or alternate functions 2 and 4 Note 2 Note 3 RPFCmn 0 Alternate function 1 Alternate function 3 1 Alternate function 2 Alternate function Aide Figure 8 11 Port function control registers in 8 bit notation Note1 The initial value depends on the pin status For details see 2 2 Port status Note2 To use alternate function 1 or 2 the bit corresponding to the function in the PFCE RPFCE register must be set to 0 Note3 To use alternate function 3 or 4 the bit corresponding to the function in the PFCE RPFCE register must be set to 1 Remark 0to3 m 0to7 n 0to7 R18UZ0003EJ0301 Page 179 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 14 11 Address PFC PFC PFC PFC PFC PFC PFC PFC PFC PFC PFCOH DODD OKRA geg RW RW RW 1 RW RW RW RW RW RW RW Initial value 0000H 14 11 0 Address PEC2H PFC PFC PFC PFC PFC PFC PFC PFC PFC PFC PFC PFC 36 35 34 33 32 27 26 25 24 23 22 400A 30327 RW RW RW RW RW RW RW RW RW RW RW RW Initial value o000OH Address Grau PFC PFC PFC PFC PFC PFC PFC PFC PFC PFC PFC PFC PFC 56 54 53 52 47 46 45 44 43 42 41 40 400A 3034H RW RW RW RW RW RW RW RW RW RW RW RW RW Initial value o000OH 14 ti 0 Address cen PFC PFC PFC PFC PFC PFC 76 74 73 72 70 0043035 RW RW RW R
12. Initial value Undefined Address PIN2H 400A 3052H Initial value Undefined Address PIN4H 400A 3054H Initial value Undefined Address PIN6H 400A 3056H Initial value Undefined Address RPINOH 400A 3450H Initial value Undefined 0 Address 14 RPIN RPIN RPIN RPIN RPIN RPIN RPIN RPIN RPIN RPIN RPIN RPIN RPIN RPIN RPIN BE 400A 3452H 37 36 35 34 33 32 31 30 27 26 25 24 23 22 21 Initial value Undefined 15to0 PINmn Use to read the input level of the port pin RPINIn Figure 8 18 Port pin input registers in 16 bit notation RPIN2H Remark l 0t0o3 m 0t07 n 0to7 R18UZ0003EJ0301 Page 186 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 Address 400A 3050H Initial value PINOW wIst oia rl o n l mn Undefined NIN N IN N N z z z zZ Z zZ ZI Z ZIg z z Z zZ Z zZ zZ Z Z Z IZ IZ IZ IZIZIZIZIZIZIZZE a a a a o a a a a R W R RRRRRRRR 24 23 22 21 20 19 18 17 16 15 14 13 Address 400A 3054H Initial value PIN4W olnlelv s nmia r eo n o mn Undefined NI IQOIOIOIOIOIOIO O WM LO LO z zZ zZ Z Z Zg g z z Z Z zZ ZI Z Z ZIZ Z Z1 ZI ZIZIZIZIZIZIZIZIZIZIZIE a a a a o a a o a a a a R W R RRRRRRRRRRABR 24 23 21 20 18 17 15 14 13 12 11 10 9876543210 Address 400A 3450H Initial value RPINOW SIK o x als nlolw ee 22212222 2 2 2 2 2 2 2 2 2 z 2 22 22
13. TMODEO TMODE2 I O Interface Input Buffer 3 3V Schmitt in 50kQ Pull down Required Connection when not in use Connect to GND TMS I O I O Buffer 3 3V 6mA 50kQ Pull up Open TDI l Input Buffer 3 3V 50kQ Pull up Open TDO O 3 state Output Buffer 3 3V 6mA Open TRSTZ l Input Buffer 3 3V Schmitt in Open 50kQ Pull up TCK Input Buffer 3 3V Open 50kQ Pull down TMC1 l TMC1 Input Buffer 3 3V for TMC Terminal Connect to GND TMC2 l TMC2 Input Buffer 3 3V for TMC Terminal Connect to GND ATP l Input Buffer 3 3V Open TESTI l Input Buffer 3 3V Connect to GND TEST2 l Input Buffer 3 3V TEST3 Input Buffer 3 3V TESTDOUT5 O Output Buffer 3 3V Open R18UZ0003EJ0301 Page 27 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 3 5 Port Signals Pin Name P00 P07 I O I O Interface UO Buffer 3 3V 6mA 2 Signals by function 1 2 Recommended connection when not in use Connect to GND P10 P11 P17 P20 P27 I O I O I O Programmable I O Buffer 3 3V 6mA Resistor select function 50kQ Pull up or 50kQ Pull down or less Programmable I O Buffer 3 3V 6mA Resistor select function 50kQ Pull up or 50kQ Pull down or less I O Buffer 3 3V 6mA Open Connect to GND P30 P36 I O Programmable I O Buffer 3 3V 6mA Resistor select function 50kQ Pull up or 50kQ Pull down or less P37 I O Pr
14. 39 DC Time loop control assigned to PDI Link detection and configuration by MI 40 MI control by PDI possible 41 Automatic TX shift 42 EEPROM emulation by Controller 49 43 Reserved 50 ERR LED RUN ERR LED Override 1 0 0 1 others Reserved R18UZ0003EJ0301 Dec 25 2014 Reserved Page 124 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 21 4 Process Data RAM DATA RAM This RAM is used in process data and mailbox The area is 8Kbyte from 400E 1000H to 400E 2FFFH Process Data Process Data RAM is only accessible if EEPROM was correctly loaded register 0x0110 0 1 R18UZ0003EJ0301 Page 125 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 7 1 Etherne PHY Function Features 7 Etherne PHY Function R IN32M3 EC supports 10BASE T 100BASE TX FX and integrated IEEE802 3 dual port Ethernet physical layer PHY It is possible to connect twisted pair UTP cable by external pulse transformer or connect optical fiber by optical transceiver And it supports Daisy chain structure and ring structure used by industry network 10BASE T 100BASE TX and 100BASE FX of based upon IEEE802 3 2 port Auto negotiation Full duplex transmission and a half duplex transmission Automatic MDI MDI X Serial management interface MDC MDIO Low latency function Quick auto negotiation Cable diagnosis function Fast link loss Det
15. 400E 0501H EEPROM Control Status EEPROM Address EEP_CONT_STAT EEP_ADR 400E 0502H 400E 0504H EEPROM Data R18UZ0003EJ0301 Dec 25 2014 EEP_DATA 400E 0508H Page 46 of 203 R IN32M3 EC User s Manual 12 MII Management Interface Registers n 0 1 6 EtherCAT Slave Controller function Register name Shortcut bits Address MII Management Control Status MI CONT STAT 16 400E 0510H PHY Address PHY ADR 8 400E 0512H PHY Register Address PHY REG ADR 8 400E 0513H PHY Data PHY DATA 16 400E 0514H MII Management ECAT Access State MII ECAT ACS STAT 8 400E 0516H MII Management PDI Access State MII PDI ACS STAT 8 400E 0517H PHY Port Status n PHY STATUSn 8 400E 0518H 0001H n 13 FMMU Registers m 0 7 Register name Shortcut bits Address FMMU Logical Start Address m FMMUm L START ADR 32 400E 0600H 0010H m FMMU Length m FMMUm LEN 16 400E 0604H 0010H m FMMU Logical Start bit m FMMUm L_START_BIT 8 400E 0606H 0010H m FMMU Logical Stop bit m FMMUm L STOP BIT 8 400E 0607H 0010H m FMMU Physical Start Address m FMMUm P START ADR 16 400E 0608H 0010H m FMMU Physical Start bit m FMMUm P START BIT 8 400E 060AH 0010H m FMMU Type m FMMUm TYPE 8 400E 060BH 0010H m FMMU Activate m FMMUm ACT 8 400E 060CH 0010H m 14 SyncManager Registers m 0 7 Register name Shortcut Address SyncManager Physical Start Add
16. CCM SNIN5 P76 P76 output mode P76 input mode INTPZ14 P1SPEED100LEDZ CCS STATION NO 6 CCM_SNIN6 P77 P77 output mode P77 input mode INTPZ15 P1SPEEDIOLEDZ CCS STATION NO 7 CCM SNIN7 Remark m 0io07 n 0to 7 R18UZ0003EJ0301 Dec 25 2014 Page 190 of 203 R IN32M3 EC User s Manual 8 Port function 2 Real time control ports RP00 to RP37 Pin PMCmn 0 port mode PMCmn 1 control mode name RPFCEmn 0 RPFCEmn 1 PMmn 0 PMmn 1 RPFCmn 0 RPFCmn 1 RPFCmn 0 RPFCmn 1 output port input port HO RP00 output mode RPOO input mode INTPZ16 SCL1 CCM SDLEDZ CCS_SDLEDZ RPO1 RPO1 output mode RPO1 input mode INTPZ17 SDA1 CCM SMSTZ RP02 RP02 output mode RP02 input mode INTPZ18 POACTLEDZ CCS BS1 RP03 RPO3 output mode RPO3 input mode INTPZ19 CCS BS2 RP04 RP04 output mode RP04 input mode INTPZ20 P1ACTLEDZ CCS BS4 RP05 RP05 output mode RPO05 input mode INTPZ21 CCS BS8 RP06 RP06 output mode RPO6 input mode WRZ2 HWRZ2 RP07 RP07 output mode RPO7 input mode WRZ3 HWRZ3 RP10 RP10 output mode RP10 input mode D24 HD24 RP11 RP11 output mode RP11 input mode D25 HD25 RP12 RP12 output mode RP12 input mode D26 HD26 RP13 RP13 output mode RP13 input mode D27 HD27 i
17. RP14 RP14 output mode RP14 input mode D28 HD28 RP15 RP15 output mode RP15 input mode D29 HD29 RP16 RP16 output mode RP16 input mode D30 HD30 RP17 RP17 output mode RP17 input mode D31 HD31 RP20 RP20 output mode RP20 input mode BCYSTZ HBCYSTZ RP21 RP21 output mode RP21 input mode A21 RP22 RP22 output mode RP22 input mode A22 RP23 RP23 output mode RP23 input mode A23 RP24 RP24 output mode RP24 input mode A24 INTPZ25 RP25 RP25 output mode RP25 input mode A25 INTPZ26 RP26 RP26 output mode RP26 input mode A26 INTPZ27 RP27 RP27 output mode RP27 input mode A27 INTPZ28 RP30 RP30 output mode RP30 input mode D16 HD16 RP31 RP31 output mode RP31 input mode D17 HD17 RP32 RP32 output mode RP32 input mode D18 HD18 RP33 RP33 output mode RP33 input mode D19 HD19 RP34 RP34 output mode RP34 input mode D20 HD20 RP35 RP35 output mode RP35 input mode D21 HD21 RP36 RP36 output mode RP36 input mode D22 HD22 RP37 RP37 output mode RP37 input mode D23 HD23 Remark m 0to3 n 0to7 R18UZ0003EJ0301 Page 191 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 8 5 Buffer function change registers DRCTLP For some port pins the driving capability and whether to connect a pull up or pull down resistor can be specified individually
18. SYSTIME Function Access from ECAT Read Local copy of the System Time when the frame passed the reference clock i e including System Time Delay Time latched at beginning of the frame Ethernet SOF delimiter Write Written value will be compared with the local copy of the System time The result is an input to the time control loop NOTE written value will be compared at the end of the frame with the latched SOF local copy of the System time if at least the first byte 0x0910 was written Access from PDI Read Local copy of the System Time Time latched when reading first byte 0x0910 R18UZ0003EJ0301 Dec 25 2014 Page 103 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 2 2 Receive Time ECAT Processing Unit register DC RCV TIME UNIT This register indicates received time of the frame latched at EtherCAT Processing Unit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address 400E 0918H DC RCV Initial Value RCVTIMEEPU TIME UNIT Undefined ECAT R RR R RR RR RR RR RR RR RR RR RR RR RR RR RR R R PDI R RR RR RR RR RR RR RR RR RRR RR RR RR RRR R RR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 RCVTIMEEPU Bit position Function 63 0 RCVTIMEEPU Local time of the beginning of a frame start first bit of preamble received at the ECAT Processing Unit containing a write access to Register
19. TXD1 P32 P32 output mode P32 input mode DMAREQZ1 CCS MON1 P33 P33 output mode P33 input mode DMAACKZ1 CCS MON2 P34 P34 output mode P34 input mode DMATCZ1 CCS MON3 P35 P35 output mode P35 input mode CSISCK1 INTPZ22 CCM IRLZ P36 P36 output mode P36 input mode CSISI1 INTPZ23 CCS FUSEZ P37 P37 output mode P37 input mode CSISO1 INTPZ24 CCM MSTZ P40 P40 output mode P40 input mode A1 HA1 P41 P41 output mode P41 input mode WAITZ HWAITZ P42 P42 output mode P42 input mode SLEEPING HERROUTZ CCM_SDGCZ P43 P43 output mode P43 input mode INTPZ11 HBUSCLK P44 P44 output mode P44 input mode CSZ1 HPGCSZ P45 P45 output mode P45 input mode CSISCKO WAITZ1 P46 P46 output mode P46 input mode CSISIO WAITZ2 P47 P47 output mode P47 input mode CSISOO WAITZ3 P50 P50 output mode P50 input mode CSZ3 CCM LNKRUNZ CCS_LNKRUNZ P51 P51 output mode P51 input mode CSZ2 CCM_RDLEDZ CCS RDLEDZ P52 P52 output mode P52 input mode TIN3 TOUT3 CCS SDGATEON P53 P53 output mode P53 input mode CRXDO CCS RD CCM RD P54 P54 output mode P54 input mode CTXDO CCS_SD CCM_SD P55 P55 output mode P55 input mode CRXD1 P56 P56 output mode P56 input mode CTXD1 CATRESTOUT P57 P57 output mode P57 input mode T
20. With internal pull up P32 DMAREQZ1 CCS_MON1 resistor P33 DMAACKZ1 CCS_MON2 P34 DMATCZ1 CCS MON3 P35 CSISCKI INTPZ22 CCM IRLZ P36 CSISI1 INTPZ23 CCS FUSEZ P37 CSISO1 INTPZ24 CCM MSTZ P4 P40 Al HA1 Hi Z P41 WAITZ HWAITZ With internal pull up P42 SLEEPING HERROUTZ CCM_SDGCZ resistor P43 INTPZ11 HBUSCLK P44 CSZ1 HPGCSZ P45 CSISCKO WAITZ1 P46 CSISIO WAITZ2 P47 CSISOO WAITZ3 P5 P50 CSZ3 CCM_LNKRUNZ CCS_LNKRUNZ P51 CSZ2 CCM_RDLEDZ CCS_RDLEDZ P52 TIN3 TOUT3 CCS_SDGATEON Hi Z With internal pull down resistor P53 CRXDO CCS_RD CCM_RD Hi Z P54 CTXDO CCS_SD CCM_SD With internal pull up P55 CRXD1 resistor P56 CTXD1 CATRESTOUT P57 TIN2 TOUT2 R18UZ0003EJ0301 Dec 25 2014 Page 13 of 203 R IN32M3 EC User s Manual Port TE Mode 1 Mode 2 Mode 3 Mode 4 P6 P60 SCLO P61 SDAO P62 RTDMAREQZ CCM MDINO P63 RTDMAACKZ CCM MDIN1 P64 RTDMATCZ CCM MDIN2 P65 DMAREQZO CCM MDIN3 P66 DMAACKZO P67 DMATCZO P7 P70 CSICS00 PODUPLEXLEDZ CCS STATION NO 0 CCM SNINO P71 CSICS01 CCS STATION NO 1 CCM SNIN1 P72 CSICS10 POSPEED100LEDZ CCS STATION NO 2 CCM SNIN2 P73 CSICS11 POSPEED10LED CCS STATION NO 3 CCM SNIN3 P74 INTPZ12 P1DUPLEXLEDZ CCS STATION NO 4 CCM SNIN4 P75 INTPZ13 CCS STATION NO 5 CCM SNIN5
21. the external interrupt input is also shared Remark n 0to7 m 0 3 R18UZ0003EJ0301 Dec 25 2014 Page 162 of 203 R IN32M3 EC User s Manual 8 Port function PMC initial value Write PMC Read PMC Write PFCE Read PFCE PFCE initial value PFC initial value Write PFC Read PFC Read PIN Write Port Read Port Write PM Read PM Alternate function 0 nactive Level Alternate function 1 nactive Level Alternate function 2 nactive Level Alternate function 3 nactive Level Alternate function 0 input output attribute Alternate function 1 input output attribute 9 Alternate function 2 input output attribute LU Alternate function 3 input output attribute Output alternate function 0 Output alternate function 1 Output alternate function 2 Output alternate function 3 Figure 8 1 Basic port circuit configuration R18UZ0003EJ0301 Dec 25 2014 Page 163 of 203 R IN32M3 EC User s Manual 8 Port function 8 3 Registers 1 6 Register name Symbol Address Port register 0 8 bits POB 400A 3000H Port register 1 8 bits P1B 400A 3001H Port register 2 8 bits P2B 400A 3
22. 1000H LOOPBACK Enable Disable the settings of internal loop back mode 0 Disable 1 Enable SPEED SELCTION Set the Link speed 0 10Mb s 1 100Mb s AUTO NEGOTIATION ENABLE Enable Disable the settings of auto negotiation 0 Disable 1 Enable POWERDOWN Set the power down mode 0 Normal operation 1 Power down mode ISOLATE Set isolation 0 Normal operation 1 Electrically disconnect from MII RESTART_ AUTO NEGOTIATION Restart the auto negotiation process 0 Normal operation 1 Restart the auto negotiation process DUPLEX_MODE Set the duplex mode This setting is invalid when bit 12 is 1 0 Half Duplex 1 Full Duplex COLLISION TEST Enable Disable the settings of collision signal 0 Disable 1 Enable RESERVED R18UZ0003EJ0301 Dec 25 2014 Reserved Write 0 and ignore reading Page 135 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 2 Register 1 Status Register Register shows the status of Ethernet PHY 15 MR1 100BASE T4 Bit Position 14 13 12 11 gt x lt LLI a a LL HALF DUPLEX 100BASE TX 100BASE TX 10M HALF Bit Name 100BASE T4 100BASE TX FULL DUPLEX DUPLEX 10 9 8 7 6 5 4 3 2 1 0 o o PHY Address E E lt lt 5 3 3 O l ni 2 I sa BEE DI RESERVED ga o gt k a Sa Initial Value 42 5 43 5 amp HX
23. Bit position Bit name Function 31 0 ADDRESS EEPROM Address 0 First word 16 bit 1 Second word Actually used EEPROM Address bits 9 0 EEPROM size up to 16 kBit 17 0 EEPROM size 32 kBit 4 Mbit Note Write access depends upon the assignment of the EEPROM interface ECAT PDI Write access is generally blocked if EEPROM interface is busy 0x0502 15 1 R18UZ0003EJ0301 Page 86 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 16 5 EEPROM Data register EEP DATA This register is used to set write data to EEPROM or indicates read data from EEPROM It is possible to write each I word and read each 2 words 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 43 2 1 0 Address 400E 0508H Initial Value EEP DATA HIDATA LODATA 0 ECAT R R H RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW PDI R R R R R R R R R R R R R R RR RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW Bit position Bit name Function EEPROM Read data data read from EEPROM higher bytes EEPROM Write data data to be written to EEPROM or EEPROM Read data data read from EEPROM lower bytes Note Write access depends upon the assignment of the EEPROM interface ECAT PDI Write access is generally blocked if EEPROM interface is busy 0x0502 15 1 R18UZ0003EJ0301 Page 87 of 20
24. FCS Figure 7 1 Preamble of Ethernet frames R18UZ0003EJ0301 Dec 25 2014 lt MII Data lt LINE Data lt Ethernet Frame Page 126 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 22 Quick auto negotiation function R IN32M3 EC supports quick auto negotiation function which means completing auto negotiation in less time than the specific time of IEEE802 3 and link up If the PHY is corresponding to the quick auto negotiation Auto negotiation can be complete in a shorter time than normal by reducing the timer time of the three elements described below among the auto negotiation state machine Break Link Timer Break Link Timer is defined as the time from PHY links down to auto negotiation restarts and it is usually 1250ms Break Link Timer OUT Link Down Auto Negotiation Restart DD Fast Link Pulse Eg Idle Pattern or Link Pulse Autonego Wait Timer Autonego Wait Timer is defined as the waiting time from auto negotiation stops to parallel detection starts and it is usually 850ms Autoneg Wait Timer at AY OUT Z Z IN Auto Negotiation Parallel Detection Stop Start DDD Fast Link Pulse E l Idle Pattern or Link Pulse R18UZ0003EJ0301 Page 127 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 Etherne PHY Function amp Link Fail Inhibit Timer Link Fail Inhibit Timer is defined as the waiting time from signal loss or becomes abnormal to link down and it is usu
25. Process Data Interfaces Digital I O No Yes SPI Slave No Yes Host MPU Interface On chip bus 8bit 16bit async sync SRAM Host Interface Caution Register area QE 0000H 0E OF7FH can t be accessed from the external MPU I F 6 2 Peripheral circuit of EtherCAT Peripheral circuit Giga bit Ethernet Ether MAC Switch 5 Media I F WW e VO 10 100M Part O 8 E Butter PHY Ether CAT Slave Controller CSEL ETHDRCTRL 5 Media I F 3 VO 10 100M Port 1 CATODDADD p 8 Buffer lt gt PHY CATEMMD gt 12C Interface CATI2CCLK CATI2CDATA SYNC LATCH PDI Interface LED IRQ RESET l Internal Bus d Figure 6 1 Peripheral circuit of EtherCAT R18UZ0003EJ0301 Page 40 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 3 Table 6 2 Interrupt list of EtherCAT Slave Controller 6 EtherCAT Slave Controller function Interrupt list and I O signals Exce Connection ption Name Cause group NVIC HW DMAC Eng Timer No RTOS Port 43 INTCATSYNCO EtherCAT Synco interrupt O O 44 INTCATSYNC1 EtherCAT Synci interrupt O O O O 45 INTCAT EtherCAT interrupt O O O O O 46 INTCATSOF EtherCAT SOF interrupt O O O O O 47 INTCATEOF EtherCAT EOF interrupt O O O
26. Reserved Write 0 and ignore reading 9 FARLOOPBACK Enable disable the settings of remote loopback mode All the packets are send back at the same time by setting Only correspond to 100BASE TX FX mode 0 Disabled 1 Enabled 8 FASTEST Enable disable the settings of test mode of auto negotiation Only used for simulation The time of software reset is also decreased 0 Disabled 1 Enabled 7 AUTOMDIX EN Enable disable the settings of auto MDIX function 0 Disabled Set bit 6 of register 17 manually 1 Enabled 6 MDI MODE Set the MDI MDI X mode manually when bit 7 of register 17 is 0 If bit 7 of register 17 is 1 it means the status of mode and write to the register is disabled at this time 0 MDI mode 1 MDI X mode 5 RESERVED Reserved Write 0 and ignore reading R18UZ0003EJ0301 Page 144 of 203 Dec 25 2014 R IN32M3 EC User s Manual Bit Position Bit Name DCD PAT GEN RESERVED Function Enable disable the settings of pattern generation for DCD measurement in the test mode 0 Disabled 1 Enabled Reserved Write 0 and ignore reading 7 Etherne PHY Function 2 2 FORCE GOOD LINK STATUS Make the link state in force Only use for test 0 Normal operation 1 Link status of 100BASE X ENERGYON Shows the energy detection state of line 0 Energy from the line within 256ms is not detected 1 Detection of energy from the line RESERVED
27. 2 s iccnie sect ua I Ei e pN eee eens 60 6 10 1 ESC Reset ECAT register ESC RESET ECAT rmnernrernrvrnvrrnrnrnrnvnvrnnrnvervnevvnnnvernvervvrrnrrevrveraverasvreevresnen 60 Contents 2 6 10 2 ESC Reset PDI register ESC RESE T PDD sismo smon tls aksenten 61 6 10 3 ESC DL Control register ESC DL CONTROL sisser seriite itoe iisisseso ra raer Piko ete be SEEE Ess E Pereis riii 62 6 10 4 Physical Read Write Offset register PHYSICAL RW OST 63 6 10 5 ESC DL Status register ESC DL STATU 64 6 11 Application Layer Reser si kr se fooro dpe l pros elegio loos atenerne EE deg 66 6 11 1 AL Control resister AL CONTROL sss sss sme SIVO SA 66 6 11 2 AL Status register AL STATUS sss ss SASANIDA EAS 67 6 11 3 AL Status Code register AL STATUS COD 67 6 11 4 RUN LED Override register RUN LED OVERRIDE rsvorerervrervrnrvrnvrnvvrnrnrernrevvnnvvnrvvervvrsvrrevssersereee 68 6 11 5 ERR LED Override register ERR LED ONVRRRIUDE AAA 69 6 12 PDI DEE 70 6 12 1 PDI Control register PDI CONTROL eerronenonnorrrvennnnerrrvennnnerrrvenneneranennnnesranennenesrsvennnnenrssennnnesrssennener 70 6 12 2 ESC Configuration register ESC CONPIO roepsteen staven p e e ipes eE pE ESen EEN iea 71 6 12 3 PDI Configuration register PDI CONPIO 72 6 12 4 SYNC LATCH PDI Configuration register SYNC LATCH CONFIG rervrrvvvrvvrrvvrrvvrrvrrrvererrversvvree 73 6 12 5 Extended PDI Configuration register EXT PDI CONFIG rerennnnenrnvennnnsnrnvenn
28. 28 3 23 s 8 KS 7809H az ke EE I 5 LIO R R R R R R R LH R RLL R LH R Function Shows enable disable on communication of 100BASE T4 0 Disable 1 Enable Shows enable disable on full duplex communication of 100BASE TX 0 Disable 1 Enable 100BASE TX HALF DUPLEX 10M FULL DUPLEX 10M HALF DUPLEX Shows enable disable on half duplex communication of 100BASE TX 0 Disable 1 Enable Shows enable disable on 10Mb s full duplex communication 0 Disable 1 Enable Shows enable disable on 10Mb s half duplex communication 0 Disable 1 Enable RESERVED AUTO NEGOTIATION COMPLETE Reserved Write 0 and ignore reading Notice of auto negotiation completion 0 Incompletion 1 Completion REMOTE FAULT Shows the detection result of the failure of remote side 0 Failure undetected 1 Failure detected AUTO NEGOTIATION ABILIT Enable Disable the settings of auto negotiation 0 Disable 1 Enable LINK STATUS Shows the status of link 0 link down 1 link up JABBER DETECT Shows the detection result of jabber state 0 Jabber undetected 1 Jabber detected EXTENDED CAPABILITY R18UZ0003EJ0301 Dec 25 2014 Shows whether the extended register is used 0 Use only basic register set 1 Use extended register set Page 136 of 203 R IN32M3 EC User s Manual 7 4 3 15 13 12 10 9 8 7 6 5 4 3 2 1 0 PHY Addre
29. 400E 0140H 400E 0141H PDI Configuration SYNC LATCH PDI Configuration PDI_CONFIG SYNC_LATCH_CONFIG 400E 0150H 400E 0151H Extended PDI Configuration 8 Interrupts Registers Register name EXT_PDI_CONFIG Shortcut 400E 0152H Address ECAT Event Mask ECAT_EVENT_MASK 400E 0200H AL Event Mask AL_EVENT_MASK 400E 0204H ECAT Event Request ECAT_EVENT_REQ 400E 0210H AL Event Request 9 Error Counters Registers n 0 1 AL_EVENT_REQ 400E 0220H Register name Shortcut bits Address Rx Error Counter n RX_ERR_COUNTn 16 400E 0300H 0002H n Forwarded Rx Error counter n FWD_RX_ERR_COUNTn 8 400E 0308H 0001H n ECAT Processing Unit Error Counter ECAT_PROC_ERR_COUNT 8 400E 030CH PDI Error Counter PDI_ERR_COUNT 8 400E 030DH Lost Link Counter n LOST LINK COUNTn 8 400E 0310H 0001H n 10 Watchdog Registers Register name Shortcut Address Watchdog Divider Watchdog Time PDI WD DIVIDE WDT PO 400E 0400H 400E 0410H Watchdog Time Process Data WDT DATA 400E 0420H Watchdog Status Process Data WDS DATA 400E 0440H Watchdog Counter Process Data WDC DATA 400E 0442H Watchdog Counter PDI 11 SIl EEPROM Interface Registers Register name WDC_PDI Shortcut 400E 0443H Address EEPROM Configuration EEP_CONF 400E 0500H EEPROM PDI Access State EEP_STATE
30. DRCTLP5H SR 196 8 5 5 Real time port 0 buffer function change registers DRCTLRPOL DRCTLRPOH 197 8 5 6 Real time port I buffer function change registers DRCTLRPIL DRCTLRP1H 198 8 5 7 Real time port 2 buffer function change registers DRCTLRP2L DRCTLRP2H 199 8 5 8 Real time port 3 buffer function change registers DRCTLRP3L DRCTLRP3H 200 8 6 Operation of port IUNCHONS sse sss sos ets e oTe enas SEENEN sblencys couse en EA Sss does ebe 201 8 6 1 Readini and writing via VO portis sss th mikon Le ep mpreno 201 8 6 2 Alternate function pin output status in control mode 201 8 7 Trigger synchronous ports RPOO to RI 202 9 Electrical Gpechicaitons renn nrnnnnnnnnrn renner ann nnnnnnnenenr rea nnnsannnenenresnnrnennrnsennennnnsene 203 Contents 6 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 6 1 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 8 6 Figure 8 7 Figure 8 8 Figure 8 9 Figure 8 10 Figure 8 11 Figure 8 12 Figure 8 13 Figure 8 14 Figure 8 15 Figure 8 16 Figure 8 17 Figure 8 18 Figure 8 19 Contents of figures Memory map Va ND E rr oooo TII TTT TTT TEF 30 Memory map APB Peripheral registers area ssrrnvrrnorrnrrvnrrnvrrnrvenrvernrrnvvrnenrnrnnernenvvnsnvernersvsesnseensee 31 Memory
31. Have additional pages ACKNOWLEDGE Result of link signal from the link partner 0 Failure Success 1 Success REMOTE_FAULT Fault condition of the link partner 0 Not fault 1 Fault RESERVED Reserved Write 0 and ignore reading PAUSE_OPERATION Pause auction of MAC of remote device supported or not 0 Not supported 1 Supported 100BASE T4 100BASE T4 supported or not Fixed to 0 in this LSI 0 Not supported 1 Supported 100BASE TX 100BASE TX Full Duplex supported or not FULL DUPLEX 0 Not supported 1 Supported 100BASE TX 100BASE TX supported or not 0 Not supported 1 Supported 10BASE T 10BASE T Full Duplex supported or not FULL DUPLEX 0 Not supported 1 Supported 10BASE T 10BASE T supported or not 0 Not supported 1 Supported SELECTOR FIELD 00001 IEEE std 802 3 R18UZ0003EJ0301 Page 139 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 6 Register 5 Auto Negotiation Link Partner Ability Next Page Register Register 5 shows the Next Page of the information received from the partner when using auto negotiation LU MR5 O Next Page e x lt DI E R Bit Position LU Lu Lu EA kens Lu o lz O lt O Z Kai Z S 1S Ka lt R R R Bit Name NEXT PAGE TOGGLE PHY Address 05H MESSAGE UNFORMATTED CODE FIELD Initial value 0000H Function Whether there are add
32. LENESAS GE d D o Q D R IN32M3 Series User s Manual R IN32M3 EC All information of mention is things at the time of this document publication and Renesas Electronics may change the product or specifications that are listed in this document without a notice Please confirm the latest information such as shown by website of Renesas Document number R18UZ0003EJ0301 Issue date Dec 25 2014 Renesas Electronics A RM www renesas com Notice Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas
33. R R R R R R R R R R R R R R R R Bit Position Bit Name Function Reserved Write 0 and ignore reading 7 4 15 Register 22 Reserved 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 PHY Address 16H MR22 RESERVED Initial Value 0000H Loo Eh R R R R R R R R R R R R R R R R RESERVED Reserved Write 0 and ignore reading R18UZ0003EJ0301 Page 148 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 4 16 Set BER counter function mode of Ethernet PHY and show the results Register 23 BER counter Register BER LNK OK startup 1 The state of the link is good lt O 5 MR23 BER_CNT_TRIG BER_WINDOW BER_COUNT Si x e Li uz m mi R RW RW RW RW RW RW RW RW R R R R R Bit Position Bit Name Function Shows the quality status of the link It turns to 1 if the value of BER counter is below the threshold after startup It is used to detect the reliable links after 0 Not linked or the state of the link is not good 7 Etherne PHY Function PHY Address 17H Initial Value 5080H BER CNT LNK EN threshold 1 Bring down the link Operation when the count value of BER and FEQ monitor exceeds the 0 Only BER LNK OK becomes 0 without bringing down the link BER CNT TRIG value of BER counter 1 or more More than 1 2 or more More than 2 3 or more More than 4 5 or more More than 8 9 or more More than 16 17 or more More than
34. a a oe a oe a oe a oe a oe a oe a oe a oe o oe o o o o o o o a a a a RW R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 27 26 25 24 23 22 21 20 19 18 17 16 Address 400A 3410H ee Initial value 0 GI GID SINIS AE FFFF FFFFH gt 32 3 gt 3 gt gt gt gt gt e a o o lalala o ala ala ec c e ee loci lolol lo lo R W R W RAV RAV RAV RAV RAV R W RAV RAV R W RAV R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W RW 31 to 0 PMmn RPMIn Set the port to input or output mode 0 Output mode output buffer is on 1 Input mode output buffer is off initial value Figure 8 7 Port mode registers in 32 bit notation Remark I Oto3 m Oto7 n Oto7 R18UZ0003EJ0301 Page 175 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 8 3 3 Port mode control register PMC RPMC These registers are used to select whether to use a port as a port or for its alternate function Address Initial 7 6 5 4 3 2 1 0 value PMCOB PMC07 PMC06 PMC05 PMC04 PMC03 PMC02 PMCO1 PMC00 400A 3020H 00H PMC1B PMC17 PMC16 PMC15 PMC14 PMC13 PMC12 PMC11 PMC10 400A 3021H o0H PMC2B PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 400A 3022H OOH PMC3B PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 400A 3023H O0H PMC4B PMC47 PMC46 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 400A 3024H o0H PMC5B PMC57 PMC56 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 400A 3025H OOH PMC6B PMC67 PMC
35. s Manual This manual 2 Notation of Numbers and Symbols Weight in data notation Left is high order column right is low order column Active low notation xxxZ_ capital letter Z after pin name or signal name or xxx_N capital letter N after pin name or signal name or xxnx pin name or signal name contains small letter n Note explanation of Note in the text Caution Item deserving extra attention Remark Supplementary explanation to the text Numeric notation Binary XXXX XxxxB or n bxxxx n bits Decimal xxxx Hexadecimal xxxxH or n hxxxx n bits Prefixes representing powers of 2 address space memory capacity K kilo 2 1024 M mega 2 1024 G giga 2 10247 Data Type Word 32 bits Halfword gt 16 bits Byte 8 bits ds 2 Contents SNE EE ns nd e a nl A 1 1 1 veel ee EE 1 1 2 OVErvIEW Like TI kaker TTT TTT TE TTT TT TTETTTTTTTTT E TEL 2 1 3 INTERNAL BLOCK DIAGRAM 5 es subsses estio e ssonsiob Euro p SEE oer vastas sobran dEr 4 1 4 Pin Placement Top VIEW snuro NA SANNIO a oj 5 G lle eed errr eer p eer mn mm IPO PE 6 2 1 Signals by fUNCHON siisii erener in ra esp Eir TTT TT TTETTTTTTTTTTTTTTTT TTT TTT TTT 6 2 1 1 Ethernet Signali sio seer eee es nn l le E A 6 2 1 2 EtherCAT Slave Controller Signal isinne eoori torent ennen reni er oei rae ene En Eesi en ESKER 8 2 1 3 External Memory Interface Sienals iiinis sisarien roeren ieres i eera ier ener ei
36. 0 P67 Low DMAREQZ 1 l DMA transfer request port 1 P32 Low Hi Z DMAACKZI O DMA acknowledge output port 1 P33 Low With internal pull up DMATCZ1 O DMA Terminal count output port 1 P34 Low resistor Caution Each DMA interface is assigned to a specific DMA channel DMA channel 0 interface 0 DMAREQZ0 DMAACKZO DMATCZO DMA channel 1 interface 1 DMAREQZ1 DMAACKZ1 DMATCZ1 DMA channels 2 3 no external interface R18UZ0003EJ0301 Page 16 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 Signals by function 2 1 8 External Interrupt Input Signals Pin Name I O Function Shared Port Active Level during reset amp Level after reset NMIZ l Non maskable external interrupt input port i Low Hi Z With internal pull up resistor INTPZO INTPZ5 l External interrupt input port P00 P05 Low Hi Z INTPZ6 INTPZ7 P12 P13 Low Hi Z With internal pull up resistor INTPZ8 INTPZIO P22 P24 Low Hi Z INTPZ11 P43 Low Hi Z With internal pull up resistor INTPZ12 INTPZ15 P74 P77 Low Hi Z INTPZ16 INTPZ21 RP00 RPO5 Low Hi Z INTPZ22 INTPZ24 P35 P37 With internal pull up resistor INTPZ25 INTPZ28 RP24 RP27 Hi Z With internal pull down resistor R18UZ0003EJ0301 Dec 25 2014 Page 17 of 203 R IN32M3 EC User s Manual 2 Signals by function 2 1 9 Timer I O Signals Pin Name I O Function Shared Active Level during reset amp Port Level af
37. 01 Not configured SII EEPROM 10 EBUS 11 MII RMII 0 Address Initial Value OFH 5 4 P2 Port2 configuration This LSI doesn t implement port2 00 Not implemented 01 Not configured SII EEPROM 10 EBUS 11 MII RMII 3 2 P1 Port1 configuration This LSI is MII 00 Not implemented 01 Not configured SII EEPROM 10 EBUS 11 MII RMII PortO configuration This LSI is MII 00 Not implemented 01 Not configured GI EEPROM 10 EBUS 11 MII RMII R18UZ0003EJ0301 Dec 25 2014 Page 55 of 203 R IN32M3 EC User s Manual 6 7 8 6 EtherCAT Slave Controller function ESC Features supported register FEATURE This register indicates the features supported by the EtherCAT Slave Controller 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value Zle lo PEER ad rd 6 5 400E 0008H OSCH EAR ECAT 0 0 0 0 R R R R PDI 0 0 0 0 R R R R Bit position Bit name Function 11 FSCONFIG Fixed FMMU SyncManager configuration 0 Variable configuration 1 Fixed configuration 10 RWSUPP EtherCAT read write command support BRW APRW FPRW 0 Supported 1 Not supported 9 LRW EtherCAT LRW command support 0 Supported 1 Not supported 8 DCSYNC Enhanced DC SYNC Activation 0 Not available 1 Available 7 FCS Separate Handling of FCS Errors 0 Not supported 1 Supported frames with wrong FCS and additional nibble will be
38. 2 7 2 1 7 2 2 7 2 3 7 2 4 7 3 7 3 1 7 3 2 7 3 3 7 4 7 4 1 7 4 2 7 4 3 7 4 4 7 4 5 7 4 6 7 4 7 7 4 8 7 4 9 7 4 10 7 4 11 7 4 12 7 4 13 7 4 14 7 4 15 7 4 16 7 4 17 7 4 18 7 4 19 7 4 20 7 4 21 7 4 22 7 4 23 7 4 24 7 5 7 5 1 Battes eegene ZOE dukke asekedelge kuta pre pe been ro p po o p nn mmen 126 Special functions EE 126 OSA Irilo ske EE 126 Quick auto negotiation function resies n ea in Ea a E iI EEE ER RREA 127 Cable diagnostic function TDR functpon 129 Fast link loss detection function s sessar n i a ere eie e a EE Soe SEEE T E ee N ERVE 132 power down Mod siiri eserse bre ee E re buo eb wot kea nb ESE dk sk hk ulo e dankos kodo 133 plaid ware poWerdoWwNModes zs See dese S oe a E E EEEN ES SA 133 Software power down mode 5 3 ss iutsses sab sacks ecssegssebsvnss yedacesvchasseebeesntescebachess REES ERE EE e S ETP ESETERE SREE 133 Energy detection power down mode 133 MII management register with Ethernet PHY internal eeronnrerorvrnrvrornrevrnrvrnrvrnvnnnnnnrnvervvrrveveveversverasvrasvresner 134 Repister 0 Control Register sss stn sss snu sss 135 Reister P Status ReEBIStET ss a on Eeer 136 Register 2 3 PHY Id ntifierssis ikea se oddsene dikene STE 137 Register 4 Auto Negotiation Advertisement Register 138 Register 5 Auto Negotiation Link Partner Ability Base Page Renate 139 Register 5 Auto Negotiation Link Partner Ability Next Page Register
39. 25 2014 R IN32M3 EC User s Manual 7 4 18 Register 25 Diagnostic control Status Register Set diagnostic function of Ethernet PHY and show the results MR25 RESERVED RW Bit Position 7 Etherne PHY Function RW RW RW SC Bit Name RESERVED PHY Address Wu I 19H ADG MAX VALUE l sie oj Se z ADC TRIGGER EEE PW DIAG Initial Value Q Ci Q o RW RW RW RW R R RW RW RW RW RW Function Reserved Write 0 and ignore reading DIAG INIT Start TDR test and generate a single cycle pulse 0 Normal operation 1 Pulse generation Turns to 0 after pulse generation ADC MAX VALUE Read Shows the maximum minimum signed value of the reflected wave When the TDR test starts PHY sends out a trigger pulse and waits for the reflected wave for 255 cycles 2040ns of 8ns clock DIAG DONE bit is set after the time Indicates the maximum value of the received wave if it is a positive value and minimum value if negative ADC TRIGGER Write Sets the threshold voltage for detecting the reflected wave from 000111 0 5V to 001111 1 5V This setting cannot be read DIAG DONE DIAG POL DIAG SEL LINE PW DIAG R18UZ0003EJ0301 Dec 25 2014 Shows that the counter is stopped 0 Running or TDR untested 1 Stop set to 0 after reading Shows the polarity of the reflected wave detected 0 Positive logic 1 Negative logic Select t
40. 3 6 11 3 AL Status Code register AL STATUS CODE This register indicates error code from slave application 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value AL STATUS STATUSCODE CODE 400E 0134H 0000H ECAT R R R R R R R R R R R R R R R R PDI RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 15 0 STATUSCODE AL Status Code Error codes from the slave application R18UZ0003EJ0301 Page 67 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 11 4 RUN LED Override register RUN LED OVERRIDE This register is used to override RUN LED control 7 3 2 1 0 Address Initial Value 6 5 RUN_LED_ 0 0 0 LEDCODE 400E 0138H 00H OVERRIDE 0 0 0 4 ECAT RW RW RW R W R W PDI 0 0 0 R W R W R W R W R W OVERRIDEEN Bit position Bit name Function 4 OVERRIDEEN Enable Override 0 Override disabled 1 Override enabled 3 0 LEDCODE LED code FSM State 0x0 Off 1 Init Ox1 0xC Flash 1x 12x 4 SafeOp 1x OxD Blinking 2 PreOp OxE Flickering 3 Bootrap OxF On 8 Op Caution Changes to AL Status register 0x0130 with valid values will disable RUN LED Override 0x0138 4 0 The value read in this register always reflects current LED output Normally RUN LED is controlled by AL Status register automatically It is not necessary to override RUN LED in order to indicate status of general state machine E g it is available to use this register i
41. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 Address 400A 3044H S Initial value PFCE4W m a r ol0 0lols ala 0101010 0 mann ta dd a va 0000 00004 O O O O0 O O O O LL LL LL LL LL LL LL LL a a a a o a a a RW RWRIWRWRWRWRWRWRW O 0 RWRWRWRW O O O O O RWRWRWRWRW O 0 O O ORW 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 Address 400A 3440H RPFCEOW LO Initial value 01010101010101010101 0 0 0 Si O 0000 0000H LL S SES Ss R W 0000000000000000000000000 0 RIW R W R W RAW RW RW Bit position Function PFCEmn Specify whether to use alternate functions 1 and 2 or alternate functions 3 and 4 RPFCEIn 0 Alternate function 1 Alternate function 29 1 Alternate function 3 7 Alternate function 4993 Note1 The initial value depends on the pin status For details see 2 2 Port status Note2 To use alternate function 1 or 3 the bit corresponding to the function in the PFC RPFC register must be set to 0 Note3 To use alternate function 2 or 4 the bit corresponding to the function in the PFC RPFC register must be set to 1 Remark 1 0to3 m 0to7 n 0to7 R18UZ0003EJ0301 Page 184 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 8 3 6 Port pin input registers PIN RPIN These are read only registers for reading the input level of port pins Address Initial 7 6 5 4 3 2 1 0 value PINOB PINO7 PINO6 PINOS P
42. 4 Request Safe Operational State 8 Request Operational State Initiate State Transition of the Device State Machine Note The PDI has to read the AL Control register after ECAT has written it Otherwise ECAT can not write again to the AL Control register After Reset AL Control register can be written by ECAT Regarding mailbox functionality both registers 0x0120 and 0x0121 are equivalent e g reading 0x0121 is sufficient to make this register writeable again Reading AL Control from PDI clears AL Event Request 0x0220 0 R18UZ0003EJ0301 Dec 25 2014 Page 66 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 11 2 AL Status register AL STATUS This register indicates Slave application status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value LLI AL STATUS o O 0 400E 0130H 0001H cc FE e O W st R R R R R ECAT 0 0 0 0 0 0 0 0 0 0 0 ack ack ack ack ack PDI 0 0 0 0 0 0 0 0 0 0 0 Ri w R w R w Rw R w Bit position Bit name Function Error Ind 0 Device is in State as requested or Flag cleared by command 1 Device has not entered requested State or changed State as result of a local action ACTSTATE Actual State of the Device State Machine 1 Init State 3 Request Bootstrap State 2 Pre Operational State 4 Safe Operational State 8 Operational State Note Reading AL Status register from ECAT clears ECAT Event Request 0x0210
43. 5 4 3 2 1 0 a 1DH 5 Initial Val FE nitial Value o L KS D Ka N co LO lt Ed N Ro 0000H E LI EI E E I LE E e w ES Zz zZ ac Zz Z Z Zz Z Z ES ac Function Reserved Write 0 and ignore reading INT12 Clipping INT11 Maxlvl INT10 BER counter trigger INT9 RESERVED FEQ Trigger Reserved Write 0 and ignore reading INT7 Energy detection of the line INT6 Auto negotiation is complete INT5 Remote fault detection INT4 Link down INT3 Auto negotiation is complete and receive the last FLP INT2 INT1 Parallel detection failure Auto negotiation is transition to Complete Acknkowledge state RESERVED R18UZ0003EJ0301 Dec 25 2014 Reserved Write 0 and ignore reading Page 155 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 23 Register 30 Interrupt Factor Mask Register Enable disable interrupt factors of Ethernet PHY 0 is invalid mask while 1 is valid 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR30 PHY Address 7 Si Ka e Ka SE p Ka SE SE x TEN RESERVED I I FI LIZ LI LILL 2 2 AU Z initial Value a fo fo a Mea Ee a a a 2 0000H z zZ zi zMez zZz z2 2 Z2 2 2 9 R R R RW RW RW RW R RW RW RW RW RW RW RW R Bit Position Bit Name Function RESERVED R
44. 6 5 4 3 2 1 0 Address Initial Value PDI ERR PDIERRCNT 400E 030DH 00H COUNT ECAT RM clr RAW clr R W clr R W clr R W clr R W clr Bic RM clr PDI R R R R R R R R Bit poston 7 0 PDIERRCNT PDI Error counter counting is stopped when OxFF is reached Counts if a PDI access has an interface error Cleared if register is written 6 14 5 Lost Link Counter n register LOST_LINK_COUNTn This register counts lost links at port n 7 6 5 4 3 2 1 0 Address Initial Value LOST LINK 400E 0310H LOSTLINKONT 00H COUNTn 0001H n ECAT RM clr RAWV clr Bic R MW clr R W clr R W cir Bic RAM clr PDI R R R R R R R R Bit position 7 0 LOSTLINKCNT Lost Link counter of Port n counting is stopped when Oxff is reached Counts only if port loop is Auto or Auto Close Only lost links at open ports are counted Cleared if one of the Lost Link counter registers is written Note Only lost links at open ports are counted R18UZ0003EJ0301 Page 80 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 15 Watchdogs Registers 6 15 1 Watchdog Divider register WD_DIVIDE This register is used to set the divider ratio for 25MHz as the basic watchdog increment 15 14 13 12 11 10 9 0 Address Initial Value WD_DIVIDE WDDIV 400E 0400H 09C2H ECAT RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PDI R R R R R R R R R R R R R R R R Bit position 15 0 WDDIV Watchdog divi
45. 64Kbyte Data RAM area 512Kbyte Reserved Instruction RAM area 768Kbyte 400F COOOH 400F BFFFH 400F BOOOH 400F AFFFH 400F A000H 400F 9FFFH 400F 8000H 400E 3000H 400E 2FFFH 4Gbyte 400E OF80H 400E 0000H 400A FFFFH 400A 3000H 4001 FFFFH 4001 0000H 2007 FFFFH 2000 0000H 000D 2FFFH 000C 0000H 000B FFFFH 0000 0000H Figure 3 5 External MPU interface area R18UZ0003EJ0301 Dec 25 2014 Page 33 of 203 R IN32M3 EC User s Manual 4 Exception handling function R IN32M3 use the Interrupt Controller built in to Cortex M3 Please refer to the following URL of ARM for Exceptions handling operation of Cortex M3 4 Exception handling function http infocenter arm com help topic com arm doc set cortexm index html 4 1 Ex ceptions list Exception No 1 15 is system exception of Cortex M3 CPU The interrupt from the internal hardware of R IN32M3 and External port is assigned after Exception No 16 Exception Exception type Priority Remark No 1 Reset 3 Reset port RST_B input most significant Reset from Watchdog Timer Set 1 the SYSRESETREQ bit of NVIC built in Cortex M3 CPU 2 NMI 2 NMI port input Generate NMI from Watchdog Timer 3 Hard fault 1 Using to the promotion of exception fault of all class that can be operated by other exceptions Memory manage fault programmable Exception from MPU Bus fault programmable Bus error of bus
46. 86 Contents 3 6 16 5 6 17 6 17 1 6 17 2 6 17 3 6 17 4 6 17 5 6 17 6 6 17 7 6 18 6 18 1 6 18 2 6 18 3 6 18 4 6 18 5 6 18 6 6 18 7 6 18 8 6 19 6 19 1 6 19 2 6 19 3 6 19 4 6 19 5 6 19 6 6 20 6 20 1 6 20 2 6 20 3 6 20 4 6 20 5 6 20 6 6 21 6 21 1 6 21 2 6 21 3 6 21 4 EEPROM Data register EEP DATA ssnnunsisnrnsnssnsineteen RT TOTEEN 87 MI Management Interface Registers sosiete cedshssesossssvaasssssvesoedessessdessonsvcusscescgessbascebeseuvegdsossevasensessesnigse 88 MII Management Control Status register MIL CONT STAT 88 PHY Address tegister PHY ADR sss sss AS A Abe 89 PHY Register Address register PHY REG ADR 89 PHY Data r gister PHY DATA sia maso EA SA KA AMARA 90 MII Management ECAT Access State register MI BCAT ACR STAT 90 MII Management PDI Access State register MI PDI ACS SIATI 91 PHY Port Status n register PHY STATUSn nie ER EA E E EEO RSS 92 FMMU eJ RAS o oJoeiep sr qo oHBooerr p T J ooooe PITT TTT 93 FMMU Logical Start Address m register FMMUm L START ADR 93 FMMU Length m register EPMMUm LENA 93 FMMU Logical Start bit m register FMMUm L START BUI 94 FMMU Logical Stop bit m register FMMUm L STOP BI 94 FMMU Physical Start Address m register FMMUm P START ADR 95 FMMU Physical Start bit m register FMMUm P START BI 95 EMMU Type m resister EMMU M TYPE suisse siono deeg dE 96 FMMU Activate m register FMMUmM ACT rrn
47. Bytes ECATWREN ECAT write enable 0 Write requests are disabled 1 Write requests are enabled This bit is always 1 if PDI has EEPROM control Note Write access depends upon the assignment of the EEPROM interface ECAT PDI Write access is generally blocked if EEPROM interface is busy 0x0502 15 1 R18UZ0003EJ0301 Dec 25 2014 Page 85 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function Caution 1 Error bits are cleared by writing 000 or any valid command to Command Register Bits 10 8 2 Write Enable bit 0 is self clearing at the SOF of the next frame Command bits 10 8 are self clearing after the command is executed EEPROM Busy ends Writing 000 to the command register will also clear the error bits 14 13 Command bits 10 8 are ignored if Error Acknowledge Command is pending bit 13 6 16 4 EEPROM Address register EEP_ADR This register is used to set EEPROM address to be accessed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 21 0 Address 400E 0504H Initial Value 0000 0000H EEP ADR ADDRESS ECAT RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW PDI RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW ROW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RAW RW RAW RAW RAW RAW RAW RAW
48. DC ACT 400E 0981H Pulse Length of SyncSignals Activation Status DC PULSE LEN DC ACT STAT 400E 0982H 400E 0984H SYNCO Status DC SYNCO STAT 400E 098EH SYNC1 Status Start Time Cyclic Operation Next SYNCO Pulse DC SYNC1 STAT DC CYC START TIME 400E 098FH 400E 0990H Next SYNC1 Pulse SYNCO Cycle Time DC NEXT SYNC1 PULSE DC SYNCO CYC TIME 400E 0998H 400E O9A0H SYNC1 Cycle Time DC_SYNC1_CYC_TIME 400E 09A4H DC Latch In Unit registers LatchO Control DC LATCHO CONT 400E 09A8H Latch1 Control DC LATCH1 CONT 400E 09A9H LatchO Status DC LATCHO STAT 400E 09AEH Latch1 Status LatchO Time Positive Edge DC LATCH1 STAT DC LATCHO TIME POS 400E 09AFH 400E 09BOH LatchO Time Negative Edge DC LATCHO TIME NEG 400E 09B8H Latch1 Time Positive Edge DC LATCH1 TIME POS 400E 09COH Latchi Time Negative Edge DC LATCH1 TIME NEG 400E 09C8H DC SyncManager Event Times registers Buffer Change Event Time DC ECAT CNG EV TIME 400E 09FOH PDI Buffer Start Event Time PDI Buffer Change Event Time R18UZ0003EJ0301 Dec 25 2014 DC PDI START EV TIME DC PDI CNG EV TIME 400E 09F8H 400E 09FCH Page 48 of 203 R IN32M3 EC User s Manual 16 ETC Registers 6 EtherCAT Slave Controller function Register name Shortcut byte Address PRODUCT ID PRODUCT ID 8 400E OE00H Vender ID VENDOR
49. Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property
50. ID 8 400E OE08H User RAM USER RAM 400E OF80H 400E OFFFH Process Data RAM DATA_RAM 400E 1000H 400E 2FFFH Caution 1 When accessing 1 Peripheral function registers via the external microcontroller interface the base address is D 0000H When accessing these registers from the CPU or DMA controller the base address is 4001_0000H When accessing from the CPU or DMA controller BASE 4001_0000H When accessing via the external microcontroller interface BASE D 0000H When accessing via the external microcontroller interface only User RAM and Process Data RAM 400E OF80H 400E 2FFF can be accessible in the whole ESC memory area 400E 0000H 400E 2FFFH R18UZ0003EJ0301 Dec 25 2014 Page 49 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 6 Peripheral Function Registers 6 6 1 EtherCAT PHY offset address setting register CATOFFADD CATOFFADD register set the offset address of Ether PHY in case of using EtherCAT This register can be read Written in 32 bit or 16bit units Caution This register can be written only in case of releasing protection by specific sequence using system protects command register SYSPCMD Please refer to system protect command register SYSPCMD for protection releasing procedure In addition the special sequence is not necessary in case of reading the value of this register Please refer to R IN32M3 User s Manual Periph
51. O O INTECATRST EtherCAT RESET interrupt O O z Table 6 3 I O signals of EtherCAT Slave Controller excluding PHY MDI signals Pin Name UO Function Shared Port Active CATLEDRUN O Ether CAT RUN LED port POO High CATIRQ O Ether CAT IRQ port PO1 High CATLEDSTER O Ether CAT Dual color State LED port P02 High CATLEDERR O Ether CAT Error LED port P03 High CATLINKACTO O Ether CAT Link Activity LED port Port 0 P04 High CATLINKACT1 O Ether CAT Link Activity LED port Port 1 P05 High CATSYNCO O Ether CAT SYNCO port P11 High CATSYNC1 O Ether CAT SYNC1 port P10 High CATLATCHO l Ether CAT LATCHO port P11 High CATLATCH1 l Ether CAT LATCHI port P10 High CATI2CCLK O Ether CAT EEPROM 12C clock port P22 CATI2CDATA I O Ether CAT EEPROM I2C data port P23 CATRESTOUT O Ether CAT PHY RESETOUT port P56 R18UZ0003EJ0301 Dec 25 2014 Page 41 of 203 R IN32M3 EC User s Manual 6 4 Functional Overview 6 EtherCAT Slave Controller function Typical functions of EtherCAT Slave Controller and supported function by R IN32M3 EC are shown below Regarding the detailed specification of EtherCAT and ESC refer to the documentation e g ETG 1000 EtherCAT Specification provided by EtherCAT Technology Group ETG and the EtherCAT Slave Controller IP Core v2 04 datasheet provided by Beckhoff Automation Table 6 4 Typical functions of EtherCAT Slave Controller and supported function by R IN32M3 EC 1 3 Features Func
52. P76 INTPZ14 P1SPEED100LEDZ CCS STATION NO 6 CCM SNIN6 P77 INTPZ15 P1SPEED10LEDZ CCS STATION NO 7 CCM SNIN7 R18UZ0003EJ0301 Dec 25 2014 2 Signals by function 3 4 Level during reset amp Level after reset Hi Z Page 14 of 203 R IN32M3 EC User s Manual 2 Signals by function RPOx RP3x are Real time ports which can transfer data via a dedicated DMA comtroller and are unaffected by bus congestion They are able to perform input and output of the port by 32 bit unit in sync with DMA transfer trigger by DMA Controller for exclusive use of the Real time port Port 4 4 Level during reset amp Nene Mode 1 Mode 2 Mode 3 Mode 4 en RPO RPOO INTPZ16 SCL1 CCM_SDLEDZ Hi Z CCS_SDLEDZ With internal pull up RPO1 INTPZ17 SDA1 CCM SMSTZ resistor RPO2 INTPZ18 POACTLEDZ CCS_BS1 RPO3 INTPZ19 CCS BS2 RP04 INTPZ20 P1ACTLEDZ CCS BS4 RP05 INTPZ21 CCS BS8 RP06 WRZ2 BENZ2 HWRZ2 HBENZ2 RP07 WRZ3 BENZ3 HWRZ3 HBENZ3 D24 HD24 D25 HD25 D26 HD26 D27 HD27 D28 HD28 D29 HD29 D30 HD30 D31 HD31 Hi Z With internal pull up resistor BCYSTZ ADVZ HBCYSTZ Hi Z With internal pull up resistor A21 A22 A23 A24 INTPZ25 A25 INTPZ26 A26 A27 INTPZ27 INTPZ28 Hi Z With internal pull down resistor D16 HD16 D17 HD17 D18 HD18 D19 HD19 D2
53. PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC AOOA 3022H 37 36 35 34 33 32 31 30 27 26 25 24 23 22 21 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RA lInitial value Wielt W e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address PMCAH PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC A DA 3024H 57 56 55 54 53 52 51 50 47 46 45 44 43 42 41 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RA Initial value Wielt W e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address PMC6H PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC 400A 3026H 77 76 75 74 73 72 71 70 67 66 65 64 63 62 61 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Rw Initial value OOOOH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPMCOH RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RA lInitial value OOOOH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address RPMC2H RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM C36 C35 ca4 cas C32 c31 cao C27 c26 C25 C24 c23 C22 C21 c20 4004 3422H RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Rw Initial value o000KH 15to0 PMCmn Specify whether to use the port as a port or for its alternate function RPMCIn 0 Port mode The Inactive level is input to the
54. R ack R ack R ack R ack R ack PDI R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack Black R ack R ack R ack R ack R ack R ack R ack R ack Black R ack R ack R ack R ack R ack 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 1 0 SYSTIME ECAT R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack PDI R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack Black R ack R ack R ack R ack R ack R ack R ack R ack Black R ack R ack R ack R ack R ack Bit position Function 63 0 SYSTIME Register captures System time at the negative edge of the LatchO signal Reading clears LatchO Status 0x09AE 1 Note 1 Register bits 63 8 are internally latched ECAT PDI independently when bits 7 0 are read which guarantees reading a consistent value 2 Clearing LatchO Status flag function depends upon setting of 0x0980 4 R18UZ0003EJ0301 Page 118 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 5 7 Latch1 Time Positive Edge register DC LATCH1 TIME POS This register indicates System time at the positive edge of the Latch signal 63 6
55. Remark 1 0t03 m 0to7 n 0to7 R18UZ0003EJ0301 Page 170 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address e eee vo or ros rr r rr Jo o RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Rw lInitial value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW lInitial value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW lInitial value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address ros roe reve rer or ro rs re rs rs ro son RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Rw Initial value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address RPOH RP17 RP16 RP15 RP14 RP13 IRP12 IRP11 RP10 RPO7 RPO6 RPO5 RPO4 RPO3 RPO2 RPO1 RPOO 400A 3400H RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RA Initial value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address RP2H RP37 RP36 RP35 RP34 RP33 RP32 RP31 RP30 RP27 RP26 RP25 RP24 RP23 RP22 IRP21 RP20 400A 3402H RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Rw Initial value 0000H 15t00 Pmn RPIn Set the value of the output latch when the port is used in output mode If read the value of the output latch is read Figure 8 3 Port registers in 16 bit notation Remark 0to3 m 0to7 n 0to7 R18UZ0003EJ0301 Page 171 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port funct
56. Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with
57. Revision Register Vendor specific Mode Control Status Register Vendor specific Special Mode Register Reserved Vendor specific Vendor specific Reserved Vendor specific Reserved Vendor specific Reserved Vendor specific BER counter Register Vendor specific FEQ monitor Register Vendor specific Diagnostic control Status Register Diagnostic Counter Register Vendor specific Vendor specific Special Control Status Indication Register Vendor specific Reserved Vendor specific Interrupt Factor Register Vendor specific Interrupt Factor Mask Register Vendor specific R18UZ0003EJ0301 Dec 25 2014 PHY Special Control Status Register Vendor specific Page 134 of 203 R IN32M3 EC User s Manual 7 4 1 7 Etherne PHY Function Register 0 Control Register Register 0 makes the basic settings of the Ethernet PHY 15 14 13 12 11 z HL oH x Soa MRO Es W lt x a zz m nols w D LL o ow SAAR 9 159 29 RW RW RW RW RW SC Bit Position Bit Name 10 9 8 7 6 5 4 3 2 1 NEGOTIATION RESERVED ISOLATE RESTART AUTO DUPLEX MODE COLLISION TES T RW RW SC RW Function Reset the Ethernet PHY Please don t change the settings of the other bits of this register when resetting 0 Normal operation 1 Software Reset PHY Address 00H Initial Value
58. ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack PDI R ack R ack R ack R ack R ack Black R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack Black R ack R ack R ack R ack R ack R ack R ack R ack Black R ack R ack R ack R ack R ack Bit position Function 63 0 SYSTIME Register captures System time at the positive edge of the LatchO signal Reading clears LatchO Status 0x09AE 0 Note 1 Register bits 63 8 are internally latched ECAT PDI independently when bits 7 0 are read which guarantees reading a consistent value 2 Clearing LatchO Status flag function depends upon setting of 0x0980 4 R18UZ0003EJ0301 Page 117 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 5 6 LatchO Time Negative Edge register DC LATCHO TIME NEG This register indicates System time at the negative edge of the LatchO signal 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address 400E 09B8H DC_ Initial Value LATCHO_ SYSTIME 0000 0000 TIME_NEG 0000 0000H ECAT Rack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack
59. clock input port Renesas test port R18UZ0003EJ0301 Page 23 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 Signals by function 2 1 18 Operation mode Setting Signals Pin Name UO Function Active Level during reset amp Level after reset BOOT1 BOOTO Boot mode select port 00 External memory boot 01 External serial flash ROM boot 10 External MPU boot 11 Instruction RAM boot debugger used ONLY MEMIFSEL External Memory Interface select port 0 Slave memory Interface 1 External MPU Interface BUS32EN I External Memory Interface Bus width select port 0 16bit bus 1 32bit bus HIFSYNC External MPU I F Operation mode select port 0 asynchronous SRAM Interface 1 synchronous SRAM Interface HWRZSEL l External MPU Interface HWRZ HBENZ select port 0 HBENZ use 1 HWRZ use MEMCSEL Internal Memory Controller select port 0 asynchronous SRAM MEMC 1 synchronous burst access MEMC Note ADMUXMODE Multiplex of Address Data port 0 Separate 1 Multiplex of Address Data Note ADMUXMODE port is only available when MEMCSEL port is High which selects synchronous burst access MEMC The asynchronous SRAM MEMC does not support address data multiplexing R18UZ0003EJ0301 Page 24 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 Signals by function 2 2 Port status T
60. controller and buffer for the network processor High performance with low CPU usage by offloading functions to Real Time OS Accelerator e Multiple timers serial interfaces general purpose I O GPIO external memory interfaces R IN32M3 EC User s Manual 1 2 Overview Table 1 1 1 Overview Overview of R IN32M3 EC 1 2 R IN32M3 EC es Product CPU core ARM Cortex M3 32 bit RISC CPU Real Time OS Accelerator Hardware Real Time OS HW RTOS Operating frequency 100MHz Instruction set Thumb 2 instruction ARMv7 M architecture Instruction RAM 768KByte RAM w ECC Data RAM 512KByte RAM w ECC Buffer RAM Internal System Bus 64KByte RAM w ECC 32 bit system bus at 100MHz 128 bit communication bus at 100MHz DMA Bus System Bus Side 4 channels 1 channel for Real time port Supports software and various interrupt triggered DMA Boot options Serial Flash ROM Boot External Memory Boot External MPU Boot External Memory Support 16 bit or 32 bit bus interface Page ROM ROM SRAM interface Synchronous burst memory interface Four chip selects for external SRAM 256MByte max external memory space Programmable wait function External MPU interface 16 bit or 32 bit bus interface General purpose interface for static memory Address space 2MByte Instruction RAM Data RAM Register area Serial Flash ROM Memory Contr
61. damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a
62. map External memory are 32 Memory map CC Link Master area cece ceeeeeeeeceeeceescesecesecsecsaecsaecsaeenaeeaeseaeeeeeeeeeeenseeaeenaes 32 External MPU interface area 2 c ccsscccsscesvecchetiesiagcessdecestoceodesansaecdcvessdebunnevavasdodendesaavescesyvssenseenvdecosnbende 33 Peripheral circuit of EtherCA Toei eet suas sneberbendenasbennedap eee 40 Preamble of Ethernet frames eege keete ASMA A hane 126 Behavior of cable disconnected rennvnrnrnvennvnrnrnrennnnrnraeennenenrnennnnenrsnennnnenravennenenrsnennenenrasennenenrssenneser 129 Behavior of cable short circuited eernoronnnnvrrrnennvnerrrnennnneeranennnnerranennnnesrsnennnnenrsvennenevrsnennenesrssennener 129 cable diagnostic process TIOW s seis po ssensssosk vu st upoeso stio issnin a iss arna r EEEE EEEE EE SE r 131 Basic port circuit confteuraton 163 Port registers in 8 bit notation senorrrnrnvennvnrnrnrenrnnenrasennnnsnanennnnenrassnnnnenrssennenenrsssnnnnenrsssnnensnrssennener 170 Port registers in 16 bit notation enrii ea E E R A A R 171 Port registers in 32 bit notation ensenen icen e n iii iee E E E E 172 Port mode registers in 8 bit notation senrrrrnrnvennvnrnranennnnenrnennnnerrnennnnerravennenenrsvennnnerssennenesrssennesee 173 Port mode registers in 16 bit notation rrronreronrvnrnranennnnenrnennnnerranennenerrarsnnenerravennenesrssennenerssenneser 174 Port mode registers in 32 bit notation nrrrrnreronnvnrnrnrennnnenrr
63. position 11 Bit name SMSTA7 400E 0210H 0000H v SMSTA7 v SMSTA6 m SMSTA5 2 SMSTA4 x SMSTA3 v SMSTA2 x SMSTA1 x SMSTAO w w ALSTA 2 7 DLSTA x DCLATCH Function Mirrors values of SyncManager7 Status 0 No Sync Channel 7 event 1 Sync Channel 7 event pending 10 SMSTA6 Mirrors values of SyncManager6 Status 0 No Sync Channel 6 event 1 Sync Channel 6 event pending SMSTA5 Mirrors values of SyncManager5 Status 0 No Sync Channel 5 event 1 Sync Channel 5 event pending SMSTA4 Mirrors values of SyncManager4 Status 0 No Sync Channel 4 event 1 Sync Channel 4 event pending SMSTA3 Mirrors values of SyncManager3 Status 0 No Sync Channel 3 event 1 Sync Channel 3 event pending SMSTA2 Mirrors values of SyncManager2 Status 0 No Sync Channel 2 event 1 Sync Channel 2 event pending SMSTA1 SMSTAO Mirrors values of SyncManager1 Status 0 No Sync Channel 1 event 1 Sync Channel 1 event pending Mirrors values of SyncManagero Status 0 No Sync Channel 0 event 1 Sync Channel 0 event pending ALSTA AL Status event 0 No change in AL Status 1 AL Status change Bit is cleared by reading out AL Status0x0130 0x0131 from ECAT DLSTA DL Status event 0 No change in DL Status 1 DL Status change Bit is cleared by reading out DL Status 0x0110 0x0111 from ECAT DCLATCH DC Latch event 0 No change on DC Latch I
64. supply GND LX O Regulator 1 5V power Output EXTRES Reference resistor for EtherPHY connect port POVDDARXTX Analog Port Rx Tx power supply 1 5V Port 0 VDDAPLL EtherPHY Analog Central power supply 1 5V P1VDDARXTX Analog Port Rx Tx power supply 1 5V Port 0 VDDACB EtherPHY Analog Central power supply 3 3V S S AGND EtherPHY Analog Ground supply GND VDD15 EtherPHY I O for EtherPHY power supply 1 5V VSSAPLLCB EtherPHY Analog Central Ground supply GND VDD33ESD AVDD_REG EtherPHY Analog Test power supply 3 3V Regulator Analog power supply 3 3V AGND_REG Regulator Analog Ground supply GND BVDD Regulator power supply 3 3V BGND Regulator Ground supply GND FB Regulator Feedback port S VDDQ PECL BO PECL Buffer power supply 3 3V VDDQ PECL Bi R18UZ0003EJ0301 Dec 25 2014 PECL Buffer power supply 3 3V Page 22 of 203 R IN32M3 EC User s Manual 2 Signals by function 2 1 17 Test Signals Pin Name I O Function Active Level during reset amp Level after reset TMODEO TMODE2 Test mode select port TMS VO JTAG mode select port TDI JTAG serial data input port E TDO O JTAG serial data output port TRSTZ JTAG reset port Low TCK ATpNIS TMC1 TMC2 TESTI TEST2N0e TEST3 TESTOUTSN4 O JTAG
65. the software power down mode set 0 to bit 11 POWERDOWN of MII management register 0 The digital circuits are initialized automatically by Ethernet PHY at the conclusion of software power down mode However please note that some bits of MII management registers are not initialized Bit described as NASR are eligible in 7 4 MII management register with Ethernet PHY internal 7 3 3 Energy detection power down mode It can be shifted to energy detection power down mode by setting 1 to bit 13 EDPWRDOWN of MII management register 17 with Ethernet PHY internal Please note that energy detection power down mode can t be transited to when auto negotiation is enabled In this mode Ethernet PHY will not output anything except for several modules such as serial management interface when there is no input of link pulse or packet signal to Ethernet PHY Ethernet PHY will be reset automatically to the speed before becoming energy detection power down mode when link pulse or packet signal is input in this state At that time you may fail to receive the first and the next signal because of the detection of link pulse and packet signal Set 0 to bit 13 EDPWRDOWN of MII management register to end the energy detection power down mode and return to the normal mode R18UZ0003EJ0301 Page 133 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 4 It is the MII management register includes Ethernet PHY The state of Ethernet PHY can be got by variou
66. 0 27 26 25 24 23 22 21 20 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Initial value FFFFH 15t0 0 PMmn Set the port to input or output mode RPMIn 0 Output mode output buffer is on 1 Input mode output buffer is off initial value Figure 8 6 Port mode registers in 16 bit notation Remark l 0t0o3 m 0t07 n 0to7 R18UZ0003EJ0301 Page 174 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14131211109 8 7 6 5 43 210 Address 400A 3010H Initial value PMOW MIMNIMIMIMIMNIMNIM NININE IN IN INININ eelst gt 2 3232 gt gt gt 3 gt gt 3 2 gt gt gt gt gt 3 gt gt gt gt 3 gt 2 gt gt gt 3 gt gt 3 gt gt gt leleleleleleleleleleleleleleleleelelelelelelelelelelelelele eel R W R W R W R W R W R W R W R W R W R W RAW R W R W RAW R W R W RAW R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 543 210 Address 400A 3014H Initial value PM4W R NINIRIRI INIRIR o 0 I0O IO JO JO O O MIVMIVIMN M WMIV IND I Sy ty testy lt 3 2 33333333 33332 gt gt gt gt gt 3 gt 3 gt 2 gt gt gt 3 gt gt gt gt gt 2 a
67. 0 0 0 0 0 0 0 RW RW RW RW RW RW Initial value 0000H 15 14 13 12 11 1 0 Address 0 0 9 8 7 6 5 4 3 2 1 erce o o o o o o o o o o o o o oo o ons 0 0 0 0 0 0 0 0 0 0 0 0 Initial value o000H 0 0 0 Bit poston PFCEmn Specify whether to use alternate functions 1 and 2 or alternate functions 3 and 4 Note 2 Note 3 RPFCEIn 0 Alternate function 1 Alternate function 2 1 Alternate function 3 Alternate function Aide Figure 8 15 Port function control expansion registers in 16 bit notation Note1 The initial value depends on the pin status For details see 2 2 Port status Note2 To use alternate function 1 or 3 the bit corresponding to the function in the PFC RPFC register must be set to 0 Note3 To use alternate function 2 or 4 the bit corresponding to the function in the PFC RPFC register must be set to 1 Remark 0to3 m 0to7 n 0to7 R18UZ0003EJ0301 Page 183 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function Figure 8 16 Port function control expansion registers in 32 bit notation 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1413 12 11 10 9 8 7 6 5 43 210 Address 400A 3040H Initial value PFCEOW 0lolvls no a EH u l foo ed di 0000 0000H O O O 0 0 LL LL LL LL LL a a a a a R W R WR IWRWRWRMWRMW O O 0 RWRWRWRWRWRWRW O 0 0 0 R WR WR WR WR WR WR WR WRWRW O 0
68. 0 HD20 D21 HD21 D22 HD22 D23 HD23 Hi Z With internal pull up resistor R18UZ0003EJ0301 Dec 25 2014 Page 15 of 203 R IN32M3 EC User s Manual 2 Signals by function 2 1 6 Serial Flash ROM Interface Signals The Serial Flash ROM Interface supports Fast Read Fast Read Dual Output and Fast Read Dual I O mode Pin Name I O Function Shared Active Level during reset amp Port Level after reset SMSCK O Serial clock output port for serial flash ROM P14 tll Hi Z SMSI VO Serial data port for serial flash ROM P15 High With internal pull up Connect to SO of serial flash ROM resistor SMSO I O Serial data port for serial flash ROM P16 High Connect to SI of serial flash ROM SMCSZ O Chip select output port for serial flash ROM P17 Low 2 1 7 DMA Interface Signals There are two DMA Controllers one with four internal channels but only two external interfaces and one with one internal channel and one external interce as real time DMA controller Pin Name IO Function Shared Active Level during reset amp Port Level after reset RTDMAREQZ l RTDMAC DMA transfer request port P62 Low Hi Z RTDMAACKZ O RTDMAC DMA acknowledge output port P63 Low RTDMATCZ O RTDMAC terminal count output port P64 Low DMAREQZO DMA transfer request port 0 P65 Low DMAACKZO O DMA acknowledge output port 0 P66 Low DMATCZO O DMA Terminal count output port
69. 0000 9999H R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OR WO 1 RWRW O 1R o ER o Bit position Bitname Function Reserved Be sure to write 0 to these bits If read 0 is returned PUIOP4n Specify whether to connect a pull up or pull down resistor to the P47 to P40 pins PDIOP4n Connection of a pull up or pull down resistor to the P47 to P40 pins Do not connect a pull up or pull down resistor Connect a pull down resistor Connect a pull up resistor Setting prohibited Remark n 7toO R18UZ0003EJ0301 Page 195 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 8 5 4 Port 5 buffer function change registers DRCTLP5L DRCTLP5H lt R gt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 1 0 Address BASE 0248H DRCTLP5L 0 0 010 0 0 e CH Initial value 0000 0599H o o RIW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O O RM HIN RM RW RM RAW RM RAW R W R W R W R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 oa A 131211109 8 76 543210 Address BASE 024CH 0 Initial value 0000 9000H 1000000000000 DRCTLP5H 0 0 010 010 PUIOP57 R W 000000000000000 OR 2 Bit position Bit name Function Reserved Be sure to write 0 to these bits If read 0 is returned PUIOP5n Specify whether to connect a pull up or pull down resistor to the P57 and P52 to P50 pins PDIOP5n
70. 000000 O O O O O O O 0RWRW O 1 RWRW O 1 RWRW O 1 RW R W R W R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 54 3 2 1 0 Address BASE 022CH NIN OD LO LO DRCTLP1H a a a a a a a a iti o 0 0 0 0 0 010 0 10 010 0 0 010 8 18 01118180 11181810 115801 Initial value S Ala alm a lm 0000 9999H R W 000000000000000 OR 2 O 1 RWRW O 1 RWRW O 1 RWRW O 1 Bit position Bitname Function Reserved Be sure to write 0 to these bits If read 0 is returned PUIOP1n Specify whether to connect a pull up or pull down resistor to the P17 to P10 pins PDIOP1n Connection of a pull up or pull down resistor to the P17 to P10 pins Do not connect a pull up or pull down resistor Connect a pull down resistor Connect a pull up resistor Setting prohibited IOLP101 Specify the driving capability of the P10 pin IOLP100 IOL1 IOLO Driving capability of P10 pin 12 mA Other than above Setting prohibited Remark n 7t00 R18UZ0003EJ0301 Page 193 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 8 5 2 Port 3 buffer function change registers DRCTLP3L DRCTLP3H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13121110 9 8 7 6 5 43 2 10 Address Bit position BASE 0238H SE D o SIS DRCTLP3L 010 0 0 010 5 5 0 5 e o S e Initial value FL as F 2 0000 9999H RW 000000000000 0 0 0 ORWRW O 1 RWRW O 1 RWRW O 1 RWRW O 1 31 30 29 28 2
71. 002H P3B 400A 3003H Port register 4 8 bits P4B 400A 3004H Port register 5 8 bits P5B 400A 3005H P6B 400A 3006H Port register 3 8 bits Port register 7 8 bits 400A 3007H Port register 0 16 bits 400A 3000H Port register 2 16 bits 400A 3002H 400A 3004H Port register 6 16 bits 400A 3006H Port register 6 8 bits Port register 4 16 bits Port register 0 32 bits 400A 3000H Port register 4 32 bits Port mode register 0 8 bits 400A 3004H 400A 3010H Port mode register 1 8 bits 400A 3011H Port mode register 2 8 bits Port mode register 3 8 bits 400A 3012H 400A 3013H Port mode register 4 8 bits 400A 3014H Port mode register 5 8 bits 400A 3015H Port mode register 6 8 bits 400A 3016H 400A 3017H Port mode register 0 16 bits 400A 3010H Port mode register 2 16 bits Port mode register 4 16 bits 400A 3012H 400A 3014H Port mode register 6 16 bits 400A 3016H Port mode register 0 32 bits 400A 3010H Port mode register 7 8 bits Port mode register 4 32 bits R18UZ0003EJ0301 Dec 25 2014 400A 3014H Page 164 of 203 R IN32M3 EC User s Manual Register name Symbol 8 Port function Address 2 6 Port mode control register 0 8 bits 40
72. 03EJ0301 Page 90 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 17 6 MII Management PDI Access State register MI PDI ACS STAT This register is used to set access state of MII management interface 7 6 5 4 3 2 1 0 Address MIL PDI 0 a 400E 0517H ACS STAT de 3 g lt ECAT 0 0 0 0 0 0 RW R PDI 0 0 0 0 0 0 R R W Bit position Bit name Function FORPDI Force PDI Access State 0 Do not change Bit 0x0517 0 1 Reset Bit 0x0517 0 to 0 ACSMII Access to MII management 0 ECAT has access to MII management 1 PDI has access to MII management 6 EtherCAT Slave Controller function Initial Value 00H Note Write access to bit 0 is only possible if 0x0516 0 0 and 0x0517 1 0 R18UZ0003EJ0301 Dec 25 2014 Page 91 of 203 R IN32M3 EC User s Manual 6 17 7 PHY_ STATUSn ECAT PDI Bit position 6 EtherCAT Slave Controller function PHY Port Status n register PHY STATUSn This register indicates PHY port status each port 0 0 0 0 0 Bit name PHYCONFIG 5 4 3 2 1 0 Address Initial Value x g D E L EL ka LL Re 400E 0518H Z an ks lt lt x 00H O lt x LLI E E Z 4 O g O 9 9 0001H n z Mi A pr ao a l A R W clr R R W clr R R R R W clr R R W clr R R R Function PHY configuration updated 0 No update 1 PHY configuration was updated Cleared by writing any value to at least one of the PHY Status Port n registers LINKPARTERR Link pa
73. 0A 3020H Port mode control register 1 8 bits 400A 3021H Port mode control register 2 8 bits 400A 3022H Port mode control register 3 8 bits 400A 3023H Port mode control register 4 8 bits PMC4B 400A 3024H Port mode control register 5 8 bits PMC5B 400A 3025H Port mode control register 6 8 bits PMC6B 400A 3026H PMC7B 400A 3027H Port mode control register 0 16 bits 400A 3020H Port mode control register 2 16 bits 400A 3022H Port mode control register 4 16 bits Port mode control register 6 16 bits 400A 3024H 400A 3026H Port mode control register 7 8 bits Port mode control register 0 32 bits 400A 3020H Port mode control register 4 32 bits 400A 3024H Port function control register 0 8 bits 400A 3030H Port function control register 1 8 bits 400A 3031H Port function control register 2 8 bits 400A 3032H Port function control register 3 8 bits 400A 3033H Port function control register 4 8 bits 400A 3034H Port function control register 5 8 bits 400A 3035H Port function control register 6 8 bits 400A 3036H Port function control register 7 8 bits 400A 3037H Port function control register 0 16 bits 400A 3030H Port function control register 2 16 bits 400A 3032H Port function control register 4 16 bits 400A 3034H Port function control register 6 16 bits 400A 3036H Port function control register 0 32 bits 400A 3030H Port functio
74. 0H ACT I I 0008H m O O E E lt x lt x ECAT RW R W PDI R ack Rack Bit position Bit name Function LATCHPDI Latch Event PDI 0 No 1 Generate Latch events if PDI issues a buffer exchange or if PDI accesses buffer start address 6 LATCHECAT Latch Event ECAT 0 No 1 Generate Latch event if EtherCAT master issues a buffer exchange 1 REPEATREQ Repeat Request A toggle of Repeat Request means that a mailbox retry is needed primarily used in conjunction with ECAT Read Mailbox 0 SMEN SyncManager Enable Disable 0 Disable Access to Memory without SyncManager control 1 Enable SyncManager is active and controls Memory area set in configuration Note 1 m 0 7 2 Reading this register from PDI in all SyncManagers which have changed activation clears AL Event Request 0x0220 4 R18UZ0003EJ0301 Page 100 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 19 6 This register SMm PDI CONT ECAT PDI Bit position SyncManager PDI Control m register SMm PDI CONT is used to control SyncManager from PDI 1 0 Address Initial Value 7 6 5 4 3 2 x Q Ww res gt 400E 0807H 0 x E 00H Li O 0008H m o lt x OI Li cc a 0 0 0 0 0 0 R R 0 0 0 0 0 0 RW RW Bit name Function REPEATACK Repeat Ack If this is set to the same value as set by Repeat Request the PDI acknowledges the execution of a previous set Repeat request DEACTIVE Deactivate SyncMan
75. 0x0900 NOTE E g if port 0 is open this register reflects the Receive Time Port 0 as a 64 Bit value R18UZ0003EJ0301 Page 104 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 2 3 System Time Offset register DC SYS TIME OFFSET This register is used to indicate difference between local time and System Time 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address 400E 0920H DC SYS Initial Value TIME SYSTIMOFST 0000 0000 OFFSET 0000 0000H ECAT RW RW RW RW RW RW RW RW RW RW RW RV RW RW RV RW RW RW RAW RW RW RAW RW RW RAW RW RW RAW RW R W RW R W PDI R RR RR RR RR RR RR RR RR RRR RR RR RR RRR R RR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 21 0 SYSTIMOFST Bit position Function 63 0 SYSTIMOFST Difference between local time and System Time Offset is added to the local time 6 20 2 4 System Time Delay register DC SYS TIME DELAY This register indicates propagation delay between Reference Clock and the ESC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 10 Address 400E 0928H DC SYS Initial Value TIME SYSTIMDLY 0000 0000H DELAY ECAT RW RW RW RW RW RW RW RW RW R W RW RW RW R W RW RW RW R W R W RW R W R W RW RW R W R W RW RW R W R W RW RW PDI R R RR RR RR RR RR RR RR RR RR RR ARR RR RR RR RR Bit position Bit name Fun
76. 1 m 0 7 2 Register can only be written if SyncManager is disabled 0x6 0 0 R18UZ0003EJ0301 Dec 25 2014 Page 98 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 19 4 SyncManager Status m register SMm STATUS This register indicates the status of SyncManager 7 5 4 3 2 1 0 Address Initial Value a SMm u E 5 Ge 400E 0805H sid STATUS fra TE ei T 0008H m 2 I ECAT R R R R 0 R R PDI R R 0 R R Bit position Bit name Function 7 WRBUF Write buffer in use opened 6 RDBUF Read buffer in use opened 5 4 BUFFERED Buffered mode buffer status last written buffer 00 1 buffer 01 2 buffer 10 3 buffer 11 no buffer written Mailbox mode reserved 3 MAILBOX Mailbox mode mailbox status 0 Mailbox empty 1 Mailbox full Buffered mode reserved 1 INTRD Interrupt Read 1 Interrupt after buffer was completely and successful read 0 Interrupt cleared after first byte of buffer was written 0 INTWR Interrupt Write 1 Interrupt after buffer was completely and successfully written O Interrupt cleared after first byte of buffer was read Note m 0 7 R18UZ0003EJ0301 Page 99 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 19 5 SyncManager Activate m register SMm ACT This register is used to activate SyncManager 7 6 Address Initial Value e SMm lt 400E 0806H 2 re 0
77. 10 01010101010101010 10 1015 LI geo E lt x CO R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 000 0 0 0 0 RW Bit position Function CATRST Reset EtherCAT 0 during reset 1 release reset R18UZ0003EJ0301 Page 52 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 7 ESC Information Register 6 7 1 Type register TYPE This register indicates the type of the EtherCAT Slave Controller 7 6 5 4 3 2 1 0 Address Initial Value TYPE TYPE 400E 0000H AOH ECAT R R R R R R R R PDI R R R R R R R R Bit position Bit name Function TYPE Type of the EtherCAT Slave Controller 6 7 2 Revision register REVISION This register indicates the revision of the EtherCAT Slave Controller 7 6 5 4 3 2 1 0 Address Initial Value REVISION REV 400E 0001H 01H ECAT R R R R R R R R PDI R R R R R R R R Bit position Function Revision of the EtherCAT Slave Controller 6 7 3 Build register BUILD This register indicates the build number of the EtherCAT Slave Controller 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value BUILD BUILD 400E 0002H 0000H ECAT R R R R R R R R R R R R R R R R PDI R R R Bit position Function BUILD Build number of the EtherCAT Slave Controller R18UZ0003EJ0301 Page 53 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 7 4 FMMUS
78. 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value ao SMLEN 400E 0802H LEN 0008H m 0000H ECAT RAW RAW RAW RW RAW R W RAW R W RW RAW RAW RW RW RW RW RW PDI R R R R R R R R R R R R R R R R Bit position 15 0 SMLEN Number of bytes assigned to SyncManager shall be greater 1 otherwise SyncManager is not activated If set to 1 only Watchdog Trigger is generated if configured Note 1 m 0 7 2 Register can only be written if SyncManager is disabled 0x6 0 0 R18UZ0003EJ0301 Page 97 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 19 3 This register is used to control SyncManager SMm Ee O CONTROL cc Q ECAT 0 R W PDI 0 R Bit name WDTRGEN Bit position HL lt x Q O Si oO e o RAW RM RW RW R R R R Watchdog Trigger Enable 0 Disabled 1 Enabled 6 EtherCAT Slave Controller function SyncManager Control m register SMm CONTROL 1 0 Address Initial Value a 400E 0804H OO 00H 0008H m LU D e RAW RAW R R Function IRQPDI IRQECAT Interrupt in PDI Event Request Register 0 Disabled 1 Enabled Interrupt in ECAT Event Request Register 0 Disabled 1 Enabled Direction 00 Read ECAT read access PDI write access 01 Write ECAT write access PDI read access 10 Reserved 11 Reserved OPEMODE Operation Mode 00 Buffered 3 buffer mode 01 Reserved 10 Mailbox Single buffer mode 11 Reserved Note
79. 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value FMMUm FMMULEN 400E 0604H venu LEN 0010H m ECAT RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PI R R R R R R R R R R R R R R R R Bit position 15 0 FMMULEN Offset from the first logical FMMU Byte to the last FMMU Byte 1 e g if two bytes are used then this parameter shall contain 2 Note m 0 7 R18UZ0003EJ0301 Page 93 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 18 3 FMMU Logical Start bit m register FMMUm L START BIT This register is used to set logical starting bit shall be mapped 7 6 5 4 3 2 1 0 Address Initial Value FMMUm 0 LSTABIT 400E 0606H 00H L START BIT 0010H m ECAT 0 0 0 0 0 RW RW R W PDI 0 0 0 0 R R R 0 Bit postion Function 2 0 LSTABIT Logical starting bit that shall be mapped bits are counted from least significant bit 0 to most significant bit 7 Note m 0 7 6 18 4 FMMU Logical Stop bit m register FMMUm L_STOP_BIT This register is used to set last logical bit shall be mapped 7 6 5 4 3 2 1 0 Address Initial Value FMMUm m 0 LSTPBIT 400E 0607H 00H L STOP BIT 0010H m ECAT 0 0 0 0 0 RW R W R W PDI 0 0 0 0 R R R 0 sit postion Findon 2 0 LSTPBIT Last logical bit that shall be mapped bits are counted from least significant bit 0 to most significant bit 7 Note m 0 7 R18UZ0003EJ0301 Page 94 of 203 Dec 25 2014 R IN32M3 EC U
80. 1211109 8 7 6 5 A Address 400A 3420H Sapien ala She see d Initial value P 0 LO 9 101016101010101010 010 5 0000 0000H S S S S S S S S S S S o lo o o o o o o NAA A DEI CC EC EC rd Ec rd rd oc R W R W RW RW R W R W RW RW R W R W R W R W R W R W RI RW RW Specify whether to use the port as a port or for its alternate function 0 Port mode The Inactive level is input to the input pin of the alternate function Page 178 of 203 R IN32M3 EC User s Manual 8 Port function 8 3 4 Port function control registers PFC RPFC These registers are used to specify which alternate function is used These registers can be set in 1 bit units Address Initial 7 6 5 4 3 2 1 0 value PFCOB 1 PFC06 PFCO5 PFC04 PFC03 PFCO2 PFCO1 PFCO0 400A 3030H 00H PFC1B 0 0 0 0 0 PFC12 PFC11 PFC10 400A 3031H 00H PFC2B PFC27 PFC26 0 PFC24 PFC23 PFC22 0 0 400A 3032H 00H PFC3B PFC37 PFC36 PFC35 PFC34 PFC33 PFC32 0 0 400A 3033H OOH PFC4B PFC47 PFC46 PFC45 PFC44 PFC43 PFC42 PFC41 PFC40 400A 3034H o0H PFC5B PFC57 PFC56 0 PFC54 PFC53 PFC52 0 0 400A 3035H OOH PFC6B 0 0 0 0 0 0 0 0 400A 3036H OOHN99 PFC7B PFC77 PFC76 0 PFC74 PFC73 PFC72 0 PFC70 400A3037H 00H RPFCOB RPFCO7 RPFCO6 0 RPFCO04 0 RPFCO2 RPFCO1 RPECOO 400A 3430H 00H RPFC1B 0 0 0 0 0 0 0 0 400A 3431H 00H RPFC2B RPFC27 RPFC26 RPFC25 RPFC24 0 0 0 RPFC20 400A 3432H 00H RPFC3B 0 0 0 0 0 0 0 0 400A 3433H 00H
81. 18UZ0003EJ0301 Dec 25 2014 EtherCAT interrupt O10JOJO O 1O O1 O O1O0 JOJO O JO O O O10 JOJO O 1O O O Oo O0 O O OO O O Page 35 of 203 R IN32M3 EC User s Manual 4 Exception handling function 2 4 Connection Cause group INTCATSOF EtherCAT SOF interrupt INTCATEOF EtherCAT EOF interrupt INTBUFDMA Inter Buffer DMA transfer completion INTPHYO Ether PHY interrupto INTPHY1 Ether PHY interrupt1 INTETHMII Ether Mil management access completion interrupt 52 INTETHPAUSE Ether pause packet transmission completion 53 INTETHTX Ether transmission completion interrupt 54 INTETHSW Ether SWITCH interrupt 55 INTETHSWDLR Ether SWITCH DLR interrupt 56 INTETHSWSEC Ether SWITCH SEC interrupt 57 INTETHRXFIFO RX FIFO overflow 58 INTETHTXFIFO TX FIFO underflow 59 INTETHRXDMA Ether MACDMA reception completion 60 INTETHTXDMA Ether MACDMA transmission completion 61 INTMACDMARX receive frame successfully interrupt Oo o o O O Oo o o O O Oo o o O O Oo Oo O O O O ODO ODO O O Oo Oo O O O O ODO ODO O O O O O Oplo O O O FRM 62 INTHOSTIF External MPU I F interrupt 63 INTPZO INTPZ0 input 64 INTPZ1 INTPZ1 input 65 INTPZ2 INTPZ2 input 66 INTPZ3 INTPZ3 input 67 INTPZ4 INTPZ4 input 68 INTPZ5 INTPZ5 input 69 INTPZ6 INTPZ6 input 70 INTPZ7 INTPZ7 input INTPZ8 INTPZ8 inp
82. 2 2 2 ziz 2iziziziz 79079 a a a a a a a a a oc io ojo ojo R W R R R R R R R R R Bit position Bit name Function 31100 PINmn RPINIn Use to read the input level of the port pin Remark I 0to3 m Oto7 n Oto7 R18UZ0003EJ0301 Page 187 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 4 Available combinations of alternate functions 8 Port function The combinations of alternate functions that can be specified by using the port related registers are shown below 1 Pin nam Ports P00 to P77 1 3 PMCmn 0 port mode PMCmn 1 control mode PFCEmn 0 PFCEmn 1 PMmn 0 PMmn 1 PFCmn 0 PFCmn 1 PFCmn 0 PFCmn 1 output port input port POO POO output mode POO input mode INTPZO CATLEDRUN P01 PO1 output mode POT input mode INTPZ1 CATIRQ P02 P02 output mode PO2 input mode INTPZ2 CATLEDSTER PO3 P03 output mode PO3 input mode INTPZ3 CATLEDERR CCS MON5 P04 P04 output mode P04 input mode INTPZ4 CATLINKACTO CCS_MON6 P05 P05 output mode P05 input mode INTPZ5 CATLINKACT1 CCS_MON7 P06 P06 output mode PO6 input mode POLINKLEDZ CCS_MONO P07 PO7 output mode PO7 input mode P1LINKLEDZ CCS RESOUT P10 P10 output mode P10 input mode CATLATCH1 CATSYNC1 CCS REFSTB P11 P11 output mode P11 input mode CATLATCHO CATSYNCO CCS MON4
83. 2 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address 400E 09COH DC_ Initial Value LATCH1_ SYSTIME 0000 0000 TIME_POS 0000 0000H ECAT Rack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack PDI R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 1 0 SYSTIME ECAT R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack Risch R ack R ack R ack R ack R ack PDI R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack Black R ack R ack R ack R ack R ack R ack R ack R ack Black R ack R ack R ack R ack R ack Bit position Function 63 0 SYSTIME Register captures System time at the positive edge of the Latch1 signal Reading clears Latch1 Status OxO9AF 0 Note 1 Register bits 63 8 are internally latched ECAT PDI independently when bits 7 0 are read which guarantees rea
84. 3 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 17 MI Management Interface Registers 6 17 1 MII Management Control Status register MI CONT STAT This register is used to control MIT management interface and to indicate the status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value MILGONT elElololo z PHYOFFSET l STAT lt E 400E 0510H 0006H gt LLI O gt j KE KSE IR H 5 2 u Q o Ec mo O SSES ECAT R R RW 0 0 0 RW RW R R R R RW PDI R R RW 0 0 0 RW RW R R R R R Bit position Bit name Function 15 BUSY Busy 0 MI control state machine is idle 1 MI control state machine is active 14 CMDERR Command error 0 Last Command was successful 1 Invalid command or write command without Write Enable Cleared with a valid command or by writing 00 to Command register bits 9 8 13 READERR Read error 0 No read error 1 Read error occurred PHY or register not available Cleared by writing to this register 9 8 COMMAND Command register Write Initiate command Read Currently executed command Commands 00 No command MI idle clear error bits 01 Read 10 Write Others Reserved invalid commands do not issue 7 3 PHYOFFSET PHY address offset 2 MILINK MI link detection link configuration link detection registers 0x0518 0x051B 0 Not available 1 MI link detection active 1 PDICTRL Management Interface can be controlled by PDI register
85. 32 33 or more More than 64 65 or more 0 1 2 3 4 5 6 7 Set the condition to determine the link down or interrupt occurrence by the BER WINDOW 1 0 2ms 2 0 4ms 3 0 8 ms 15 3 2 sec Set the width of the window of BER counter BER_COUNT R18UZ0003EJ0301 Dec 25 2014 Count value of bit errors in the window time before current Page 149 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 17 Register 24 FEQ monitor Register Set FEQ monitor function Ethernet PHY and show the results PHY Address 18H MR24 FEQ DELTA FEQ VAL Initial Value 0000H RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Position Bit Name Function FEQ DELTA Set the amount of change in FEQ2 factor allowed for the value of the reference Write that has been latched When BER CNT LINK EN bit of register 23 is 1 if the value of FEQ2 exceeds this value FEQ interrupt is generated and the link is down FFFF Disable FEQ monitor function and continue to latch on the FEQ2 factor ongoing FFFE The current reference value can be read from this register The value of FEQ DELTA does not change Other Set the threshold of amount of change FEQ monitor function starts to work with setting this value FEQ VAL Shows 17 2 bit of FEQ2 coefficient latched as a reference when write FFFE to Read FEQ DELTA Others Current FEQ2 coefficient R18UZ0003EJ0301 Page 150 of 203 Dec
86. 32M3 EC User s Manual 6 16 3 6 EtherCAT Slave Controller function EEPROM Control Status register EEP CONT STAT This register is used to control EEPROM access and indicate the status EEP CONT STAT ECAT PDI 2 7 ACKCMDERR Rad a R R D 7 WRENERR Bit name BUSY Bit position 15 14 WRENERR Address Initial Value 400E 0502H 0000H RAW RAW RW R W RAW RAW m 7 LOADSTA Function Busy 0 EEPROM Interface is idle 1 EEPROM Interface is bus Error Write Enable amp 2 0 No error 1 Write Command without Write enable 13 ACKCMDERR Error Acknowledge Command 0 No error 1 Missing EEPROM acknowledge or invalid command 12 LOADSTA EEPROM loading status 0 EEPROM loaded device information ok 1 EEPROM not loaded device information not available EEPROM loading in progress or finished with a failure 11 CKSUMERR Checksum Error at in ESC Configuration Area 0 Checksum ok 1 Checksum error 10 8 COMMAND Command register2 0r2 Write Initiate command Read Currently executed command Commands 000 No command EEPROM idle clear error bits 001 Read 010 Write 100 Reload Others Reserved invalid commands do not issue PROMSIZE Selected EEPROM Algorithm 0 1 address byte 1KBit 16KBit EEPROMs 1 2 address bytes 32KBit 4 MBit EEPROMs READBYTE Supported number of EEPROM read bytes 0 4 Bytes 1 8
87. 3440H RT port pin input register 0 8 bits RPINOB 400A 3450H RT port pin input register 1 8 bits RPIN1B 400A 3451H RT port pin input register 2 8 bits RPIN2B 400A 3452H RT port pin input register 3 8 bits RPIN3B 400A 3453H RT port pin input register 0 16 bits RPINOH 400A 3450H RT port pin input register 2 16 bits RPIN2H 400A 3452H RT port pin input register 0 32 bits RPINOW 400A 3450H R18UZ0003EJ0301 Dec 25 2014 Page 168 of 203 R IN32M3 EC User s Manual Register name Symbol 8 Port function Address 6 6 Buffer function change register P1L DRCTLP1L 4001 0228H Buffer function change register P1H DRCTLP1H 4001 022CH Buffer function change register P3L DRCTLP3L 4001 0238H Buffer function change register P3H DRCTLP3H 4001 023CH Buffer function change register P4L DRCTLP4L 4001 0240H Buffer function change register P4H DRCTLP4H 4001 0244H Buffer function change register P5L DRCTLP5L 4001 0248H Buffer function change register P5H DRCTLP5H 4001 024CH Buffer function change register P7H DRCTLP7H 4001 025CH Buffer function change register RPOL DRCTLRPOL 4001 0260H Buffer function change register RPOH Buffer function change register RP1L DRCTLRPOH DRCTLRP1L 4001 0264H 4001 0268H Buffer function change register RP1H DRCTLRP1H 4001 026CH Buffer function change register RP2L DRCTLRP2L 4001 0270H Buffer function change re
88. 57 Ethernet PHY function setting register ssrrnvrrnvrrnvrrnrvrnevvrrveravvranvrnnnrarneevrarnnesveevvnevvennvernersnsvsvsversserassrasvaesnen 158 List Of repisters eessen EE ee hint vato 158 Contents 5 7 5 2 Ethernet PHY operation mode control register PHY MI 159 7 5 3 Ethernet PHY power up status register PHY DUS 160 8 PON UOO a e Lee a nr 161 8 1 lar i E E EEEE or E AET 161 8 2 Port configuration sse na rn rs pk pn eee kn E a ete ap ee 162 8 3 REpIStoN s sus sama SN A o AA KA A I GR ses Iu Auto l 164 8 3 1 Pottriegisters E RP ss se soni snb da pontosan doodo 170 8 3 2 Port mode r gisters PM REM sss so AA SAN raet 173 8 3 3 Port mode control register PMC RPMO rrrsnrnnrnrnvennvnrnrnvennnnernvennnnenrasennnnenrsvennnnsnrasennenenrasennensnrssenner 176 8 3 4 Port function control registers PFC RPFC A 179 8 3 5 Port function control expansion registers PFCE RPFCE AA 182 8 3 6 Port pin input registers PIN RPIN EERSTEN EERSTEN seeSava sive lo poso gedbbasveboseh sedebeensceosspessge deeds 185 8 4 Available combinations of alternate Tunctons 188 8 5 Buffer function change registers DRCTLP AA 192 8 5 1 Port 1 buffer function change registers DRCTLPIL DRCTLPID 193 8 5 2 Port 3 buffer function change registers DRCTLP3L DRCTLDOAH eee cece cece creeeeteeeeeeeeeeees 194 8 5 3 Port 4 buffer function change registers DRCTLP4L DRCTLDAH A 195 8 5 4 Port 5 buffer function change registers DRCTLPSL
89. 66 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 400A 3026H o0Hlge PMC7B PMC77 PMC76 PMC75 PMC74 PMC73 PMC72 PMC71 PMC70 400A 3027H 00H RPMCOB RPMCO7 RPMC06 RPMCO5 RPMC04 RPMCO03 RPMCO2 RPMCO1 RPMCOO 400A 3420H oof RPMC1B RPMC17 RPMC16 RPMC15 RPMC14 RPMC13 RPMC12 RPMC11 RPMC10 400A 3421H OOH RPMC2B RPMC27 RPMC26 RPMC25 RPMC24 RPMC23 RPMC22 RPMC21 RPMC20 400A 3422H o0H RPMC3B RPMC37 RPMC36 RPMC35 RPMC34 RPMC33 RPMC32 RPMC31 RPMC30 400A 3423H oni Bit position Function 7to0 PMCmn Specify whether to use the port as a port or for its alternate function RPMCIn 0 Port mode The Inactive level is input to the input pin of the alternate function 1 Alternate function control mode Figure 8 8 Port mode control registers in 8 bit notation Note The initial value depends on the pin status For details see 2 2 Port status Remark I 0t0o3 m 0t07 n 0to7 R18UZ0003EJ0301 Page 176 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address PMCOH PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC PMC 400A 3020H 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW lInitial value OOOOH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address PMC2H PMC PMC PMC
90. 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 80 Bendemeer Road Unit 06 02 Hyflux Innovation Centre Singapore 339949 Tel 65 6213 0200 Fax 65 6213 0300 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jin Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2013 2014 Renesas Electronics Corporation All rights reserved
91. 7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 121110 9 876 543210 Address BASE 023CH Bit name 0 1 Initial value 0000 9999H IOLP371 IOLP370 PUIOP36 PUIOP35 PUIOP34 Function Reserved Be sure to write 0 to these bits If read 0 is returned PUIOP3n PDIOP3n Specify whether to connect a pull up or pull down resistor to the P37 to P30 pins Connection of a pull up or pull down resistor to the P37 to P30 pins Do not connect a pull up or pull down resistor Connect a pull down resistor Connect a pull up resistor Setting prohibited IOLP371 IOLP370 Specify the driving capability of the P37 pin IOL1 IOLO Driving capability of P37 pin 12 mA Other than above Setting prohibited Remark n 7t00 R18UZ0003EJ0301 Dec 25 2014 Page 194 of 203 R IN32M3 EC User s Manual 8 Port function 8 5 3 Port 4 buffer function change registers DRCTLP4L DRCTLP4H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 10 Address BASE 0240H FIL Y F SIS DRCTLP4L a a eg a a a a iti 0 0 0 0 0 0 olo 5 515 Slo Initial value FL alice as 0000 9999H RW 0 0 0 0 0 0 0 0 O O O O O 0 O 0 RWRW O 1 RWRW O 1 RWRW O 1 RWRW O 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 43 2 1 0 Address BASE 0244H G F LL ee IT DRCTLP4H a a a a a a a a iti aroge oo e roe eeo SIS SS slalo sd Initial value al rea a IN 212 as
92. 7 n 0to7 R18UZ0003EJ0301 Page 173 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address PMOH PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PMO7 PMOG PMOS PM04 PM03 PM02 PM01 PMOO0 400A 3010H RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RA lInitial value FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address PM2H PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 400A 3012H RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Rw lInitial value FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address PM4H PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM47 PM46 PM45 PM44 PM43 PM42 PM41 400A 3014H RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RA Initial value FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address PM6H PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 PM67 PMSG PMSS PM64 PM63 PM62 PM61 400A 3016H RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RAW Initial value FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address RPMOH RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM 400A 3410H 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Rw lInitial value FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address RPM2H RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM RPM 400A 3412H 37 36 35 34 33 32 31 3
93. AW R W RAW RAW RW PDI RI W R W R W RAW RAW RAW RW R W RAW RAW RAW RW RAW RW RW RW RAW RAW RAW RAW RAW RAW R W RAW RAW RAW R W RAW R W R W RW RW Bit position Function SYNC1CYC Time between SYNC1 pulses and SYNCO pulse in ns Note Write to this register depends upon setting of 0x0980 0 6 20 5 Latch In Unit Registers 6 20 5 1 LatchO Control register DC LATCHO CONT This register is used to control the edge function of LatchO input signal 7 6 5 4 3 2 DC LATCHO 0 CONT 0 0 0 0 0 0 ECAT PDI 0 0 0 0 0 0 Address Initial Value e 400E 09A8H 00H I NEGEDGE Ke POSEDGE 2 32 2 3 Bit position Bit name Function NEGEDGE LatchO negative edge 0 Continuous Latch active 1 Single event only first event active POSEDGE LatchO positive edge 0 Continuous Latch active 1 Single event only first event active Note Write to this register depends upon setting of 0x0980 4 R18UZ0003EJ0301 Page 114 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 5 2 Latch1 Control register DC LATCH1 CONT This register is used to control the edge function of Latch1 input signal 7 6 5 4 3 2 DC LATCH1 CONT 0 0 0 0 0 0 ECAT PDI 0 0 0 0 0 0 CH Address Initial Value 400E 09A9H 00H NEGEDGE POSEDGE 2 2 3 m Bit position Bit name Function NEGEDGE Latch
94. D 5 a C O aa S D 0000 9999H W R W RW R W R W R W R W R W R W R W R W R W R W R W R W R W PUIORP1n PDIORP1n Specify whether to connect a pull up or pull down resistor to the RP17 to RP10 pins Do not connect a pull up or pull down resistor Connect a pull down resistor Connect a pull up resistor Setting prohibited IOLRP1nt1 IOLRP1nO Specify the driving capability of the RP17 to RP10 pins IOL1 IOLO Driving capability of RP17 to RP10 pins 0 1 6 mA recommended 1 1 12mA Other than above Setting prohibited Remark n 7toO R18UZ0003EJ0301 Dec 25 2014 Page 198 of 203 R IN32M3 EC User s Manual 8 Port function 8 5 7 Real time port 2 buffer function change registers DRCTLRP2L DRCTLRP2H DRCTLRP2L DRCTLRP2H Bit position Bit name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W 000000000000 00 0 0 Ri 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1413 12 1110 9 8 7 6 5 43 2 Function Reserved Be sure to write 0 to these bits If read 0 is returned R W 0000000000 0 0 0 0 0 O RW RW RW RAW RW RW RW RW RW RW RW RAW R W RW RW RW 1 0 Address gig 5 NIN 5 Q zle BASE 0270H E E E E D E ala Initial value Se alle edel 5la 5la a a a G e a a S Q a Q Q 0000 5559H 151413 121110 9 8 765 43 2 10 Address SINIs el isigg Als glas ig BASE 0274H ce E SS EAS ce foe S EEL initial value SSES e aS S
95. D COUNT FIL DEPTH This register is used to set filter depth for averaging the clock period deviation 7 6 5 4 3 2 1 0 Address Initial Value DC SPEED COUNT FIL 0 CLKPERDEP 400E 0935H OCH DEPTH ECAT 0 0 0 0 R W R W R W R W PDI 0 0 0 R R R R 0 Bit postion Function 3 0 CLKPERDEP Filter depth for averaging the clock period deviation A write access resets the internal speed counter filter 6 20 3 Cyclic Unit Control Registers 6 20 3 1 Cyclic Unit Control register DC CYC CONT This register is used to control cyclic unit 7 1 0 Address Initial Value DC_CYC_ 5 0 O 400E 0980H 00H CONT Q gt VD ECAT 0 0 RW PDI 0 0 R R 0 0 0 R Bit position Bit name Function LATCH1 Latch In unit 1 0 ECAT controlled 1 PDI controlled NOTE Latch interrupt is routed to ECAT PDI depending on this setting LATCHO Latch In unit 0 0 ECAT controlled 1 PDI controlled NOTE Always 1 PDI controlled if System Time is PDI controlled Latch interrupt is routed to ECAT PDI depending on this setting SYNCOUT SYNC out unit control 0 ECAT controlled 1 PDI controlled R18UZ0003EJ0301 Page 108 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 20 4 6 20 4 1 6 EtherCAT Slave Controller function SYNC Out Unit Registers Activation register DC ACT This register is used to activate Sync Out Unit 7 6 Address Initial Value LLI w Lu 5 w E DC ACT 2 5 8 5 5 400E 0981H 00H L
96. Do not connect a pull up or pull down resistor Connect a pull down resistor Connect a pull up resistor Setting prohibited IOLP5n1 Specify the driving capability of the P51 to P50 pins lt R gt IO Pin IOL1 IOLO Driving capability of P51 to P50 pins 0 1 6 mA recommended 1 1 12mA Other than above Setting prohibited Remark n 7to0O R18UZ0003EJ0301 Page 196 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 8 5 5 Real time port 0 buffer function change registers DRCTLRPOL DRCTLRPOH DRCTLRPOL DRCTLRPOH Bit position Bit name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W 00000000000 0 0 0 0 OR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1413 12 1110 9 8 7 6 5 43 2 Function Reserved Be sure to write 0 to these bits If read 0 is returned R W 000000000 0 00 0 0 0 O RW R W RW RAW RW RW RW RW RW RW RM RW RW RW RW RW 1 0 Address gig 5 ajg 5 gie IS BASE 0260H E E T E E a E E SIS Initial value lie S 9 E S 9 E E 5la 5la 5 a aja Ge e a a S OjO a a O O 0000 9999H 1514131211109 8 765 43 2 10 Address S S5 clelS SisigiSlSlsiglS Sigig BASE 0264H e Ele EEE SEE EEE ES Initial value 6 8414 8618 6 8 816 e 5la Sla 5 a 5 a Slel i ls les les lei 0000 9999H W R W R W R W R W R W R W R W R W R W RAW R W R W R W R W R W PUIORPOn PDIORPOn Specify whether to connect a pull up or pull down res
97. E FX Transmit data PO FX EN OUT PHYO 100BASE FX FX Enable Indication 1 100BASE FX mode P1_FX_EN_OUT PHY1 100BASE FX FX Enable Indication 1 100BASE FX mode Remark In MDI X mode the input and output attributes of TXP TXN and RXP RXN are reversed R18UZ0003EJ0301 Page 6 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 Signals by function 2 Other Signals Pin Name I O Function Shared Active Level during reset amp Port Level after reset POLINKLEDZ O SIP PHYO Link status LED port P06 Low Hi Z P1LINKLEDZ O SIP PHY1 Link status LED port P07 Low ETHSWSECOUT O EtherSwitch Event par 1sec output port P24 High Hi Z PODUPLEXLEDZ O SIP PHYO half duplex status LED port P70 With internal pull up SE resistor 0 full duplex 1 half duplex POSPEED100LEDZ O SIP PHYO 100 BASE status LED portee P72 Low POSPEED10LEDZ O SIP PHYO 10 BASE status LED port Note P73 Low P1DUPLEXLEDZ O SIP PHY1 half duplex status LED port P74 Note2 0 full duplex 1 half duplex P1SPEED100LEDZ O SIP_PHY1 100 BASE status LED port P76 Low P1SPEED10LEDZ O SIP PHY1 10 BASE status LED port Note P77 Low POACTLEDZ O SIP PHYO RX status LED port RPO2 Low P1ACTLEDZ O SIP PHY1 TX status LED port RP04 Low R18UZ0003EJ0301 Page 7 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 1 2 Pin Name EtherCAT Slave Controller Signal Function Shared Ac
98. EE RE Initial value S S EE E amp E SS Sla 5la 5 a 5 8 ala O Ola les les lei 0000 9999H W R W R W R W R W R W R W RW R W R W RAW R W R W R W R W R W PUIORP3n PDIORP3n Specify whether to connect a pull up or pull down resistor to the RP37 to RP30 pins Do not connect a pull up or pull down resistor Connect a pull down resistor Connect a pull up resistor Setting prohibited IOLRP3n1 IOLRP3n0 Specify the driving capability of the RP37 to RP30 pins IOL1 IOLO Driving capability of RP37 to RP30 pins 0 1 6 mA recommended 1 1 12mA Other than above Setting prohibited Remark n 7to0 R18UZ0003EJ0301 Dec 25 2014 Page 200 of 203 R IN32M3 EC User s Manual 8 Port function 8 6 Operation of port functions The port operation differs depending on the I O mode setting as shown below 8 6 1 Reading and writing via I O ports 1 In output mode If a value is written to port register n Pn or RPn the value is written to that port s output latch Pn or RPn The value of the output latch is output from the pin The value written to the output latch is held until another value is written The value of the output latch Pn or RPn can be read by reading port register n Pn or RPn To directly read the pin level read port pin input register n PINn or RPINn 2 In input mode If a value is written to port register n Pn or RPn the val
99. EtherCAT Slave Controller function 2 ENHLINKD Enhanced Link detection 0 Deactivated for all ports 1 Activated for at least one port NOTE EEPROM value is only taken over at first EEPROM load after power on or reset 1 PDIWDST PDI Watchdog Status 0 Watchdog expired 1 Watchdog reloaded 0 PDIOPE PDI operational EEPROM loaded correctly 0 EEPROM not loaded PDI not operational no access to Process Data RAM 1 EEPROM loaded correctly PDI operational access to Process Data RAM Note Reading DL Status register from ECAT clears ECAT Event Request 0x0210 2 R18UZ0003EJ0301 Dec 25 2014 Page 65 of 203 R IN32M3 EC User s Manual 6 11 Application Layer Registers 6 11 1 AL Control register AL_CONTROL 6 EtherCAT Slave Controller function This register is used to initiate State Transition of the Device State Machine and to acknowledge error indication 6 0 ECAT 0 0 PDI 0 0 0 0 0 0 0 0 0 0 Bit position Bit name 4 ERRINDACK Error Ind Ack 1 Ack of Error Ind in AL status register 15 14 13 12 11 10 9 8 5 TL DR 0 0 0 0 0 0 0 0 0 No Ack of Error Ind in AL status register Address 4 3 2 1 0 Initial Value 400E 0120H 0001H x O EN G ra or Lu INISTATE RAW RAW RAW RAW RAW R R R R R clear clear clear clear clear Function 3 0 INISTATE 1 Request Init State 3 Request Bootstrap State 2 Request Pre Operational State
100. H 400F AOOOH 400F 8400H CC Link Master memory area PATO 256byte 400F 9FFFH Reserved CC Link Master memory area 8Kbyte 400F 839FH 400F 8000H 400F 8000H Reserved Figure 3 4 Memory map CC Link Master area Caution1 CC Link Master shows function block of Intelligent station CC Link Master memory area transmit buffer1 924byte Caution2 CC Link Slave shows function block of remote device station R18UZ0003EJ0301 Dec 25 2014 Page 32 of 203 R IN32M3 EC User s Manual 3 Memory Maps MCU area LE Pere Data RAM area 512Kbyte 18 0000H 17 FFFFH Reserved Internal AHB area OF BOOOH area 4Kbyte OF AFFFH CC Link Master UO Reserved 10 0000H OF FFFFH HOSTIF registers area OF FFOOH 256byte OF C000H c OF BFFFH CC Link Slave OC link SEVE area 4Kbyte CC Link Master UO area 4Kbyte CC Link Master memory area 8Kbyte OF AOOOH area 4Kbyte 2Mbyte OF 9FFFH GG Link Master momory OF 8000H area 8Kbyte Reserved OE 3000H OE 2FFEH Ether CAT area Reserved Ether CAT area 8 125Kbyte Reserved OE OF80H 8 125Kbyte Reserved Ge System registers area OD 0000H 64Kbyte OG FFFFH AHB Peripheral area OC 3000H Upper 52Kbyte OC 0000H Reserved OB FFFFH Instruction RAM area 768Kbyte 00 0000H AHB Peripheral area Upper 52Kbyte System registers area
101. Hi Z Low With internal pull up resistor A2 A20 O HA2 HA20 Hi Z A21 A27 O RP21 With Hi Z RP27 internal With Do D15N9 VO Data bus port HDO HD15 pull down internal resistor pull down resistor D16 D31 9 VO HD16 HD3 RP30 Hi Z 1 RP37 With internal pull up RP10 resistor RP17 RDZ O Read strobe output port HRDZ Low Hi Z High WRSTBZ O Write strobe output port HWRSTBZ Low With WRZO WRZ1 O Effectively Byte lane strobe HWRZ0 Low internal BENZO BENZ1 output port HWRZ1 pull up HBENZO resistor HBENZ1 WRZ2 WRZ3 O HWRZ2 RPO6 BENZ2 BENZ3 HWRZ3 RPO7 HBENZ2 HBENZ3 WAITZ Wait signal input port HWAITZ P41 Low Hi Z WAITZ1 WAITZ3 P45 P With internal pull up Neige 47 resistor BCYSTZ ADVZ O Address valid output port HBCYSTZ RP20 Low Hi Z Note3 With internal pull up resistor Remark External Memory Interface Signal expects BUSCLK is an input signal while the internal reset signal HRESETZ is active R18UZ0003EJ0301 Dec 25 2014 Page 9 of 203 R IN32M3 EC User s Manual 2 Signals by function Note1 When using synchronous burst access MEMC this port is shared with Address port when ADMUXMODE is high Note2 This port is available only when using synchronous burst access MEMC Note3 This port functions as BCYSTZ when using asynchronous SRAM MEMC it functions as ADVZ when using synchronous burst access MEMC R18UZ0003EJ0301 Page 10 of 203 Dec 25 2014 R I
102. IN2 TOUT2 Remark m 0to7 n 0to7 R18UZ0003EJ0301 Dec 25 2014 Page 189 of 203 R IN32M3 EC User s Manual 8 Port function 3 3 Pin PMCmn 0 port mode PMCmn 1 control mode nam PFCEmn 0 PFCEmn 1 e PMmn 0 PMmn 1 PFCmn 0 PFCmn 1 PFCmn 0 PFCmn 1 output port input port P60 P60 output mode P60 input mode SCLO P61 P61 output mode P61 input mode SDAO P62 P62 output mode P62 input mode RTDMAREQZ CCM_MDINO P63 P63 output mode P63 input mode RTDMAACKZ CCM_MDIN1 P64 P64 output mode P64 input mode RTDMATCZ CCM_MDIN2 P65 P65 output mode P65 input mode DMAREQZO CCM_MDIN3 P66 P66 output mode P66 input mode DMAACKZO P67 P67 output mode P67 input mode DMATCZO P70 P70 output mode P70 input mode CSICS00 PODUPLEXLEDZ CCS STATION NO 0 CCM SNINO P71 P71 output mode P71 input mode CSICSO1 CCS STATION NO 1 CCM SNIN1 P72 P72 output mode P72 input mode CSICS10 POSPEED100LEDZ CCS STATION NO 2 CCM SNIN2 P73 P73 output mode P73 input mode CSICS11 POSPEED10LEDZ CCS STATION NO 3 CCM SNIN3 P74 P74 output mode P74 input mode INTPZ12 P1DUPLEXLEDZ CCS STATION NO 4 CCM SNIN4 P75 P75 output mode P75 input mode INTPZ13 CCS STATION NO 5
103. INO4 PINO3 PINO2 PINO1 PINOO 400A 3050H Undefined PIN1B PIN17 PIN16 PIN15 PIN14 PIN13 PIN12 PIN1 1 PIN10 400A 3051H Undefined PIN2B PIN27 PIN26 PIN25 PIN24 PIN23 PIN22 PIN21 PIN20 400A 3052H Undefined PIN3B PIN37 PIN36 PIN35 PIN34 PIN33 PIN32 PIN31 PIN30 400A 3053H Undefined PIN4B PIN47 PIN46 PIN45 PIN44 PIN43 PIN42 PIN41 PIN40 400A 3054H Undefined PINSB PINS7 PIN56 PIN55 PINS4 PIN53 PIN52 PINS1 PIN50 400A 3055H Undefined PIN6B PIN67 PIN66 PIN65 PIN64 PIN63 PIN62 PIN61 PIN60 400A 3056H Undefined PIN7B PIN77 PIN76 PIN75 PIN74 PIN73 PIN72 PIN71 PIN70 400A 3057H Undefined RPINOB RPINO7 RPINO6 RPINOS RPINO4 RPINO3 RPINO2 RPINO1 RPINOO 400A 3450H Undefined RPIN1B RPIN17 RPIN16 RPIN15 RPIN14 RPIN13 RPIN12 RPIN11 RPIN10 400A 3451H Undefined RPIN2B RPIN27 RPIN26 RPIN25 RPIN24 RPIN23 RPIN22 RPIN21 RPIN20 400A 3452H Undefined RPIN3B RPIN37 RPIN36 RPIN35 RPIN34 RPIN33 RPIN32 RPIN31 RPIN30 400A 3453H Undefined Bit Bit position Bitname name Funn 7to0 PINmn Use to read the input level of the port pin RPINIn Figure 8 17 Port pin input registers in 8 bit notation Remark 0to3 m 0to7 n 0to7 R18UZ0003EJ0301 Page 185 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function Address PINOH 400A 3050H 14 11 PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN 17 16 15 14 13 12 11 10 07 06 05 04 03 02 01 00
104. L E lt lt a ke oc o O 9 O lt E E E sa UI EL x 5 gt Q E N MI x VD ECAT RW R W R W R W R W R W R W R W PDI R W R W R W R W R W R W R W R W Bit position Bit name Function 7 DBGPULSE SyncSignal debug pulse Vasili bit 0 Deactivated 1 Immediately generate a single debug ping on SYNCO and SYNC1 according to 0x0981 2 1 This bit is self clearing always read 0 6 NEARFUTURE Near future configuration approx STARTTIME 0 DC width future 2 ns or 2 ns 1 2 1 sec future 2 ns Start Time plausibility check 0 Disabled SyncSignal generation if Start Time is reached 1 Immediate SyncSignal generation if Start Time is outside near future see 0x0981 6 EXTSTARTTIME Extension of Start Time Cyclic Operation 0x0990 0x0993 0 No extension 1 Extend 32 bit written Start Time to 64 bit AUTOACT Auto activation by writing Start Time Cyclic Operation 0x0990 0x0997 0 Disabled 1 Auto activation enabled 0x0981 0 is set automatically after Start Time is written SYNC1 generation 0 Deactivated 1 SYNC1 pulse is generated 1 SYNCO SYNCO generation 0 Deactivated 1 SYNCO pulse is generated 0 SYNCACT Sync Out Unit activation 0 Deactivated 1 Activated NOTE Write 1 after Start Time was written Note Write to this register depends upon setting of 0x0980 0 R18UZ0003EJ0301 Dec 25 2014 Page 109 of 203 R IN32M3 EC User s Manu
105. N32M3 EC User s Manual 2 1 4 Pin Name External MPU Interface Signals Function Shared Signal Shared port 2 Signals by function Level during reset amp Level after reset HBUSCLK l Bus clock for Host MPU INTPZ11 P43 Hi Z output port With internal pull up HCSZ Chip select signal input port CSZ0 Low resistor HPGCSZ l Pogrom mode Chip select CSZ1 P44 Low signal input port HWAITZ O Wait signal output port WAITZ P41 Low HA1 Address input port Al P40 Hi Z With internal pull up resistor HA2 HA20 l A2 A20 Hi Z HDO HD15 I O Data bus port DO D15 With internal pull down resistor HD16 HD31 VO D16 D31 RP30 Hi Z RP37 With internal pull up RP10 resistor HRDZ Read strobe input port RDZ HWRSTBZ Write strobe output port WRSTBZ HWRZO HWRZ1 HBENZO HBENZ1 HWRZ2 HWRZ3 HBENZ2 HBENZ3 Effectively Byte lane strobe input port WRZO WRZ1 BENZO BENZ1 WRZ2 WRZ3 BENZ2 BENZ3 Hi Z With internal pull up resistor HERROUTZ HBCYSTZ Error interrupt output port Bus cycle input port SLEEPING BCYSTZ ADVZ Hi Z With internal pull up resistor Caution When you use asynchronous mode please input Low into a HBUSCLK pin Remark External MPU interface signals operate as an External MPU interface durinug reset R18UZ0003EJ0301 Dec 25 2014 Page 11 of 203 R IN32M3 EC User s Manual 2 Sign
106. NC1PULSE SYNC1PULSE System time of next SYNC1 pulse in ns Function 6 20 4 8 SYNCO Cycle Time register DC SYNCO CYC TIME This register is used to set cycle time of SYNCO pulse 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 1 0 Address 400E 09A0H DC SYNCO Initial Value SYNCOCYC CYC TIME 0000 0000H ECAT R W R W R W RAW RAW RAW RAW RAW RAW RW RAW R W RAW R W R W R W RAW R W RAW RAW RAW RAW RAW RAW R W RAW R W RAW RAW RAW R W RW PDI RAW RAW R W R W RAW R W R W R W RAW R W R W R W RAW R W R W R W R W RAW R W RAW RAW RAW R W RAW R W RAW R W RAW R W R W RW RAW Bit position Bit name Function SYNCOCYC Time between two consecutive SYNCO pulses in ns 0 Single shot mode generate only one SYNCO pulse Note Write to this register depends upon setting of 0x0980 0 R18UZ0003EJ0301 Page 113 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 4 9 SYNC1 Cycle Time register DC SYNCi CYC TIME This register is used to set time between SYNCI pulse and SYNCO pulse 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 21 0 Address 400E 09A4H DC SYNC1 Initial Value 7 SYNC1CYC CYC_TIME 0000 0000H ECAT RI W R W R W RAW RAW RAW DW R W RAW RW RAW R W RAW RAW RAW RW RAW RAW RAW RAW RAW RAW R W RAW RAW RAW RAW R
107. NO area 128Kbyte System register area 64Kbyte Reserved Watchdog timer 16byte Reserved IIC1 64byte Reserved IICO 64byte Reserved UART1 128byte Reserved UARTO 128byte CSI 256byte Cem 256byte Timer TAUJ 256byte Figure 3 2 Memory map APB Peripheral registers area R18UZ0003EJ0301 Dec 25 2014 Page 31 of 203 R IN32M3 EC User s Manual 3 Memory Maps 1C00 0000H 1BFF FFFFH 2008 0000H Reserved Hz 2007 FFFFH P Data RAM area Ba 1800 0000H 512Kbyte P 17FF FFFFH 2000 0000H er 1FFF FFFFH External memory area 256Mbyte 1400 0000H 13FF FFFFH 1000 0000H OFFF FFFFH 0800 0000H Buffer memory area 128Mbyte Reserved CSZ3 area 64Mbyte CSZ2 area 64Mbyte CSZ1 area 64Mbyte CSZ0 area 64Mbyte Figure 3 3 Memory map External memory area Reserved 400F A37FH CC Link Master UO area 4Kbyte p 400F A100H Reserved 400F 9CFFH 400F 9000H CC Link Master memory area receive buffer 3328byte Reserved Reserved 400F 8CO0H CC Link Master memory area PAT1 256byte 400F BFFFH Reserved CC Link Slave area 4Kbyte 400F 8B9FH 400F BOOOH 400F 8800H CC Link Master memory area transmit buffer2 924byte 400F AFFFH Reserved CC Link Master I O area 4Kbyte 400F 84FF
108. RECEIVED Next Page function of local device supported or not 0 Not supported 1 Supported Receive new link code word and stored in register 5 And it turns to 0 when reading register 6 0 New page not received 1 New page received LINK PATNER AUTO NEGOTIATION ABLE Auto negotiation with link partner supported or not 0 Not supported 1 Supported R18UZ0003EJ0301 Dec 25 2014 Page 141 of 203 R IN32M3 EC User s Manual 7 4 8 Register 7 Auto Negotiation Next Page Transmit Register 7 Etherne PHY Function MR7 NEXT PAGE RW Bit Position RESERVED MESSAGE PAGE ACKNOWLEDGE TOGGLE R RW RW R Bit Name NEXT_PAG RESERVED MESSAGE_UNFORMATTED_CODE_FIELD RW RW RW RW RW RW RW RW RW Function Whether there are additional Next page 0 Last page 1 Have additional Next Page Reserved Write 0 and ignore reading RW PHY Address 07H Initial Value 2001H MESSAGE PAGE Encoding method of bit 10 s code field 0 Unformatted Page 1 Message Page ACKNOWLEDGE2 Shows correspondence to message supported or not 0 Not supported 1 Supported TOGGLE MESSAGE UNFORMAT TED CODE FIELD R18UZ0003EJ0301 Dec 25 2014 Used for synchronization with the link partner during the replacement with Next Page 0 Sent link code word is 1 1 Sent link code word is 0 11 bit code word send to the link partne
109. RVED Reserved Write 0 and ignore reading SPEED INDICATION RX_DV_J2T Shows the speed 001 10Mbps half duplex 101 10Mbps duplex 010 100Mbps half duplex 110 100Mbps duplex Set the delimiter to identify the beginning and the end of the frame 0 RX DV rises by JK delimiter and falls down by TR delimiter 1 RX_DV rises by JK delimiter and falls down by TR delimiter SCRAMBLE_ DISABLE R18UZ0003EJ0301 Dec 25 2014 Valid Invalid settings of data scrambing 0 Valid 1 Invalid Page 157 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 5 Ethernet PHY function setting register This register is used to change the behavior can t be controlled by MII management register of built in Ethernet PHY without going through the serial management interface 7 5 1 List of registers Register Name Abbreviations Address Ethernet PHY operation mode control register 4001 06A0H Ethernet PHY Power up status register PHYPUS 4001 06A4H R18UZ0003EJ0301 Page 158 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 5 2 7 Etherne PHY Function Ethernet PHY operation mode control register PHYMD PHYMD set the operating mode of Ethernet PHY It is a read write accessible register in 32 16 bit units Caution This register can be written only in case of releasing protection by specific sequence using system protects command register SYSPCMD Please refer to system protect
110. RW Specify whether to use alternate function 1 or 2 0 Alternate function 1 Alternate function 3 1 Alternate function 2 Alternate function 4 PFCmn RPFCIn Figure 8 13 Port function control registers in 32 bit notation Address 400A 3430H Initial value 0000 0000H Page 181 of 203 R IN32M3 EC User s Manual 8 Port function 8 3 5 Port function control expansion registers PFCE RPFCE These registers are used to specify which alternate expansion function is used These registers can be set in 1 bit units Address Initial 7 6 5 4 3 2 1 0 value PFCEOB PFCEO07 PFCE06 PFCEO5 PFCE04 PFCE03 PFCEO2 0 0 400A 3040H 00H PFCE1B 0 0 0 0 PFCE13 PFCE12 PFCE11 PFCE10 400A3041H 00H PFCE2B 0 PFCE26 PFCE25 PFCE24 PFCE23 PFCE22 PFCE21 PFCE20 400A3042H 00H PFCE3B PFCE37 PFCE36 PFCE35 PFCE34 PFCE33 PFCE32 0 0 400A 3043H OOH PFCE4B 0 0 0 0 0 PFCE42 0 0 400A 3044H 00H PFCE5B 0 0 0 PFCE54 PFCE53 PFCE52 PFCE51 PFCE50 400A3045H opp PFCE6B 0 0 PFCE65 PFCE64 PFCE63 PFCE62 0 0 400A 3046H OOH PFCE7B PFCE77 PFCE76 PFCE75 PFCE74 PFCE73 PFCE72 PFCE71 PFCE70 400A 3047H 00H RPFCEOB 0 0 RPFCEO5 RPFCE04 RPFCEOS RPFCEO2 RPFCEO1 RPFCEOO 400A 3440H ou RPFCE1B 0 0 0 0 0 0 0 0 400A 3441H OOH RPFCE2B 0 0 0 0 0 0 0 0 400A 3442H our RPFCE3B 0 0 0 0 0 0 0 0 400A 3443H oo Bit position Function 7to0 PFCEmn Speci
111. RW RW RW RW R R R R R NASR Function Reserved Write 0 and ignore reading SWRST FAST Test the software reset counter 0 Normal operation 1 Shorten the software reset counter from 256us to 10us for production test SQEOFF Valid Invalid the SQE test 0 Valid 1 Invalid RESERVED Reserved Write 0 and ignore reading FEFIEN Valid Invalid the setting of Far End Fault Indication in 100BASE FX 0 Invalid 1 Valid Automatic polarity detection result of 10BASE T 0 Normal 1 Reversal R18UZ0003EJO Dec 25 2014 RESERVED 301 Reserved Write 0 and ignore reading Page 153 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 21 Register 28 Reserved This register is used for testing Please don t read or write to this register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR28 PHY Address 1CH RESERVED Initial Value 1400H RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Bit Position Bit Name Function so RESERVED R18UZ0003EJ0301 Page 154 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 4 22 7 Etherne PHY Function Register 29 Interrupt Factor Register Register 29 indicates the source of interrupt when the interrupt output of Ethernet PHY is active Bit I points to the cause of the interrupt Interrupt output is cleared by reading Bit Position Bit Name RESERVED MR29 PHY Address 11 10 9 8 7 6
112. Reserve INTUAJOTIS UARTJO status interrupt INTUAJ1TIS INTCSIHOIRE UARTJ1 status interrupt CSIHO communication error interrupt INTCSIH1IRE CSIH1 communication error interrupt INTFCNOERR FCNO error detection INTFCN1ERR FCN1 error detection INTDERRO DMAC error response interrupt INTDERR1 RTDMAC error response interrupt INTETHTXFIFOERR INTETHRXERR TX FIFO error interrupt Ether receive flame error INTETHRXDERR MACDMA reception error interrupt INTETHTXDERR MACDMA transmission error interrupt INTBUFDMAERR Internal Buffer DMA error OJ1OI1OJO 01010 OD DO 0 O O O O o o o Oo 01010 OD DO 0 O O O O Reserve INTECATRST EtherCAT RESET interrupt Reserve Reserve Reserve Reserve Reserve Reserve R18UZ0003EJ0301 Dec 25 2014 Reserve Page 37 of 203 R IN32M3 EC User s Manual 4 Exception handling function 4 4 Connection Cause group Reserve Reserve 122 Reserve 123 Reserve S S S E 124 Reserve 125 Reserve 126 Reserve 127 Reserve 128 Reserve i Reserve Reserve INTCCMRQ CC Link INTRQ interrupt 132 INTCCSRFSTB CC Link RFSTB interrupt Note 133 INTCCSMON3 CC Link MONS interrupt Note To use a CC Link remote de
113. Set up the DRCTLP registers during initialization after the reset period ends After that the setting of each DRCTLP register can only be changed when the corresponding buffer function change pin is not being used For example a DRCTLP register setting can be changed at times when only a memory space is being accessed internally The DRCTLP register setting becomes valid regardless of the operating mode of the pin port mode or control mode in which an alternate function is used e Access These registers can be read and written in 32 bit or 16 bit units Caution1 These registers are write protected and can only be written after being protection unlocked by using a special instruction sequence initiated by using the system protection command register SYSPCMD For how to unlock protection see the description of the system protection command register SYSPCMD No special instruction sequence is required for reading these registers Caution2 Changing the pull up pull down resistor setting affects the level when a pin enters a high impedance state R18UZ0003EJ0301 Page 192 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 8 5 1 Port 1 buffer function change registers DRCTLP1L DRCTLP1H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 10 Address BASE 0228H olo SA S S DRCTLP1L a a ajla ala ala iti 0 0 0 0 0 0 Slo Slo 515 Slo Initial value FE alm ale ale 0000 9959H R W 00
114. T EV TIME This register indicates local time when at least one SyncManager asserts a PDI buffer start event 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 1 0 Address 400E 09F8H DC PDI Initial Value START EV PDISTART 0000 0000H TIME ECAT RRRRRRRRRRRRRRRRRRRRRRRRRRRRARRRR PDI HB PRP RR HR PPR RR HB PR HPHP RR RH PR PRP HHP RR RH Bit position Function PDISTART Register captures local time when at least one SyncManager asserts an PDI buffer start event Note Register bits 31 8 are internally latched ECAT PDI independently when bits 7 0 are read which guarantees reading a consistent value R18UZ0003EJ0301 Page 121 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 6 3 PDI Buffer Change Event Time register DC PDI CNG EV TIME This register indicates local time when at least one SyncManager asserts a PDI buffer change event 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13121110 9 8 7 6 5 43 2 10 Address 400E 09FCH DC PDI Le Initial Value CNG EV PDICHANGE 0000 0000H TIME ECAT RRRRRRRRRRRRRRRRRRRRRRRR PR RR HPP RR PDI RRRRRRRRRRRRRRRRRRRRRRRRRRRRARR RR Bit position Function 31 0 PDICHANGE _ Register captures local time when at least one SyncManager asserts an PDI buffer change event Note Register bits 31 8 are internally latched ECAT PDI independently when bits 7 0 are read which gua
115. T Event masking of the ECAT Event Request Events for mapping into ECAT event field of EtherCAT frames 0 Corresponding ECAT Event Request register bit is not mapped 1 Corresponding ECAT Event Request register bit is mapped 6 13 2 AL Event Mask register AL EVENT MASK AL event request PDI interrupt is used to transmit the ESC interrupt to the slave application This register is used to set mask to each event of AL event request register This register and AL event request register are ANDed and it is used as interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 10 Address 400E 0204H AL EVENT Initial Value ALEVMASK MASK OOFF FFOFH ECAT R RR RR RR RR RRR RRR RR RR RR R RRR R RR RR RR PDI RW RW RW RW RW RV RAW RW RW RW RW RV RW RW RV RW RW RW RAW RW RW RAW RW RW RAW R W RW RAW RW R W RW R W Bit position Function 31 0 ALEVMASK AL Event masking of the AL Event Request register Events for mapping to PDI IRQ signal 0 Corresponding AL Event Request register bit is not mapped 1 Corresponding AL Event Request register bit is mapped R18UZ0003EJ0301 Page 75 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 13 3 ECAT Event Request register ECAT EVENT REQ This register indicates events of ECAT event request ECAT interrupt 7 6 5 4 3 2 1 0 Address Initial 15 14 13 12 11 10 9 8 Value ECAT EVENT REQ ECAT PDI Bit
116. T S 9 2 1 4 External MPU Interface Signals cceccesecessesesesesseseseeeesesesceceseecsecsenseesseeesecaesesaeaeeececaeneeataeeeeeeaenees 11 2 1 5 Port Signals Real time port Signals erorrrornrororvrnrnrnvnvnvnnnnnnrnvrrnvrrnrrenrveraverasvrnevnnsveevvenvnennvernessvsesvsvensee 12 2 1 6 Serial Flash ROM Interface Signals ennnen innn kio deierste koe S ier EES 16 2 1 7 DMA Interface S18nalS es recur soseo ii edo kssa ENEE RRE seas Lv kaas on ledas 16 2 1 8 External Interrupt Input Stenale 17 2 1 9 Timer VO Signals sss kas LA AE AA deed o ate BAe ie La seas 18 2 1 10 W tchd g Timer Output Signals sss seis dada sere dio 18 2 1 11 KE UE 18 2 1 12 CPU Power Control Signals ssc c sscesscescescsciscdeks sa seio sees poa stun sadesstedavesdensscensdsdeeescenagcnsstebssssteedsesedeensess 18 2 1 13 Serial Interface Signals sse sni aint en esa ls ities in eed ne te 19 2 1 14 CC Link Signals Intelligent device station sesessesssseesssreesestrrtsrrsreerestertsststrsresteereseentesrerrsrerrreresreet 20 2 1 15 CC Link Signals Remote device station ennnnrnrnrennvnrnrnvennnnenrnvennnnenranennnnenrsvennnnenrnsennenenrssennnssnrassnsener 21 2 1 16 Seu rI TT EF TTT TTT TTT TTT TET E rE 22 2 1 17 RK EE 23 2 1 18 Operation mode Setting SignalS s s sss esvsoeepootsesonesosuoabesbooa seasons ebesson ees pak obadusepachernebuedevsesaseeveetenbiegs 24 22 Port EE 25 2 3 Buffer Type and Recommended Conn
117. T_ECAT 400E 0040H 00H ECAT ECAT RW RW RW RW RW RW RW R W PDI R R R R R R R R Bit postion Function 7 0 RESET_ECAT A reset is asserted after writing 0x52 R 0x45 E and 0x53 S in this register with 3 consecutive frames Read 7 6 5 4 3 2 1 0 Address Initial Value ESC_RESET_ 0 RESET_ECAT 400E 0040H 00H ECAT ECAT 0 0 0 0 0 0 RW RW PDI 0 0 0 0 0 R R 0 Gir poston Function 1 0 RESET_ECAT Progress of the reset procedure 01 after writing 0x52 10 after writing 0x45 if 0x52 was written before 00 else R18UZ0003EJ0301 Page 60 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 10 2 ESC Reset PDI register ESC RESET PDI This register is used to reset the EtherCAT Slave Controller from PDI slave by software Write 7 6 5 4 3 2 1 0 Address Initial Value ESC_RESET_ RESET_PDI 400E 0041H 00H PDI ECAT R R R R R R R R PDI RW RW RW RW RW RW RW RW Function 7 0 RESET_PDI A reset is asserted after writing 0x52 R 0x45 E and 0x53 S in this register with 3 consecutive frames Read 7 6 5 4 3 2 1 0 Address Initial Value ESC_RESET_ 0 RESET_PDI 400E 0041H 00H PDI ECAT 0 0 0 0 0 0 R R PDI 0 0 0 0 0 RW RW 0 sit poston Function 1 0 RESET_PDI Progress of the reset procedure 01 after writing 0x52 10 after writing 0x45 if 0x52 was written before 00 else R18UZ0003EJ0301 Pa
118. W R W R CW RAW R W R W R W RAW RAW PDI RA WIRAW RA W RAW RAW RAW R W R W RW RW RW RAW RAW RAW RAW RAW R IW R W R W R W R W RAW RAW R W R W R W R W RW R W R W RAW R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 1 0 STATIM ECAT RAWIRAW RIW RAWJRAW RAMW RAWRAWRAWRAWRAW RAWRAMWRAMWRAW RAWRAWJRAWRAW RAW RAW RAW R MWJR WR AWRAWIRAWRAW RAW RAW RAW R W PDI RAW RAW RAW R W R W RAW R W RAW RAW RAW RAW R W RAW R W RAW RAW RAW RAW RAW RAW RAW RAW RW R W R W R W R W R W R W RW RAW R W Bit position Function 63 0 STATIM Write Start time System time of cyclic operation in ns Read System time of next SYNCO pulse in ns Note 1 Write to this register depends upon setting of 0x0980 0 Only writable if 0x0981 0 0 2 Auto activation 0x0981 3 1 upper 32 bits are automatically extended if only lower 32 bits are written within one frame R18UZ0003EJ0301 Page 112 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 4 7 Next SYNC1 Pulse register DC NEXT SYNC1 PULSE This register indicates System Time of next SYNCI pulse 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address DC 400E 0998H NEXT Initial Value SYNC1PULSE SYNC1_ 0000 0000 PULSE 0000 0000H ECAT R RR RR RR RR RR RR RR RR RR RR RR PDI R RR RRR RR RR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 SY
119. W RW Initial value 0000H 14 11 0 Address PFC RPF RPF RPFC RPFC RPFC RPFCOH DREES 400A 5430H RW RW RW RW RW Initial value 0000H 14 11 0 Address RPFC2H PFCIRPFCIRPFCIRPFC RPFC CTE LEE LERE sa lm RW RW RW RW Initial value 0000H 15t00 PFCmn Specify whether to use alternate function 1 or 2 RPFCIn 0 Alternate function 1 Alternate function 3 1 Alternate function 2 Alternate function 4 Figure 8 12 Port function control registers in 16 bit notation Note The initial value depends on the pin status For details see 2 2 Port status Remark 1 0to3 m 0to7 n 0to7 R18UZ0003EJ0301 Page 180 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function PFCOW 31 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 Address PFC27 PFC23 PFC22 R W AW BIN BIN 400A 3030H Initial value 0000 0000H PFCAW PFC77 PFC76 0 Address PECH PFC54 PFC53 PFC52 PFC43 R W R WR W O R W R W 0 R WR WR W O 400A 3034H Initial value 0000 0000H RPFCOW Note The initial value depends on the pin status For details see 2 2 Port status Remark 0to3 m 0to7 n 0to7 R18UZ0003EJ0301 Dec 25 2014 31 30 29 28 13 12 11 10 9 RPFC25 RPFC24 R W 00000000 O RWRW O RW 0
120. X P 3 3V Analog Input Buffer Open PO HAN Pi RX P Pl RXN PO TXP 3 3V Analog Output Buffer Open PO TX N Pl TX P P1 TXN PO SD P PO SDN Pl SDP Pl SDN PO RD P PO RDN Pl RD P Pl RON PO TD OUT P PO TD OUT N 3 3V PECL Input Buffer Connect to GND 3 3V PECL Output Buffer Open P1_TD_OUT_N PO FX EN OUT P1 FX EN OUT Output Buffer 3 3V 12mA O O P1_TD_OUT_P O O O O 2 3 2 External Memory MPU Interface Signals Pin Name IO Interface Recommended connection when not in use BUSCLK O Output Buffer 3 3V AMA Open CSZO HCSZ I O I O Buffer 3 3V 6mA 50kO Pull up Open A2 A20 HA2 HA20 I O I O Buffer 3 3V 6MA 50kQ Pull down Open DO D15 HDO HD15 RDZ HRDZ I O I O Buffer 3 3V 6mA 50kQ Pull up Open WRSTBZ HWRSTBZ WRZO WRZ1 BENZO BENZ1 HWRZO HWRZ1 R18UZ0003EJ0301 Page 26 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 Signals by function 2 3 3 System Signals Pin Name UO Interface Recommended connection when not in use NMIZ l Input Buffer 3 3V Schmitt in Connect to VDD33 3 3V 50kQ Pull up XT1 Oscillator with EN Connect to GND XT2 RSTOUTZ O Output Buffer 3 3V 6mA Open RESETZ l Input Buffer 3 3V Schmitt in PONRZ OSCTH Input Buffer 3 3V Schmitt in Connect to VDD33 3 3V JTAGSEL 50kQ Pull down 2 3 4 Test Signals Pin Name
121. Z0003EJ0301 Dec 25 2014 Measure complete Error not detect 106 lt DIAGCNT Le No Measure complete No Calculate distance Measure complete Page 131 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 2 4 Fast link loss detection function It is possible to generate the interrupt as soon as possible or bring down the link by monitoring the state of the communication when the communication is poor It has two functions of BER monitor and FEQ monitor 1 BER monitor Bit error rate BER function can be used to measure the bit error of specific time count the number of errors and notify When the threshold is exceeded it can link down as a trigger and tell CPU with an interrupt Element to be an error is when it is different between IDLE state and data communication as follows Inthe IDLE state which communication is not performed count the error judged as bit error when received symbol other than J which means the start of IDLE symbol or frame delimiter e When the communication is performed count the error judged as bit error when received other than 32 kinds of symbol The operation of the BER monitor function is done by register 23 and as shown below The first step is to check whether the port is in link state by reading BER LNK OK Pay attention on the link down state which does not work properly Set the BER CNT LNK EN BER CNT TRIG BER WINDOW parameters once the link state is ver
122. a 32Mbyte 0200 0000H 000C 0000H Reserved 000B FFFFH Instruction RAM area 768Kbyte 0000 0000H Figure 3 1 Memory map ALL R18UZ0003EJ0301 Dec 25 2014 3 Memory Maps j 400A FFFFH f Reserved Synchronous burst access MEMC control registers area 400A 8000H 8Kbyte Reserved 400A 4800H CC Link Master Slave Bridge control registers 1Kbyte 400A 4400H Reserved Real time port 1Kbyte GPIO 1Kbyte DMA controller RTPORT 400A 2CO0H control registers area 1Kbyte DMA controller 400A 2800H Control registers area 1Kbyte Serial Flash ROM memory controller 400A 2400H control registers area 1Kbyte Asynchronous SRAM MEMC 400A 2000H control registers area 1 Kbyte 400A 3400H 400A 3000H Reserved QINT BUFID 4Kbyte Giga bit Ether 4Kbyte 4009 2000H 4009 1000H 4009 0000H HW RTOS 64Kbyte Page 30 of 203 R IN32M3 EC User s Manual 3 Memory Maps 400B 0000H 400A FFFFH AHB Peripheral registers area 192Kbyte APB Peripheral registers area 512Kbyte Reserved 4008 0000H 4007 FFFFH 4000 0000H Reserved f 4007 FFFFA 4007 0000H 4004 0000H 4002 0000H 4001 0000H 4000 0700H 4000 0600H 4000 0500H 4000 0400H 4000 0300H 4000 0200H 4000 0100H 4000 0000H ETHER SWITCH control register area 64Kbyte Reserved CAN1 area 128Kbyte CA
123. access to the area that is not controlled by MPU 6 Use fault programmable Error about operating instruction including undefined Reserved instruction SVCall programmable Call of system service by SVC interrupt Debug Monitor programmable Debug Monitor Reserved 14 PendSV programmable Request to system service that can be reserved 15 SysTick programmable Indication from system timer 16 R IN32M3 specific programmable Interrupt from the internal hardware of R IN32M3 and Interrupt External port R18UZ0003EJ0301 Page 34 of 203 Dec 25 2014 R IN32M3 EC User s Manual 4 2 Interrupt list 4 Exception handling function This interrupt is exception interrupt after the Exception No 16 that is assigned NVIC of Cortex M3 CPU In R IN32M3 the interrupts from the internal hardware of R IN32M3 and external port connect to not only NVIC of Cortex M3 but also the internal Hardware Real time OS starting trigger of internal DMAC and timer R IN32M3 support the following interrupts Table4 1 Interrupt list Cause group Connection 1 4 INTIICBOTIA IICBO transmission reception interrupt request INTIICB1TIA IICB1 transmission reception interrupt request INTFCNOREC INTFCNOTRX FCNO reception completion FCNO transmission completion INTTAUJZIO Timer array TAUJ2 channel 0 interrupt O O O O O INTTAUJ211 Timer arra
124. ager Read 0 Normal operation SyncManager activated 1 SyncManager deactivated and reset SyncManager locks access to Memory area Write 0 Activate SyncManager 1 Request SyncManager deactivation NOTE Writing 1 is delayed until the end of a frame which is currently processed Note m 0 7 R18UZ0003EJ0301 Page 101 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 Distributed Clocks Registers 6 20 1 DC Receive Times Registers 6 20 1 1 Receive Times Pott register DC RCV TIME PORTO This register is used to latch receive time of the frame at all ports if write to this register and to indicate the receive time latched at port 0 if read this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 10 Address 400E 0900H DC RCV Initial Value TIME RCVTIMEO Undefined PORTO ECAT RW RW RW RW RW RW RW RW RW R W RW RW RW R W RW RW RW R W R W RW R W R W RW RW R W R W RW R W R W R W RW RW PDI R R RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR Bit name Function RCVTIMEO Write A write access to register 0x0900 with BWR APWR any address or FPWR configured address latches the local time of the beginning of the receive frame start first bit of preamble at each port Read Local time of the beginning of the last receive frame containing a write access to this register NOTE The time stamps cannot be read in the same fram
125. al 6 20 4 2 DC PULSE LEN ECAT PDI Bit position 6 EtherCAT Slave Controller function Pulse Length of SyncSignals register DC PULSE LEN This register indicates pulse length of SyncSignals 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value oe 400E 0982H 2710H R R R R R R R R R R R R R R R R R R R Function 15 0 PULSELEN Pulse length of SyncSignals in Units of 10ns 0 Acknowledge mode SyncSignal will be cleared by reading SYNCO SYNC1 Status register 6 20 4 3 Activation Status register DC_ACT_STAT This register indicates activation status of SyncSignals 7 6 5 4 3 2 1 0 Address Initial Value DC_ACT_STAT 0 E z 400E 0984H 00H 2 e i 0 0 ECAT 0 0 0 0 R R R PDI 0 0 0 0 R R R Bit position Bit name Function 2 STARTTIME Start Time Cyclic Operation 0x0990 0x0997 plausibility check result when Sync Out Unit was activated 0 Start Time was within near future 1 Start Time was out of near future 0x0981 6 1 SYNC1ACT SYNC1 activation state 0 First SYNC1 pulse is not pending 1 First SYNC1 pulse is pending 0 SYNCOACT SYNCO activation state 0 First SYNCO pulse is not pending 1 First SYNCO pulse is pending R18UZ0003EJ0301 Page 110 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 4 4 SYNCO Status register DC SYNCO STAT This register indicates SYNCO status It is only used in Acknowledge m
126. ally 850ms Link Fail Inhibit Timer OUT a i Signal Lost Link Down LLU Fast Link Pulse e Idle Pattern or Link Pulse This three timer can be set by setting the 8 5 bit of register 18 PHY MODE 3 0 bit When PHY_MODE 3 is 0 the value of PHY MODE 1 0 can t be reflected Please set PHY_MODE 3 1 if you want to use this function PHY MODEJ 3 PHY MODE 1 0 Break Link Timer Autoneg Wait Timer Link Fail Inhibit Timer 0 XX 1250ms 850ms 850ms 1 00 80ms 35ms 50ms 1 01 120ms 50ms 75ms 1 10 240ms 100ms 150ms 1 11 1250ms 850ms 850ms R18UZ0003EJ0301 Page 128 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 2 3 Cable diagnostic function TDR function Cable diagnostic function TDR function is a diagnostic function for detecting the type and location of abnormality when disconnection or short occurs in the Ethernet cable Output the pulse of Ethernet cable and measuring the time of pulse waveform reflected by the cable This time can be used to determine the distance of abnormal whether the short or open from polarity The mechanism is as follows is the test pulse in Figure 7 2 is the threshold for detecting the reflected pulse and can be set by register When the cable is disconnected cable end open the sent pulse will get back attenuated in the same polarity as shown in Figure 7 2 When the cable is short circuited cable end closed the sent pulse will ge
127. als by function 2 1 5 Port Signals Real time port Signals Port Signals and Real time port Signals are configured as 12 sets of 8 bit ports They are able to realize 32 bit access by grouping 4 ports i e Ports 0 3 Ports 4 7 or Real time ports 0 3 1 4 Port Level during reset amp Name Mode 1 Mode 2 Mode 3 Mode 4 er PO POO INTPZO CATLEDRUN Hi Z P01 INTPZ1 CATIRQ P02 INTPZ2 CATLEDSTER P03 INTPZ3 CATLEDERR CCS_MON5 P04 INTPZ4 CATLINKACTO CCS MONS6 P05 INTPZ5 CATLINKACT1 CCS_MON7 P06 POLINKLEDZ CCS MONO P07 P1LINKLEDZ CCS RESOUT P1 P10 CATLATCH1 CATSYNC1 CCS REFSTB Hi Z With internal pull up resistor P11 CATLATCHO CATSYNCO CCS MON4 Hi Z With internal pull down resistor P12 INTPZ6 Hi Z P13 INTPZ7 CCS_WDTZ With internal pull up CCM_WDTENZ resistor P14 SMSCK P15 SMSI P16 SMSO P17 SMCSZ P2 P20 RXDO CCM LINKERRZ Hi Z P21 TXDO CCM ERRZ P22 INTPZ8 CATI2CCLK CCS_IOTENSU P23 INTPZ9 CATI2CDATA CCS_SENYUO P24 INTPZ10 ETHSWSECOUT CCS SENYU1 P25 WDTOUTZ CCS ERRZ P26 TIN1 TOUT1 CCM RUNZ CCS RUNZ P27 TINO TOUTO R18UZ0003EJ0301 Page 12 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 Signals by function 2 4 SE Mode 1 Mode 2 Mode 3 Mode 4 kog P3 P30 RXD1 Hi Z P31 TXD1
128. amp E SS 5 5la 5 a 5 a ala O Ola les les lei 0000 5555H W R W R W R W R W R W R W R W R W R W RAW R W R W R W R W R W PUIORP2n PDIORP2n Specify whether to connect a pull up or pull down resistor to the RP27 to RP20 pins Do not connect a pull up or pull down resistor Connect a pull down resistor Connect a pull up resistor Setting prohibited IOLRP2n1 IOLRP2n0 Specify the driving capability of the RP27 to RP20 pins IOL1 IOLO Driving capability of RP27 to RP20 pins 0 1 6 mA recommended 1 1 12 mA Other than above Setting prohibited Remark n 7to0 R18UZ0003EJ0301 Dec 25 2014 Page 199 of 203 R IN32M3 EC User s Manual 8 Port function 8 5 8 Real time port 3 buffer function change registers DRCTLRP3L DRCTLRP3H DRCTLRP3L DRCTLRP3H Bit position Bit name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W 000000000000 00 0 0 H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 Function Reserved Be sure to write 0 to these bits If read 0 is returned R W 0 00000000000 0 0 O O RW R W RAW RAW RW RW RW RW RW RW RW RW RW RW RW RW 10 Address gig 5 JIN 5 gig IS BASE 0278H E E GR E E D E E Ola Initial value lie Q e g ao lit 5la 5la 5 a aja Ge e a a S OjO a a O O 0000 9999H 1514131211109 8 765 43 2 10 Address BIBls e isg 8 85 g3 g BASE 0270H e EE EEE EE E
129. are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable ARM AMBA ARM Cortex Thumb and ARM Cortex M3 are a trademark or a registered trademark of ARM Limited in EU and other countries Ethernet is a registered trademark of Fuji Zerox Limited IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers Inc EtherCAT is a registered trademark of Beckhoff Automation GmbH Germany CC Link and CC Link IE Field are a registered trademark of CC Link Partner Association CLPA Additionally all product names and service names in this document are a trademark or a registered trademark which belongs to the respective owners Real Time OS Accelerator and Hardware Real Time OS is based on Hardware Real Time OS of ARTESSO made in KERNELON SILICON Inc How to use this manual 1 Purpose and target readers This manual i
130. ation mode setting register CATEMMD sssssesssesesssrsssreerssrrrrsrestenresreeresrerreresrenresreeees 51 6 6 3 EtherCAT reset register CATRESBET ss ko KN uen 52 6 7 ESC Information Register eer pe pe E e oopJ der TT TTT TTT TETTE s PoR IPEE ESSE 53 6 7 1 Type resister T YPE s n eee ates as nee een o a se Ee 53 6 7 2 Revision register REVISION Luis sszss sis RSS knee eien skiidrett 53 6 7 3 Buildr aister BUILD ENE TPP TTT REEERE 53 6 7 4 FMMUS supported register FMMU NUM 54 6 7 5 SyncManagers supported register SYNC MANAGER 54 6 7 6 RAM Size resister RAM SIZE sss areenan iaeiae EE idretter cuca Kabe EENS EEN ee 54 6 7 7 Port Descriptor register PORT DESC as agistnssenige En E en voe Aksess 55 6 7 8 ESC Features supported register FEATURE A 56 6 8 Station Address Registers un RD lra a eo 57 6 8 1 Configured Station Address register STATION ADR ST 6 8 2 Configured Station Alias register STATION ALLAR ST 6 9 Write Protection Registers cesit iesene enren o Febo DEDE EAr sepso apr Sapa aLa aaa evs 58 6 9 1 Write Register Enable register WR REG ENABLE errorennnnrnrnvennnnenrnennenerrrvennnnerrrvennenerravennnnesrssennener 58 6 9 2 Write Register Protection register WR RO DROTECTI 58 6 9 3 ESC Write Enable register ESC WR ENABLE renrvnernvenvvnerrrvenvnnesrasennnnsnrnvennnnenrsvsnnensnrasennnnsnrassnnenes 59 6 9 4 ESC Write Protection register ESC WR PROTEOCT 59 6 10 Data Link Layer Registers
131. ck R ack R ack R ack R ack R ack R ack Black R ack R ack R ack R ack R ack Bit position Function 63 0 SYSTIME Register captures System time at the negative edge of the Latch1 signal Reading clears LatchO Status OxO9AF 1 Note 1 Register bits 63 8 are internally latched ECAT PDI independently when bits 7 0 are read which guarantees reading a consistent value 2 Clearing Latch1 Status flag function depends upon setting of 0x0980 5 R18UZ0003EJ0301 Page 120 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 6 SyncManager Event Times Registers 6 20 6 1 Buffer Change Event Time register DC ECAT CNG EV TIME This register indicates local time of the beginning of the frame which causes at least one SyncManager to assert an ECAT event 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 1 0 Address 400E 09FOH DC ECAT Initial Value CNG EV ECATCHANGE 0000 0000H TIME ECAT RRRRRRRRRRRRRRRRRRRRRRRRRRRRARR RR PDI RRRRRRRRRRRRRRRRRRRRRRRRRRRRARR RR Bit position Bit name Function 31 0 ECATCHANGE Register captures local time of the beginning of the frame which causes at least one SyncManager to assert an ECAT event Note Register bits 31 8 are internally latched ECAT PDI independently when bits 7 0 are read which guarantees reading a consistent value 6 20 6 2 PDI Buffer Start Event Time register DC PDI STAR
132. command register SYSPCMD for protection releasing procedure In addition the special sequence is not necessary in case of reading the value of this register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8765432 1 0 Adress 4001 06A0H 2 a Initial Value PHYMD o o o o 0 o 0 o o o 0 D SP 2 0000 003FH L a o o o a o a a a RW 000 Bit Position Bit Name Function 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWRI HI 2 2 P1PHYEN Valid Invalid PHY of Port1 0 Valid 1 Invalid Initial value P1FXMODE Valid Invalid FX mode of Port including the input and output terminal control O Valid 1 Invalid Initial value P1ATMDIXEN Valid Invalid MDIX automatic recognition of Port1 0 Invalid 1 Valid Initial value POPHYEN Valid Invalid PHY of Port 0 Valid 1 Invalid Initial value POFXMODE Valid Invalid FX mode of PortO including the input and output terminal control 0 Valid 1 Invalid Initial value POATMDIXEN Valid Invalid MDIX automatic recognition of Porto 0 Invalid 1 Valid Initial value R18UZ0003EJ0301 Page 159 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 5 3 Ethernet PHY power up status register PHYPUS This register is used to confirm the Power up state of the built in Ethernet PHY It can be only read access in 32 bit unit
133. counted separately in Forwarded RX Error Counter 6 LINKDECMII Enhanced Link Detection MII 0 Not available 1 Available 3 DCWID Distributed Clocks width 0 32 bit 1 64 bit 2 DC Distributed Clocks 0 Not available 1 Available 0 FMMU FMMU Operation 0 Bit oriented 1 Byte oriented R18UZ0003EJ0301 Page 56 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 8 Station Address Registers 6 8 1 Configured Station Address register STATION ADR This register indicates the address used for node addressing 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value STATION_ADR NODADDR 400E 0010H 0000H ECAT RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PDI R R R R R R R R R R R R R R R R Bit position 15 0 NODADDR Address used for node addressing FPxx commands 6 8 2 Configured Station Alias register STATION_ALIAS This register indicates the alias address used for node addressing FPxx commands 15 14 13 12 n 10 9 8 7 6 5 4 3 2 1 0 Address Initial STATENE NODALIADDR ALIAS 400E 0012H 0000H ECAT R R R R R R R R R R R R R R R R PDI RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 15 0 Alias Address used for node addressing FPxx commands The use of this alias is activated by Register DL Control Bit 24 0x0100 24 0x0103 0 Note Initial Value is 0 until first EEPROM load then EEPROM ADR 0x0004 EEPROM value is only taken over at first EEPROM load a
134. ction SYSTIMDLY Delay between Reference Clock and the ESC R18UZ0003EJ0301 Page 105 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 2 5 System Time Difference register DC SYS TIME DIFF This register indicates mean difference between local copy of System Time and received System Time 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 1 0 Address gt 400E 092CH DC SYS 5 Initial Value 9 DIFF TIME DIFF 0000 0000H O O a ee ee e e I e Se l ECAT R RR R RR RR RR RR RR RR RR RR RR RR RR RR RR RR PDI R RR RR RR RR RR RR RR RR RR RR RR RR R RRR R RR Function LOCALCOPY Greater or smaller 0 Local copy of System Time greater than or equal received System Time 1 Local copy of System Time smaller than received System Time Mean difference between local copy of System Time and received System Time values 6 20 2 6 Speed Counter Start register DC SPEED COUNT START This register is used to set bandwidth for adjustment of local copy of System Time 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value DC_SPEED_ COUNT 0 SPDCNTSTRT 400E 0930H 1000H START ECAT 0 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PDI 0 R R R R R R R R R R R R R R R Bit position Bit name Function 14 0 SPDCNTSTRT Bandwidth for adjustment of local copy of System Time larger values smaller bandwidth and smoother adjus
135. der Number of 25 MHz tics minus 2 that represents the basic watchdog increment Default value is 100us 2498 6 15 2 Watchdog Time PDI register WDT_PDI This register is used to set overflow time of PDI watchdog 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value WDT PDI WDTIMPDI 400E 0410H 03E8H ECAT RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PDI R R R R R R R R R R R R R R R R 15 0 WDTIMPDI Watchdog Time PDI number or basic watchdog increments Default value with Watchdog divider 100us means 100ms Watchdog Watchdog is disabled if Watchdog time is set to 0x0000 Watchdog is restarted with every PDI access R18UZ0003EJ0301 Dec 25 2014 Page 81 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 15 3 Watchdog Time Process Data register WDT DATA This register is used to set overflow time of PDI watchdog 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value MOT DATA WETIMED 400E 0420H 03E8H ECAT RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PDI R R R R R R R R R R R R R R R R Bit position Bit name Function 15 0 WDTIMPD Watchdog Time Process Data number of basic watchdog increments Default value with Watchdog divider 100us means 100ms Watchdog There is one Watchdog for all SyncManagers Watchdog is disabled if Watchdog time is set to 0x0000 Watchdog is restarted with every write access to SyncManagers with Watchdog Trigger Enable Bit set
136. ding a consistent value 2 Clearing Latch1 Status flag function depends upon setting of 0x0980 5 R18UZ0003EJ0301 Page 119 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 5 8 Latch1 Time Negative Edge register DC LATCH1 TIME NEG This register indicates System time at the negative edge of the Latch1 signal 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address 400E 09C8H DC_ Initial Value LATCH1_ SYSTIME 0000 0000 TIME_NEG 0000 0000H ECAT Black R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack PDI R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 1 0 SYSTIME ECAT R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack PDI R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack Black R ack R a
137. e control register 1 8 bits RPMC1B 400A 3421H RT port mode control register 2 8 bits RPMC2B 400A 3422H RT port mode control register 3 8 bits RPMC3B 400A 3423H RT port mode control register 0 16 bits RPMCOH 400A 3420H RT port mode control register 2 16 bits RPMC2H 400A 3422H RT port mode control register 0 32 bits RPMCOW 400A 3420H RT port function control register 0 8 bits RPFCOB 400A 3430H RT port function control register 1 8 bits RPFC1B 400A 3431H RT port function control register 2 8 bits RPFC2B 400A 3432H RT port function control register 3 8 bits RPFC3B 400A 3433H RT port function control register 0 16 bits RPFCOH 400A 3430H RT port function control register 2 16 bits RPFC2H 400A 3432H RT port function control register 0 32 bits RPFCOW 400A 3430H R18UZ0003EJ0301 Dec 25 2014 Page 167 of 203 R IN32M3 EC User s Manual Register name Symbol 8 Port function Address 5 6 RT port function control expansion register 0 8 bits RPFCEOB 400A 3440H RT port function control expansion register 1 8 bits RPFCE1B 400A 3441H RT port function control expansion register 2 8 bits RPFCE2B 400A 3442H RT port function control expansion register 3 8 bits RPFCE3B 400A 3443H RT port function control expansion register 0 16 bits RPFCEOH 400A 3440H RT port function control expansion register 2 16 bits RPFCE2H 400A 3442H RT port function control expansion register 0 32 bits RPFCEOW 400A
138. e in which this register was written 6 20 1 2 Receive Times Port register DC RCV TIME PORT1 This register indicates received time of the frame latched at port 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 1 0 Address 400E 0904H DC RCV Initial Value TIME RCVTIME1 Undefined PORT1 ECAT R RR RR RR RR RR ARR RR RR AR ARR ARR RR RR RR RR RR PDI R RR RR R R R Bit position Function 31 0 RCVTIME1 Local time of the beginning of a frame start first bit of preamble received at port 1 containing a BWR APWR or FPWR to Register 0x0900 R18UZ0003EJ0301 Page 102 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 20 2 6 20 2 1 DC_SYS_ TIME ECAT R R PDI R R ECAT PDI R R Bit position 63 0 6 EtherCAT Slave Controller function DC Time Loop Control Unit Registers System Time register DC SYS TIME This register indicates local copy of the System Time 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 w w no p E IS I p p a to p o p e LS p o o zi i o a vik A a Di N sk o co N o a CH w De o RW RW RW RW RW RW RW RW RW R W RW RW RW R W RW RW RW R W R W RW R W R W RW RW R W R W RW RW R W R W RW RW Bit name SYSTIME 40 39 38 37 36 35 34 33 32 Address 400E 0910H Initial Value 0000 0000 0000 0000H SYSTIME
139. ection function BER Monitor FEQ Monitor Caution EtherCAT Slave Controller When using EtherCAT Slave Controller it doesn t correspond to 100BASE FX Please use 100BASE TX 7 2 7 2 1 Special functions Low latency function It is possible to shorten the latency time for Ethernet frame passing through PHY from LINE interface to MII interface Low latency mode Ethernet frame starts from preamble while this preamble starts from symbol 11000 J and 10001 K of symbol 5B of LINE In the devices generally based on Ethernet it s recognized as start preamble by detecting symbol J and K In latency function mode it s recognized as start preamble by detecting symbol J only This means RX DV signal is asserted at this moment and it becomes possible to shorten the latency 40ns If symbol J is incorrectly detected by a bit error RX_ER signal is asserted and the receiver will continue when symbol K in the following is not received Low latency mode becomes effective by setting bit 1 RX_DV_J2T bit of register 31 by 1 IDLE 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 11111 11000 J 10001 10110 10110 K 10110 10110 10110 10110 10110 10110 10110 10110 10110 10110 10110 10111 Preamble SFD Dest Addr Source Addr Length Payload
140. ection of Unused Dmns 26 2 3 1 Ethernet Signals aan sss tunns sna aen rn en kub ako enes 26 2 3 2 External Memory MPU Interface Sugnal 26 2 3 3 System EE 27 2 3 4 Test EE 27 2 3 5 Port Signals facie e e SLR 28 2 3 6 Operation Mode Setting Signals osiers ese cseeeeeeeceseceseceecesecaecsaecsaesaecsaecaaecaeecseseseseaeeseeeeeseenseenaes 29 2 3 7 CC Link Master Signal Intelligent device station Remote device stoaton 29 Contents 1 2 3 8 duete sg fua ITT TETTE TTT TTT TETTE TTT TTT 29 3 Memory MapsS sssscsegeretsoieoserojrnocorsoodonooi sacces kee SETAREA A TRE ARATTA AEEA ARTEARI A 30 4 Exception handling TUNC ON siari eei aiana eaa a NA Ai N EEA NENE EANN EATEN 34 4 1 Exceptlonis BTI AEE EE I E E EEE E ae es es ei 34 4 2 Interrupt lists EE 35 GR Ve Oe EE 39 6 EtherCAT Slave Controller function usserrvernrernranvrnvrvavrvrrnnerrnvenn vern vern neevrevnrervrnrvraneraveraervareneesvennveenveen ne 40 6 1 Pe tur s Lusastsesearjstaddtrasn saksa tagtndta TTT TTT TTT TTT ESTE FT 40 6 2 Peripheral circuit of Eher CAT ass sss ss is on ras sp ni A Ss Sau ee ines 40 6 3 Interrupt list and I O signals nee SEENEN NEESS 41 6 4 Functional Overview is ic pas ns sn Ma ee bk ks e SA SO Jovo LUN 42 6 5 BtherCAT fegister EE 45 6 6 Peripheral Function Replstert e ssessooso iD up soseo kera DA SD Spes OKSO Suba seas vio 50 6 6 1 EtherCAT PHY offset address setting register CATOPPAIID 50 6 6 2 EtherCAT oper
141. ennnnerrrrennnneersrenneneranennenesrasennenesrssennener 175 Port mode control registers in 8 bit notation esrrrnrevenvvnrnrnennrnerrrnennnnerrrvennenerravennenesrasennenesrssenneser 176 Port mode control registers in 16 bit notation eenreronrvnonrrennvnvrrrnennnnerrrrennnnerrrnennenesranenneneerssennener 177 Port mode control registers in 32 bit notation rrrrnrnvonrnnrnrnvenrnnrnrnsennnnnnrnsenrnnsnrnsennrnsnrnsensnssnrssenr 178 Port function control registers in 8 bit notaton 179 Port function control registers in 16 bit notapon 180 Port function control registers in 32 bit notapon 181 Port function control expansion registers in 8 bit notation sorrnvrvvrrvvnrnvrrnvrrnvrrverrvrversrerareraevresnen 182 Port function control expansion registers in 16 bit notation esvrrvrrrvrrnvrrnvrvnvvrnvvrnrverrvernveravvreenen 183 Port function control expansion registers in 32 bit notation oe ee ee eee eeeecesecesecesecseecneeeaeeees 184 Port pin input registers in 8 bit notatton 185 Port pin input registers in 16 bit notapon 186 Configuration of Trigger Synchronous Porte 202 Contents 7 Table4 1 Table 6 1 Table 6 2 Table 6 3 Table 6 4 Table 7 1 Contents of tables Interrupt list RART EE ESA EE EE EE 35 Features of EtherCAT Slave Controller ssesssesesssseeseseeessstertesrsessesreerssrerrssesrentestesresrentrsreresserernresrenens 40 Interrupt list of EtherCAT Slave Controller
142. eral functions edition for the detail of system protect command register SYSPCMD R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 21 0 Address GATOFFADDI0 010101010101010101010101010101010101010101010 0 010 BASE 0620H Initial Value 0000 0000H OADD2 OADD1 OADDO o o o o o o o o o o o o o o o o o o o o o o o o o o o 2 2 2 R18UZ0003EJ0301 Page 50 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 6 2 EtherCAT operation mode setting register CATEMMD CATEMMD register set the operation mode in case of using EtherCAT This register can be read Written in 32 bit or 16bit units Caution This register can be written only in case of releasing protection by specific sequence using system protect command register SYSPCMD Please refer to system protect command register SYSPCMD for protection releasing procedure In addition the special sequence is not necessary in case of reading the value of this register Please refer to R IN32M3 User s Manual Peripheral functions edition for the detail of system protect command register SYSPCMD R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 1 0 Address mm babe 000000000000000000 000000000 0 0 0 0 RW Bit position Function I2CSIZE Set the I2C memory size of EtherCAT 0 16Kbi
143. errnrennvnerranennnnerrrvennnneeranennnnenrsnennnnenrrvennenenrsvennnnesrssenneser 96 SyncMana ger Registers imron E eN re 97 SyncManager Physical Start Address m register SMm P START ADR 97 SyncManager Length m register GMm LN 97 SyncManager Control m register GMm CONTROL 98 SyncManager Status m register SMm STATUS ererorerarvrnvvrnrnrnrnnnvvnrvvernvervrrrvrversrerarernevrernrevveesvesnvener 99 SyncManager Activate m register Mm ACTA 100 SyncManager PDI Control m register SMm PDI CONT eee ce ceeeceeeceeeeeseceseceseceaecaessaeeneeeas 101 Distributed Clocks Registers sssri ss tu bs se sontcsesessebavesestssvass jeden EEN sueescesosbestcodasessesssebstessansceebasesesstaeed 102 DC Receive Times Registers inneni na SN NES RON a 102 DC Time Loop Control Unit Regester 103 Cyclic Unit Control Registers is ein enpe dki 108 SYNG Out Unit Registers isi reren SA EE r E ASIA be 109 Latch In Upit Registers nienean TE 114 SyncManager Event Times Registers rnvrrnvronrronrvernveravvrnrvrnenrernnenvnnnvenvensvennvenneervvvsvrvensvevaserasvresvresnen 121 IKEJ Co E TETTE R cu a a A E E E 123 PRODUCT ID register PRODUCT ID suerge savhseiedsvas vsssvesscetseesbebescbvegedsensceesspessgneeds 123 Vender ID register VENDOR ID enre i i E E EE E EEEE ARE E ETE a 123 Use RAM USER RAM sus naso ALAN ASNO E EEEE 124 Process Data RAM DATA RAM Jaa e aeaa ee e Eo i Eein 125 Contents 4 7 Etherne PHY FUnCtron EE 126 7 1 7
144. eserved Write 0 and ignore reading 12 INT12 MASK Clipping 11 INT11_MASK Maxlvl 10 INT10 MASK BER counter trigger 9 INT9 MASK FEQ trigger 8 RESERVED Reserved Write 0 and ignore reading 7 INT7 MASK Energy detection of the line 6 INT6 MASK Auto negotiation is complete 5 INT5 MASK Remote fault detection 4 INT4 MASK Link down 3 INT3 MASK Auto negotiation is complete and receive the last FLP 2 INT2 MASK Parallel detection failure 1 INT1 MASK Auto negotiation is transition to Complete Acknkowledge state 0 RESERVED Reserved Write 0 and ignore reading R18UZ0003EJ0301 Page 156 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 4 24 7 Etherne PHY Function Register 31 PHY special control Status register Register 31 does the configuration and status of the special features of Ethernet PHY MR31 RESERVED RW RW RW Bit Position Bit Name RESERVED AUTODONE AUTODONE m a a a SPEED amp RESERVED w ee INDICATION a 4 nm gt m o a LI x i er T RW RW RW RW RW RW RW R R R RW Function Reserved Write 0 and ignore reading Completion notice of auto negotiation 0 Incomplete or auto negotiation not set 1 Completion PHY Address 1FH Initial Value 0040H SCRAMBLE DISABLE RW RESERVED Reserved Write 0 and ignore reading ENABLE 4B5B Enable disable settings in 4B 5B encoding decoding 0 Invalid Bypass 4B 5B encoding decoding 1 Valid RESE
145. essseeeseeeseeeseesesesresseseeerssterrsserresterteetesrentssrerrsserrrneesrentes 41 I O signals of EtherCAT Slave Controller excluding PHY MDI signals ee ecese ici 41 Typical functions of EtherCAT Slave Controller and supported function by R IN32M3 EC 42 Summary of PHY MIT Management registers rrrerarvrarvrarnerernnvrnrnrennenvnnnnvnnneerveernevsnrvenaversseraseraevresnee 134 Contents 8 2tENESAS R18UZ0003EJ0301 R IN32M3 EC User s Manual Dec 25 2014 1 Overview 1 1 Introduction Ethernet communication continues to spread rapidly in the field of industrial automation as manufacturers seek to improve the capability efficiency and flexibility of their organizations Modern Industrial Ethernet applications require high speed real time response low power consumption and high performance These requirements are not necessarily met by traditional methods such as hard wired Ethernet processors or dedicated high speed CPUs Renesas R IN32M3 EC of large scale integrated circuits LSI are specifically tailored to meet the demands of Industrial Ethernet applications Key features include High speed real time deterministic low latency low jitter response for real time applications Low power consumption Integrated ARM Cortex M3 core for flexibility Integrated Real Time OS Accelerator with support for LITRON version 4 0 Integrated 10 100Mbps EtherPHY Dedicated DMA
146. f the output latch when the port is used in output mode If read the value of the output latch is read Figure 8 4 Port registers in 32 bit notation Remark 0to3 m 0to7 n 0to7 R18UZ0003EJ0301 Page 172 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 8 3 2 Port mode registers PM RPM These registers are used to set a port to input or output mode Address Initial 7 6 5 4 3 2 1 0 value PMOB PMO7 PM06 PM05 PM04 PM03 PM02 PMO1 PM00 400A 3010H FFH PM1B PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 400A 3011H FFH PM2B PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 400A 3012H FFH PM3B PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 400A 3013H FFH PM4B PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 400A 3014H FFH PM5B PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 400A 3015H FFH PM6B PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 400A 3016H FFH PM7B PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 400A 3017H FFH RPMOB RPM07 RPM06 RPM05 RPM04 RPMO3 RPM02 RPMO1 RPM00 400A 3410H FFH RPM1B RPM17 RPM16 RPM15 RPM14 RPM13 RPM12 RPM11 RPM10 400A 3411H FFH RPM2B RPM27 RPM26 RPM25 RPM24 RPM23 RPM22 RPM21 RPM20 400A 3412H FFH RPM3B RPM37 RPM36 RPM35 RPM34 RPM33 RPM32 RPM31 RPM30 400A 3413H FFH Bit position Function 7t00 PMmn Set the port to input or output mode RPMIn 0 Output mode output buffer is on 1 Input mode output buffer is off initial value Figure 8 5 Port mode registers in 8 bit notation Remark 0to3 m 0to
147. fter power on or reset R18UZ0003EJ0301 Page 57 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 9 Write Protection Registers 6 9 1 Write Register Enable register NR REG ENABLE This register is used to release the write protection temporarily when Write Register Protection is enabled 7 6 5 4 3 2 1 0 Address Initial Value LLI WR REG x 0 0 Es 400E 0020H 00H ENABLE Zz Li ECAT 0 0 0 0 0 0 0 R W PDI 0 0 0 0 0 0 R 0 Bit position Function ENABLE If write register protection is enabled this register has to be written in the same Ethernet frame value does not care before other writes to this station are allowed Write protection is still active after this frame if Write Register Protection register is not changed 6 9 2 Write Register Protection register WR_REG_PROTECT This register is used to protect from writing register The register in the area 400E 0000H to 400E OFFFH are write protected excluding 0x0020 and 0x0030 7 6 5 4 3 2 1 0 Address Initial Value WR REG 5 0 0 0 0 0 0 0 LL 400E 0021H 00H PROTECT Q ke a ECAT 0 0 0 0 0 0 0 R W o o o o o D PDI 0 0 Bit position Function PROTECT Write register protection 0 Protection disabled 1 Protection enabled Registers 0x0000 0x0FOF are write protected except for 0x0030 R18UZ0003EJ0301 Page 58 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller f
148. fy whether to use alternate functions 1 and 2 or alternate functions 3 and 4 RPFCEIn 0 Alternate function 1 Alternate function 2 3 1 Alternate function 3 Alternate function Aide Figure 8 14 Port function control expansion registers in 8 bit notation Note1 The initial value depends on the pin status For details see 2 2 Port status Note2 To use alternate function 1 or 3 the bit corresponding to the function in the PFC RPFC register must be set to 0 Note3 To use alternate function 2 or 4 the bit corresponding to the function in the PFC RPFC register must be set to 1 Remark 0to3 m 0to7 n 0to7 R18UZ0003EJ0301 Page 182 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 14 13 11 10 Address 15 12 9 8 7 6 5 4 3 2 1 PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCEOH ple ee Ps rei Pi e s e e Pos ern o 0 0 0 o RW RW RW RW RW RW RW RW RW RW Initial value 0000H Address PFCE2H 400A 3042H Initial value 0000H 14 11 10 0 Address 15 13 12 9 8 7 6 5 4 3 2 1 PFCE4H PFCE PFCE PFCE PFCE PFCE PFCE 0 0 0 0 0 0 0 o RW 0 0 RW RW RW RW RW Initial value opo0otfide 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address 77 76 75 74 73 72 71 70 65 64 63 62 RW RW RW RW RW RW RW RW 0 0 RW RW RW RW 0 0 Initial value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address 2 RPFC RPFC RPFC RPFC RPFC RPFC core oN RCNP oo SES ES exe fem o 0 0 0
149. ge 61 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 10 3 ESC DL Control register ESC DL CONTROL This register is used to control loop and configure RX FIFO size and Station Alias 6 EtherCAT Slave Controller function 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 121110 9 8 7 6 5 43 210 Address 400E 0100H ESC DL Rei wj Initial Value glO 010 5 CONTROL a Cl 0007 C001H O D it ECAT 0 0 0 0 0 0 0 RAW 0 0 0 0 PDI 0 0 0 00 0 0 A 00 00 0R RRR RR RRR RR 000000 RR Bit position Bit name Function 24 STAALIAS Station alias 0 Ignore Station Alias 1 Alias can be used for all configured address command types FPRD FPWR 18 16 RXFIFO RX FIFO Size ESC delays start of forwarding until FIFO is at least half full RX FIFO Size RX delay reduction 0 3 40 ns 4 6 no change 7 default 15 14 LP3 Loop Port 3 Port3 is not available on this LSI 00 Auto 01 Auto Close 10 Open 11 Closed 13 12 LP2 Loop Port 2 Port2 is not available on this LSI 00 Auto 01 Auto Close 10 Open 11 Closed 11 10 LP1 Loop Port 1 00 Auto 01 Auto Close 10 Open 11 Closed 9 8 LPO Loop Port 0 00 Auto 01 Auto Close 10 Open 11 Closed 1 TEMPUSE Temporary use of settings in Register 0x101 0 permanent use 1 use for about 1 second then revert to previous settings 0 FWDRULE Forwarding rule 0 EtherCAT frames are processed Non EtherCAT frames are forwarded without processing 1 Et
150. gister 4 Port pin input register 2 8 bits Port pin input register 5 8 bits 400A 3055H Port pin input register 6 8 bits 400A 3056H 400A 3057H Port pin input register 7 8 bits Port pin input register 0 16 bits 400A 3050H Port pin input register 2 16 bits 400A 3052H Port pin input register 4 16 bits 400A 3054H Port pin input register 6 16 bits 400A 3056H Port pin input register 0 32 bits 400A 3050H Port pin input register 4 32 bits 400A 3054H R18UZ0003EJ0301 Page 166 of 203 Dec 25 2014 R IN32M3 EC User s Manual Register name RT port register 0 8 bits Symbol 8 Port function 4 6 Address 400A 3400H RT port register 1 8 bits RP1B 400A 3401H RT port register 2 8 bits RP2B 400A 3402H RT port register 3 8 bits RP3B 400A 3403H RT port register 0 16 bits RPOH 400A 3400H RT port register 2 16 bits RP2H 400A 3402H RT port register 0 32 bits RPOW 400A 3400H RT port mode register 0 8 bits RPMOB 400A 3410H RT port mode register 1 8 bits RPM1B 400A 3411H RT port mode register 2 8 bits RPM2B 400A 3412H RT port mode register 3 8 bits RPM3B 400A 3413H RT port mode register 0 16 bits RPMOH 400A 3410H RT port mode register 2 16 bits RPM2H 400A 3412H RT port mode register 0 32 bits RPMOW 400A 3410H RT port mode control register 0 8 bits RPMCOB 400A 3420H RT port mod
151. gister RP2H DRCTLRP2H 4001 0274H Buffer function change register RP3L DRCTLRP3L 4001 0278H Buffer function change register RP3H R18UZ0003EJ0301 Dec 25 2014 DRCTLRP3H 4001 027CH Page 169 of 203 R IN32M3 EC User s Manual 8 Port function 8 3 1 Port registers P RP The R IN32M3 EC incorporates twelve 3 state I O ports Input or output mode can be specified in 1 bit units For output ports the port register can be used to write the output level If a port register is read the value of the output latch is read Use the PINn or RPINm register to read the pin level Address Initial 7 6 5 4 3 2 1 0 value POB P07 P06 P05 P04 P03 P02 P01 POO 400A 3000H 00H P1B P17 P16 P15 P14 P13 P12 P11 P10 400A 3001H 00H P2B P27 P26 P25 P24 P23 P22 P21 P20 400A 3002H 00H P3B P37 P36 P35 P34 P33 P32 P31 P30 400A 3003H 00H P4B P47 P46 P45 P44 P43 P42 P41 P40 400A 3004H 00H P5B P57 P56 P55 P54 P53 P52 P51 P50 400A 3005H 00H P6B P67 P66 P65 P64 P63 P62 P61 P60 400A 3006H 00H P7B P77 P76 P75 P74 P73 P72 P71 P70 400A 3007H 00H RPOB RPO7 RPO6 RP05 RP04 RPO3 RPO2 RPO1 RPOO 400A 3400H 00H RP1B RP17 RP16 RP15 RP14 RP13 RP12 RP11 RP10 400A 3401H 00H RP2B RP27 RP26 RP25 RP24 RP23 RP22 RP21 RP20 400A 3402H 00H RP3B RP37 RP36 RP35 RP34 RP33 RP32 RP31 RP30 400A 3403H 00H Bit Bit position Bitname name e pue SES output latch is read Figure 8 2 Port registers in 8 bit notation
152. he initial status of Port function after the reset cancellation varies according to the status of the operation mode setting signal External memory boot Asynchronous MEMC Synchronous burst MEMC External MPU boot 16bit 32bit P14 16bit 32bit P14 P14 External Serial Flash ROM boot P15 P15 P15 P16 P16 P16 P17 P17 P17 P40 HA1 P40 P41 HWAITZ HWAITZ P42 HERROUTZ HERROUTZ P43 HBUSCLK HBUSCLK P44 WRZ2 BENZ te1 WRZ2 BE N znge HPGCSZ RPO06 HPGCSZ HWRZ2 HBENZ9 e2 RPO6 WRZ3 BEN KAP WRZ3 BEN EAR RPO7 HWRZ3 HBENZ amp RPO7 RP20 ADVZ HBCYSTZ HBCYSTZ RP20 D24 D31 D24 D31 RP10 RP17 HD24 HD31 RP10 RP17 D16 D23 D16 D23 RP30 RP37 HD16 HD23 RP30 RP37 Note1 When using asynchronous SRAM MEMC WRZ 3 0 and BENZ 3 0 are converted by WREN register In addition when using synchronous burst MEMC WRZ 3 0 and BENZ 3 0 are converted by OPMODE register Note2 HWRZ 3 0 and HBENZ 3 0 are converted by the level of HWRZSEL port R18UZ0003EJ0301 Dec 25 2014 Page 25 of 203 R IN32M3 EC User s Manual 2 Signals by function 2 3 Buffer Type and Recommended Connection of Unused Pins 2 3 1 Ethernet Signals 1 Media Interface Signal Pin Name IO Interface Recommended connection when not in use PO R
153. he line to implement the TDR test 0 RX line 1 TX line Set the width of the pulse send out at TDR test in range of 8ns to 248ns for each 8ns 0 Normal operation Other than 0 Setting x 8 ns Page 151 of 203 R IN32M3 EC User s Manual 7 4 19 Register 26 Diagnostic counter register Set diagnostic counter of Ethernet PHY and show the results MR26 RW Bit Position RW RW Bit Name CNT WINDOW CNT WINDOW RW RW RW RW RW Function DIAGCNT Set the time to mask as invalid detection result from the start of delivery of the pulse Set in order to avoid the influence of noise of the sent pulse itself and immediately after delivery It will be about 0 8m per 1 count 7 Etherne PHY Function PHY Address 1AH Initial Value 0000H R18UZ0003EJ0301 Dec 25 2014 DIAGCNT Shows the value of the counter when detecting reflected wave It turns to 0x00 immediately after sending a pulse and OxFF when the reflected wave is not detected It becomes to 0x01 if the cable is not connected Page 152 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 20 Register 27 Special control Status instruction register Set PHY mode of Ethernet PHY and show the results RW Bit Position MR27 RESERVED RW RW Bit Name RESERVED SWRST FAST RW PHY Address 1BH RESERVED RESERVED Initial Value 0001H SQEOFF RW RW RW
154. herCAT frames are processed Non EtherCAT frames are destroyed The source MAC address is changed for every frame SOURCE MAC 1 is set to 1 locally administered address regardless of the forwarding rule R18UZ0003EJ0301 Page 62 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function Caution 1 Loop configuration changes are delayed until the end of a currently received or transmitted frame at the port 2 The possibility of RX FIFO Size reduction depends on the clock source accuracy of the ESC and of every connected EtherCAT Ethernet devices master slave etc RX FIFO Size of 7 is sufficient for 100ppm accuracy FIFO Size 0 is possible with 25ppm accuracy frame size of 1518 1522 Byte 6 10 4 Physical Read Write Offset register PHYSICAL_RW_OFFSET This register is used to set offset size between read address and write address in the R W command 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value PHYSICAL RWOFFSET RW OFFSET 400E 0108H 0000H ECAT RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PDI R R R R R R R R R R R R R R R R 15 0 RWOFFSET Offset of R W Commands FPRW APRW between Read address and Write address RD ADR ADR and WR ADR ADR R W Offset R18UZ0003EJ0301 Page 63 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 10 5 ESC DL Stat This register indicates EtherC ESC DL STATUS ECAT ack ack ack PDI R R R Bit name COMP3 Bit p
155. i negative edge 0 Continuous Latch active 1 Single event only first event active POSEDGE Latch1 positive edge 0 Continuous Latch active 1 Single event only first event active Note Write to this register depends upon setting of 0x0980 5 6 20 5 3 LatchO Status register DC LATCHO STAT This register indicates the state of LatchO input signal NI O OI CH wo W e Address Initial Value DC LATCHO STAT 400E 09AEH 00H ECAT 0 0 0 0 0 PDI 0 0 0 0 0 a I PINSTATE 3 D EVENTNEG 3 EVENTPOS Bit position Bit name Function PINSTATE LatchO pin state EVENTNEG Event LatchO negative edge 0 Negative edge not detected or continuous mode 1 Negative edge detected in single event mode only Flag cleared by reading out LatchO Time Negative Edge EVENTPOS Event LatchO positive edge 0 Positive edge not detected or continuous mode 1 Positive edge detected in single event mode only Flag cleared by reading out LatchO Time Positive Edge R18UZ0003EJ0301 Page 115 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 5 4 Latch1 Status register DC LATCH1 STAT This register indicates the state of Latch1 input signal Address Initial Value N O OT CH wo W CH DC LATCH1 STAT 400E 09AFH 00H ECAT 0 0 0 0 0 PDI 0 0 0 0 0 x 7 IPINSTATE 3 7 EVENTNEG a 7 EVENTPOS Bit position Bit name F
156. iation Select timing by bit 1 and bit Half duplex by parallel detection standard Specify the PHY address Setting of PHY ADD 0 is ignored and 0 is assigned to Loopback Isolate port 0 while 1 to port 1 Internal loop back mode Note 1 The timing of auto negotiation can be changed in order to reduce the auto negotiation time between 2 PHY It is possible to adjust the timing by changing the settings when link problem appears R18UZ0003EJ0301 Dec 25 2014 Page 146 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function PHY MODE 3 PHY MODE 1 0 Break Link Timer Autoneg Wait Timer Link Fail Inhibit Timer 0 XX 1250ms 850ms 850ms 1 00 80ms 35ms 50ms 1 01 120ms 50ms 75ms 1 10 240ms 100ms 150ms 1 11 IEEE 1250ms 850ms 850ms compliant 7 4 12 Register 19 Reserved 15 14 13 12 11 10 9 8 7 5 4 3 2 1 0 PHY Address 13H MR19 RESERVED Initial Value 0000H R R R R R R R R R R R R R R R 7 4 13 Register 20 Reserved 15 14 13 12 ti 10 9 8 7 5 4 3 2 1 0 PHY Address 14H MR20 RESERVED Initial Value 0000H RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RESERVED Reserved Write 0 and ignore reading R18UZ0003EJ0301 Dec 25 2014 Page 147 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 14 Register 21 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHY Address 15H MR21 RESERVED Initial Value 0000H
157. ified The error detection function starts to operate by writing a non zero on BER WINDOW An interrupt is generated when the number of errors exceeds the threshold is detected within the specified time in the BER WINDOW When using the interrupt please release the interrupt mask by writing to bit 10 of register 30 before setting the parameters before To end the operation of BER function write 0 to BER WINDOW When using an interrupt mask the interrupt by writing 0 to bit 10 of register 30 2 FEQ motor To stably receive the incoming data optimization is done by filtering the incoming signal by DSP in PHY FEQ is the coefficients of this filter and the value fluctuates greatly when the amplitude of the signal being received is changed It can output the interrupt when detecting variation exceeds the threshold set in advance or link down by monitoring the variation The operation of FEQ monitor function is done by register 24 shown as below Firstly set the variation to be detected in FEQ DELTA The reference value at the time of writing can be referred by writing Oxfffe to FEQ DELTA and reading FEQ VAL FEQ monitor function will begin to work when the threshold of variable of FEQ DELTA is set Current value of FEQ monitor can be detected by reading FEQ VAL An interrupt is generated when the value of FEQ VAL exceeds the threshold When using the interrupt please release the interrupt mask by writing I to bit 9 of register 30 before setting
158. igh With internal pull up CCS WDTZ Watchdog Timer port P13 Low resistor CCS RDLEDZ O Receive data LED control port P51 Low CCS RD l Data receive port P53 CCS SD O Data transfer port P54 CCS SDLEDZ O Operation check LED port RPOO Low CCS_SDGATEON O Transfer data amp gate control port P52 High Hi Z With internal pull down resistor CCS BS1 l Baud rate setting switch port RP02 Hi Z CCS BS2 l Baud rate setting switch port RPO3 With internal pull up CCS BS4 l Baud rate setting switch port RP04 resistor CCS BS8 l Baud rate setting switch port RP05 CCS FUSEZ Fuse cutting signal port P36 Low CCM_CLK80M l CC Link clock R18UZ0003EJ0301 Page 21 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 Signals by function 2 1 16 System Signals Pin Name I O Function Active Level during reset amp Level after reset XT1 Crystal Oscillator for system clock connect port XT2 I O Oscillator output connects to X2 in the case of connecting it directly RESETZ l Reset input port Low PONRZ Internal RAM Power on reset input port Low OSCTH l Input High level when external clock input mode JTAGSEL l JTAG Operation mode setting port RSTOUTZ O Reset to external circuit output port Low PLL VDD i PLL power supply 1 0V i PLL GND PLL power Ground supply GND VDD33 I O power supply 3 3V VDD10 S Internal power supply 1 0V GND Ground
159. ignore reading PAUSE OPERATION Set the action of Pause 00 No action 01 Symmetry Behavior 10 Asymmetry Behavior to the link partner 11 Asymmetry Pause Behavior to Symmetry pulse and local device 100BASE T4 100BASE T4 supported or not Fixed to 0 in this LSI 0 Not supported 1 Supported 100BASE TX FULL DUPLEX 100BASE TX Full Duplex supported or not 0 Not supported 1 Supported 100BASE TX 100BASE TX supported or not 0 Not supported 1 Supported R18UZ0003EJO Dec 25 2014 10BASET FULL DUPLEX 10BASE T SELECTOR FIELD 301 10BASE T Full Duplex supported or not 0 Not supported 1 Supported 10BASE T supported or not 0 Not supported 1 Supported 00001 IEEE std 802 3 Page 138 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 5 Register 5 Auto Negotiation Link Partner Ability Base Page Register Register 5 shows the Base Page of the information received from the partner when using auto negotiation w PHY Address oO 5 x x l gie eG 8 gle Falk a Base s z uwu 2 Eu fs S 5 SELECTOR FIELD Initial value Page a 2 Q m ugl lt lt Ji x DI 9 g x Re 3wu ml m lt 0001H if Oo iu LU zo 25 a 5 a E lt re Tr Col e Eri 2 Pr e R R R R R R R R R R R R R R R R Bit Position Bit Name Function NEXT_PAGE Whether there are additional pages 0 Last page 1
160. input pin of the alternate function 1 Alternate function control mode Figure 8 9 Port mode control registers in 16 bit notation Note The initial value depends on the pin status For details see 2 2 Port status Remark 1 0to3 m 0to7 n 0to7 R18UZ0003EJ0301 Page 177 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function Note The initial value depends on the pin status For details see 2 2 Port status Remark 1 0to3 m 0to7 n 0to7 R18UZ0003EJ0301 Dec 25 2014 PMCmn RPMCIn Figure 8 10 Port mode control registers in 32 bit notation 1 Alternate function control mode 31 30 29 28 27 26 25 24 23 15 14 13 121110 9 8 765 43 2 1 0 Address 400A 3020H Initial value PMCOW GEES NINN ANIA lala 518 0000 0000H e O 1O O OIO IO IO IO IOIO O OIO HdE 5 35 3 3 33 53 dE Ajaja ala a a a a a a A a a R W R W R W R W R MRMWRMWR MWRMR R W RW 31 30 29 23 22 21 20 19 18 17 16 1 0 Address 400A 3024H eat Initial value 4 KIRIRIR B 8 8 38 amp 5 8 BISS FIY 0000 0000 H e O JO O O OlOJOJOJO O O O COOC O O OD 5 5 5 3 S S S S S S S 3 3 5 35155 ajajaja a a a a o a o a n a a a Aaja R W R W R W R W R W R MRMWRMWR WRMR R W R W R W R W R W R W RW RWRW 23 22 21 20 19 18 17 16 13
161. ion 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 10 Address 400A 3000H Initial value POW 0000 0000H NI OINI TIOINIT JOIN IOINI TIOINIT JOIN TJOIN MIN rT O IN JO DI I MIN T O MI MIMIMIMIMI IMIMOININE JA JN INININ N Ir Im Im Ir Iririr r Oolod o o QO o o o BLE 2 EP E lees Sia a a a a EEE ELLE 2 R W R W R W R W R W R W R W R W RAW R W R W R W RAW RW R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 Address 400A 3004H Initial value P4w 0000 0000H BMIOLOITIMINIK LOIMS O OITIMINIT DS I DI DIT MIN I DI IO OIF IM IN IO NINININININININ DODO coco co co co OLO LO LO LO LOPFLO LO DO ITI o o a a o o a a a o o a a o a a a o o o a a o a a a o a a a a a RW R W R W R W R W R W R W RW RU R W R W R W RAW R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W RW RW 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 Address 400A 3400H Initial value RPOW DE lela 0000 0000H MIMIM NN o a o o a la EIEII R W RIM RN RW R W R W R W 31 to 0 Pmn RPIn Set the value o
162. istor to the RPO7 to RPOO pins Do not connect a pull up or pull down resistor Connect a pull down resistor Connect a pull up resistor Setting prohibited 13 12 9 8 5 4 1 0 IOLRPOn1 IOLRPOnNO Specify the driving capability of the RPO7 to RPOO pins IOL1 IOLO Driving capability of RPO7 to RPOO pins 0 1 6 mA recommended 1 1 12mA Other than above Setting prohibited Remark n 7toO R18UZ0003EJ0301 Dec 25 2014 Page 197 of 203 R IN32M3 EC User s Manual 8 Port function 8 5 6 Real time port 1 buffer function change registers DRCTLRP1L DRCTLRP1H DRCTLRP1L DRCTLRP1H Bit position Bit name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W 0000000000000 0 0 OR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 4 3 2 Function Reserved Be sure to write 0 to these bits If read 0 is returned R W 0 0 0000000000 0 0 O O RWRAW RAW RAW RW RW RW RW RW RW RW RW RW RW RW RW 1 0 Address ajoj Q al 2 2 o BASE 0268H a a o a alaj inital val a a a o a Initial value Q e g lit D Q QO amp jo 5 a 5 a 5 a alalelelala 0 30 22 0 0 0000 9999H 15 14 13 121110 9 8 7 6 5 43 210 Address NINlalo 9lelyulolnlnlilol l ol BASE 026CH alao Salae Leja eaat xirja a LC a a MImIa o TIETo jo Initial val OG z 6 r 6 r GO a E nitial value 5 a 5la 5 a 5 a ales a DS
163. ite accesses 1 Use mapping for write accesses Read access mapping 0 Ignore mapping for read accesses 1 Use mapping for read accesses Note m 0 7 6 18 8 This register is used to activate FMMU Activate m register FMMUm ACT FMMU 0 Bit position i ACTIVATE 7 6 5 4 3 2 1 0 Address Initial Value FMMUm Li 400E 060CH 0 0 00H ACT gt 0010H m oO st ECAT 0 0 0 0 o 0 0 RW PDI 0 0 0 0 0 0 R Function Activate FMMU 0 FMMU deactivated 1 FMMU activated FMMU checks logical addressed blocks to be mapped according to mapping configured Note m 0 7 R18UZ0003EJ0301 Dec 25 2014 Page 96 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 19 SyncManager Registers 6 19 1 SyncManager Physical Start Address m register SMm P START ADR This register is used to set the physical start address for SyncManager 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value SMm SMSTAADDR 400E 0800H 0000H P_START_ADR 0008H m ECAT RAW RAW RAW RW RW R W RAW R W RW RAW R W RAW RW RW RW RW PDI R R R R R R R R R R R R R R R R 15 0 SMSTAADDR Specifies first byte that will be handled by SyncManager Note 1 m 0 7 2 Register can only be written if SyncManager is disabled 0x6 0 0 6 19 2 SyncManager Length m register SMm LEN This register is used to set the length for SyncManager area 15 14 13 12 11
164. itional Next page 0 Last page 1 Have additional Next Page ACKNOWLEDGE Result of link signal from the link partner 0 Success 1 Failure MESSAGE PAGE Encoding method of bit 10 0 s code filed 0 Unformatted Page 1 Message Page ACKNOWLEDGE2 Shows correspondence to message supported or not 0 Not supported 1 Supported TOGGLE Used for synchronization with the link partner during the replacement with Next Page 0 Sent link code word is 1 1 Sent link code word is 0 MESSAGE UNFORMA TTED CODE FIELD R18UZ0003EJ0301 Dec 25 2014 11 bit code word received from the link partner Page 140 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 7 Register 6 Auto Negotiation Expansion Register PHY Add MR6 z o 2 zi ress Ejga lt gt Ge 06H Zu w u Z lt RESERVED so Eg 9 amp EE initial Value do ES 5 E EG eHivk amp amp zu 0004H Tu Z ul ui d Zom nao Iz z D tH lt Bit Position Bit Name RESERVED R R R R R R R LH R R R LH R Function Reserved Write 0 and ignore reading PARALLEL DETECTION_FAULT LINK PATNER NEXT PAGE ABLE Shows whether the failure was detected in parallel detection function It is set to 0 when reading register 6 0 Undetected 1 Detected Next Page function of link partner supported or not 0 Not supported 1 Supported NEXT PAGE ABLE PAGE
165. l register 0x0120 0x0121 from PDI R18UZ0003EJ0301 Page 77 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 14 Error Counters Registers 6 14 1 Rx Error Counter n register RX ERR COUNTn This register counts RX frame errors 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value RX_ERR_ RXERRCNT INVFRMCNT 400E 0300H 0000H COUNTn 0002H n ECAT RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW clr clr clr cir cmo cl cr cmo cl cmo ciro cl cmo cl cr clr PDI R R R R R R R R R R R R R R R R Bit position Bit name Function 15 8 RXERRONT RX Error counter of Port n counting is stopped when OxFF is reached This is coupled directly to RX ERR of MII interface Cleared if one of the RX Error counters 0x0300 0x030B is written 7 0 INVFRMCNT Invalid frame counter of Port n counting is stopped when OxFF is reached Cleared if one of the RX Error counters 0x0300 0x030B is written Note 1 n 0 1 n 0 Port 0 n 1 Port 1 2 The invalid frame counters are incremented if there is an error in the frame format Preamble SFD Start of Frame Delimiter FCS Checksum invalid length If the FCS is invalid and an additional nibble is appended the FCS error is not counted This is why EtherCAT forwards frames with errors with an invalid FCS and an additional nibble RX Errors may appear either inside or outside frames RX Errors inside f
166. me and expand frame Transmission speed 1Mbps max Clock Synchronized Serial 2 channels Interface Synchronized Serial data transmission by three wire system Selectable Master mode or Slave mode Built in Baud rate generator Transmission data length 7bit 16bit CC Link Intelligent device station lt R gt Remote device station 10 100Mbps EtherPHY EtherCAT 2ports Support for 10BaseT and 100BaseTX FX EtherCAT Slave controller On chip debug function Select serial wire or JTAG Support Full Trace Built in ETM Internal PLL Generates various clocks from 25MHz input clock Power supply voltage I O VDD33 3 3 0 3V Internal circuit VDD10 1 0 0 1V Note Please ask us about a detail for support R18UZ0003EJ0301 Dec 25 2014 Page 3 of 203 1 Overview R IN32M3 EC User s Manual INTERNAL BLOCK DIAGRAM 1 3 12C x 2ch p Timer Array p UART x 2ch p CAN x 2ch CSI x 2ch yurT 09 LYOdLY OVNA 2P0D I NdI epo d NdI weyshs 140 Zem Vogt I mg ETE 00MANS9L por OWAN TYOAN WVU OWAN oan ola NON OVNG Vuen UOTJINIISUT USE ELIAS p s sl sl is s OUNI VINGGYHHV WVU Bed AL dOL OVI sng UORVITUNUWWUO 101 KI VING OV IN VING Au OY borastro PINE vu ma SO PULL VRI ATI8MDIEH 1017000 uorpun g AIEADIEH
167. n accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they
168. n control register 4 32 bits 400A 3034H R18UZ0003EJ0301 Page 165 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 3 6 Register name Symbol Address Port function control expansion register 0 8 bits PFCEOB 400A 3040H Port function control expansion register 1 8 bits PFCE1B 400A 3041H Port function control expansion register 2 8 bits PFCE2B 400A 3042H Port function control expansion register 3 8 bits PFCE3B 400A 3043H Port function control expansion register 4 8 bits PFCE4B 400A 3044H Port function control expansion register 5 8 bits PFCE5B 400A 3045H Port function control expansion register 6 8 bits PFCE6B 400A 3046H Port function control expansion register 7 8 bits PFCE7B 400A 3047H 16 bits PFCEOH 400A 3040H 16 bits PFCE2H 400A 3042H 16 bits PFCE4H 400A 3044H 16 bits PFCE6H 400A 3046H 32 bits PFCEOW 400A 3040H 32 bits PFCE4W 400A 3044H Port pin input register 0 8 bits PINOB 400A 3050H Port pin input register 1 8 bits 400A 3051H 400A 3052H Port pin input register 3 8 bits 400A 3053H Port pin input register 4 8 bits 400A 3054H Port function control expansion register 0 Port function control expansion register 2 Port function control expansion register 4 Port function control expansion register 6 Port function control expansion register 0 lm lsmo Log PE om les lom DEG ee Lee e e ee Port function control expansion re
169. n order to indicate specific slave position R18UZ0003EJ0301 Page 68 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 11 5 ERR LED Override register ERR LED OVERRIDE This register is used to override ERR LED control 7 6 5 4 3 2 1 0 Address Initial Value Zz Li ERR LED 5 0 0 0 T LEDCODE 400E 0139H 00H OVERRIDE ks D gt O ECAT 0 0 0 R W R W RW RW RW PDI 0 0 0 R W RW RW RW RW Bit position Bit name Function 4 OVERRIDEEN Enable Override 0 Override disabled 1 Override enabled 3 0 LEDCODE LED code 0x0 Off 0x1 0xC Flash 1x 12x OxD Blinking OxE Flickering OxF On Caution New error conditions will disable ERR LED Override 0x0139 4 0 The value read in this R18UZ0003EJ0301 Dec 25 2014 register always reflects current LED output ESC automatically controls ERR LED in the condition below SII EEPROM load error PDI watchdog timeout Regarding the other errors ERR LED should be controlled by application using this register 6 EtherCAT Slave Controller function Page 69 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 12 PDI Registers 6 12 1 PDI Control register PDI CONTROL This register indicates the type of PDI 7 6 5 4 3 2 1 0 Address Initial Value PDI CONTROL PDI 400E 0140H 80H ECAT R R R R R R R R PDI R R R R R R R R Bit poston 7 0 Process data interface This LSI indicates the below value 0x80 On chip bus
170. nal MPU interface area 40 125 Modification of 6 EtherCAT Slave Controller function 3 01 Dec 25 2014 3 Change status for Intelligent device station for CC Link in 1 3 Overview 196 Remove IOLP521 IOLP520 bit at 8 5 4 Port 5 buffer function change registers DRCTLP5L DRCTLP5H because driving capability of P52 is fixed to 6mA REVISION 2 R IN32M3 EC User s Manual REVISION HISTORY Memo REVISION 3 R IN32M3 Series User s Manual R IN32M3 EC r8RRENESAS SALES OFFICES Renesas Electronics Corporation http Avwww renesas com Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 651 700 Fax 44 1628 651 804 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 Dusseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21
171. nction PHYREGADDR Address of PHY Register that shall be read written Note Write access depends on assignment of MI ECAT PDI Write access is generally blocked if Management interface is busy 0x0510 15 1 R18UZ0003EJ0301 Dec 25 2014 Page 89 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 17 4 PHY Data register PHY DATA This register is used to set data to write to PHY register or to indicate read data from PHY register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value PHY_DATA PHYREGDATA 400E 0514H 0000H ECAT RAW RAW RAW RUW RAW RAW RAW RAW RAW RAW RUW RAW RAW RAW RAW RAW PDI RAW RAW RAW ROW RAW RAW RAW RAW RAW RAW RW RAW RAW RAW RAW RAW 15 0 PHYREGDATA PHY Read Write Data Note Write access depends on assignment of MI ECAT PDI Write access is generally blocked if Management interface is busy 0x0510 15 1 6 17 5 MII Management ECAT Access State register MII ECAT ACS STAT This register is used to set access state of MII management interface 7 6 5 4 3 2 1 0 Address Initial Value MIL ECAT 0 0 400E 0516H 00H ACS_STAT Oo O lt x ECAT 0 0 0 0 0 0 0 R W PDI 0 0 0 0 0 0 R 0 Bit postion See AGSMII Access to MII management 0 ECAT enables PDI takeover of MII management control 1 ECAT claims exclusive access to MII management Note Write access is only possible if 0x0517 0 0 R18UZ00
172. nnenravennnnenrnsennensnrsssnnene 74 6 13 Interrupts ru ilo FR usunne 15 6 13 1 ECAT Event Mask register ECAT EVENT MARK 15 6 13 2 AL Event Mask register AL EVENT MASK 75 6 13 3 ECAT Event Request register ECAT EVENT RO 76 6 13 4 AL Event Request register AL EVENT RON TI 6 14 Error Counters Reglsters s isesmcis erste eds E E polso LaO sn Sa baa ENEE 78 6 14 1 Rx Error Counter n register RX ERR COUNTni AA 78 6 14 2 Forwarded Rx Error counter n register FWD RX ERR COUNTnn A 79 6 14 3 ECAT Processing Unit Error Counter register ECAT PROC ERR COUNTN 79 6 14 4 PDI Error Counter register PDI ERR COUNT AA 80 6 14 5 Lost Link Counter n register LOST LINK COUNIni 80 6 15 WatchidogsS Registers o sss Sn IA AR AGAR enste IL AN oseo 81 6 15 1 Watchdog Divider register WD DIVIDE is eseserseesesipe deoeh s iii eseshe esi sn nessen assisi seser soviposa 81 6 15 2 Watchdog Time PDI register WDT BD 81 6 15 3 Watchdog Time Process Data register WDT DATA 82 6 15 4 Watchdog Status Process Data register WDS DATA 82 6 15 5 Watchdog Counter Process Data register WDC DATA 83 6 15 6 Watchdog Counter PDI register WDC PI 83 6 16 SILEEPROM Interface RegIster5 ss sees bonlo teste I SEO AVON VUNDAS Sin skii 84 6 16 1 EEPROM Configuration register BER CONPN A 84 6 16 2 EEPROM PDI Access State register EEP STAT 84 6 16 3 EEPROM Control Status register EEP CONT STAT 85 6 16 4 EEPROM Address register EEP ADR
173. nputs 1 At least one change on DC Latch Inputs Bit is cleared by reading DC Latch event times from ECAT for ECAT controlled Latch Units so that Latch 0 1 Status OxO9AE 0x09AF indicates no event R18UZ0003EJ0301 Dec 25 2014 Page 76 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 13 4 AL Event Request register AL EVENT REQ This register indicates events of AL event request PDI interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14131211109 8 7 6 5 43 21 0 Address 400E 0220H Initial Value 0000 0000H AL EVENT REQ DCSYNC1STA DCSYNCOSTA ECAT 0 0 0 0 0 0 0 0 0 0 0 0 01 0 0 0 A R R R RR RR OR RR RR RR PDI 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 r R RRR RR RO RR RR RRR Bit position Bit name Function 15 SMINT7 SyncManager 7 interrupts SyncManager register offset 0x5 bit 0 or 1 0 No SyncManager 7 interrupt 1 SyncManager 7 interrupt pending 14 SMINT6 SyncManager 6 interrupts SyncManager register offset 0x5 bit 0 or 1 0 No SyncManager 6 interrupt 1 SyncManager 6 interrupt pending 13 SMINT5 SyncManager 5 interrupts SyncManager register offset 0x5 bit 0 or 1 0 No SyncManager 5 interrupt 1 SyncManager 5 interrupt pending SMINT4 SyncManager 4 interrupts SyncManager register offset 0x5 bit 0 No SyncManager 4 interrupt 1 SyncManager 4 interrupt pending SMINT3 SyncManager 3 interrupts SyncManager register offset 0x5 bit 0 No SyncManager 3 inter
174. ode 7 6 5 4 3 2 1 0 Address Initial Value DC SYNCO 0 0 400E 098EH 00H STAT O Zz gt VD ECAT 0 0 0 0 0 0 0 R PDI 0 0 0 0 0 0 0 R ack Bit position Bit name Function SYNCOSTA SYNCO state for Acknowledge mode SYNCO in Acknowledge mode is cleared by reading this register from PDI use only in Acknowledge mode 6 20 4 5 SYNC1 Status register DC_SYNC1_STAT This register indicates SYNCI status It is only used in Acknowledge mode 7 6 5 4 3 2 1 0 Address Initial Value DC_SYNC1_ 0 0 0 0 0 0 a 400E 098FH 00H STAT 9 zZ gt N ECAT 0 0 0 0 0 0 0 R PDI 0 0 0 0 0 0 R ack 0 Bit position Function SYNC1STA SYNC1 state for Acknowledge mode SYNC1 in Acknowledge mode is cleared by reading this register from PDI use only in Acknowledge mode R18UZ0003EJ0301 Page 111 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 4 6 Start Time Cyclic Operation Next SYNCO Pulse register DC CYC START TIME This register is used set start time of cyclic operation if write to this register and to indicate System Time of next SYNCO pulse if read this register 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address 400E 0990H DC CYC Initial Value START STATIM 0000 0000 TIME 0000 0000H ECAT RIW R W R W RAW RAW RAW R W R W R W RAW RW RAW RAW RAW RAW RAW R CW R W R W R W R W RAW RAW R
175. ogrammable UO Buffer 3 3V Load Drive select function 6mA 12mA Resistor select function 50kQ Pull up or 50kQ Pull down or less P40 P47 I O Programmable I O Buffer 3 3V 6mA Resistor select function 50kQ Pull up or 50kQ Pull down or less P50 P51 I O Programmable UO Buffer 3 3V Load Drive select function 6mA 12mA Resistor select function 50kQ Pull up or 50kQ Pull down or less P52 I O Programmable I O Buffer 3 3V 6mA Resistor select function 50kQ Pull up or 50kQ Pull down or less Open P53 P56 P57 P60 P67 R18UZ0003EJ0301 Dec 25 2014 I O I O I O 5V tolerant I O Buffer 4mA 50kQ Pull up Programmable I O Buffer 3 3V 6mA Resistor select function 50kQ Pull up or 50kQ Pull down or less I O Buffer 3 3V 6mA Open Open Connect to GND Page 28 of 203 R IN32M3 EC User s Manual 2 Signals by function 2 2 Pin Name IO Interface Recommended connection when not in use P70 P77 UO I O Buffer 3 3V 6mA Connect to GND RPOO RPO7 UO Programmable UO Buffer 3 3V Open RP10 RP17 Load Drive select function 6mA 12mA RP20 RP27 Resistor select function RP30 RP37 50kQ Pull up or 50kQ Pull down or less 2 3 6 Operation Mode Setting Signals Pin Name UO Interface Recommended connection when not in use BOOTO BOOT Input Buffer 3 3V Schmitt in MEMIFSEL BUS32EN HIFSYNC HWRZSEL MEMCSEL ADMUXMODE
176. oller Support serial interface compatible with SPI of the companies Support direct boot from serial memory device Support Fast Read Fast Read Dual Output Fast Read Dual I O mode Direct layout in memory space Interrupt Support 29 external interrupt ports Internal Peripherals I O Ports CMOS I O 96ports max System Timers R18UZ0003EJ0301 Dec 25 2014 Internal timer of Hardware RTOS internal timer of CPU 4channel timer array 32bit counter amp 32bit data register counter by external signal Page 2 of 203 R IN32M3 EC User s Manual Table 1 1 Internal Peripherals cont 1 Overview Overview of R IN32M3 EC 2 2 MG Product R IN32M3 EC Watchdog Timer 1 channel Software triggered start mode Watchdog error response options Generate Non Maskable Interrupt NMI Generate Reset Asynchronous serial interface I2C Serial interface 2 channels Full duplex FIFOs 10 bit x 16 receive and 8 bit x 16 transmit Support output of receive errors and status Character length 7 or 8 bit Parity bit options odd even 0 none Transmit stop bits 1 or 2 bit 2 channels Operation modes normal or high speed Transfer modes single transfer mode or continuous transfer mode Transmission data length 8 bit CAN controller 2 channels Conforming to ISO11898 Support to transfer and receive normal fra
177. ort Descriptor PORT_DESC 8 400E 0007H ESC Features supported FEATURE 1 400E 0008H 3 Station Address Registers Register name Shortcut Address Configured Station Address STATION_ADR 400E 0010H Configured Station Alias STATION_ALIAS 400E 0012H 4 Write Protection Registers Register name Write Register Enable WR_REG_ENABLE Address 400E 0020H Shortcut Write Register Protection WR_REG_PROTECT 400E 0021H ESC Write Enable ESC_WR_ENABLE 400E 0030H ESC Write Protection ESC_WR_PROTECT 8 400E 0031H 5 Data Link Layer Registers Register name ESC Reset ECAT ESC_RESET_ECAT Address 400E 0040H Shortcut ESC Reset PDI ESC RESET PDI 400E 0041H ESC DL Control ESC DL CONTROL 400E 0100H Physical Read Write Offset PHYSICAL RW OFFSET 400E 0108H ESC DL Status 6 Application Layer Registers Register name ESC DL STATUS 400E 0110H Shortcut Address AL Control AL CONTROL 400E 0120H AL Status AL Status Code RUN LED Override AL STATUS AL STATUS RUN LED OVERRIDE 400E 0130H CODE 400E 0134H 400E 0138H ERR LED Override R18UZ0003EJ0301 Dec 25 2014 ERR LED OVERRIDE 400E 0139H Page 45 of 203 R IN32M3 EC User s Manual 7 PDI Registers Register name 6 EtherCAT Slave Controller function Shortcut Address PDI Control ESC Configuration PDI CONTROL ESC CONFIG
178. osition 15 6 EtherCAT Slave Controller function us register ESC DL STATUS AT Slave Controller status Initial Value Address 400E 0110H 0004H 2 ENHLINKD 0 ack ack ack ack ack ack ack ack ack ack ack R R R R R R R R R 0 R R Function Communication on Port 3 Port 3 is not available on this LSI 0 No stable communication 1 Communication established 14 LP3 Loop Port 3 Port 3 is not available on this LSI 0 Open 1 Closed 13 COMP2 Communication on Port 2 Port 2 is not available on this LSI 0 No stable communication 1 Communication established 12 LP2 Loop Port 2 Port 2 is not available on this LSI 0 Open 1 Closed 11 COMP1 Communication on Port 1 0 No stable communication 1 Communication established 10 LP1 Loop Port 1 0 Open 1 Closed COMPO Communication on Port 0 0 No stable communication 1 Communication established LPO Loop Port 0 0 Open 1 Closed PHYP3 Physical link on Port 3 Port 3 is not available on this LSI 0 No link 1 Link detected PHYP2 Physical link on Port 2 Port 2 is not available on this LSI 0 No link 1 Link detected PHYP1 PHYPO Physical link on Port 1 0 No link 1 Link detected Physical link on Port 0 0 No link 1 Link detected R18UZ0003EJ0301 Dec 25 2014 Page 64 of 203 R IN32M3 EC User s Manual 6
179. oston 7 0 WDCNTPDI Watchdog PDI counter counting is stopped when OxFF is reached Counts if PDI Watchdog expires Cleared if one of the Watchdog counters 0x0442 0x0443 is written Initial Value 00H R18UZ0003EJ0301 Dec 25 2014 Page 83 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 16 GI EEPROM Interface Registers EtherCAT controls the SII EEPROM interface if EEPROM configuration register 0x0500 0 0 and EEPROM PDI Access register 0x0501 0 0 otherwise PDI controls the EEPROM interface 6 16 1 EEPROM Configuration register EEP_CONF This register is used to configure EEPROM access 7 6 5 4 3 2 1 0 Address Initial Value H 3 EEP CONF 0 LI a 400E 0500H 00H O 5 e 5 ECAT 0 0 0 0 0 0 RW RW PDI 0 0 0 0 0 0 R R Bit position Bit name Function 1 FORCEECAT Force ECAT access 0 Do not change Bit 0x0501 0 1 Reset Bit 0x0501 0 to 0 0 CTRLPDI EEPROM control is offered to PDI 0 no 1 yes PDI has EEPROM control 6 16 2 EEPROM PDI Access State register EEP_STATE This register is used to configure EEPROM access from PDI 7 6 5 4 3 2 1 0 Address Initial Value VD 2 e KEKEE iu 7 a S ECAT 0 0 0 0 0 0 0 R PDI 0 0 0 0 0 0 RAW 0 Bit position Function PDIACCEES Access to EEPROM 0 PDI releases EEPROM access 1 PDI takes EEPROM access PDI has EEPROM control R18UZ0003EJ0301 Page 84 of 203 Dec 25 2014 R IN
180. r Page 142 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 9 Register 16 Silicon Revision Register PHY Address 10H MR16 RESERVED SILICON REVISION RESERVED Initial Value 0040H Bit Position Bit Name Function 15 10 RESERVED Reserved Write 0 and ignore reading SILICON REVISION Shows silicon revision RESERVED Reserved Write 0 and ignore reading R18UZ0003EJ0301 Page 143 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 10 Register 17 mode control status Register 1 2 l PHY Address E Zz Q E O il oO SR e SIE E 21 u EEE Wa wi oO EEN z E 2 Z 1 a BN WE o 1 5 ee iti MR17 Q Li O Le O O Z x E gt T Initial Value Li AGS 9 o 1 35 Mi o Bl Uo o Li a SR WEN SEW He Lo a GJ E Wa 0080H ul oc a s m T o9 Cla BU EAS o E au 9 E Z Z gx s Ea E ls Bit Position FASTRIP NASR Bit Name RESERVED Function Reserved Write 0 and ignore reading FASTRIP Set 10BASE T fast mode Only simulation can be used 0 Normal operation 1 PHYT 10 test mode EDPWRDOWN RESERVED Enable disable the settings of power down mode for energy detection 0 Disabled 1 Enabled Reserved Write 0 and ignore reading LOWSQEN Low squelch setting 0 Normal operation 1 Low down the threshold Increase sensitivity of signal RESERVED
181. rames will lead to invalid frames R18UZ0003EJ0301 Page 78 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 14 2 Forwarded Rx Error counter n register FWD RX ERR COUNTn This register counts forwarded RX frames errors 7 6 5 4 3 2 1 0 Address Initial Value FWD_RX_ 400E 0308H FWDERRCNT 00H ERR_COUNTn 0001H n ECAT RAW clr Bic Hier R W cl Bic RAW cl Bic RA clr PDI R R R R R R R R FWDERRCNT Forwarded error counter of Port n counting is stopped when OxFF is reached Cleared if one of the RX Error counters 0x0300 0x030B is written Note n 0 1 n 0 Port 0 n 1 Port 1 6 14 3 ECAT Processing Unit Error Counter register ECAT_PROC_ERR_COUNT This register counts error frame errors passing ECAT Processing Unit 7 6 5 4 3 2 1 0 Address Initial Value ECAT_PROC_ EPUERRCNT 400E 030CH 00H ERR_COUNT ECAT RMWclr R W clr Bic R MW clr R W clr R W clr Bic RAM clr PDI R R R R R R R R Bit poston 7 0 EPUERRCNT ECAT Processing Unit error counter counting is stopped when OxFF is reached Counts errors of frames passing the Processing Unit e g FCS is wrong or datagram structure is wrong Cleared if register is written R18UZ0003EJ0301 Page 79 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 14 4 PDI Error Counter register PDI ERR COUNT This register counts PDI access errors 7
182. rantees reading a consistent value R18UZ0003EJ0301 Page 122 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 21 ETC Registers 6 21 1 PRODUCT ID register PRODUCT ID This register indicates product ID 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address 400E OEOOH PRODUCT Initial Value PROID ID 0001 0000 0000 0000H ECAT R RR RR RR RR RR RR RR RR RR RR RR RR R RR RR RR PDI RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR RR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 10 PROID Bit position Function o PROD Producti 6 21 2 Vender ID register VENDOR_ID This register indicates vendor ID 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address 400E OE08H VENDOR Initial Value 0 0 0 0 0 0 0 0 ID 0000 0000 0000 0000H ECAT 00000000000000000000000000000000 PDI 000000000000000000 Oo o 0 0 0 0 0 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 54 3 2 1 0 VENDORID ECAT R R R RR RR RR RR RR RR RR RR RR RR RR RR RR PDI R R R R R R R R Bit position Function VENDORID Vendor ID R18UZ0003EJ0301 Page 123 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 21 3 User RAM USER RAM 6 EtherCAT Slave Controller function This register indicates the
183. ress m SMm P_START_ADR 400E 0800H 0008H m SyncManager Length m SMm LEN 400E 0802H 0008H m SyncManager Control m SMm CONTROL 400E 0804H 0008H m SyncManager Status m SyncManager Activate m SMm STATUS SMm ACT 400E 0805H 0008H m 400E 0806H 0008H m SyncManager PDI Control m R18UZ0003EJ0301 Dec 25 2014 SMm PDI_CONT 400E 0807H 0008H m Page 47 of 203 R IN32M3 EC User s Manual 15 Distributed Clocks Registers 6 EtherCAT Slave Controller function Register name Shortcut bits Address DC Receive Times registers Receive Times Porto DC RCV TIME PORTO 32 400E 0900H Receive Times Port1 DC RCV TIME PORTI 32 400E 0904H DC Time Loop Control Unit registers System Time DC SYS TIME 64 400E 0910H Receive Time ECAT Processing Unit DC RCV TIME UNIT 64 400E 0918H System Time Offset DC SYS TIME OFFSET 64 400E 0920H System Time Delay DC SYS TIME DELAY 32 400E 0928H System Time Difference DC SYS TIME DIFF 32 400E 092CH Speed Counter Start DC SPEED COUNT START 16 400E 0930H Speed Counter Diff DC SPEED COUNT DIFF 16 400E 0932H System Time Difference Filter Depth DC SYS TIME DIFF FIL DEPTH 8 400E 0934H Speed Counter Filter Depth DC SPEED COUNT FIL DEPTH 8 400E 0935H DC Cyclic Unit Control registers Cyclic Unit Control DC CYC CONT 400E 0980H DC SYNC Out Unit registers Activation
184. rtner error 0 No error detected 1 Link partner error READERR LINKSTAERR Read error 0 No read error occurred 1 A read error has occurred Cleared by writing any value to at least one of the PHY Status Port n registers Link status error 0 No error 1 Link error link inhibited LINKSTA Link status 100 Mbit s Full Duplex Autonegotiation 0 No link 1 Link detected PHYLINKSTA Physical link status PHY status register 1 2 0 No physical link 1 Physical link detected Note1 n 0 1 n 0 Port 0 n 1 Port 1 2 Write access depends on assignment of MI ECAT PDI R18UZ0003EJ0301 Dec 25 2014 Page 92 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 18 FMMU Registers 6 18 1 FMMU Logical Start Address m register FMMUm L_START_ADR This register is used to set the logical start address within the EtherCAT Address Space 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1413 12 1110 9 8 7 6 5 43 2 1 0 Address 400E 0600H FMMUm 0010H m L START LSTAADR Initial Value ADR 0000 0000H ECAT RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R W RW R W R W RW R W R W R W RW RW R W R W R W RW R W R W R W PDI R R R R R R RR Bit position Function LSTAADR Logical start address within the EtherCAT Address Space Note m 0 7 6 18 2 FMMU Length m register FMMUm LEN This register is used to set the length for FMMU area 15 14 13
185. rupt 1 SyncManager 3 interrupt pending SMINT2 SyncManager 2 interrupts SyncManager register offset 0x5 bit 0 No SyncManager 2 interrupt 1 SyncManager 2 interrupt pending SMINT1 SyncManager 1 interrupts SyncManager register offset 0x5 bit 0 No SyncManager 1 interrupt 1 SyncManager 1 interrupt pending SMINTO SyncManager 0 interrupts SyncManager register offset 0x5 bit 0 No SyncManager 0 interrupt 1 SyncManager 0 interrupt pending Watchdog Process Data 0 Has not expired 1 Has expired Bit is cleared by reading Watchdog Status Process Data 0x0440 from PDI 4 SYNCACT SyncManager activation register SyncManager register offset 0x6 changed 0 No change in any SyncManager 1 At least one SyncManager changed Bit is cleared by reading SyncManager Activation registers 0x0806 etc from PDI 3 DCSYNC1STA State of DC SYNC1 if register 0x0151 7 1 Bit is cleared by reading of SYNC1 status 0x098F from PDI 2 DCSYNCOSTA State of DC SYNCO if register 0x0151 3 1 Bit is cleared by reading SYNCO status 0x098E from PDI 1 DCLATCH DC Latch event 0 No change on DC Latch Inputs 1 At least one change on DC Latch Inputs Bit is cleared by reading DC Latch event times from PDI for PDI controlled Latch Units so that Latch 0 1 Status OxO9AE 0x09AF indicates no event 0 ALCTRL AL Control event 0 No AL Control Register change 1 AL Control Register has been written Bit is cleared by reading AL Contro
186. s 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 43 2 1 0 Address 5 BASE 06A4H C ae i a a Initial Value PHYPUS o o o o o o o o o o o o ele 0000 0000H a 0 o ajo R W 00000000000000000000000000000 0 R R Function P1PWRUPRST Inform the completion of the power up of the built in Ethernet PHY POPWRUPRST 1 Power up and reset 0 Power up is complete R18UZ0003EJ0301 Page 160 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 8 Port function 8 1 Features Number of I O ports 96 amp Can function alternately as the I O pins of other peripheral functions Input or output can be specified by bit unit R18UZ0003EJ0301 Page 161 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 2 Port configuration 8 Port function The R IN32M3 EC incorporates eight ports of 3 state I O port and four real time control ports Input or output mode can be specified for ports in 1 bit units Each port basically consists of 8 bits but ports 0 to 3 can also be aligned to enable reading and writing in 32 bit units The real time ports RP00 to RP37 can be used for I O in synchronization with interrupt signals Each port has the registers shown below each of which is used to set the I O mode and specify the use of the alternate function of the port The basic circuit configuration is shown in Figure 8 1 Register name Port regis
187. s 0x0516 0 x0517 0 Only ECAT control 1 PDI control possible 0 WREN Write enable 0 Write disabled 1 Write enabled This bit is always 1 if PDI has MI control Note Write access depends on assignment of MI ECAT PDI Write access is generally blocked if Management interface is busy 0x0510 15 1 R18UZ0003EJ0301 Page 88 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function Caution Write enable bit 0 is self clearing at the SOF of the next frame or at the end of the PDI access Command bits 9 8 are self clearing after the command is executed Busy ends Writing 00 to the command register will also clear the error bits 14 13 The Command bits are cleared after the command is executed 6 17 2 PHY Address register PHY_ADR This register is used to set PHY address PDI 0 0 RW RAW 7 6 5 4 3 2 1 0 Address Initial Value PHY_ADR 0 fe PHYADDR 400E 0512H 00H ECAT 0 0 0 RAW RAW RAW RW RAW 0 PHYADDR PHY address Note Write access depends on assignment of MI ECAT PDI Write access is generally blocked if Management interface is busy 0x0510 15 1 6 17 3 PHY Register Address register PHY REG ADR This register is used to set PHY register address 7 6 5 4 3 2 1 0 Address Initial Value PHY_REG_ 0 PHYREGADDR 400E 0513H 00H ADR ECAT 0 0 0 RAW RAW RAW R W R W PDI 0 0 0 R W R W R W R W R W Fu
188. s intended for users who wish to understand the functions of Industrial Ethernet network LSI R IN32M3 EC MC 10287F1 HN4 A for designing application of it It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering logic circuits and microcontrollers Particular attention should be paid to the precautionary notes when using the manual These notes occur within the body of the text at the end of each section and in the Usage Notes section The revision history summarizes the locations of revisions and additions It does not list all revisions Refer to the text of the manual for details Literature Literature may be preliminary versions Note however that the following descriptions do not indicate Preliminary Some documents on cores were created when they were planned or still under development So they may be directed to specific customers Last four digits of document number described as indicate version information of each document Please download the latest document from our web site and refer to it The document related to R IN32M3 EC Document name Document number R IN32M3 series Datasheet R18DS0008EJ R IN32M3 CL User s Manual R18UZ0005EJ R IN32M3 series User s Manual Peripheral function R18UZ0007EJ R IN32M3 Series Proguraming Manual OS edition R18UZ0011EJ R IN32M3 Series Proguraming Manual Driver edition R18UZ0009EJ R IN32M3 EC User
189. s settings to MII management register with Ethernet PHY internal 7 Etherne PHY Function the Ethernet PHY This register can be accessed by either the MIIM register of on chip Ethernet MAC or MII Management Interface register of EtherCAT Slave Controller via the serial management interface from each MAC Table 7 1 Caution Register 8 15 are the mirror of register 24 31 and the entity of register 8 15 do not exit Access to register 8 15 is prohibited Summary of PHY MII Management registers Register address Register name type 0 Control Register Basic 1 Status Register Basic 2 PHY Identifier Extension 3 PHY Identifier Extension 4 Auto Negotiation Advertisement Register Extension 5 Auto Negotiation Link Partner Ability Register Extension 6 Auto Negotiation Expansion Register Extension 7 Auto Negotiation Next Page Transmit Register Extension 8 Unsupported Access prohibited for the mirror of register 24 9 Unsupported Access prohibited for the mirror of register 25 10 Unsupported Access prohibited for the mirror of register 26 11 Unsupported Access prohibited for the mirror of register 27 12 Unsupported Access prohibited for the mirror of register 28 13 Unsupported Access prohibited for the mirror of register 29 14 Unsupported Access prohibited for the mirror of register 30 15 Unsupported Access prohibited for the mirror of register 31 Silicon
190. ser s Manual REVISION HISTORY REVISION R IN32M3 EC User s Manual HISTORY Rev Date Description Page Summary 1 00 2013 2 8 First edition issued Preliminary 1 00 Apr 03 2013 overall Modification of English expressions overall Change the description of CC Link CC Link Slave CC Link Remote device station 1 Modification of the contents of 7 1 Introduction 3 Standby mode deletion of Table1 1 Overview of R IN32M3 EC 9 Modification of the status of BUSCLK during the reset of 2 1 2 External Memory Interface Signals Addition of synchronous burst access MEMC information of 2 1 2 External Memory Interface Signals 10 Modification of the status of HDO HD15 HBCYSTZ during the reset of 2 1 3 External MPU Interface Signals 21 Modification of PONRZ function of 2 1 16 System Signals Addition the signals of HOTRESETZ VDDQ MI of 2 1 16 System Signals 24 Modification of the status of P40 of 2 2Port status Modification of the contents of Note1 and Note2 of 2 2Port status 1 01 Dec 09 2013 overall Modification of the supported station of CC Link 2 00 Feb 07 2014 4 Addition of a connection of GPIO block and DMAC_RTPORT bus of 7 3 Internal block diagram Addition of a connection of RealTimeGPIO block and DMAC bus of 1 3 Internal block diagram 6 24 Addition the status after reset timing of 2 1 Signals by function 21 Add CCM CLK80M pins to list of 2 1 15 CC Link Signals Remote de
191. ser s Manual 6 EtherCAT Slave Controller function 6 18 5 FMMU Physical Start Address m register FMMUm P START ADR This register is used to set physical start address of the ESC for FMMU area 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value FMMUm PHYSTAADR 400E 0608H 0000H P_START_ADR 0010H m ECAT RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW PDI R R R R R R R R R R R R R R R R Bit position Function 15 0 PHYSTAADR Physical Start Address mapped to logical Start address Note m 0 7 6 18 6 FMMU Physical Start bit m register FMMUm P START BIT This register is used to set physical starting bit of the ESC for FMMU area 7 6 5 4 3 2 1 0 Address Initial Value FMMUm 0 PHYSTABIT 400E 060AH 00H P_START_BIT 0010H m ECAT 0 0 0 0 0 RW R W R W PDI 0 0 0 0 0 R R R Function 2 0 PHYSTABIT Physical starting bit as target of logical start bit mapping bits are counted from least significant bit 0 to most significant bit 7 Note m 0 7 R18UZ0003EJ0301 Page 95 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 18 7 6 EtherCAT Slave Controller function FMMU Type m register FMMUm TYPE This register is used to set FMMU access type 7 6 FMMUm 0 TYPE ECAT 0 0 PDI 0 0 Bit position Bit name 5 4 3 2 1 0 Address Initial Value 400E 060BH Ww 00H bE QO 0010H m E li ra 0 0 0 0 RW RW 0 0 0 0 R R Function Write access mapping 0 Ignore mapping for wr
192. ss 02H MR2 PHY ID NUMBER Initial value 0033H R R R R R R R R R R R R R R Bit Position Bit Name Function Register 2 3 PHY Identifier Register 2 3 shows the identification number of PHY by 32 bit in total 7 Etherne PHY Function 3rd to 18th bit of OUI MR3 PHY ID NUMBER Bit Position Bit Name PHY ID NUMBER MODEL NUMBER 19th to 24th bit of OUI Function PHY Address 03H REVISION NUMBER Initial value 2002H MODEL NUMBER Manufacturer model number REVISION NUMBER R18UZ0003EJ0301 Dec 25 2014 Manufacturer revision number Page 137 of 203 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 4 4 Register 4 Auto Negotiation Advertisement Register Register 4 inform the partner when using auto negotiation mode MR4 NEXT PAGE RW Bit Position RESERVED REMOTE FAULT RESERVED R RW RW Bit Name NEXT PAGE RW PAUSE PHY Address x lt gt x lt z o x p O IEN E top p E 4 um 4 ka D SELECTOR FIELD Initial value Kal Kal cr 5 S lt 4 lt O1E1H olen r RW R RW RW RW RW RW RW RW RW RW Function Support Next Page function or not 0 Not supported 1 Supported RESERVED Reserved Write 0 and ignore reading REMOTE_FAULT Set the status of local device in remote fault detection function 0 Not fault 1 Fault RESERVED Reserved Write 0 and
193. ster indicates PDI configuration PDI CONFIG ONCHIPBUS ECAT PDI Bit position Bit name ONCHIPBUS ONCHIPBUSCLK Function On chip bus type This LSI indicates 010 6 EtherCAT Slave Controller function Address Initial Value 400E 0150H 44H ONCHIPBUSCLK On chip bus clock This LSI indicates 4 100MHz R18UZ0003EJ0301 Dec 25 2014 Page 72 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 12 4 SYNC LATCH PDI Configuration register SYNC LATCH CONFIG This register indicates the configuration of SYNC output and LATCH input 7 6 5 4 3 2 1 0 Address Initial Value SYNC_LATCH_ CONFIG 400E 0151H EEH SYNCOOUT ECAT PDI I SYNC1MAP D D SYNCLAT1 SYNC1OUT 2 D SYNCOMAP x 9 SYNCLATO Bit position Bit name Function SYNC1MAP SYNC1 mapped to AL Event Request register 0x0220 3 This LSI always indicates 1 0 Disabled 1 Enabled SYNCLAT1 SYNC1 LATCH1 configuration This LSI always indicates 1 0 LATCH1 input 1 SYNC1 output SYNC1OUT SYNC1 output driver polarity This LSI always indicates 10 Push Pull active high SYNCOMAP SYNCO mapped to AL Event Request register 0x0220 2 This LSI always indicates 1 0 Disabled 1 Enabled SYNCLATO SYNCO LATCHO configuration This LSI always indicates 1 Sie 0 LATCHO input 1 SYNCO output SYNCOOUT SYNCO output driver polarity This LSI always indicates 10 Push Pull active high
194. supported features dependent on IP core configuration The area is 128Byte from 400E OF80H to 400E OFFFH Value 1 of reset value means supported features But bit 7 0 indicate the number of bits defined in the User RAM The value of R IN32M3 EC is 33H Bit position Description Reset value 7 0 Number of extended feature bits This LSI indicates 51bits 33H 33H 8 Extended DL Control Register 0x0102 0x0103 1 9 AL Status Code Register 0x0134 0x0135 1 10 ECAT Event Mask 0x0200 0x0201 1 11 Configured Station Alias 0x0012 0x0013 1 12 General Purpose Inputs 0x0F18 0x0F1F 0 13 General Purpose Outputs 0x0F10 0x0F17 0 14 AL Event Mask 0x0204 0x0207 1 15 Physical Read Write Offset 0x0108 0x0109 1 16 Watchdog divider writeable 0x0400 0x04001 and Watchdog PDI 0x0410 0x0f11 1 17 Watchdog counters 0x0442 0x0443 1 18 Write Protection 0x0020 0x0031 1 19 Reset 0x0040 0x0041 1 20 Reserved 0 21 DC SyncManager Event Times 0x09F0 0x09FF 1 22 ECAT Processing Unit PDI Error Counter 0x030C 0x030D 1 23 EEPROM Size configurable 0x0502 7 1 0 EEPROM Size fixed to sizes up to 16 Kbit 1 EEPROM Size configurable Reserved Lost Link Counter 0x0310 0x0313 MII Management Interface 0x0510 0x0515 Enhanced Link Detection MIl Enhanced Link Detection EBUS Run LED DEV_STATE LED Link Activity LED Reserved Reserved Reserved Reserved
195. supported register FMMU NUM This register indicates the number of supported FMMU channels or entities of the EtherCAT Slave Controller 7 6 5 4 3 2 1 0 Address Initial Value FMMU NUM NUMFMMU 400E 0004H 08H ECAT R PDI R R 7 0 NUMFMMU Number of supported FMMU channels or entities of the EtherCAT Slave Controller R R R R R R 6 7 5 SyncManagers supported register SYNC_MANAGER This register indicates the number of supported SyncManager channels or entities of the EtherCAT Slave Controller 7 6 5 4 3 2 1 0 Address Initial Value SYNC_ NUMSYNC 400E 0005H 08H MANAGER ECAT R R R R R R R R PDI R R R NUMSYNC Number of supported SyncManager channels or entities of the EtherCAT Slave Controller 6 7 6 RAM Size register RAM SIZE This register indicates the Process Data RAM size supported by the EtherCAT Slave Controller in Kbyte 7 6 5 4 3 2 1 0 Address Initial Value RAM SIZE RAMSIZE 400E 0006H 08H ECAT R PDI R R R R R R R R RAMSIZE Process Data RAM size supported by the EtherCAT Slave Controller in KByte R18UZ0003EJ0301 Page 54 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 7 7 Port Descriptor register PORT DESC This register indicates the port configuration Bit position 7 6 P3 7 ECAT R PDI R Bit name 6 5 4 3 2 1 Function Port3 configuration This LSI doesn t implement port3 00 Not implemented
196. t back attenuated in opposite phase as shown in Figure 7 3 send pulse gt YA NNN III PHY AAA k TT receive pulse 2 J MN Figure 7 2 Behavior of cable disconnected 1 send pulse me NY N N N N AO N rav VVVVVVVV PHY E A A A A A MUV UV A A proe f i receive pulse 2 Figure 7 3 Behavior of cable short circuited R18UZ0003EJ0301 Page 129 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 Etherne PHY Function The operation of TDR function is performed by using register 25 and register 26 as follows Disable the auto negotiation and auto crossover and set to 100Base Half Duplex at first It won t be measured correctly without this Then set the register with parameters related to pulse transmission and pulse detection whether TX line or RX line Pulse is sent by writing 1 to the DIAG INIT bit and the measurement is started after the configuration is complete The value of counter when pulse is detected is saved in DIAGCNT register and the information about open or short is saved in the DIAG POL register at this time The following shows an example of setting the parameters when measuring However please note that it is necessary to adjust some parameters depending on the configuration of hardware and the installation environment Cable length ADC TRIGGER CNT WINDOW PW DIAG Conditions of counter
197. t or less 1 32Kbit to 4Mbit Ll Ll BASE 0624H Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000H E I2CSIZ R18UZ0003EJ0301 Page 51 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 6 3 EtherCAT reset register CATRESET PHYMD register control the reset operation of EtherCAT EtherCAT is reset status when R IN32M3 is started Please released reset by this register after completion of shared port setting of EtherCAT In addition please reset EtherCAT again by this register when the reset interrupt occurs from EtherCAT This register can be read written in 32 bit units Caution1 This register can be written only in case of releasing protection by specific sequence using system protect command register SYSPCMD Please refer to system protect command register SYSPCMD for protection releasing procedure In addition the special sequence is not necessary in case of reading the value of this register Please refer to R IN32M3 User s Manual Peripheral functions edition for the detail of system protect command register SYSPCMD Caution2 Please release the reset after securing time to satisfy reset width to EtherPHY by software in case of reset ting EtherCAT again 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 5 43 2 1 0 Address BASE 0628H Initial Value CATRESET 10 010 0 010101010101010101010101010 0
198. ter reset TINO TOUTO I O Timer TAUJO port P27 Hi Z TIN1 TOUT1 I O Timer TAUJ1 port P26 TIN2 TOUT2 UO Timer TAUJ2 port P57 Hi Z With internal pull up resistor TING TOUT3 WO Timer TAUJ3 port P52 Hi Z With internal pull down resistor 2 1 10 Watchdog Timer Output Signals Pin Name Function Shared Active Level during reset amp Level after reset WDTOUTZ Watchdog Timer output port Low Hi Z 2 1 11 Trace Signals Pin Name Function Active Level during reset amp Level after reset TRACECLK Trace port clock output port TRACEDATAS TRACEDATAO 2 1 12 CPU Power Control Signals Pin Name VO Function Shared Active Level during reset amp Port Level after reset SLEEPING CPU SLEEP mode output port i Hi Z With internal pull up resistor R18UZ0003EJ0301 Page 18 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 Signals by function 2 1 13 Serial Interface Signals Pin Name UO Function Shared Port Active Level during reset amp Level after reset TXDO O UARTO serial data output port P21 Hi Z RXDO l UARTO serial data input port P20 TXD1 O UART1 serial data output port P31 Hi Z RXD1 l UART1 serial data input port P30 With internal pull up CSISCKO I O CSIO serial clock port P45 resistor CSISIO l CSI0 serial data input port P46 CSISOO O CSIO serial data output port P47 CSICS00 CSICSO1 O CSIO chip select 0 1 port P70 P71 Low Hi Z
199. ters Pn RPm Purpose and operation Read Used to read the value of the output latch Write Used to set a value to the output latch Port mode registers PMn RPMm Port mode control registers PMCn RPMCm Used to read whether the port is in input or output mode Used to read whether the port is used as a port or as an alternate function pin Used to set the port to input or output mode Used to specify whether to use a port as a port or for an alternate function Port function control registers PFCn RPFCm Used to read which alternate function of the port is selected if the port has more than one alternate function Used to specify which alternate function of the port to be selected if the port has more than one alternate function Port function control expansion registers PFCEn RPFCEm Port pin input registers PINn RPINm Used to read which alternate function of the port is selected if the port has more than two alternate functions Used to read the input level of the port pin Used to specify which alternate function of the port to be selected in combination with the PFCn register setting if the port has more than two alternate functions Cannot be written Caution If a port that has multiple alternate functions including external interrupt input is set to control mode by using the PMCn register and if the alternate function is used in input mode
200. the applicable export control laws and regulations and follow the procedures required by such laws and regulations It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics Instructions for the use of product In this section the precautions are described for over whole of CMOS device Please refer to this manual about individual precaution When there is a mention unlike the text of this manual a mention of the text takes first priority 1 Handling of Unused Pins Handle unused pins i
201. the parameters before To end the operation of FEQ function write OxFFFF to FEQ DELTA When using an interrupt mask the interrupt by writing 0 to bit 9 of register 30 R18UZ0003EJ0301 Page 132 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 Etherne PHY Function 7 3 power down mode It has hardware power down mode software power down mode and energy detection power mode and each of the power down modes is described as follows 7 3 1 Hardware power down mode It can be shifted to hardware power down mode by setting 1 to bit 2 POPHYEN or bit 5 PIPHYEN of Ethernet PHY operation mode control register PHYMD Ethernet PHY does not work at all in hardware power down mode and MII management register can t be accessed The power consumption of the port will be almost 0 To wake up from the hardware power down mode set 0 to bit 2 POPHYEN orbit5 PIPHYEN of Ethernet PHY operation mode control register PHYMD When returning from the hardware power down mode both analog and digital circuits are initialized by Ethernet PHY and so is MII management registers 7 3 2 Software power down mode It can be shifted to software power down mode by setting I to bit 11 POWERDOWN of MII management register 0 with Ethernet PHY internal IDLE signal is not output in the transition of software power down mode and in software power down mode but MII management register can be accessed and controlled in software power down mode To wake up from
202. tions Support EtherCAT Protocol Handling the following frames O Ethernet frames with Ether type 0x88A4 EtherCAT frames encapsulated in UDP IP EtherCAT frames with VLAN Tag Normal Ethernet frames Addressing Modes Device Addressing O Auto Increment Address Configured Station Address Broadcast Logical Addressing O Working Counter Counting the number of Read Write from to the device O EtherCAT Command Processing the command that master requests slaves to address each O Types addressing mode Loop Control Loop Control and Loop State Shadow buffers Shadow buffers function when register is written Circulating Frames Processing of circulating frames during the failure Link Detection Link MII signal MI Link Detection and Configuration Enhanced Link Detection FIFO size reduction Ethernet Physical Layer RX FIFO size reduction because of reduction of propagation delay MII MDI 100BASE TX MDI 100BASE FX EBUS Back to Back MII connection MII Management Interface Read Write of the PHY register via MII Management Interface PHY address offset Manual TX clock shift compensation Automatic TX clock shift compensation FMMU Mapping between logical address and physical address SyncManager R18UZ0003EJ0301 Dec 25 2014 Buffered Mode Mailbox Mode Interrupt and latch event generation when a buffer was completely and successfull
203. tive 2 Signals by function Level during reset amp Port Level after reset CATLEDRUN O Ether CAT RUN LED port P00 High Hi Z CATIRQ O Ether CAT IRQ port NO High CATLEDSTER O Ether CAT Dual color State LED port P02 High CATLEDERR O Ether CAT Error LED port P03 High CATLINKACTO O Ether CAT Link Activity LED port P04 P05 High CATLINKACT1 CATSYNC1 O Ether CAT SYNC1 port P10 High Hi Z With internal pull up resistor CATSYNCO O Ether CAT SYNCO port P11 High Hi Z With internal pull down resistor CATLATCH1 Ether CAT LATCH1 port Hi Z With internal pull up resistor CATLATCHO Ether CAT LATCHO port P11 High Hi Z With internal pull down resistor CATI2CCLK O Ether CAT EEPROM 12C clock port P22 Hi Z CATI2CDATA IO Ether CAT EEPROM I2C data port P23 CATRESTOUT O Ether CAT PHY RESETOUT port P56 Hi Z With internal pull up resistor R18UZ0003EJ0301 Page 8 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 Signals by function 2 1 3 External Memory Interface Signals Shared Shared Level during Level after Pin Name IO Function Active Signal port reset reset BUSCLK O Bus clock output port CSZ0 O Chip select signal output HCSZ Low Hi Z High CSZ1 O port HPGCSZ P44 With Hi Z CSZ2 O P51 internal With CSZ3 O P50 pull up internal resistor pull up resistor A1 O Address output port HA1 P40
204. tment A write access resets System Time Difference 0x092C 0x092F and Speed Counter Diff 0x0932 0x0933 Valid range 0x0080 to Ox3FFF R18UZ0003EJ0301 Page 106 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 20 2 7 6 EtherCAT Slave Controller function Speed Counter Diff register DC SPEED COUNT DIFF This register indicates the deviation between local clock period and Reference Clock s clock period 15 14 13 DC SPEED COUNT_DIFF ECAT R R R PDI R R R 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial Value SPDCNTDIFF 400E 0932H 0000H Bit poston 15 0 SPDCNTDIFF Representation of the deviation between local clock period and Reference Clock s clock period representation two s complement Range Speed Counter Start 0x7F 6 20 2 8 System Time Difference Filter Depth register DC SYS TIME DIFF FIL DEPTH This register is used to set filter depth for averaging the received System Time deviation 7 6 DC SYS TIME DIFF 0 0 FIL_DEPTH ECAT 0 0 PDI 0 0 SYSTIMDEP 5 4 3 2 1 0 Address Initial Value 0 0 SYSTIMDEP 400E 0934H 04H 0 0 R W R W R W R W 0 0 R R R R Function Filter depth for averaging the received System Time deviation A write access resets System Time Difference 0x092C 0x092F R18UZ0003EJ0301 Dec 25 2014 Page 107 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 2 9 Speed Counter Filter Depth register DC SPEE
205. ue is written to that port s output latch Pn or RPn However the pin status does not change because the output buffer is off The value written to the output latch is held until another value is written To read the input level read port pin input register n PINn or RPINn 8 6 2 Alternate function pin output status in control mode The port pin level can be read directly by reading port pin input register n PINn or RPINn regardless of the settings in the PMCn PMn PFCn and PFCEn registers R18UZ0003EJ0301 Page 201 of 203 Dec 25 2014 R IN32M3 EC User s Manual 8 Port function 8 7 Trigger synchronous ports PPOO to RP37 The status of the 32 bit port pins RP00 to RP37 is updated in synchronization with an interrupt from an on chip peripheral function Use the RPTRGMD register to specify whether to set a port to trigger synchronous port control mode in 1 bit units To select the trigger use the RPTFRO to RPTFR3 registers For details see R IN32M3 User s Manual Peripheral Functions PORT RTGPIO RPxx Interrupt select cuircuit RPTRGMD Register Figure 8 19 Configuration of Trigger Synchronous Ports R18UZ0003EJ0301 Page 202 of 203 Dec 25 2014 R IN32M3 EC User s Manual 9 Electrical Specifications 9 Electrical Specifications Please refer to R IN32M3 series datasheet for the Electrical Specifications R18UZ0003EJ0301 Page 203 of 203 Dec 25 2014 R IN32M3 EC U
206. unction 6 9 3 ESC Write Enable register ESC WR ENABLE This register is used to release the write protection temporarily when ESC Write Protection is enabled 7 6 5 4 3 2 1 0 Address Initial Value ESC_WR_ Li 0 0 a 400E 0030H 00H ENABLE Es E Li ECAT 0 0 0 0 0 0 0 R W PDI 0 0 0 0 0 0 R 0 TE Function ENABLE If ESC write protection is enabled this register has to be written in the same Ethernet frame value does not care before other writes to this station are allowed ESC write protection is still active after this frame if ESC Write Protection register is not changed 6 9 4 ESC Write Protection register ESC_WR_PROTECT This register is used to protect from writing register and Process Data RAM The area 400E 0000H to 400E 2FFFH are write protected excluding 0x0020 and 0x0030 7 6 5 4 3 2 1 0 Address Initial Value HL ESC WR Ge 0 0 E 400E 0031H 00H PROTECT Q E D ECAT 0 0 0 0 0 0 0 RW PDI 0 0 0 0 0 0 R 0 Sg Sege PROTECT Write protect 0 Protection disabled 1 Protection enabled All areas are write protected except for 0x0030 R18UZ0003EJ0301 Page 59 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 10 Data Link Layer Registers 6 10 1 ESC Reset ECAT register ESC_RESET_ECAT This register is used to reset the EtherCAT Slave Controller from ECAT master by software Write 7 6 5 4 3 2 1 0 Address Initial Value ESC_RESET_ RESE
207. unction PINSTATE Latch1 pin state EVENTNEG Event Latch1 negative edge 0 Negative edge not detected or continuous mode 1 Negative edge detected in single event mode only Flag cleared by reading out Latch1 Time Negative Edge 0 EVENTPOS Event Latch1 positive edge 0 Positive edge not detected or continuous mode 1 Positive edge detected in single event mode only Flag cleared by reading out Latch1 Time Positive Edge R18UZ0003EJ0301 Page 116 of 203 Dec 25 2014 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 20 5 5 LatchO Time Positive Edge register DC LATCHO TIME POS This register indicates System time at the positive edge of the LatchO signal 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address 400E 09BOH DC_ Initial Value LATCHO_ SYSTIME 0000 0000 TIME_POS 0000 0000H ECAT Black R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack PDI R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack R ack Black R ack R ack R ack R ack R ack R ack R ack R ack Black R ack R ack R ack R ack R ack 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109 8 7 6 54 3 2 1 0 SYSTIME ECAT R ack R
208. upt output port P35 Low CCM WDTENZ I Watchdog Timer error input port P13 Low CCM MSTZ O Operation check LED port P37 Low CCM_SMSTZ O Stand by master LED control port RPO1 Low CCM RD Data receive port P53 CCM SD O Data transfer port P54 CCM SDGCZ O Transfer data amp gate control port P42 Low CCM CLK80M CC Link Clock R18UZ0003EJ0301 Page 20 of 203 Dec 25 2014 R IN32M3 EC User s Manual 2 Signals by function 2 1 15 CC Link Signals Remote device station Caution To use a remote device station it is necessary to connect a CCS_REFSTB terminal to an external interrupt terminal INTPZ Pin Name VO Function Shared Active Level during reset amp Port Level after reset CCS MON1 O Monitor port P32 P34 Hi Z CCS MON3 With internal pull up resistor CCS MON4 O Monitor port P11 Hi Z With internal pull down resistor CCS MONO O Monitor port P06 Hi Z CCS MON5 O Monitor port P03 P05 CCS_MON7 CCS_RESOUT O reset port P07 High CCS IOTENSU l Initial setting port P22 CCS SENYUO l Initial setting port P23 CCS SENYU1 l Initial setting port P24 CCS ERRZ O Operation check LED port P25 Low CCS RUNZ O Operation check LED port P26 Low CCS STATION NO 0 Station No setting switch port P70 P77 CCS STATION NO 7 CCS LNKRUNZ O Link RUN LED control port P50 Low Hi Z CCS REFSTB O Interrupt port P10 H
209. ut INTPZ9 INTPZ9 input INTPZ10 INTPZ10 input INTPZ11 INTPZ11 input INTPZ12 INTPZ12 input INTPZ13 INTPZ13 input INTPZ14 INTPZ14 input INTPZ15 INTPZ15 input INTPZ16 INTPZ16 input INTPZ17 INTPZ17 input INTPZ18 INTPZ18 input INTPZ19 INTPZ19 input Oo O o o o O O OD O O O O O ODO ODO OD OD ODO O O O Oo o o o o ODO ODO OD DO O O O O ODO ODO OD OD DO O O O Oo Oo o o o OD OD OD O O O O O ODO ODO OD OD ODO O O O Oo Oo o o o OD ODO OD DO O O O O ODO ODO OD OD DO O O O Oo o o o o OD OD OD DO O O O O ODO ODO OD OD DO O O O R18UZ0003EJ0301 Page 36 of 203 Dec 25 2014 INTPZ20 R IN32M3 EC User s Manual Cause group INTPZ20 input 4 Exception handling function O Connection 3 4 INTPZ21 INTPZ22 INTPZ21 input INTPZ22 input INTPZ23 INTPZ23 input INTPZ24 INTPZ24 input INTPZ25 INTPZ25 input INTPZ26 INTPZ26 input INTPZ27 INTPZ27 input INTPZ28 INTHWRTOS INTBRAMERR INTPZ28 input HW RTOS interrupt Buffer RAM area access error Oo Oo O0 O0 0 O0 O O O O Oo Oo O0 0 O0 OD O O O O O0 0 O0 O O O O Oo O O0 0 O0 O O O O O O O0 0 O0 O O O O INTIICBOTIS I2CO status interrupt O O O INTSFLASH Serial Flash ROM controller error interrupt 95 INTIICB1TIS I2C1 status interrupt 96
210. value Below 20m 10 15 DIAGCNT 255 and DIAGCNT 42 20m 40m 30 DIAGCNT 255 and 32 lt DIAGCNT 68 DIAGCNT 255 and 56SDIAGCNT lt 88 DIAGCNT 255 and at ka 78 lt DIAGCNTS114 DIAGCNT 255 and 5 More than 80m 8 75 12 106SDIAGCNT R18UZ0003EJ0301 Page 130 of 203 Dec 25 2014 R IN32M3 EC User s Manual 7 Etherne PHY Function ekveki Calculato distance r No1 use Send Pulse to TX Parameter No 1 use Send Pulse to TX r No 2 use I Send Pulse to RX Parameter No 3 use Send Pulse to TX Parameter No 4 use lo Yes 56 lt DIAGCNT lt 8 No H i Calculate distance Measure complete Yes Calculate distance Send Pulse to RX Parameter No 4 use Measure complete Calculate distance Ker Measure complete Yes No 32 lt DIAGCNT lt 68 No si R ato RX Calculate distance r No 2 use I N lo 32 lt DIAGCNT 68 No Measure complete Yes Send Pulse to TX r No3 use I Calculate distance Send Pulse to TX Parameter No 5 use Measure complete Yes Send Pulse to RX Parameter No 5 use Calculate distance DIAGCNT 255 Measure complete No 56 lt DIAGCNT lt 88 No Calculate distance ar Yes leo Measure complete Figure 7 4 cable diagnostic process flow R18U
211. vice Station 22 Deletion the description about VDDQ_MIl of 2 1 16 System Signals 24 Modification of Boot mode select of 2 1 18 Operation mode Setting Signals 25 Addition Synchronous burst MEMC of 2 2 Port status 28 29 Addition of a resister value of Pull up down of 2 3 5 Port Signals Modification of a description of the drive current of P10 P30 P31 P52 of 2 3 5 Port Signals Modification of title name of 2 3 7 CC Link Signal Intelligent device station Remote device station Modification of the end address of EtherCAT area of Fig 3 1 Memory Map ALL Modification of the end address of EtherCAT area of Fig 3 5 External MPU interface area Addition of the contents of Note of INTCCSRFSTB register of 4 2 Inerruput list Adidtion 6 2 Peripheral circuit of EtherCAT Addition 7 Ether PHY Function Modification of initial value of Fig 8 7 Port mode registers REVISION 1 R IN32M3 EC User s Manual REVISION HISTORY Rev Date Description Page Summary 2 01 Apr 18 2014 overall Modification of CC Link Signals Remote device station 60 Modification of the contents of ACKNOWLEDGEbit of 7 4 5 Register 5 Auto Negotiation Link Partner Ability Base Page Register 3 00 Jun 30 2014 22 Modification of attribution of FB of 2 1 16 System Signals 30 Modification of the end address of EtherCAT area of Fig 3 1 Memory Map ALL 33 Modification of the end address of EtherCAT area of Fig 3 5 Exter
212. vice station V2 0 INTCCSRFSTB can not be used It is necessary to connect a CCS_REFSTB P10 terminal to an external interrupt terminal INTPZ R18UZ0003EJ0301 Page 38 of 203 Dec 25 2014 R IN32M3 EC User s Manual 5 Peripheral function functions Clock function CPU Bus structure Hardware Real time OS Giga bit Ethernet I F Asynchronous SRAM MEMC Synchronous burst access MEMC Serial Flash ROM MEMC DMA function Timer Array Unit J TAUJ Window Watchdog Timer A WDTA Asynchronous Serial Interface J UARTJ Clocked Serial Interface H CSIH DC BUS IICB CAN Controller FCN CC Link Intelligent device station CC Link Remote device station Other I F control Debug function R18UZ0003EJ0301 Dec 25 2014 5 Peripheral function Please refer to R IN32M3 User s Manual Peripheral functions edition for the detail of following peripheral Page 39 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 6 EtherCAT Slave Controller function 6 1 Features The EtherCAT Slave Controller ESC core is made by Beckhoff Automation GmbH Germany The ESC processes EtherCAT communications and acts as interface between EtherCAT Field bus and Slave applications Table 6 1 Features of EtherCAT Slave Controller Feature R IN32M3 EC ET1100 Remark Ports FMMUs SyncManagers Process Data RAM KByte Distributed Clocks 64bit 64bit EBus No Yes 0 4
213. y TAUJ2 channel 1 interrupt O O O O O 18 INTTAUJ212 Timer array TAUJ2 channel 2 interrupt O O O O O 19 INTTAUJ2I3 Timer array TAUJ2 channel 3 interrupt O O O O O 20 INTUAJOTIT UARTJO transmission interrupt O O O O O 21 INTUAJOTIR UARTJO reception interrupt O O O O O 22 INTUAJITIT UARTJI1 transmission interrupt O O O O O 23 INTUAJ1TIR UARTJ1 reception interrupt O O O O O 24 INTCSIHOIC CSIHO communication status interrupt O O O O O 25 INTCSIHOIR CSIHO reception status interrupt O O O O O 26 INTCSIHOIJC CSIHO end of job interrupt O O O O O 27 INTCSIH1IC CSIH1 communication status interrupt O O O O O 28 INTCSIH1IR CSIH1 reception status interrupt O O O O O 29 INTCSIH1IJC CSIH1 end of job interrupt O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O INTFCNOWUP FCNO sleep and wakeup transmission suspension INTFCN1REC FCN1 reception completion O O O O O INTFON1TRX INTFCN1WUP FCN1 transmission completion FCN1 sleep and wakeup transmission suspension OJO OJO OJO OJO INTDMAOO DMAC channel0 transfer completion interrupt INTDMAO1 DMAC channel transfer completion interrupt INTDMAO2 INTDMAO3 DMAC channel transfer completion interrupt DMAC channel3 transfer completion interrupt INTRTDMA RTDMAC transfer completion interrupt INTCATSYNCO EtherCAT Synco interrupt INTCATSYNC1 EtherCAT Sync1 interrupt INTCAT R
214. y written or read Repeating Mailbox Communication SyncManager Deactivation by the PDI Page 42 of 203 R IN32M3 EC User s Manual 6 EtherCAT Slave Controller function 2 3 Features Functions Support Distributed Clocks Clock Synchronization considering propagation delay and drift compensation O Generation of synchronous output signals SyncSignals O Cyclic Generation Single Shot Mode Cyclic Acknowledge Mode Single Shot Acknowledge Mode Precise time stamping of input events LatchSignals O Single Event Mode Continuous Mode SyncManager Event Generation of synchronous interrupts O Synchronous Digital Output updates Synchronous Digital Input sampling ECAT or PDI Control Sync signals Latch signals System Time PDI Controlled Communication Timing Free Run Synchronized to Output Event Synchronized to SyncSignal EtherCAT State Machine Control of State Machine Indication of the Status and error code Device Emulation SII EEPROM SII EEPROM Commands SII EEPROM Error Indication SII EEPROM Access Interface EEPROM Size selection EEPROM Emulation Interrupt AL Event Request PDI Interrupt ECAT Event Request ECAT Interrupt Watchdog Process Data Watchdog PDI Watchdog Error Counters Port Error Counters O O O O Forwarded RX Error Counter ECAT Processing Unit Error Counter PDI Error Counter Lost Link Counter

R-IN32M3-EC Series User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents