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MC68QH302 Supplement to the MC68302 Integrated Multiprotocol

1. 0x610 0x610 Buffer Descriptors Buffer Descriptors 0x660 Other Registers Other Registers 0x660 0x680 0x680 D Parameter RAM B2 Parameter RAM Ox6AC _B2 Fixed Param RAM B2 Fixed Param RAM_ 0x6AC 0x6C0 0x6C0 Reserved Reserved 0x800 0x800 Figure 3 D Channel and B2 Channel Parameter Swapping MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 shows the B2 parameter location depending on the activation status of the B2 and D channels Table 3 B2 Channel Parameter Location Status of B2 D Stopped B2 stopped 0x500 0x52B 0x500 0x52B 0x680 0x6AB Indeterminate Note The fixed address parameters also need to be initialized Table 4 shows the D channel parameter locations depending on the activation status of the B2 and D channels Table 4 D Channel Parameter Location Status of B2 D Stopped B2 stopped 0x680 0x6AB 0x680 0x6AB 0x500 0x52B Indeterminate Table 5 shows the QH mode channel parameter mapping Note the two highlighted swapping areas starting at offsets 0x500 and 0x680 Table 5 QH Mode Parameter RAM Map Base Offset Description 0x400 0x40F B1 channel parameter RAM 0x410 0x47F Buffer descriptors 0x480 0x4BF B1 channel parameter RAM 0x4C0 O0x4FF Reserved not implemented 0x500 0x52B_ B2 channel parameter RAM with B2
2. cescsscsscssesseceseceseeseceseceseceeeeaeeeaeeseeeaeeeneenees 10 10 B2 Channel Rx Swapped Parameter 11 11 B2 Channel Tx Swapped Parameters seeeseeseesersesesesersesestsersesestsersesestsereeeestseneeeesesereesee 12 12 D Channel Rx Swapped Parameters ssssssssssssssesessseetseseerssesesesrssestsesrsnenesenesresesesesees 13 13 D Channel Tx Swapped Parameters sssssessssseseesesesssstsesesessestsesrsseseseerereseneneeresenesesees 14 14 RSTATE Field Descriptions for HDLC Transparent Channels AN 15 15 RSTATE Field Descriptions for UART Channels AAA 16 16 TSTATE Field Descriptions A 17 BTMODE Field Descriptions 18 BNOF Field Descriptions niss cee eeeeeessessesecseesececsecseesessecsessessesaesaesaesassassaesaeeaeeategs 19 B_STAT1 Field Descriptions 20 B_STAT2 Field Descriptions 21 C_MASK_H L Constant 22 T_F_MASK and R_F_MASK Field Descriptions ee eeesceeseeeseeeeeeeeeseeeeeeeeeneenees 21 23 Non QH Channel Parameter RANM 22 24 SOM Field DESCriptonss ee seirer eener ieran e ene ae ae a ae 23 25 V410 Mode RV D DESCriptiOn soi cciciseecccscasesscecodscecessdsceessodesecetodssnsedv s cede svcbissedsin ecess sistes 24 26 Tx Status and Control Field Descriptions cece cscs ceeceecneceeeecaeceeaeeaeeaesaeeaeegs 27 27 Rx Status and Control Field Descp ons cece cece esses ceeeeceeececeeaeeesaeeaeeateas 28 28 SCCEL Field Re sc scisiscistsstaneeteencaartnavsnanensnisananandasnavandaansnendsantonncbionnsndonneneadsan
3. 0x6CO 0x7FF Reserved not implemented Note As defined in the BAR base address register MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 1 2 QH Mode Parameter RAM Map The QH302 s parameter RAM has been remapped to accommodate QH mode To implement the three channels of ISDN and a UART host channel all running on three SCCs part of the B2 channel parameters are juggled with the D channel parameters The B2 channel parameters are broken into three areas two are fixed address while the third swaps back and forth with the D channel parameters as B2 is enabled and disabled Figure 3 shows the swapping moving from left to right when B2 is enabled and back again when B2 is disabled QH Mode Parameter RAM QH Mode Parameter RAM Map with B2 Stopped Map with B2 Running 0x400 B1 Parameter RAM B2 enabled B1 Parameter RAM 0x400 0x410 E ae 0x410 Buffer Descriptors Buffer Descriptors 0x480 B2 disabled 0x480 B1 Parameter RAM B1 Parameter RAM 0x4C0 0x4C0 Reserved Reserved 0x500 0x500 B2 Parameter RAM D Parameter RAM 0x52CY 0x52C 0x530 0x530 Buffer Descriptors Buffer Descriptors 0x580 0x580 SCC2 Parameter RAM SCC2 Parameter RAM 0x5AC 0x5AC Reserved Reserved 0x600 B2 Fixed Param RAM B2 Fixed Param RAM 0x600
4. Figure 22 SCC Buffer Descriptor Memory Structure 2 10 QH302 Tx Buffer Descriptors for HDLC Transparent Mode The transmitter uses the Tx BD to report information about the transmitted data associated with each BD The first word contains status and control information and is shown in Figure 23 Table 26 describes the status and control bit fields 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R W L TC UN CT Figure 23 Tx Buffer Descriptor Status and Control MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 26 Tx Status and Control Field Descriptions 0 The data buffer is not ready for sending Cleared by the transmitter after the buffer has been fully sent or an error condition occurs 1 The data buffer is ready for sending but has not yet been fully sent The host should not modify any field of this BD after setting this bit Reserved Wrap 0 Not the last BD in the Tx BD table 1 The last BD in the Tx BD table Interrupt 0 No TXB interrupt is generated after this buffer was transmitted 1 The TXB bit in the event register SCCE will be set Last 0 Not the last buffer in the frame 1 The last buffer in the frame Transmit CRC Valid only when the last L bit is set 0 Do not send CRC after the last byte is sent 1 Send the CRC after
5. 2 8 SCC Mode Register SCM The QH302 supports five protocols HDLC UART V 110 transparent and QH Only SCC1 can run the QH protocol The SCC mode registers SCM determine the protocol to be run for each SCC Figure 15 shows the SCM register Im wm 12 1 10 9 8 H 6 5 4 3 2 1 0 Mode Specific Bits Diag 1 0 Mode 1 0 Figure 15 SCM Register SCM 5 0 are common to each protocol while the mode specific bits SCM 15 6 vary according to the protocol selected in SCM 1 O This register is cleared by reset See Table 24 for field descriptions Table 24 SCM Field Descriptions Ce e e E EEE 1H 0 Modef 1 0 Channel mode 00 HDLC 01 UART 10 V 110 11 Totally transparent QH for SCC1 only Descriptions of the specific mode settings follow 2 8 1 HDLC Mode Settings In HDLC mode the SCM register is the same as in the 302 see Figure 16 15 14 13 12 11 10 9 8 4 6 5 4 3 2 1 0 Pd ott Figure 16 SCM Register in HDLC Mode MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 8 2 UART Mode Settings In UART mode the SCM register is the same as in the 302 see Figure 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 17 SCM Register in UART Mode 2 8 3 V 110 Mode Settings The V 110 mode is selected by programming the SCM register as in Figure 18 The V 110 mode may be activated when operating in non QH mode only
6. RB STATT contains B channel receiver status bits and internal use bits After reset or a hardware overrun error the user must clear this byte for both B channels After this initial clearing however the user should access this byte using host commands only see Section 2 13 1 B Channel Host Commands for more information on how host commands affect B channel status bits Figure 11 shows the fields and Table 19 describes them 7 6 5 4 3 2 1 0 000000 BOV BRV Figure 11 B_STAT1 Byte Table 19 B_STAT1 Field Descriptions For internal use must be initialized to zero B channel receiver overrun must be initialized to zero 0 No overrun error 1 Overrun error B channel receiver valid must be initialized to zero 0 Bchannel receiver disabled 1 B channel receiver enabled 2 6 6 1 B Channel Overrun and B Channel Receiver Valid Flags B_STAT1 BOV reports overrun errors and B_STATI BRV reflects the channel activation status When the host does not prepare an empty buffer descriptor for incoming data a receiver error RXE interrupt is triggered and the overrunning B channel s B_STAT1 BOV is set disabling the receiver The user must determine which B channel has overrun by polling both B channels B_LSTAT1 BOV and then issue STOP RX for that channel STOP RX clears B_STAT1 BRV Note that both B channels could overrun simultaneously as in the case of a hardware overrun It is the user s responsibility to re initiali
7. Thie Number QH302 Tx Buffer Descriptors for HDLC Transparent Mode 26 QH302 Rx Buffer Descriptors for HDLC Transparent Mode 27 QH Mode SCC1 Event Register GGCCEI A 29 Channel Host Commande 30 B Chaninel Host Commands a cdsccccdsdccestvdzccesdedeiessdecceessdvdnscgetederccsdvceecssdsissext 31 D Channel Host Commande 31 QH Parameters Initialization Summary 32 OH302 ADE SR E 33 QH302 UART Protocolar eei Ei E A 34 QH302 UART Parameter RAM Map 34 QH Mode Hardware Inmpalt zapen 35 QH302 ISDN BRI Performance 36 MC68QH302 Supplement to MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ILLUSTRATIONS Figure f Page Hamper BS Number 1 MC68QH302 Block Diaeram AA 1 2 Full ISDN Basic Rate Interface Using the OH 20 2 3 D Channel and B2 Channel Parameter Swapptmg eee cece ceeeseensceeeneeneeeente 5 4 Global QOH Mode Register sissies ifestscs covsleceiserssvasieedsesdsvesseedesnsvestecedsendevessentesncscssteetsendecessend 7 5 OH Type and Revision NUM DEP iiccccccscssecseoncseccvecesecectecvesecevescbevecaveveccssvesscevescbssasscevesessvees 8 6 RSTATE for HDLC Transparent Channels 1 14 7 RSTATE for UART Channels ta A ENE RGE 16 8 STATE E 16 9 RR CEET 17 10 ENEE 17 11 B STAT tesche 18 12 EEN E 19 13 Data Buffer Function Code Registers cece eeececesceecesenecsessesesneeecaesaeeaesaesaeeategs 20 14 Framer Bit Maskote eneee e eae eae EAA E E EASED EEA EATE AE E
8. fixed address parameters 10 location 6 Rx swapped parameters 11 swapping 5 Tx swapped parameters 12 B channel host commands 31 Block diagram 1 BNOF B channel number of flags byte 17 BTMODE B channel transmit mode byte 17 Buffer descriptors buffer descriptor structure 25 Rx buffer descriptor 27 Tx buffer descriptor 26 Cc C_MASK_L H constant for CRC check 21 Changes from 302 3 33 Channel host commands 30 Channel parameters B_STATI 18 B_STATZ2 19 B2 channel parameter swapping 5 B channel host commands 31 BNOF 17 BTMODE 17 C_MASK_L H 21 D channel host commands 31 parameter swapping 5 ISDN BRI channel performance 36 MRBLR 20 R_F_MASK 21 RBASE 20 RBDPTR 20 RFCR 20 INDEX Index RSTATE HDLC transparent channels 14 UART channels 16 T_F_MASK 21 T_MODE 16 TBASE 20 TBDPTR 20 TFCR 20 TSTATE 16 Commands channel host 30 D Data buffer function code registers TFCR RFCR 20 D channel parameter description 13 host commands 31 location 6 Rx swapped parameters 13 swapping 5 Tx swapped parameters 14 Descriptor table base addresses 20 Differences from 302 3 33 Dual port RAM map 3 F Features list 2 Fixed address parameter RAM B2 channel 10 Flags B channel overrun 18 receiver valid 18 transmitter valid 19 underrun 19 G Global QH mode parameters 7 register 7 For More Information On This Product Go to www freesc
9. Lei MC68QH302 Figure 2 Full ISDN Basic Rate Interface Using the QH302 In non QH mode the QH302 can be used in standard 302 applications as well Note that the QH302 SCC parameter RAM mapping has been modified requiring corresponding adjustments in the configuration software See Section 2 7 Non QH Channel Parameter RAM 1 2 Features Main features of the QH302 and changes relative to the standard 302 follow e Supports two independent communications channels using SCC1 e Allows independent connection disconnection for individual B channels e Supports HDLC and totally transparent protocols for individual B channels e Allows independent transmit and receive bit masking for both B channels e Allows flexible buffer descriptor table placement using the new base address parameters RBASE and TBASE e Allows RAM microcode packages e Enables software to distinguish a QH302 from a 302 by use of a revision number e Supports special host commands for the individual B channels e Supports a 64 us or longer DRAM refresh cycle in QH mode MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc e In non QH mode all three SCCs can be used in standard 302 configurations e Pin compatible with the existing TQFP 302 package General QH302 changes relative to 302 are as follows e The X external buffer bit o
10. Table 25 describes the reverse data field RVD 13 12 11 7 1 9 8 7 6 5 4 3 2 1 0 ofofof4 o RVD 0 0 Diag 1 0 ENR ENT 10 Figure 18 SCM Register in V 110 Mode Table 25 V 110 Mode RVD Description epe o e S a Inn Reverse data Reverses the reception bit order Should be set for regular V 110 operation 2 8 4 Totally Transparent Mode Settings The transparent mode settings are shown in Figure 19 and only apply to SCC2 and SCC3 Note that since there is no data synchronization register synchronization can be achieved from an external pin or by using the serial interface 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Po e pepe ee ae epee Figure 19 SCM Register in Transparent Mode 2 8 5 QH Mode Settings The QH mode applies to SCC1 only and must be selected for SCC1 when QH operation is needed QH mode can be selected for IDL or GCI modes only without any bit masking by the SIMASK register Figure 20 shows the QH settings 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a E EE EE EE EE EE ENEE Figure 20 SCM Register in OH Mode MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 9 QH302 Buffer Descriptor BD Structure The QH302 s overall buffer descriptor structure is the same as in the 302 however the status and control word has been modified The 302 s X external buffer bit and the LG Rx frame length violatio
11. Tx buffer descriptor base address OxAA BRKCR Break count register Tx OxAC UADDR1 UART address character 1 OxAE UADDR2 UART address character 2 0xB0 RCCR Receive control character register 0xB2 CHARACTER1 Control character 1 0xB4 CHARACTER2 Control character 2 0xB6 CHARACTER3 Control character 3 0xB8 CHARACTER4 Control character 4 OxBA CHARACTERS Control character 5 O0xBC CHARACTER6 Control character 6 OxBE CHARACTER7 Control character 7 2 17 QH Mode Hardware Initialization The proper initialization order of the internal QH302 modules begins with the external pins then the serial interface and the SCCs last The following shows the proper hardware initialization sequence for QH operation 1 2 Program the parallel I O to select the pins needed for the application Select SCC2 pins for dedicated mode to connect SCC2 to the external pins to operate as a DTE connection Program the serial interface registers to configure the serial channel physical interface SIMASK write OxFFFF to SIMASK register SIMODE select the IDL GCI mode using the MS 0 1 bits Route B1 and B2 to SCC1 that is B1RB B1RA 01 B2RB B2RA 01 Route D channel to SCC3 that is DRB DRA 11 and MSC3 0 Route SCC2 to the NMSI pins that is MSC2 1 All other bits are user defined 4 Program the QH parameters in the dual port RAM Program SCON1 and SCON3 to 0x3000 to enable operating from the SI clock MC68QH
12. and Table 17 describe the bit fields 7 6 5 4 3 2 1 0 Figure 9 BTMODE Byte Table 17 BTMODE Field Descriptions a 7 FLG Flag mode send FLAG or IDLE characters between HDLC frames 0 Send IDLEs OxFF between frames must be selected when in transparent mode 1 Send FLAG characters 0x7E between frames e TIDL Programmed to be the complement of the FLG bit FLG 5 4 PAGE Page selection 00 B1 channel 10 B2 channel MSNUM Serial number should always be programmed to 0b1000 2 6 5 BNOF B Channel Number of Flags The B channel number of flags byte specifies the number of flags to be sent between frames on the B channels Figure 10 and Table 18 show the bit fields for initialization 7 6 5 4 3 2 1 0 Figure 10 BNOF Byte Table 18 BNOF Field Descriptions For internal use must be initialized to zero Page selection 00 B1 channel 10 B2 channel Minimum number of flags between or before frames 0 to 15 For transparent mode NOF must be zero so that the closing flag of one frame will be followed by the opening flag of the next frame In HDLC mode when NOF 0 the closing flag of one frame and the opening flag of the next frame overlap only one shared flag is transmitted between consecutive frames MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 6 6 B_STAT1 B Channel Receiver Status
13. and thus are no longer limited to holding only 8 buffer descriptors The user must initialize RBASE and TBASE before enabling the channel They must be divisible by 8 and range from 0 to 0x800 to fit within the dual port RAM Furthermore RBASE and TBASE should be chosen to ensure descriptor tables of different channels do not overlap 2 6 9 TBDPTR and RBDPTR Tx Rx Buffer Descriptor Pointers Rx buffer descriptor pointer RBDPTR and Tx buffer descriptor pointer TBDPTR point to the buffer descriptors currently being used by the receive and transmit channels respectively They should be initialized to the values of RBASE and TBASE respectively 2 6 10 TFCR and RFCR Data Buffer Function Code Registers The function code registers define the address space of the receive RFCR and transmit TFCR data buffers These registers must be initialized before enabling the SCC Bits 3 0 and bit 7 are internal use only but must be initialized to 0 see Figure 13 Note that setting FC 2 0 to 0b111 will cause a conflict with the interrupt acknowledge cycle See the MC68302 user s manual for more information on function codes 7 6 5 4 3 2 1 0 LAR hese Eee Figure 13 Data Buffer Function Code Registers 2 6 11 MRBLR Maximum Receive Buffer Length Register The MRBLR sets the maximum number of bytes that the QH302 will write to a receiver buffer before moving to the next The QH302 may write fewer bytes to the buffer if an end of frame or erro
14. 0x692 0x512 C_MASK_L Word Constant CRC mask low word 0x694 0x514 C_MASK_H Word Constant CRC mask high word 0x696 0x516 RSTATE Word Rx internal state Notes 1As defined in the BAR base address register Rx parameter location when B2 Rx channel is disabled or after a reset 3Rx parameter location when B2 Rx channel is enabled MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The transmitter parameters are shown in Table 13 Table 13 D Channel Tx Swapped Parameters Base Offset Base Offset B2 Stopped B2 Running Description TSTATE Tx internal state TBDPTR Tx buffer descriptor pointer 2 Words Tx internal data pointer Tx internal byte count Tx temp Temp transmit CRC Tx buffer descriptor table base address Tx mode Notes 1As defined in the BAR base address register Tx parameter location when B2 Tx channel is disabled 3Tx parameter location when B2 Tx channel is enabled 2 6 Channel Parameter Descriptions This section describes the channel parameters the user must initialize before a channel is enabled Any active channel must first be stopped before updating parameters 2 6 1 RSTATE Receive Internal State RSTATE must be initialized by the user Its bit field definitions depend on the communications mode selected Figure 6 shows the fields for HDLC or transparent channels Tab
15. 302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 6 Program the interrupt controller mask register IMR to enable SCC interrupts 7 Program SCC1 mask register SCCM1 to enable B channel interrupts 8 Program SCC1 mode register SCM1 for both Bland B2 channels to totally transparent mode that is SCM1 Ox600F 9 Program SCC3 mask register SCCMS3 to enable D channel interrupts 10 Program SCC3 mode register SCM3 D channel to HDLC transparent mode as in the 302 11 Program SCC2 mask register SCCM2 to enable SCC2 interrupts 12 Program SCON2 to select the clock source for SCC2 13 Program SCC2 mode register SCM2 DTE connection to HDLC transparent UART mode as in the 302 2 18 QH302 ISDN BRI Performance Channel speeds for a basic rate ISDN interface is shown in Table 37 Table 37 QH302 ISDN BRI Channel Performance 64 Kbps 64 Kbps 16 Kbps 230 Kbps 115 Kbps 33 MHz 64 Kbps 64 Kbps 16 Kbps 460 Kbps 230 Kbps Notes HDLC on SCC1 2HDLC on SCC3 leie MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Numerics 302 differences from QH302 3 33 B BD STATT B channel receiver status byte 18 B_STAT2 B channel transmitter status 19 Bl channel parameter RAM 8 B2 channel parameter description 10
16. 68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 1 1 Non QH Mode Parameter RAM Map In non QH mode the QH302 s parameter RAM map reflects QH302 specific needs and the added buffer descriptor flexibility gained with RBASE and TBASE Buffer descriptor areas are no longer dedicated to a particular SCC SCC parameter areas start at the same locations QH302 specific parameters such as the global QH mode and the QH type and revision number start at offset 0x660 Table 2 shows the parameter RAM map for non QH operation Table 2 Non QH Mode Parameter RAM Map Base Offset Width Description 0x400 0x47F 64 words Buffer descriptors 0x480 0x4BF SCC1 parameter RAM 0x4C0 0x4FF Reserved not implemented 0x500 0x56F 56 words Buffer descriptors 0x570 0x57F Buffer descriptors DRAM refresh parameters 0x580 O0x5BF 32 words SCC2 parameter RAM 0x5C0 0x5FF Reserved not implemented 0x600 0x65F Buffer descriptors 0x660 Word Global QH mode 0x662 0x665 2 words Reserved for internal HW use SMC1 Rx buffer descriptor SMC1 Tx buffer descriptor SMC2 Rx buffer descriptor SMC2 Tx buffer descriptor SMC1 SMC2 internal use SCP Rx Tx buffer descriptor SCC1 SCC3 BERR bus error channel number QH type and revision number 0x680 0x6AB SCC3 parameter RAM Ox6AC Ox6BF 10 words Buffer descriptors
17. Freescale Semiconductor Inc MC68QH302SUPL AD 10 97 MC68QH302 Supplement to the MC68302 Integrated Multiprotocol Processor User s Manual A We gt freescale senrnrconductar For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 81 2666 8080 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in t
18. TR 2 words Rx internal data pointer RBCNT RCRC Word Rx internal byte count Temp receive CRC C_MASK_L Constant CRC mask low word C_MASK_H RSTATE Constant CRC mask high word Rx internal state TSTATE Tx internal state TBDPTR 2 words Tx buffer descriptor pointer Tx internal data pointer Word Tx internal byte count Word Tx temp Temp transmit CRC Tx buffer descriptor table base address TFLGIDL Tx mode Tx frame separator internal TTOPTMP Tx top temporary internal R_F_POST R_F_PRE Rx framer post byte internal Rx framer pre byte internal R_F_STAT Rx framer state T_F_DATA T_F_POST Tx framer data byte Tx framer post byte internal T_F_STAT Tx framer state T_F_MASK Tx framer mask byte Framer internal temporary storage for mask Tx framer pre byte Pack 2 bytes into 1 word Note As defined in the BAR base address register MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 4 B2 Channel Parameter RAM There are 2 types of B2 channel parameters swapped and fixed address The fixed address B2 channel parameters are defined in Table 9 Table 9 B2 Channel Fixed Address Parameters Base Offset Name Width Description 0x600 R_F_DATA Word Rx fram
19. _STAT For B1 0x0000 For B1 0x02C0 For B2 0x0020 For B2 0x02E0 mee oS OS RSTATE See Section 2 6 1 RSTATE Receive Internal State MR BLR O See Section 2 6 11 MRBLR Maximum Receive Buffer Length Register 2 15 QH302 HDLC Differences The QH302 HDLC protocol does not support the following Address recognition no SCC data synchronization register DSR Error statistics counters Checking of frames that are too long MFLR Additional differences are as follows Non octet frame the last 16 data bits of non octet frame may be corrupted The data length word of the last Rx buffer descriptor in frame contains the length of the last buffer only IDL CTS CD interrupts are not supported for either B channel but are supported for the QH HDLC protocol Host commands for the B channels can only enable disable the Rx Tx channels see Section 2 13 Channel Host Commands ENTER HUNT MODE does not exist for the B channels Instead the user must STOP RX update parameters and then RESTART RX After executing a STOP TX instruction for either B channel the channel enters idle mode until the RESTART TX instruction is executed MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc e B channels acknowledge the transmission when the data enters the SCC1 s FIFO buffer and not when actually sent e The QH302
20. ale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Tey freescale For More Information On This Product Go to www freescale com Paragraph Number 1 1 12 2 1 2 1 1 2 1 2 2 2 22M 2 2 2 23 2 4 2 5 2 6 2 6 1 2 6 2 2 6 3 2 6 4 2 6 5 2 6 6 2 6 6 1 2 6 7 2 6 7 1 2 6 8 2 6 9 2 6 10 2 6 11 2 6 12 2 6 13 2 6 14 2 7 2 8 2 8 1 2 8 2 2 8 3 2 8 4 2 8 5 2 9 Freescale Semiconductor Inc CONTENTS Title VE Eet EE EES Dual Port RAM Map Non QH Mode Parameter RAM Map AE QH Mode Parameter RAM Map Global QH Parameters esaeen e R E A SS Global QH Mod sssrinin nii s QH Type and Revision Number 1 Bl1 Channel Parameter BAM B2 Channel Parameter BAM D Channel Parameter BAM Channel Parameter DeSCriptions cece cece ceeeee eee cneeeeeeeeeaeeaees RSTATE Receive Internal State 0 c
21. ale com Freescale Semiconductor Inc INDEX H Hardware initialization 35 HDLC protocol 33 HDLC transparent mode RSTATE 14 Rx buffer descriptors 27 Tx buffer descriptors 26 Host command register 30 l Initialization summary hardware initialization 35 QH parameters initialization 32 ISDN basic rate interface 2 ISDN BRI channel performance 36 M Maps Bl channel parameter RAM map 8 B2 channel parameter RAM map 10 D channel parameter RAM map 13 dual port RAM map 3 non QH mode parameter RAM map 4 22 parameter RAM map 3 QH mode parameter RAM map 5 6 system RAM map 3 MRBLR maximum receive buffer length register 20 N Non QH mode parameter RAM map 4 22 O Opcodes OH mode opcodes for command register 30 Overview P Parameters B 1 channel parameter RAM map 8 B2 channel parameter RAM map 10 D channel parameter RAM map 13 global QH parameters 7 non QH mode parameter RAM map 4 22 parameter swapping B2 channel 5 D channel 5 QH mode initialization summary 32 parameter RAM map 5 6 UART protocol RAM map 34 Q QH mode global parameters 7 hardware initialization 35 initialization summary 32 opcodes for command register 30 parameter RAM map 5 6 SCCE1 register 29 QH type and revision number register 7 R R_F_MASK Rx framer bit mask 21 RAM maps Bl channel 8 B2 channel 10 D channel 13 dual port 3 non QH mode 4 22 parameter RAM map 3 QH mode 5 6 syst
22. ate TBDPTR Word Tx buffer descriptor pointer Tx internal data pointer Word Tx internal byte count Word Tx temp Temp transmit CRC 0x528 0x6A8 TBASE Word Tx buffer descriptor table base address 0x52A Ox6AA T_MODE Word Tx mode Notes 1As defined in the BAR base address register Parameter location when updating Tx values 3Unsafe location for updating read only MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com 2 5 D Channel Parameter RAM Freescale Semiconductor Inc All the D channel parameters are swapped Their location depends on whether the B2 channel is running or not The receiver parameters are shown in Table 12 Boldfaced parameters are initialized or used by the host and must not be changed while the channel is operating Other parameters are for internal use and should not be changed Table 12 D Channel Rx Swapped Parameters Base Offset Base Offset B2 Stopped B2 Running Name Width Description 0x680 0x500 RFCR Byte Rx function code 0x681 0x501 TFCR Byte Tx function code 0x682 0x502 MRBLR Word Maximum receive buffer length 0x684 0x504 RBASE Word Rx buffer descriptor table base address 0x686 0x506 RBDPTR Word Rx buffer descriptor pointer 0x688 0x508 RBPTR 2 words Rx internal data pointer 0x68C 0x50C RBCNT Word Rx internal byte count Ox68E Ox50E RCRC 2 words Temp receive CRC
23. bsite at http www mot com netcomm 1 1 Overview The MC68QH302 quad HDLC integrated multiprotocol processor is based on the three SCC MC68302 family of chips with the addition of the QH protocol and two extra serial DMA channels The QH302 supports a total of four independent communications channels handling two HDLC or transparent channels on SCC1 see Figure 1 for a block diagram Sa are oe a ea ee ee gee ee E ee E ee E p General Purpose 3 Timers RAM Interrupt DMA 4 Chip Selects Controllers Paraliel VO ROM 68000 M68000 System Bus ore 20 Address Lines 8 16 Data Lines Dual Port RAM 8 DMA Channels RI Peripheral Bus Controller s CH n O 1152 Bytes SCH SCC2 SCP 2 Channels SCC3 2 SMCs Figure 1 MC68QH302 Block Diagram GG MC68QH302 MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc For external active ISDN terminal adaptor applications SCC1 supports both B channels B1 and B2 and SCC3 handles the D channel SCC2 is thus free to carry a UART host interface eliminating the need for host interface glue logic Figure 2 shows the implementation of a full ISDN basic rate interface using the QH302 B1 B2 SCC1 QH Faber IDL GCI Lil Si S T or U pe a SCC2 UART ISDN Line Transceiver D SCP SCC3 HDLC
24. c ccceecscccceceesssssseeeeeeeees T_MODE Transmit Mode ccccccccccccccesssssceseecesssssseeeeeeees TSTATE Transmit Internal State BTMODE B Channel Transmit Mode BNOF B Channel Number of Flags AAA B_STAT1 B Channel Receiver Status cccccccccceesssteseeeeees B Channel Overrun and B Channel Receiver Valid Flags B_STAT2 B Channel Transmitter Status B Channel Underrun and B Channel Transmitter Valid Flags RBASE and TBASE Descriptor Table Base Addresses TBDPTR and RBDPTR Tx Rx Buffer Descriptor Pointers TFCR and RFCR Data Buffer Function Code Registers MRBLR Maximum Receive Buffer Length Register C_MASK_L H Constant for CRC Check T_F_MASK and R_F_MASK Tx Rx Framer Bit Masks Other Channel Parameters 1 Non QH Channel Parameter RAAM SCC Mode Register GC HDLC Mod Seti o gt icc ceiccccescasccseceencciscoagenscscastecesvsacctecscetesecossene UART Mode Settings ccctivcsseviteccivscercstvceancstvearetenssuvecsdetcovasnestestets V1 JO Mode Settings eee aet iri AERAR RRR Totally Transparent Mode Settmngs eee eee eee eeeeeeeneeees QH Mode Seti 88 ee QH302 Buffer Descriptor BD Structure Contents For More Information On This Product Go to www freescale com Page Number Paragraph Number 2 10 2 11 2 12 2 13 2 13 1 2 13 2 2 14 2 15 2 16 2 16 1 2 17 2 18 Freescale Semiconductor Inc CONTENTS p Page
25. cee 29 29 QH Mode Opcodes for the Command Regteter 1 30 30 Command Register Channel Numbers for QH and Non QH Modes AAA 30 31 B Channel Host CommanndS 2 lt iccc ciccceciccsiecscocescecosnte cess suiesneecesnsescieteceds sietnsscete etein stedne 31 32 D Channe l Host Commands resies ereere erti eeii enee ea eii EEE EO SE EAEI EEE ESERE eiis 31 33 Parameters to be Initialized before SCC1 Is Enabled AAA 32 34 Parameters to be Initialized before Every restart D 32 Tables For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLES Table gt Page Number Title Number 35 Parameters to be Initialized before Every restart Ca 33 36 UART Parameter RAM cscscscrevsevrensevevsessevssossnsessevssvsenssvessseoseoseossossosessesseossoeenss 34 37 QH302 ISDN BRI Channel Performance 36 MC68QH302 Supplement to MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc This supplement to the MC68302 Integrated Multiprotocol Processor User s Manual MC68302UM AD highlights implementation specific features of the MC68QH302 referred to as the QH302 and how they differ from the MC68302 referred to as the 302 The MC68302 Integrated Multiprotocol Processor User s Manual should be consulted for any features not described in this document To locate any published errata or updates for this document refer to the we
26. dified only while the channel is stopped or disabled Table 33 Parameters to be Initialized before SCC1 Is Enabled rn F_DATA C For B2 0xE028 B_STAT1 See Section 2 6 6 B_STAT1 B Channel Receiver Status B_STAT2 See Section 2 6 7 B_STAT2 B Channel Transmitter Status RSTATE See Section 2 6 1 RSTATE Receive Internal State See Section 2 6 13 T_F_MASK and R_F_MASK Tx Rx Framer Bit Masks RF mask o O See Section 2 6 13 T_F_MASK and R_F_MASK Tx Rx Framer Bit Masks Table 34 Parameters to be Initialized before Every RESTART TX HDLC Mode Value Transparent Mode Value men O 0x7E7E OxFFFF SS Flag mode 0x8000 0x0000 Idle mode 0x0000 pg See Section 2 6 5 BNOF B Channel Number of Flags ee See Section 2 6 4 BTMODE B Channel Transmit Mode TSTATE See Section 2 6 3 TSTATE Transmit Internal State TFCR See Section 2 6 10 TFCR and RFCR Data Buffer Function Code Registers TBASE See Section 2 6 8 RBASE and TBASE Descriptor Table Base Addresses TBDPTR See Section 2 6 9 TBDPTR and RBDPTR Tx Rx Buffer Descriptor Pointers T_MODE See Section 2 6 2 T_MODE Transmit Mode MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 35 Parameters to be Initialized before Every RESTART RX HDLC Mode Value Transparent Mode Value R_F
27. e B channel goes into idle mode sending idle characters 1 s following the abort sequence After executing RESTART TX the channel starts from its initial state as programmed in the BTMODE register channel is now considered running prohibiting parameter modification and the first Tx buffer RESTART TX RESTART TX initiates transmission on a B channel following a STOP TX command or an underrun error The command sets B_STAT2 BTV and clears B_STAT2 BUN of the designated B channel The descriptor is polled channel The host can now modify the parameters see Section 2 14 QH Parameters Initialization STOP RX STOP RX stops a Rx B channel It must be issued after a receive error or if the B channel parameters need to be modified STOP RX clears the B_STAT1 BRV of the designated B channel invalidating the Summary for B channel parameter initialization the start of frame condition on the receive data line to fill the first Rx buffer with data RESTART RX RESTART RX initiates reception on a B channel setting B_STAT1 BRV of the designated B channel The channel is now considered running prohibiting parameter modification The receiver searches for 2 13 2 D Channel Host Commands The D channel host commands are described in Table 32 Table 32 D Channel Host Commands D Channel Wi STOP TX STOP TX stops the channel It must be issued after a transmit error or if the channel parameters need to be modified Channel tran
28. em RAM map 3 UART RAM maps 34 RBASE 20 RBDPTR Rx buffer descriptor pointer 20 Registers global QH mode 7 host command 30 MRBLR 20 QH type and revision number 7 RFCR 20 SCCE1 29 SCM 23 TFCR 20 RFCR register 20 RSTATE receive internal state HDLC transparent channels 14 UART channels 16 Rx buffer descriptors HDLC transparent mode 27 Rx swapped parameter RAM B2 channel 11 D channel 13 S SCC buffer descriptor memory structure 26 SCC mode register 23 SCCE1 SCC1 event register 29 SCM SCC mode register 23 System RAM map 3 MC68QH302 Supplement to MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INDEX T T_F_MASK Tx framer bit mask 21 T_MODE transmit mode 16 TBASE 20 TBDPTR Tx buffer descriptor pointer 20 TFCR register 20 TSTATE transmit internal state 16 Tx buffer descriptors HDLC transparent mode 26 Tx swapped parameter RAM B2 channel 12 D channel 14 U UART protocol RAM map 34 RSTATE 16 Index For More Information On This Product Go to www freescale com Freescale Semiconductor Inc INDEX MC68QH302 Supplement to MC68302 User s Manual For More Information On This Product Go to www freescale com
29. ent frame the RISC controller underruns The controller then sets BLSTAT2 BUN disabling the underrunning B channel s transmitter and signals the host with a transmitter error TXE interrupt An abort sequence followed by idle characters high voltage will be automatically sent The user must determine which B channel has underrun by polling both B channels B_STAT2 BUN and then issue STOP TX for that channel STOP TX clears B_STAT2 BUN Note that both B channels could underrun simultaneously as in the case of a hardware underrun It is the user s responsibility to re initialize the channel parameters and then issue RESTART TX reactivating the channel RESTART TX clears B_STATI BUN and sets B_STATI BTYV MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc If an underrun exception occurs in a B channel programmed for flag mode see Section 2 6 4 BTMODE B Channel Transmit Mode tbe B channel will go into idle mode that is transmit idle 1 s 2 6 8 RBASE and TBASE Descriptor Table Base Addresses RBASE and TBASE allow the user to program the base address of buffer descriptor tables in the dual port RAM Each channel has its own pair an RBASE to point to its Rx buffer descriptor table and a TBASE for its Tx descriptor table In other words unlike the 302 the QH302 s descriptor tables are not locked into a fixed position
30. er data internal byte F_D_O Word Rx Tx framer data out also DTSCC 0x604 R_F_MASK Byte Rx framer mask byte F_CTR Byte Framer internal counter TUNPACK Word Unpack a word to 2 bytes 0x608 B_STAT1 Byte B channel Rx mode amp status BNOF Byte B channel number of flags and internal parameters B_STAT2 Byte B channel Tx mode amp status 0x60B BTMODE Byte B channel mode amp status user defined mode bits RTEMP Word Rx temp NFC Word Number of flags counter internal Ox6AC TFLGIDL Word Tx frame separator internal TTOPTMP Word Tx Top temporary internal R_F_POST Byte Rx framer post byte internal Ox6B1 R_F_PRE Byte Rx framer pre byte internal R_F_STAT Word Rx framer state T_F_DATA Byte Tx framer data byte Ox6B5 T_F_POST Byte Tx framer post byte internal T_F_STAT Word Tx framer state T_F_MASK Byte Tx framer mask byte Ox6BA F_TMPM Word Framer internal temporary storage for mask Ox6BC T_F_PRE Word Tx framer pre byte RPACK Word Pack 2 bytes into 1 word Note As defined in the BAR base address register MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc The swapped B2 channel parameters are further divided into receive Rx and transmit Tx areas Table 10 shows the Rx channel parameter locations when the B2 receiver is running or stopped See Section 2 6 6 B_STAT1 B Channel Receiver Status for information on determini
31. eration they only need to be initialized every time the QH receiver or transmitter channel is restarted Section 2 14 QH Parameters Initialization Summary lists initial values for these parameters The initial value of parameters not described is unimportant MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 7 Non QH Channel Parameter RAM Table 23 describes the parameter RAM for SCCs operating in non QH mode If QH mode is selected this parameter RAM only applies to SCC2 For full descriptions of these parameters see Section 2 6 Channel Parameter Descriptions Table 23 Non QH Channel Parameter RAM SCC Base Offset Name Width Description 0x80 RFCR Byte Rx function code 0x81 TFCR Byte Tx function code 0x84 RBASE Word Rx buffer descriptor table base address 0x86 RBDPTR Word Rx internal buffer pointer 0x8C RBCNT Word Rx internal byte count Ox8E RCRC 2 words Temp receive CRC 0x96 RSTATE Word Rx internal state 0x98 TSTATE Word Tx internal state 0x9C TBPTR 2 words Tx internal data pointer OxA0 TBCNT Word Tx internal byte count OxA4 TCRC 2 words Temp transmit CRC OxA8 TBASE Word Tx buffer descriptor table base address MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc
32. f the buffer descriptor s status and control word is reserved in QH302 e The LG Rx frame length violation indication bit of the buffer descriptor status and control word is not supported by the QH302 e BISYNC and DDCMP protocols are not supported by the QH302 e The SCC data synchronization register DSR no longer exists e A part of the B2 channel parameters swap RAM position with the D channel parameters when the B2 channel is enabled The parameter positions swap back once B2 is disabled e The HDLC specific parameter RAM of a B channel occupies a larger address space in the QH302 2 1 Dual Port RAM Map The QH302 internal 1176 byte dual port RAM has 576 bytes of usable system RAM and 576 bytes of parameter RAM The system RAM map of the QH302 is unchanged It may be used to hold special RAM microcode packages buffer descriptor tables or other user defined structures Table 1 shows the system RAM map Table 1 System RAM Map Base Offset Width Description 000 0x23F 576 bytes User data memory microcode and buffer descriptors 0x240 0x3FF Reserved not implemented Note As defined in the BAR base address register The parameter RAM map on the other hand has changed In non QH 3 channel mode the mapping change accounts for QH302 specific global parameters and more flexible buffer descriptor placement In QH mode the QH protocol remaps the parameter RAM to accommodate the four serial channels MC
33. his document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freesc
34. iS 21 15 SCM REg ISTE ee erei EEEE EAE AEA AEE EE E EE AE EEEa 23 16 SCM Register in HDLC Mode AAA 23 17 SCM Register in UART le EE 24 18 SCM Register in V 110 Mode A 24 19 SCM Register in Transparent Mode AAA 24 20 SCM Register in OH Mode isccciecicceccccidecsescctscaccastuccencutvcassccescsescatarcsscstessescesaneescpberceecstece s 24 21 Butler Descriptor Format seietan ee Eege EE 25 22 SCC Buffer Descriptor Memory Structure 26 23 Tx Buffer Descriptor Status and Control 26 24 Rx Buffer Descriptor Status and Control 27 25 SCCEL REGIS Ei E 29 26 Host Command REGister sci iiccssciccasisticcinccisessassthccapenchassscedhetenssssesapsrdecdsncsinetsnesdvcsassssosssee 30 Illustrations For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MC68QH302 Supplement to MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc TABLES Table Page Number mille Number 1 System RAM ET 3 2 Non QH Mode Parameter RAM Map 4 3 B2 Channel Parameter locati ns toere ee e eaa AE E REEE AEEA 4 D Channel Parameter Locaton eccecssesseeseceseceseseeceseceaessecesececeseeeaeeeseceeeseeeaeeseeeaeenss 5 OH Mode Paramete RAM Man geed 6 Global QH Mode Field Descriptions 7 QH Type and Revision Number Field Descriptions s sssssssssisssesesetsisssssesesesssesesessses 8 8 B1 Channel Parameter RAN 8 9 B2 Channel Fixed Address Parameters
35. indicates a busy condition or an overrun has been detected by one or both B channels The receiver stops and sets the channel s B_STAT1 BOV Upon a RXE event the host should read each B channels B_STAT1 BOV to determine which channel s are reported For each B channel whose BOV bit is set the host should issue STOP Rx initialize the receive parameters see Section 2 14 QH Parameters Initialization Summary and then issue RESTART RX to restart the channel Tx buffer A TXB event indicates a buffer has been sent in either B1 or in B2 When enabled the TXB interrupt is generated when the last data of the buffer is written to the FIFO but not yet sent This is opposite to the 302 behavior for the last buffer in a frame fo In Rx buffer An RXB event indicates that a buffer has been received either in B1 or in B2 MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 13 Channel Host Commands The host issues commands to the CPM through the command register The host should set the FLG bit when sending a command After executing the command the CPM clears the FLG bit to signal command completion The host should poll the FLG bit before issuing the next command A reset clears the command register Figure 26 shows the fields of the command register 7 6 5 4 3 2 1 0 Figure 26 Host Command Register For non QH operation and f
36. le 14 describes these fields for QH and non QH mode operations 14 13 12 11 10 9 8 7 6 3 2 1 0 15 5 4 mee tert ee Cem Figure 6 RSTATE for HDLC Transparent Channels MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 14 RSTATE Field Descriptions for HDLC Transparent Channels Bits Name QH Mode QH 1 Non QH Mode QH 0 15 MODE 0 HDLC mode Must be programmed to match the mode 1 Transparent mode selected in the SCC mode register SCM CRC CRC 16 Must be programmed to match the corresponding CRC 32 bit in the SCC mode register SCM For internal use must be initialized to zero E 0 Receiving LSB first Must be programmed to match the corresponding 1 Receiving MSB first illegal for HDLC bit in the SCC Mode register SCM 11 B CH B channel in QH mode Must be cleared 0 Not used for B channel 1 Used for B channel sl For internal use must be initialized to zero E For internal use must be initialized to one D channel in QH mode Must be cleared 0 Not used for D channel 1 Used for D channel Page selection 00 B1 channel 00 SCC1 DI SCC2 for UART channel 01 Scc2 10 B2 channel or D channel 10 SCC3 Serial number 1001 B1 or B2 channel selected 1001 SCC1 1011 SCC2 for UART channel 1011 SCC2 1101 D channel 1101 SCC3 MC68QH302 Supplement to the MC68302 User s Manual For More Information On This P
37. m o 0 Not the last BD in Rx BD table 1 The last BD in Rx BD table Interrupt 0 The RXB bit is not set after this buffer is used but RXF operation remains unaffected 1 The RXB bit in the event register SCCE will be set Last Set by the receiver when this buffer is the last in a frame implying the end of frame reception due to a closing flag in HDLC mode or an error 0 Not the last buffer in the frame 1 The last buffer in the frame First Set by the receiver when this buffer is the first in a frame 0 Not the first buffer in the frame 1 The first buffer in the frame os f Jee 4 NO Rx non octet aligned A frame that contained a number of bits not exactly divisible by 8 was received The last data word written into a non octet BD is undefined and should be discarded by software 3 AB Rx abort sequence At least seven consecutive 1 s occurred during frame reception Valid for HDLC mode only CRC error The frame contains a CRC error Overrun A receiver overrun occurred Not set for B channels CD Carrier detect lost The carrier detect CD signal was negated during frame reception Valid for NMSI channels only Notes written by the user before the buffer is linked to the Rx buffer descriptor table Updated by the receiver after the data has been placed into its buffer MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Free
38. n indication bit are no longer supported in the QH302 s buffer descriptor status and control word Figure 21 shows the buffer descriptor format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 Status and Control 2 Data Length Buffer Pointer 24 bits used upper 8 bits must be 0 Figure 21 Buffer Descriptor Format All the buffer descriptors of a particular channel are combined into a single buffer descriptor table A buffer descriptor table forms a circular queue with a programmable length The user programs the tables base addresses using RBASE and TBASE to place the tables in any unused portion of the dual port RAM including any unused parameter RAM The data buffers are free to go anywhere in the address space however internal placement of buffers will not result in better performance Figure 22 shows the BD memory structure MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Dual Port RAM External RAM SCC Buffer Descriptor Data Buffer lt Table Pointers Rx Tx BDPTR RBASE TBASE Data Buffer Le Buffer Descriptors Ad fate SCC Buffer pei Descriptor Table Status and Control Data Length Buffer Pointer
39. ng the receiver s status Note that any modification of parameters should be done only when the channel is stopped or before the SCC is enabled Table 10 B2 Channel Rx Swapped Parameters Base Offset Base Offset B2 Stopped B2 Running Name Width Description 0x500 0x680 RFCR Byte Rx function code 0x501 0x681 Tx function code 0x502 0x682 Maximum receive buffer length 0x504 0x684 Rx buffer descriptor table base address 0x506 0x686 RBDPTR Rx buffer descriptor pointer 0x508 0x688 RBPTR Rx internal data pointer 0x50C 0x68C RBCNT Rx internal byte count Ox50E Ox68E RCRC 2 words Temp receive CRC 0x512 0x692 C_MASK_L Word Constant CRC mask low word 0x514 0x694 C_MASK_H Word Constant CRC mask high word 0x516 0x696 RSTATE Word Rx internal state Notes 1As defined in the BAR base address register 2Parameter location when updating Rx values 3Unsafe location for updating read only MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 11 shows the Tx channel parameter locations when the B2 transmitter is running or stopped See Section 2 6 7 B_STAT2 B Channel Transmitter Status for information on determining the transmitter s status Table 11 B2 Channel Tx Swapped Parameters Basel Offset Base Offset ae B2 Stopped B2 Running vane wn Description TSTATE Word Tx internal st
40. or non QH or NMSI channels the QH302 s command register functions the same as in the 302 The RST and GCI commands are also the same In QH mode however the channel numbers and opcodes are interpreted differently Table 29 shows the QH mode interpretation of the opcodes Table 30 shows the difference in channel numbers between QH and non QH modes Table 29 QH Mode Opcodes for the Command Register B Channel Command D Channel Command Table 30 Command Register Channel Numbers for QH and Non QH Modes Channel Number Non QH Mode QH Mode MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 13 1 B Channel Host Commands The B channel host commands are described in Table 31 Note that the B channel receivers do not have an ENTER HUNT MODE option and must be explicitly stopped and restarted Table 31 B Channel Host Commands B Channel STOP TX STOP TX stops a Tx B channel It must be issued after a transmit error or if the B channel parameters need to be modified STOP Tx clears B_STAT2 BTV of the designated B channel invalidating the channel The B channel transmission is aborted and idle characters 1 s are sent The host can now modify the parameters In HDLC mode an HDLC abort pattern is sent Note If the STOP TX is for a B channel programmed in flag mode see Section 2 6 4 BTMODE B Channel Transmit Mode th
41. r RAM The B1 channel parameter RAM is defined in Table 8 Boldfaced parameters are initialized or used by the host but must not be changed while the channel is running see Section 2 6 Channel Parameter Descriptions when initializing parameters Non boldfaced parameters are for internal use and should not be changed Modification of either B channels parameters should be done only when the channel is stopped or before SCC1 is enabled Table 8 B1 Channel Parameter RAM Base Offset Name Width Description R_F_DATA Rx framer data byte internal FDO Rx Tx framer data out also DTSCC R_F_MASK Rx framer mask byte F_CTR Framer internal counter TUNPACK Unpack a word to 2 bytes B_STAT1 B channel Rx mode amp status internal BNOF B channel number of flags and internal parameters B_STAT2 B channel Tx mode amp status internal BTMODE B channel mode amp status user defined mode bits Rx temp Number of flags counter internal Rx function code 0x481 TFCR Byte Tx function code MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 8 B1 Channel Parameter RAM Continued Base Offset Name Width Description 0x482 MRBLR Word Maximum receive buffer length 0x484 RBASE Word Rx buffer descriptor table base address RBDPTR Word Rx buffer descriptor pointer RBP
42. r occurs MRBLR must hold an even number greater than zero MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 6 12 C_MASK_L H Constant for CRC Check The C_MASK constant is used for the CRC check The values for CRC16 CRC32 modes are shown in Table 21 For software testing an incorrect initialization can be used to force a receive CRC error Table 21 C_ MASK_H L Constants CRC Mode C_MASK_H C_MASK_L CRC16 This field is ignored FOB8 CRC32 0x20E3 DEBB 2 6 13 T_F_MASK and R_F_MASK Tx Rx Framer Bit Masks T_F_MASK and R_F_MASK select what bits are active in the B channel Any combination of the 8 bits may be chosen Figure 14 shows the fields for the framer masks Table 22 describes the masking for sending and receiving These parameters must be initialized if QH mode is selected 15 14 13 12 11 10 9 8 J Figure 14 Framer Bit Mask Table 22 T_F_MASK and R_F_MASK Field Descriptions E BEER ns 0 O Mask the corresponding TXD bit 1 is 0 Mask the corresponding RXD bit the bit S Ge is not received 14 8 M 1 7 driven on the transmit line f A Pape 1 Bit transmitted data will be transmitted se ES EG Note The bit order in this entry is opposite to the bit order in the SIMASK register 2 6 14 Other Channel Parameters All other parameters do not need to be accessed by the user in normal op
43. roduct Go to www freescale com Freescale Semiconductor Inc Figure 7 and Table 15 show the RSTATE fields for UART channels 15 14 13 12 11 10 9 8 7 3 2 1 0 COCCO e o Figure 7 RSTATE for UART Channels Table 15 RSTATE Field Descriptions for UART Channels QH Mode QH 1 Non QH Mode QH 0 For internal use must be initialized to zero 00 SCC1 DI Scc2 Page selection must use SCC2 01 gt Gee 10 SCC3 1001 SCC1 1011 SCC2 1101 SCC3 Serial number must use SCC2 1011 SCcc2 2 6 2 T_MODE Transmit Mode T_MODBE is internal use only but must be initialized to the same initial value as RSTATE 2 6 3 TSTATE Transmit Internal State TSTATE must be initialized by the user Figure 8 and Table 16 show the bit fields 15 14 13 12 11 10 9 8 7 3 2 1 0 Os e w Figure 8 TSTATE Register Table 16 TSTATE Field Descriptions KORCE QH Mode QH 1 Won OH Mode QH 0 For internal use must be initialized to zero Zi es Page selection 00 B1 channel 00 SCC1 01 SCC2 01 SCC2 10 B2 or D channel 10 SCC3 3 0 MSNUM Serial number 1000 B1 or B2 channel 1000 SCC1 1010 SCC2 1010 SCC2 1100 D channel 1100 SCC3 MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 6 4 BTMODE B Channel Transmit Mode The B channel transmit mode byte is valid when operating in QH mode only and contains B channel mode bits Figure 9
44. s serial performance is degraded by 10 relative to the 302 see Appendix A SCC Performance of the MC68302 user s manual 2 16 QH302 UART Protocol The QH302 s UART parameter RAM has been relocated and remapped otherwise UART operation is the same as in the 302 See the latest MC68302 user s manual for UART initialization and operation 2 16 1 QH302 UART Parameter RAM Map The QH302 s UART parameter map is similar to the 302 but parameters were moved to new offsets see Table 36 The two new parameters RBASE and TBASE allow the user to place the buffer descriptor tables in any free space in the dual port RAM see Section 2 6 8 RBASE and TBASE Descriptor Table Base Addresses One control character was removed Table 36 UART Parameter RAM SCC Base Offset Name Width Description 0x80 RFCR Byte Rx function code 0x84 RBASE Word Rx buffer descriptor base address 0x8C RBCNT Word Rx internal byte count 0x92 NOSEC Word Receive noise counter 0x98 TSTATE Word Tx internal state DNA TBCNT Word Tx internal byte count MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 36 UART Parameter RAM Continued SCC Base Offset Name Width Description OxA4 MAX_IDL Word Maximum IDLE characters Rx OxA6 IDLC Word Temporary receive IDLE counter OxA8 TBASE
45. scale Semiconductor Inc 2 12 QH Mode SCC1 Event Register SCCE1 In QH mode the SCC1 event register SCCE1 reports events occurring in both B channels When SCCEI reports an event the user must check each B channels Rx Tx status registers B_STAT1 2 to determine which B channel reported Figure 25 shows SCCE1 7 6 5 4 3 2 1 0 ae Cre Ce Figure 25 SCCE1 Register Each bit of the event register can generate an interrupt maskable by the SCC mask register SCCM SCCE1 7 5 should always be masked for the B channels Table 28 describes the SCCE1 fields Table 28 SCCE1 Field Descriptions a 7 5 Should be masked in the SCC1 mask register their value is undefined in QH mode 4 TXE Tx error An underrun error has occurred Once detected the B channel ends buffer transmission and sends an abort sequence The transmitter sets B_STAT2 BUN and sets SCCE1 TXE Note that the BUN bit can be set in both channels Upon a TXE event the host should read each B channels B_STAT2 BUN to determine which channel s underran For each B channel whose BUN bit is set the host should issue STOP TX initialize the transmit parameters see Section 2 14 QH Parameters Initialization Summary and then issue RESTART TX to restart the B channe s I Rx frame A RXF event indicates a complete frame has been received in one or both B channels Host must check each BD table to determine which channel s has a new frame Rx error A RXE event
46. smission is aborted and idle characters 1 s are sent The host can now modify the parameters see Section 2 14 QH Parameters Initialization Summary for parameter initialization In HDLC mode an HDLC abort pattern is sent Note As long as the B2 channel is running the D channel parameters will remain in their swapped position RESTART TX RESTART TX initiates transmission on the channel following a STOP TX command or an underrun error The channel is now considered running prohibiting parameter modification and the first Tx buffer descriptor is polled ENTER HUNT ENTER HUNT MODE is generally used to abort reception of the current frame and restart reception of MODE the next frame It is the same as in the 302 MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 14 QH Parameters Initialization Summary All parameters must be initialized after every software or hardware reset and before enabling any serial channel but only some of them should be initialized before every RESTART See Table 33 Table 34 and Table 35 for the initialization of the B channels when operating in QH mode Initialization of all other serial channels parameters boldfaced parameters in Section 2 7 Non QH Channel Parameter RAM should be initialized as in the 302 with the addition of RSTATE and T MODE Each channels parameters can be mo
47. st time for QH 0 OH protocol over SCC1 has already started 1 First time to start QH protocol over SCC1 transmitter Must be set by the user only before enabling SCC1 or after hardware underrun Should not be set when B1 and or B2 channel s was were stopped using STOP TX Valid only if QH mode is selected Set by the user and cleared by the QH302 QH mode 0 Non QH mode QH protocol is disabled SCC1 functions as in 302 operation 1 OH mode QH protocol is enabled Must be set even if the QH protocol is not currently running but will in the future 2 2 2 QH Type and Revision Number QH type and revision number is initialized by the CPM after a hardware reset or a CPM reset command It holds the chip type and the internal revision code number Software can use the type to distinguish between a 302 and a QH302 Figure 5 shows the bit fields and Table 7 describes them QH type and revision number should be initialized to 0x8002 for the first QH302 revision MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 13 12 11 10 9 8 Z 6 5 4 3 2 1 0 15 14 Gg cl con a A EN TE CO EE E Figure 5 QH Type and Revision Number Table 7 QH Type and Revision Number Field Descriptions owe ome ee 15 Type Chip type 0 302 chip 1 QH302 chip kie For internal use must be initialized to zero Internal revision number 2 3 B1 Channel Paramete
48. stopped D channel parameter RAM with B2 running 0x52C O0x52F Reserved not implemented 0x530 0x56F Buffer descriptors 0x570 0x57F Buffer descriptors DRAM refresh parameters 0x580 0x5AB SCC2 parameter RAM Ox5AC Ox5FF Reserved not implemented 0x600 Ox60F B2 channel fixed address parameter RAM 0x610 Ox65F Buffer descriptors Ox660 0x67F same as corresponding segment in Table 2 0x680 0x6AB D channel parameter RAM with B2 stopped B2 channel parameter RAM with B2 running MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 5 QH Mode Parameter RAM Map Continued Base Offset Description Ox6AC Ox6BF B2 channel fixed address parameter RAM Ox6CO Ox7FF Reserved not implemented Note As defined in the BAR base address register 2 2 Global QH Parameters The QH302 has two QH specific global parameters global QH mode and QH type and revision number 2 2 1 Global QH Mode Global QH mode is a memory mapped register for setting up QH operation The user must initialize it before enabling any of the SCCs Figure 4 shows the bit fields and Table 6 describes them 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fach ROESER E ESERESEREAESESEOER Figure 4 Global OH Mode Register Table 6 Global QH Mode Field Descriptions For internal use must be initialized to zero Fir
49. the last byte is sent Underrun A transmitter underrun occurred Not set for B channels cT Clear to send lost The CTS for an NMSI channel or L1GR layer 1 grant in IDL GCI for the D channel was lost during frame transmission Notes written by the user before the buffer is sent Status flag set by the transmitter after the entire data buffer has been sent 2 11 QH302 Rx Buffer Descriptors for HDLC Transparent Mode The receiver uses the Rx buffer descriptor to report information about the received data Figure 24 shows the status and control word Table 27 describes the status and control bit fields 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 E W L E NO AB CR ON cD Figure 24 Rx Buffer Descriptor Status and Control MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 27 Rx Status and Control Field Descriptions CEA 15 E Empty 0 The data buffer associated with this BD has been filled with data or data reception was aborted due to error condition The host is free to examine or write to any field of the BD 1 The data buffer associated with this BD is empty The host should not write to any field of this BD after it sets this bit Cleared by the receiver when the buffer is full or frame reception was stopped due to an end of frame or an error w E e
50. ze the channel parameters and then issue RESTART RX reactivating the channel RESTART RX clears B_STATI BOV and sets B_STATI BRV MC68QH302 Supplement to the MC68302 User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 6 7 B_STAT2 B Channel Transmitter Status B_STAT2 contains B channel transmitter status bits and internal use bits After reset the user must clear this byte for both B channels After this initial clearing however the user should access this byte using host commands only see Section 2 13 1 B Channel Host Commands for more information on how host commands affect B channel status bits Figure 12 shows the fields and Table 20 describes them 7 6 5 4 3 2 1 0 i eB e o Figure 12 B_STAT2 Byte Table 20 B_STAT2 Field Descriptions For internal use must be initialized to zero B channel transmitter underrun must be initialized to zero D No underrun error 1 Underrun error For internal use must be initialized to zero B channel transmitter valid must be initialized to zero 0 Bchannel transmitter disabled 1 B channel transmitter enabled For internal use must be initialized to zero 2 6 7 1 B Channel Underrun and B Channel Transmitter Valid Flags B_STAT2 BUN reports underrun errors and B_STAT2 BTV reflects the channel s activation status When the host does not prepare the necessary data for the complete transmission of the curr

MC68QH302 Supplement to the MC68302 Integrated Multiprotocol

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