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PC-CamLink™ User`s Manual 405-00009-00

1. Figure 34 PC CamLink Power Cable 42 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Appendix B Video Overlay Overlay is graphical data possibly alphanumeric or other symbology that appears on top of video data on a video display There are several different techniques for achieving an overlay on video data acquired on Coreco Imaging Inc s image capture products All techniques described are for video in a window on a single monitor driven by the system VGA as the image capture products have no on board display The techniques up until recently have pro vided a destructive overlay which has disadvantages These techniques will be discussed for completeness Howev er there are now techniques which can provide a non destructive overlay which is preferable Destructive Overlay There are two techniques for creating destructive overlays Destructive means that video information and the overlay information reside in the same area of memory The overlay information is written directly on the video information destroying it The drawback with destructive overlay is if you want to view live video at 30 fps 25 fps or any speed other than static the video information is also overwriting the overlay information and destroying it In the two destructive overlay techniques discussed there are no inherent limitations on acquisition modules that can be used on the image capture product
2. Use the worksheet at the end of this manual to document your changes to the factory configuration 123 123 JP1 HN o o JP2 JP3 Ho o JP4 To JP5 JP6 Bl o JP7 ni c C JP9 MN o o JP8 123 123 Rev 01 July 30 2001 Figure 2 PC CamLink Factory Default Configuration PC CamLink User s Manual 405 00009 00 Hardware Installation Before installing the board turn off power to the computer and peripherals Discharge static electricity from your body by touching a metal part of the computer chassis or use a static protection strap if available NOTE Hardware Jumpers on the PC CamLink board set the default power up state of the Parallel I O port PIO and the TTL Differential Opto coupled outputs on the I O connector Refer to Appen dix B for information on these jumpers 1 Remove the computer chassis cover Locate an empty PCI bus slot PC CamLink may fit into a partially ob structed slot Remove the back panel slot cover if necessary for the PC CamLink connector to pass through PC CamLink Board Figure 3 Install the PC CamLink in the Computer 2 Slide the PC CamLink board carefully into the slot so the end bracket slips properly into the filler bracket Make sure the board is pressed firmly into the connector and does not touch other boards components or h
3. 2001 23 PC CamLink User s Manual 405 00009 00 m i LUTOPG 7 0 Ki L1PSIZE Li BYTEL LOPSIZE LOBYTEL Figure 15 8 bit two tap input For 8 bit two tap input program both LUTS for Pixel Size of 8 bits LOPSIZE and L1PSIZE select Port A as the Low Byte for LUTO LOBYTEL and Port B as the Low Byte for LUT1 LIBYTEL and use the eight Page Select bits to change the LUT Page LUTOPG and LUT1PG for independent selection of up to 256 different LUT trans forms for each tap Only the lower 8 bits of each LUT output are stored in the image memory LUT1 n Ji C Port B T A L1PSIZE LOBYTEL Figure 16 8 bit three tap input For 8 bit three tap input program LUTO for Pixel Size of 16 bits LOPSIZE and LUTI for Pixel Size of 8 bits LIPSIZE Select Port A as the Low Byte for LUTO LOB YTEL Port B as the High Byte for LUTO LOBYTEH and Port C as the Low Byte for LUT1 LIBYTEL LUTO has no available page select bits LUT1 has eight Page Select bits LUT1PG The 16 bit output of LUTO and the lower 8 bits of LUT1 output are stored in the image memory 24 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Port B PortA LOBYTEH LOBYTEL Figure 17 Single Tap 10 to 16 bit input For 10 bit 12 bit 14 bit or 16 bit single tap input program the correct Pixel Size LOPSIZE select Port A for the Low Byte LOBYTEL and port B for the High Byte LOBYTEH and use the a
4. 49 45V 5 V power output 2 4 6 8 10 12 14 Digital Ground 16 18 20 22 24 26 Digital Ground 28 30 32 34 36 38 Digital Ground 40 42 44 46 48 50 Digital Ground Rev 01 July 30 2001 41 PC CamLink User s Manual 405 00009 00 CAMERA CABLES The Camera Link connector is compatible with 3M Cable Assembly 14x26 SZLB xxx 0LC x is the Shell option B Thumbscrew Shell Kit T Thumbscrew Overmold Shell xxx is cable length 100 1 meter 20022 meters 30023 meters 400 4 5 meters 50025 meters 700 7 meters A00 10 meters The 3 meter cable 14B26 SZLB 300 OLC is available from Coreco Imaging l O CABLES The following I O Cables are currently offered for the PC CamLink 26 pin I O Connector Table 4 I O Cables Cable Part Number Description Power Cable 509 00078 00 12 pin Hirose connector for 12 Volt power 1 BNC for TTL_INO Trigger 0 The pin out of the Hirose connector is not guaranteed to work with all cameras Make sure your camera requires power on pin 2 and ground on pin 1 CAUTION DO NOT use the PCVision or PCVisionplus break out cables with the PC CamLink Damage to the PC CamLink will result Table 5 Power Cable Pin Out 12 pin Hirose Signal Description 26 pin I O 1 12 Volt return 10 2 12 Volts DC 1 3 12 no connection BNC connector conductor TTL_INO TTL input 0 shield DGND Digital Ground 18 lt 6 feet gt BDL 26 pins 12 pins TTL_INO 6 inches
5. Camera Connection 0 0 0 eee eee Figure 5 Configurator Startup Screen oo ooococcooccoccoccoco o Figure 6 PC CamLink Block Diagram ooooooocococcoocoooo Figure 7 Acquisition and Timing 0 20s eee ee eee eee Figure 8 Basic Opto Isolator 0 0 0 0 cee eee eee Figure 9 Opto Coupled Input Circuit ooooooocoocoocooooooooo Figure 10 Input to Opto Coupled Circuit oooooooooooooooooo Figure 11 Opto Coupled Output Circuit o o oo oooococoooooooo Figure 12 Output from Opto Coupled Circuit o ooooooooooooo Figure 13 Input LUT ori ar ad Figure 14 Single Tap 8 bit Input ooooooooococococcooooo oo Figure 15 8 bit two tap input 0 0 0 0 eee Figure 16 8 bit three tap input 0 0 0 00 eee Figure 17 Single Tap 10 to 16 bit input oooooococcoocoooo Figure 18 Two Tap 10 or 12 bit input 0 00 0 Figure 19 24 bit RGB input 0 0 22 eee ee eee eee Figure 20 32 bit RGB cion e ee ee eS Figure 21 32 bit aRGB a a eee Figure 22 16 bit 565 RGB 5 036008 csc esas Ie RR Rev 01 July 30 2001 PC CamLink User s Manual Page TL eI 39 PE la 40 m 41 A 42 VIDA ERN UR Ee Reg 42 vii PC CamLink User s Manual 405 00009 00 Figure 23 Digital Input Buffers o ooo oooocoococrorororr I eens 29 Figure 24 Single Tap ob ob A OR e V doi de 30 Figure 25 Odd EvenPIX
6. 16 bit images in normal or 4 2 2 format e Color plane separation during transfer possible e Output clipping of Windows colors during bus master to eliminate conflicts with Windows reserved colors External Trigger Timing e Advanced multi trigger acquisition modes e 2 External Trigger available as differential TTL or Opto coupled e Software triggering for host controlled acquisition e Trigger divider allows precise control over incoming trigger events Programmable Window Generator e Enables acquisition of subset of camera image e Maximum window size 64K by 64K resolution of 1 pixel and 1 line e Programmable independent X Y decimation by 2 4 8 16 performed during image acquisition e Color images stored using packed 24 bit or 16 bit formats or sequential color planes Camera Timing and Control e Camera Link timing inputs Clock PCLK Line valid LVAL Frame valid FVAL Data valid DVAL and spare input SPR e External Sync and Programmable Integration outputs e 4 Static control lines for selecting camera modes e Serial port interface between camera and PC CamLink frame grabber Look Up Tables LUTs e Dual 16 by 16 LUTs for pixel transformations e Arithmetic operations on or between 8 bit image data 12 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Multi Tap Data Resequencing e Reformats multi tap data on the fly e Provides line row resequencing to output most any multi tap image in normal ra
7. OPTO OUTI collector Opto coupled output OPTO OUTO collector Opto coupled outputs Ground input emitters Opto coupled input OPTO INI positive anode Opto coupled input OPTO INI negative cathode Opto coupled input OPTO INO positive cathode Opto coupled input OPTO INO negative anode Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Parallel I O Connector The Digital I O is available on a 50 pin dual row post header connector This provides parallel I O capability of 8 input and 8 output high drive TTL channels This port allows controlling or monitoring external events The pin out is OPTO 22 compatible All even numbered pins are connected to Digital Ground Jumpers on the PC CamLink board set the power up state of the outputs Table 3 50 Pin Dual Row Header Pin Signal name Description 1 5V 5 V power output 3 5 no connection 7 9 no connection 11 STROBE_O Strobe Output Output data latch 13 STROBE_I Strobe Input Input data latch 15 I O INT Interrupt Input 17 IN7 Digital Input pin 7 19 IN6 Digital Input pin 6 21 INS Digital Input pin 5 23 IN4 Digital Input pin 4 25 OUT7 Digital Output pin 7 27 OUT6 Digital Output pin 6 29 OUTS Digital Output pin 5 31 OUT4 Digital Output pin 4 33 IN3 Digital Input pin 3 35 IN2 Digital Input pin 2 37 IN1 Digital Input pin 1 39 INO Digital Input pin 0 41 OUT3 Digital Output pin 3 43 OUT2 Digital Output pin 2 45 OUTI Digital Output pin 1 47 OUTO Digital Output pin 0
8. The second non destructive technique is to bus master video data to the secondary surface and put the overlay in the primary surface In this method the secondary surface must be a 16 bit YCrCb 4 2 2 surface The frame grabber must have 16 bit YCrCb data to bus master to this surface Coreco Imaging Inc s image capture products can provide data in this format This 16 bit data can be either color data from an NTSC or PAL camera or monochrome data from an RS 170 or CCIR camera The overlay is accomplished by mixing in video data from the secondary surface into the video window of the ap plication GUI in the primary surface using a chroma key A specific chroma value is designated as the hardware chroma key and wherever this value appears in the primary surface the video data from the secondary surface is substituted for it in the display The application GUI overlay and all windows graphics reside in the primary surface and the video is mixed in wherever it is needed by placing the chroma value There are no problems with color dots using this technique There are also no problems with the overlay being turned off as in the previous technique since Windows is managing all of the graphics while video is just being quietly mixed in by the chroma key The primary surface can be run at whatever bit depth is best for the application Windows VGA Display Memor Key Color par 2 A VGA Display Overlay Data
9. be constantly updated by the host Windows VGA Acquired Image Display Memory Transfer Image Key Color to Host Memory Jk y S VGA Display PCI Bus Primary Surface Streams Processor Secondary Surface chroma key mix Overlay Data P Figure 37 Bus Master to the Primary Surface Limitations There are some limitations with this technique First there are the normal restrictions incurred with Direct Draw of video data to the VGA card VGA bit depth matching and color dots As always we have to match the pixel bit depth of the output of the frame grabber with the VGA display If 8 bit monochrome data is being acquired the VGA card primary surface must be set at eight bits to bus master to it This equates to a computer display of only 256 colors to be shared by Windows and all of the gray scale values of your video which ideally would be 256 just by them selves Windows will demand a minimum of 20 colors usually numbers 0 9 and 246 255 in the palette If video data is bus mastered to the VGA memory with those values reserved for Windows colors the pixels with those values will take on these colors instead of the gray scale values that were intended We call these color dots and they can be distracting or unacceptable The technique used to remove color dots is to clip the data with a Look Up Table before it is transferred This leaves only 236
10. camera definition name use the updated information Your files are saved to the Config User directory You cannot overwrite the origi nal camera definitions All User and original definitions are displayed in the List of Cameras e A Configuration File defines the installed frame grabbers and the camera port assignments The configura tion file calls out the camera file names used in the camera database The configuration file does not contain the camera parameter values e A Portable Configuration File defines the frame grabbers port assignments and camera parameter values The portable configuration file does not call out camera definitions in the camera database File Names All IFC examples try to load a default configuration file The name of the default file changes with the frame grabber board used The PC CamLink examples on the CDROM look for the file name Inktest txt 10 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Part 2 Hardware e The PC CamLink is an image capture board that uses the Camera Link interface to acquire images from digital output or digitizing cameras up to 24 bits e The PC CamLink provides fully programmable timing and a variety of trigger and I O options that are ideal for many machine vision applications e The PCI bus interface incorporates a hardware scatter gather table for highly efficient fully automated and simultaneous image transfers from the image memory e P
11. defines the number of lines acquired to create a frame Alternatively a stop trigger can be used to end acquisition at the end of the current line Area Scan After the trigger occurs the next rising edge of FVAL begins the acquisition A stop trigger can be used to end acquisition at the end of the current frame PC CamLink Triggers PC CamLink has two active trigger inputs TriggerO and Trigger1 Both trigger inputs support three different signal types differential TTL and Opto isolated Refer to the Block Diagram in Figure 6 These are the Hardware Trigger Sources input on the 26 pin D Sub I O Connector The differential input is EIA 644 LVDS Both trigger circuits have a glitch detector circuit enabled or disabled by software There are also two software triggers The triggers can be programmed to start acquisition end acquisition start the external sync counter or cause an interrupt The trigger input must be re armed to acquire subsequent frames All trigger features can be enabled and configured in the Camera Configurator utility and saved in a camera file You can also use the IFC Parameter Access functions in the Class CICamera to change the trigger parameters All PC CamLink parameters are listed in an Appendix of the IFC SDK Software Manual Pay special attention to Hard ware Specific Classes and functions for the PC CamLink in Class CPCLink Class CICapmod and the Acquisition Functions in Class CICamera NOTE Each frame gra
12. 0 1 2 TTL Outputs tri stated disabled on power up 2 3 TTL Outputs enabled on power up JP8 OPTO OUT 1 0 1 2 Opto Outputs high 1 on power up 2 3 Opto outputs low 0 on power up JP9 DIFF_OUT 1 0 1 2 Differential Outputs high 1 on power up 2 3 Differential Outputs low 0 on power up 123 123 123 x Square Pad for Pin 1 position 1 2 position 2 3 Figure 1 Jumper Positions 4 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Factory Default Configuration The following table gives the factory default settings for all jumpers on the PC CamLink board All outputs are dis abled or tri stated except the Opto outputs during power up and set to default to 1 if enabled The 5 Volt 475 ohm resistor is chosen for the two Opto coupled inputs Figure 2 shows this configuration Jumper Position JP1 1 2 JP2 1 2 JP3 1 2 JP4 1 2 JP5 1 2 JP6 1 2 JP7 1 2 JP8 1 2 JP9 1 2 Pins Controlled Function OPTO IN 1 0 Opto Input 0 Input Resistor 475 ohms 5 Volt operation DIFF OUT 1 0 Differential Outputs and CC4 Tri Stated disabled on power up OPTO IN 1 0 Opto Input 1 Input Resistor 475 ohms 5 Volt operation TTL OUT 2 0 TTL Outputs high 1 on power up OUT 7 0 Parallel Outputs high 1 on power up OUT 7 0 Parallel Outputs tri stated disabled on power up TTL OUT 2 0 TTL Outputs tri stated disabled on power up OPTO OUT 1 0 Opto Outputs high 1 on power up DIFF OUT 1 0 Differential Outputs high 1 on power up
13. 5V Maximum Reverse Voltage Pi 45 mW Maximum Input Power Dissipation PE Connecting to a TTL Output Current Sinking Output V de 4 peer gt Mu amet enel v TTL Output L 4 Output v AAA Connecting to a O Vcc or PWR Output Current Sourcing Output ae Relay pullup a sie w y 4 mi E p i A dc CL arr common Figure 10 Input to Opto Coupled Circuit Rev 01 July 30 2001 19 PC CamLink User s Manual 405 00009 00 Opto Coupled Output Circuits P Jumper vec 7 P8 2Kohm E Value e VCC or sonal too ohm y 24 p e oPro oc e GND Pio ri tl Figure 11 Opto Coupled Output Circuit Figure 11 shows the internal circuitry in the Opto Coupled outputs When the internal logic is one the diode and transmitter are on and the open collector connection OPTO_OC is pulled low When the internal logic is zero the diode and transmitter are off and the OPTO_OC is tri stated or pulled high depending on the external circuit Jumper JP8 selects the state of the two opto coupled outputs only during power up until the FPGA files are loaded and the PC CamLink initialized Figure 12 shows two circuits for using the output When the internal logic goes high the diode and transistor are turned on and the OPTO_OC output goes low The output transistor can be connected as a Current Sinking Output The component values depend upon the vol
14. C CamLink uses the high data transfer rates of the PCI bus to eliminate the need for on board processing or display circuitry Image display and processing is handled by the host computer resources The linear format image memory allows acquisition of a variety of image sizes The image memory behaves as a temporary buffer between the camera interface and the host PCI bus system e The PC CamLink is capable of bus mastering image data directly to a destination memory within the PCI bus system such as system memory or VGA memory Transfer rates in excess of 100MB Ss can be sustained depend ing upon the host capabilities Images can be transferred to host memory in a fraction of the time that they were acquired By minimizing the PCI bus transfer time and CPU overhead more bandwidth is available for process ing or other system resources Rev 01 July 30 2001 11 PC CamLink User s Manual 405 00009 00 FEATURES Sensor Interface e Camera Link Base Mode up to 24 bit differential digital data input from 20 MHz up to 62 5 MHz e 8 10 12 14 16 or 24 bit single tap e 8 10 or 12 bit dual tap e 24 bit RGB color 8 bits per color Image Buffering and Output e 16MB high bandwidth SDRAM supports acquisition rates up to 187 5MB s 24 bits at 62 5 MHz e Provides ROI cropped transfer to reduce data volume e On the fly re sequencing of image data for multi tap cameras e Data re formatting to allow non destructive overlays Transfer 8 bit or
15. Coreco Imaging Inc PC CamLink User s Manual 405 00009 00 Rev 01 July 30 2001 CORECO IMAGING PC CamLink User s Manual Document Number 405 00009 00 Revision 01 July 30 2001 Copyright Coreco Imaging Inc 2001 All rights reserved Printed in the United States of America All copyrights in this manual and the hardware and software described in it are the exclusive property of Coreco Imaging Inc and its licensors Claim of copyright does not imply waiver of Coreco Imaging Inc s or its licensor s other rights in the work See the following Notice of Propri etary Rights NOTICE OF PROPRIETARY RIGHTS This manual and the related hardware and software are confidential trade secrets and the property of Coreco Imaging Inc and its licensors Use examination reproduction copying transfer and or disclosure to others of all or any part of this manual and the related documentation are pro hibited except with the express written consent of Coreco Imaging Inc Portions of the software library use the Halo Image File Format Library which is a copyrighted product of Media Cybernetics The information in this document is subject to change without notice Coreco Imaging Inc makes no representations or warranties with respect to the contents of this manual and specifically disclaims any implied warranties of merchantability or fitness for a particular purpose Coreco Imag ing Inc assumes no responsibility for err
16. E S oidor RA As E 30 Figure 26 Two Line Segments 0 0 20 oe ee ee IA e nee n eres 31 Figure 27 Two Reverse Line Segments o oo oooococoococro eee eee 31 Figure 28 Two Converging Line Segments 0 0 0 0 ccc cee eee eee 31 Figure 29 Interline secs so hak ens tae ais A Sah a eh Rd Oe bed a 32 Figure 30 Three Line Segments nee eror 24 d babes Aw REED EUR Se lee ESPER 32 Figure 32 Programming Design 0 0 cee cette eee eens 34 Figure 32 PC CamLink Board and Connectors 0 0 0 eee eee eee 38 Figure 33 Connector Pin Orientation ss sss e peresa cesa uona nuaa cece teen eee 38 Figure 34 PC CamLink Power Cable 0 0 0 0 42 Figure 35 Destructive Mix in VGA Memory 00 0 eee eee eens 43 Figure 36 Destructive Mix in Host Memory 0 00 eee eee eee eee 44 Figure 37 Bus Master to the Primary Surface 00 0 eee eee eee 45 Figure 38 Bus Master to Secondary Surface 0 0 0 eee ee 46 Figure 39 PC CamLink Configuration Worksheet 1 1 2 00 0 cece eee eee eee nee 47 viii Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Part 1 Introduction Welcome to the PC CamLink User s Guide The purpose of this manual is to help you obtain the maximum performance from the PC CamLink This guide explores how to use key hardware features and software tools which make This manual covers the installation setup and use of the PC CamLink hardware and IFC SD
17. E B Acquired Image Primary Surface Transfer Image to Host Memory P chroma key mix PCI Bus Secondary Surface Figure 38 Bus Master to Secondary Surface 46 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Use this worksheet to document your configuration 123123 JP Eo o Eo 9 JP2 JPO O o 0 o JP8 123 123 Figure 39 PC CamLink Configuration Worksheet Rev 01 July 30 2001 47 PC CamLink User s Manual 405 00009 00 48 Rev 01 July 30 2001
18. GE L Y Expansion TTL IN1 _ ry Slot Trigger DIFF_IN1 9 97 MUX K OPTO IN1 TTL_IN2 gt PRI lt Y Image Image DIFF OUT 2 H Olite EXSYNC lt Memory O Memory TTL_OUT 3 H eens DIFF_OUT 2 Control P l TTL OUT 3 OPTO OUT 2 l OPTO OUT 2 DMA 32 Table Data In 8 gt r Strobe In 8 V PCI Bus interrupt gt Parallel Control L2 Interface CITUR Port Registers Data Out 8 K Strobe Out f 1______ Software PIO Connector Timer 32 PCI bus Figure 6 PC CamLink Block Diagram 14 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Acquisition Mode The PC CamLink slaves to the camera through the Camera Link connector The timing signals are input directly to the PC CamLink timing control The PC CamLink supports area scan and line scan cameras and sensors Clock Data valid Line valid TUVUVUVUVUVVUV UU Frame valid SF Master H Slave PA PC with PC CamLink Figure 7 Acquisition and Timing Normal Acquisition The beginning and ending of a normal acquisition is based on the framing signal FVAL frame enable in area scan mode or LVAL line enable in line scan mode Line Scan In Line Scan mode The Vertical Active VACT defines the number of lines acqu
19. K software development kit This manual is meant to explain most of what you need to know about PC CamLink to take advantage of the features designed into it After installing your hardware and software please take the time to read the Software Release Notes and any readme files for the latest information available The Software Release Notes are available in electronic form on the CD ROM and on your system after you have installed the ITEX software Introduction and Overview PC CamLink is a PCI bus plug n play board that provides image capture for Camera Link digital camera ap plications PC CamLink offers efficient Camera Link M cabling for camera input and general purpose I O for con trolling or monitoring external events PC CamLink supports the Base Mode configuration of the Camera Link in terface This means there is one Camera Link connector supporting one camera input up to 24 bits The PC CamLink supports 8 10 12 14 and 16 bit monochrome and 24 bit RGB color input One of the most important features of PC CamLink is the ability to reformat multi tap data into normal raster scan images in real time Installation and Setup This section describes how to quickly install PC CamLink board and IFC software run the diagnostic software con nect a camera and start acquiring images NOTE Please install the IFC Software before installing the PC CamLink board System Requirements for using PC CamLink e PCI bus compute
20. LUTO LOBYTEL Port B as the High Byte for LUTO LOBYTEH and Port C as the Low Byte for LUT LIBYTEL The input multiplexers are hard wired to present the same 565 RGB data to both LUTs 28 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Parallel I O The 16 bit digital I O port has 8 TTL inputs and 8 TTL CMOS outputs The pin out of the 26 pin connector is found in Appendix A The directions input output cannot be changed The I O port includes support for the following e Interrupt generating input e Input latching e Read status of latched data or current states at input pins Output strobe for latching an external device The I O port inputs can be used in pass through mode or latched mode Figure 23 illustrates the two paths In latched mode a strobe input latches the state of the inputs into a buffer Reading the input data actually reads the latch buffer In pass through mode reading the input data actually reads the pass through buffer or the current live state of the input Pass through Buffer 8 bit 8 bit input data data strobe input Figure 23 Digital Input Buffers Rev 01 July 30 2001 29 PC CamLink User s Manual 405 00009 00 MULTI TAP FORMATS Multi tap area scan and line scan cameras output image data in a variety of pixel sequences An important PC Cam Link feature is the ability to transfer images to the host i
21. amera Control 3 pos 12 15 CC4 Camera Control 4 pos CTL4 25 2 CC4 Camera Control 4 neg 13 13 SHIELD Inner cable shield 26 26 SHIELD Inner cable shield Rev 01 July 30 2001 39 PC CamLink User s Manual l O Connector 405 00009 00 The 26 pin D Sub connector contains TTL Differential and Opto coupled programmable inputs and outputs and 12 Volt power Jumpers on the PC CamLink board set the power up state of the outputs 00 1 OV tA 4 OQ L2 y z NNNNNN DNDN e RRR Re rR KF O NMNPWNKFK TDOWANANANHKWNK CO 40 Signal name 12_OUT DIFF_INO DIFF INO DIFF_IN1 DIFF_INI XTTL_OUTO XTTL OUTI XTTL INO XTTL INI 12 RET DIFF OUTO DIFF OUTO DIFF_OUT1 DIFF_OUTI GND XTTL_OUT2 XTTL_IN2 GND OPTO_VCC_IN OPTO_OC_1 OPTO_OC_0 OPTO_GND_IN OPTO_IN1 OPTO_IN1 OPTO_INO OPTO_INO Table 2 I O Connector Description 12 Volt Power output Differential input DIFF_INO positive Differential input DIFF_INO negative Differential input DIFF_IN1 positive Differential input DIFF INI negative TTL output TTL OUTO TTL output TTL OUTI TTL input TTL INO TTL Input TTL INI 12 Volt return Differential output DIFF OUTO positive Differential output DIFF OUTO negative Differential output DIFF OUTI positive Differential output DIFF OUTI negative Digital ground TTL output TTL OUT2 TTL input TTL IN2 Digital ground Opto coupled outputs VCC input base pull up Opto coupled output
22. amera connected The program tests the internal timebase and a camera that supplies timing could cause false failures Do not connect or disconnect cameras with the computer power on Because the connectors pro vide 12 Volt power the camera or PCVision could be damaged by hot plugging 1 Double click on the Diagnostics icon in the IFC program group 2 The program will report back any hardware failures it finds for each module in a DLG file called DIAG located in the C IFCroot BIN directory If there is a failure contact your local field applications engineer to verify the problem or contact Customer Support at Coreco Imaging Inc Connect a Camera and Acquire an Image e Use the Camera Configurator Utility to match your camera or video source to the correct video port initialize the system and acquire a picture You are now ready to connect and configure a camera and acquire an image First shut down the computer NOTE Do not connect or disconnect cameras with the computer power on The camera or PC CamLink could be damaged by hot plugging 1 Turn power off if you have not already done so 2 Connect your video source to the 26 pin Camera Link connector Refer to Figure 4 NOTE The Camera Link cable does not supply power to the camera Use an external supply or the sepa rate PC CamLink Power Cable 509 00078 00 shown in Appendix A of this manual Camera PC CamLink Boar
23. available page select bits LUT1 has eight Page Select bits LUTIPG The 16 bit output of LUTO and the lower 8 bits of LUTI output are stored in the image memory 0x0 Port C Port B Port A L1BYTEH LOBYTEL Pe Figure 20 32 bit RGBa For 32 bit RGBa data from a 24 bit RGB input program LUTO and LUT Page Size for 16 bit input LOPSIZE and L1PSIZE Select Port A as the Low Byte for LUTO LOBYTEL and Port B as the High Byte for LUTO LOBY TEH Select Port C as the Low Byte for LUT1 LIBYTEL and zero as the High Byte for LUT1 LIBYTEH The 16 bit output of LUTO and LUT are stored in the image memory Rev 01 July 30 2001 27 PC CamLink User s Manual 405 00009 00 Port C Port B L1BYTEH LOBYTEL e Figure 21 32 bit aRGB For 32 bit aRGB data from a 24 bit input program LUTO and LUTI Pixel Size for 16 bit input LOPSIZE and L1PSIZE Select zero as the Low Byte for LUTO LOBYTEL and Port A as the High Byte for LUTO LOBYTEH Select Port B as the Low Byte for LUT LIBYTEL and Port C as the High Byte for LUT1 LIBYTEH The 16 bit output of LUTO and LUTI are stored in the image memory Port C Port B Port A L1BYTEL LOBYTEH LOBYTEL L1PSIZE L1PSIZE 565 RGB 565 RGB 16 16 Figure 22 16 bit 565 RGB For 16 bit 565 RGB data from a 24 bit input program LUTO and LUTI Pixel Size for 16 bit 565 RGB mode LOPSIZE and L1PSIZE Select Port A as the Low Byte for
24. bate Shs 22 LUT Input Modes 00 iia RE Ob de SERRE eR Med eet 23 Parallel VO a ue hu ERI bb E vete tp Ee 29 Multi tap Formats on cco gd e e a ee dd abd ec dd 30 Single TP bins ibe Sad oh ha Gann tates Meet SF OE cales Ea 30 Rev 01 July 30 2001 V PC CamLink User s Manual 405 00009 00 Odd Even Pixels nane nevux Tr v Ub A EPA EU 30 Dual Tap with Line Segments 0 0 0 eee I I 30 Dual Tap with Reversed Line Segments lesse 31 Dual Tap with Converging Line Segments ooooooocoococooooro eee ee eee 31 Dual Tap Interline zoe er Ee Ge SES eee ee eee ees 32 Three Tap with Line Segments 0 0 cece cece eens 32 Part 3 Software OVERVIEW oh act dents Wie dux D EVE UNS TOS hae ooh ee ie PEE ERA 33 Visual C Programming with MFC 0 cee eee eee 33 Multiple Instances oc io e nts edi eee 33 Multi Threading 5 D acta ep pepe be A epi eb re epe ed 34 Creating a Project File cc cas cone ERES TS lis GREASE URSUS 35 Part 4 Examples Quick Confis x enceinte oe Pie ban ofa Neh PIRE 36 Grab Example 4 jeden di EPIS A RESCUE Eb ue obi dunt E 36 Interr ipt Example a2 ex cheer se dee tains shoe ee SMe e aes et SAS Ee OPT Ease tates wee a ton 36 Sequence ACUTE a A A IE dab i A en oe 36 Mideo amp Overlay ivi RA RA IIS E ERAS le 37 Large Format Acquire pais RE re et na ae a id a at 37 Multi Threaded Processing Appilication 0 0 00 eee eee eee eens 37 Visual Basic Example oes Sins e
25. bber supported by IFC has different trigger set up requirements and functions Pay special attention to notes in the Acquisition functions that refer to specific hardware sup ported by specific functions For example many acquisition functions with trig in the function name apply only to the PCVision frame grabber Trigger Input Divider The PC CamLink incorporates a trigger divider The divider may be used to rate divide one of the trigger inputs TriggerO or Trigger1 under software control The divider provides a programmable division of 1 to 256 This fea ture is particularly useful in line scan applications where the camera scan rates can be set up to operate at rates less than the trigger rate being received from a shaft encoder Rev 01 July 30 2001 17 PC CamLink User s Manual 405 00009 00 Using the Opto Coupled I O The PC CamLink has two opto coupled inputs and two opto coupled outputs The plus and minus input connections are the two sides of the LED light emitting diode The OC output connection is the open collector of an NPN transistor The VCC and GND power and ground of this device are also provided on the PC CamLink connector Figure 8 shows a single opto isolator Anode 4 VER Cathode Gnd Figure 8 Basic Opto Isolator The PC CamLink uses the HP HPCL 0531 dual channel isolator Do not exceed the absolute maximum ratings of the diode and transistor in these devices Opto Coupled In
26. board control the power up values for the outputs and select the input resistor for the Opto coupled inputs Leaving the outputs undefined during power up can adversely affect external equipment connected to the OPTO 22 parallel port or the the TTL Differential and Opto coupled outputs You should set these jumpers for the preferred power up conditions for any equipment connected to the PC CamLink to prevent damag ing or hazardous conditions in the attached equipment The following table defines the functions of all jumpers Figure 1 illustrates the jumper positions 1 2 and 2 3 A square pad identifies pin 1 The numbers 1 2 3 are not on the board Jumper Pins Controlled Position Function JP1 OPTO_IN 1 0 1 2 Opto Input 0 Input Resistor 475 ohms 5 Volt operation 2 3 Opto Input 0 Input Resistor 2 7 K ohms 24 Volt operation JP2 DIFF_OUT 1 0 1 2 Differential Outputs and CC4 Tri Stated disabled on and CC4 power up 2 3 Differential Outputs and CC4 Enabled on power up JP3 OPTO_IN 1 0 1 2 Opto Input 1 Input Resistor 475 ohms 5 Volt operation 2 3 Opto Input 1 Input Resistor 2 7 K ohms 24 Volt operation JP4 TTL_OUT 2 0 1 2 TTL Outputs high 1 on power up 2 3 TTL Outputs low 0 on power up JP5 OUT 7 0 1 2 Parallel Outputs high 1 on power up 2 3 Parallel Outputs low 0 on power up JP6 OUT 7 0 1 2 Parallel Outputs tri stated disabled on power up 2 3 Parallel Output enabled on power up JP7 TTL OUT 2
27. colors left for gray scale video which reduces the contrast of the video somewhat It also may be said that limiting Windows to its minimum 20 colors makes for an unattractive Windows display If 24 bit color data is being acquired then the VGA primary surface must be set at 24 bits This presents fewer color dot problems The color video data can be clipped by a look up table to leave room for the 20 Windows colors and more if desired with negligible degradation to the video quality 20 colors out of 224 There is a restric tion on the overlay as well The overlay is in the secondary surface of the VGA card and is not being managed by Windows Windows keeps track of all of the objects in the primary surface so that they all remain good Windows neighbors Pull down menus dialog boxes tool bars main windows video in a window bus mastered data etc Rev 01 July 30 2001 45 PC CamLink User s Manual 405 00009 00 are all managed so that the proper components are on top in the background in the foreground and displaying prop erly Windows does not keep track of the secondary surface where the overlay data resides a problem arises if any Windows graphics such as a dialog box intrudes on the same area of the screen as the overlay The overlay will be turned off by the VGA card if the graphics encroaches on its area even if just by a few pixels This can cause prob lems with the application s GUI Bus Master to the Secondary Surface
28. cond image finishes a second request for transfer is sent to the bus master controller The second image is trans ferred and the acquire operation switches back to the first frame This sets up a ping pong acquire buffer Programmable Window Generator A programmable window generator PWG defines how much of the incoming image data in each line gets acquired to the image buffer and how many lines of the image up to 64K pixels per line or 64K lines Data occurring outside the programmed window is not stored This capability does not affect the speed of the acquisition and is similar to the concept of a sub region or ROI region of interest The PWG can be programmed through the Camera Configu rator or through IFC Camera and Capture Module functions Image memory bandwidth is maximized when ac quired data is a multiple of 256 bytes 16 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual External Triggering External Trigger synchronizes image acquisition to external events The trigger inputs can be used to start acquire and stop image acquisition When acquiring an image in external trigger mode the acquisition will not start until PC CamLink receives a trigger signal When performing external trigger acquisition be sure the starting field bits of the Acquire Control register are set for next field Line Scan After the trigger occurs the next rising edge of LVAL begins the acquisition The vertical active register
29. ctor is a standardized 26 pin Mini D Ribbon MDR connector Standard 26 pin Camera Link cables are available from Coreco Imaging Inc or from 3M Contact 3M Interconnect Solutions Divi sion 6801 River Place Blvd Austin TX 78726 9000 800 255 5373 38 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Camera Connector The 26 pin MDR camera connector conforms to the Camera Link specification This connector supports camera data timing four camera control signals and serial I O All signals are LVDS This connector supports the Camera Link Base Operation up to 24 bit data Ports A B and C Table 1 Camera Link Connector Camera PC CamLink Signal name Description 1 1 SHIELD Inner cable shield 14 14 SHIELD Inner cable shield 2 25 X0 Data Channel 0 neg 15 12 X0 Data Channel 0 pos 3 24 X1 Data Channel 1 neg 16 11 X1 Data Channel 1 pos 4 23 X2 Data Channel 2 neg 17 10 X2 Data Channel 2 pos 5 22 XCLK Data Clock neg 18 9 XCLK Data Clock pos 6 21 X3 Data Channel 3 neg 19 8 X3 Data Channel 3 pos 7 20 SerTC Camera Serial Transmit pos Cam Tx 20 7 SerTC Camera Serial Transmit neg 8 19 SerTFG Frame Grabber Serial Transmit neg Cam Rx 21 6 SerTFG Frame Grabber Serial Transmit pos 9 18 CC1 Camera Control 1 neg CTLO 22 5 CC1 Camera Control 1 pos 10 17 CC2 Camera Control 2 pos CTL1 23 4 CC2 Camera Control 2 neg 11 16 CC3 Camera Control 3 neg CTL2 24 3 CC3 C
30. d n Figure 4 Camera Connection Rev 01 July 30 2001 gi PC CamLink User s Manual 405 00009 00 Configurator Utility The Camera Configurator utility makes it very easy to set up and configure each video input to a camera Addition al information about cameras occurs later in this manual At this time we are just interested in initializing and acquir ing an image A camera must be connected before power is turned on Connecting or disconnecting cameras with power on can damage the camera or PC CamLink 1 Double click on the Configurator icon in the IFC program group The utility will take a moment to detect and initialize the hardware When you start the Camera Configurator or select FilelNew the program detects all the Coreco Imaging Inc hard ware supported by IFC installed and creates a Hardware Data Structure that defines all the installed frame grabber boards 2 Now you should see the screen shown in Figure 5 the Configurator window with an Image Display window inside The Camera Configurator opens with three main viewing panes e Config View hardware configuration file and hardware parameters e Camera View camera definitions and image display does not open if no hardware is installed e Log View command log and error log Any changes you make to these panes change size close hide will be applied the next time the program opens W First click on a port in t
31. d bits of the Acquire Control register are set for next field Line Scan After the trigger occurs the next rising edge of LVAL begins the acquisition The Vertical Active VACT defines the number of lines acquired to create a frame Alternatively a stop trigger can be used to end acquisition at the end of the current line Rev 01 July 30 2001 15 PC CamLink User s Manual 405 00009 00 Area Scan After the trigger occurs the next rising edge of FVAL begins the acquisition The trigger input must be re armed to acquire subsequent frames Multiple Frame Acquire Mode PC CamLink has the ability to acquire and store up to eight images sequentially into image memory with the execu tion of one snap command Program the Frame Count FCNT or number of frames argument to the desired number of frames per snap command 1 to 8 For non interlaced acquisitions the multiple acquire mode count FCNT al ways refers to full frames For interlaced acquisitions the multiple acquire mode count FCNT always refers to fields and must be programmed to twice the number of full frames In Normal mode the frame count is set for to 8 images When a Snap command is executed the programmed number of images is acquired sequentially into a memory frame In Grab mode the set number of images is acquired and then the acquire address wraps back to the start of acquire address overwriting the previous images The image size must be taken into account when acquir
32. d formatting the video data Acquired Image PC Host Memory Dar Me la Transfer Image Transfer Image to Host Memory to VGA Memory W PCIBus i PCI Bus I Destructive Overlay Data i Convert to DIB Destructive Overlay data Figure 36 Destructive Mix in Host Memory Non Destructive Overlay The non destructive techniques use a feature of certain newer VGA chips called streams processing This feature allows a VGA chip to parse the memory on the VGA card into two parts called the primary surface and the secon dary surface These surfaces are individually addressable These two surfaces can be mixed together by the VGA chip for display The secondary surface can only be defined as a 16 bit surface There are several different 16 bit formats to choose from but 16 bit is the only choice We use two different 16 bit formats in the two non destructive overlay tech niques The first is RGB 5 5 5 1 there are five bits each of red green and blue information with an extra bit which serves as a kind of mask If that bit is one then that pixel will be mixed in for overlay If it is zero it will not be This format is inherently poor at displaying monochrome data since the effective bit depth of an image is 5 bits or 64 gray scales Itis however fine for displaying color as you have a palette of 215 colors The second format is YCrCb 4 2 2 In this format Y is the lumi
33. ded in the IFCxx Examples directory when you install the IFC software The direc tories for all applications are given here with brief descriptions The IFC portions of these files are commented in the source files Quick Config Directory ifexx examples Qconfig Quick Config is an example showing how the IFC parameter functions can be used to configure a custom camera It shows a list of currently available camera files If your camera is in the list you can select and display an image Any of the camera parameters can be changed This program is a simplified alternative to the Camera Configurator Grab Example Directory ifcxx examples CGrab This example illustrates a C wrapper around the IFC library This example initializes the board and software and acquires an image into a buffer in host PC memory This example does not include a display of the captured image Interrupt Example Distributed executable ifcxx bin seqsnap exe Directory ifexx examples PC CamLink intrex This example illustrates the use of Triggers and Interrupts for PC CamLink Both hardware and software triggers are accessible The example displays menus for trigger selection and interrupt monitoring counters This example does not include a display of the captured image Sequence Acquire Distributed executable ifcxx bin seqsnap exe Directory ifexx examples PC CamLink seqsnap This example illustrates the multiple frame acquire capability of the PC CamL
34. e Using ANSI C illustrated by the example VWFCxx Examples CGrab Visual C Programming with MFC Using Microsoft Visual C and the Microsoft Foundation Classes to design your application gives you a great amount of flexibility in addressing the Windows Operating system at a root level You can use the Applications Wizard to create your program in the standard doc View App structure but there are a few items that you need to be aware of in the program design Each is addressed here Multiple Instances When locating the initialization code for the PC CamLink board in your application keep in mind that multiple ap plications cannot access the hardware at the same time Because of this you must develop your application to pro vide one interface to the hardware You can also have multiple threads react to events but make hardware access mutually exclusive Rev 01 July 30 2001 33 PC CamLink User s Manual 405 00009 00 Multi Threading Keeping the above section in mind the same can also be said about the thread safety of your application when operat ing on concurrent processes Each of your threads should not change the hardware state of the PC CamLink board without signaling the other threads through the use of Semaphores or another similar method Keeping your hardware interface code in the Application module accomplishes this Multiple documents can exist when they have a common IFC application interface Quick Config is an example o
35. eat sinks Install the end bracket screw 3 If you have the I O ribbon cable attach it to the 50 pin header connector Replace the chassis cover but do not plug the computer in yet 4 Connect all other peripherals to your computer Do not connect the camera and cable yet The Diagnostic software must be run with no camera connected Power up and boot your system e Under Windows 95 or 98 the Plug and Play Configuration Manager detects new hardware after installing PC CamLink If you re prompted for a manufacturer s CD or diskette to install the IFC device driver place the CD ROM in the appropriate drive and follow the instructions for installing the driver The driver is located in the root directory on the CD Windows NT should boot normally 6 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Run the Diagnostic Utility After installing the PC CamLink for the first time it is a good idea to run the diagnostic utility to verify the installa tion is correct and the board is functioning properly The diagnostic tests must be run without a camera connected This program will auto detect the number of boards you have plugged into the system initializes them then per forms some functional and memory tests NOTE Before running this tool shut down any other Windows applications that are running to prevent timeouts from occurring causing the program to generate false failures NOTE Run the diagnostic test with no c
36. ed A dao 37 Appendix A Connectors and Cables Connectots onde ied a waist eles Male sine pESIE WEBER A se is 38 Connector Part Numb rs olei SES ee e ed TRE e EY 38 Cam ra Connector a exuta v id A Pid Pe eee EP AERE 39 VO Connector osse bb Act orbs a ee UR Sh dee vert exi hop bte uper eb 40 Parallel VO Connector ince eee ER Rte RC Rer doe RR RC RSS 41 Camera Cables vii a Soe we eal es el M UE EVE 42 VO Cables ost Rte e epe aet gb Eg dada 42 Appendix B Video Overlay Destructive Overlay ho E elena COE ROS MEREVEUPOUEE E NE ER CEU 43 Destructive Mix in VGA Memory sseeeee eee 43 Destructive Mix in Host Memory 0 cece eee me 44 Non Destructive Overlay o o oooooooooorrrr e 44 Bus Master to the Primary Surface peuss 0 0 0 cee ee 44 Limitations beste ERRORES I DERE ea uet Un 45 Bus Master to the Secondary Surface o ooocoocooccoccocco eee 46 vi Rev 01 July 30 2001 405 00009 00 List of Tables Number Title Table 1 Camera Link Connector o ooooooooooocooroooo Table 2 O Connector terri di Table 3 50 Pin Dual Row Header lees Fable 4 I O Cables 2 2 eR shod he ee Shee ech eR Pene TS Table 5 Power Cable Pin Out o ooooooooooooooroor Number Title Figure 1 Jumper Positions psss susep ure ino atisar inap eee Figure 2 PC CamLink Factory Default Configuration Figure 3 Install the PC CamLink in the Computer Figure 4
37. f the use of multiple documents If each document had initialized the hardware and managed the transfer into their own display there would be multi ple access to the same board creating arbitrary hardware states for all concurrent documents The following figure illustrates the differences in modeling your application Main Application Main application providing common PC CamLink interface for each document Correct Design Main Application Main application Images with providing NO Init and PC CamLink code at all Transfer routines Incorrect Design Figure 31 Programming Design 34 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Creating a Project File Using the IFC Application Wizard in Microsoft C we can create the entire framework necessary for a robust win dows application A project can very easily be created using standard project options with the following options specific to IFC e Extra Include Directory VFCxxNnclude e Extra Library Path VFCxxNib The following steps lead you through creating a project file The same steps apply to building your own Win32 ap plications Step 1 Start the Visual Studio pull down the File menu and select New Select the Projects tab Step 2 Select IFC AppWizard and fill in the project name Use the defaults or point to VFCxxNXExamples directory or to your application file directory The AppWizard steps you through eigh
38. he Config File Config View then click on a camera name in the List of Cameras Cam era View The display display context changes immediately a If Single Click Assignment is checked that camera gets assigned to the port highlighted in the Config View b If Single Click Assignment is not checked double click on the camera name right click on the camera name or drag and drop the camera name onto the highlighted port Refer to the IFC Camera Configurator User s Manual for additional information on using the Camera Configurator 8 Rev 01 July 30 2001 405 00009 00 A Camera Configurator PCVtest File View Tools Window Help PC CamLink User s Manual 15 x Dam Neu Local Machine E Bl PCvision B 59 Board 0 F Pot DEF_AS640x480P meti lt DE 540 480 nfig J 480x Camera Timing Parameters Par E Para y LEN Polarity IFC_FALLING_EDGE a FEN Polarity IFC_FALLING_EDGE Horizontal Sync Frequency K 15 734000 Horizontal Sync Pulse Width 4 700000 H Sync Polarity IFC_ACTIVE_LOW Vertical Sync Frequency Hz 60 000000 Vertical Sync Pulse Width lin 3 000000 V Sync Polarity IFC ACTIVE LOW Pixel Clock Frequency MHz 12 250000 Pixel Clock Polarity IFC RISING EDGE For Help press F1 live 2aseaear s width 640 Height 480 Depth 88its Pixel X ii ll E T BH ay p S es e e EH Pcvision mp Boara 0 y M Single Click Assign
39. igure 25 Odd Even Pixels Dual Tap with Line Segments One channel A carries the left half of the line or frame and the other channel B carries the right half of the line or frame Data is presented simultaneously on both channels Figure 26 shows where the data appears in a line from the original image PC CamLink can support this format for pixel depths from 8 bits up to 12 bits The IFC Software Library calls this Two Channel Separate Tap Left to Right or LNK_2CHAN_SEP_TAP_L2R 30 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Figure 26 Two Line Segments Dual Tap with Reversed Line Segments One channel A carries the left half of the line or image and the other channel B carries the right half of the line or image The direction is right to left or reversed from what we consider the normal left to right scan Data is present ed simultaneously on both channels Figure 27 shows where the data appears in a line from the original image PC CamLink can support this format for pixel depths from 8 bits up to 12 bits The IFC Software Library calls this Two Channel Separate Tap Right to Left or LNK_2CHAN_SEP_TAP_R2L Figure 27 Two Reverse Line Segments Dual Tap with Converging Line Segments One channel A carries the left half of the line or frame and the other channel B carries the right half of the line or frame Channel A scans left to right and cha
40. ing multiple images The image memory is 16MB and wraps around if the number of incoming pixels fills the buffer With frame count programmed to acquire infinite frames the grab continues to acquire images without resetting the address Acquire infinite frames is only used with the grab com mand In Triggered mode snap or grab each incoming external trigger will acquire one frame and advance the frame count In triggered snap mode each incoming trigger acquires a frame until the frame count is reached and the snap operation ends In triggered grab mode each incoming trigger acquires a frame until the frame count is reached the frame count resets and the acquire address resets to its original start point usually address zero and the triggered acquire continues until a freeze command is issued Acquire infinite frames can be used in triggered grab mode Using multiple frames with bus mastering allows simultaneous acquire and transfer without loss of video A typical application would define two image frames in memory and program a grab acquire At the end of the first image a request is sent to the bus master controller which processes the request and transfers the first image Simultaneously the second image is acquired into the next frame location in memory No data gets over written as long as the transfer of the first image is completed prior to the end of the second image acquire The operation repeats when the se
41. inish to restart your computer Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Environment Changes The following additions have been made to your system e Windows 98 driver location c windows system itipci vxd e Windows NT driver location c winnt system32 drivers mventp sys e The IFC configuration file path has been added to your computer environment IFCCNF C VFCROOT config Under Windows 98 this is in your Autoexec bat file Under Windows NT Right Click on My Computer then select Properties Environment e The IFC Program Folder now contains all the example programs IFC utilities documentation and release notes NOTE IFCROOT refers to the destination directory where IFC was installed for example cMFC52 e Help file versions of the PC CamLink Manuals are installed on your hard disk Help files for other manuals are available on the CD ROM in the DOC directory Entire chapters can be printed from the Content tab e Adobe Acrobat versions of the PC CamLink and other manuals are available on the CD ROM in the DOC PDFDOC directory for printing hard copy NOTE If you update or reinstall your C compiler the link to extension help is lost Uninstall and rein stall the IFC software to reestablish this link This is faster than copying and editing the IFCSW CNT file Rev 01 July 30 2001 3 PC CamLink User s Manual Configuration Jumpers 405 00009 00 The jumpers on the PC CamLink
42. ink board and software The example also presents options for camera selection triggering setup save and read images overlay drawing parallel port input and output LUT display hardware overlay window generator cropping and hardware zoom decimation The captured images are displayed on the PC monitor 36 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Video amp Overlay Distributed executable ifcxx bin overlay2 exe Directory ifexx examples overlay This example illustrates the video display capabilities of PC CamLink There are a number of different techniques discussed in Appendix B of this manual and each is covered in this example This example displays the captured image on the PC monitor You can zoom or stretch the image and draw rectangles ellipses and free hand in the over lay Large Format Acquire Distributed executable ifcxx bin largeacq exe Directory examples PC CamLink LargAcq This example illustrates using a ring buffer in host memory and a ping pong buffer in PC CamLink frame memory This method is used to acquire very large format images The snap and grab both use the same ring buffer in host memory Playing the buffer contents after a grab may show a sequence that jumps backwards because the ring buffer may not have filled and restarted completely when the grab terminated The snap sequence always starts and ends cleanly within the ring buffer Multi Threaded Processing Applicati
43. ired to create a frame image Line scan is a non interlaced acquire The starting field select bits must be programmed to next field A snap command performs a single frame acquire beginning at the next LVAL rising edge and acquires VACT number of lines A grab command performs continuous acquisition beginning on the next LVAL rising edge A freeze com mand will stop a grab when the VACT count is reached The End of Acquire trigger event stops a grab at the next falling edge of LVAL line enable not valid Area Scan A snap command performs a single frame acquire beginning at the next FVAL rising edge A grab com mand performs continuous acquisition beginning on the next FVAL rising edge A freeze command will stop a grab at the next falling edge of FVAL When acquiring non interlaced images a snap lasts for one field 1 frame When acquiring interlaced images a snap lasts for one field one half frame You must program the frame counter to snap twice the number frames you need Field select bits determine which field of the interlaced image will be ac quired first Setting these bits for next field allows either field even or odd to be acquired next External Trigger Acquisition External Trigger synchronizes image acquisition to external events When acquiring an image in external trigger mode the acquisition will not start until PC CamLink receives a trigger signal When performing external trigger acquisition be sure the starting fiel
44. is feature in 10 bit and 12 bit modes The input multiplexers are hard wired for the correct data format in these modes The input LUTs are two 16 bit in 16 bit out Look Up Tables Addressing and page size changes with the pro grammed pixel size LUT data paths are programmable in single tap modes but are hard wired for dual tap modes to format the three Camera Link data ports into two 10 bit or 12 bit fields 0x0 Port C Port B PortA 0x0 Port C PortB PortA LxBYTEH LUT High Byte LUTxPG 7 0 LUT Page LxPSIZE Pixel Size LxBYTEL LUT Low Byte 16 Figure 13 Input LUT 22 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Figure 13 illustrates one of the two Input LUTs The two LUTs are identical The low byte and high byte multiplexers select from four 8 bit inputs The pixel size LOPSIZE and L1PSIZE controls how much of the high byte is passed to the LUT and how much is masked off and substituted with page select bits LUTOPG and LUT1PG LUT Input Modes LUTOPG 7 0 Port A LOPSIZE LOBYTEL Le 16 Figure 14 Single Tap 8 bit Input For 8 bit single tap input the program the Pixel Size to 8 bits LOPSIZE select the 8 bit data usually Port A as the Low Byte LOBYTEL and use the eight Page Select bits to change the LUT Page LUTOPG 7 0 for up to 256 different LUT transforms Only the lower 8 bits of the output are stored in the image memory Rev 01 July 30
45. m this should automatically be selected and software IFC Win32 then click Start Install to begin installation Atthe Welcome screen click Next Please take a moment to read the Software License Agreement click Yes to continue Enter User Information then click Next to continue to the Destination screen Choose a location on the local system hard drive to install the IFC Note This destination is referred to as the JFCroot directory Click Next to continue Select Installation Type Typical is recommended and will install all files To install software on a Run time system loads only the DLLs Device Driver Diagnostics and Camera Configurator select Compact Click Next to continue Select the product documentation and examples you wish to install and click Next Enter a Program Folder name and click Next You have the option of installing the Acrobat Reader for viewing and printing documentation supplied in PDF format choose Yes or No For Windows 95 users DirectX Media Components are installed at this point Setup is done Click Finish to restart your computer Shut down your computer and install the PCVision hardware For Windows 98 users DirectX Media Components are installed at this point 10 When Setup has finished copying files you will need to reboot your computer to complete the installation Click F
46. ment EA CV M10 640x480 Xtal NI 4 CV M10 640x480 NI PLL EH DEF_CC512x512P SH DEF_CC512x512x T DEF_CC720x574P S DEF_CC720x574 BD DEF_CC768x574P SHDEF CC7583574X DEF CC920x574P UN DEF_CC920x574 EH DEF_AS512x480P E DEF_RAS512x480 ZH DEF_RS640x480P T DEF_AS540x480 E DEF_AS720x480P A DEF_AS720x480 RM DEF_RS752x480P A DEF_AS752x480 Figure 5 Configurator Startup Screen Rev 01 July 30 2001 PC CamLink User s Manual 405 00009 00 Save Files You can save three different file types using the Camera Configurator All files are saved as text txt You can save the frame grabber and camera port assignments to a Configuration File Configuration files do not contain the camera parameters or your changes to the parameter values You can save your parameter changes to a new or existing Camera Definition file in the camera database This updates only the one definition file All configuration files that point to that definition file in the camera data base will use the updated information You can save your parameter changes to a Portable Configuration File This updates only the one Configuration File and not the camera database Only the current Portable Configuration File receives the updated informa tion e A Camera Definition File defines one camera s parameter values without the frame grabber or port assign ment This file is used in the camera database All configuration files that call out this
47. n Free Run mode EXSYNC continuously outputs a pulse at a programmable interval retrig gering itself In External Trigger mode the EXSYNC pulse is asserted for the programmed period when an external trigger occurs In Vertical Blanking mode the EXSYNC pulse is asserted for the programmed period when the PC CamLink enters the vertical blank period between valid frames In software trigger mode the EXSYNC pulse is asserted whenever the host writes to the Software Trigger register Software can disable the EXSYNC counter and use software trigger mode to hold the EXSYNC output low or high generating integration or exposure times longer than supported by the EXSYNC counter EXSYNC can be a frame reset pulse output EXSYNC can be used as the exposure input to the camera when using the Xillix Kodak MEGAPLUS and Ham mamatsu cameras EXSYNC is used as the line transfer input to the Dalsa cameras All External Sync features can be enabled and configured in the Camera Configurator utility and saved in a camera file You can also use the IFC Parameter Access functions in the Class CICamera to change the EXSYNC parame ters All PC CamLink parameters are listed in an Appendix of the FC SDK Software Manual Programmable Integration The PRI output signal is used with Dalsa cameras to control integration time PRI is a programmable one shot pulse output with a period ranging from 210 ns to 18 75 s and a pulse width ranging from 140 ns to 572 us The
48. n the normal raster scan format for processing or display PC CamLink provides the necessary line and row resequencing to output virtually any image from a multi tap cam era in the normal raster scan format Resequencing is performed in real time without host processor intervention Typical multi tap image resequencing consists of reordering odd and even pixel sequences odd and even lines or opposite scans The figures in this section illustrate a variety of multi tap pixel data sequences from line scan and area scan cameras PC CamLink can resequence all cases shown Single Tap One channel presents the pixel data in sequential order The acquired sequence represents the original image with no need for sorting or reformatting Figure 24 shows where the data appears in the original image PC CamLink can support this format for pixel depths from 8 bits up to 24 bits The IFC Software Library calls this One Channel Left to Right or LNK_1CHAN_L2R Figure 24 Single Tap Odd Even Pixels One channel A carries only even pixels and the other channel B carries only odd pixels Data is presented simulta neously on both channels The pixels are interleaved in the original Figure 25 shows where the data appears in a line from the original image PC CamLink can support this format for pixel depths from 8 bits up to 12 bits The IFC Software Library calls this Two Channel Interleaved or LNK_2CHAN_INTERLEAVED Aaa A 7 F
49. nance monochrome component and the Cr and Cb are color components The term 4 2 2 is a representation of how much of each kind of data Y Cr and Cb respectively is present in this format In each 16 bit pixel there are 8 bits of luminance data and 8 bits of color data An unsophisticated compres sion is achieved by having adjacent pixels share the same chroma information Therefore the data effectively looks like YOCr0 Y1Cb0 Y2Cr2 Y3Cb2 All of the luminance data is retained while some of the color data is averaged or shared This loss of color data actually has little effect on the image as viewed and therefore is a good format for displaying data This is a very popular format in graphics and multimedia Bus Master to the Primary Surface The first non destructive technique is to use Direct Draw to provide video data to the primary surface and put the overlay in the secondary surface In this method the secondary surface must be a 16 bit RGB surface The Direct 44 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Draw of the video data to the primary surface is a familiar technique to achieve a live display Now however it is possible to have overlay data present in the secondary surface and have the two surfaces mixed together by the VGA hardware for display There is no speed penalty for performing this hardware mix The overlay data in the secondary surface is never overwritten therefore it does not have to
50. nnel B scans right to left Data is presented simultaneously on both chan nels Figure 28 shows where the data appears in a line from the original image PC CamLink can support this format for pixel depths from 8 bits up to 12 bits The IFC Software Library calls this Two Channel Separate Tap Converg ing or LNK_2CHAN_SEP_TAP_CONVERGE Figure 28 Two Converging Line Segments Rev 01 July 30 2001 31 PC CamLink User s Manual 405 00009 00 Dual Tap Interline One channel carries the even lines and the other channel carries the odd lines The lines are interlaced in the origi nal image Data is presented simultaneously on both channels Figure 29 shows where the data appear in the original image There are two options as shown Tap A can present the even lines 0 2 4 6 8 or the odd lines 1 3 5 7 9 The PC CamLink can support this format for pixel depths from 8 bits up to 12 bits The IFC Software Library calls this Two Tap Interline A Even and Two Tap Interline B Even or LNK_2TAP_INTERLINE_A_EVEN and LNK_2TAP_INTERLINE_B_EVEN A Even B Even Figure 29 Interline Three Tap with Line Segments A line is divided into three equal segments Data is presented simultaneously on all three channels Figure 30 shows where the data appears in a line from the original image The PC CamLink can support this format for 8 bit pixels The IFC Software Library calls this Three Channel Separate Tap Lef
51. on Distributed Executable ifcxx bin imgproc exe Directory ifexx examples ImProc This example illustrates processing using threads and interrupt services This example displays the captured image on the PC monitor You can open a second image window and select some basic processing invert LUT normal linear LUT mirror and highlight motion or difference between frames delta Visual Basic Example Directory ifcxx examples VB Vbexamp This example illustrates a VisualBasic wrapper on the IFC library Double click on the VBExamp vbp file to open the project Compile and run the example The captured image is displayed on the PC monitor with some controls for acquire and LUT processing Rev 01 July 30 2001 37 PC CamLink User s Manual 405 00009 00 Appendix A Connectors and Cables CONNECTORS PC CamLink provides three connectors for camera and I O Ports In addition the board has two connectors for the expansion module Resettable Parallel Port 5 V Fuse _y2 50 Try II a 1 49 26 pin__ Camera C E um Expansion onnector Slot Connectors Em 26 pin VO gt Connector El A Resettable 12 V Fuse Figure 32 PC CamLink Board and Connectors I O Camera Link 19 00000000 126 14 26 10 0000 000 00 18 Emera 000000000 y 1 13 Figure 33 Connector Pin Orientation Connector Part Numbers The PC CamLink Camera Conne
52. ors or omissions in this document Sherlock SMART Search PCVision and the Coreco Imaging logo are trademarks of Coreco Imaging Inc MVTools SherlockPro ITEX and PCVisionplus are Registered Trademarks of Coreco Imaging Inc All other trademarks are the property of their respective owners Coreco Imaging Inc 55 Middlesex Turnpike Bedford MA 01730 1421 1 781 275 2700 FAX 1 781 275 9590 Email info imaging com http www imaging com 405 00009 00 PC CamLink User s Manual EMC EMI Precautions This product has been tested and found to comply with the FCC limits for a class A device The intended use of this product is in a commercial industrial work environment Operation of this product within a domestic environment may cause radio interference in which case the user may be required to take adequate measures This product has been tested and found to comply with the European Community Directive for EMC 89 336 EEC In order to maintain compliance with the EMC Directive this product must be installed in an EEC EMC compliant chassis that has a CE marking Additionally all cables used to connect the computer and peripher als must be shielded grounded and securely fastened Rev 01 July 30 2001 111 PC CamLink User s Manual 405 00009 00 iv Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Table of Contents Part 1 Introduction Welcome to the PC CamLink User s Guide 0 cece eee ee 1 Introd
53. polarity of the PRI output is programmable The PRI counters can be disabled and can be reset using control register writes Rev 01 July 30 2001 21 PC CamLink User s Manual 405 00009 00 The PRI signal can be selected as output on any of the four camera control lines on the Camera Link connector The PRI signal can be selected as output on any of the general outputs on the separate I O connector three TTL two Opto coupled and two Differential outputs PRI operate in the same mode selected for the EXSYNC signal free run mode external trigger mode vertical blank ing mode or software trigger mode PRI and EXSYNC are used together to synchronize the Dalsa line scan cameras to a varying external trigger pulse while maintaining constant exposure time All Programmable Integration features can be enabled and configured in the Camera Configurator utility and saved in a camera file You can also use the IFC Parameter Access functions in the Class CICamera to change the PRI parameters All PC CamLink parameters are listed in an Appendix of the IFC SDK Software Manual Input LUTs By default the IFC library programs the input LUTs to normalize 10 bit 12 bit and 14 bit data to 16 bits For exam ple the most significant bit msb of 12 bit data is left shifted four places creating a 16 bit data value with zeros in the four least significant bits Isbs This feature can be defeated by programming the pixel size to 16 bits Do not defeat th
54. put Circuits J se cec al umper JP1 or aa Vcc or PWR eh 5 62 H ohm OPTO_INx JA o gt 475 ohm v7 Trigger or e Value OPTO INx MEER ae al Figure 9 Opto Coupled Input Circuit Figure 9 shows the internal circuitry in the Opto Coupled inputs When the diode is excited the transmitter is on and the internal Value is zero When the diode is off the transmitter is off and the internal Value is one Jumper JP1 selects the input resistor for the OPTO_INO input Jumper JP3 selects the input resistor for the OPTO_IN1 input Figure 10 shows a few practical examples for using the input The positive input is connected to your logic or signal and the negative input is connected to ground through a 330 ohm 1 8 Watt resistor The resistor limits current through the diode The internal 2 7K ohm or 475 ohm resistor limits the voltage across the diode When the external input goes high the diode turns on and the internal value becomes zero When the external input goes low the diode turns off and the internal Value becomes one The diode and resistors are the Load connected to a sensor output The component values depend upon the voltage and current of your circuits Do not exceed the Absolute Maxi mum Ratings of the input diode 18 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual e Diode Absolute Maximum Ratings If avg 25mA Maximum Average Forward Current If pk 50 mA Maximum Peak Forward Current Vr
55. r with Pentium processor or equivalent and at least 32MB e Windows 95 98 ME 2000 or Windows NT 4 0 e Anopen half length 32 bit PCI bus expansion slot Optional To support hardware overlays the VGA video card should have one of the following chipsets S3 Virge Intel 740 or ATI 3D RAGE RAGE PRO Rev 01 July 30 2001 1 PC CamLink User s Manual 405 00009 00 Software Installation IMPORTANT Please read BEFORE installing the IFC SDK Rh W oo Uninstall any previous versions of the IFC SDK To do this run the Windows Add Remove Program Utility located in the Control Panel folder on your system The Control Panel folder can be found by selecting Start Settings Control Panel from the Windows task bar Installing the IFC SDK under Windows NT requires Administrative Privileges Make sure that the Microsoft C C or Visual Basic compiler version 5 0 or later has already been installed before installing the IFC SDK so that IFC extension help will be installed and enabled properly Before running the Setup program make sure all other Windows applications have been closed To install the ITEX SDK software place the CD in the appropriate drive to start the installation automatically If Auto Start is not enabled manually start the install program by selecting Run from the Windows Start Menu and type CD drive gt SETUP EXE Click on Install Software Select the appropriate Operating Syste
56. s Destructive Mix in VGA Memory The first technique for implementing destructive overlay is to use Direct Draw to transfer video information to the VGA card The host then writes graphical data on the video data on the VGA card to achieve the overlay The graphi cal data has to be constantly rewritten by the host because new video data is being written over it usually at 25 or 30 fps This requires a certain amount of host involvement Another disadvantage is that the overlay flickers on the display The video is being written at 30 Hz the host is writing the overlay however often it has the time to and the VGA is running at its own speed probably 72 Hz This inherent lack of synchronization causes flicker Windows VGA Acquired Image Display Memory VGA Display Transfer image to VGA memory PCI Bus A Destructive Overlay data Figure 35 Destructive Mix in VGA Memory Rev 01 July 30 2001 43 PC CamLink User s Manual 405 00009 00 Destructive Mix in Host Memory The second destructive overlay technique is to use DIB Device Independent Bit maps to transfer video information to the VGA card A DIB transfer starts by performing a bus master transfer to host memory The host then writes graphical overlay data on the video data and transfers the entire frame to the VGA card This method removes flick er but requires much more host involvement in transferring an
57. ster scan format e Color plane separation during transfer possible On Board Digital I O e OPTO 22 compatible 8 bits in 8 bits out e 3 TTL outputs 2 Differential outputs and 2 Opto coupled outputs PCI Interface e Pixel replication on transfer to host by factors of 2 or 4 independently in horizontal and vertical axis performed during bus master transfer to host e Scatter gather hardware feature for highly efficient image transfers e Bus master of image data at 120MB s sustained e Target access random R W to onboard registers image memory and LUTs e Multiple interrupt sources Display Windows e Display Resolution as per installed video display card e Non destructive hardware enabled overlay support e DirectX compatible display card SVGA required for real time display Rev 01 July 30 2001 13 PC CamLink User s Manual 405 00009 00 Camera Link Connector SerTC SerTFG CC4 CC3 CC2 CC1 XCLK X0 X1 X2 X3 i i E Camera Control Interface Camera Data Interface js Multiplexers T a E a l1 Camera Data 24 CTLO CTL1 CTL2 CTL3 Timing Control EXSYNC PRI i Input 1 0 Connector 412VDC Sync a sS Window Pixel Generator LUTs TTL INO _ A 2 Trigger OPTO_INO Trigger LT DIVO
58. t 2to Right or LNK_3CHAN_SEP_TAP_L2R Figure 30 Three Line Segments 32 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual Part 3 Software Overview The latest information pertaining to the software release can be found in the software release notes included on the shipping media and installed in the root directory that you have chosen such as C IFC52 The CD ROM contains the Imaging Studio CD ROM contains the IFC SDK environment and ITEX SDK which includes all of the li braries header files and runtime DLLs necessary for software development In addition there is on line help elec tronic documentation and example programs The example programs illustrate the proper use of functions pro vided These examples are not intended to be complete applications with all possible error checking and bullet proofing usually associated with a robust application They are intended to illustrate the basic concepts of program ming with IFC The IFC libraries have been developed to provide the highest performance image acquisition possible with the least amount of processor and developmental overhead The functions take advantage of interrupts multi threading multi processors if available and PCI bus mastering The IFC programming language supports the following e C Using MFC the IFC App Wizard creates the basic framework e Using VisualBasic illustrated by the example IFCxx Examples VB VBExamp
59. t steps to setting up an application The first six steps are the same as using the MFC AppWizard The last two steps select video display and interrupt handling threads and events Use the defaults for setps 1 through 7 In step 8 select the first interrupt ICAP_INTR_VB Build and then run the application With a camera attached to the PC CamLink you can open up to four image win dows by selecting WIndow New Window New HEI Files Projects Workspaces Dther Documents 8 ATL COM Appwizard Project name 2 Cluster Resource Type Wizard Ea Custom Appwizard y Database Project Location A DevStudio Add in Wizard jc Program Files Microsoft Visua 3 IFC App wizard Hee ISAPI Extension Wizard hy Makefile Create new workspace MFC ActiveX Control wizard Add to current workspace MFC Appwizard dll I Dependency of ea MFC App Wizard exe J Ti Utility Project 8 win32 Application win32 Console Application e win32 Dynamic Link Library caballo e Win32 Static Library i Win32 m Rev 01 July 30 2001 35 PC CamLink User s Manual 405 00009 00 Part 4 Examples The example programs are intended to illustrate the proper use of the IFC functions These examples are for your reference only not meant to be complete applications with all possible error checking and bullet proofing usually associated with a robust application The following examples are provi
60. tage and current of your circuits Do not exceed the Absolute Maxi mum Ratings of the output transistor e Transistor Absolute Maximum Ratings Vcc 30V Maximum Supply Voltage Vo 20V Maximum Output Voltage lo avg 5mA Maximum Average Output Current lo pk SOmA Maximum Peak Output Current Po 35 mW Maximum Output Power Dissipation 20 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual connected as a Current Sinking Output Vcc or PWR V dc VDC Poo 2 4 I PLC input E IC Logic Input 4 A e Relay Actuator K Ft SS eo 0V dc oia es al OV de L common common Figure 12 Output from Opto Coupled Circuit Sync Output The external synchronization output EXSYNC can control camera timing and integration EXSYNC is a program mable one shot pulse output with a period ranging from 210 ns to 18 75 s and a pulse width ranging from 140 ns to 572 us The polarity of the EXSYNC output is programmable The EXSYNC counters can be disabled and can be reset using control register writes The EXSYNC signal can be selected as output on any of the four camera control lines on the Camera Link connector The EXSYNC signal can be selected as output on any of the general outputs on the separate I O connector three TTL two Opto coupled and two Differential outputs EXSYNC can operate in four different modes free run mode external trigger mode vertical blanking mode or soft ware trigger mode I
61. uction and Overview 0 iren os ea e 1 Installation and Setup iii cease RR Ret pe RR RE REGIMES HR eek ERES 1 Software Installation kso A Aedes UI es A Ba Pe E s 2 Environment Changes sree 0 cece ence eect eee 3 Configuration Jumpers avis wih eines VPN ee a a a Ree 4 Factory Default Configuration 2 0 eee cece eee 5 Hardware Installation 5 veles eerzr SE OES SSAA e pes 6 Run the Diagnostic Utility 2 0 0 0 ee III 7 Connect a Camera and Acquire an Image 0 00 eee cece eee 7 Configurator Utility cp hae wise AA ARA A 8 sayetbilesxiue O O ea tel ara teh 10 File Names oc a SPR Gis Cae RO E ee SN Soe ed 10 Part 2 Hardware ECM EE 12 Acquisition Mode vor ria EROR P REP e VERG EEG Le er ER Re E 15 Normal Acquisition ps ugs 95545 ber eR eR au ERR M ER ee E RES 15 External Trigger Acquisition ooooooooocooooco IIIA 15 Multiple Frame Acquire Mode 0 ee 16 Programmable Window Generator 0 0 0c eect eee eee ee 16 External Irigserig turis ed oe lack ee URE AAA ENA NC BU Rae acs PRESSE 17 PC Camlink MOSES cti bess ee ok haw sitet be 17 Trigger Input Divider 4 4 uc ld RE ORI ADR RE DOR RR RUNS 17 Using the Opto Coupled IO sucia Roe RE ERR SE ee 18 Opto Coupled Input Circuits llle 18 Opto Coupled Output Circuits llle III 20 Sync Output 435524 da o eV ES 21 Programmable Integration 0 cece ee ee hh m mee 21 Input LUIS iiie ERU SR RR ER CURE p RR a bb a
62. vailable Page Select bits LUTOPG to change the LUT Page The IFC library programs the LUTs to left shift 10 bit 12 bit and 14 bit data to 16 bit data with zeros in the least significant bits Rev 01 July 30 2001 25 PC CamLink User s Manual 405 00009 00 Port B Port B L1BYTEH L1BYTEL LOBYTEH LUT1PG LUTOPG L1PSIZE LOPSIZE Port B Port A LOBYTEL Figure 18 Two Tap 10 or 12 bit input For 10 bit or 12 bit two tap input program the correct Pixel Size LOPSIZE LUTO Low Byte LOBYTEL and Port B for the LUTO High Byte LOBYTEH and L1PSIZE select Port A for the select Port C for the LUT1 Low Byte L1BYTEL and Port B for the LUTI High Byte LIBYTEH The input MUXs have been hard wired to deliver the correct bits from Port B to each LUT to make up the 10 bit or 12 bit pixels Use the available Page Select bits LUTOPG and LUTIPG to change the LUT Page The IFC library programs the LUTS to left shift 10 bit and 12 bit to 16 bits data with zeros in the least significant bits 26 Rev 01 July 30 2001 405 00009 00 PC CamLink User s Manual LUT1PG 7 0 Port C L1PSIZE LOBYTEL fA_ Figure 19 24 bit RGB input For 24 bit RGB data program LUTO Pixel Size for 16 bits LOPSIZE and LUT1 Pixel Size for 8 bits L1PSIZE Select Port A as the Low Byte for LUTO LOBYTEL Port B as the High Byte for LUTO LOBYTEH and Port C as the Low Byte for LUT1 LIBYTEL LUTO has no

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PC-CamLink™ User`s Manual 405-00009-00