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VR4181™

1. 19 3 REGISTCE 19 3 1 SIURB 1 0 0 00 0010 LCR7 0 19 3 2 SIUTH 1 0 0 00 0010 LCR7 0 Write 193 3 SIUDLL 1 0x0600 0010 91 c inerte ee UD Ordena 19 3 4 SIUIE 1 0 0 00 0011 LCR7 0 200444040400 0 nennen nennen nnt e nnne nnne nens 19 3 5 SIUDEM 1 0x0C00 0011 LORI S1 unitate ttt peek cte erret ce nents 19 3 6 SIUIID 1 0 0 00 0012 Read enne enne a E 19 3 7 SIUEG 1 0x0G00 0012 Write lt i aie fei gt eed 1938 SIUEG 1 0x0C00 0013 RERO PRU RR RU 19 3 9 SIUMC 1 0x0GO00 0014 inde ties edet fede dee HE 19 310 SIBES 1 0x0C00 005 nume hile ava eee de aah dee 19311 SUMS MOOC OO 0016 od RE AREARE E ENER aS 19 3 12 51056 1 0X0G00 0017 itn e ee te ute e ecu elena 19 313 SIDRESET 1 0x0600 00 19 2 2 itt eet ei eer qa eto bee ete fedet pre 19 3 14 SIUACTMSK 1 0 0 00 0016 nennen nnne nennen nentes enne 19 3 15 SIUACTTMR 1 0 0 00 001 User s Manual U14272EJ3VOUM 21 CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 379 2071
2. 324 16 3 4 KIUWKS 0 0 00 0194 nennen nnns 325 16 3 5 KIDWKT OXOBOO 0 196 3 tree tt b Ee mE r bee center 326 163 6 KIUINT 0x0BOO 0 1998 ertt te RR Ur RR CEPR RE 327 CHAPTER 17 COMPACTFLASH CONTROLLER ECU 2 2 2 328 17 1 ue a eee eles 328 17 2 Register Set Summary Crab ac a tamea e Le Rate runc ener hanenin 328 17 3 ECU Control Registers Aaaa a da atean haaa Eana Gai Ein 331 17 327 INTSTATREG 0x0BO00 08EB 2 ttn i e 331 17 3 2 INTMSKREG 0 0 00 08 getto ERE RIO EAM 332 17 3 9 GFG REG 1 0x0B00 08F E 2 eet ge eee epit 333 174 ECU Reg qe Ts 334 17 4 1 ID REV REG Index 0x00 A CER de cedet as 334 17 42 IF STAT REG Indexs 0x01 oret 335 17 4 3 PWRRSETDRYV Index 0x02 442244440 336 17 4 4 ITGENCTREG Index 0x03 337 17 4 5 CDSTCHGREG Index 0 04 2 2 202 2 2 0 0 00 00000030 nne nnnnn nene nnnee tenen nnnnn nnns 338 17 4 6 CRDSTATREG Index OXx05y
3. 40 EntryHi register tienne hee 75 EntryLo 70 iioi teas cr dcr et 81 ErrorEPG register ie hee SETS 89 ETIMEHREQ erue tide 218 ETIMELREQ 5 rto rtt cer 217 ETIMEMREG eed 217 lack bi dee 328 exception code eerie 80 external ROM CONNGCHON c nm 119 nec EET 125 memory map euet ipte 118 external system bus 93 F FBENDADREG nuin RE 423 2 adiens tege 423 EBSTADREGI x tt etae 422 FBSTADREQG2 2 noinen nene 422 FHENDREQ hee 424 EHSTARTREG x tette ette tes 424 FIFO mode 368 373 387 392 flashimemory itc 123 124 127 ELM niis eben 404 410 411 frame buffer 406 TAME ClOCK is rtr retra ten 404 410 Fullspeed 45 190 FVENDREG Hexen e Bd 417 EVSTARTRBEQ s pte detinet 417 G general purpose l O esee 33 general purpose I O signals 58 general purpose I O 236 general purpose register 37 238 alU ci ete D eig tere guis 236 GIU regiSter ie e cene 244 G
4. nnne 298 14 6 2 A D poit scan TIMING me o pe te ode dg im a eR dee 298 14 7 Data Loss 2 299 CHAPTER 15 AUDIO INTERFACE UNIT AIU 4222222 2 22 2 301 15 1 General 301 15 2 Register ae edited 302 15 2 1 SDMADATREG 0 0 00 0160 02 1 1 000000 303 15 2 2 MDMADATREG 0 0 00 0162 2 0 0 1 60 606000000 00000 nennen nennen enne nnns 304 15 2 3 DAVREF SETUP 0 0 00 0164 22 40 2 111 006000000000000000 305 15 2 4 SODATREG 0x0B00 0166 2 1 24102044 6000000 000000000000 000000000000 nennt rennes 306 15 2 5 SCNTREG 0 0 00 0168 02 22222 113 eene enne nnne rennen rennen nennen nnns 307 15 2 6 SCNVC END 0 0 00 016 a per nennen nennen nnns 308 15 2 7 MIDATREG 0x0B00 0170 309 User s Manual U14272EJ3VOUM 19 15 2 8 MONTREG 0X0BO0 0172 tte tet 310 15 2 9 0 0 00 01778 e mea Hd e DERE REED 311 15 240 SEQREG 0x
5. 57 serial interface unit 1 360 serial interface unit 2 379 SHOLI fea ie nue eder 405 Shift ClOCk iae aes 405 shutdown control icii 193 OYA aii tote ttt Rie 360 SUT r 361 SIU 379 SIU2 registerSa o 380 SIUACTMSK 1 377 SIDAGIMSK32 dE 397 SIUACTTMR 1 iiiter itte esters 378 SIUAGCTTMR 2 toss 398 SIDOSEL 2 3 31 it et s 396 SIBI 71 5 iiit oom 362 SIUDLL 2 eee eet 381 SIUDEM eee aeree 364 SIDDLME2 iti eame ede 383 SIEG eene ect EY 368 SIUFG 2 ccc eet entes 387 4 aite 363 2 ua RE 382 SUID teens 366 SIUD 2 idee 385 SIWIRSELA 2 on it htm ieget 395 SIBEG e s Lt ui 371 SIEG is DRE 390 SIDES itcr e 373 SIULS 2 aca eh mee eau 392 NMG irr a S 372 SIUMC 0st itte etu mmu 391 eene 375 SIMS 22 394 SIDBRBTT 3 ennt een 362 SIDRB 2 edente netus 381 SIURESET 1 iiis etre 376 SIURESET 2 3 eI estes ences 396 niea 376 SIUSO 22 4 395 tette ees 362 eee
6. lt Internal ISA Bus 108 User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 6 1 1 MBA Host Bridge ROM and register address space Physical address Ox1FFF FFFF to 0x1800 0000 Memory range Device ROM 0 0 00 0014 to 0 0 00 0000 I O range Bus control registers 0 0 00 0080 y o Interrupt register 0x0A00 008C y o Interrupt register 0 0 00 0098 y o Interrupt register 0x0A00 009A y o Interrupt register 0 0 00 0200 y o Interrupt register 0 0 00 0206 y o Interrupt register In addition to the decoding of above addresses the Host Bridge generates MBA select signals if other MBA masters intend to access the above devices The Host Bridge responds to the above addresses only upon a CPU access For any other addresses the Host Bridge initiates an MBA cycle to access an appropriate resources 6 1 2 MBA modules address space 1 Memory controller OxOSFF FFFF to 0x0000 0000 Memory range DRAM 0x0A00 to 0 0 00 0300 I O range Control registers The MBA memory controller is selected when the above address ranges are accessed 2 DMA controller 0 0 00 0048 to 0x0A00 0020 I O range Control registers 1 0x0A00 O6FF to 0 0 00 0600 I O range Control registers 2 The MBA controller is selected when the above ranges are access
7. 56 touch panel interface 275 transmit iere mee a 160 370 389 transmit 156 U UMA i indem Reel us 34 399 V VDD sigrals en e a e a 59 vertical 402 405 view 4 44 0 1 402 nth eid 349 VOLTSENREG pee IR ete ee 348 VRTOTALEREQ 2 ted 416 VBVISIBBEG bonn EUER 416 ICI ETE 352 wake up 35 243 WatchHi register toits 85 WatchLo register 4 22 85 Wired register ii incepet tii Dee 73 42 X XContext 2 440400 00 86 XISAGTL e ets 140 444 User s Manual U14272EJ3VOUM This datasheet has been downloaded from www EEworld com cn Free Download Daily Updated Database 100 Free Datasheet Search Site 100 Free IC Replacement Search Site Convenient Electronic Dictionary Fast Search System www EEworld com cn Datasheets Cannot Be Modified Without Permission Copyright O Each Manufacturing Company
8. 381 306 SO utes D tee 105 SOPTINTREG knee 179 software shutdown 22 100 193 uel He leer aad 301 315 152 SPKRGLEENREG 5 Lenis 150 User s Manual U14272EJ3VOUM 443 APPENDIX B INDEX SPKRSRGHAREG Hf iiiter 147 SPKRSRGIREG2 m ues ROBES 147 SPKRSRG2REG 1 iuuat ee e teg 148 SPKRSRG2REQ2 2 cime e 148 Standby 45 190 state PIU sition MA tae 279 297 Status 76 STN i tete den E oir iced 34 399 Suspend 45 190 entering 205 206 OXIUING cio cit eile Re Le e oie ct 207 SYSGEK beta c tied uds 47 141 SYSINTTREG nine 174 SYSINT2REQ i eletti eis 180 SYSMEMELnREG n 0 4 345 SYSMEMSLnREG n 0 to 4 344 system bus interface 52 System control coprocessor 67 T TagFliregister o ees 88 TagLo register cid 88 E e DUROS 31 47 57 117 timing 411 ER 44 touch detection eene 298 touch pariel eiie tenerte 276 touch panel interface signals
9. 368 373 387 392 A activation 440 194 328 CompactFlash interrupt 196 DCD interrupt request 198 ElapsedTime interrupt request 200 GPIO activation interrupt 197 power switch interrupt request 195 A D Converterz A sett EE 275 301 A D port Scan ee ED RUPEE 298 address 92 109 addressing re mde teme Ande 40 addressing 2 78 245 indere eme es 340 PO 6 e o et etre oom eei t 301 operation 315 AIU registers cei Shanes eta Rede 302 149 AIUINTREQ oie IHRE dee tete eoe 183 alternate functions 106 236 238 audio interface 56 audio interface 301 142 auto scan 318 auto stop 8 142 B BadVAddr 2 74 battery monitor interface 55 BATTINH shutdown essssseeeeeneneee 193 b
10. ROMs 1 0 Defines ROM size to be used for all banks 00 Reserved 01 32 Mbit 10 64 Mbit 11 Reserved Reserved 0 is returned when read ROMWENO Enables flash memory write for all banks Write strobe can be generated when this bit is set to 1 0 Disabled 1 Enabled Reserved 0 is returned when read Rtype 1 0 ROM type for all banks 00 Ordinary ROM 01 Flash memory 10 Page ROM 11 Reserved RSTOUT RESET output control This bit does not affect GPIO21 RESET state when this pin is not defined as RESET output 0 RESET is active low level 1 RESET is inactive high level This register is used to set ROM type and capacity of ROM Bank 0 1 2 and 3 Caution When writing to flash memory be sure to set Rtype 1 0 bits to 01 in addition to a setting of ROMWENO bit to 1 Remark When a ROM type other than flash memory is selected Rtype 1 0 bits are set to other than 01 the operation of the 4181 is undefined if a write to the ROM space is performed Users Manual U14272EJ3VOUM 111 CHAPTER 6 BUS CONTROL 6 2 2 CMUCLKMSK 0x0A00 0004 Name Reserved Reserved R W At reset Bit 7 6 5 4 3 2 1 0 R W Reserved MSKCSU MSKAIU MSKPIU MSKADU MSKSIU MSKADU PCLK PCLK 18 18 Reserved At reset Reserved 0 is returned when read MSKCSUPCLK Supply Mask Clocked
11. 415 21 4 5 VRTOTALREG 0 0 00 0408 416 21 4 6 VRVISIBREG 0 0 00 0404 416 21 4 7 FVSTARTREG 0x0A00 0406 417 21 4 8 FVENDREG 0 0 00 040 417 21 4 9 0 0 00 0410 2 2 222 421 01 2 12 0 00000000 1 0000000 418 21 4 10 LCDINRQREG 0x0A00 0412 2 2 2 2 0 1 0 00 00000000 419 21 4 11 ECDGFGREGO 0x0A00 0414 e tie UE e 420 21 4 12 LCDCFGREG1 0 0 00 0416 sse enne ener 421 22 User s Manual U14272EJ3VOUM 21 4 13 EBSTADREG 1 0x0A00 04198 2 rtt tt tdt edie et edge 422 21 4 14 FBSTADREG2 0x0A00 041 nnn rennes 422 21 4 15 FBENDADREG 0 0 00 0420 423 21 4 16 FBENDADREG2 0 0 00 0422 423 21 4 17 FHSTARTREG 0 0 00 0424 424 21 4 18 FHENDREG 0 0 00 0426 0 40 0 424 21 4 19 PWRCONREG1 0x0A00 0430 0400 0 425 21 4 20 PWRCONREG2 0 0 00 0432 22 4004 0 10 1 000 nennen nnns 426 21 4 21 LCDIMSKREG 0x0A00 0434 2 2 0 4 1 1 00000000000
12. 339 17 4 7 ADWINENREG Index 0x06 22 42 0 0 00000000 340 17 4 8 REG 0 07 edi es 341 17 4 9 IOADSLBnREG Index 0x08 OXOC 4000004 0 00 342 17 4 10 IOADSHBnREG Index 0x09 0 342 17 4 11 IOSLBnREG Index 0 0 OXOE nennen 343 17 4 12 IOSHBnREG Index 0 0 OxOF 343 20 User s Manual U14272EJ3VOUM 17 4 13 SYSMEMSLnREG Index 0x10 0x18 0x20 0x28 0X30 17 4 14 MEMWIDn REG Index 0x11 0x19 0x21 0x29 Ox31 sss 17 4 15 SYSMEMELnREG Index 0x12 0x1A 0x22 Ox2A 0 32 17 4 16 MEMSELn REG Index 0x13 0x1B 0x23 Ox2B 0X33 17 4 17 MEMOFFLnREG Index 0x14 0 1 0x24 Ox2C 0 34 17 4 18 MEMOFFHnREG Index 0x15 Ox1D 0x25 Ox2D 0X35 17 4 19 DTGENCLREG Index 0x16 cccecccccessnececesecececeaeeeeeseaecesseneeeeseaeeesssaeeesseaeeeeseneeeeesenseesesaes 17 4 20 GLOGTRLEREG Index OxTE dea 17 4 24 VOLTSENREG Index Ox1F 4 1 0000 0000000000000000
13. 412 21 4 ECD Controller Registers E ERR DPI EOM DIEA 413 23212 Coprocessor O Hazards oet ande e erp aem bla n i end d er ls eye a 432 23 2 Calculation Example of Hazard and Number of Instructions Inserted 435 28 User s Manual U14272EJ3VOUM CHAPTER 1 INTRODUCTION This chapter describes the outline of the 4181 PD30181 which is a 64 32 bit microprocessor 1 1 Features The 4181 which is a high performance 64 32 bit microprocessor employing the RISC reduced instruction set computer architecture developed by MIPS is one of the VR Series microprocessor products manufactured by NEC Electronics The Vr4181 contains the 41107 CPU core of ultra low power consumption with cache memory high speed product sum operation unit and memory management unit It also has interface units for peripheral circuits such as LCD controller CompactFlash controller DMA controller keyboard interface serial interface IrDA interface touch panel interface real time clock A D converter and D A converter required for the battery driven portable information equipment The features of the Vn4181 are described below e Employs 0 25 m process 64 bit RISC Vn4110 CPU core with pipeline clock up to 66 MHz operation in 32 bit mode is available e Optimized 5 stage pipeline e On chip instruction and data caches with 4 KB each in size e
14. 108 6 1 1 MBA Host Bridge ROM and register address space 109 6 1 2 MBA modules address 109 6 2 Bus Control Registers eese nnns nnne n than e oi aeae nasa anas sns sas 110 6 21 BCUCNTREG1 0x0A00 0000 cei cde 111 6 2 2 CMUCLKMSK 0x0A00 0004 sireenin ana nnns 112 6 2 3 BCUSPEEDREG 0x0A00 0000 sssssssseseseeeeneenenennenee nnne nrennren nnne nnne nennen en nen nnne 113 6 2 4 BCURFCNTREG 0x0A00 0010 2 nennen nnne nnne neret nenne rennen nnns 115 6 2 5 REVIDREG 0x0A00 00 14 miiir perte rte teme Dil Do eee Diis exe nt e 116 6 2 6 CLKSPEEDREG 0x0A00 0018 117 6 3 ROM IETA Ce EE H 118 6 3 1 External ROM devices memory mapping sess 118 6 3 2 Connection to external ROM x 16 119 6 3 3 Example of ROM Connection accio tee c eene t docencia dpa cn 120 6 3 4 External ROM CyCleS uu oe eU B E ERE ERREUR 125 6 4 DRAM nterface iaaa erare ara EErEE aT IEEE EEA endete BERI 128 6 4 1 EDO DRAM configuration ecco coe a iE Rr er ce 128 6 4 2 Mixed memory mode EDO DRA
15. Function 15to 10 Reserved 0 is returned when read 9 MIDLEINTR Microphone idle interrupt request receive data loss Cleared to 0 when 1 is written 1 Occurred 0 Normal MSTINTR Microphone receive completion interrupt request Cleared to 0 when 1 is written 1 Occurred 0 Normal Reserved 0 is returned when read SIDLEINTR Speaker idle interrupt request mute Cleared to 0 when 1 is written 1 Occurred 0 Normal Reserved 0 is returned when read This register indicates occurrence of various interrupt request of the AIU When data is received from the A D converter the MIDLEINTR bit is set if valid data still exists in the MIDATREG register MIDATV bit 1 In this case the MIDATREG register is overwritten MSTINTR bit is set when data is received in the MDMADATREG register When data is passed to the D A converter the SIDLEINTR bit is set if there is no valid data in the SODATREG register SODATV bit 0 However this interrupt request is valid only after AIUSEN bit 1 in the SODATREG register after which SODATV bit 1 in the DVALIDREG register User s Manual U14272EJ3VOUM 313 CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 12 MCNVC END 0 0 00 017E MCNVC9 MCNVC8 RTCRST Other resets RTCRST Other resets 15100 15 0 Microphone sample rate control This register is used to select a conver
16. nnn enne 427 21 4 22 CPINDCTREG 0x0A00 047E essssssssssseseeeenee rennen nennen nennen nnne nnne nennen rennes 428 21 4 28 CPALDATREG 0 0 0 0480 40 4 0 0 rennen nennen nnns 429 CHAPTER 22 PLL PASSIVE COMPONENTS snnm n nnne nns nn sata nnnm 430 CHAPTER 23 COPROCESSOR 0 HAZARDS 11 nena nnn nennt nsn nn ass s snnm 431 APPENDIX RESTRICTIONS ON 4181 2 4 2 436 1 RSTSW During HALTimer Operation 436 2 RSTSW3 in Hibernate Mode nnana 437 439 User s Manual U14272EJ3VOUM 23 Fig No 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 12 3 13 3 14 3 15 3 16 3 17 3 18 3 19 3 20 3 21 3 22 3 23 3 24 3 25 3 26 3 27 3 28 4 1 24 LIST OF FIGURES 1 3 Title Page Internal Block Diagramm 1 deer HERE Pee aed oleae cued Sask deseo et 30 Vr4110 CPU Core I
17. eC 379 20 2 Clock Control DOJO tele Eod tentent faite nette 379 20 3 Register Seth e 380 20 3 1 SIURB 2 0 0 00 0000 LCR7 0 Read 2 0 381 20 3 2 SIUTH 2 0 0 00 0000 LCR7 0 Write 381 20 3 3 SIUDLL 2 0 0 00 0000 LCR7 1 22 2 0 0 01 000000000 a s 381 20 3 4 SIUIE 2 0 0 00 0001 LCR7 0 oe eee a araen aia raikasi 382 20 3 5 SIUDLM 2 0 0 00 0001 LCR7 1 22 1 00000000 383 20 3 6 SIUIID 2 0 0 00 0002 Read sssssssssseseseeneeeneeenneeen nennen nene nnne nnne enne 385 20 3 7 SIUFC 2 0x0C00 0002 Write 387 20 3 8 SIULC 2 0x0CO00 0003 ite entend ete Li inerte edet 390 20 39 510 2 OXOGO0 0004 eere 391 20 3 10 SSIBES 2 0x0G00 0005 OECD 392 20 3 11 SIUMS 2 0x0C00 0006 unti i ete edet Aa P aD Ta c De een 394 20 312 51 56 250 0 600 0007 7 ttt cte pec de 395 20 9 13 SIUIRSEL 2 0x0C00 0008 den v on tertiis 395 20 3 14 SIURESET 2 OxOGO0 0009 eene eei Se te ri XE ER RR ae 396 20
18. 5 1 5 2 5 4 5 5 5 7 5 8 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 8 1 9 1 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 10 10 11 10 12 LIST OF FIGURES 2 3 Title Page E de eo erdt e e o Ned HER ecd 97 HSTSW RBSSE inito ni te bem eiie DEEP be ER uic Cette eo bc cea ble rato 98 Deadman s Switch Reset eiu e pe E ee eb eoe A eL LEE Let 99 Software ShU tdoWl Rz tt ote eot Po t acceded Ga eed 100 HAL Tirmer sh tdOWTF 5 eu dene i DER BEEF 101 VR4181 Activation Sequence When Activation Is 102 VR4181 Activation Sequence When Activation Is 103 Gold Bleset item a euntibus nemi i dm E tee 104 105 4181 Internal Bus Struct re cene eter iin eie eu e i e ena 108 ROM Read Cycle and Access Parameters esssssssssseeeeeeeeeeneeenen nennen nennen nnne nnne ener 114 Ordinary ROM Read Cycle WROMA 3 0 0101 sse 125 PageROM Read Cycle WROMA 3 0 0011 WPROM 2 0 001 seen 126 Flash Memory Read Cycle Rtype 1 0 01 WROMA 3 0 0101 127 Flash Memory Write Cycle Rtype 1 0 01 WROMA 3 0 0100 127 Exter
19. User s Manual 41817 64 32 Bit Microprocessor Hardware uPD30181 Document No U14272EJ3VOUMOO 3rd edition Date Published November 2002 NS CP K NEC Electronics Corporation 2000 MIPS Technologies Inc 1998 Printed in Japan 2 User s Manual U14272EJ3VOUM NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc he
20. signal is at low level Hibernate mode or during CPU core activation to stop supplying voltage to the 2 5 V power supply systems is recommended to reduce leak current This means that this power supply can be 0 V while the MPOWER signal is inactive The following operation will not be affected by supplying voltage of 2 3 V or more to this power supply within the period from when the MPOWER signal becomes active to when PLL starts oscillation Caution When the CPU core enters the Hibernate mode by executing the HIBERNATE instruction if an activation factor occurs simultaneously the CPU core may be activated without asserting the POWERON signal after the MPOWER signal is once de asserted Moreover if RSTSW which is not an activation factor of the Hibernate mode is asserted at the same time a transition to the Hibernate mode by executing the HIBERNATE instruction occurs the CPU core may be activated without asserting the POWERON signal after the MPOWER signal is de asserted once 194 User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 5 1 Activation via Power Switch interrupt request When the POWER signal is asserted the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated After asserting the POWERON signal the PMU checks the BATTINH signal and then de asserts the POWERON signal If the BATTINH signal is at high level the PMU cancels peripheral unit res
21. Other resets Bit Name Function Reserved 0 is returned when read STABLE 5 0 Touch panel voltage stabilization wait time DataScan CMDScan state A D scan timeout time ADPScan state Touch detection start wait time Disable WaitPenTouch Interval state Wait time STABLE 5 0 x 30 us The voltage stabilization wait time for the power applied to the touch panel can be set via the STABLE 5 0 bits in 30 us units between 0 us and 1 890 us 286 User s Manual U14272EJ3VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 3 5 PIUCMDREG 0 0 00 012A Reserved Reserved Reserved STABLEON TPYEN1 TPYENO TPXEN1 TPXENO RTCRST Other resets Name TPYD1 TPYDO TPXD1 TPXDO ADCMD3 ADCMD2 ADCMD1 ADCMDO R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 1 1 1 1 Other resets 0 0 0 0 1 1 1 1 15 to 13 Reserved Function 0 is returned when read 12 STABLEON Touch panel voltage stabilization wait time STABLE 5 0 of PIUSTBLREG enable during command scan 1 Wait for panel voltage stabilization time 0 Ignore panel voltage stabilization time wait time 0 1 0 TPY port input output switching during command scan 11 TPY1 output TPYO output 10 TPY1 output TPYO input 01 TPY1 input TPYO output 00 TPY1 input TPYO input TPXEN 1 0 TPX port input output switching during command scan 11 TPX1 output TPXO output 10
22. 1 e p et Eee CE GRE E MEER 44 1 4 6 Memory management 44 R TAROT o E Em 44 1 4 8 Instructiori pI pele r n eee eee a a a aa E Ea a aE 44 1 4 9 Power modes infe aS a baara aaa deste tii d due indie eR D 45 1 410 Gode compatibility 2 5 2 cte recep rac cte eet ce eine ret p e n 46 1 5 Clock Interface 47 CHAPTER 2 PIN FUNCTIONS ree 50 2 1 Pink COMPQUIATIONN 50 2 2 Pin Function Description 52 2 2 1 System bus interface signals 52 22 2 LOD interface SIQNalS x ohio eei e p aai be Det diet profs 54 2 2 3 Initialization interface signals memes 55 2 2 4 Battery monitor interface signals 55 2 2 5 Glock interface Signals mie UENIT e 55 2 2 6 Touch panel interface and audio interface signals 56 User s Manual U14272EJ3VOUM 13 2 2 7 LEDinterface sigalg iet mt cete ed aed tm eg rer neces renee 56 2 2 8 CompactFlash interface and keyboard interface signals 56 2 2 9 Serial interface channel 1 signals sssssssseseeneenenenneneennen nennen nennen 57 2 21
23. 19200 52 08 38400 26 04 57600 17 36 115200 8 68 128000 7 81 144000 6 94 192000 5 21 230400 4 34 288000 3 47 384000 2 60 576000 1 74 1152000 0 868 384 User s Manual U14272EJ3VOUM CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 20 3 6 SIUIID 2 0 0 00 0002 Read Name Reserved Reserved R W RTCRST Other resets IIR 7 6 Function Becomes 11 when FCRO bit 1 Reserved 0 is returned when read 3 Pending of the character timeout interrupt request FIFO mode 1 No pending 0 Pending 2 1 IIR 2 1 Indicates the priority level of interrupts See the following table 0 IRO Pending interrupt requests 1 No pending 0 Pending This register indicates priority levels for interrupts and existence of pending interrupt requests From highest to lowest priority the involved interrupts are the receive line status the receive data ready the character timeout the transmit holding register empty and the modem status The content of the IIR3 bit is valid only in the FIFO mode and it is always 0 in the 16450 mode The IIR2 bit becomes 1 when the IIR3 bit is set to 1 User s Manual U14272EJ3VOUM 385 CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 SIUIID 2 register Bit Bit 1 Priority level Highest 1st Table 20 3 Interrupt Function Interrupt type Receive line
24. 20 3 12 SIUSC 2 0 0 00 0007 Name SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCRO R W R W R W R W R W R W R W R W R W RTCRST Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Other resets Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Name Function 7100 SCR 7 0 General purpose data This register is a readable writable 8 bit register and can be used freely by users It does not affect control of the SIU2 20 3 13 SIUIRSEL 2 0 0 00 0008 Reserved Reserved Reserved Reserved Reserved Reserved Reserved SIRSEL RTCRST Other resets Reserved 0 is returned when read Reserved Write 0 when write 0 is returned when read Reserved 0 is returned when read Reserved Write 0 when write O is returned when read Reserved 0 is returned when read SIRSEL Selects communication format 1 IrDA 0 RS 232 C This register is used to set the SIU2 s communication format IrDA or RS 232 C To use the IrDA format an external IrDA module must be connected User s Manual U14272EJ3VOUM 395 CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 20 3 14 SIURESET 2 0 0 00 0009 Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets Bit Name Function Reserved 0 is returned when read SIURESET SIU2 reset 1
25. OOt LL 07 9 2 beoeeesangotosa 906 5596 002 252 Oszziozz28 Szaszxo SEes2r orang 1125 5 lt 8551500555 6525 2829 9000606420606055 B gt 2995 2 gt gt gt gt m tO LO t t t c AN IRDOUT TxD2 26 0O IRDIN RxD2 22 0 CTS 21 jo DCD 23 lt O RTS 25 lt lt gt RxD 24 0O TxD A GND T PX PX PY PY VDD ADIN ADIN ADIN AUDIOIN O gt VDD_AD AUDIOOUT IORDY GPIO18 IOCS168 GPIO19 RESET GPIO21 ROMCS3 ROMCS2 GPIO24 ROMCS1 GPIO23 O ROMCSOX GPIO22 SYSEN O SYSDIR O MEMWR MEMRD iolou coccouo GND VDD LDQMI LOGIC O LOGIC O LCAS O UDQM UCAS SDRAS O CAS RASO SDCSO GND IO O VDD IO RAS1 SDCS1 CLKEN DATAO O 1 DATA1 gt DATA2 O 1 DATA3 O 1 DATA4 O DATA8 O 44 VDD IO O DATA9 43 DATA10 O DATA5 41 DATA6 DATA15 O 51
26. 0 0 00 002E SPKRSRC2REG2 Speaker source 2 address register 2 0 0 00 0040 DMARSTREG DMA reset register 0 0 00 0046 AIUDMAMSKREG Audio DMA mask register 0 0 00 0600 to 0 0 00 0654 Reserved Write 0 when write 0 is returned after a read 0 0 00 0658 MICRCLENREG Microphone record length register 0x0A00 065A SPKRCLENREG Speaker record length register 0x0A00 065C Reserved Write 0 when write 0 is returned after a read 0 0 00 065E MICDMACFGREG Microphone DMA configuration register 0 0 00 0660 SPKDMACFGREG Speaker DMA configuration register 0 0 00 0662 DMAITRQREG DMA interrupt request register 0 0 00 0664 DMACTLREG DMA control register 0 0 00 0666 144 DMAITMKREG DMA interrupt mask register User s Manual U14272EJ3VOUM CHAPTER 7 DMA CONTROL UNIT DCU 7 2 1 Microphone destination 1 address registers 1 MICDEST1REG1 0x0A00 0020 Name MD1A15 MD1A14 MD1A13 MD1A12 MD1A11 MD1A10 MD1A9 MD1A8 R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 Name R W At reset MD1A 15 0 Lower 16 bits A 15 0 of DMA destination 1 address for Microphone 2 MICDEST1REG2 0x0A00 0022 Name MD1A31 MD1A30 MD1A29 MD1A28 MD1A27 MD1A26 MD1A25 MD1A24 R W At reset Name MD1A23 MD1A22 MD1A21 MD1A20
27. 230 DMA control unit 142 DMA priority tte eee 143 DMACTLREG nd ate Ld 154 DMAITMMKREQG tate 155 153 enrich te teenie een 149 doubleword either 42 DRAM data 192 DRAM 128 201 lt HO Ren 95 DRAMMHIBGTL 215 sinunt ceto ah nee teeta 230 register setting 235 DSU registers iin ee ie etaed 230 DSUGERREQ o petto cna 233 DSUGCNTREQG 5 inei eee iis 231 DSUSETREQ eee 232 DSUTIMREG zi iun tto niei ER 234 DTI GENGLEREG oe eee cde 347 dum 410 311 EGMPEREQ pedet 220 ECMPLREG wk ied ede 219 ECMBPMBEG eub eB 219 n ete EE aei i 328 ECU control registers 331 EGCU registers 334 EDO DRAM 128 129 192 201 203 205 207 437 EDOMGYTREQG aciei de 131 ElapsedTime 2 20 216
28. Reserved 0 is returned when read PENCHGINTR Touch panel contact status change interrupt request 0 Not occurred 1 Occurred This register indicates when various PIU related interrupt requests level 2 occur 182 User s Manual U14272EJ3VOUM CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 8 AIUINTREG 0 0 00 0084 Name Reserved Reserved Reserved Reserved Reserved Reserved INTMIDLE INTMST R W RTCRST Other resets RTCRST Other resets Function 15 10 Reserved 0 is returned when read 9 INTMIDLE Audio input microphone idle interrupt request received data is lost This interrupt request occurs if a valid data exists in the MIDATREG register when data is received from the A D converter 0 Not occurred 1 Occurred INTMST Audio input microphone receive completion interrupt request This interrupt request occurs when a 10 bit converted data from the A D converter is received 0 Not occurred 1 Occurred Reserved 0 is returned when read INTSIDLE Audio output speaker idle interrupt request mute This interrupt request occurs if there is no valid data in the SODATREG register when data is transferred to the D A converter 0 Not occurred 1 Occurred Reserved 0 is returned when read This register indicates when various AlU related interrupt requests occur User s Manual U14272EJ3VOUM 183 C
29. Reserved 0 is returned when read Pre scal 1 0 gclk clock for LCD controller pre scalar mode to the MBA clock 00 Divide by 1 01 Divide by 2 10 Divide by 4 11 RFU Color depth selection 00 1 bit black and white for monochrome panel 01 2 bits 4 gray scale for monochrome panel 10 4 bits 16 gray scale for monochrome or 16 colors for color panel 1 8 bits 256 colors for color panel Panelcolor Color monochrome selection 0 Color 1 Monochrome PanDbus Panel data width 0 4 bits 1 8 bits for dual scan panel or for 8 bit high scan Remark In the 4 bpp mode 16 gray scale for monochrome panels the Blue area of the color palette is used for displaying The palette is not used in the other modes 1 bpp and 2 bpp for monochrome panels 420 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 21 4 12 LCDCFGREG1 0x0A00 0416 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved HpckH5 HpckH4 HpckH3 HpckH2 HpckH1 HpckHO Bit Name Function Reserved 0 is returned when read HpckL 5 0 Number of gclk cycles for hpck low level width Reserved 0 is returned when read HpckH 5 0 Number of gclk cycles for hpck high level width Users Manual U14272EJ3VOUM 421 CHAPTER 21 LCD CONTROLLER 21 4 13 FBSTADREG1 0x0A00 0418 FBSA10 FBSA15 FBSA14 FBSA13 FBSA12 15 to 0 FBSA
30. 0 0 00 02A6 PIUPBOSREG PIU page 0 buffer 3 register 0 0 00 02A8 PIUPB10REG PIU page 1 buffer 0 register 0 0 00 02AA PIUPB11REG PIU page 1 buffer 1 register 0x0B00 02AC PIUPB12REG PIU page 1 buffer 2 register 0 0 00 02AE 0 0 00 02 0 PIUPB13REG PIUABOREG PIU page 1 buffer 3 register PIU A D scan buffer 0 register 0 0 00 02B2 PIUAB1REG PIU A D scan buffer 1 register 0 0 00 02 4 PIUAB2REG PIU A D scan buffer 2 register 0 0 00 02B6 PIUAB3REG PIU A D scan buffer 3 register 0x0B00 02BC PIUPBO4REG PIU page 0 buffer 4 register 0 0 00 02 PIUPB14REG PIU page 1 buffer 4 register State of interrupt requests caused by the PIU is indicated and can be set in the following registers which are included in the ICU refer to CHAPTER 9 INTERRUPT CONTROL UNIT ICU for details Table 14 2 PIU Interrupt Registers 0 0 00 0082 PIUINTREG PIU interrupt indication register 0 0 00 008 MPIUINTREG PIU interrupt mask register User s Manual U14272EJ3VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 3 1 PIUCNTREG 0 0 00 0122 Reserved Reserved PENSTC PADSTATE2 PADSTATE1 PADSTATEO PADATSTOP PADATSTART RTCRST Other resets Name PADSCAN PADSCAN PADSCAN PIUMODE1 PIUMODEO PIUSEQEN PIUPWR PADRST STOP START TYPE R W R W R W R W R W R W R W
31. 126 User s Manual U14272EJ3V0UM CHAPTER 6 BUS CONTROL 3 Flash memory read cycle Figure 6 5 Flash Memory Read Cycle Rtype 1 0 01 WROMA 3 0 0101 TClock internal ADD 21 0 output ROMCS 3 0 output MEMRD output DATA 15 0 read WROMA 3 0 Valid Remark in the figure indicates the sampling timing 4 Flash memory write cycle Figure 6 6 Flash Memory Write Cycle Rtype 1 0 01 WROMA 3 0 0100 TClock internal ADD 21 0 output ROMCS 3 0 output MEMWR output DATA 15 0 write JN NU NA NI NE XI AG A e WROMA 3 0 User s Manual U14272EJ3VOUM 127 CHAPTER 6 BUS CONTROL 6 4 DRAM Interface The Vn4181 supports 16 Mbit or 64 Mbit DRAM EDO DRAM or SDRAM The DRAM size type and access speed is set via the memory controller s registers 6 4 4 EDO DRAM configuration Figure 6 7 External EDO DRAM Configuration ADD 12 0 UCAS LCAS MEMWR RASO DATA 15 0 Vn4181 Figure 6 7 illustrates an example when connecting devices of 4 Mbits x 16 Addresses when connecting devices of 16 Mbits or 64 Mbits are mapped as follows DRAM bank Physical address 16 Mbits Physical address 64 Mbits 0x001F FFFF to 0x0000 0000 0x007F FFFF to 0x0000 0000 0 00 FFFF to 0x0020 0000 OxOOFF FFFF to 0x0080 0000 Remark 6
32. RTC tema j alam intr Internal POWERON Output MPOWER Output BATTINH BATTINT Input Figure 10 12 Activation via ElapsedTime Interrupt Request BATTINH L RTC alam intr Internal POWERON Output MPOWER Output L BATTINH BATTINT Input L 200 User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 6 DRAM Interface Control The PMU provides a register to control the DRAM interface during Hibernate mode or Suspend mode The DRAMHIBCTL register permits software to directly control the state of the DRAM interface pins prior to executing a HIBERNATE or SUSPEND instruction The DRAMHIBCTL register also provides status indication of the memory controller The software flow when entering and exiting Hibernate mode or Suspend mode is shown below 10 6 1 Entering Hibernate mode EDO DRAM 1 2 3 4 5 6 lt 7 gt lt 8 gt lt 9 gt contents of all 2 5 V registers i e DRAM type and configuration ROM type and configuration etc that must be preserved during Hibernate mode into the general purpose registers MISCREG 0 15 in the GIU or into external memory Remark 3 3 V peripheral units PMU GIU LED and RTC 2 5 V peripheral units all peripherals except PMU GIU LED
33. Reserved 90 6 MHz Reserved 84 1 MHz Reserved 78 5 MHz Reserved 69 3 MHz 65 4 MHz 62 0 MHz 49 1 MHz TClock is generated from PClock and its frequency is always 1 2 of the PClock frequency after RTC reset User s Manual U14272EJ3VOUM 57 CHAPTER 2 PIN FUNCTIONS 2 2 10 IrDA interface signals Signal name IRDIN RxD2 Description of function IrDA receive data input or serial channel 2 receive data input Connect this pin to GND digital via resistor when an IrDA receive component is connected IRDOUT TxD2 2 2 11 General purpose signals Signal name GPIO 31 25 IrDA transmit data output or serial channel 2 transmit data output Description of function See 2 2 9 Serial interface channel 1 signals in this section GPIO 24 16 See 2 2 1 System bus interface signals in this section GP1015 FPD7 CD2 General purpose I O LCD screen data output or CompactFlash card detect 2 input GP1014 FPD6 CD1 General purpose I O LCD screen data output or CompactFlash card detect 1 input GPIO13 FPD5 General purpose or LCD screen data output GPIO12 FPD4 General purpose I O or LCD screen data output GPIO11 PCS13 General purpose or programmable chip select 1 GPIO10 FRM SYSCLK General purpose serial frame input for clocked serial interface or external bus System clock output GPIO9 CTS2 Gen
34. User s Manual U14272EJ3VOUM 85 CHAPTER 3 REGISTERS 3 2 18 XContext register 20 The read write XContext register contains a pointer to an entry in the page table entry PTE array an operating System data structure that stores virtual to physical address translations If a TLB miss occurs the operating system loads the untranslated data from the PTE into the TLB to handle the software error The XContext register is used by the XTLB Refill exception handler to load TLB entries in 64 bit addressing mode The XContext register duplicates some of the information provided in the BadVAddr register and puts it in a form useful for the XTLB exception handler This register is included solely for operating system use The operating system sets the PTEBase field in the register as needed Figure 3 22 XContext Register 63 35 34 33 32 4 3 0 ricer meme PTEBase Base address of the PTE entry table R Space type 00 User 01 Supervisor 11 Kernel The setting of this field matches virtual address bits 63 and 62 BadVPN2 The value VPN2 obtained by halving the virtual page number of the most recent virtual address for which translation failed 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read The 29 bit Bad VPN field has bits 39 to 11 of the virtual address that caused the TLB miss bit 10 is excluded because a single TLB entry maps to an even odd p
35. 0 Value of the IO1DSZ bit 1 CF IOIS16 signal from the card IO1DSZ window 1 access data size 0 8 bits 1 16 bits This bit has no function when the 1 CS16MD bit is set to 1 window 0 wait addition in 16 bit accesses 0 Without additional wait state 1 Adds 1 wait state WO IOWS window 0 wait addition in 8 bit accesses 0 No additional wait state 1 Adds 1 wait state 00 CS16MD window 0 IOCS16 source 0 Value of the IOODSZ bit 1 CF IOIS16 signal from the card 100082 window 0 access data size 0 8 bits 1 16 bits This bit has no function when the 00 CS16MD bit is set to 1 Users Manual U14272EJ3VOUM 341 CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 9 IOADSLBnREG Index 0x08 0x0C Remark 0 1 IOADSLBOREG 0x08 for Window 0 IOADSLB1REG 0x0C for Window 1 STARTA7 Name STARTA6 STARTA5 STARTA4 STARTAS STARTA2 STARTA1 STARTAO R W R W R W R W R W R W R W R W R W en ee EE ae pose poss ee Bit Name Function STARTA 7 0 window start address bits 7 to 0 Low order address bits used to determine the start address of an I O address window Minimum 1 byte can be specified for the I O address window 17 4 10 IOADSHBnREG Index 0x09 OxOD Remark 0 1 IOADSHBOREG 0x09 for Window 0 IOADSHB1REG 0 00 f
36. 19 2 Clock Control Logic The power of the 16550 core can be managed by monitoring activity on the modem status pins and writes to the transmit buffer The clock control logic for the 16550 core monitors activity on the four serial interface input signals RxD1 RTS1 DCD1 and DTR1 It also monitors writes to the 16550 transmit buffer Each source has an associated mask bit which prevents a source from causing reset of the Activity Timer Activity on the RxD1 RTS1 DCD1 and DTR1 inputs is defined as any change of state high to low or low to high When no unmasked activity has been detected on any of the inputs and no writes have occurred to the transmit buffer within the programmed time out period specified in the Activity Timer block the UART1 clock is stopped The UART1 clock will remain stopped until any activity is detected on the monitored sources 360 User s Manual U14272E3V0UM CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 Register Set The SIU1 registers are listed below Physical address 0x0C00 0010 Table 19 1 SIU1 Registers Register symbol SIURB 1 Function Receive buffer register read SIUTH 1 SIUDLL 1 Transmit holding register write Divisor latch least significant byte register 0x0C00 001 1 SIUIE 1 Interrupt enable register SIUDLM 1 Divisor latch most significant byte register 0x0C00 0012 SIUIID 1 Interrupt identification register read SI
37. An interrupt is enabled by setting the corresponding bit to 1 Overall use of interrupt functions can be halted by setting bits 0 to 3 of this register to 0 When interrupts are prohibited pending is not displayed in the IIRO bit in the SIUIID_1 register even when interrupt conditions have been met Other functions in the SIU1 are not affected even though interrupts are prohibited and the settings in the SIULS 1 register and SIUMS 1 register are valid To access this register set the LCR7 bit bit 7 of the SIULC_1 register to 0 User s Manual U14272EJ3VOUM 363 CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 5 SIUDLM 1 0 0 00 0011 LCR7 1 Name DLM7 DLM6 DLM5 DLM4 DLM3 DLM2 DLM1 DLMO R W R W R W R W R W R W R W R W R W RTCRST Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Other resets Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Function Baud rate divisor high order byte This register is used to set the divisor division rate for the baud rate generator The data in this register and the data in the SIUDLL_1 register as lower 8 bits are together handled as 16 bit data To access this register set the LCR7 bit bit 7 of the SIULC_1 register to 1 The relationship between baud rates and the settings of the SIUDLL 1 and SIUDLM 1 registers are as follows 364 User s Manual U14272EJ3VOUM CHAPTER 19 SERI
38. CHAPTER 12 DEADMAN S SWITCH UNIT 050 This chapter describes operations and register settings of the DSU Deadman s Switch Unit 12 1 General The DSU detects runaway endless loop state of the Vn4181 and resets the Vn4181 Use of the DSU allows terminating runaway states that may occur due to software in earlier phase to minimize data loss 12 2 Register Set The DSU registers are listed below Table 12 1 DSU Registers Physical address Register symbol Function 0 0 00 00 0 DSUCNTREG DSU control register 0 0 00 00 2 DSUSETREG DSU cycle setting register 0 0 00 00 4 DSUCLRREG DSU clear register 0 0 00 00 6 DSUTIMREG DSU elapsed time register Each register is described in detail below 230 User s Manual U14272EJ3VOUM CHAPTER 12 DEADMAN S SWITCH UNIT DSU 12 2 1 DSUCNTREG 0 0 00 00 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Function Reserved 0 is returned when read DSWEN Deadman s Switch function enable 1 Enabled 0 Disabled This register is used to enable use of the Deadman s Switch function User s Manual U14272EJ3VOUM 231 CHAPTER 12 DEADMAN S SWITCH UNIT DSU 12 2 2 DSUSETREG 0 0 00 00 2 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTC
39. External ISA CompactFlash or flash memory mode write cycle Don t care External Buffer Disable DRAM read write cycle or Hibernate mode User s Manual U14272EJ3VOUM 53 CHAPTER 2 PIN FUNCTIONS 2 2 2 LCD interface signals Signal name SHCLK LCDCS Output Description of function LCD shift clock output or chip select for external LCD controller LOCLK MEMCS16 y o LCD load clock output or bus sizing request input for system bus memory access When using as MEMCS16 the external agent must activate this signal at the System bus memory access in 16 bit width FLM MIPS16EN The function of this pin differs depending on the operating status During RTC reset input This signal enables use of MIPS16 instructions 0 Disable use of MIPS16 instructions 1 Enable use of MIPS16 instructions During normal operation output LCD first line clock output Note FPD 7 4 GPIO 15 12 Output See 2 2 11 General purpose signals in this section Note FPD 3 0 Output LCD screen data VPLCD VPGPIO1 Output LCD logic power control This signal may be defined as a general purpose output when an external LCD controller is used VPBIAS VPGPIOO Output LCD bias power control This signal may be defined as a general purpose output when an external LCD controller is used Note Connection between FPD 7 0 of the 4181 and LCD panel data lines differs
40. Name I7TYP1 I7TYPO 6 ISTYPO l4TYP1 l4TYPO R W R W R W R W R W R W R W R W R W RTCRST Other resets ISTYPO 12 1 12 0 IOTYP1 IOTYPO R W R W R W R W R W R W R W R W RTCRST Other resets Function I7TYP 1 0 These bits define the type of interrupt generated when the pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 1 0 These bits define the type of interrupt generated when the GPIO6 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 1 0 These bits define the type of interrupt generated when the GPIO5 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt IATYP 1 0 These bits define the type of interrupt generated when the GPIOA pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt Note Holds the v
41. This register indicates whether valid data has been stored in the SODATREG SDMADATREG MIDATREG or MDMADATREG register If data has been written directly to the SODATREG SDMADATREG MIDATREG MDMADATREG register via software the bits in this register are not set so that 1 must be written via software Write is used for debugging and is enabled when the AIUSEN or AIUMEN bit of the SEQREG register is set to 1 If the AIUSEN bit 0 or AIUMEN bit 0 in the SEQREG register then the SODATV bit SDMAV bit 0 or MIDATV bit bit 0 Users Manual U14272EJ3VOUM 311 CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 10 SEQREG 0 0 00 017A Name AIURST Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Function AIURST AIU reset via software 1 Reset 0 Normal Reserved 0 is returned when read AIUMEN Microphone block operation and DMA enable 1 Enable 0 Disable Reserved 0 is returned when read AIUSEN Speaker block operation and DMA enable 1 Enable 0 Disable This register is used to enable disable the AIU s operation 312 User s Manual U14272EJ3VOUM CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 11 INTREG 0x0B00 017C Name Reserved Reserved Reserved Reserved Reserved Reserved MIDLEINTR MSTINTR R W RTCRST Other resets RTCRST Other resets
42. 0 0 0 STOPA 15 8 window stop address bits 15 to 8 High order address bits used to determine the stop address of an address window Address bits 25 to 16 of an window address are fixed to 0 Therefore an 1 window is always mapped to the address space between 0x1400 0000 and 0x1400 FFFF which is the first 64 KB of the ISA IO space Remark User s Manual U14272EJ3VOUM 343 CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 13 SYSMEMSLnREG Index 0x10 0x18 0x20 0x28 0x30 Remark n 0to4 SYSMEMSLOREG 0x10 for Window 0 SYSMEMSL1REG 0x18 for Window 1 SYSMEMSL2REG 0x20 for Window 2 SYSMEMSLS3REG 0x28 SYSMEMSLAREG 0x30 for Window 3 for Window 4 MWSTART A19 MWSTART A18 MWSTART A17 MWSTART A16 MWSTART A15 MWSTART A14 MWSTART A13 MWSTART A12 R W R W R W R W R W R W R W R W 0 0 0 0 0 0 Function 0 0 MWSTARTA 19 12 Memory window start address bits 19 to 12 Low order address bits used to determine the start address of a memory address window Minimum 4 KB can be specified for memory address window 17 4 14 MEMWIDn REG Index 0x11 0x19 0x21 0x29 0x31 Remark 0104 MEMWIDO REG 0x11 for Window 0 MEMWID1 REG 0x19 for Window 1 MEMWID2 REG 0x21 for Window 2 DWIDTH MWSTART A25 MEMWID3 REG 0x29 for Window
43. 0 to 6 The WINTVL 9 0 bits specify the interval between one scan and another in 32 768 kHz clock cycles After the last SCANOUT pin has been driven as high impedance and a time set in the 4 0 bits has elapsed the KIU will wait for the time set in the WINTVL 9 0 bits before driving SCANOUTO as low to start the next scan sequence User s Manual U14272EJ3VOUM 319 CHAPTER 16 KEYBOARD INTERFACE UNIT KIU 16 2 5 Reading scanned data Scanned data is read from the SCANIN 7 0 pins When a SCANOUT pin has been driven as low and the keyboard settling time specified by the T1CNT 4 0 bits has been elapsed the KIU latches scanned data from the SCANIN pins and stores into one of the internal key data registers 16 2 6 Interrupts and status reporting The KIU provides scan status indication that may be polled by the CPU core and may also generate interrupt requests to request keyboard servicing Scan status indication is provided through the SSTAT 1 0 bits of the KIUSCANS register These bits are decoded as follows SSTAT1 SSTATO KIU scan sequencer status Stopped Waiting for key press Scanning T1CNT or During scan interval WINTVL The KIU generates 3 types of maskable interrupt requests KIU interrupt pending status is reported through the KDATLOST KDATRDY and KEYDOWN bits of the KIUINT register All interrupt requests generated by the should be considered asynchronous and must
44. 14 2 14 3 14 4 14 5 14 6 14 7 15 1 15 2 16 1 17 1 17 2 17 3 19 1 20 1 21 1 21 2 21 3 21 4 21 5 21 6 21 7 21 8 21 9 21 10 22 1 1 2 26 LIST OF FIGURES 3 3 Title Page PIU Peripheral Block Diagram 276 Coordinate Detection Equivalent Circuits sessessseseseeeeeeeeeeeenneenenen nennen nnne nene nns 277 Internal Block Diagram of PIU ien ee cec La eee EI ee tete di viene 277 Scan Sequencer State Transition 278 Int rval Times and States 25 28e nen Ue ERU RD Una ee qia Nite 286 Touch Release Detection Timing 444044000 0 nennen nnn nnne nennen 298 A D Port Scan TIMING usui ire iil nena Pec ertet xoc t tet cp de a epa et dee ale 298 Speaker Output and AUDIOOUT Pin nnne 315 AUDIOIN Pin and Microphone Operation ssssssesseseneeeneeeneenneennnnen nennen nennen nnne nnns nnns 316 SGCANOUT Signal Outp t Timirig de deretur pie petet Tbe aa 319 CompactFlash Interrupt Eogic a 333 Mapping of CompactFlash Memory Space sse nennen nennen nennen nnne 350 Mapping of CompactFlash I O Space ssssssseeeeeeneneen
45. 256 colors The LCD controller includes a 256 entry x 18 bit color pallet In color 8 bpp mode the pallet is used to select 256 colors out of possible 262 144 colors The LCD controller can support up to 320 x 320 pixels and typical LCD panel horizontal vertical resolutions are as follows Table 21 1 LCD Panel Resolutions in Pixels TYP Horizontal resolution Vertical resolution The LCD controller also provides power on and power down sequence control for the LCD panel via the VPLCD pin which is for LCD logic power control and VPBIAS pin which is for LCD bias power control Power sequencing is provided to prevent latch up damage to the panel The LCD controller may be disabled to allow connection of an external LCDC with integrated frame buffer RAM such as NEC Electronics PD16661 When the internal LCD controller is disabled by setting the LCDGPMODE register in the GIU the SHCLK LOCLK VPLCD and VPBIAS pins are redefined as follows User s Manual U14272EJ3VOUM 399 CHAPTER 21 LCD CONTROLLER Table 21 2 Redefining LCD Interface Pins When LCD Controller Is Disabled Redefined function Default function LCDCS SHCLK MEMCS16 LOCLK VPGPIO1 VPLCD VPGPIOO VPBIAS 21 2 LCD Module Features e Resolutions Horizontal Up to 320 pixels the number of pixels must be multiplies of 8 Vertical Up to 320 pixels Color 4 bpp 8 bpp up to 256 colors Monochrome 1 bpp 2 bp
46. 31 Notes1 2 Reserved for future use This register is defined to maintain compatibility with the Vr4000 and Vr4400 This register is meaningless during normal operations This register is defined to maintain compatibility with the Vr4100 This register is not used in the Vn4181 hardware User s Manual U14272EJ3VOUM 43 CHAPTER 1 INTRODUCTION 1 4 5 Floating point unit FPU The Vn4181 does not support the floating point unit FPU Coprocessor Unusable exception will occur if any FPU instructions are executed If necessary FPU instructions should be emulated by software an exception handler 1 4 6 Memory management unit The Vn4181 has a 32 bit physical addressing range of 4 GB However since it is rare for systems to implement physical memory space as large as that memory space the CPU provides a logical expansion of memory space by translating addresses composed in the large virtual address space into available physical memory addresses The Vn4181 has three operating modes User Supervisor and Kernel The manner in which memory addresses are mapped depends on these operating modes In addition the Vn4181 supports the 32 bit and 64 bit addressing modes The manner in which memory addresses are translated or mapped depends on these addressing modes A detailed description of the physical address space is given in CHAPTER 4 MEMORY MANAGEMENT SYSTEM For details about the virtual address space r
47. Disable 1 Enable MBATINTR Enables battery low interrupt 0 Disable 1 Enable This register is used to enable disable level 1 interrupts Users Manual U14272EJ3VOUM 177 CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 3 NMIREG 0x0A00 0098 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Reserved Function 0 is returned when read NMIORINT Battery low interrupt request routing 0 NMI 1 IntO This register is used to set the interrupt request signal used to notify the Vn4110 CPU core when a battery low interrupt request has occurred 178 User s Manual U14272EJ3VOUM CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 4 SOFTINTREG 0 0 00 009A Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Function Reserved 0 is returned when read SOFTINTR Set clear a software interrupt request This bit is a write only bit Software interrupt request pending status is reported in the SYSINT1REG 0x0A000080 0 Clear 1 Set This register is used to set a software interrupt request Users Manual U14272EJ3VOUM 179 CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 5 SYSINT2REG 0x0A00 0200 Name Reserved Reserved Rese
48. Not occurred 1 Occurred BATINTR Battery low interrupt request 0 Not occurred 1 Occurred This register indicates level 1 interrupt requests status User s Manual U14272EJ3VOUM 175 CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 2 MSYSINT1REG 0 0 00 008C 1 2 Name Reserved Reserved MDOZEPIU Reserved Reserved MSIUINTR MGIUINTR INTR R W RTCRST Other resets METIMER MRTCL1 MPOWER INTR INTR INTR RTCRST Other resets Function 15 14 Reserved 0 is returned when read 13 MDOZEPIUINTR Enables PIU interrupt during Suspend mode 0 Disable 1 Enable 12 Reserved 0 is returned when read 11 MSOFTINTR Enables software interrupt 0 Disable 1 Enable 10 Reserved 0 is returned when read 9 MSIUINTR Enables SIU interrupt 0 Disable 1 Enable 8 MGIUINTR Enables GIU interrupt 0 Disable 1 Enable 7 MKIUINTR Enables KIU interrupt 0 Disable 1 Enable 6 MAIUINTR Enables AIU interrupt 0 Disable 1 Enable 176 User s Manual U14272EJ3VOUM CHAPTER 9 INTERRUPT CONTROL UNIT ICU 2 2 Function MPIUINTR Enables PIU interrupt 0 Disable 1 Enable Reserved 0 is returned when read METIMERINTR Enables ElapsedTime interrupt 0 Disable 1 Enable MRTCL1INTR Enables RTCLongl interrupt 0 Disable 1 Enable MPOWERINTR Enables Power switch interrupt 0
49. PC AT is a trademark of International Business Machines Corporation User s Manual U14272EJ3VOUM 3 Exporting this product or equipment that includes this product may require a governmental license from the U S A for some countries because this product utilizes technologies limited by the export control regulations of the U S A The information in this document is current as of January 2002 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others Description
50. lt 4 gt lt 5 gt lt 6 gt lt gt lt 8 gt lt 9 gt Stop operations of the DMA controller and LCD controller Set registers in the ICU and to allow notification of the interrupt requests used as wake up events to Fullspeed mode to the CPU core Copy the codes for the Suspend mode lt 4 gt through 11 below beginning at a 16 byte boundary into the cache by using a Fill operation of CACHE instruction and jump to the cached codes Stop all peripheral clocks by writing zero to the CMUCLKMSK register in the MBA Host Bridge If DRAM can accept mixed use of burst and distributive CBR refresh set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge Then execute CBR refresh cycles for a specific time period i e OXGFFF x TClock period burst refresh interval required by DRAM Set Ox3FF to the BCURFCNTREG register in the MBA Host Bridge that determines refresh interval to maximum to prevent an interruption of a Suspend mode sequence Set the SUSPEND bit in the DRAMHIBCTL register to 1 If the BstRefr bit of the MEMCFG REG register in the memory controller to 1 the memory controller performs a burst refresh cycle and then put the DRAM into self refresh mode Poll the OK STOP CLK bit in the DRAMHIBCTL register to confirm that the memory controller completes a burst refresh cycle and put the DRAM into self refresh mode Set the STOP CLK bit in the DRAMHIBCTL reg
51. 0x13 0x1B 0x23 0x2B 0x33 Remark n 0to4 MEMSELO REG 0x13 for Window 0 MEMSEL1 REG 0x1B for Window 1 MEMSEL2 REG 0x23 for Window 2 MEMSELS REG 0x2B for Window MEMSELA4 REG 0x33 for Window 4 MWSTOPA 25 MWSTOPA 24 MWSTOPA 23 MWSTOPA 22 MWSTOPA 21 MWSTOPA 20 R W R W R W R W R W R W 0 0 0 0 0 0 M16W 1 0 Memory window wait state select for 16 bit accesses 00 No additional wait state 01 2 additional wait states 10 3 additional wait states 11 4 additional wait states MWSTOPA 25 20 Memory window stop address bits 25 to 20 The ECU automatically inserts wait states when memory windows are accessed in 16 bit width User s Manual U14272EJ3VOUM 345 CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 17 MEMOFFLnREG Index 0x14 Ox1C 0x24 Ox2C 0x34 Remark n 0to4 MEMOFFLOREG 0x14 for Window 0 MEMOFFL1REG 0x10 for Window 1 MEMOFFL2REG 0x24 for Window 2 OFFSETA 19 OFFSETA 18 OFFSETA 17 OFFSETA 16 MEMOFFL3REG 0 2 MEMOFFLAREG 0x34 for Window 4 OFFSETA 15 OFFSETA 14 C for Window 3 OFFSETA 13 OFFSETA 12 R W R W R W R W R W R W R W R W 0 0 0 0 name Function Vn4181 17 4 18 MEMOFFHnREG Index 0x15 0x1D 0x25 0x2D 0x35 Remark n 0to4 MEMOFFHOREG 0x15 for Window 0 MEMOFFH1REG 0x1D for Wind
52. 13 4 Serial Interface Channel 1 5101 Signals 2 2 22 1 0 00000 239 User s Manual U14272EJ3VOUM 27 LIST TABLES 2 2 Table Title Page 13 5 Interface Channel 1 5101 Loopback Control sessssseseeeeeenee nennen 239 13 6 Interface Channel 2 5102 Signals ssssssseeeeeeeenenee nennen nennen nnne nnne 240 13 7 Serial Interface Channel 2 5102 Loopback Control sss 240 13 8 STN Color LCD Interface Signals 241 13 9 External LCD Controller Interface Signals nennen nennen 241 13 10 Programmable Chip Select Signals 4 1 0 0 20 nnne nnne nnn 242 1321 Registers econtra crt essc ip cct ea 244 14 1 PIU Registers 5 oio eee head loe repe it 280 14 2 PIV Interrupt Registers s n cie c cime eee re ect dea de ctr eet 280 14 83 PIUCNTREG Bit Manipulation and States sssssssssseeeeeeeneeneeen nennen nennen enne 283 14 4 PIUASCNREG Bit Manipulation and States sssssssssesseeeeeeeeen eene nennen nennen 290 14 5 Detected Data and Page Buffers seien rnnt nennen ntn enirn nnns 293 14 6 A D Ports and Data Buffers ee e E i Ee le
53. 2 er eet teeth ea 227 11 27 REC interr pt register ectetuer 229 CHAPTER 12 DEADMAN S SWITCH UNIT 50 22 2 2 1 230 jacere 230 12 2 Register E nete edes ua i eee DEn Enc 230 12 2 DSUCNTREG 0x0BO00 00EOQ irent d ctt ertt tetti ieee de Eee ra ct ep adierit teret 231 12 2 2 DSUSETREG 0X0BO00 00E2 mim teu ERREUR 232 12 2 8 DSUCERREG OXOB00 OOE4 rere t repe e ee re rr rede re p ecd 233 12 2 4 DSUTIMREG 0 0 00 00 6 nnne nnne aaa pira ei ie ai nnne nens 234 12 3 Register Setting FlOW ice fadat aD aa 235 CHAPTER 13 GENERAL PURPOSE UNIT 2 2 236 1321 el Mil e 236 13 1 1 GPIO pins and alternate functions 4 4 0 0 0000 236 134 2 VO direction Control i e oc Ee en 238 13 1 3 General purpose registers 238 13 2 Alternate Functions Overview 238 13 2 1 Clocked serial interface CSI 2222244 4 1 0 nennt 238 13 2 2 Serial int
54. 275 PIU registers eise ee 280 PIUABnREG n 0 to 294 temere pend 291 PIUASGNREG 2 i en iter ELI 289 PIUGIVEREG gp eed bt t ens 292 PIUGMDREG 3 nite nettes 287 PIUCNTRE QG in e teeth 281 che ctt eet 284 PIUPBnmREG n 0 or 1 M 0 to 4 293 PIUSIVEREQ etre dete et 285 PIUSTBLERBEQG s n eee 286 pixel ii 34 399 PLL passive 430 PM 188 PMU registers h t 208 dehet 211 PMUDIMREQG RUE 214 PMUIRNITREGZ 3 eub 209 PMUMALI TREG en hee 213 polling Mode inenen 370 389 power management 188 power 31 45 188 ANSON ee eee 189 442 User s Manual U14272EJ3VOUM APPENDIX INDEX power Orn Contro c cie erede 194 power on sequence 102 407 PRid register en etie decet 82 programmable chip selects 1 242 PWRGONREG H ne tet 425 PWRGONREQG2 eet pee 426 PWRRSETDRV ueri een 336 R Random register 10 44242221 69 realtime clock unit 216 re
55. BATTINT signal This is an interrupt signal that is input when remaining battery power is low during normal operations The external agent checks the remaining battery power and activates this signal if voltage sufficient for operations cannot be supplied 2 2 5 Clock interface signals RTCX 2 1 Connections to 32 768 kHz crystal resonator CLKX 2 1 Connections to 18 432 MHz crystal resonator User s Manual U14272EJ3VOUM 55 CHAPTER 2 PIN FUNCTIONS 2 2 6 Touch panel interface and audio interface signals Signal name Description of function Touch panel X coordinate data They use the voltage applied to the X coordinate and the voltage input to the Y coordinate to detect which coordinates on the touch panel are being pressed Touch panel Y coordinate data They use the voltage applied to the Y coordinate and the voltage input to the X coordinate to detect which coordinates on the touch panel are being pressed ADIN 2 0 Input General purpose A D data inputs AUDIOIN Input Audio input AUDIOOUT Output Audio output 2 2 7 LED interface signals LEDOUT Output This is an output signal for lighting LEDs 2 2 8 CompactFlash interface and keyboard interface signals Signal name Description of function WEZ SCANOUT7 Output CompactFlash write enable output or keyboard scan data output OEZ SCANOUT6 Output CompactFlash output ena
56. Bit 7 6 Reserved 0 is returned when read LCE 7 0 X coordinate of the second edge of the LOCLK Set this register to a value one half of the second edge of the LOCLK Users Manual U14272EJ3VOUM 415 CHAPTER 21 LCD CONTROLLER 21 4 5 VRTOTALREG 0x0A00 0408 Reserved Reserved 0 is returned when read Vtot 8 0 Vertical total number of lines including vertical retrace period Reserved Bit 7 6 5 4 3 2 1 Function Dummy line inserting position 0 Immediately before vertical blank 1 Anywhere in vertical blank Reserved 0 is returned when read Vact 8 0 Vertical visible number of lines 416 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 21 4 7 FVSTARTREG 0x0A00 040C Reserved Reserved 0 is returned when read FLMS 8 0 Y coordinate of the first FLM edge Reserved Bit Reserved 0 is returned when read FLME 8 0 Y coordinate of the second FLM edge User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 21 4 9 LCDCTRLREG 0x0A00 0410 Reserved Reserved Bit 7 6 5 4 3 2 1 0 Name FIFOC2 FIFOC1 FIFOCO Reserved ContCkE LPPOL FLMPOL SCLKPOL Reserved 0 is returned when read FIFOC 2 0 FIFO control A FIFO transfer is performe
57. DATA12 48 DATA14 50 GND IO O DATA11 47 DATA13 O Remark _ indicates active low SDCLK O ADDO ADD1 ADD2 ADD3 ADD4 ADD5 GND_LOGIC O VDD_LOGIC O ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 O GND IO O VDD IO ADD12 O ADD13 O ADD14 O 0015 0016 0017 0018 0019 0020 ADD21 DTR1 GPIO30 CLKSEL2 DSRI GPIO31 POWER O RSTSW lt RTCRST POWERON MPOWER lt BATTINH BATTINT VDD LOGIC O GND LOGIC gt CF_AEN SCANINO lt CF_DIR SCANIN1 CF_DEN SCANIN2 VCCENZ SCANIN3 lt 015164 5 4 lt WAITS SCANINS RESET SCANING lt gt CF_REG SCANIN7 DD IO ND IO F_BUSY SCANOUTO F_CE1 SCANOUT1 F_CE2 SCANOUT2 F_STSCHG SCANOUT3 F_lOR SCANOUT4 F_lOW SCANOUTS F_OE SCANOUT6 F_WE SCANOUT7 m e o lt lt lt 50 User s Manual U14272EJ3VOUM CHAPTER 2 PIN FUNCTIONS Pin Identification ADD 21 0 ADIN 2 0 AUDIOIN AUDIOOUT BATTINH BATTINT CD1 CD2 CF_AEN CF_BUSY _ 2 1 _ DIR 516 CF CF IOWs CF CF_REG CF_RESET CF_STSCHG CF_VCCEN CF_WAIT CF_WE
58. DCU runs at the MBA bus clock TClock frequency Remark DCU contains a 32 bit temporary storage register for each DMA channel For memory to I O transfers the DCU performs a 32 bit memory read from DRAM and stores the read data into the temporary storage register The DCU then transfers data from this register to the target I O device For a 16 bit device such as the Speaker channel the DCU performs two I O writes to the D A converter for each memory read During DMA transfers all DCU registers are write protected if valid data is present in the temporary storage registers Because of this to start DMA transfers software must read the register that is written immediately after the write to confirm that the register has been correctly set Users Manual U14272EJ3VOUM 143 CHAPTER 7 DMA CONTROL UNIT DCU 7 2 DCU Registers Physical address 0 0 00 0020 Table 7 1 DCU Registers Register symbol MICDEST1REG1 Function Microphone destination 1 address register 1 0 0 00 0022 MICDEST1REG2 Microphone destination 1 address register 2 0 0 00 0024 MICDEST2REG1 Microphone destination 2 address register 1 0 0 00 0026 MICDEST2REG2 Microphone destination 2 address register 2 0 0 00 0028 SPKRSRC1REG1 Speaker source 1 address register 1 0 0 00 002A SPKRSRC1REG2 Speaker source 1 address register 2 0x0A00 002C SPKRSRC2REG1 Speaker source 2 address register 1
59. Figure 6 8 SDRAM Configuration ADD 13 0 SDRAS CAS UDQM LDQM MEMWR SDCSO DATA 15 0 SDCLK CLKEN 4181 SDCS1 A 13 0 RAS CAS UDQM LDQM WE CS D 15 0 CLK CKE SDRAM Banko Figure 6 8 illustrates an example when connecting devices of 4 Mbits x 16 Remark The SDRAMs supported by the Vr4181 are as follows Capacity 16 Mbits Configuration 512 Kbits x 16 x 2 banks Address pins Bank address 64 Mbits 2 Mbits x 16 x 2 banks 64 Mbits 130 1 Mbits x 16 x 4 banks User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 6 5 Memory Controller Register Set Table 6 3 Memory Controller Registers 0x0A00 0300 EDOMCYTREG EDO DRAM timing register 0x0A00 0304 R W MEMCFG_REG Memory configuration register 0x0A00 0308 R W MODE_REG SDRAM mode register 0x0A00 030C R W SDTIMINGREG SDRAM timing register Caution Since these registers are powered by 2 5 V power supply the contents of these registers are cleared after Hibernate mode 6 5 1 EDOMCYTREG 0x0A00 0300 SrefRpre2 SrefRpre1 SrefRpreo Caspre1 0 At reset Name R W Rcasdly1 R W Rcasdly0 R W At reset 0 0 Bit Name Function 15 to 13 Reserved 0 is returned when read 12 to 10 SrefRpre 2 0 Self refresh RAS precharge time 000 3 TClock 001 4 TClock 01
60. Microphone input data register 0 0 00 0172 MCNTREG Microphone input control register 0 0 00 0178 DVALIDREG Data valid indication register 0 0 00 017A SEQREG Sequencer enable register 0x0B00 017C INTREG Interrupt register 0 0 00 017E MCNVC END Microphone sample rate control register State of interrupt requests caused by AIU is indicated and can be set in the following registers which are included in the ICU refer to CHAPTER 9 INTERRUPT CONTROL UNIT ICU for details 302 0 0 00 0084 Table 15 2 AIU Interrupt Registers AIUINTREG AIU interrupt indication register 0 0 00 0090 MAIUINTREG AIU interrupt mask register User s Manual U14272EJ3VOUM CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 1 SDMADATREG 0 0 00 0160 Name Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets Name SDMA7 SDMA6 SDMA5 SDMA4 SDMA3 SDMA2 SDMA1 SDMAO R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 15 to 10 Reserved 0 is returned when read 9to0 SDMA 9 0 Speaker output DMA data This register is used to store 10 bit DMA data for speaker output When SODATREG register is empty the data is transferred to the SODATREG register Write is used for debugging and is enabled when the AIUSEN bit of the SEQREG register is set to 1 This register
61. Note 2 Note 1 GPIO8 DSR2ft Note 1 Note 2 Note 1 GPIO7 DTR2 Note 1 Note 2 Note 1 GPIO6 RTS2 Note 1 Note 2 Note 1 GPIO5 DCD2 Note 1 Note 2 Note 1 4 Note 1 Note 2 50 Note 1 1 Note 2 Hi Z GPIO2 SCK Note 1 Note 2 Note 1 GPIO1 SO Note 1 Note 2 Note 1 GPIOO SI Note 1 Note 2 Note 1 LEDOUT Notes1 Maintains the state of previous Fullspeed mode 2 The state depends on the GPHIBSTH GPHIBSTL register setting 3 The input level is sampled to determine the CPU core operation frequency Remark 0 low level 1 high level Hi Z high impedance 62 User s Manual U14272EJ3VOUM Note 1 Note 1 CHAPTER 2 PIN FUNCTIONS 2 4 Recommended Connection of Unused Pins and Circuit Types 1 3 Pin Name Recommended Connection When Not Used Circuit Type ADD 21 0 DATA 15 0 MEMRD B MEMWR SDCS 1 0 RAS 1 0 UDQM UCAS LDQM LCAS CAS Leave open SDRAS Leave open SDCLK Leave open CLKEN Leave open SYSDIR Leave open SYSEN Leave open IORD Z GPIO16 Connect to VDD IO or GND via resistor IOWRZ GPIO17 Connect to VDD IO or GND via resistor IORDY GPIO18 Connect to VDD IO or GND via resistor IOCS162 GPIO19 Connect to VDD IO or GND via resistor UBEZ GPIO20 M Connect to VDD IO o
62. Other resets RTCRST Other resets Function Reserved 0 is returned when read PCLKDIV 1 0 PCLK peripheral clock divisor rate selection These bits select the operating frequency of PCLK 00 TClock 8 01 TClock 4 10 TClock 2 11 TClock 1 This register is used to set the PCLK divisor rate PCLK is a clock for internal ISA peripherals and its frequency must be set to between 18 432 MHz and 33 MHz 138 User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 6 7 2 ISABRGSTS 0 0 00 02C2 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Reserved Function 0 is returned when read IDLE ISA Bridge status 0 ISA Bridge is busy 1 ISA Bridge is idle This register shows the ISA Bridge operation status User s Manual U14272EJ3VOUM 139 CHAPTER 6 BUS CONTROL 6 7 3 XISACTL 0 0 00 02 4 Name Reserved Reserved Reserved Reserved Reserved INTRESULT R W RTCRST Other resets RTCRST Other resets 15to 11 Reserved Function 0 is returned when read 10 EXTRESULT External ISA result cycle enable 0 Disabled The MBA bus arbiter waits until an external ISA read is finished 1 Enabled The MBA bus arbiter issues a result cycle
63. Reset 0 Release reset This register is used to reset SIU2 forcibly 20 3 15 SIUCSEL_2 0x0C00 000A Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved SIUCSEL R W RTCRST Other resets Bit Name Function Reserved 0 is returned when read SIUCSEL Mask for echo back of IrDA 1 Mask disabled 0 Mask enabled echo back mode This register is used to specify whether the use of echo back function on IrDA transmission and reception is enabled 396 User s Manual U14272EJ3VOUM CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 20 3 16 SIUACTMSK 2 0 0 00 000C Name Reserved Reserved RxDMSK RTSMSK DCDMSK DTRMSK Reserved TxWRMSK R W R R R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Function Reserved 0 is returned when read RxDMSK Mask for notification of change on RxD2 1 Mask 0 Unmask RTSMSK Mask for notification of change on RTS2 1 Mask 0 Unmask DCDMSK Mask for notification of change on DCD2 1 Mask 0 Unmask DTRMSK Mask for notification of change on DTR2 1 Mask 0 Unmask Reserved Write 0 when write 0 is returned when read TxWRMSK Mask for notification of transmit buffer write 1 Mask 0 Unmask This register is used to set masks for notification of operation statuses to the Activity Timer of the SIU2 When 1 is set in this register stat
64. Voltage sense status These bits are read only and hardwired to 10 binary since the Vn4181 has no voltage sense pins 348 User s Manual U14272EJ3VOUM CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 22 VOLTSELREG Index 0x2F Reserved Reserved Reserved Reserved Reserved Reserved VCCEN1 VCCENO R W R W 1 0 Function Reserved 0 is returned when read VCCEN 1 0 Card connection status 01 3 3 V card connected 10 No card connected Caution Do not perform any write to this bit If the PWREN bit of the PWRRSETDRYV register is set to 1 when the VCCEN 1 0 bits 01 the CF VCCEN signal becomes active Remark 4181 supports cards with the card voltage of 3 3 V only User s Manual U14272EJ3VOUM 349 CHAPTER 17 COMPACTFLASH CONTROLLER 17 5 Memory Mapping of CompactFlash Card 1 Memory window In the VR4181 memory windows can be placed at any address in the ISA memory space The start address of a memory window is output without modification to the Vn4181 s ADD pins However spaces used for programmable chip select LCD chip select etc must not be specified as a memory window The CompactFlash memory space is 2 KB and the minimum memory window size is 4 KB Accordingly when using CompactFlash with the Vn4181 the card s entire memory space is mapped to a single memory window Mapping starts from the LSB The remaining part of the memory wind
65. WAITZ SCANIN5 Connect to VDD IO via resistor A CF_IOIS16 SCANIN4 Connect to VDD_IO via resistor A CF_VCCEN SCANIN3 Leave open A CF_DEN SCANIN2 Leave open A CF_DIR SCANIN1 Leave open A CF_AEN SCANINO Leave open A RxD1 GPIO25 Connect to VDD IO or GND via resistor A TxD1 GPIO26 CLKSELO Connect to VDD IO GND_IO via resistor A RTS14 GPIO27 CLKSEL1 Connect to VDD IO or GND via resistor A CTS14 GPIO28 Connect to VDD IO or GND via resistor A DCD14 GPIO29 Connect to VDD IO or GND via resistor A DTR1 GPIO30 CLKSEL2 Connect to VDD IO or GND_IO via resistor A DSR1 GPIO31 Connect to VDD IO or GND_1O via resistor A IRDIN RxD2 Connect to VDD IO or GND_1O via resistor A IRDOUT TxD2 Leave open A GPIO 15 14 FPD 7 6 CD 2 1 4 Connect to VDD IO or GND via resistor A GPIO 13 12 FPD 5 4 Connect to VDD IO or GND via resistor A GPIO11 PCS1 Connect to VDD_IO or GND_1O via resistor A GPIO10 FRM SYSCLK Connect to VDD IO or GND via resistor A GPIO9 CTS2 Connect to VDD IO or GND_1O via resistor A GPIO8 DSR2 Connect to VDD IO or GND via resistor A GPIO7 DTR2 Connect to VDD IO or GND_1O via resistor A GPIO6 RTS2 Connect to VDD IO or GND via resistor A GPIO5 DCD2 Connect to VDD IO or GND_1O via resistor A GPIO4 Connect to VDD IO or GND_1O via resistor A 64 User s Manual U14272EJ3VOUM CHAPTER 2 PIN FUNCTIONS 3 3 Recommended Connection When Not Used Circuit Typ
66. address 0x0B00 0314 for additional information see 13 3 14 GPSICTL 0 0 00 0314 When GPIO pins have been assigned to provide the serial interface channel 1 inputs RxD1 DTR1 RTS1 DCD1 the GIU simply passes the signals driven on the GPIO pins to the corresponding serial interface channel 1 inputs Otherwise the GIU drives these signals based on the value programmed in the GPSICTL register as follows Table 13 5 Serial Interface Channel 1 SIU1 Loopback Control LOOPBK 1 bit value Source for driving SIU1 input DSR1 REGDSR1 bit 9 value CTS1 REGCTS1 bit 10 value DCD1 REGDCD1 bit 8 value RxD1 REGRXD1 bit 11 value DSR1 DTR1 output CTS1 RTS1 output DCD1 REGDCD1 bit 8 value RxD1 REGRXD1 bit 11 value User s Manual U14272EJ3VOUM 239 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU The serial interface channel 2 SIU2 utilizes the dedicated IRDIN RXD2 and IRDOUT TxD2 pins The line control signals DTR2 RTS2 DCD2 DSR2 and CTS2 are enabled by writing to the GPIO Mode registers and utilized through the following GPIO pins Table 13 6 Serial Interface Channel 2 SIU2 Signals GPIO pin 5102 signal GPIO9 GPIO8 Output Input Output The transmit and receive data signals 2 and RxD2 are enabled by writing to the SIUIRSEL 2 register in the 5102 Control of the serial interface channel 2 line status inputs is identical to that of the
67. and RTC Stop operations of the DMA controller and LCD controller Copy the codes for the Hibernate mode lt 4 gt through 11 below beginning at a 16 byte boundary into the cache by using a Fill operation of CACHE instruction and jump to the cached codes Stop all peripheral clocks by writing zero to the CMUCLKMSK register in the MBA Host Bridge If DRAM can accept mixed use of burst and distributive CBR refresh set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge Then execute CBR refresh cycles for a specific time period i e OXGFFF x TClock period burst refresh interval required by DRAM Set Ox3FF to the BCURFCNTREG register in the MBA Host Bridge that determines refresh interval to maximum to prevent an interruption of a Hibernate mode sequence Set the SUSPEND bit in the DRAMHIBCTL register to 1 If the BstRefr bit of the MEMCFG REG register in the memory controller to 1 the memory controller performs a burst refresh cycle and then put the DRAM into self refresh mode Poll the OK STOP CLK bit in the DRAMHIBCTL register to confirm that the memory controller completes a burst refresh cycle and put the DRAM into self refresh mode Set the STOP CLK bit in the DRAMHIBCTL register to 1 to stop supplying TClock to the memory controller 10 Set the DRAM EN bit in the DRAMHIBCTL register to 1 so that the DRAM interface signals are latched 11 Execute a HIBERNATE instruc
68. and the modem status The content of the IIR3 bit is valid only in the FIFO mode and it is always 0 in the 16450 mode The IIR2 bit becomes 1 when the IIR3 bit is set to 1 366 User s Manual U14272EJ3VOUM CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 SIUIID 1 register Note Bit 3 Bit 2 Bit 1 Priority level Highest 1st Table 19 3 Interrupt Function Interrupt type Receive line status Interrupt set reset function Interrupt source Overrun error parity error framing error or break interrupt Interrupt reset control Read line status register 2nd Receive data ready Receive data exists or has reached the trigger level Read the receive buffer register or lower the data in the FIFO than trigger level Character timeout During the time period for the four most recent characters not one character has been read from the receive FIFO nor has a character been input to the receive FIFO During this period at least one character has been held in the receive FIFO Read receive buffer register Transmit holding register empty Transmit register is empty Read IIR if it is the interrupt source or write to transmit holding register Note FIFO mode only Modem status CTS1 DSR1 or DCD1 User s Manual U14272EJ3VOUM Read modem status register 367 CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 7 SIUFC 1 0 0 00 0012 Write Na
69. from one to 16 characters can be written to the transmit FIFO during servicing of this interrupt or when the SIUIID 2 register is read 2 If there are not at least two bytes of character data in the transmit FIFO between one time when the LSR5 bit 1 transmit FIFO is empty in the SIULS 2 register and the next time when the LSR5 bit 1 transmit FIFO empty status is reported to the IIR bits after a delay period calculated as the time for one character the time for the last stop bit s When transmit interrupts are enabled the first transmit interrupt request that occurs after the FCRO bit FIFO enable bit in the SIUFC 2 register is overwritten is indicated immediately The priority level of the character timeout interrupt and receive FIFO trigger level interrupt is the same as that of the receive data ready interrupt The priority level of the transmit FIFO empty interrupt is the same as that of the transmit holding register empty interrupt Whether data to be transmitted exists or not in the transmit FIFO and the transmit shift register check the LSR6 bit of the SIULS 2 register The LSR5 bit of the SIULS 2 register is used to check whether data to be transferred exists or not in the transmit FIFO only Therefore there may be data in the transmit shift register FIFO polling mode When the FCRO bit 2 1 FIFO is enabled in the SIUFC 2 register if the value of any or all of the SIUIE 2 register bits 3 to 0 becomes 0 SIU2 enters
70. oia eee eR PH HAE RA RERO Pte e 276 14 2 Scan Sequencer State Transition eese eeeeeeeeen nennen nnne tnn nana 278 14 3 ISI dlc Ps 280 14 3 1 PIUCNTREG 0x0BO00 0122 en saspe aeneae dea cree ao dors 281 14 3 2 PIUINTREG 0x0B00 0124 ric ED i imde ERR a Re e a ed 284 14 3 3 PIUSIVLREG OxOBOO 0126 eene nennen nnne rennes 285 14 3 4 PIUSTBLREG 0 0 00 0128 286 14 3 5 PIUCMDREG 0 0 00 012A 42 0 2 6 600000 00000 000000000 287 14 3 6 PIUASCNREG 0 0 00 0130 289 14 3 7 PIUAMSKREG 0 0 00 0132 291 14 3 8 PIUCIVLREG 0 0 00 013E nennen eene nennen nnne 292 14 3 9 PIUPBnmREG 0 0 00 02A0 to 0 0 00 02AE 0 0 00 02BC to 0 0 00 02 293 14 3 10 PIUABnREG 0 0 00 02 0 to 0 0 00 02B6 294 14 4 State Transition Flow 295 14 5 Relationships among TPX TPY ADIN and AUDIOIN Pins and States 297 14 6 Timing mee nee enon een es BT Seo Dt ane emis LU emu A I c TELS 298 14 6 1 Touch release detection timing
71. sampling starts after the period calculated with the formula below 5 1 conversion rate 44 1 22 05 11 025 or 8 us 5 Set microphone power ON via GPIO 6 Enable microphone operation 0 0 00 017A AIUMEN 1 Output A D request to A D converter Acknowledge and 10 bit conversion data are returned from A D converter Store data in MIDATREG 0x0B00 0178 MDMAV 0 MIDATV 1 Transfer data from MIDATREG to MDMADATREG MDMAV 1 MIDATV 0 MSTINTR 1 and an interrupt request receive complete occurs Issue DMA request and store MDMADATREG data to memory MDMAV 0 MIDATV 0 Issue an A D request once per conversion timing interval and receive 10 bit data becomes MIDLEINTR 1 when DMA delays and MIDATV 1 during conversion timing interval and data loss interrupt request occurs DMA page boundary interrupt request occurs at page boundary Clear the page interrupt request to continue output 7 Disable microphone operation Ox0B00 017A AIUMEN 0 8 Set microphone power OFF via GPIO 9 Set A D converter s Vref to OFF 0x0B00 0172 ADENAIU 0 10 Disable DMA in DCU Pons Figure 15 2 AUDIOIN Pin and Microphone Operation A lt 1 gt to lt 3 gt lt 4 gt lt 5 gt lt 6 gt 7 8 lt 9 gt lt 10 gt AUDIOIN time sampling 316 User s Manual U14272EJ3VOUM CHAPTER 16 KEYBOARD INTERFACE UNIT KIU 16 1 General The Keyboard Interface Unit KIU provides the interface betw
72. the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown After the CPU core is restarted the BATTINH bit must be checked and cleared to 0 by software Figure 10 5 Activation via CompactFlash Interrupt Request BATTINH F RTO intemal MEME AG CF_BUSY Input POWERON Output ZEN MPOWER Output BATTINH BATTINT Input t OON Figure 10 6 Activation via CompactFlash Interrupt Request BATTINH L RTC Internal 5 Input POWERON Output MPOWER Output L Input L 196 User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 5 3 Activation via GPIO activation interrupt request When any of the GPIO 15 0 signals are asserted the PMU checks the GPIO 15 0 activation interrupt enable bits in the GIU If GPIO 15 0 activation interrupts are enabled the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated since the GPIO 15 0 activation enable interrupt bits are cleared after an RTC reset the GPIO 15 0 signal cannot be used for activation immediately after an RTC reset After asserting the POWERON signal the PMU checks the BATTINH signal and de asserts the POWERON signal If the BATTINH signal is at high level the PMU cancel
73. 0 Remark 6 2 3 BCUSPEEDREG 0x0A00 000C Modification of Figure 6 2 ROM Read Cycle and Access Parameters Deletion of description for Div4 mode and addition of description in Remark in 6 2 6 2 Peripheral clock TClock User s Manual U14272EJ3VOUM Major Revisions in This Edition 2 5 Page Description p 119 Modification of description in 6 3 2 Connection to external ROM x 16 devices p 122 Modification of Remark in 6 3 3 4 64 Mbit PageROM p 123 Modification of figure in 6 3 3 5 32 Mbit flash memory when using Intel DD28F032 pp 125 to 128 130 Modification of Figure 6 3 through Figure 6 8 p 129 Addition of description in Table 6 2 Vn4181 EDO DRAM Capacity p 134 Addition of Caution and modification in Remark in 6 5 2 MEMCFG REG 0 0 00 0304 135 Modification of description for bits 6 to 4 in 6 5 3 MODE REG 0x0A00 0308 136 Modification of Note in 6 5 4 SDTIMINGREG 0x0A00 030C 137 Addition of description in 6 6 ISA Bridge 138 Addition of description in 6 7 1 ISABRGCTL 0 0 00 02 0 140 Modification of description for bits 10 and 9 and addition of description in 6 7 3 XISACTL 0 0 00 02 4 149 Modification of description for bits 3 and 2 in 7 2 6 AIUDMAMSKREG 0x0A00 0046 150 Modification of values at reset in 7 2 7 MICRCLENREG 0x0A00 0658 and 7 2 8 SPKRCLENREG 0x0A00 065A 151 Addition of description for bi
74. 0 00 0326 273 Modification of description for bit 7 in 13 3 23 LCDGPMODE 0 0 00 032E 275 Addition of Caution in 14 1 General 283 Modification of location of Note in Table 14 3 PIUCNTREG Bit Manipulation and States 286 Modification of description for bits 5 to 0 in 14 3 4 PIUSTBLREG 0 0 00 0128 289 Addition of description in 14 3 6 PIUASCNREG 0 0 00 0130 290 Modification of description in Table 14 4 PIUASCNREG Bit Manipulation and States 291 Addition of description in 14 3 7 PIUAMSKREG 0 0 00 0132 292 Modification of values at reset for bits 2 to 0 in 14 3 8 PIUCIVLREG 0 0 00 013E 295 Modification of description in Table 14 7 Mask Clear During Scan Sequencer Operation 298 Addition of Note in Figure 14 6 Touch Release Detection Timing 298 Modification of Figure 14 7 A D Port Scan Timing l l lp l l l l 9 301 Modification of description and addition of Caution in 15 1 General pp 303 304 Modification of addresses in 15 2 1 SDMADATREG 0 0 00 0160 and 15 2 2 MDMADATREG 0x0BOO 0162 p 308 Modification of values at reset for bits 11 10 and 5 and addition of Caution in 15 2 6 SCNVC END 0x0BOO 016E p 314 Modification of values at reset for bits 11 10 and 5 and addition of Caution in 15 2 12 MCNVC END 0x0BOO 017E pp 315 316 Addition of descriptions in 15 3 1 Output speake
75. 0 or 1 m 0 to 3 276 User s Manual U14272EJ3VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU Figure 14 2 Coordinate Detection Equivalent Circuits a Y coordinate detection TPY1 pin 3 V TPY1 pin 0 V Vv2 44 pin O TPXO0 pin Q TPYO 0 V TPYO pin 3 V b X coordinate detection pin TPYO pin DL pEm aati Vx pin 3 V O O TPX1 pin 0 V TPXO pin O O Text pin V Figure 14 3 Internal Block Diagram of PIU Waa tod PIU Internal bus Internal bus Scan sequencer controller PIU registers Touch panel Touch panel interface controller A D converter General purpose A D ports Audio input port User s Manual U14272EJ3VOUM 277 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU The PIU includes three blocks the internal bus controller the scan sequencer and the touch panel interface controller Internal bus controller The internal bus controller controls the internal bus the PIU registers and interrupts and communicates with the A D converter Scan sequencer The scan sequencer is used for PIU state management Touch panel interface controller The touch panel interface controller is used to control the touch panel 14 2 Scan Sequencer State Transition Figure 14 4 Scan Sequencer State Transition Diagram Disable m Reset 1
76. 1 to keep the processor from overwriting the address of the exception causing instruction contained in the EPC register in the event of another exception The EPC register never indicates the address of the instruction in a branch delay slot Figure 3 15 EPC Register When MIPS16 ISA Is Disabled a 32 bit mode EPC b 64 bit mode EPC EPC Restart address virtual after exception processing User s Manual U14272EJ3VOUM 81 CHAPTER 3 REGISTERS Figure 3 16 EPC Register When MIPS16 ISA Is Enabled a 32 bit mode 31 1 0 EPC EIM EPC Bits 31 to 1 of restart address virtual after exception processing EIM ISA mode at which an exception occurs 1 When MIPS16 SIA instruction is executed 0 gt When MIPS III ISA instruction is executed b 64 bit mode 63 1 0 EPC EIM EPC Bits 63 to 1 of restart address virtual after exception processing EIM ISA mode at which an exception occurs 1 When MIPS16 SIA instruction is executed 0 gt When MIPS III ISA instruction is executed 3 2 14 Processor Revision Identifier PRId register 15 The 32 bit read only Processor Revision Identifier PRId register contains information identifying the implementation and revision level of the CPU and CPO Figure 3 17 PRid Register 31 16 15 8 7 0 Imp CPU core processor ID number 0 0 for the Vn4181 Rev CPU core processor revision number 0 Reserved for future use Write 0
77. 13 3 11 GPINTSTAT 0x0B00 09814 i inten eee Detenido edes 262 18 User s Manual U14272EJ3VOUM 19 3 12 GPHIBSTH 0x0BOO 03106 rrt rre eee 263 13 3 18 GPHIBSTL 0 0 00 0318 sss eene enne nennen nnne nere nennen nnns 264 13 314 GPSIG TI OXOBOO OS TA 5 men eeu cesi uteri 265 19 3 15 KEYEN 0x0B00 0310O tr rm crecer teet cree eoe tet 267 13 3 16 PCSOSTRA 0 0 00 0320 2255 bes eite ive uide 268 19 837 PESOSTPA 0x0B00 0322 11 5 namen eee Sine eii Na He 268 13 3 18 PCSOHIA OxOBOO 0324 2 24 44 4 1 2 106000000000 0600000 0 000000000000 nnne rennes 269 13 3 19 PCS1STRA 0x0BO0 0826 ce eite utet ge ve uoa a 270 13 3 20 PCS1S TPA 0x0B00 0328 ois ee ERR RENE E recie d teens 270 13 3 21 PCS1HIA OxOBOO 0324 a aA aE a ae nnne nennen nnne rennes 271 13 3 22 PCSMODE 0x0B00 0320 272 13 3 23 LCDGPMODE 0 0 00 032 0 cecccceceesecceeeeceeeeeneeeeeeeaeeeecseaeeeseneeeesssaeeeesseneeesseseeesssnseessseaes 273 13 3 24 MISCREGn 0 0 00 0330 to 0 0 00 034 274 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU nnmnnn 275 1 hea Hine nee eed ee eae ee ete 275 1411 Blockdiagrarms
78. 15 0 Frame buffer start address lower 16 bits Caution FBSA 2 0 bits must be cleared to 0 21 4 14 FBSTADREG2 0x0A00 041A FBSA31 FBSA30 FBSA29 FBSA28 FBSA27 FBSA26 FBSA25 FBSA24 FBSA23 FBSA22 FBSA21 FBSA20 FBSA19 FBSA18 FBSA17 FBSA16 R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 15 to 0 FBSA 31 16 Frame buffer start address upper 16 bits FBSA 31 29 are always 0 when read The FBSTADREG1 and FBSTADREG2 registers are used to specify the frame buffer starting address The frame buffer is linear and the pixels are packed This address corresponds to the first top left pixel of the screen 422 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 21 4 15 FBENDADREG1 0x0A00 0420 FBEA12 FBEA15 FBEA14 FBEA13 FBEA10 15to 0 FBEA 15 0 Frame buffer end address lower 16 bits 21 4 16 FBENDADREG2 0x0A00 0422 1 0 29 28 27 26 25 FBEA24 FBEA23 FBEA22 21 FBEA20 FBEA19 FBEA18 FBEA17 FBEA16 R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 15100 31 16 Frame buffer end address upper 16 bits FBEA 31 29 are always 0 when read User s Manual U14272EJ3VOUM
79. 193 Modification of description in Table 10 3 Operations During Shutdown 194 Modification of description of Caution in 10 5 Power on Control 196 Modification of signal name in 10 5 2 Activation via CompactFlash interrupt request 197 Modification of description in 10 5 3 Activation via GPIO activation interrupt request User s Manual U14272EJ3VOUM 7 Major Revisions in This Edition 3 5 Page Description p 198 Modification of description of Cautions in 10 5 4 Activation via DCD interrupt request pp 201 to 204 Modification of descriptions in 10 6 1 through 10 6 4 pp 205 to 207 Addition of 10 6 5 through 10 6 8 209 Modification of description for bit 6 in 10 7 1 PMUINTREG 0 0 00 00A0 211 Modification of value at reset for bit 7 in 10 7 2 PMUCNTREG 0 0 00 00A2 214 Modification of description for bit 2 to 0 in 10 7 4 PMUDIVREG 0 0 00 00AC 215 Modification of description for bit 4 in 10 7 5 DRAMHIBCTL 0 0 00 00B2 220 Modification of value at reset for bit 15 in 11 2 2 3 ECMPHREG 0 0 00 00CC 238 Modification and addition of descriptions in 13 1 3 General purpose registers 242 Modification of description in 13 2 5 16 bit bus cycles 254 Modification of R W for bits 15 to 8 in 13 3 5 GPDATHREG 0 0 00 0308 267 Modification of description in 13 3 15 KEYEN 0 0 00 031C 270 Modification of description for bit 15 in 13 3 19 PCS1STRA 0
80. 256 KB TLB read and write instructions use this register as either a source or a destination Bits 18 to 11 that are targets of comparison are masked during address translation The contents of the PageMask register are undefined after a reset so that it must be initialized by software Figure 3 5 PageMask Register 31 19 18 11 10 0 MASK Page comparison mask which determines the virtual page size for the corresponding entry 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read Table 3 3 lists the mask pattern for each page size If the mask pattern is one not listed below the TLB behaves unexpectedly Table 3 3 Mask Values and Page Sizes Page size 1 KB 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 1 1 16 KB 0 0 0 0 1 1 1 1 64 KB 0 0 1 1 1 1 1 1 256 1 1 1 1 1 1 1 1 72 User s Manual U14272EJ3VOUM CHAPTER 3 REGISTERS 3 2 6 Wired register 6 The Wired register is read write register that specifies the lower boundary of the random entry of the TLB as shown in Figure 3 6 Wired entries cannot be overwritten by a TLBWR instruction but by a TLBWI instruction Random entries can be overwritten by both instructions Figure 3 6 Positions Indicated by the Wired Register TLB BM 31 Range specified by the Random register I 4 Value in the Wired register Range of Wired entries Lp gt 0 The Wired r
81. 3 MEMWID4_REG 0x31 for Window 4 MWSTART A24 MWSTART A23 MWSTART A22 MWSTART A21 MWSTART A20 R W RW R W R W R W R W DWIDTH 0 0 8 bits 1 16 bits 0 0 Memory window data width 0 0 0 0 Doesn ot request 1 Requests Zero wait state enable This bit is used to set whether the zero wait state is requested to the ISA Bridge in memory accesses MWSTARTA 25 20 Memory window start address bits 25 to 20 This register is used to set the memory window data width zero wait state enable and high order address bits used to determine the start address of a memory address window 344 User s Manual U14272EJ3VOUM CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 15 SYSMEMELnREG Index 0x12 0x1A 0x22 0x2A 0x32 Remark n 0to4 SYSMEMELOREG 0x12 for Window 0 SYSMEMEL1REG 0x14 for Window 1 SYSMEMEL2REG 0x22 for Window 2 SYSMEMELS3REG 0x24 for Window 3 SYSMEMELAREG 0x32 for Window 4 MWSTOPA 19 MWSTOPA 18 MWSTOPA 17 MWSTOPA 16 MWSTOPA 15 MWSTOPA 14 MWSTOPA 13 MWSTOPA 12 R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 Bit Name Function MWSTOPA 19 12 Memory window stop address bits 19 to 12 Low order address bits used to determine the stop address of a memory address window 17 4 46 MEMSELn REG Index
82. 3 2 Connection to external ROM x 16 devices The ADD 21 0 pins are connected to the address line ADD 21 0 inside the Vn4181 during DRAM accesses However during ROM or flash memory accesses they are connected to the address line ADD 22 1 inside the Vn4181 This allows providing a greater address space capacity for ROM or flash memory ROM address pin 32 Mbit ROM 2 Mbits x 16 64 Mbit ROM 4 Mbits x 16 VR4181 CPU core physical VR4181 pin CPU core physical address line address A21 ADD21 adr22 20 ADD20 adr21 ADD20 adr21 A19 ADD19 adr20 ADD19 adr20 A18 ADD18 adr19 ADD18 adr19 17 ADD17 adr18 ADD17 adr18 A16 ADD16 adr17 ADD16 adr17 A15 ADD15 adr16 ADD15 adr16 14 ADD14 adr15 ADD14 adr15 A13 ADD13 adr14 ADD13 adr14 12 ADD12 adr13 ADD12 adr13 11 ADD11 adr12 ADD11 adr12 A10 ADD10 adr11 ADD10 adr11 A9 ADD9 adr10 ADD9 adr10 8 ADD8 adr9 ADD8 adr9 ADD7 adr8 ADD7 adr8 A6 ADD6 adr7 ADD6 adr7 A5 ADD5 adr6 ADD5 adr6 A4 ADD4 adr5 ADD4 adr5 ADD3 adr4 ADD3 adr4 A2 ADD2 adr3 ADD2 adr3 A1 ADD1 adr2 ADD1 adr2 AO ADDO ADDO User s Manual U14272EJ3VOUM 119 CHAPTER 6 BUS CONTROL 6 3 3 Example of ROM connection 1 32 Mbit ordinary ROM ADD 20 0 ROMCSO DATA 15 0 2 64 Mbit ordinary ROM ADD 21 0 ROMCSO DATA 15 0 120 User s Manual U14272EJ3VOUM CHAPTE
83. 408 420 MPIUINTREGQ cct recte trt 185 MSYSINTTREG 2 idee dede 176 MSYSINT2REQ gn andati 181 N NMIREG n onn 178 operating 78 ordinary 114 120 125 PageHOoM 114 121 122 126 81266 0 cea 72 PageMask 4 24 22 2 1 72 palette beo 406 428 429 Parity Error register 2 2 11 87 37 te 47 138 2 eat at 31 47 57 117 PGSOBIA 269 Aie 268 did edid 268 271 amp eite ure 270 POCSTSTRA a 270 POSMODBDE deu identi 272 physical 0 92 amp M 52 50 CONNGCHON tinea 63 eie 63 66 Stal Shs M M 60 44 pipeline 31
84. 423 CHAPTER 21 LCD CONTROLLER 21 4 17 FHSTARTREG 0x0A00 0424 Reserved Reserved Bit 7 6 5 4 3 2 1 0 Name FLMHS7 FLMHS6 FLMHS5 FLMHS4 FLMHS3 FLMHS2 FLMHS1 FLMHSO Reserved 0 is returned when read FLMHS 7 0 X coordinate of the first FLM edge Set this register to a value one half of the first edge of FLM Reserved Reserved Bit 7 6 5 4 3 2 1 0 FLMHE7 FLMHE6 FLMHES FLMHE4 FLMHES FLMHE2 FLMHE1 FLMHEO R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 Reserved 0 is returned when read FLMHE 7 0 X coordinate of the second FLM edge Set this register to a value one half of the second edge of FLM 424 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 21 4 19 PWRCONREG1 0 0 00 0430 Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W R W R W R W R W R W R W 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Biason4 Biason3 Biason2 Biason1 Reserved 0 is returned when read Reserved Write 0 when write 0 is returned when read Biason 4 0 Frame at which the bias voltage is turned on Users Manual U14272EJ3VOUM 425 CHAPTER 21 LCD CONTROLLER Testmode 21 4 20 PWRCONREG2 0x0A00 0432 Reserved Reserved BiasCon R W R W R W R W 0 0 0 0 Bit 7 6 5 4 3 2 1 0 l Fon2 l Font 0 Vccon4 Vccon3 Vccon
85. After clearing the data lost interrupt request by setting the PADDLOSTINTR bit to 1 set the PADATSTART bit or PADSCANSTART bit of the PIUCNTREG register to restart the coordinate detection operation Once the data lost interrupt request is cleared the page in which the loss occurred becomes invalid If the valid data prior to the data loss is needed be sure to save the data that is being stored in the page buffer before clearing the data lost interrupt request 2 When the A D port scan has not been completed within the time set via PIUSTBLREG register Cause Same as cause of condition 1 Response After clearing the data lost interrupt request by setting the PADDLOSTINTR bit to 1 set the ADPSSTART bit of the PIUASCNREG register to restart the A D port scan operation Once the data lost interrupt request is cleared the page in which the loss occurred becomes invalid If the valid data prior to the data loss is needed be sure to save the data that is being stored in the page buffer before clearing the data lost interrupt request User s Manual U14272EJ3VOUM 299 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 3 When transfer of the next coordinate data starts while valid data for both pages remains in the buffer Cause This condition is caused when the data buffer contains two pages of valid data both the data buffer page 1 and data buffer page 0 interrupt requests have occurred but the valid data has not been processed If the A D co
86. CLKEN CLKSEL 2 0 CLKX1 CLKX2 CTS1 CTS2 DATA 15 0 DCD1 DCD2 DSR1 DSR2 DTR1 DTR2 FLM FPD 7 0 FRM GND AD GND 10 GND LOGIC GND OSC GND PLL GND TP GPIO 31 0 IOCS16 IORD IORDY IOWR IRDIN IRDOUT LCAS LCDCS Address Bus Analog Data Input Audio Input Audio Output Battery Inhibit Battery Interrupt Column Address Strobe Card Detect for CompactFlash Address Enable for CompactFlash Buffer Ready Busy Interrupt Request for CompactFlash Card Enable for CompactFlash Data Enable for CompactFlash Buffer Data Direction for CompactFlash Buffer I O is 16 bits for CompactFlash Read Strobe for CompactFlash Write Strobe for CompactFlash Output Enable for CompactFlash Register Memory Access for CompactFlash Reset for CompactFlash Status Change of CompactFlash Vcc Enable for CompactFlash Wait Input for CompactFlash Write Enable for CompactFlash Clock Enable for SDRAM Clock Select Clock Input Clear to Send Data Bus Data Carrier Detect Data Set Ready Data Terminal Ready First Line Clock for LCD Screen Data of LCD Clocked Serial Frame Ground for A D and D A Converter Ground for I O Ground for Logic Ground for Oscillator Ground for PLL Ground for Touch Panel General Purpose I O 16 bit Bus Sizing I O Read Ready Write IrDA Data Input IrDA Data Output Lower Column Address Strobe Chip Select for LCD
87. DRAM data RSTSW reset 192 10 4 Shutdown Control 2 ncc rz ice rece ice ce Ld oco fedt ee coz nece 193 10 41 HAETimer ShU tdOWri 2 asi rai ette zie pde RR ve Ege PEL eeepc ERA ame 193 10 4 2 Softwate shutdOWn 5 eU ER RA 193 104 3 BATTINE Sh tdOWn iecit eere deut terere dr HE Ue vob 193 10 5 Power on Control 1 194 10 5 1 Activation via Power Switch interrupt 195 10 5 2 Activation via CompactFlash interrupt 196 10 5 3 Activation via GPIO activation interrupt 1 1 197 10 5 4 Activation via DCD interrupt request 198 10 5 5 Activation via ElapsedTime RTC alarm interrupt request 200 10 6 DRAM Interface Control 201 10 6 1 Entering Hibernate mode EDO 201 10 6 2 Entering Hibernate mode 5 202 10 6 3 Exiting Hibernate mode EDO DRAM 2 nennen nennen nnne 203 10 6 4 Exiting Hibernate mode 5 2 22400000 00 204 10 6 5 Entering Suspend mode EDO D
88. Exception processing Virtual address where the most recent error occurred a wo pv Count Exception processing Timer count a EntryHi Memory management Higher half of TLB entry including ASID a Compare Exception processing Timer compare value Status Exception processing Status indication E Cause Exception processing Cause of last exception AR EPC Exception processing Exception Program Counter a PRId Memory management Processor revision identifier zs Config Memory management Configuration memory system modes specification N LLAddr 9 Memory management Physical address for self diagnostics eS WatchLo Exception processing Memory reference trap address low bits WatchHi Exception processing Memory reference trap address high bits 20 XContext Exception processing Pointer to kernel virtual PTE in 64 bit mode 21 to 25 Reserved for future use 26 Note2 Parity Error Exception processing Cache parity bits 27 Note2 Cache Error Exception processing Index and status of cache error 28 TagLo Memory management Lower half of cache tag 29 TagHi Memory management Higher half of cache tag 30 ErrorEPC Exception processing Error Exception Program Counter
89. GPIO2 CSI serial clock input GPIO1 CSI serial data output GPIOO 236 CSI serial data input User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU The second group GPIO 31 16 pins are capable of supporting the following types of functions e External ISA I O interface e External 16 bit bus sizing signal ROM chip select Serial interface channel 1 e General purpose input e General purpose output Remark GPIO 31 16 pins can not be used as interrupt wake up inputs The assignment of interface signals to particular GPIO pins is shown in the following table Table 13 2 Alternate Functions of GPIO 31 16 Pins GPIO pin Alternate signal Alternate signal Definition 1 GPIO31 DSR1 SIU1 DSR input GPIO30 DTR1 SIU1 output GPIO29 DCD1 SIU1 DCD input GPIO28 CTS1 5101 CTS input GPIO27 RTS1 SIU1 RTS output GPIO26 TxD1 SIU1 transmit data output GPIO25 RxD1 SIU1 receive data input 24 ROMCS2 ROM chip select for bank 2 GPIO23 ROMCS1 ROM chip select for bank 1 GPIO22 ROMCSO chip select for bank 0 GPIO21 RESET External ISA reset GPIO20 UBEst M External ISA upper byte enable or LCD modulation output GPIO19 IOCS16 External ISA I O 16 bit bus sizing GPIO18 IORDY External ISA I O channel ready GPIO17 IOWR External ISA I O write strobe GPIO16 IORD External ISA I O read
90. LCD Panel System bus ISA is LCD controller CompactFlash card 32 768 FT kHz pn 18 432 peaker MHz Ed Touch panel Ih 0 1 N IR RS 232 C Battery monitor module driver K LED 30 User s Manual U14272EJ3V0UM CHAPTER 1 INTRODUCTION 1 3 1 CPU core The Vn4181 integrates NEC Electronics Vr4110 CPU core supporting both the MIPS and MIPS16 instruction sets The Vn4181 supports the following pipeline clock PClock and internal bus clock TClock frequencies The PClock is set by attaching pull up or pull down resistors to the CLKSEL 2 0 pins The frequency of the TClock which is used in MBA bus is set by PMUDIVREG register in Power Management Unit Table 1 1 Supported PClock and TClock Frequencies PClock frequency TClock frequency 65 4 MHz 65 4 32 7 21 8 MHz 62 0 MHz 62 0 31 0 20 7 MHz 49 1 MHz 49 1 24 6 MHz The Vn4110 core of the Vn4181 includes 4 KB of instruction cache and 4 KB of data cache The Vn4110 core also supports the following power management modes e Fullspeed e Standby e Suspend e Hibernate Note Note Suspend mode is supported only when the internal LCD controller has been disabled or the LCD panel has been powered off 1 3 2 B
91. LCD controller also provides power on and power down sequence control for the LCD panel via the VPLCD and VPBIAS pins Power sequencing is provided to prevent latch up damage to the panel The LCD controller can be disabled to allow connection of an external LCDC with integrated frame buffer RAM such as NEC Electronics PD16661 When the internal LCD controller is disabled the SHCLK LOCLK VPLCD and VPBIAS pins are redefined as follows Table 1 5 Functions of LCD Interface Pins when LCD Controller Is Disabled Redefined function Default function LCDCS SHCLK MEMCS16 LOCLK VPGPIO1 VPLCD VPGPIOO VPBIAS 34 User s Manual U14272EJ3VOUM CHAPTER 1 INTRODUCTION 1 3 17 Wake up events The Vr4181 supports 4 power management modes Fullspeed Standby Suspend and Hibernate Of these modes Hibernate is the lowest power mode and results in the powering off of all system components including the 2 5 V logic in the Vn4181 The 4181 3 3 V logic which includes RTC PMU and non volatile registers remain powered during the Hibernate mode as does the system DRAM Software can configure the Vn4181 waking up from the Hibernate mode and returning to Fullspeed mode due to any one of the following events e Activation of the DCD1 pin e Activation of the POWER pin e RTC alarm e Activation of one of the GPIO 15 0 pins e Activation of the CF_BUSY pin CompactFlash interrupt request IREQ Remark Different from t
92. LED control register 0 0 00 024A LEDASTCREG LED auto stop time setting register 0 0 00 024C LEDINTREG LED interrupt register These registers are described in detail below User s Manual U14272EJ3VOUM 353 CHAPTER 18 LED CONTROL UNIT LED 18 2 1 LEDHTSREG 0 0 00 0240 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Function Reserved 0 is returned when read HTS 4 0 LED ON time setting 11111 1 9375 seconds 10000 1 second 01000 0 5 seconds 00100 0 25 seconds 00010 0 125 seconds 00001 0 0625 seconds 00000 Prohibited Note A value before reset is retained This register is used to set the LED s ON time high level width of LEDOUT The ON time ranges from 0 0625 to 1 9375 seconds and can be set in 0 0625 second units The initial setting is 1 second This register must not be changed once the LEDENABLE bit of the LEDCNTREG register has been set to 1 The operation is not guaranteed if a change is made after that point 354 User s Manual U14272EJ3VOUM CHAPTER 18 LED CONTROL UNIT LED 18 2 2 LEDLTSREG 0 0 00 0242 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets Name Reserved R W RTCRST Other resets Function Reserved 0 is returned
93. Manual U14272EJ3VOUM 9 2 4 SOFTINTIREG OxQA00 009A tttm c tr ttt amete teet tec 179 9 2 5 SYSINT2REG 0x0A00 0200 1 35 x deseen e ibat Ae aE 180 9 2 6 MSYSINT2REG 0x0A00 0206 tenens 181 9 2 7 0 0 00 0082 rre dece cote e eed 182 9 2 8 0 0 00 0084 itis cdi eae tede erre a a dx td eee eee 183 9 29 KIUINTREG 0x0OBOO 0086 us cctv nace D See das i eal tend 184 9 2 10 MPIUINTREG 0 0 00 008 185 9 2 11 0 0 00 0090 2 186 9 22 MKIUINTREG 0x0B00 0092 2 187 CHAPTER 10 POWER MANAGEMENT UNIT PMU 22222 1 1 1 188 101 Genera e 188 10 2 Vn4181 Power 188 10 2 1 Power mode state 188 10 3 Reset Control 191 10 83 14 BTG reS6l i aei citet o a e si re c a 191 1032 RSTSW reset ueber iau diu 192 10 3 3 Deadman s Switch reset nee eere pe oe een etn Ra 192 10 3 4 Preserving
94. Note 3 Note 1 CF_WAIT SCANIN5S CF_IOIS16 SCANIN4 CF_VCCEN SCANIN3 Note 4 Note 1 CF_DEN SCANIN2 1 Note 1 CF_DIR SCANIN1 1 Note 1 CF_AEN SCANINO Notes1 2 When CF wake up is enabled Outputs high level Maintains the state of the previous Fullspeed mode When CF wake up is disabled Becomes high impedance 3 When CF wake up is enabled Outputs low level When CF wake up is disabled Becomes high impedance 4 When CF wake up is enabled Outputs low level When CF wake up is disabled Outputs high level Remark 0 low level 1 high level Hi Z high impedance User s Manual U14272EJ3VOUM 1 Note 1 61 CHAPTER 2 PIN FUNCTIONS Signal Name RxD1 GPIO25 During RTC Reset After RTC Reset After Reset by Deadman s Switch or RSTSW During Suspend Mode 3 3 During Hibernate Mode or Shutdown by HALTimer Note 1 Note 2 TxD1 GPIO26 CLKSELO Note 1 Note 2 RTS1 GP1027 CLKSEL1 Note 1 Note 2 CTS1 GP1028 Note 1 Note 2 DCD1 GP1029 DTR1 GP1030 CLKSEL2 Note 1 Note 2 Note 1 Note 2 DSR1 GPIO31 IRDIN RxD2 Note 1 Note 2 IRDOUT TxD2 Note 1 Hi Z GPIO 15 14 FPD 7 6 CD 2 1 Note 1 0 Note 1 Note 2 Note 1 GPIO 13 12 FPD 5 4 Note 1 0 Note 2 Note 1 GPIO11 PCS13 Note 1 1 Note 2 Hi Z GPIO10 FRM SYSCLK Note 1 0 Note 2 Note 1 Hi Z GPIO9 CTS2 Note 1
95. Once an interrupt request is generated writing to the VIReq bit clears the interrupt request However the state of the VIReq bit changes to 0 only after the controller returns to top left corner Note that there is some delay between the controller s entering or leaving the vertical blank and the changes in the VIReq bit 21 3 2 Controller clocks All LCD controller timing is based on the internal clock hpck The hpck is derived from the gclk which is derived from the MBA clock TClock The frequency of gclk can be equal to one half of or one quarter of that of the MBA clock depending on the Pre scal 1 0 bits of the LCDCFGREGO register and the MBA clock frequency The hpck frequency is programmable In each cycle the hpck is at high level for cycles set in the HpckH 5 0 bits of the LCDCFGREG1 register and at low level for cycles set in the HpckL 5 0 bits of the LCDCFGREG1 register The values in HpckH and HpckL fields are not arbitrary Their sum must be at least 5 and the following condition must be satisfied f hpck Htotal x Vtotal x f refresh Both the hpck and the gclk can be turned off when the panel is inactive Setting the ContCkE bit of the LCDCTRLREG register to 1 initializes the LCD controller and turns on both clocks or 0 turns them off User s Manual U14272EJ3VOUM 405 CHAPTER 21 LCD CONTROLLER 21 3 3 Palette The Col 1 0 bits of the LCDCFGREGO register indicate the desired color depth If they are set to 0 then
96. PCS1DSIZE PCS1MD1 PCS1MDO PCSOMIOB PCSODSIZE PCSOMD1 PCSOMDO R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Bit Name Function 15108 Reserved PCS1MIOB 0 is returned when read Programmable chip select 1 target cycle 0 Enabled only during cycles 1 Enabled only during memory cycles PCS1DSIZE Programmable chip select 1 data size 0 Defined as an 8 bit device During accesses to the address range specified for PCS1 8 bit cycles will be generated unless MEMCS16 or IOCS16 is asserted 1 Defined as a 16 bit device During accesses to the address range specified for PCS1 16 bit cycles will be generated PCS1MD 1 0 Programmable chip select 1 mode 00 Disabled 01 Qualified also with I O or memory read strobe 10 Qualified also with I O or memory write strobe 11 Based on address decode only PCSOMIOB Programmable chip select 0 target cycle 0 Enabled only during I O cycles 1 Enabled only during memory cycles PCSODSIZE Programmable chip select 0 data size 0 Defined as an 8 bit device During accesses to the address range specified for PCSO 8 bit cycles will be generated unless MEMCS16 or IOCS16 is asserted 1 Defined as a 16 bit device During accesses to the address range specified for PCSO 16 bit cycles will be generated PCSOMD 1 0 Note Holds the value before reset 272 Prog
97. PIUABOREG PIUAB1REG PIUAB2REG PIUAB3REG 0x0B00 02B0 0x0B00 02B2 0x0B00 02B4 0x0B00 02 6 Reserved Reserved Reserved Reserved Reserved PADDATAY PADDATA8 amp R W RTCRST Other resets Name PADDATA7 PADDATA6 PADDATAS PADDATA4 PADDATA3 PADDATA2 PADDATA1 PADDATAO R W RTCRST Other resets Bit Name Function Indicates validity of data in buffer 1 Valid 0 Invalid 14 to 10 Reserved 0 is returned when read 9100 PADDATA 9 0 A D converter s sampling data These registers are used to store sampling data of the general purpose A D port and audio input port or command scan data There are four data buffers and the addresses register address where the data is stored are fixed The VALID bit which indicates whether the data is valid is automatically rendered invalid when the page buffer interrupt source the PADADPINTR bit in the PIUINTREG register is cleared Table 14 6 shows correspondences between the sampled data and the register in which the sampled data is stored Table 14 6 A D Ports and Data Buffers Register During ADPScan During CMDScan TPPSCAN 0 TPPSCAN 1 PIUABOREG ADINO CMDScan data PIUAB1REG ADIN1 PIUAB2REG ADIN2 PIUABSREG AUDIOIN 294 User s Manual U14272EJ3VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 4 State Transition Flow Be sure to initialize the PIU before scan
98. PIUPWR 0 PIUPWR 1 PIUSEQEN 0 ADPSSTART ADPScan PIUSEQEN 1 amp ADPSSTART 1 Release amp ADPSSTART PADATSTOR auto timeout PIUSEQEN 0 21 DataScan PIUSEQEN 1 amp PADATSTART PIUSEQEN 1 amp PIUMODE 01 Rele se PIUSEQEN 1 amp PADSCANSTART 1 PIUSEQEN 0 PIUSEQEN 0 or PADSCANSTOP 1 278 User s Manual U14272EJ3VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU Disable state In this state the A D converter is in standby status the output pins are in touch detection status no PIU interrupt and the input pins are in mask status to prevent misoperation when an undefined input is applied Standby state In this state the PIU is in scan idle status The touch panel is in low power status 0 V voltage is applied to the touch panel and the A D converter is in disable status Normally this is the state in which various mode settings are made Caution Since a state transition occurs when the PIUSEQEN bit is active the PIUSEQEN bit must be set as active after various mode settings have been completed ADPScan state This is the state in which voltage is measured at the A D converter s three general purpose ports and one audio input port After the A D converter is activated and voltage data is obtained the data is stored in the PIU s internal data buffer PIUABnREG n 0 to 3 After the four ports are scanned an A D port sc
99. Power Supply for I O Power Supply for Logic Power Supply for Oscillator Power Supply for PLL Power Supply for Touch Panel Bias Power Control for LCD General Purpose Output for LCD Panel Power Control Logic Power Control for LCD 51 CHAPTER 2 PIN FUNCTIONS 2 2 Pin Function Description Remark indicates active low 2 2 1 System bus interface signals 1 2 Signal name Description of function Note ADD 21 0 Output Address bus Used to specify address for the DRAM ROM flash memory or system bus ISA DATA 15 0 Data bus Used to transmit and receive data between the 4181 DRAM ROM flash memory or system bus IORD GPIO16 System bus I O read signal output or general purpose It is active when the 4181 accesses the system bus to read data from an I O port when configured as IORD IOWR GPIO17 System bus I O write signal output or general purpose I O It is active when the 4181 accesses the system bus to write data to an I O port when configured as IOWR IORDY GPIO18 System bus I O channel ready input or general purpose I O Set this signal as active when system bus controller is ready to be accessed by the 4181 when configured as IORDY IOCS1642 GPIO19 Bus sizing request input for system bus or general purpose Set this signal as active when system bus I O accesses data in 16 bit width if configured as 516 UBEZ GPIO20 M System bus u
100. RSTSW Reset O c eee RSTSW Input POWER Input L MPOWER Output H p ColdReset Internal 774 144 Reset Internal 72227101 27 F Stable oscillation Stable oscillation eene ULLAL naerine 4 gt 4 5 gt 3RTC 16ms a4 pl 16MasterClock ete RTC Internal 32 768 kHz Stable oscillation Note MasterClock is the basic clock used in the CPU core Its frequency is one forth of TClock frequency 98 User s Manual U14272EJ3VOUM CHAPTER 5 INITIALIZATION INTERFACE 5 1 3 Deadman s Switch reset After the Deadman s Switch unit is enabled if the Deadman s Switch is not cleared within the specified time period the 4181 immediately enters to reset status Setting and clearing of the Deadman s Switch is performed by software A Deadman s Switch reset initializes the entire internal state except for the RTC timer the GIU and the PMU Since the DRAM is not switched to self refresh mode the contents of DRAM after a Deadman s Switch reset are not at all guaranteed After a reset the processor becomes the system bus master which executes a Cold Reset exception sequence and begins to access the reset vectors in the ROM space Since only part of the internal status is reset when a reset occurs in the VR4181 the processor should be completely initialized by software see 5 4 Notes on Initialization Figure 5 3 Deadman s Switch
101. Remark indicates active low LDQM LEDOUT LOCLK M MEMCS16 MEMRD MEMWR MIPS16EN MPOWER PCS 1 0 POWERON RAS 1 0 RESET ROMCS 3 0 RSTSW RTCRST RTCX1 RTCX2 RTS1 RTS2 RxD1 RxD2 SCANIN 7 0 SCANOUT 7 0 5 SDCLK SDCS 1 0 SDRAS SHCLK SI SO SYSCLK SYSDIR SYSEN TPX 1 0 TPY 1 0 TxD1 TxD2 UBE UCAS UDQM VDD AD VDD IO VDD LOGIC VDD OSC VDD PLL VDD TP VPBIAS VPGPIO 1 0 VPLCD User s Manual U14272EJ3VOUM Lower Byte Enable for SDRAM LED Output Load Clock for LCD LCD Modulation Clock Memory 16 bit Bus Sizing Memory Read Memory Write MIPS16 Enable Main Power Programmable Chip Select Power Switch Power On State Row Address Strobe for DRAM Reset Output Chip Select for ROM Reset Switch Real time Clock Reset Real time Clock Input Request to Send Receive Data Scan Data Input Scan Data Output CSI Clocked Serial Interface Clock Operation Clock for SDRAM Chip Select for SDRAM Row Address Strobe for SDRAM Shift Clock for LCD Clocked Serial Data Input Clocked Serial Data Output System Clock for System Bus System Data Direction System Data Enable Touch Panel Data of X Touch Panel Data of Y Transmit Data Upper Byte Enable for System Bus Upper Column Address Strobe for DRAM Upper Byte Enable for SDRAM Power Supply for A D and D A Converter
102. Speaker source 1 address registers sesssssssssssssssseeeeeeeeeneeen nennen nene 147 7 2 4 Speaker source 2 address registers essssssssssssseeeeeeeeeeeeneeen eren 148 7 2 5 DMARSTREG 0x0A00 0040 149 7 2 6 AIUDMAMSKREG 0x0A00 0046 ssssssseeseeeeeeneeeneeeneeennen nennen nnne trennt nnne nnne 149 7 2 7 MICRCLENREG 0 0 00 0658 neret neret nenne nennen 150 7 2 8 0 0 00 0654 cider eo ce Ete ee ced 150 7 2 9 MICDMACFGREG 0x0A00 065E itr errie ae an REEE oa rai Aa EE iae 151 7 2 10 SPKDMACFGREG 0 0 00 0660 2240222440 4 1 00000 152 7 211 DMAITRQREG 0 0 00 0662 13 2 ioi ceteri te cen reticere deri Race e 153 7 2 12 DMACTLREG 0x0A00 0664 240 222 2 0000 0000 10 154 7 2 13 DMAITMKREG 0x0A00 0666 02 24 20 4 50000 155 CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT 6 2 2 2 22 156 Mou v 156 8 2 Operation of CSM iue due ueteres ied tiic eic 156 8 21 Transmit recelve operationis n ei dea Brera Pei 156 8 2 2 SCK phase and CSI transfer timing ssssssseeeeeeeeeeneeenee nennen enn
103. Speaker source 1 address registers 1 SPKRSRC1REG1 0x0A00 0028 Name SS1A15 SS1A14 SS1A13 SS1A12 SS1A11 SS1A10 SS1A9 SS1A8 R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 Name R W At reset SS1A 15 0 Lower 16 bits A 15 0 of DMA source 1 address for Speaker 2 SPKRSRC1REG2 0x0A00 002A Name SS1A31 SS1A30 SS1A29 SS1A28 SS1A27 SS1A26 SS1A25 551 24 R W At reset Name SS1A23 SS1A22 SS1A21 SS1A20 SS1A18 SS1A17 SS1A16 R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 SS1A 31 16 Upper 16 bits A 31 16 of DMA source 1 address for Speaker These two registers specify the source memory address of the primary DMA buffer for the Speaker channel User s Manual U14272EJ3VOUM 147 CHAPTER 7 DMA CONTROL UNIT DCU 7 2 4 Speaker source 2 address registers 1 SPKRSRC2REG1 0x0A00 002C Name SS2A15 SS2A14 SS2A13 SS2A12 SS2A11 SS2A10 SS2A9 SS2A8 R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 Name R W At reset SS2A 15 0 Lower 16 bits A 15 0 of DMA source 2 address for Speaker 2 SPKRSRC2REG2 0x0A00 002E Name SS2A31 SS2A30 SS2A29 SS2A28 SS2A27 SS2A26 SS2A25 SS2A24 R W At reset Name 552 23 552 22 552 21 SS
104. TLBWR Source The confirmation of a source register of these instructions and registers used to specify a TLB entry Destination The completion of writing to TLB by these instructions TLBP Source The confirmation of the PageMask register and the EntryHi register before the execution of TLBP Destination The completion of writing the result of execution of TLBP to the Index register ERET Source The confirmation of registers containing information necessary for executing ERET Destination The completion of the processor state transition by the execution of ERET CACHE Index Load Tag Destination The completion of writing the results of execution of this instruction to the related registers User s Manual U14272EJ3VOUM 433 CHAPTER 23 COPROCESSOR 0 HAZARDS 8 CACHE Index Store Tag Source The confirmation of registers containing information necessary for executing this instruction 9 Coprocessor usable test Source The confirmation of modes set by the bits of the CPO registers in the Source column Examples 1 After the contents of the CUO bit of the Status register are modified when accessing the registers in User mode or when executing an instruction such as TLB instructions CACHE instructions or branch instructions that use the resource of the CPO 2 When accessing the CPO registers in the operating mode set in the Status register after the KSU EXL and ERL bits of the Status register are mod
105. UNIT 11 2 3 RTCLongl registers 1 RTCL1LREG 0x0B00 0000 Name RTCL1P15 RTCL1P14 RTCL1P13 RTCL1P12 RTCL1P11 RTCL1P10 RTCL1P9 RTCL1P8 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Name RTCL1P7 RTCL1P6 RTCL1P5 RTCL1P4 RTCL1P3 RTCL1P2 RTCL1P1 RTCL1PO R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 15 to 0 RTCL1P 15 0 Note Holds the value before reset Bits 15 to 0 for RTCLong1 timer count cycle User s Manual U14272EJ3VOUM 221 CHAPTER 11 REALTIME CLOCK UNIT 2 RTCL1HREG 0x0B00 0002 Name Reserved Reserved R W RTCRST Other resets RTCL1P23 RTCL1P22 RTCL1P21 RTCL1P20 RTCL1P19 RTCL1P18 RTCL1P17 RTCL1P16 R W R W R W R W R W R W R W R W RTCRST Other resets Function Reserved 0 is returned when read RTCL1P 23 16 Bits 23 to 16 for RTCLong1 timer count cycle Note Holds the value before reset Use these registers to set the RTCLong1 timer count cycle RTCLong1 timer begins its countdown at the value written to these registers A write operation is valid once values have been written to both registers RTCL1LREG and RTCL1HREG When setting these registers again wait until at least 100 us three
106. W R W R W R W R W R W R W R W RTCRST Other resets GISTS7 GISTS6 GISTS5 GISTS4 GISTS3 GISTS2 GISTS1 GISTSO RTCRST R W R W R W R W R W R W R W R W Other resets GISTS 15 0 Note Holds the value before reset Function GPIO interrupt request status There is a one to one correspondence between these bits and GPIO pins When a GPIO pin is defined as a general purpose input these bits reflect the interrupt request status as follows 0 No Interrupt request pending 1 Interrupt request pending Interrupt request pending status is reflected regardless of the setting of the interrupt mask bits Therefore the status of an interrupt request can be returned as pending when this register is read even though the interrupt is masked When a GPIO interrupt request is defined as an edge triggered type the interrupt request is cleared by writing 1 to the corresponding bit of this register For example if GPIO11 is defined as an edge triggered interrupt request input an interrupt request generated by this pin would be cleared by writing 1 to the bit 11 of this register 262 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 12 GPHIBSTH 0 0 00 0316 Name GPHST31 GPHST30 GPHST29 GPHST28 GPHST27 GPHST26 5 25 GPHST24 R W R W R W R W R W R W R W R W R W RTCRST Oth
107. Write back cache for reducing store operation that use the system bus e 32 bit physical address space and 40 bit virtual address space and 32 double entry TLB e Instruction set MIPS III with the FPU LL and SC instructions left out MIPS16 Supports MADD16 and DMADD16 instructions for executing a multiply and accumulate operation of 16 bit data x 16 bit data 64 bit data within one clock cycle e Effective power management features which include four operating modes Fullspeed Standby Suspend and Hibernate mode On chip PLL and clock generator DRAM interface supporting 16 bit width SDRAM and EDO DRAM e Ordinary ROM PageROM flash memory interface e UMA based LCD controller e 4 channel DMA controller e RTC unit including 3 channel timers and counters e Two UART compatible serial interfaces and one clocked serial interface e IrDA SIR interface e Keyboard scan interface supporting 8 x 8 key matrix e X Y auto scan touch panel interface e CompactFlash interface compatible with EXCA e A D and D A converters e Includes ISA subset bus Supply voltage 2 5 V for CPU core 3 3 V for I O e Package 160 pin LQFP User s Manual U14272EJ3VOUM 29 CHAPTER 1 INTRODUCTION 1 2 Ordering Information Part number Package Maximum internal operating frequency u PD30181GM 66 8bED 1 3 Vn4181 Key Features 160 pin plastic LQFP fine pitch 24 x 24 Figure 1 1 Internal Block Diagram 66 MHz
108. are valid only during the ADPScan state User s Manual U14272EJ3VOUM 291 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 3 8 PIUCIVLREG 0 0 00 013E Reserved Reserved Reserved Reserved Reserved INTVAL10 CHECK INTVAL9 CHECK INTVAL8 RTCRST Other resets Name CHECK CHECK CHECK CHECK CHECK CHECK CHECK CHECK INTVAL7 INTVAL6 INTVAL5 INTVAL4 INTVAL3 INTVAL2 INTVAL1 INTVALO R W R R R R R R R R RTCRST 1 0 1 0 0 0 0 0 Other resets 1 0 1 0 0 0 0 0 15 to 11 Reserved 0 is returned when read Function 10100 CHECKINTVAL 10 0 Interval count value This register indicates the value of an internal register that counts down based on the PIUSIVLREG register setting 292 User s Manual U14272EJ3VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 3 9 PIUPBnmREG 0 0 00 02A0 to 0x0B00 02 0x0B00 02BC to 0x0B00 02BE Remark Name n 0 1 0104 PIUPBOOREG 0 0 00 02A0 PIUPBO1REG 0 0 00 02A2 PIUPBO2REG 0 0 00 02 4 PIUPBOSREG 0 0 00 02A6 PIUPBO4REG 0 0 00 02BC Reserved Reserved PIUPB10REG PIUPB11REG PIUPB12REG PIUPB13REG PIUPB14REG Reserved 0 0 00 02A8 0x0B00 02 0x0B00 02 0x0B00 02 0 0 00 02BE Reserved Reserved PADDATA9 PADDATA8 R W RTCRST Other resets Name PADDATA7 PADDATA6 PADDATAS PADDATA4 PA
109. as dirty and therefore writable This bit is actually a write protect bit that software can use to prevent alteration of data V Valid lf this bit is set to 1 it indicates that the TLB entry is valid otherwise a TLB Invalid exception TLBL or TLBS occurs G Global If this bit is set in both EntryLoO and EntryLo1 then the processor ignores the ASID during TLB lookup 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read The coherency attribute C bits are used to specify whether to use the cache in referencing a page When the cache is used whether the page attribute is cached or uncached is selected by algorithm Table 3 2 lists the page attributes selected according to the value in the C bits 70 User s Manual U14272EJ3VOUM CHAPTER 3 REGISTERS Table 3 2 Cache Algorithm C bit value Cache algorithm Cached Cached Uncached Cached Cached Cached Cached Cached 3 2 4 Context register 4 The Context register is a read write register containing the pointer to an entry in the page table entry PTE array on the memory this array is a table that stores virtual to physical address translations When there is a TLB miss the operating system loads the unsuccessfully translated entry from the PTE array to the TLB The Context register is used by the TLB Refill exception handler for loading TLB entries The Context register dupl
110. bus space ce 93 4 2 3 Internal l O SpaCce 5 o en 94 424 DRAM ee etat utere tele e ede dedu 95 14 User s Manual U14272EJ3VOUM CHAPTER 5 INITIALIZATION INTERFACE eene 96 5 1 Reset EUnclloh rere ied eene eene rtis 96 Slit RG POSCL IP EE M 97 5 2 HSTSW tesel x ERR RE ERE e ROTER ERREUR 98 5313 Deadman s Switch reset ext Dedi dedo i e ite d tU DER e ce edi e e pd 99 51 4 Software Sh tdOWR RR ECRIRE RM RR REUNIR ARAS 100 Sko HAL Timer shutdown REI eoru ne 101 5 2 Power on Sequence e ere rette eese ENa aaaea 102 5 3 Reset of CPU Core 5 aio aade aart uta sese cos sacr dave cL aa seca esae 104 5 3 1 Gold Reset needed e e eben e ede ubi eR lee Ru es 104 5 3 2 508 us noa eee edo e otn be ete fotos dde S Teide 105 5 4 Notes on Initialization 1 106 5 4 1 GPU COPE ea etu tenis A 106 5 4 2 Internal peripheral nit 5 ee EP E CHR 106 5 4 3 Returning from power 107 CHAPTER 6 BUS CONTROL tace ee race ct aac er vedo ce ce Xd appe AEAEE 108 6 1 MBA Host Bridge
111. contents of these registers are undefined after a reset Figure 3 25 TagLo Register a When used with data cache 31 10 9 8 6 0 7 p a 45 4 b When used with instruction cache 31 109 8 0 mw PTagLo Specifies physical address bits 31 to 10 V Valid bit D Dirty bit However this bit is defined only for the compatibility with the VR4000 Series processors and does not indicate the status of cache memory in spite of its readability and writability This bit cannot change the status of cache memory W Writeback bit set if cache line has been updated 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read Figure 3 26 TagHi Register 31 0 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read 88 User s Manual U14272EJ3VOUM CHAPTER 3 REGISTERS 3 2 22 ErrorEPC register 30 The Error Exception Program Counter ErrorEPC register is similar to the EPC register It is used to store the Program Counter value at which the Cold Reset Soft Reset or NMI exception has been serviced The read write ErrorEPC register contains the virtual address at which instruction processing can resume after servicing an error The contents of this register change depending on whether execution of MIPS16 instructions is enabled or disabled Setting the MIPS16EN pin after RTC reset specifies whether the execution of MIPS16 instru
112. depending on the panel data width as below For details refer to CHAPTER 21 LCD CONTROLLER 4181 LCD Panel Data 4 bit width LCD Panel Data 8 bit width Data Line 0 Data Line 4 Data Line 1 Data Line 5 Data Line 2 Data Line 6 Data Line 3 Data Line 7 Data Line 0 Data Line 1 Data Line 2 54 Data Line 3 User s Manual U14272EJ3VOUM CHAPTER 2 PIN FUNCTIONS 2 2 3 Initialization interface signals Signal name Description of function POWER Vr4181 activation signal RSTSW Vn4181 reset signal RTCRST Reset signal for internal Real time clock and internal logic When power is first supplied to the system the external agent must activate this signal POWERON This signal indicates that the Vr4181 is ready to operate It becomes active when power on factor is detected and becomes inactive when the BATTINH BATTINT signal check has been completed MPOWER This signal indicates that the Vn4181 is operating This signal is inactive during Hibernate mode During this signal being inactive turn off the 2 5 V power supply 2 2 4 Battery monitor interface signals Signal name Description of function BATTINH BATTINT The function of this pin differs depending on the state of the MPOWER pin lt When MPOWER 0 gt BATTINH signal Enables or disables activation on power application 1 Enable activation 0 Disable activation lt When MPOWER 1 gt
113. described in detail below RTC interrupt register User s Manual U14272EJ3VOUM CHAPTER 11 REALTIME CLOCK UNIT 11 2 1 ElapsedTime registers 1 ETIMELREG 0x0B00 00CO Name ETIME15 ETIME14 ETIME13 ETIME12 ETIME11 ETIME10 ETIME9 ETIME8 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Name ETIME7 ETIME6 ETIMES ETIME4 2 1 ETIMEO R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 15100 15 0 Note Continues counting 2 ETIMEMREG 0 0 00 00C2 Name ETIMES1 ETIMESO ElapsedTime timer bits 15 to 0 ETIME29 ETIME28 ETIME27 ETIME26 ETIME25 ETIME24 R W R W R W R W R W R W R W R W R W RTCRST Other resets Name ETIME23 ETIME22 ETIME21 ETIME20 ETIME19 ETIME18 ETIME17 ETIME16 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 15100 ETIME 31 16 Note Continues counting ElapsedTime timer bits 31 to 16 Users Manual U14272EJ3VOUM 217 CHAPTER 11 REALTIME CLOCK UNIT 3 ETIMEHREG 0 0 00 00C4 Name ETIME47 ETIME46 ETIME45 ETIME44 ETIME43 ETIME42 ETIME41 ETIME40 R W R W R W R W R W R W R W R W R W RTCRST Other resets ETIME39 ETIME38 ETIME37 ETIME36 ETIME35 ETIME34 ET
114. disables the use of the coprocessor 1 Enabled 0 Disabled can be used in Kernel mode at all times RE Enables disables reversing of the endian setting in User mode 0 Disabled 1 Enabled This bit must be set to 0 since the Vn4181 supports the little endian order only DS Diagnostic Status field see Figure 3 13 IM Interrupt mask field used to enable disable interrupts 0 Disabled 1 Enabled This field consists of 8 bits that are used to control eight interrupts The bits are assigned to interrupts as follows Masks a timer interrupt IM 6 2 Mask ordinary interrupts Int 4 0 However Int 4 3 IM 1 0 Mask software interrupts Note never occur in the Vn4181 Note Int 4 0 are internal signals of the VR4110 CPU core For details about connection to the on chip peripheral units refer to CHAPTER 9 INTERRUPT CONTROL UNIT ICU 76 User s Manual U14272EJ3VOUM CHAPTER 3 REGISTERS Figure 3 12 Status Register 2 2 KX SX UX KSU ERL EXL Enables 64 bit addressing in Kernel mode 0 32 bit 1 64 bit 64 bit operations are always valid in Kernel mode Enables 64 bit addressing and operation in Supervisor mode 0 32 bit 1 64 bit Enables 64 bit addressing and operation User mode 0 32 bit 1 64 bit Sets and indicates the operating mode 10 User 01 Supervisor 00 Kernel Sets and indicates the e
115. enable 0 Disable 1 Enable Remark When using the receive function only communication must be performed with the TXEN bit 0 and the TXCLR bit 1 CSI receive burst mode 0 Continuous mode 1 Burst mode CSI receive buffer clear 0 Enable receive shift register and FIFO 1 Reset receive shift register and FIFO Users Manual U14272EJ3VOUM 161 CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 2 2 Function FRM mode 0 FRM controls transfer directions receive when 1 transmit when 0 1 FRM enables transfers transmit receive enabled when FRM 0 lote CSI clock polarity A 0 SCK is active high 1st transition is low to high 1 SCK is active low 1st transition is high to low Note CSI clocking mode 0 Character data is valid prior to the 1st transition of SCK 1 Character data is valid at the 1st transition of SCK Reserved 0 is returned after read LSBMSB Transmit receive mode bit ordering 0 Bit 7 is the first bit transmitted or received MSB mode 1 BitO is the first bit transmitted or received LSB mode Note The TXCLR and RXCLR bits must be cleared after changing the CKPOL or CKMD bit The CKPOL bit must be set as follows according to the state of SCK when a communication is not performed e When SCK is at low level during no communication CKPOL bit 0 e When SCK is at high level during no communication CKPOL bit 1 16
116. enabled Masks DMA for Microphone audio input channel SPKMSK 0 Speaker channel disabled 1 Speaker channel enabled Masks DMA for Speaker audio output channel Reserved 0 is returned after a read User s Manual U14272EJ3VOUM 149 CHAPTER 7 DMA CONTROL UNIT DCU 7 2 7 MICRCLENREG 0x0A00 0658 15 MICRL14 MICRL13 MICRL12 MICRL11 MICRL10 MICRL9 MICRL8 R W R W R W R W R W R W R W R W R W At reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 Name R W MICRL7 MICRL6 MICRL5 MICRL4 MICRL3 MICRL2 MICRL1 MICRLO At reset Name channel DMA Record Length for Microphone MICRLO bit must be written to zero This register defines the number of 16 bit words to be transferred during DMA operation in the Microphone 7 2 8 SPKRCLENREG 0x0A00 065A Name SPKRL15 SPKRL14 SPKRL13 SPKRL12 SPKRL10 SPKRL9 SPKRL8 R W At reset Name SPKRL7 SPKRL6 SPKRL5 SPKRL4 SPKRL3 SPKRL2 SPKRL1 SPKRLO R W R W R W R W R W R W R W R W R W At reset 1 1 1 1 1 1 1 1 15100 SPKRL 15 0 DMA Record Length for Speaker SPKRLO bit must be written to zero This register defines the number of 16 bit words to be transferred during DMA operation in the Spe
117. have assigned functions as follows e rO is hardwired to a value of zero and can be used as the target register for any instruction whose result is to be discarded 0 can also be used as a source when a zero value is needed e r31 is the link register used by link instructions such as JAL Jump and Link instruction This register can be used for other instructions However be careful that use of the register by a link instruction will not coincide with use of the register for other operations The register group is provided within the CPO to process exceptions and to manage addresses CPU registers can operate as either 32 bit or 64 bit registers depending on the 4181 processor mode of operation The operation of the CPU registers differs depending on what instructions are executed 32 bit instructions or MIPS16 instructions For details refer to 4100 Series Architecture User s Manual The 4181 has no Program Status Word PSW register as such this is covered by the Status and Cause registers incorporated within the CPO see 1 4 4 CPO registers Figure 1 3 shows the CPU registers Figure 1 3 CPU Registers General purpose registers 63 32 31 0 Multiply divide registers 63 32 31 0 H 63 32 31 0 L r29 Program Counter r30 63 32 31 0 r31 LinkAddress User s Manual U14272EJ3VOUM 37 CHAPTER 1 INTRODUCTION 1 4 2 CPU instruction set overview There are tw
118. in a write operation When this field is read 0 is read The processor revision number is stored as a value in the form y x where y is a major revision number in bits 7 to 4 and x is a minor revision number in bits 3 to O The processor revision number can distinguish CPU core revisions of the Vn4181 however there is no guarantee that changes to the CPU core will necessarily be reflected in the PRId register or that changes to the revision number necessarily reflect real CPU core changes Therefore create a program that does not depend on the processor revision number field 82 User s Manual U14272EJ3VOUM CHAPTER 3 REGISTERS 3 2 15 Config register 16 The Config register specifies various configuration options selected on the 4181 Some configuration options as defined by the EC and BE fields are set by the hardware during Cold Reset and are included in the Config register as read only status bits for the software to access Other configuration options AD EP and KO fields can be read written and controlled by software on Cold Reset these fields are undefined Since only a subset of the Vr4000 Series options are available in the VR4181 some bits are set to constants e g bits 14 and 13 that were variable in the 4000 Series The Config register should be initialized by software before caches are used The contents of the Config register are undefined after a reset so that it must be initialized by softw
119. is initialized 0x0200 by resetting the AIUSEN bit of the SEQREG register to 0 User s Manual U14272EJ3VOUM 303 CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 2 MDMADATREG 0 0 00 0162 Name Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Function 15to 10 Reserved 0 is returned when read 9100 MDMA 9 0 Microphone input DMA data This register is used prior to DMA transfer to store 10 bit data that has been converted by the A D converter and stored in the MIDATREG register Write is used for debugging and is enabled when the AIUMEN bit of the SEQREG register is set to 1 This register is initialized 0x0200 by resetting the AIUMEN bit of the SEQREG register to 0 Therefore if the AIUMEN bit is set to 0 during transfer invalid data may be transferred 304 User s Manual U14272EJ3VOUM CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 3 DAVREF SETUP 0 0 00 0164 Name DAVREF15 DAVREF14 DAVREF13 DAVREF12 DAVREF10 DAVREF9 DAVREF8 R W RTCRST Other resets RTCRST Other resets 15 to 0 DAVREF 15 0 D A converter Vref setup time This register is used to select a Vref setup time for the D A converter The following expression is used to calculate the value set to this register DAVREF 15 0 5 us x PCLK frequency For example if the internal peripheral c
120. mode control 10 2 Vn4181 Power Mode This section describes the Vn4181 power modes in detail The Vn4181 supports the following four power modes e Fullspeed mode e Standby mode e Suspend mode e Hibernate mode 10 2 1 Power mode and state transition 4181 transits from Fullspeed mode to Standby mode Suspend mode or Hibernate mode by executing a STANBY SUSPEND or HIBERNATE instruction respectively An RTC reset is always valid in every mode and initializes resets units in the 4181 including the RTC The figure on the following page Figure 10 1 is a conceptual diagram showing the interaction and control of the four power modes of the Vn4181 188 User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU Figure 10 1 Transition of Vn4181 Power Mode Standby mode Suspend mode Fullspeed mode Hibernate mode Transition No Factors STANDBY instruction All interrupt requests SUSPEND instruction After transition DRAM self refresh Assertion of POWER Assertion and then deassertion of RSTSW Interrupt request such as ElapsedTime timer Key press DCD1 5101 RTCLong1 Pen touch CF_BUSY RTCLong2 GPIO 15 0 BATTINTR HIBERNATE instruction After transition DRAM self refresh Deassertion of MPOWER Assertion of POWER Interrupt request such as ElapsedTime timer GPIO 15 0 DCD1 CF_BUSY Assertion of RTCRST lt After transition gt Deass
121. monochrome image can be displayed on a monochrome panel If they are set 1 then a 4 shade gray scale image can be displayed on a monochrome panel If they are set to 2 or 3 then a palette is enabled and a color panel can be used The palette has 256 entries Each entry has 18 bits and is 6 6 6 format for the RGB color To access an entry first store its index in the Pallndex 7 0 bits of the CPINDCTREG register then read from or write to the PalData 17 0 bits of the CPALDATREG register To accelerate continuous accesses the PalRDI bit or the PalWRI bit of the CPINDCTREG register can be set to 1 When the PalRDI bit is set to 1 the LCD controller automatically adds 1 to the Pallndex 7 0 bits of the CPINDCTREG register after reading from the PalData field when the PalWRI bit is set to 1 the LCD controller automatically adds 1 to the Pallndex 7 0 bits after writing to the PalData field If the Col field is set to 2 then the pixel data provides only the lower half of the palette index The upper half is provided by the PalPage 3 0 bits of the CPINDCTREG register Together they specify one entry in the palette Finally the hpck and the gclk must be turned on before the palette is accessed 21 3 4 Frame buffer memory and FIFO The frame buffer is linear and supports a packed pixel format The length of a scan line must be a multiple of 32 The last double word of a scan line need not be completely filled The pixels are stored in double words The
122. of these register bits to the scan operation Figure 16 1 SCANOUT Signal Output Timing TICNT 4 0 1 SCANOUTO output SCANOUT1 output 5 2 Hi Z Hi Z output 777777777777 PU OGNI Ns gid ee hs S ge Allee oe NS s Yi Hi Z Hi Z Oe a ICM DE SCANOUT4 Hi Z Hi Z output Ph og OO on KE SCANOUTS Hi Z Hi Z pd up d CIE DA eo SCANOUTe Hi Z Hi Z i 5 M Ter X c mero mS de ee Eee M I SCANOUT7 Hi Z output Ee Pg Ie ag a The T1CNT 4 0 bits specify the keyboard settling time and is expressed in 32 768 kHz clock cycles Following the low level of one of the SCANOUT 7 0 pins the KIU will wait for the time set in the T1CNT 4 0 bits before reading returned data to the SCANIN 7 0 pins Actually the SCANOUT pins will be driven as low for T1CNT 4 0 1 32 768 kHz clock cycles The T3CNT 4 0 bits specify the delay from driving one SCANOUT as high impedance to driving the next SCANOUT pin as low and is also expressed in 32 768 kHz clock cycles When the SCANOUTn pin is driven as high impedance the KIU will wait for the time set in the T3CNT 4 0 bits before driving the SCANOUTn 1 pin as low to allow the external pull up resistors to return the SCANINn pin as high n
123. priority level than the receive data ready interrupt When characters are transferred from the shift register to the receive FIFO 1 is set to the LSRO bit of the SIULS 1 register The value of this bit returns to 0 when the FIFO becomes empty When receive FIFO is enabled and receive interrupts are enabled receive FIFO timeout interrupt requests can occur as described below 1 Followings are the conditions under which FIFO timeout interrupt requests occur Atleast one character is being stored in the FIFO The time required for sending four characters has elapsed since the serial reception of the last character includes the time for the second stop bit in cases where it is specified that two stop bits are required The time required for sending four characters has elapsed since the last read of the FIFO by the CPU The time between receiving the last character and issuing a timeout interrupt request is a maximum of 160 ms when operating at 300 baud and receiving 12 bit data The transfer time for a character is calculated based on the baud rate clock for reception internal which is why the elapsed time is in proportion to the baud rate Once a timeout interrupt request has occurred the timeout interrupt is cleared and the timer is reset as soon as the CPU reads one character from the receive FIFO If no timeout interrupt request has occurred the timer is reset when a new character is received or when the CPU reads th
124. register appears on the GPIO pin When one of the GPIO 31 16 pins is configured as other function the corresponding bit value in this register is invalid Note Holds the value before reset 254 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 6 GPDATLREG 0x0B00 030A Name GPDAT15 GPDAT14 GPDAT13 GPDAT12 GPDAT11 GPDAT10 GPDAT9 GPDAT8 R W R W R W R W R W R W R W R W R W RTCRST Other resets GPDAT7 GPDAT6 GPDAT5 GPDAT4 GPDAT3 GPDAT2 GPDAT1 GPDATO R W R W R W R W R W R W R W R W RTCRST Other resets Function GPDAT 15 0 General purpose data There is a one to one correspondence between these bits and GPIO pins When a GPIO pin is configured as a general purpose input the value of the pin can be read from this register When the pin is defined as a general purpose output the value written to this register appears on the GPIO pin When one of the GPIO 15 0 pins is configured as other function the corresponding bit value in this register is invalid Note Holds the value before reset User s Manual U14272EJ3VOUM 255 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 7 GPINTEN 0 0 00 030C Name GIEN15 GIEN14 GIEN13 GIEN12 GIEN1 1 GIEN10 R W R W R W R W R W R W R W RTCRST Other resets RTCRST Other resets GIEN 15 0 Note Holds the value before rese
125. resets Function Reserved 0 is returned when read PADCMDINTR Enables PIU command scan interrupt 0 Disable 1 Enable PADADPINTR Enables PIU A D Port Scan interrupt 0 Disable 1 Enable PADPAGE1INTR Enables PIU data buffer page 1 interrupt 0 Disable 1 Enable PADPAGEOINTR Enables PIU data buffer page 0 interrupt 0 Disable 1 Enable PADDLOSTINTR Enables data loss interrupt 0 Disable 1 Enable Reserved 0 is returned when read PENCHGINTR Enables touch panel contact status change interrupt 0 Disable 1 Enable This register is used to mask various PIU related interrupts User s Manual U14272EJ3VOUM 185 CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 11 MAIUINTREG 0 0 00 0090 Name Reserved Reserved Reserved Reserved Reserved Reserved INTMIDLE INTMST R W RTCRST Other resets RTCRST Other resets Function 15 to 10 Reserved Write 0 when write 9 INTMIDLE Enables audio input microphone idle interrupt received data is lost 0 Disable 1 Enable INTMST Enables audio input microphone receive completion interrupt 0 Disable 1 Enable Reserved Write O when write INTSIDLE Enables audio output speaker idle interrupt mute 0 Disable 1 Enable Reserved Write O when write This register is used to mask various AIU related interrupts This register is a write only register and it
126. returns to Fullspeed mode if any interrupt request occurs 3 Suspend mode When the SUSPEND instruction has been executed the processor can be set to Suspend mode During Suspend mode the pipeline clock PClock in the CPU core is held at high level The VR4181 also stops supplying TClock and PCLK to peripheral units While in this mode the register and cache contents are retained Contents of DRAM can also be retained by putting DRAM into self refresh mode During Suspend mode the processor returns to Fullspeed mode if any of power on factors or some of interrupt requests occurs 4 Hibernate mode When the HIBERNATE instruction has been executed the processor can be set to Hibernate mode During Hibernate mode clocks other than the RTC clock 32 768 kHz are held at high level and the PLL stops While in this mode contents of the registers and caches are not retained Contents of DRAM can be retained by putting DRAM into self refresh mode Power consumption during Hibernate mode is about 0 W if power to 2 5 V power supply is not applied it does not go completely to 0 W due to the existence of a 32 768 kHz oscillator or on chip peripheral circuits that operate at 32 768 kHz During Hibernate mode the processor returns to Fullspeed mode if any of power on factors or some of interrupt requests occurs User s Manual U14272EJ3VOUM 45 CHAPTER 1 INTRODUCTION 1 4 10 Code compatibility The 4110 core is designed in consideration of t
127. serial input RxD2 to the receive block is cut off The transmit shift register s output is looped back to the receive shift register s input The four modem control inputs DSR2 CTS2 RI internal and DCD2 are cut off and the four modem control outputs DTR2 RTS2 OUT1 internal and OUT2 internal are internally connected to the corresponding modem control inputs The modem control output pins are forcibly set as inactive high level During this kind of loopback mode transmitted data can be immediately and directly received When in loopback mode both transmit and receive interrupts can be used The interrupt sources are external sources in relation to the transmit and receive blocks Although modem control interrupts can be used the low order four bits of the modem control register can be used instead of the four modem control inputs as interrupt sources As usual each interrupt is controlled by an interrupt enable register User s Manual U14272EJ3VOUM 391 CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 20 3 10 SIULS 2 0 0 00 0005 Name R W RTCRST Other resets Function Error detection FIFO mode 1 Parity error framing error or break is detected 0 No error Transmit block empty 1 No data in transmit holding register and transmit shift register No data in transmit FIFO during FIFO mode Data exists in transmit holding register or transmit shift register Data exists in
128. signal supports input only FPD7 CD2 GPIO31 User s Manual U14272EJ3VOUM DSR1 33 CHAPTER 1 INTRODUCTION 1 3 15 Programmable chip selects The 4181 provides support for 2 programmable chip selects PCS which are also available as general purpose pins Each PCS can decode either I O or memory accesses and can optionally be qualified to read write or both read and write 1 3 16 LCD interface The LCD controller of the 4181 is Unified Memory Architecture UMA based in which the frame buffer is part of system DRAM The LCD controller supports monochrome STN LCD panels having 4 bit data bus interfaces and color STN LCD panels having 8 bit data bus interface When interfacing to a color LCD panel general purpose pins must be allocated to provide the upper nibble of the 8 bit LCD data bus In monochrome mode the LCD controller supports 1 bpp mode mono 2 bpp mode 4 gray levels and 4 bpp mode 16 gray levels In color mode it supports 4 bpp mode 16 colors and 8 bpp mode 256 colors The LCD controller includes a 256 entry x 18 bit color pallet In 8 bpp color modes the pallet is used to select 256 colors out of possible 262 144 colors The LCD controller supports LCD panels of up to 320 x 320 pixels Typical LCD panel horizontal vertical resolutions are as follows Table 1 4 LCD Panel Resolutions in Pixels TYP Horizontal resolution Vertical resolution The
129. tg ete dade d ess 76 Status Register Diagnostic Status Field seessssssssssseeesseeeeeeee nennen nennen rens 77 GauseReglsler 79 EPC Register When MIPS16 ISA Is Disabled 22 22 4 1000 000000 nennen 81 EPC Register When MIPS16 ISA Is Enabled sssssseseeeeeeeeneennennneen nennen nnne nnne 82 PRId Reglster ee ER re eere cr e Dee i e eee oU ee a i 82 Config Register uere pa patr me Ue 83 bL Addr Fiegister I DR T 84 Watchl o Fteglstet 5 e e ir e TE ee EIE ee Meg e RECEN 85 Watch REGIStC MS mE 85 XGontextHRHegistet d RUD RR DRE ERR 86 Parity Error Reglster e Ld een e ed biben ERE oe 87 Cache Ettor Begister s c mc ot tc E tiet t D E Ded Et A 87 Taglo Register eR Ee LR e c P eda D eee rt ant 88 TagHi RegIStet ae had nd 88 ErrorEPC Register When MIPS16 ISA Is Disabled 2 90 ErrorEPC Register When MIPS16 ISA Is Enabled esses 90 VR438 t Physical Address Space 5 out RU 92 User s Manual U14272EJ3VOUM Fig
130. the PIU When the PENCHGINTR bit is set to1 the PENSTC bit of the PIUCNTREG register indicates the touch panel contact status touch or release when a contact status changes The PENSTC bit s status remains until the PENCHGINTR bit is cleared to 0 Also when the PENCHGINTR bit is cleared to 0 the PENSTC bit indicates the touch panel contact status However the PENSTC bit does not change while the PENCHGINTR bit is set to 1 even if the touch panel contact status changes between release and touch Caution Inthe Hibernate mode the Vn4181 retains the touch panel status Therefore if the Hibernate mode has been entered while the touch panel is touched the contact status may be mistakenly recognized as having changed when the Vn4181 returns to Fullspeed mode If a touch panel status change interrupt request occurs immediately after the Vn4181 returns from the Hibernate mode the PENCHGINTR bit may be set to 1 due to a miss recognition such as above Similarly other bits of the PIUINTREG register may be set to 1 on returning from the Hibernate mode Therefore set each bit of the PIUINTREG register to 1 to clear an interrupt request immediately after a restore from the Hibernate mode 14 3 3 PIUSIVLREG 0 0 00 0126 Name Reserved Reserved Reserved Reserved Reserved SCAN SCAN SCAN INTVAL10 INTVAL9 INTVAL8 R W RTCRST Other resets Name SCAN SCAN SCAN SCAN SCAN SCAN SCAN SCAN INTVAL7 INTVAL6 INTVAL5 INTVAL4 INTVAL3 INTVAL2 IN
131. the SIULS_2 register and SIUMS_2 register are valid To access this register set the LCR7 bit bit 7 of the SIULC 2 register to 0 382 User s Manual U14272EJ3VOUM CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 20 3 5 SIUDLM 2 0x0C00 0001 LCR7 1 Name DLM7 DLM6 DLM5 DLM4 DLM3 DLM2 DLM1 DLMO R W R W R W R W R W R W R W R W R W RTCRST Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Other resets Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Function Baud rate divisor high order byte This register is used to set the divisor division rate for the baud rate generator The data in this register and the data in SIUDLL_2 register as lower 8 bits are together handled as 16 bit data To access this register set the LCR7 bit bit 7 of the SIULC 2 register to 1 The relationship between baud rates and the settings of the SIUDLL 2 and SIUDLM 2 registers are as follows User s Manual U14272EJ3VOUM 383 CHAPTER 20 SERIAL INTERFACE UNIT 2 512 Table 20 2 Correspondence between Baud Rates and Divisors Baud rate bps Divisor 1 clock width us DLM 7 0 DLL 7 0 50 20000 00 75 13333 33 110 9090 91 134 5 7434 94 150 6666 67 300 3333 33 600 1666 67 1200 833 33 1800 555 56 2000 500 00 2400 416 67 3600 277 78 4800 208 33 7200 138 89 9600 104 17
132. the analog input microphone input processing of the internal A D converter It is also used to make settings related to the A D and D A converters The main functions of the AIU are as follows Holding the digital value converted by the internal A D converter Holding the digital value to be converted by the internal D A converter e Separating data being converted by the A D or D A converter and transfer data by using double buffers Linking the update of the double buffers and the generation of transfer requests with the data conversion rate Caution clocks are supplied to the AIU A D converter and D A converter in the initial state When using the AIU set the MSKAIUPCLK MSKADUPCLK and MSKADU18M bits of the CMUCLKMSK register in the MBA Host Bridge to 1 in advance so that clocks are supplied User s Manual U14272EJ3VOUM 301 CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 Register Set The AIU registers are listed below Physical address 0 0 00 0160 Table 15 1 Registers Register symbol SDMADATREG Function Speaker DMA data register 0 0 00 0162 0 0 00 0164 MDMADATREG DAVREF SETUP Microphone DMA data register D A converter Vref setup register 0 0 00 0166 SODATREG Speaker output data register 0 0 00 0168 SCNTREG Speaker output control register 0 0 00 016E SCNVC END Speaker sample rate control register 0 0 00 0170 MIDATREG
133. the deassertion of the Reset signal synchronized with the rising edge of MasterOut In general data in the CPU core is preserved for debugging purpose Upon reset the CPU core becomes bus master and drives the SysAD bus internal After Reset is deasserted the CPU core branches to the Reset exception vector and begins executing the reset exception code Figure 5 9 Soft Reset H MasterClockNete Internal Reset Internal N MasterOut Internal m Xu Aes Nu Note MasterClock is the basic clock used in the CPU core Its frequency is one forth of TClock frequency User s Manual U14272EJ3VOUM 105 CHAPTER 5 INITIALIZATION INTERFACE 5 4 Notes on Initialization This section explains the case in which manipulation by software is necessary after the Vn4181 has been reset When a Cold Reset sequence is executed the reset exception vector is accessed Perform manipulation described here by using the software handler for reset exceptions located at the reset exception vector 5 4 1 CPU core 1 Coprocessor 0 Be sure to initialize at least the following internal registers of the coprocessor 0 after the reset RSTSW reset or Deadman s Switch reset has been cleared or the Vn4181 has returned from the Hibernate mode Config register e Status register e WatchLo register 2 Cache tag The contents of the tag RAM of the cache are undefined immediately afte
134. the receive shift register goes full the data is automatically transferred to the receive FIFO When the transmit shift register goes empty it is automatically reloaded from the transmit FIFO Once the burst length has been set and the burst transaction enabled the CSI behaves as follows The CSI begins tracking the number of bits transmitted and or received At the end of each bit transfer the bit count is updated and compared to the corresponding burst length value transmit and or receive If the number of bits transferred is equal to the burst length the CSI shift register is halted If the transfer is a reception the contents of the shift register will be copied to the receive FIFO a Receive Burst End interrupt request will be generated if unmasked and additional activities on the SCK input will be ignored If the transfer is a transmission a Transmit Burst End interrupt request will be generated if unmasked and additional SCK cycles will cause an invalid data to be output on SO 2 Continuous mode Continuous mode transfers are always defined as 8 bit fixed length transfers In continuous mode software must control the flow of data between the Vn4181 and the external master When continuous mode is enabled and the receive shift register goes full the data is automatically transferred to the receive FIFO When the transmit shift register goes empty it is automatically reloaded from the transmit FIFO User s Manual U14272EJ3VOUM
135. to the ISA bridge after finishing an external ISA cycle and obtains results of the read Normally set 1 to this bit INTRESULT Internal ISA result cycle enable 0 Disabled The MBA bus arbiter waits until an internal ISA read is finished 1 Enabled The MBA bus arbiter issues a result cycle to the ISA bridge after finishing an internal ISA cycle and obtains results of the read Normally set 1 to this bit EXBUFFEN External buffer enable 0 Enable external buffer control with SYSDIR and SYSEN pins 1 Disable external buffer control with SYSDIR and SYSEN pins SYSEN and SYSDIR pins are both forced to low level MEMWS 1 0 External ISA memory wait states read write strobe width 00 1 5 SYSCLK cycles 01 2 5 SYSCLK cycles 10 3 5 SYSCLK cycles 11 4 5 SYSCLK cycles 140 IOWS 1 0 External ISA I O wait states read write strobe width 00 1 5 SYSCLK cycles 01 2 5 SYSCLK cycles 10 3 5 SYSCLK cycles 11 4 5 SYSCLK cycles User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL Reserved Function 0 is returned when read 2 2 SCLKDIV 1 0 SYSCLK external ISA bus clock divisor rate selection 00 PCLK 2 01 POLK 6 11 POLK 8 This register is used to set the external ISA configurations SYSCLK is an operation clock for the external ISA bus and is output only when an external ISA cycle is generated User s Manual U14272EJ3VO
136. transmit shift register check the LSR6 bit of the SIULS 1 register The LSR5 bit of the SIULS 1 register is used to check whether data to be transferred exists or not in the transmit FIFO only Therefore there may be data in the transmit shift register FIFO polling mode When the FCRO bit 1 FIFO is enabled in the SIUFC 1 register if the value of any or all of the SIUIE 1 register bits 3 to 0 becomes 0 SIU1 enters FIFO polling mode Because the transmit block and receive block are controlled separately polling mode can be set for either or both blocks When in this mode the status of the transmit block and or receive block can be checked by reading the SIULS 1 register via a user program When in the FIFO polling mode there is no notification when the trigger level is reached or when a timeout occurs but the receive FIFO and transmit FIFO can still store characters as they normally do User s Manual U14272EJ3VOUM CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 8 SIULC 1 0 0 00 0013 Name R W RTCRST Other resets Function 7 LCR7 Divisor latch access register switching 1 Divisor latch access register 0 Receive buffer transmit holding register interrupt enable register 6 LCR6 Break control 1 Set break 0 Clear break 5 LCR5 Parity fixing 1 Fixed parity 0 Parity not fixed 4 LCR4 Parity setting 1 Even parity 0 Odd parity 3 LCR3 Parity enable 1 Creat
137. upon Cold Reset This register is also set to the upper bound when the Wired register is written Figure 3 2 shows the format of the Random register Figure 3 2 Random Register 31 5 4 0 Lm Random TLB random index 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read User s Manual U14272EJ3VOUM 69 CHAPTER 3 REGISTERS 3 2 3 EntryLoO 2 and EntryLo1 3 registers The EntryLo register consists of two registers that have identical formats EntryLoO used for even virtual pages and EntryLo1 used for odd virtual pages The EntryLoO and EntryLo1 registers are both read write accessible They are used to access the built in TLB When a TLB read write operation is carried out the EntryLoO and EntryLo1 registers hold the contents of the low order 32 bits of TLB entries at even and odd addresses respectively The contents of these registers are undefined after a reset so that they must be initialized by software Figure 3 3 EntryLoO and EntryLo1 Registers a 32 bit mode 31 28 27 6 5 3210 EntryLoO F c 0 2 31 28 27 6 5 3 2 1 0 v ii e b 64 bit mode 63 28 27 6 5 3 2 1 0 crintoo 9 N Ive 63 28 27 6 5 3 2 1 0 o jojvje Page frame number high order bits of the physical address C Specifies the TLB page attribute see Table 3 2 D Dirty If this bit is set to 1 the page is marked
138. via DCD Interrupt Request BATTINH DCD1 Input POWERON Output MPOWER Output BATTINH BATTINT Input H Figure 10 10 Activation via DCD Interrupt Request BATTINH L acora LI LE LE L LI LE LI LT LI I DCD1 Input ff POWERON Output MPOWER Output L y BATTINH BATTINT Input L y User s Manual U14272EJ3VOUM 199 CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 5 5 Activation via ElapsedTime RTC alarm interrupt request When the alarm alarm intr signal generated from the ElapsedTime timer is asserted the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated After asserting the POWERON signal the PMU checks the BATTINH signal and then de asserts the POWERON signal If the BATTINH signal is at high level the PMU cancels the peripheral unit reset and starts the Cold Reset sequence to activate the CPU core If the BATTINH signal is at low level the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown After the CPU core is restarted the BATTINH bit must be checked and cleared to 0 by software Caution The ElapsedTime interrupt is ignored while the POWERON signal is active After the POWERON signal becomes inactive the PMU is notified Figure 10 11 Activation via ElapsedTime Interrupt Request BATTINH z H
139. when read CDRSMEN Card detect resume enable 1 Enables notification of change on CD1 and CD2 inputs This bit is valid when the CD EN bit is set to 1 the CRDSTATREG register 0 is returned when read Reserved 0 is returned when read CFGRSTEN Configuration reset enable 1 Enables initializing registers on high level of both 1 and CD2 inputs The registers involved are all I O registers all memory registers ITGENCTREG register and ADWINENREG register DLY16INH 16 bit memory delay prohibit This bit is used to set whether the falling edge of the WE and OE CF_WE and CF_OE signals of the CompactFlash is delayed in synchronization with SYSCLK when a memory window is set to be 16 bit in the DWIDTH bit of the MEMWIDn_REG register 0 Delayed 1 Not delayed The functionality and acknowledgment of this software interrupt request operate in the same way as those of the hardware generated interrupt requests The functionality and acknowledgement of the hardware card detect or card status change interrupt request are not affected by the setting of the SWCDINT bit If card detect or card status change is signaled through the CD1 and CD2 inputs a hardware card detect or card status change interrupt request is generated When the CDRSMEN bit is set to 1 the RIO signal internal goes from high level to low and the CD bit in the CDSTCHGREG register is set to 1 The RIO signal remains low until ei
140. when read LTS 6 0 LED OFF time setting 1111111 7 9375 seconds 1000000 4 seconds 0100000 2 seconds 0010000 1 second 0001000 0 5 seconds 0000100 0 25 seconds 0000010 0 125 seconds 0000001 0 0625 seconds 0000000 Prohibited Note A value before reset is retained This register is used to set the LED s OFF time low level width of LEDOUT The OFF time ranges from 0 0625 to 7 9375 seconds and can be set in 0 0625 second units The initial setting is 2 seconds This register must not be changed once the LEDENABLE bit of LEDCNTREG register has been set to 1 The operation is not guaranteed if a change is made after that point User s Manual U14272EJ3VOUM 355 CHAPTER 18 LED CONTROL UNIT LED 18 2 3 LEDCNTREG 0 0 00 0248 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets LEDSTOP LEDENABLE R W R W RTCRST Other resets Function Reserved 0 is returned when read LEDHLB LED status indication 1 0 LEDSTOP LED blink auto stop setting 1 Automatically stops 0 Does not stop automatically LEDENABLE LED blink setting 1 Blinks 0 Does not blink Note value before reset is retained This register is used to make various LED settings Caution When setting LED to blink make sure that a value other than zero has already been set to the LEDHTSREG
141. 0 CE2 CE1 Flash memory Bank2 STS CEO WE OE A 21 0 CE2 CE1 Flash memory Bank3 STS CEO WE OE DATA 15 0 Note There is no corresponding in the Vn4181 Using one of the GPIO pins for this function Remark Using one of the GPIO pins in the Vn4181 to control ON OFF of VPP program erase supply voltage 124 User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 6 3 4 External ROM cycles The following timing diagrams illustrate the external ROM cycles depending on the settings in the bus control register and bus speed control register 1 Ordinary ROM read cycle Figure 6 3 Ordinary ROM Read Cycle WROMA 3 0 0101 TClock internal ADD 21 0 7 output Valid ROMCS 3 0 output MEMRD output WROMA 3 0 DATA 15 0 read Remark circle in the figure indicates the sampling timing User s Manual U14272EJ3VOUM 125 CHAPTER 6 BUS CONTROL 2 PageROM read cycle Figure 6 4 PageROM Read Cycle WROMA 3 0 0011 WPROM 2 0 001 TClock internal ADD 21 0 output ROMCS 3 0 output MEMRD output L WROMA 3 0 2 0 WPROM 2 0 WPROM 2 0 WPROM 2 WPROM 2 0 WPROM 2 0 WPROM 2 0 DATA 15 0 Remark in the figure indicates the sampling timing
142. 0 6 TClock 011 8 TClock 100 11 TClock Others Reserved Caspre 1 0 CAS precharge time 00 1 2 TClock 1 1 TClock 10 2 TClock 11 Reserved Rcasdly 1 0 RAS to CAS delay time 00 2 TClock 1 3 TClock 10 5 TClock 1 6 TClock Users Manual U14272EJ3VOUM 131 CHAPTER 6 BUS CONTROL 2 2 Function Tcas 1 0 CAS pulse width 00 1 2 TClock 01 1 TClock 10 2 TClock 11 Reserved RAS precharge time 00 1 TClock 01 2 TClock 10 3 TClock 11 4 TClock Tras 1 0 RAS pulse width 00 2 TClock 01 3 TClock 10 5 TClock 11 6 TClock This register is used to set EDO DRAM timing parameters Software must set these parameters suitable before using DRAM Remark Do not set Tcas 1 2 TClock and Caspre 1 TClock or Tcas 1 TClock and Caspre 1 2 TClock at the same time 132 User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 6 5 2 MEMCFG REG 0 0 00 0304 Name 1 2 B1Config1 B1ConfigO Reserved Bstreftype R W R W R W R W At reset 0 0 0 Bit 7 6 5 4 3 2 1 0 R W BstRefr EDOAsym Reserved EDO SDRAM Reserved Reserved BOConfig1 BOConfigO At reset This bit is for SDRAM only When software writes 1 to this bit the memory controller issues a SDRAM mode set command After the SDRAM mode is set hardware automatically resets this bit to 0 When EDO DRAM is used this bit must not be set to 1 14
143. 0 General purpose input 01 RFU 10 General purpose output 11 SIU1 RTS1 output User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 2 2 Function GP26MD 1 0 These bits control direction and function of the GPIO26 as follows 00 General purpose input 01 RFU 10 General purpose output 11 SIU1 TxD1 output GP25MD 1 0 These bits control direction and function of the GPIO25 pin as follows 00 General purpose input 01 SIU1 RxD1 input 10 General purpose output 11 RFU GP24MD 1 0 These bits control direction and function of the GPIO24 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 ROMCS2 output User s Manual U14272EJ3VOUM 253 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 5 GPDATHREG 0 0 00 0308 Name GPDAT31 GPDAT30 GPDAT29 GPDAT28 GPDAT27 GPDAT26 GPDAT25 GPDAT24 R W R W R W R W R W R W R W R W R W RTCRST Other resets GPDAT23 GPDAT22 GPDAT21 GPDAT20 GPDAT19 GPDAT18 GPDAT17 GPDAT16 R W R W R W R W R W R W R W R W RTCRST Other resets Function GPDAT 31 16 General purpose data There is a one to one correspondence between these bits and GPIO pins When a GPIO pin is configured as a general purpose input the value of the pin can be read from this register When the pin is defined as a general purpose output the value written to this
144. 0 Low level triggered interrupt 11 High level triggered interrupt Note Holds the value before reset 258 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 2 2 Function H1TYP 1 0 These bits define the type of interrupt generated when the 11 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt MOTYP 1 0 These bits define the type of interrupt generated when the GPIO10 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 1 0 These bits define the type of interrupt generated when the 9 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 1 0 These bits define the type of interrupt generated when the pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt User s Manual U14272EJ3VOUM 259 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 10 GPINTTYPL 0 0 00 0312 1 2
145. 0 IrDA interface signals 1 nime c eem pt m rd ctp ct det eine rer ee Eg 58 2 2 11 General purpose I O signals 58 2 2 12 Dedicated Vpp GND signals eerte eene se eee denne dene 59 2 3 Pin Status in Specific Status 60 2 4 Recommended Connection of Unused Pins and I O Circuit Types 63 2 5 Pin V O Ci C S em cc 66 CHAPTER 3 CPO REGISTERS ieu ec esee tae aati hk ili 67 3 1 Copro essor GPO 22 5 re ernest neat 67 3 2 Details of CPO Registers 69 3 2 1 Index register 0 ne ete tei En Pad 69 3 2 2 Random register 1 e dee t etus 69 3 2 3 EntryLoO 2 and EntryLo1 3 registers 2 70 2 224 71 3 2 5 PageMask register 5 2 te peg ERRARE E 72 3 26 Wired register titres rtr rete ce ettet 73 3 2 7 BadVAddr register 8 ERE epo tre donee readin 74 23 2 8 Go ntregister 9 x uide e a i ER e cp ii de te p De Eb reme Rd 74 3
146. 0 is read The Status register has the following fields where the modes and access statuses are set User s Manual U14272EJ3VOUM 77 CHAPTER 3 REGISTERS 1 Interrupt enable Interrupts are enabled when all of the following conditions are true e IE bit is set to 1 e EXL bit is cleared to 0 e ERL bit is cleared to 0 The appropriate bit of the IM field is set to 1 2 Operating modes The following Status register bit settings are required for User Kernel and Supervisor modes e The processor is in User mode when KSU 10 EXL 0 and ERL 0 e The processor is in Supervisor mode when KSU 01 EXL 0 and ERL 0 e The processor is in Kernel mode when KSU 00 EXL 1 or ERL 1 Access to the kernel address space is allowed when the processor is in Kernel mode Access to the supervisor address space is allowed when the processor is in Supervisor or Kernel mode Access to the user address space is allowed in any of the three operating modes 3 Addressing modes The following Status register bit settings select 32 or 64 bit operation for each of User Kernel and Supervisor operating modes Enabling 64 bit operation permits the execution of 64 bit opcodes and translation of 64 bit addresses 64 bit operation for User Kernel and Supervisor modes can be set independently 64 bit addressing for Kernel mode is enabled when KX bit 1 64 bit operations are always valid in Kernel mode If this bit is s
147. 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is restarted RTCRST RTC reset detection Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is restarted RSTSW interrupt request detection Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is restarted DMSRST Deadman s Switch interrupt request detection Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is restarted BATTINTR Battery low detection during normal operation Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is restarted POWERSWINTR Power Switch interrupt request detection Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is restarted This register indicates the statuses of power on factors and interrupt requests It also indicates the status of the DCD1 pin The BATTINTR bit is set to 1 when the BATTINH BATTINT signal becomes low and a battery low interrupt request occurs during modes other than the Hibernate mode MPOWER The POWERSWINTR bit is set to 1 when the POWER signal becomes high and a Powe
148. 00000000000 nnnm rennen nennen nenne 17 4 22 VOLTSELREG Index Ox2F esssssssssssssssssseseeenenee nennen nennen nnne nennen enne nennen 17 5 Memory Mapping of CompactFlash Card eese eene eene nnne 17 6 Controlling Bus When CompactFlash Card Is Used sese 17 61 Controlling PUS SIZE eee Leere e itte co oo s 14 6 2 Controlling Walt ie e erre Ea eget Dec tone CHAPTER 18 LED CONTROL UNIT LED eene 18 1 E 18 2 Register Set 18 2 1 LEDHTSREG 0 0 00 0240 sse 18 2 2 LEDLTSREG 0x0B00 0242 inerenti EE ive aa 18 2 3 LEDCNTREG 0 0 00 0248 44 0 000 18 2 4 LEDASTCREG 0 0 00 0244 18 2 5 LEDINTREG 0 0 00 0246 222 cierre e esee ders 18 3 Operation FOW aa CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 4 2 22 42 2 1 19 1 General RN 19 2 Clock
149. 00E6 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Reserved Function 0 is returned when read CRTTIME 3 0 Current Deadman s Switch timer value elapsed time 1111 15 seconds 1110 14 seconds 0010 2 seconds 0001 1 second 0000 Setting prohibited This register indicates the elapsed time of the current Deadman s Switch timer 234 User s Manual U14272EJ3VOUM CHAPTER 12 DEADMAN S SWITCH UNIT DSU 12 3 Register Setting Flow The DSU register setting flow is described below 1 Set the DSU timer count cycle from 1 to 15 seconds Register DSUSETREG address 0 0 00 00 2 data 0x000x The CPU core will be reset if the timer is not cleared 1 is not written to DSUCLRREG register within this time period 2 Enable the DSU Register DSUCNTREG address 0x0BOO 00 0 data 0x0001 3 Clear the timer within the time period specified in step 1 above Cancel the clearance of the timer to start another counting Register DSUCLRREG address 0 0 00 00 4 data 0x0001 timer clear Register DSUCLRREG address 0 0 00 00 4 data 0x0000 timer operation start For normal use repeat step 3 To obtain the current elapsed time read the contents 4 bits of the DSUTIMREG register address 0x0B00 OOE6 4 Disable the DSU during Suspend mode or a shutd
150. 0BO00 0 17A iei e gie tpe pe eet d ra DR EE rp ERR ez 312 15 211 INTREG OXOBO0 0176 nt cbe er pec atte 313 15 2 12 MCNVC END 0 0 00 017E 314 15 3 eaae a AAEE 315 1523 4 Output Speaken E DEDERE 315 15 3 2 Input microphone stickies N dece ve ea 316 CHAPTER 16 KEYBOARD INTERFACE UNIT KIU 2 22 22 4 2 317 i SEc Icmeeec 317 16 2 Functional Description 317 16 2 1 Automatic keyboard scan mode Auto Scan 318 16 2 2 Manual keyboard scan mode Manual Scan mode sese 318 16 2 3 Key press detection cea e peste e ECCE eL Ae EE 318 16 2 425 t atte t da a t tdi th eta Tiger 319 16 2 5 Reading scanned data issii nei e e Et RR EC ER REIR ERE Red 320 16 2 6 Interrupts and status reporting 2 320 16 3 Regi siet Set ICD m 321 16 3 1 KIUDATn 0 0 00 0180 to 0 0 00 018 322 16 3 2 KIUSCANREP 0 0 00 0190 easa a aa 323 16 3 3 5 5 0 0 00 192 50
151. 1 TXFEINT Transmit FIFO Empty interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 TXBSYINT Transmit Shift Register Busy interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 Reserved 0 is returned after read ORNINT Receive FIFO Overrun interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 Users Manual U14272EJ3VOUM 167 CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 2 2 Function RXBEINT Receive Burst End interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 RXFFINT Receive FIFO Full interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 RXBSYINT Receive Shift Register Busy interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 168 User s Manual U14272EJ3VOUM CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 8 3 7 CSITXBLEN 0 0 00 090C Name TXBLN15 TXBLN14 TXBLN13 TXBLN12 TXBLN10 TXBLN9 TXBLN8 R W RTCRST Other resets RTCRST Other resets Function TXBLN 15 0 Transmit burst length These bits determine the number of bits transmitted during one burst cycle 0x0000 Reserved 0x0001 1 bit 0x0002 2 bits 0x00FD 253 bits OxOOFE 254 bits OxOOFF 255 bits OxFFFD 65533 bits OxFFFE 6
152. 159 CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 8 2 4 Transmit and receive FIFOs The CSI contains two 8 deep 16 bit FIFOs One is for transmission and the other for reception The transmit and receive shift registers access the FIFOs by 8 bits at a time The CPU core accesses the FIFOs in either 8 bit or 16 bit units The threshold of each FIFO is independently programmable For the transmit FIFO an interrupt request is generated to inform the CPU that 1 2 or 4 16 bit words are empty in the FIFO For the receive FIFO an interrupt request is generated to inform the CPU core that 1 2 or 4 16 bit words can be read from the FIFO The FIFO control logic can also generate interrupt requests to signal an overrun condition for the receive FIFO or an underrun condition for the transmit FIFO An overrun occurs when the receive shift register attempts to transfer data to a location in the FIFO which has not be read by the CPU core An underrun occurs when the transmit shift register attempts to load a value from the FIFO which has not been updated by the CPU core 1 Overrun underrun errors When an overrun error occurs the receive FIFO logic generates an overrun interrupt request if unmasked and overwrites the next location in the FIFO with the contents of the receive shift register When an underrun error occurs the transmit FIFO logic generates an underrun interrupt request if unmasked and reloads the transmit shift register with the contents
153. 180 to 0x0B00 018E Remark n 0to7 KIUDATO KIUDAT1 KIUDAT2 KIUDAT3 0 0 00 0180 0 0 00 0182 0 0 00 0184 0 0 00 0186 KIUDAT4 KIUDAT5 KIUDAT6 KIUDAT7 0 0 00 0188 0 0 00 018A 0 0 00 018C 0 0 00 018E Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets Name RETDAT7 RETDAT6 RETDATS RETDAT4 RETDATS RETDAT2 RETDAT1 R W RTCRST Other resets Bit Name Function Reserved 0 is returned when read RETDAT 7 0 Scan data 1 Key is released 0 Key is pressed These registers reflect the state of the returned signals for the selected SCANOUT pins Each register corresponds to one SCANOUT pin as follows SCANOUT pin KIUDAT register SCANOUT7 KIUDAT7 SCANOUT6 KIUDAT6 SCANOUTS5 KIUDAT5 SCANOUT4 KIUDAT4 SCANOUT3 KIUDAT3 SCANOUT2 KIUDAT2 SCANOUT1 KIUDAT1 SCANOUTO KIUDATO 322 User s Manual U14272EJ3VOUM CHAPTER 16 KEYBOARD INTERFACE UNIT KIU 16 3 2 KIUSCANREP 0 0 00 0190 Name Reserved Reserved Reserved Reserved Reserved STPREP5 STPREP4 R W RTCRST Other resets RTCRST Other resets Function KIU enable This bit enables a KIU operation When this bit is set to 0 the scan sequencer and all interrupt requests are disabled 1 Enable 0 Disable 14 to 10 Reserved 0 is returned when
154. 181 1 3 10 Serial interface channel 1 SIU1 The 4181 provides 16550 UART for implementing RS 232 C type serial interface When the serial interface is not needed each of the 7 serial interface pins can be individually redefined as general purpose pins 1 3 11 Serial interface channel 2 SIU2 The serial interface channel 2 is also based on a 16550 UART but only reserves 2 pins for the interface The serial interface channel 2 can be configured in one of the following modes Simple 2 wire serial interface using TxD2 and RxD2 SIR type IrDA interface using IRDIN and IRDOUT Full RS 232 C compatible interface using 2 RxD2 and 5 GPIO pins 32 User s Manual U14272EJ3VOUM CHAPTER 1 INTRODUCTION 1 3 12 Clocked serial interface CSI The 4181 provides a clocked serial interface CSI which has an option to be configured as general purpose I O pins This interface supports slave mode operation only The clocked serial interface requires allocation of 4 signals SI SO SCK and FRM The clock source for this interface is input on the pin assigned to SCK 1 3 13 Keyboard interface KIU The Vn4181 provides support for 8 x 8 key matrix This keyboard interface can only be supported when the CompactFlash interface is disabled and reconfigured to provide the SCANIN 7 0 inputs and the SCANOUT 7 0 outputs 1 3 14 General purpose Vn4181 provides total 32 bits of general purpose I O Sixte
155. 2 1 VcconO Testmode Test mode enable 0 Normal operation 1 Enters test mode Vcc VPLCD signal polarity control 0 Active low 1 Active high Reserved Write 0 when write 0 is returned when read BiasCon Bias VPBIAS signal polarity control 0 Active low 1 Active high Power control 0 Off 1 Fon 4 0 Frame at which the panel logic interface signals are turned on Vccon 4 0 426 Frame at which the panel Vcc is turned on User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 21 4 24 LCDIMSKREG 0x0A00 0434 Reserved Reserved Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved MVIReq MFIFO Reserved OVERR Reserved 0 is returned when read MVIReq Vertical retrace interrupt mask 0 Mask 1 Unmask MFIFOOVERR FIFO overrun interrupt mask 0 Mask 1 Unmask Reserved 0 is returned when read Users Manual U14272EJ3VOUM 427 CHAPTER 21 LCD CONTROLLER 21 4 22 CPINDCTREG 0x0A00 047E PalPage3 PalPage2 PalPage1 PalPageO PalRDI PalWRI R W R W R W R W R W R W 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Pallndex7 Pallndex6 Pallndex5 Pallndex4 Pallndex3 Pallndex2 Pallndex1 PallndexO Bit Name Function 15 to 12 PalPage 3 0 Palette page select used in 4 bpp mode 11 10 Reserved 0 is returned when
156. 2 9 EntryHi tegister TO iere ete e CREER ERG REESE 75 3 2 10 Compare register 11 eie ei cd tr Late cn de e EO fe p ie Re edat 76 9 2 11 Stat s register 12 2 qc eb Ee eie 76 2 2 12 Gause tregister 13 ee eR 79 3 2 13 Exception Program Counter EPC register 14 2 02400440040 00 0 81 3 2 14 Processor Revision Identifier PRId register 15 82 2 2215 Config register 16 een da ae f a AE eee 83 3 2 16 Load Linked Address LLAddr register 17 se 84 3 2 17 WatchLo 18 and WatchHi 19 registers 85 3 2 18 XC ntext register 20 tien eee Cere ede ke pec ei Pee cde oce idet 86 3 2 19 Parity Error register 26 x cusam eet Pe tet tree ee ve tx ce b Ree eee Fg 87 9 2 20 Cache Error register 27 ROMERO 87 3 2 21 TagLo 28 and TagHi 29 registers 88 9 2 22 Errore PG register GO iaei x rd eaten eed tener 89 CHAPTER 4 MEMORY MANAGEMENT SYSTEM 24222 2 91 AN OVOTNIGW e AN 91 4 2 Physical Address Space 92 AsV ROM SpaCe HARE RAUM HINDINAME D maim 93 4 2 2 External system
157. 2 User s Manual U14272EJ3VOUM CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 8 3 2 CSIRXDATA 0 0 00 0902 Name R W RTCRST Other resets RTCRST Other resets 15100 RXD 15 0 CSI receive data CSI data received on the SI pin is read through these data bits 8 3 3 CSITXDATA 0 0 00 0904 R W RTCRST Other resets Name R W RTCRST Other resets 15 to 0 TXD 15 0 CSI transmit data CSI data written to these bits is transmitted on the SO pin User s Manual U14272EJ3VOUM 163 CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 8 3 4 CSILSTAT 0 0 00 0906 Name TFIFOT1 TFIFOTO Reserved Reserved Reserved TXFIFOF TXFIFOE R W RTCRST Other resets RTCRST Other resets TFIFOT 1 0 Function CSI transmit FIFO threshold These bits select the level at which the transmit FIFO empty status is notified 00 1 or more words are free in transmit FIFO 01 2 or more words are free in transmit FIFO 10 4 or more words are free in transmit FIFO 11 Reserved 13 to 11 Reserved 0 is returned after read 10 TXFIFOF CSI transmit FIFO full status This bit is set to 1 when the transmit FIFO contains no free space 0 Transmit FIFO not full 1 Transmit FIFO full TXFIFOE CSI transmit FIFO empty status This bit is set to 1 when the tra
158. 20 1 General The 5102 is a serial interface that conforms to the RS 232 C communication standard and is equipped with two one channel interfaces one for transmission and one for reception This unit can be also used as an interface in the IrDA format by means of register setting This unit is functionally compatible with the NS16550 except for the additional clock control logic to permit the 16650 core clock source to be stopped Figure 20 1 SIU2 Block Diagram Vn4181 IRDOUT TxD2 ART2 clock IRDIN RxD2 RTS2 DCD2 DTR2 Activity Timer 2 Seclk siu clk32k Caution clock is supplied to the SIU2 in the initial state When using the SIU2 set the MSKSIU18M bit of the CMUCLKMSK register in the MBA Host Bridge to 1 in advance so that the clock is supplied 20 2 Clock Control Logic The power of the 16550 core can be managed by monitoring activity on the modem status pins and writes to the transmit buffer The clock control logic for the 16550 core monitors activity on the four serial interface input signals RxD2 RTS2 DCD2 and DTR2 It also monitors writes to the 16550 transmit buffer Each source has an associated mask bit which prevents a source from causing reset of the Activity Timer Activity on the RxD2 RTS2 DCD2 and DTR2 inputs is defined as any change of state high to low or low to high When no unmasked activity has been detected on any of the inputs a
159. 250 ns to the BCURFCNTREG register in the MBA Host Bridge Then execute CBR auto refresh cycles for a specific time period i e Ox8FFF x TClock period burst refresh interval required by DRAM Clear the BstRefr bit of the MEMCFG_REG register in the memory controller to 0 to disable a burst refresh Then set SUSPEND bit in the DRAMHIBCTL register to 1 to put the DRAM into self refresh mode Poll the OK_STOP_CLK bit in the DRAMHIBCTL register to confirm that the memory controller puts the DRAM into self refresh mode Set the STOP_CLK bit in the DRAMHIBCTL register to 1 to stop supplying TClock to the memory controller lt 10 gt Set the DRAM_EN bit in the DRAMHIBCTL register to 1 so that the DRAM interface signals are latched lt 11 gt Clear the SUSPEND bit in the DRAMHIBCTL register to 0 after waiting for about 2 us lt 12 gt Execute a HIBERNATE instruction lt 13 gt Stop applying 2 5 V power supply when the MPOWER signal becomes low level Caution When entering Hibernate mode set the BEV bit of the Status register in the CPO of the CPU core 202 to 1 to make sure that the vector of the exception handler points the ROM area User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 6 3 Exiting Hibernate mode EDO DRAM 1 Generate a wake up event such as a transition on the POWER pin a DCD interrupt etc which causes the PMU to start a power on sequence 2 Apply 2 5 V power supply when the MPOWE
160. 2A20 SS2A18 SS2A17 SS2A16 R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 SS2A 31 16 Upper 16 bits 31 16 of source 2 address for Speaker These two registers specify the source memory address of the secondary DMA buffer for the Speaker channel 148 User s Manual U14272EJ3VOUM CHAPTER 7 DMA CONTROL UNIT DCU 7 2 5 DMARSTREG 0x0A00 0040 Name Reserved Reserved R W At reset Bit 7 6 5 4 3 2 1 0 DMARST Name R W Reserved Reserved Reserved Reserved Reserved Reserved Reserved At reset Bit Name Function Reserved 0 is returned after a read DMARST Resets DMA functions 0 Resets DMA channels 1 Normal operation When DMARST bit is written to zero all active DMA transfers are immediately terminated and the DCU enters in the reset state While DMARST bit is 0 all DMA requests become pending until this bit is set to 1 7 2 6 AIUDMAMSKREG 0x0A00 0046 Name Reserved Reserved R W At reset Name Reserved Reserved Reserved Reserved MICMSK SPKMSK Reserved Reserved R W R R R R R W R W R R At reset 0 Reserved 0 0 0 0 is returned after a read 0 0 0 0 MICMSK 0 Microphone channel disabled 1 Microphone channel
161. 3 Status of interrupt request 5 4 and 3 internal 0 Invalid 1 Valid Reserved 0 is returned when read Remark A single bit corresponds to each interrupt request User s Manual U14272EJ3VOUM 331 CHAPTER 17 COMPACTFLASH CONTROLLER 17 3 2 INTMSKREG 0 0 00 08FA IMSK015 5 014 5 012 5 010 IMSK09 Reserved IMSK0 15 14 Mask for interrupt request 15 and 14 internal 0 Unmask 1 Mask Reserved 0 is returned when read IMSKO0 12 9 Mask for interrupt request 12 11 10 and 9 internal 0 Unmask 1 Mask Reserved 0 is returned when read IMSK07 Mask for interrupt request 7 internal 0 Unmask 1 Mask Reserved 0 is returned when read IMSK0 5 3 Mask for interrupt request 5 4 and 3 internal 0 Unmask 1 Mask Reserved 0 is returned when read Remark A single bit corresponds to each interrupt request 332 User s Manual U14272EJ3VOUM CHAPTER 17 COMPACTFLASH CONTROLLER Figure 17 1 CompactFlash Interrupt Logic IRQSEL 3 0 Index 0x03 IRQ3 IREQ CF_BUSY INTSTATREG 0 0 00 08 8 CDSTCHGREG Index 0x04 SIRQ 3 0 Index 0x05 BATDEAD STSCHG Status IRQS CF_STSCHG change ecuint D1 D2 interrupt to ICU INTMSKREG 0x0B00 08FA RDY BSY CF_BUSY Remark All IRQ signals are ORed together to generate ecuint a
162. 3 rz 15 11 10 87 0 l64 type 164 funct immediate i 5 11 10 87 54 RI64 type 164 funct immediate JAL JALX type 31 16 15 11 10 9 54 0 Immediate 15 0 JAL X Immediate 20 16 Immediate 25 21 User s Manual U14272EJ3VOUM 39 CHAPTER 1 INTRODUCTION The instruction set can be further divided into the following four groupings a Load and store instructions move data between memory and general purpose registers They include 18 and RI64 types b Computational instructions perform arithmetic logical shift and multiply and divide operations on values in registers They include RI RRIA 18 RI64 164 RR RRR I8 MOVR32 and I8 MOVS2R types c Jump and branch instructions change the control flow of a program They include JAL JALX RR RI I8 and I types d Special instructions are BREAK and Extend instructions The BREAK instruction transfers control to an exception handler The Extend instruction extends the immediate field of the next instruction They are RR and types When extending the immediate field of the next instruction by using the Extend instruction one cycle is needed for executing the Extend instruction and another cycle is needed for executing the next instruction 1 4 3 Data formats and addressing The Vn4181 uses the following four data formats Doubleword 64 bits Word 32 bits e Halfword 16 bits e Byte 8 bits If the data format is any one of hal
163. 3 15 SIBGCSEL2 0x0G00 000A 2 nitore tenente te e ctt derit feret 396 20 3 16 SIUACTMSK 2 0x0C00 0000 ssssseesseseneeneennenenneenn nene nen 397 20 83 17 SIUAGTIMR amp 2 0x0C00 000E ien tr e ro eid De c eae EE ope 398 CHAPTER 21 LCD CONTROLLER 5 uen chika ien 399 AES MO M 399 21 11 LCD Ite race a eee edu He S LE ep e SE Arni ne e ERR 399 21 2 LCD Module Features 400 21 3 LCD Controller Specification 402 21 3 1 Panel configuration and interface 402 21 3 2 Gonttoller cloCkS uiia tmu epi ebur 405 21 3 3 Palette ea de e LA ee e e cete te PL ex 406 21 3 4 Frame buffer memory and FIFO seessssssessesssseeeeee nennen rennen nnne nennen nennen 406 21 3 5 Panel power ON OFF sequence 407 21 3 6 Operation of LED controller crt eer e e ste 408 21 4 Register Set tee eet etes cee lus Aaa nr rae ia Eae Danar aaiae 413 21 4 1 HRTOTALREG 0x0A00 0400 414 21 4 2 HRVISIBREG 0 0 00 0402 414 21 4 3 LDCLKSTREG 0 0 00 0404 415 21 4 4 LDCLKENDREG 0 0 00 0406
164. 300 Va5000A Va5432 Va10000 Vn4111 Vn4122 Vn4305 Va12000 Supported instructions Vr4310 MIPS MIPS II MIPS III LL bit manipulation MIPS IV MIPS16 A A Multiply add A A A 16 bits 32 bits 32 bits Floating point operation N A N A A A Power mode transition A A A A 46 User s Manual U14272EJ3VOUM CHAPTER 1 INTRODUCTION 1 5 Clock Interface The Vn4181 has the following eight clocks e CLKX1 CLKX2 input These are oscillation inputs of 18 432 MHz and used to generate operation clocks for the CPU core serial interface and other peripheral units e RTCX1 RTCX2 input These are oscillation inputs of 32 768 kHz and used for PMU RTC and so on PClock internal This clock is used to control the pipeline in the Vn4110 core and for units relating to the pipeline This clock is generated from the clock input of CLKX1 and CLKX2 pins via the PLL Its frequency is determined by CLKSEL 2 0 pins MasterOut internal This is a bus clock of the Vn4110 core and used for interrupt control This clock operates in frequency of 1 4 of the TClock frequency The contents of the CPO s Count register are incremented synchronously with this clock TClock internal This is an operation clock for internal MBA bus and is supplied to the internal MBA modules memory controller LCD controller and DMA controller This clock is generated from P
165. 4 Mbit EDO DRAMs of other than 13 rows and 9 columns cannot be used with the 4181 128 User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 6 4 2 Mixed memory mode EDO DRAM only The MEMCFG_REG register provides two bits each for Bank 0 and Bank 1 to set types of DRAMs to be used This allows the two banks to be configured with different types of DRAMs for example Bank 0 be mapped on 64 Mbit devices and Bank 1 on 16 Mbit devices to optimize the cost of the total memory required 16 Mbits Table 6 2 Vn4181 EDO DRAM Capacity 0 Total DRAM capacity 16 Mbits 16 Mbits 64 Mbits 0 16 Mbits 64 Mbits 64 Mbits 16 Mbits 64 Mbits 64 Mbits 6 4 3 EDO DRAM timing parameters The following table shows examples of EDO DRAM timing parameters when using EDO DRAMs with access time of 60 ns These parameters are set in EDOMCYTREG register TClock frequency RAS to CAS delay 3 TClock CAS pulse width 1 TClock CAS precharge 1 TClock RAS precharge 3 TClock RAS pulse width 3 TClock Self refresh RAS precharge 8 TClock 2 TClock 1 TClock 1 TClock 2 TClock 3 TClock 6 TClock 2 TClock 1 2 TClock 1 2 TClock 2 TClock 2 TClock 4 TClock 2 TClock 1 2 TClock 1 2 TClock 1 TClock User s Manual U14272EJ3VOUM 2 TClock 3 TClock 129 CHAPTER 6 BUS CONTROL 6 4 4 SDRAM configuration
166. 4272EJ3VOUM Readers Purpose Organization How to read this manual Conventions PREFACE This manual targets users who intend to understand the functions of the VR4181 and to design application systems using this microprocessor This manual introduces the hardware functions of the VR4181 to users following the organization described below Two manuals are available for the VR4181 Hardware User s Manual this manual and Architecture User s Manual common to the Vn4100 Series Hardware Architecture User s Manual User s Manual Pin functions Pipeline operation Physical address space Cache organization and memory Function of Coprocessor 0 management system Initialization interface Exception processing Peripheral units Interrupts Instruction set It is assumed that the reader of this manual has general knowledge in the fields of electric engineering logic circuits microcomputers and SDRAMs To learn about the overall functions of the VR4181 Read this manual in sequential order To learn about instruction sets Read Vn4100 Series Architecture Users Manual that is separately available To learn about electrical specifications Refer to Data Sheet that is separately available Data significance Higher on left and lower on right Active low XXX trailing after pin and signal names Note Description of item marked with Note in the text Caution Information requirin
167. 5534 bits OxFFFF 65535 bits User s Manual U14272EJ3VOUM 169 CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 8 3 8 CSIRXBLEN 0 0 00 090E Name RXBLN15 RXBLN14 RXBLN13 RXBLN12 RXBLN10 RXBLN9 RXBLN8 R W RTCRST Other resets RTCRST Other resets Function RXBLN 15 0 Receive burst length These bits determine the number of bits received during one burst cycle 0x0000 Reserved 0x0001 1 bit 0x0002 2 bits 0x00FD 253 bits OxOOFE 254 bits OxOOFF 255 bits OxFFFD 65533 bits OxFFFE 65534 bits OxFFFF 65535 bits 170 User s Manual U14272EJ3VOUM CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 1 Overview The ICU collects interrupt requests from the various on chip peripheral units and transfers them with internal interrupt request signals IntO Int1 Int2 Int3 Int4 and NMI to the CPU core The signals used to notice interrupt requests to the CPU are as below NMI battint only However the signal for battint be switched between NMI IntO is enabled according to NMIREG registers settings Because NMI s interrupt masking cannot be controlled by means of software switch to IntO to mask battint Int4 Not used fixed to 1 inactive Int3 Not used fixed to 1 inactive Int2 rtclong2 only RTCLong2 Timer Inti rtclong1 only RTCLong1 Timer IntO All other interrupts For details of the interrupt sources see 9 2 Register
168. 6 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 IORD output Users Manual U14272EJ3VOUM 251 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 4 GPMD3REG 0 0 00 0306 Name GP31MD1 GP31MDO GP30MD1 GP30MDO GP29MD1 GP29MDO GP28MD1 1 2 GP28MDO R W R W R W R W R W R W R W R W R W RTCRST Other resets GP27MD1 GP27MDO GP26MD1 GP26MDO GP25MD1 GP25MDO GP24MD1 GP24MDO RTCRST R W R W R W R W R W R W R W R W Other resets GP31MD 1 0 Function These bits control direction and function of the GPIO31 pin as follows 00 General purpose input 01 SIU1 DSR1 input 10 General purpose output 11 RFU GP30MD 1 0 These bits control direction and function of the GPIO3O pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 SIU1 DTR1 output GP29MD 1 0 These bits control direction and function of the GPIO29 pin as follows 00 General purpose input 01 SIU1 DCD1 input 10 General purpose output 11 RFU GP28MD 1 0 These bits control direction and function of the GPIO28 pin as follows 00 General purpose input 01 SIU1 CTS1 input 10 General purpose output 11 RFU GP27MD 1 0 Note Holds the value before reset 252 These bits control direction and function of the GPIO27 pin as follows 0
169. AL INTERFACE UNIT 1 5101 Table 19 2 Correspondence between Baud Rates and Divisors Baud rate bps Divisor 1 clock width us DLM 7 0 DLL 7 0 50 20000 00 75 13333 33 110 9090 91 134 5 7434 94 150 6666 67 300 3333 33 600 1666 67 1200 833 33 1800 555 56 2000 500 00 2400 416 67 3600 277 78 4800 208 33 7200 138 89 9600 104 17 19200 52 08 38400 26 04 57600 17 36 115200 8 68 128000 7 81 144000 6 94 192000 5 21 230400 4 34 288000 3 47 384000 2 60 576000 1 74 1152000 0 868 User s Manual U14272EJ3VOUM 365 CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 6 SIUIID 1 0 0 00 0012 Read Name Reserved Reserved R W RTCRST Other resets Function IIR 7 6 Becomes 11 when bit 1 Reserved 0 is returned when read 3 Pending of the character timeout interrupt request FIFO mode 1 No pending 0 Pending 2 1 IIR 2 1 Indicates the priority level of interrupts See the following table 0 IIRO Pending interrupt requests 1 No pending 0 Pending This register indicates priority levels for interrupts and existence of pending interrupt requests From highest to lowest priority the involved interrupts are the receive line status the receive data ready the character timeout the transmit holding register empty
170. AL INTERFACE UNIT 2 5102 20 3 1 SIURB 2 0 0 00 0000 LCR7 0 Read Name R W RTCRST Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Other resets Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Serial receive data 7100 This register stores receive data used serial communications To access this register set the LCR7 bit bit 7 of the SIULC 2 register to 0 RXD 7 0 20 3 2 SIUTH 2 0 0 00 0000 LCR7 0 Write RTCRST Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Other resets Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Serial transmit data 7100 TXD 7 0 This register stores transmit data used in serial communications To access this register set the LCR7 bit bit 7 of the SIULC 2 register to 0 20 3 3 SIUDLL 2 0 0 00 0000 LCR7 1 Name DLL7 DLL6 DLL5 DLL4 DLL3 DLL2 DLL1 DLLO R W R W R W R W R W R W R W R W R W RTCRST Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Other resets 7100 Undefined DLL 7 0 Undefined Undefined Undefined Undefined Baud
171. ATV 1 Output 10 bit data 0 0 00 0166 SODAT 9 0 to D A converter SODATV 0 SDMAV 1 Send SDMADATREG data to SODATREG SODATV 1 SDMAV 0 Output DMA request and store the data after the next into SDMADATREG SODATV 1 SDMAV 1 Update data at each conversion timing interval becomes SIDLEINTR 1 when DMA delays and SODATV 0 during conversion timing interval and mute interrupt request occurs DMA page boundary interrupt request occurs at page boundary Clear the page interrupt request to continue output Disable speaker operation 0 0 00 017A AIUSEN 0 Set speaker power OFF via GPIO 10 Set D A converter s Vref to OFF 0x0B00 0168 DAENAIU 0 11 Disable DMA in DCU Figure 15 1 Speaker Output and AUDIOOUT Pin AUDIOOUT 1 2 lt 3 gt lt 4 gt lt 5 gt lt 6 gt 7 lt 8 gt lt 9 gt lt 10 gt 11 Vop 2 bsec time User s Manual U14272EJ3VOUM 315 CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 3 2 Input microphone Set conversion rate 0 0 00 017E MCNVC 15 0 any value Set D A converter Vref setup time 0 0 00 0164 any value to be DVAREF 15 0 PCLK frequency 5 us Enable DMA after setting DMA address in DCU Set A D converter s Vref to ON 0x0B00 0172 ADENAIU 1 Microphone power can be set ON and microphone operation can be enabled AIUMEN 1 without waiting for Vref resistor stabilization time about 5 us However in such a case
172. BIAS Biason 4 0 BiasCon VPLCD Vccon 4 0 VccC LCD Interface l Fon 4 0 active For example storing 1 in the BiasCon bit and 3 in the Biason field brings the LCD controller to make the VPBIAS signal from high impedance to high level three frames after the PowerC bit is set to 1 not counting the frame in which the PowerC bit is changed Setting the PowerC bit to O starts the power off sequence In the power off sequence the control pins are put into high impedance so that the power supply is turned off The pins enter high impedance in the reverse order of the power on sequence but the time delay between the two control pins remains the same Users Manual U14272EJ3VOUM 407 CHAPTER 21 LCD CONTROLLER 21 3 6 Operation of LCD controller Figure 21 5 Monochrome Panel LOCLK Output SHCLK Output Output me SAK Re Xe RoR RY Output m AK AAA AANA Output Output c SHCLK W 4 pulses Remark W panel width Hact 5 0 x 8 The polarity order of rising and falling edges of the LOCLK and the SHCLK are programmable via the LPPOL and SCLKPOL bits 408 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER Figure 21 6 Color Panel in 8 Bit Data Bus LOCLK Output SHCLK Output Output mE TCC ITE Output mo ronn CY CJ Output Output FPD7 1G 4R Output FPD6 Output
173. CACHE instruction and jump to the cached codes These codes can be executed on ROM Poll the OK STOP CLK bit in the DRAMHIBCTL register until it is set to 1 Remark Software must wait until the OK STOP CLK bit in the DRAMHIBCTL register is set to 1 before reinitializing the memory controller registers Otherwise unpredictable behavior of the memory controller could result Clear the DRAM EN bit in the DRAMHIBCTL register to 0 so that the DRAM interface signals are again driven directly by the memory controller Clear SUSPEND bit in the DRAMHIBCTL register to 0 to exit self refresh mode If DRAM can accept mixed use of burst and distributive CBR refresh set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge Then execute CBR refresh cycles for a specific time period i e OXGFFF x TClock period burst refresh interval required by DRAM Restore to the BCURFCNTREG register in the MBA Host Bridge a value that determines refresh interval satisfying the conditions of DRAM type to be used 10 6 8 Exiting Suspend mode SDRAM 1 2 lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt gt Generate a wake up event from Suspend mode such as a transition on the POWER pin a DCD interrupt etc Software execution resumes at the General exception vector OXOBFC 0380 when BEV 1 Copy the codes for the restore lt 4 gt through lt 7 gt below beginning at a 16 byte bound
174. Card memory 3 offset address low byte register 0x002D MEMOFFH3REG Card memory 3 offset address high byte register 0x002F VOLTSELREG Card voltage select register 0x0030 SYSMEMSL4REG System memory 4 mapping start address low byte register 0x0031 MEMWID4_REG System memory 4 mapping start address high byte register 0x0032 SYSMEMEL4REG System memory 4 mapping stop address low byte register 0 0033 MEMSEL4_REG System memory 4 mapping stop address high byte register 0x0034 MEMOFFL4REG Card memory 4 offset address low byte register 0 0035 330 MEMOFFH4REG Card memory 4 offset address high byte register User s Manual U14272EJ3VOUM CHAPTER 17 COMPACTFLASH CONTROLLER 17 3 ECU Control Registers 17 3 1 INTSTATREG 0x0B00 08F8 Name IRQ15 IRQ14 Reserved IRQ12 IRQ1 1 IRQ10 IRQ9 Reserved R W R R R R R R R R Reset 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved R R R R IRQ 15 14 0 0 Function Status of interrupt request 15 and 14 internal 0 Invalid 1 Valid 0 0 Reserved 0 is returned when read IRQ 12 9 0 Invalid 1 Valid Status of interrupt request 12 11 10 and 9 internal Reserved 0 is returned when read Status of interrupt request 7 internal 0 Invalid 1 Valid Reserved 0 is returned when read IRQ 5
175. Clock and its frequency is 1 1 1 2 or 1 3 of the PClock frequency it is determined by internal register setting It is set to 1 2 by default e PCLK internal This clock is supplied to the internal ISA peripherals This clock is generated from TClock and its frequency is determined by internal register setting PCLK will operate only when accesses to the internal ISA bus occur e SYSCLK internal output This clock is used as the external ISA bus clock It is also supplied to the internal CompactFlash controller This clock is generated from PCLK and its frequency is determined by internal register setting SYSCLK will operate only when accesses to the external ISA bus occur e SDCLK output This clock is supplied to SDRAM This clock operates in the same frequency as that of TClock SDCLK will operate only when accesses to SDRAM occur Users Manual U14272EJ3VOUM 47 CHAPTER 1 INTRODUCTION Figure 1 8 shows the external circuits of the clock oscillator Figure 1 8 External Circuits of Clock Oscillator a Crystal oscillation b External clock Vn4181 Vn4181 External s Note 1 Open Note2 GND OSC Note 1 Notes 1 CLKX1 RTCX1 2 CLKX2 RTCX2 Cautions1 When using the clock oscillator wire as follows in the area enclosed by the broken line in the above figures to avoid an adverse effect from wiring capacitance e Keep the wiring length as short as possible Do not cross the wiring
176. Compare 44440 76 Config register sese 83 Context 71 conversion 308 314 Coprocessor 0 uu 67 106 Coprocessor 0 431 Count register 2 tee eese 74 OP utter eth tte attain ettet au 67 CPO registers cssc eee 43 67 reine bester en 429 CPINDGTBEQ terit cer ttes 428 CPU Cores ohne te es 31 35 CPU registers iore e mte 37 CRDSTATIREG wisi i nene 339 ecl 156 238 CSLregistets 2 2 nte tee Di be derunt 160 CSI transfer 2 2 157 CSI transfer 2 159 CGSIINTMSK eco t cete perat 166 CSIINTSTAT 4 e eire cohetes 167 e ENERO E 164 CSIMOD Bet 1 i enean 161 CSIRXBLEN 5 n teens 170 User s Manual U14272EJ3VOUM 439 APPENDIX B INDEX CSIBXDATA dieci cd tena mec et eh 163 CSITXBEENS 3e 169 CSITXDATA p a aa ete 163 D D A converter 301 data formats 40 data OSS cct HERE aetate 299 DAVREF SETUP nte nies 305 DOU 142 registers 144 Deadman s Switch reset 99 192 Deadman s Switch
177. DDATAS PADDATA2 PADDATA1 PADDATAO R W RTCRST Other resets Bit Name 1 Valid 0 Invalid Function Indicates validity of data in page buffer 141010 Reserved 0 is returned when read 9100 PADDATA 9 0 A D converter s sampling data These registers are used to store coordinate data or touch pressure data There are four coordinate data buffers and one touch pressure data buffer each of which holds two pages of coordinate data or pressure data and the addresses register addresses where the coordinate data or the pressure data is stored are fixed Read coordinate data or pressure data from the corresponding register in a valid page The VALID bit which indicates whether the data is valid is automatically rendered invalid when the page buffer interrupt source the PADPAGEOINTR or PADPAGE1INTR bit in the PIUINTREG register is cleared Table 14 5 shows correspondences between the sampled data and the register in which the sampled data is stored Table 14 5 Detected Data and Page Buffers Detected data Page0 Buffer PIUPBOOREG Page1 Buffer PIUPB10REG PIUPBO1REG PIUPB11REG PIUPBO2REG PIUPB12REG PIUPBOSREG PIUPB13REG Z Touch pressure User s Manual U14272EJ3VOUM PIUPBO4REG PIUPB14REG 293 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 3 10 PIUABnREG 0 0 00 02 0 to 0 0 00 02B6 Remark n 0to3
178. E I O UNIT GIU 13 3 Register Set The GIU provides the following registers Physical address 0 0 00 0300 Table 13 11 GIU Registers 1 2 Register symbol GPMDOREG Function GPIO Mode 0 register 0 0 00 0302 GPMD1REG GPIO Mode 1 register 0 0 00 0304 GPMD2REG GPIO Mode 2 register 0 0 00 0306 GPMD3REG GPIO Mode 3 register 0 0 00 0308 GPDATHREG GPIO data high register 0 0 00 030A GPDATLREG GPIO data low register 0 0 00 030C GPINTEN GPIO interrupt enable register 0 0 00 030E GPINTMSK GPIO interrupt mask register 0 0 00 0310 GPINTTYPH GPIO interrupt type high register 0 0 00 0312 GPINTTYPL GPIO interrupt type low register 0 0 00 0314 GPINTSTAT GPIO interrupt status register 0 0 00 0316 GPHIBSTH GPIO Hibernate pin status high register 0 0 00 0318 GPHIBSTL GPIO Hibernate pin status low register 0 0 00 031A GPSICTL GPIO serial interface control register 0x0B00 031C KEYEN Keyboard scan pin enable register 0 0 00 0320 PCSOSTRA Programmable chip select 0 start address register 0 0 00 0322 PCSOSTPA 0 0 00 0324 PCSOHIA Programmable chip select 0 stop address register Programmable chip select 0 high address register 0 0 00 0326 PCS1STRA 0 0 00 0328 PCS1STPA Programmable chip select 1 start address register Programmable chip s
179. ER 13 GENERAL PURPOSE I O UNIT GIU 13 3 9 GPINTTYPH 0 0 00 0310 1 2 Name H5TYP1 H5TYPO 114 1 114TYPO 113TYP1 11 112 1 112 R W R W R W R W R W R W R W R W R W RTCRST Other resets 111 110 1 110 I9TYP1 I9TYPO 8 1 8 R W R W R W R W R W R W R W R W RTCRST Other resets Function 115 1 0 These bits define the type of interrupt generated when the GPIO15 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 14 1 0 These bits define the type of interrupt generated when the GPIO14 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 1 1 0 These bits define the type of interrupt generated when the GPIO13 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt M2TYP 1 0 These bits define the type of interrupt generated when the GPIO12 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 1
180. ERON Output 1 1 _ FF ff MPOWER Output ColdReset Internal Oo Reset Internal gt Stable oscillation 7 PLL Internal r ff Undefined Stable oscillation RTC Internal hes 32 768 kHz A lt gt Undefined lt gt gt gt 32 MS 16ms 2 600 ms 350 ms 16MasterClock ete Note MasterClock is the basic clock used in the CPU core Its frequency is one forth of TClock frequency User s Manual U14272EJ3VOUM 97 CHAPTER 5 INITIALIZATION INTERFACE 5 1 2 RSTSW reset After the RSTSW pin becomes active and then becomes inactive 100 us later the 4181 starts PLL oscillation and starts all clocks a period of about 16 ms following the start of PLL oscillation is required for stabilization of PLL oscillation An RSTSW reset basically initializes the entire internal state except for the RTC timer the GIU and the PMU The Vn4181 has function to preserve DRAM data during RSTSW reset For detail refer to CHAPTER 10 POWER MANAGEMENT UNIT PMU After a reset the processor becomes the system bus master which executes a Cold Reset exception sequence and begins to access the reset exception vectors in the ROM space Since only part of the internal status is reset when a reset occurs in the Vn4181 the processor should be completely initialized by software see 5 4 Notes on Initialization Figure 5 2
181. Eee teda 95 4 6 DRAM Address 388 euet Pane ROB GINE RC ERROR 95 6 1 Bus Control Registers i ede ae P epe 110 6 2 Vgp4181 EDO DRAM Gapacily ee erreichen ctt dete dit 129 6 3 Memory Controller Registers 12 4 2 tT UR d edi dure ce eee t 131 6 4 ISA Bridge Registers ince d fatui eu ettet aedi dated tuse ers 137 7 1 DECU Registers i n d EH Gd enc ede Hn S e Ces 144 8 1 GSERBegisters oon n REM 160 9 1 IG Registers xe Se thier er e hb tur ee MEL eie bdo dee Sete da 173 10 1 Overview of Power Modes 190 10 2 Operations During Reset eese mme E HERR ERI 191 10 3 Operations During Shutdown ssssssssssssesseseseeeneene 193 104 amp ett t en ot tette pee cei et oue oth ce Atte tt 208 11 1 RIC Regisleis d eec et o rm t bai tte leoni ie ee 216 12 1 DSU Registers ere e ee HERE eed HE EE HY Te RR cp EHE TOR e eee 230 13 1 Alternate Functions of GPIO 15 0 4 0 0000 00 nennen nnne nnne 236 13 2 Alternate Functions of GPIO 31 16 237 19 3 t CSlInterface Sign ls te tete mp be e le e hic e Pe cre Po Lb Te lE fu E Geet 238
182. FACE UNIT KIU 16 3 Register Set The KIU registers are listed below Physical address 0x0B00 0180 Table 16 2 KIU Registers Register symbol KIUDATO Function Scan line 0 keyboard data register 0 0 00 0182 0x0B00 0184 KIUDAT1 KIUDAT2 Scan line 1 keyboard data register Scan line 2 keyboard data register 0 0 00 0186 KIUDAT3 Scan line 3 keyboard data register 0 0 00 0188 KIUDAT4 Scan line 4 keyboard data register 0x0B00 018A KIUDATS Scan line 5 keyboard data register 0x0B00 018C KIUDAT6 Scan line 6 keyboard data register 0x0B00 018E R R R R R R R R KIUDAT7 Scan line 7 keyboard data register 0 0 00 0190 KIUSCANREP Scan control register 0x0B00 0192 KIUSCANS Scan status register 0 0 00 0194 KIUWKS Key scan stable time register 0 0 00 0196 KIUWKI Key scan interval time register 0x0B00 0198 KIUINT Interrupt register State of interrupt requests caused by KIU is indicated and can be set in the following registers which are included in the ICU refer to CHAPTER 9 INTERRUPT CONTROL UNIT ICU for details 0 0 00 0086 Table 16 3 KIU Interrupt Registers KIUINTREG KIU interrupt indication register 0 0 00 0092 MKIUINTREG KIU interrupt mask register User s Manual U14272EJ3VOUM 321 CHAPTER 16 KEYBOARD INTERFACE UNIT KIU 16 3 1 KIUDATn 0 0 00 0
183. FIFO polling mode Because the transmit block and receive block are controlled separately polling mode can be set for either or both blocks When in this mode the status of the transmit block and or receive block can be checked by reading the SIULS 2 register via a user program When in the FIFO polling mode there is no notification when the trigger level is reached or when a timeout occurs but the receive FIFO and transmit FIFO can still store characters as they normally do User s Manual U14272EJ3VOUM 389 CHAPTER 20 SERIAL INTERFACE UNIT 2 512 20 3 8 SIULC 2 0 0 00 0003 Name R W RTCRST Other resets Function 7 LCR7 Divisor latch access register switching 1 Divisor latch access register 0 Receive buffer transmit holding register interrupt enable register 6 LCR6 Break control 1 Set break 0 Clear break 5 LCR5 Parity fixing 1 Fixed parity 0 Parity not fixed 4 LCR4 Parity setting 1 Even parity 0 Odd parity 3 LCR3 Parity enable 1 Create parity during transmission or check parity during reception 0 No parity during transmission or no checking during reception 2 LCR2 Stop bit specification 1 1 5 bits character length is 5 bits 2 bits character length is 6 7 or 8 bits 0 1 bit 1 0 LCR 1 0 Specifies the length of one character number of bits 11 8 bits 10 7 bits 01 6 bits 00 5 bits This register is used
184. FPD5 Output FPD4 Output SHCLK x W x 3 8 pulses Remark W panel width Hact 5 0 x 8 The polarity order of rising and falling edges of the LOCLK and the SHCLK are programmable via the LPPOL and SCLKPOL bits Remark In the color 8 bit data bus mode FPD 3 0 are for upper 4 bits of the LCD data bus and FPD 7 4 are for lower 4 bits of the LCD data bus User s Manual U14272EJ3VOUM 409 CHAPTER 21 LCD CONTROLLER Figure 21 7 Load Clock LOCLK LOCLK Output Pixel row LOCLK x H pulses LOCLK x TH H pulses Remark panel height Vact TH panel height dummy lines Vtotal Remark Dummy lines are inserted when needed For example some panels can display only 240 lines but has 242 line cycles Load clock can be deactivated during the dummy lines see DummyL bit description in 21 4 6 Figure 21 8 Frame Clock FLM FLM Output Pixel row TH 1 TH 1 0 Remark YS Y Coordinates of the second FLM edge FLMS YE Y Coordinates of the first FLM edge FLME The polarity order of rising and falling edges of the FLM is programmable via the FLMPOL bit 410 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER Figure 21 9 LCD Timing Parameters LOCLK Output lt B Te T7 FLM Output p T9 SHCLK Output FPD 7 0 Output The polarity of the FLM is programmable t
185. G bit manipulation Scan sequencer s state Interval ADPScan CMDScan Note2 ADPSSTART ADPScan ADPScan TPPSCAN Notes 1 Immediately after a transition to the ADPScan state the bit is automatically cleared to 0 2 After ADPScan is completed the sequencer returns to the state in which the scan has started Remark The bit change is retained but there is no state transition x Setting prohibited operation not guaranteed Combination of state and bit status before setting does not exist 290 User s Manual U14272EJ3VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 3 7 PIUAMSKREG 0 0 00 0132 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets Name ADINM3 ADINM2 ADINM1 ADINMO TPYM1 TPYMO TPXM1 TPXMO R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Function Reserved 0 is returned when read ADINM3 Audio input port mask 1 Mask 0 Normal ADINM 2 0 General purpose A D port mask 1 Mask 0 Normal TPYM 1 0 Touch panel A D port TPY mask 1 Mask 0 Normal TPXM 1 0 Touch panel A D port TPX mask 1 Mask 0 Normal This register is used to set masking each A D port Each bit corresponds to one port If masked A D conversions are not performed for data of the corresponding port Settings in this register
186. HAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 9 KIUINTREG 0 0 00 0086 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Reserved Function 0 is returned when read KDATLOST Keyboard Data Lost interrupt request This interrupt request occurs if the KIUDATO register is updated with the next key data prior to being read by the CPU core 0 Not occurred 1 Occurred This bit is cleared by writing 1 KDATRDY Keyboard Data Ready interrupt request This interrupt request occurs when a set of scanning is completed and all the KIUDAT registers are updated 0 Not occurred 1 Occurred This bit is cleared by writing 1 KDOWNINT Key Down interrupt request This interrupt request occurs when the KIU sequencer is idle and any of the SCANIN inputs has been sampled as low level 0 Not occurred 1 Occurred This bit is cleared by writing 1 The KDATLOST bit is also cleared when the KIUDATO register is read 184 User s Manual U14272EJ3VOUM CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 10 MPIUINTREG 0 0 00 008 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets PADCMD PADADP PADPAGE1 PADPAGEO PADDLOST PENCHG INTR INTR INTR INTR INTR INTR RTCRST Other
187. IME33 ETIME32 R W R W R W R W R W R W R W R W RTCRST Other resets 15 to 0 ETIME 47 32 ElapsedTime timer bits 47 to 32 Note Continues counting These registers indicate the ElapsedTime timer s value They count up by a 32 768 kHz clock cycle and when a match occurs with the ElapsedTime compare registers an alarm ElapsedTime interrupt occurs and the counting continues A write operation is valid once values have been written to all registers ETIMELREG ETIMEMREG and ETIMEHREG These registers have no buffers for read Therefore an illegal data may be read if the timer value changes during a read operation When using the read value as a data be sure to read these registers twice and check that two read vales are the same When setting these registers again wait until at least 100 5 three cycles of 32 768 kHz clock have elapsed after the first setting 218 User s Manual U14272EJ3VOUM CHAPTER 11 REALTIME CLOCK UNIT 11 2 2 ElapsedTime compare registers 1 ECMPLREG 0 0 00 00 8 Name ECMP15 14 ECMP13 ECMP12 ECMP 1 1 ECMP10 ECMP9 ECMP8 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Name R W RTCRST Other resets 15100 15 0 Note Holds the value before reset 2 ECMPMREG 0 0 00 00CA Name ECMP31 ECMP30 Value to b
188. IO pin has not been enabled to provide DSR2 the DSR2 input to the serial interface channel 2 is driven with the value of this bit REGDCD2 DCD2 data When a GPIO pin has not been enabled to provide DCD2 the DCD2 input to the serial interface channel 2 is driven with the value of this bit 266 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 15 KEYEN 0 0 00 031C Name KEYSEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W R W RTCRST Other resets CFHIBEN R W RTCRST Other resets Function KEYSEL Keyboard scan pin enable This bit causes the pins assigned to support the CompactFlash interface to be redefined to support the keyboard scan interface 0 CompactFlash interface enabled 1 Keyboard scan interface enabled Reserved 0 is returned when read CFHIBEN CompactFlash interface enable during Hibernate mode 0 Disable 1 Enable Reserved 0 is returned when read Note Holds the value before reset The GIU only provides an internal output signal keysel when the KEYSEL bit is set to 1 An external logic is responsible for multiplexing the pin inputs and pin outputs and buffer enable control from the ECU and the KIU When the CompactFlash interface is enabled during Hibernate mode a high to low transition on the CompactFlash CF_BUSY pin will cause the 4181 to wake up and return
189. ITGENCTREG register is cleared to 0 and the 5 5 signal is at low level When this bit is set to 1 the system software then has to read the status change register in the I O card to determine the cause of STSCHG Caution CompactFlash cards do not support the BVD battery status detection signal so that the BVD2 SPKR signal of the ECU is internally fixed to low level This register indicates the source of the card status change interrupt request Each source can be enabled to generate this interrupt request by setting the corresponding bit in the CRDSTATREG register The bits in this register become 0 if their corresponding enable bits are cleared to 0 If the EXWRBK bit is set to 1 in the GLOCTRLREG register sources for the card status change interrupt request is acknowledged when 1 is set to the bit in the CDSTCHGREG register though it has been already set to 1 Once acknowledged the CD bit is cleared to 0 The interrupt request signal caused by the card status change if any of the IRQ lines is enabled remains active until all the bits in this register become 0 If the EXWRBK bit is not set to 1 the card status change interrupt request when any of the IRQ lines are enabled remains active until this register is read In this mode reading this register resets all status bits to 0 which has been set to 1 338 User s Manual U14272EJ3VOUM CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 6 CRDS
190. L OGTRERBEOG ECRIRE 348 iere eb eed 59 GPDATHRBEQ 1 dpi UR 254 GPDATEREQ eh vide 255 GPHIBSTH uim eoe 263 GPRHIBSTE 32 52 deu 264 t itte eet eleg 256 GPINIMSK tiit eet e atte 257 GPINTSTAT ideis 262 nei ritu eee ets 258 GPINTEEYPIEm iit tii BER 260 GPMDOREG eid etes 246 440 User s Manual U14272EJ3VOUM APPENDIX B INDEX 248 2 250 22 5 pee teat 252 cit anes ated trc s 265 H 2 aisi n 42 iios 106 436 HALTimer shutdown 101 193 EEE A nite 37 Hibernate mode 45 191 437 EE 201 202 exilirig eine eae 203 204 horizontal 402 HRTOTALERE 2 inte 414 5 Le dette os 414 171 IGUiregiSte hice nates ertet tet 173 IDL REV REG eine dene lane 334 IE STATZBEQG 335 Index register n nete ee ene 69 initialization 44 44222222 96 initialization interface signals 55 instruction 38 46 internal bus 31
191. LEDLTSREG and LEDASTCREG registers The operation is not guaranteed if zero is set to these registers 356 User s Manual U14272EJ3VOUM CHAPTER 18 LED CONTROL UNIT LED 18 2 4 LEDASTCREG 0 0 00 024A RTCRST Other resets RTCRST Other resets 15100 ASTC 15 0 LED auto stop time count This register is used to set the number of ON OFF times prior to automatic stopping of LED blink The set value is read on read The initial setting is 1 200 times of ON OFF pairs i e one hour in which each time includes one second of ON time and two seconds of OFF time The pair of operations in which the LED is switched ON once and OFF once is counted as 1 by this counter The counter counts down from the set value and an LEDINT interrupt request occurs when it reaches zero Caution Setting a zero to this register is prohibited The operation is not guaranteed if zero is set to this register User s Manual U14272EJ3VOUM 357 CHAPTER 18 LED CONTROL UNIT LED 18 2 5 LEDINTREG 0 0 00 024C Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Function Reserved 0 is returned when read LEDINT Auto stop interrupt request Cleared to 0 when 1 is written 1 Occurred 0 Not occurred This register indicates when an auto stop interrupt request has occur
192. LS 1 0 0 00 0015 Name R W RTCRST Other resets Function Error detection FIFO mode 1 Parity error framing error or break is detected 0 No error Transmit block empty 1 No data in transmit holding register and transmit shift register No data in transmit FIFO during FIFO mode Data exists in transmit holding register or transmit shift register Data exists in transmit FIFO during FIFO mode Transmit holding register empty 1 Character is transferred to transmit shift register during 16450 mode Transmit FIFO is empty during FIFO mode 0 Character is stored in transmit holding register during 16450 mode Transmit data exists in transmit FIFO during FIFO mode Break interrupt 1 Detected 0 No break Framing error 1 Detected 0 No error Parity error 1 Detected 0 No error Overrun error 1 Detected receive data is overwritten 0 No error Receive data ready 1 Receive data exists in FIFO 0 No receive data in FIFO The CPU uses this register to get information related to data transfers When LSR7 and LSR 4 1 bits are 1 reading this register clears these bits to 0 Caution The 15 0 bit receive data ready bit is set before the serial data reception is completed Therefore the LSRO bit may not be cleared if the serial receive data is read from the SIURB 1 register immediately after this bit is set When reading data from t
193. M 129 6 4 3 EDO DRAM timing parameters esssseeeeneeeeenenenneeen nene nennen neret rennen 129 6 4 4 SDRAM configuration sasra E IE Aa iisa i harien aE Pas sette eren nenne nnns 130 6 5 Memory Controller Register Set 131 6 5 1 EDOMCYTREG 0x0A00 0300 sn 2n eec qeu acere i ee e e eine 131 6 5 2 MEMCFG REG 0x0A00 0304 133 6 5 3 REG 0x0A00 0908 ie utu eu aite es 135 6 5 4 SDTIMINGREG 0x0A00 030 6 136 60 ISA Bridge od ee 137 User s Manual U14272EJ3VOUM 15 6 7 ISA Bridge Register Idus de peel us 137 6 71 ISABRGCTE40x0BO00 0260 ERI Oe ERREUR ORO 138 6 7 2 ISABRGSTS 0x0B00 02 2 pereat re nla D dee petite 139 6 7 3 XISACTE 0x0BO00 026G4 A 140 CHAPTER 7 DMA CONTROL UNIT 2 1112 142 rec unlcgm 142 7 2 DEUS REGISUCKS m MEER 144 7 2 1 Microphone destination 1 address registers 145 7 2 2 Microphone destination 2 address registers ssssee mee 146 7 2 3
194. MBA address 109 MBA DbUS ieri decus 108 Host Bridge apes 108 MONTREG canadien 310 END it reto d ein 314 304 MEMGFEG eA a ae 133 MEMOFFHnREG 0 to 4 346 MEMOFFLnREG n 0 to 4 346 memory 337 338 memory controller 106 131 memory management 44 91 memory mapping 118 350 memory 350 MEMSELnREG 0 to 4 345 MEMWIDnREG n 0 to 4 344 22 145 2 sit nih 145 MIGDEST2HEQ 146 MICDEST2REG2 iieri 146 MICDMACFGREG eee 151 MICRCLENREG eese 150 microphone cerne ettet nens 301 316 MIDATREQ nece ite o Pleite is 309 MIPS instructions 2 2 38 MIPS16 39 MISCREGn n 0 to 15 274 mixed memory 129 MKIUINITREIEG 187 MODE HREQG 1 nte seeundum 135 monochrome panel
195. MD1A19 MD1A18 MD1A17 MD1A16 R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 MD1A 31 16 Upper 16 bits A 31 16 of DMA destination 1 address for Microphone These two registers specify the destination memory address of the primary DMA buffer for the Microphone channel User s Manual U14272EJ3VOUM 145 CHAPTER 7 DMA CONTROL UNIT DCU 7 2 2 Microphone destination 2 address registers 1 MICDEST2REG1 0x0A00 0024 Name MD2A15 MD2A14 MD2A13 MD2A12 MD2A11 MD2A10 MD2A9 MD2A8 R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 Name R W At reset MD2A 15 0 Lower 16 bits A 15 0 of DMA destination 2 address for Microphone 2 MICDEST2REG2 0x0A00 0026 Name MD2A31 MD2A30 MD2A29 MD2A28 MD2A27 MD2A26 MD2A25 MD2A24 R W At reset Name MD2A23 MD2A22 MD2A21 MD2A20 MD2A19 MD2A18 MD2A17 MD2A16 R W R W R W R W R W R W R W R W R W At reset 0 0 0 0 0 0 0 0 MD2A 31 16 Upper 16 bits A 31 16 of DMA destination 2 address for Microphone These two registers specify the destination memory address of the secondary DMA buffer for the Microphone channel 146 User s Manual U14272EJ3VOUM CHAPTER 7 DMA CONTROL UNIT DCU 7 2 3
196. NKI iioii eei 326 KIUWKS nn idee tete tet 325 L 399 LCD controller 413 EC D nterface secte 34 241 399 LCD interface Signals 4 54 L GD panel z 34 399 LGDCFGREGO0 ncn 420 LODCFGOGREG I 421 GDGTREREG 418 EGDGPMOBDE eg a ied 273 UODIMSKREQ iiir peine eet deett 427 LCDINRQREOG iiie 419 EDGEKENDREDG 1a et rendre 415 EDGEKSTREG 5 3 ne ni enum 415 LEDs noe e 353 operation OW 359 LED controlunit 353 LED interface signals 56 lE Dreglsters ia eet ect 353 FEDASTGREG ccna e Rete 357 Ie dpi tt 356 EEDEHTSRBEQ iis 354 FEDINTREG eoe 358 EEDBEESBEG Z te aee 355 little endlan urere 40 444444244 242 84 l O reglSter c e Ana d 37 load Clock Tt tote teri 403 410 local loopback oie 372 391 intei tette Mes 403 410 User s Manual U14272EJ3VOUM 441 APPENDIX B INDEX M M sigtial iet REB 405 MAIUINTRE G tre rode tette tee 186 manual scan 420 4 22222 318
197. O pin The interrupt mask register GPINTMSK permits temporary masking of an interrupt request for a particular GPIO pin The interrupt type registers GPINTTYPH and GPINTTYPL define the interrupt trigger type edge or level and the level type polarity of the interrupt requests input to the GPIO pin The interrupt status register GPINTSTAT allows software to determine the source of the GPIO interrupt request The functions of the enable mask polarity and type bits are shown in the following figure Figure 13 1 GPIO 15 0 Interrupt Request Detecting Logic Other GPIO interrupt requests 34 Mask bit Level triggered interrupt request GPIOINTR Enable bit GPIO input Polarity bit gt Note Edge triggered interrupt request Type bit During Hibernate mode any one of the GPIO 15 0 inputs can be used as a wake up event Wake up event notification is asynchronous and output on the GPWAKEUP signal internal following conditions must be met To enable GPIO wake up events the 1 Interrupt requests to the GPIO pin must be enabled set in the GPINTEN register 2 Interrupt requests to the GPIO pin must be unmasked set in the GPINTMSK register 3 The GPIO pin must be enabled during Hibernate mode set in the GPHIBSTL register Note The state of this signal is displayed on the GPWAKEUP bit of the PMUINTREG register in the PMU User s Manual U14272EJ3VOUM 243 CHAPTER 13 GENERAL PURPOS
198. PEND bit in the DRAMHIBCTL register to 0 to exit self refresh mode 10 Set the EDOMCYTREG and MEMCFG REG registers in the memory controller according to the DRAM type to be used 11 If DRAM can accept mixed use of burst and distributive CBR refresh set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge Then execute CBR refresh cycles for a specific time period i e OXGFFF x TClock period burst refresh interval required by DRAM 12 Restore to the BCURFCNTREG register in the MBA Host Bridge a value that determines refresh interval satisfying the conditions of DRAM type to be used User s Manual U14272EJ3VOUM 203 CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 6 4 Exiting Hibernate mode SDRAM 204 1 2 3 4 5 6 lt gt lt 8 gt lt 9 gt Generate a wake up event such as a transition on the POWER pin a DCD interrupt etc which causes the PMU to start a power on sequence Apply 2 5 V power supply when the MPOWER signal becomes high level The PMU waits until 3 3 V and 2 5 V power supply are stable and then deasserts the reset signals to the Vn4110 CPU core and on chip peripheral units Software execution resumes at the Cold Reset exception vector OxOBFC 0000 Initialize the cache tags and the Config Status and WatchLo registers in the CPO Reset the HALTimer by setting the HALTIMERRST bit in the PMUCNTREG regi
199. PIO20 M Hi Z Hi Z 1 Note 1 0 Hi Z Note 3 0 RESET GP1021 Hi Z Hi Z Note 1 0 Note 3 ROMCS 2 0 GPIO 24 22 Hi Z Hi Z 1 Note 1 Hi Z Note 3 ROMCS3 Hi Z Hi Z 1 1 Hi Z SHCLK LCDCS Hi Z 0 0 1 0 1 O Hi Z LOCLK MEMCS16 Hi Z 0 0 0 0 FLM MIPS16EN Note 4 0 0 0 0 FPD 3 0 Hi Z 0 0 0 0 VPLCD VPGPIO1 Hi Z Hi Z Hi Z Hi Z Hi Z VPBIAS VPGPIOO Hi Z Hi Z Hi Z Hi Z Hi Z POWER RTCRST RSTSW Notes1 Maintains the state of the previous Fullspeed mode 2 The state depends on the MEMCFG_REG register setting 3 The state depends on the GPHIBSTH GPHIBSTL register setting 4 The input level is sampled to determine the MIPS16 instruction mode Remark 0 low level 1 high level Hi Z high impedance 60 User s Manual U14272EJ3VOUM CHAPTER 2 PIN FUNCTIONS After RTC Reset Signal Name During RTC Reset After Reset by Deadman s Switch or RSTSW POWERON During Suspend Mode 2 3 During Hibernate Mode or Shutdown by HALTimer MPOWER BATTINH BATTINT RTCX2 RTCX1 CLKX2 CLKX1 2 0 AUDIOIN AUDIOOUT CF WEZ SCANOUT7 Note 2 Hi Z CF OEZ SCANOUT6 Note 2 Hi Z CF IOWZ SCANOUT5 Note 2 Hi Z CF IORZ SCANOUTA Note 2 Hi Z CF STSCHGZ SCANOUTS Note 1 Hi Z CF_CE 2 1 SCANOUT 2 1 Note 2 Hi Z CF_BUSY SCANOUTO Note 1 Hi Z CF_REG SCANIN7 Note 2 Note 1 CF_RESET SCANIN6
200. PIU reset Once the PADRST bit is set to 1 it is automatically cleared to 0 after four TClock cycles 1 Reset 0 Do not reset This register is used to make various settings for the PIU The PENSTC bit indicates the touch panel contact status at the time when the PENCHGINTR bit of the PIUINTREG register is set to 1 This bit s state remains as it is until the PENCHGINTR bit is cleared to 0 Also when the PENCHGINTR bit is cleared to 0 the PENSTC bit indicates the touch panel contact status at that time However the PENSTC bit does not change while the PENCHGINTR bit is set to 1 even if the touch panel contact status changes between release and touch Some bits in this register cannot be set in a specific state of scan sequencer The combination of the setting of this register and the sequencer state is as follows 282 User s Manual U14272EJ3VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU PIUCNTREG bit manipulation Note1 PADRST Table 14 3 PIUCNTREG Bit Manipulation and States Disable Scan sequencer s state Standby Disable WaitPenTouch Disable DataScan Disable PIUPWR Standby x Disable PIUSEQEN x WaitPenTouch Standby PADATSTART Note2 DataScan PADATSTOP x PADSCANSTART lote3 DataScan i PADSCANSTOP PIUCNTREG bit manipulation te PADRST ted Standby Scan seque
201. R 6 BUS CONTROL 3 32 Mbit PageROM Remark The maximum burst number when using a PageROM is 8 halfwords i e 128 bits 1 word 32 bits ADD 20 3 ROMCSO DATA 15 0 User s Manual U14272EJ3VOUM 121 CHAPTER 6 BUS CONTROL 4 64 Mbit PageROM Remark The maximum burst number when using a PageROM is 8 halfwords i e 128 bits 1 word 32 bits ADD 21 3 ROMCSO DATA 15 0 122 User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 5 32 Mbit flash memory when using Intel DD28F032 ADD 19 0 A 20 1 CE2 CE1 Flash memory Flash RDY BSY ROMCSO s CEO MEMWR WE MEMRD OE A 20 1 CE2 CE1 Flash memory Bank1 RDY BSY CEO WE OE A 20 1 CE2 CE1 Flash memory Bank2 RDY BSY CEO WE OE DATA 15 0 Note There is no corresponding pin in the 4181 Use one of the GPIO pins for this function Remark Use one of the GPIO pins in the 4181 to control ON OFF of Ver program erase supply voltage A 20 1 CE2 CE1 Flash memory Bank3 RDY BSY CEO WE OE User s Manual U14272EJ3VOUM 123 CHAPTER 6 BUS CONTROL 6 64 Mbit flash memory when using Intel StrataFlash 28F640J5 ADD 21 0 Flash StatusNete A 21 0 CE2 CE1 Flash memory Bank1 STS CEO WE OE A 21
202. R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Function Reserved 0 is returned when read PENSTC Touch release status when touch panel contact state changes 1 Touch 0 Release 12 to 10 PADSTATE 2 0 Scan sequencer status 111 CMDScan 110 Interval 101 DataScan 100 WaitPenTouch 011 RFU 010 ADPScan 001 Standby 000 Disable PADATSTOP Sequencer auto stop setting during touch panel release status 1 Auto stop after sampling data for one set of coordinates 0 No auto stop PADATSTART Sequencer auto start setting during touch panel touch status 1 Auto start 0 No auto start PADSCANSTOP Forced stop setting for touch panel sequencer 1 Forced stop after sampling data for one set of coordinates 0 Do not stop User s Manual U14272EJ3VOUM 281 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 2 2 Function PADSCANSTART Start setting for touch panel sequencer 1 Forced start 0 Do not start PADSCANTYPE Touch pressure sampling enable 1 Enable 0 Disable PIUMODE 1 0 PIU mode setting 11 RFU 10 RFU 01 Operates A D converter using any command 00 Samples coordinate data PIUSEQEN Scan sequencer operation enable 1 Enable 0 Disable PIUPWR PIU power mode setting 1 Sets PIU output as active and puts into standby status 0 Sets panel to touch detection status and set PIU operation stop enabled status PADRST
203. R signal becomes high level The PMU waits until 3 3 V and 2 5 V power supply are stable and then deasserts the reset signals to the Vr4110 CPU core and on chip peripheral units lt 3 gt Software execution resumes at the Cold Reset exception vector OxOBFC 0000 Initialize the cache tags and the Config Status and WatchLo registers in the CPO Reset the HALTimer by setting the HALTIMERRST bit in the PMUCNTREG register to 1 4 Check and clear the TIMOUTRST bit in the PMUINTREG register in the case a HALTimer Shutdown had occurred b the codes for the restore 6 through 12 below beginning at a 16 byte boundary into the cache by using a Fill operation of CACHE instruction and jump to the cached codes These codes can be executed on ROM 6 Pollthe OK STOP CLK bit in the DRAMHIBCTL register until it is set to 1 7 Reinitialize all the registers and peripherals during Hibernate mode and restore those registers saved in the general purpose registers MISCREG 0 15 which retain values during Hibernate mode in the GIU or in external memory Remark Software must wait until the OK STOP CLK bit in the DRAMHIBCTL register is set to 1 before reinitializing the memory controller registers Otherwise unpredictable behavior of the memory controller could result 8 Clear the DRAM EN bit in the DRAMHIBCTL register to 0 so that the DRAM interface signals are again driven directly by the memory controller 9 Clear SUS
204. RAM 2 205 10 6 6 Entering Suspend mode 5 206 10 6 7 Exiting Suspend mode EDO DRAM 2 nennen nennen nennen 207 10 6 8 Exiting Suspend mode SDRAM sessi nnne 207 10 7 Register Set ieu e 208 10 71 PMUINTREG 0x0BO00 OQAQ tee tecto 209 10 7 2 PMUCNTREG 0 0 00 00A2 211 10 7 3 PMUWAITREG 0 0 00 00 8 213 10 7 4 PMUDIVREG 0 0 00 OOAC 200242010140 00 000 0000 214 10 7 5 DRAMHIBCTL 0 0 00 00B2 2 20222014 0 0 1 000 215 User s Manual U14272EJ3VOUM 17 CHAPTER 11 REALTIME CLOCK UNIT enneunen 216 117 EM 216 11 2 Register Set tee tete taedet emm 216 11 2 1 ElapsedTime registers ae eee er eee 217 11 2 2 ElapsedTime compare registers 219 11 2 3 R TOL ongTitegistets p EROR he RA RR e eb RR NERA ES 221 11 2 4 RTObEong1 count registers echt e ede dee veste Eee dep ee deeds 223 11 2 5 RT GL ong2 registets 5 ea e ne D ete 225 11 2 6 RTGLong2 countregisters 5
205. RAM column address strobe Leave unconnected when using EDO DRAM SDRAS Output SDRAM row address strobe Leave unconnected when using EDO DRAM UDQM UCAS Output SDRAM upper byte enable or EDO DRAM upper byte column address strobe LDQM LCAS Output SDRAM lower byte enable or EDO DRAM lower byte column address strobe SDCLK Output SDRAM operating clock CLKEN Output SDRAM clock enable output ROMCS3 Output ROM chip select output for bank 3 ROMCS2 GPIO024 VO ROM chip select output for bank 2 or general purpose I O ROMCS1 GPIO23 VO ROM chip select output for bank 1 or general purpose I O ROMCSO GPIO22 VO ROM chip select output for bank 0 or general purpose I O MEMRD Output Memory read signal for ROM and system bus MEMWR Output Memory write signal for ROM DRAM and system bus Note The SYSEN and SYSDIR signals control a buffer which is used to isolate SDRAM data bus from the bus of other low speed devices By isolating the high speed data bus of SDRAM the load of the data bus between the 4181 and SDRAM is reduced When the EXBUFFEN bit of the XISACTL register is cleared to 0 the SYSEN and SYSDIR signals start their operation These signals keep low level until EXBUFFEN bit is cleared to 0 after a reset When an isolation buffer is used SYSEN and SYSDIR signals function as follows SYSEN SYSDIR Bus operation External ISA CompactFlash or ROM read cycle
206. REG Interrupt and general control register 0x0004 CDSTCHGREG Card status change register 0x0005 CRDSTATREG Card status change interrupt configuration register 0x0006 ADWINENREG Address window enable register 0x0007 IOCTRL REG control register 0x0008 IOADSLBOREG start address 0 low byte register 0x0009 IOADSHBOREG start address 0 high byte register 0x000A IOSLBOREG I O stop address 0 low byte register 0x000B IOSHBOREG stop address 0 high byte register 0x000C IOADSLB1REG I O start address 1 low byte register 0x000D IOADSHB1REG I O start address 1 high byte register 0 000 IOSLB1REG stop address 1 low byte register 0x000F IOSHB1REG stop address 1 high byte register 0x0010 SYSMEMSLOREG System memory 0 mapping start address low byte register 0x001 1 MEMWIDO REG System memory 0 mapping start address high byte register 0x0012 SYSMEMELOREG System memory 0 mapping stop address low byte register 0x0013 MEMSELO REG System memory 0 mapping stop address high byte register 0x0014 MEMOFFLOREG Card memory 0 offset address low byte register 0x0015 MEMOFFHOREG Card memory 0 offset address high byte register 0x0016 DTGENCLREG Card detect and general control register 0x0018 SYSMEMSL1REG System memory 1 mapping start address low byte register 0x0019 MEMWID1 REG System memor
207. RST Other resets Function Reserved 0 is returned when read DEDTIME 3 0 Deadman s Switch cycle setting 1111 15 seconds 1110 14 seconds 0010 2 seconds 0001 1 second 0000 Setting prohibited This register is used to set the cycle for Deadman s Switch function The Deadman s Switch cycle can be set in 1 second units in a range from 1 to 15 seconds The DSWCLR bit in the DSUCLRREG register must be set by means of software within the cycle time specified in this register The Vn4181 s operation is undefined when 0x0 has been set to DEDTIME 3 0 232 User s Manual U14272EJ3VOUM CHAPTER 12 DEADMAN S SWITCH UNIT DSU 12 2 3 DSUCLRREG 0 0 00 00 4 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Function Reserved 0 is returned when read DSWCLR Deadman s Switch timer clear 1 Clear stops timer 0 Timer counting Deadman s Switch timer is cleared by setting the DSWCLR bit in this register to 1 The Vr4181 automatically enters in a Cold Reset status if 1 is not written to this register within the period specified in the DSUSETREG register In order to restart operation of the timer the DSWCLR bit in this register must be cleared to 0 User s Manual U14272EJ3VOUM 233 CHAPTER 12 DEADMAN S SWITCH UNIT DSU 12 2 4 DSUTIMREG 0 0 00
208. Reset SJ S RSTSW4 Input H POWER Input L SS 5 2 S MPOWER Output H lt _ ColdReset Internal mE NE Reset Internal 27 UL Undefined Stable oscillation RTC Internal WLLL 32 768 kHz Stable oscillation 16 ms 16MasterClockNete Note MasterClock is the basic clock used in the CPU core Its frequency is one forth of TClock frequency User s Manual U14272EJ3VOUM 99 CHAPTER 5 INITIALIZATION INTERFACE 5 1 4 Software shutdown When the software executes the HIBERNATE instruction the VR4181 sets the MPOWER pin as inactive then enters reset status Recovery from reset status occurs when the POWER pin or DCD signal is asserted or when unmasked wake up interrupt request is occurred A reset by software shutdown initializes the entire internal state except for the RTC timer the GIU and the PMU After a reset the processor becomes the system bus master which executes a Cold Reset exception sequence and begins to access the reset vectors in the ROM space Since only part of the internal status is reset when a reset occurs in the Vn4181 the processor should be completely initialized by software see 5 4 Notes on Initialization Cauiton The Vn4181 does not set the DRAM to self refresh mode at the transition to Hibernate mode from Fullspeed mode To preserve DRAM data software must set the DRAM to self refresh m
209. S3 Ox1FBF FFFF to 0x1F80 0000 Bank 2 ROMCS2 When using 64 Mbit ROM Bank 3 ROMCS3 Ox1F7F FFFF to 0x1F40 0000 Bank 1 ROMCS1 Ox1FSF FFFF to 0x1F00 0000 Bank 0 ROMCSO Bank 2 ROMCS2 Ox1EFF FFFF to 0x1E80 0000 Reserved for future use 0x1E7F FFFF to 0x1E00 0000 4 2 2 External system bus space The following two types of system bus space are available External system bus I O space This corresponds to the ISA s I O space External system bus memory space This corresponds to the ISA s memory space User s Manual U14272EJ3VOUM Bank 1 ROMCS1 Bank 0 ROMCSO 93 CHAPTER 4 MEMORY MANAGEMENT SYSTEM 4 2 3 Internal space 94 The 4181 has three internal spaces Each of these spaces is described below Table 4 3 Internal I O Space 1 Physical address Internal I O 0x0C00 001F to 0x0CO00 0010 SIU1 0x0C00 000F to 0x0CO00 0000 5102 Table 4 4 Internal I O Space 2 Physical address Internal 0 0 00 O9FF to 0x0BOO 0900 CSI 0 0 00 O8FF to 0x0BOO 0800 ECU 0 0 00 07FF to 0x0BOO 0400 Reserved for future use 0 0 00 to 0x0BOO 0300 GIU 0 0 00 2 to 0x0B00 0200 Reserved for future use 0 0 00 02CF to 0 0 00 02 0 ISA Bridge 0 0 00 02BF to 0 0 00 02 0 2 0 0 00 029F to 0 0 00 0280 Reserved for future use 0 0 00 027F
210. SH CONTROLLER 17 6 Controlling Bus When CompactFlash Card Is Used Access to the CompactFlash card is made via the ISA bridge The address data and command signals operate based on external ISA cycles The operations of the signals that control the bus size and wait state MEMCS16 10 516 and IORDY can be set in the ECU 17 6 1 Controlling bus size When the memory window is accessed the data bus width is set in the DWIDTH bit of the MEMWIDn REG register n 0 to 4 This setting is output from the ECU to the ISA bridge as the source of the MEMCS16 signal When the I O window is accessed the source of the data width is selected from the 516 signal or IOnDSZ bit n or 1 via the lOn CS16MD bit n 0 or 1 of the IOCTRL REG register If the CF IOIS167 signal is selected its status is output from the ECU to the ISA bridge as the source of the OCS16 signal If the IOnDSZ bit is selected the inverted setting of the IOnDSZ bit is output 17 6 2 Controlling wait The number of wait states of the external ISA cycle can be selected from four types by using the MEMWS 1 0 and IOWS 1 0 bits of the XISACTL register of the ISA bridge regardless of whether the memory or I O is accessed In addition the ECU deasserts the IORDY signal and extends the bus cycle if the CF WAIT signal from the CompactFlash card is asserted Additional wait states can be controlled by ECU settings 1 Wait when memory window is accessed Th
211. Serial Interface CSI peripheral clock PCLK 0 Mask 1 Supply MSKAIUPCLK Supply Mask Audio Interface AIU peripheral clock PCLK 0 Mask 1 Supply MSKPIUPCLK Supply Mask Touch Panel Interface PIU peripheral clock PCLK 0 Mask 1 Supply MSKADUPCLK Supply Mask A D converter and D A converter peripheral clock PCLK 0 Mask 1 Supply MSKSIU18M Supply Mask Serial Interface 1 and 2 SIU1 SIU2 18 432 MHz clock 0 Mask 1 Supply MSKADU18M Supply Mask A D converter and D A converter 18 432 MHz clock 0 Mask 1 Supply Reserved Write 0 when write 0 is returned when read This register is used to mask the clocks that are supplied to CSI AIU PIU SIU1 and SIU2 112 User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 6 2 3 BCUSPEEDREG 0x0A00 000C Name WPROM2 WPROM 1 WPROMO Reserved Reserved R W At reset R W At reset Reserved 0 is returned when read 14 to 12 WPROM 2 0 Page ROM access speed 000 1 5 TClock 001 2 5 TClock 010 3 5 TClock 011 4 5 TClock 100 5 5 TClock 101 6 5 TClock 110 7 5 TClock 111 8 5 TClock Reserved 0 is returned when read WROMA 3 0 ROM access speed 0000 1 5 TClock 0001 2 5 TClock 0010 3 5 TClock 0011 4 5 TClock 0100 5 5 TClock 0101 6 5 TClock 0110 7 5 TClock 0111 8 5 TClock 1000 9 5 TClock 1001 10 5 TClock 1010 11 5 TClo
212. Set How an interrupt request is notified to the CPU core is shown below If an interrupt request occurs in the peripheral units the corresponding bit in the interrupt indication register of Level 2 xxxINTREG is set to 1 The interrupt indication register is ANDed bit wise with the corresponding interrupt mask register of Level 2 MxxxINTREG If the occurred interrupt request is enabled set to 1 in the mask register the interrupt request is notified to the interrupt indication register of Level 1 SYSINTREG and the corresponding bit is set to 1 At this time the interrupt requests from the same register of Level 2 are notified to the SYSINTREG as a single interrupt request Interrupt requests from some units directly set their corresponding bits in the SYSINTREG The SYSINTREG is ANDed bit wise with the interrupt mask register of Level 1 MSYSINTREG If the interrupt request is enabled set to 1 in the MSYSINTREG a corresponding interrupt request signal is output from the ICU to the CPU core battintr is connected to the NMI or IntO signal of the CPU core selected by setting of NMIREG rtclong2 and rtclong1 signals are connected to the Int2 or Int1 signal of the CPU core The other interrupt requests are connected to the IntO signal of the CPU core as a single interrupt request The following figure shows an outline of interrupt control in the ICU Users Manual U14272EJ3VOUM 171 CHAPTER 9 INTERRUPT CONTROL UNIT ICU Figure 9 1 Ou
213. Succursale Francaise Tel 01908 691 133 Taipei Taiwan V lizy Villacoublay France Fax 01908 670 290 Tel 02 2719 2377 Tel 01 30 67 58 00 Fax 02 2719 5951 Fax 01 30 67 58 99 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 Fax 6250 3583 J02 11 User s Manual U14272EJ3VOUM Major Revisions in This Edition 1 5 Page Description Throughout this manual Separation of the following parts of the previous the 2nd edition CHAPTER MIPS III INSTRUCTION SET SUMMARY CHAPTER 4 MIPS16 INSTRUCTION SET CHAPTER 5 Vr4181 PIPELINE CHAPTER 6 MEMORY MANAGEMENT SYSTEM first half CHAPTER 7 EXCEPTION PROCESSING second half CHAPTER 9 CACHE MEMORY CHAPTER 10 CPU CORE INTERRUPTS CHAPTER 27 MIPS III INSTRUCTION SET DETAILS CHAPTER 28 MIPS16 INSTRUCTION SET FORMAT p 30 Deletion of modem block in Figure 1 1 Internal Block Diagram p 34 Modification of description in 1 3 16 LCD interface 35 Modification of Remark in 1 3 17 Wake up events pp 38 to 42 p 43 Addition of 1 4 2 CPU instruction set overview and 1 4 3 Data formats and addressing Modification of description and deletion of figure in 1 4 4 registers pp 45 46 Addition of 1 4 9 Power modes and 1 4 10 Code compatibility p 47 Addition of descriptions in 1 5 Clock Interface pp 48 49 Addition of Figure 1 8 External Circuits of Clock Oscillator and Figure 1 9 Incorrect Connection Ci
214. Suspend mode transition Standby WaitPenTouch or Interval state 1 PIUCNTREG PIUSEQEN 0 Standby state 2 PIUCNTREG PIUPWR 1 Disable state 5 Transition flow when returning from Suspend mode Disable state 1 PIUCNTREG PIUPWR 1 Standby state 2 PIUCNTREG PIUMODE 1 0 00 PADATSTART 1 PADATSTOP 1 3 PIUCNTREG PIUSEQEN 1 WaitPenTouch state Touch detected DataScan state 6 Transition flow for command scan Disable state 1 PIUCNTREG PIUPWR 1 Standby state 2 PIUCNTREG PIUMODE 1 0 01 3 PIUCNTREG Setting of touch panel pins selection of input port 4 PIUCNTREG PIUSEQEN 1 CMDScan state 296 User s Manual U14272EJ3VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 5 Relationships among TPX TPY ADIN and AUDIOIN Pins and States State PADSTATE 2 0 TPX 1 0 TPY 1 0 AUDIOIN ADIN 2 0 PIU disable pen status detection Disable HH D Low power standby Standby 00 00 Pen status detection WaitPenTouch Interval HH D Voltage detection at general purpose ADO port ADPScan 00 00 Voltage detection at general purpose AD1 port ADPScan 00 00 Voltage detection at general purpose AD2 port ADPScan 00 00 Voltage detection at audio input port ADPScan 00 00 Touch pressure detection 2 DataScan HH d TPY1 L TPYO H X DataScan l LH TPY1 H TPYO L X DataSca
215. TATREG Index 0x05 SIRQS3 SIRQS2 SIRQS1 SIRQSO Reserved BDEAD_EN R W R W R W R W R W 0 0 0 0 0 Function SIRQS 3 0 Interrupt request steering for the I O card STSCHG CF_BUSY signal 0000 IRQ is not used 0001 RFU 0010 RFU 0011 IRQ3 is used 0100 IRQ4 is used 0101 IRQ5 is used 0110 RFU 0111 IRQ7 is used 1000 RFU 1001 IRQ9 is used 1010 IRQ10 is used 1011 IRQ11 is used 1100 IRQ12 is used 1101 RFU 1110 IRQ14 is used 1111 IRQ15 is used Card detect enable Enables a card status change interrupt request when a change has been detected on the 1 or 2 signals 0 Disable 1 Enable Ready enable Enables a card status change interrupt request when a transition has been detected on the BUSY signal 0 Disable 1 Enable Reserved 0 is returned when read BDEAD EN Battery not usable or status change interrupt request enable Enables a card status change interrupt request when a change has been detected on the CF_STSCHG signal battery unusable status for memory cards or status change detection for I O cards 0 Disable 1 Enable For I O cards the EN bit of the ITGENCTREG register must be cleared to 0 in advance when using the interrupt request via the CF_STSCHG signal User s Manual U14272EJ3VOUM 339 CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 7 ADWINENREG Index 0x06 IOWEN1 IOWENO Reserv
216. TPX1 output TPXO input 01 TPX1 input TPXO output 00 TPX1 input TPXO input TPYD 1 0 TPY output level during command scan 11 TPY1 TPYO 10 TPY1 TPYO L 01 TPY1 4 TPYO 00 TPY1 1 TPYO L TPXD 1 0 Remark L low level high level TPX output level during command scan 11 TPX1 10 TPX1 L 01 TPX1 4 00 TPX1 L L User s Manual U14272EJ3VOUM 287 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 2 2 Function ADCMD 3 0 A D converter input port selection for command scan 1111 A D converter standby mode request 1110 RFU RFU AUDIOIN port ADIN2 port ADIN1 port ADINO port TPY1 port TPYO port TPX1 port TPXO port This register switches input output and sets output level for each port during a command scanning operation The setting of the TPYD bits are invalid when a port is set as input in the TPYEN bits The setting of the TPXD bits are invalid when a port is set as input in the TPXEN bits 288 User s Manual U14272EJ3VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 3 6 PIUASCNREG 0 0 00 0130 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets Name Reserved Reserved R
217. TVAL1 INTVALO R W RTCRST Other resets Function 15to 11 Reserved 0 is returned when read 10 to 0 SCANINTVAL 10 0 Coordinate data scan sampling interval setting Interval SCANINTVAL 10 0 x 30 us This register sets the scan interval sampling period for coordinate data sampling The sampling interval for one set of coordinate data is the value set via SCANINTVAL 10 0 multiplied by 30 us Accordingly the logical range of sampling intervals that can be set in 30 us units is from 0 us to about 60 ms Actually if the sampling interval setting is shorter than the time required for obtaining a set of coordinate data or ADPScan data a data lost interrupt request will occur If data lost interrupt requests occur frequently set a longer interval time User s Manual U14272EJ3VOUM 285 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU Figure 14 5 Interval Times and States ADPScan State ae 3 Operation SASASASA sr aaaa SASASASA Interval time Remark S Voltage stabilization wait time STABLE 5 0 in PIUSTBLREG A A D converter conversion time about 10 us T Touch release detection 14 3 4 PIUSTBLREG 0 0 00 0128 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets Name Reserved Reserved STABLES STABLE4 STABLE3 STABLE2 STABLE1 STABLEO R W RTCRST
218. UFC 1 FIFO control register write 0x0C00 0013 SIULC 1 Line control register 0x0C00 0014 SIUMC 1 Modem control register 0x0C00 0015 SIULS 1 Line status register 0x0C00 0016 SIUMS 1 Modem status register 0x0C00 0017 SIUSC 1 Scratch register 0x0C00 0019 SIURESET 1 SIU reset register 0x0C00 001C SIUACTMSK 1 SIU activity mask register 0x0C00 001E SIUADTTMR 1 Remark LCRT7 is bit 7 of the 1 register SIU Activity Timer register User s Manual U14272EJ3VOUM 361 CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 1 SIURB 1 0 0 00 0010 LCR7 0 Read Name R W RTCRST Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Other resets Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7100 RXD 7 0 Serial receive data This register stores receive data used in serial communications To access this register set the LCR7 bit bit 7 of the SIULC_1 register to 0 19 3 2 SIUTH 1 0 0 00 0010 LCR7 0 Write RTCRST Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Other resets Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7100 TXD 7 0 Serial transmit data This register stores transmit data used in serial communic
219. UM 141 CHAPTER 7 CONTROL UNIT DCU 7 1 General The DMA Control Unit DCU controls four channels of DMA transfer Two of them are allocated for the AIU microphone and speaker though the remaining two are reserved for future use The Microphone channel performs the l O to memory transfers from the A D converter included in the AIU to memory The Speaker channel performs the memory to I O transfers from memory to the D A converter included in the AIU Each DMA channel supports both the primary and the secondary memory buffers The Source1 Source2 or Destination1 Destination2 Address registers for the associated channel determine the starting address of each memory buffer The sizes of memory buffers are determined in the associated record length registers The DCU uses the primary and secondary DMA buffers alternately when transferring For example during the first DMA transfer following either hardware or software reset of the DCU the transfer starts using the primary DMA buffer If the total number of DMA transfers through the primary DMA buffer reaches the value set in the associated record length register the next DMA transfer is performed using the secondary DMA buffer Software must keep track of which buffer contains valid DMA data Software may configure any of the DMA channels to operate in one of two modes auto stop or auto load When a channel is configured to operate in auto stop mode the DCU terminates DMA transfers
220. VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 1 General The PIU uses the on chip A D converter to detect the X and Y coordinates of pen contact locations on a touch panel and to scan the general purpose A D input port Since the touch panel control circuit and the A D converter conversion precision 10 bits are both incorporated the touch panel is connected directly to the Vn4181 The PIU s function namely the detection of X and Y coordinates is performed partly by hardware and partly by software Hardware tasks Touch panel applied voltage control Reception of coordinate data Software task Processing of coordinate data based on data sampled by hardware Features of the PIU s hardware tasks are described below Can be directly connected to touch panel with four pin resistance layers on chip touch panel driver Interface for on chip A D converter Voltage detection at three general purpose A D ports and one audio input port Operation of A D converter based on various settings and control of voltage applied to touch panel Sampling of X coordinate and Y coordinate data Variable coordinate data sampling interval Interrupt is triggered if pen touch occurs regardless of CPU operation mode interrupts do not occur during Hibernate mode Four dedicated buffers with up to two pages each for coordinate data Four buffers for A D port scan Auto manual options for coordinate data sampling start stop co
221. ables RTCLong2 interrupt 0 Disable 1 Enable This register is used to enable disable level 1 interrupts Users Manual U14272EJ3VOUM 181 CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 7 PIUINTREG 0 0 00 0082 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets PADCMD INTR PADADP INTR PADPAGE1 INTR PADPAGEO INTR PADDLOST INTR PENCHG INTR RTCRST Other resets Reserved Function 0 is returned when read PADCMDINTR PIU command scan interrupt request This interrupt request occurs when a valid data is detected during a command scan 0 Not occurred 1 Occurred PADADPINTR PIU AD Port Scan interrupt request This interrupt request occurs when a valid data is obtained during an A D port scan 0 Not occurred 1 Occurred PADPAGE1INTR PIU data buffer page 1 interrupt request This interrupt request occurs when a set of valid data is stored in the page 1 of the data buffer 0 Not occurred 1 Occurred PADPAGEOINTR PIU data buffer page 0 interrupt request This interrupt request occurs when a set of valid data is stored in the page 0 of the data buffer 0 Not occurred 1 Occurred PADDLOSTINTR Data loss interrupt request This interrupt request occurs when a set of data cannot be obtained within the specified time 0 Not occurred 1 Occurred
222. after the POWERON pin is asserted the Vn4181 checks the state of the BATTINH BATTINT pin If the BATTINH BATTINT pin s state is low the POWERON pin is deasserted one RTC clock after the BATTINH BATTINT pin check is completed then the Vn4181 is not activated If the BATTINH BATTINT pin s state is high the POWERON pin is deasserted and the MPOWER pin is asserted three RTC clocks after the BATTINH BATTINT pin check is completed then the Vn4181 is activated Figure 5 6 shows a timing chart of Vn4181 activation and Figure 5 7 shows a timing chart of when activation fails due to the pin s low state Remark While the MPOWER pin is inactive 2 5 V power supply of the Vn4181 VDD LOGIC VDD is not needed In order to reduce leak current it is recommended to turn on off the 2 5 V power supply of the Vn4181 according to MPOWER pin state Figure 5 6 Vn4181 Activation Sequence When Activation Is OK POWERON Output A MPOWER Output A ColdReset Internal Reset Internal BATTINH BATTINT Input Stable oscillation Stopped ft Undefined PLL Internal RTC Internal 32 768 kHz Detection Activation of activation of CPU factor Check BATTINH BATTINT pin 102 User s Manual U14272EJ3VOUM CHAPTER 5 INITIALIZATION INTERFACE Figure 5 7 4181 Activation Sequence When Activation Is POWERON Output A N MPOWER Outpu
223. after the number of transfers specified by the record length register and automatically resets the DMA mask bit for that channel Once the mask bit is automatically reset the DCU ignores all subsequent DMA requests for this channel To resume DMA transfers in this mode software must again unmask DMA transfers for this channel Once software unmasks DMA requests the DCU resumes DMA transfers utilizing the secondary memory buffer When channel is configured to operate in auto load mode the DCU does not terminate DMA transfers after the number of DMA transfers specified by the record length register Instead the DCU automatically switchs to the secondary DMA buffer and continues servicing DMA requests In either mode auto stop or auto load the DCU always alternates the DMA buffer to be used between the primary and secondary buffers Software must keep track of the total number of transfers and assure the appropriate DMA buffer is loaded with new DMA data before starting another DMA transfer The DCU can be programmed to generate an EOP end of process interrupt request independent of auto stop or auto load mode An EOP interrupt request is generated once the number of DMA transfers has reached to the value specified by the record length register 142 User s Manual U14272EJ3VOUM CHAPTER 7 DMA CONTROL UNIT DCU Priority of each channel is fixed The channel priority is as follows 1 AIU Microphone channel 2 AIU Speaker channel
224. age pair For a 1 KB page size this format may be used directly to address the pair table of 8 byte PTEs When the page size is 4 KB or more shifting or masking this value produces the appropriate PTE reference address 86 User s Manual U14272EJ3VOUM CHAPTER 3 REGISTERS 3 2 19 Parity Error register 26 The Parity Error PErr register is a readable writable register This register is defined to maintain software compatibility with the 4100 and is not used in hardware because the Vn4181 has no parity Figure 3 23 Parity Error Register 31 8 7 0 ome Diagnostic 8 bit self diagnostic field 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read 3 2 20 Cache Error register 27 The Cache Error register is a readable writable register This register is defined to maintain software compatibility with the Vn4100 and is not used in hardware because the Vn4181 has no parity Figure 3 24 Cache Error Register 31 0 2 1 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read User s Manual U14272EJ3VOUM 87 CHAPTER 3 REGISTERS 3 2 21 TagLo 28 TagHi 29 registers The TagLo and TagHi registers are 32 bit read write registers that hold the primary cache tag during cache initialization cache diagnostics or cache error processing The Tag registers are written by the CACHE and MTCO instructions The
225. ails of Registers 3 2 1 Index register 0 The Index register is a 32 bit read write register containing five low order bits to index an entry in the TLB The most significant bit of the register shows the success or failure of a TLB probe TLBP instruction The Index register also specifies the TLB entry affected by TLB read TLBR or TLB write index TLBWI instructions The contents of the Index register are undefined after a reset so that it must be initialized by software Figure 3 1 Index Register 31 30 5 4 0 o Indicates whether probing is successful or not It is set to 1 if the latest TLBP instruction fails It is cleared to 0 when the TLBP instruction is successful Index Specifies an index to a TLB entry that is a target of the TLBR or TLBWI instruction 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read 3 2 2 Random register 1 The Random register is a read only register The low order 5 bits are used in referencing a TLB entry This register is decremented each time an instruction is executed The values that can be set in the register are as follows e The lower bound is the content of the Wired register e The upper bound is 31 The Random register specifies the entry in the TLB that is affected by the TLBWR instruction The register is readable to verify proper operation of the processor The Random register is set to the value of the upper bound
226. aker channel 150 User s Manual U14272EJ3VOUM CHAPTER 7 DMA CONTROL UNIT DCU 7 2 9 MICDMACFGREG 0x0A00 065 i i icDsi MicSrctype MicDestype Reserved MicLoad R W R R R W At reset 1 0 0 Bit 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W At reset Reserved 0 is returned after a read MicDsize 1 0 Indicates Microphone channel data size 01 16 bits Values other than above do not appear MicSrctype Indicates Microphone channel source address type 1 1 0 0 does not appear MicDestype Indicates Microphone channel destination address type 0 Memory 1 does not appear Reserved 0 is returned after a read MicLoad DMA auto stop auto load mode setting for Microphone channel 0 Auto stop 1 Auto load When this bit is set to 1 the DCU automatically begins transferring data to the secondary buffer when the primary buffer is full When this bit is set to 0 the DCU uses the primary buffer only Reserved 0 is returned after a read Users Manual U14272EJ3VOUM 151 CHAPTER 7 DMA CONTROL UNIT DCU 7 2 10 SPKDMACFGREG 0x0A00 0660 Name Reserved Reserved R W At reset Bit 7 6 5 4 3 2 1 0 Reserved SpkDsize1 SpkDsizeO SpkSrctype SpkDestype Reserved Reserved SpkLoad R W At reset Bit Name Function Reserved 0 is re
227. alue before reset 260 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 2 2 Function 1 0 These bits define the type of interrupt generated when the pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt 2 1 0 These bits define the type of interrupt generated when the 2 pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt MTYP 1 0 These bits define the type of interrupt generated when the pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt IOTYP 1 0 These bits define the type of interrupt generated when the GPIOO pin is defined as a general purpose input 00 Negative edge triggered interrupt 01 Positive edge triggered interrupt 10 Low level triggered interrupt 11 High level triggered interrupt User s Manual U14272EJ3VOUM 261 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 11 GPINTSTAT 0 0 00 0314 Name GISTS15 GISTS14 GISTS13 GISTS12 GISTS11 GISTS10 GISTS9 GISTS8 R W R
228. an interrupt request occurs After this interrupt occurs the ADPSSTART bit is automatically set as inactive and the PIU enters the state in which the ADPSSTART bit has been set as active CMDScan state In this state the A D converter operates according to various settings Voltage data from one port only is fetched based on a combination of the touch panel pin setting TPX 1 0 TPY 1 0 and the selection of an input port TPX 1 0 TPY 1 0 AUDIOIN ADIN 2 0 to the A D converter Use PIUCMDREG register to make the touch panel pin setting and to select the input port WaitPenTouch state This is a standby state in which the PIU waits for a touch panel s panel s touch status a touch panel contact status change interrupt request occurs inside the PIU At this point if the PADATSTART bit is active the PIU enters the DataScan state During the WaitPenTouch state it is possible to enter Suspend mode because the panel state can be detected even while the TClock is stopped touch status When the PIU detects a touch DataScan state This is the state in which touch panel coordinates are detected The A D converter is activated and four data for each coordinate are sampled Caution If one complete set of coordinate data is not obtained during the interval between one set of coordinate data and the next coordinate data a data lost interrupt request occurs Interval state This is the standby state in which the PIU waits for the next coord
229. are Caution Be sure to set the EP field and the AD bit to 0 If they are set with any other values the processor may behave unexpectedly Figure 3 18 Config Register 1 2 31 30 2827 24 23 22 212019 18 1716 15 14 13 12 11 pe pe 9 System clock ratio read only 0 Processor clock frequency divided by 2 1 Processor clock frequency divided by 3 2 Processor clock frequency divided by 4 3 to 7 Reserved EP Transfer data pattern cache write back pattern setting 0 DD 1 word per 1 cycle Others Reserved AD Accelerate data mode 0 4000 Series compatible mode 1 Reserved M16 MIPS16 ISA mode enable disable indication read only 0 MIPS16 instruction cannot be executed 1 gt MIPS16 instruction can be executed BE BigEndianMem Endian mode indication 0 gt Little endian 1 Reserved CS Cache size mode indication n IC DC 0 Reserved 1 gt 2 bytes IC Instruction cache size indication 2429 bytes in the Vn4181 2 4KB Others Reserved DC Data cache size indication 29979 bytes in the Vn4181 2 4KB Others Reserved User s Manual U14272EJ3VOUM 83 CHAPTER 3 REGISTERS Figure 3 18 Config Register 2 2 KO kseg0 cache coherency algorithm 2 Uncached Others Cached 1 is returned when read 0 0 is returned when read 3 2 16 Load Linked Address LLAddr register 17 The read write Load Link
230. ary into the cache by using a Fill operation of CACHE instruction and jump to the cached codes These codes can be executed on ROM Clear the DRAM_EN bit in the DRAMHIBCTL register to 0 so that the DRAM interface signals are again driven directly by the memory controller SDRAM exits the self refresh mode If burst refreshes are needed set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge Then execute CBR auto refresh cycles for a specific time period i e OXGFFF x TClock period burst refresh interval required by DRAM Restore to the BCURFCNTREG register in the MBA Host Bridge a value that determines refresh interval satisfying the conditions of DRAM type to be used User s Manual U14272EJ3VOUM 207 CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 7 Register Set The PMU registers are listed below Table 10 4 PMU Registers Physical address Register symbol Function 0 0 00 00A0 PMUINTREG PMU interrupt status register 0 0 00 00 2 PMU control register 0 0 00 00A8 PMUWAITREG PMU wait counter register 0 0 00 00AC PMUDIVREG PMU Div mode register 0x0B00 00B2 DRAMHIBCTL DRAM Hibernate mode control register 208 User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 7 1 PMUINTREG 0 0 00 00A0 Name Reserved Reserved 1 2 Reserved GP RTCINTR BATTINH WAKEUP R W RTCRST Other res
231. ation Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster Systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E 02 11 1 User s Manual U14272EJ3VOUM Regional Information Some information contained in this document may vary from country to country Before using any NEC Electronics product in you
232. ations To access this register set the LCR7 bit bit 7 of the SIULC_1 register to 0 19 3 3 SIUDLL 1 0 0 00 0010 LCR7 1 Name DLL7 DLL6 DLL5 DLL4 DLL3 DLL2 DLL1 DLLO R W R W R W R W R W R W R W R W R W RTCRST Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Other resets Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7100 7 0 Baud rate divisor low order byte This register is used to set the divisor division rate for the baud rate generator The data in this register and the data in the SIUDLM 1 register as upper 8 bits are together handled as 16 bit data To access this register set the LCR7 bit bit 7 of the SIULC_1 register to 1 362 User s Manual U14272EJ3VOUM CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 4 SIUIE 1 0 0 00 0011 LCR7 0 Name Reserved Reserved Reserved Reserved R W RTCRST Other resets Function Reserved 0 is returned when read IE3 Modem status interrupt 1 Enable 0 Prohibit Receive status interrupt 1 Enable 0 Prohibit Transmit holding register empty interrupt 1 Enable 0 Prohibit Receive data ready interrupt or character timeout interrupt in FIFO mode 1 Enable 0 Prohibit This register is used to specify interrupt enable prohibit settings for the five types of interrupt requests used in the SIU1
233. be externally qualified with TClock The key data lost interrupt request KDATLOST bit signals that a data from the SCANIN line written to the key data register corresponding to the SCANOUTO pin before the previous data value is read by the CPU core This interrupt source can be masked through the MSKKDATLOST bit of the MKIUINTREG register The key data ready interrupt request KDATRDY bit signals one complete scan operation has been completed This interrupt request is generated during a write of a data from the SCANIN line to the key data register corresponding to the last SCANOUT pin This interrupt request source can be masked through the MSKKDATRDY bit of the MKIUINTREG register The key down interrupt request KEYDOWN bit signals a key press event has been detected This interrupt request is generated in synchronization with the rising edge of the 32 768 kHz clock when the keyboard interface is idle and any SCANIN pin is sampled as low during a period of time from a rising edge to a falling edge of the 32 768 kHz clock This interrupt request source can be masked through the MSKKDOWNINT bit of the MKIUINTREG register The MSKKDATLOST MSKKDATRDY and MSKKDOWNINT bits only prevent interrupt requests from being generated on the kiuintr signal internal These mask bits do not disable interrupt request event detection nor do they disable interrupt status reporting in the KIUINT register 320 User s Manual U14272EJ3VOUM CHAPTER 16 KEYBOARD INTER
234. bit stop bit When in FIFO mode if a break is detected for one character in the FIFO the character is regarded as an error character and the CPU is notified of a break when that character reaches the highest position in the FIFO When a break occurs one zero character is sent to the FIFO When the RxD2 enters marking status and the next valid start bit is received the next character can be transmitted The value of LSR3 bit becomes 1 when a zero spacing level stop bit is detected following the final data bit or parity bit When in FIFO mode if a framing error is detected for one character in the FIFO the character is regarded as an error character and the CPU is notified of a framing error when that character reaches the highest position in the FIFO When a framing error occurs the SIU2 prepares for synchronization again The next start bit is assumed to be the cause of the framing error and the next data is not accepted until the next start bit has been sampled twice The value of LSR2 bit becomes 1 when a received character does not satisfy the even or odd parity specified in the LCR4 bit When in FIFO mode if a parity error is detected for one character within the FIFO the character is regarded as an error character and the CPU is notified of a parity error when that character reaches the highest position in the FIFO The value of LSR1 bit becomes 1 when a character is transferred to the receive buffer register before reading by the CPU a
235. ble or keyboard scan data output CF IOWZ SCANOUT5 Output CompactFlash I O write strobe output or keyboard scan data output CF IORZ SCANOUTA Output CompactFlash I O read strobe output or keyboard scan data output CF STSCHGZ SCANOUTS3 CompactFlash status changed input or keyboard scan data output CE 2 1 Output CompactFlash card enable outputs or keyboard scan data outputs SCANOUT 2 1 CF_BUSY SCANOUTO CompactFlash ready busy interrupt request indication input or keyboard scan data output CF REGZ SCANIN7 CompactFlash register select output or keyboard scan data input RESET SCANING CompactFlash reset output or keyboard scan data input WAITZ SCANIN5 Input CompactFlash wait input or keyboard scan data input 1516 5 4 Input CompactFlash 16 bit bus input or keyboard scan data input CF VCCENZ SCANIN3 y o CompactFlash Vcc enable output or keyboard scan data input DENZ SCANIN2 y o CompactFlash data buffer enable output or keyboard scan data input DIR SCANIN1 CompactFlash data direction control output or keyboard scan data input AENZ SCANINO VO CompactFlash address buffer enable output or keyboard scan data input 56 User s Manual U14272EJ3VOUM CHAPTER 2 PIN FUNCTIONS 2 2 9 Serial interface channel 1 signals Signal name Description of function RxD1 GPIO25 Serial channel 1 receive data input or general purpose I O TxD1 GPIO26 CLKSELO The funct
236. ceive a a aai 160 369 388 receive 2 156 release detection 4 44422 2 1 298 reset Control 2 5 enge ud be o 191 reset function 2 4 0 000 nennen 96 REVIDREG ponet i edes 116 ROMr nterface n nS 118 ROM Spa66 titi pee i ede grt 93 RSTSW feset ettet ede cete hens 98 192 ilem 216 RTC registers iini deeem emen 216 DULORI E 97 191 RTCINTREG wz enti a tere vega 229 RIGLTGNTEHBEQ ie tt itr tette ees 224 RTGLTONTERBEQG iiie Ren 223 RIGEIHREG uen 222 RICLILRE GH cet titer rune 221 2 228 224 honed 227 2 226 2 225 ET Gorg usine 216 5 Scan KIUN iecore tete tet er 319 scan sequencer KIU 320 324 scan sequencer PIU 278 283 290 295 SCIKphase aei ep REPRE 157 SONTREQ iiti tede ets 307 SCNVC END is che pepe an aun ced 308 SDOLK REA 47 135 SDMADATREG IERI 303 130 192 202 204 206 207 438 SDTIMINGREG 2 nete teen 136 SEQRBEQG une Eee orn eile 312 serial interface 239 240 serial interface signals
237. ck 1011 12 5 TClock 1100 13 5 TClock 1101 14 5 TClock 1110 15 5 TClock 1111 16 5 TClock This register is used to set ROM access parameter of Bank 0 1 2 and 3 About the relationship between these bits and ROM cycles refer to Figure 6 2 ROM Read Cycle and Access Parameters Remark The maximum burst number when using a PageROM is 8 halfwords i e 128 bits 1 word 32 bits Users Manual U14272EJ3VOUM 113 CHAPTER 6 BUS CONTROL Figure 6 2 ROM Read Cycle and Access Parameters a Ordinary ROM cycle TClock internal ADD 21 0 output Valid ROMCS 3 0 output MEMRD output WROMA 3 0 DATA 15 0 read b PageROM cycle TClock internal ADD 21 3 output Valid ADD 2 0 output Valid Valid ROMCS 3 0 output WROMA 3 0 WPROM 2 0 DATA 15 0 read Valid Valid Remarks 1 ROMCS 2 0 signals are alternated with general purpose I O signals and are defined as general purpose inputs after RTC reset Set GPMD2REG and GPMD3REG registers in the GIU to use them as ROMCS 2 0 2 A circle in the figure indicates the sampling timing 114 User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 6 2 4 BCURFCNTREG 0x0A00 0010 Name R W At reset At reset Bit Name Function Reserved 0 is returned when read BRF 13 0 These bits select the DRAM refresh rate that
238. ck end time T7 Tg x HpckH HpckL x LCE FLM horizontal start time T8 Tg x HpckH HpckL x FLMHS FLM horizontal end time T9 Tg x HpckH HpckL x FLMHE Panel frame period T10 Tg x HpckH HpckL x Htot x Vtot User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 21 4 Register Set Physical address Table 21 4 LCD Controller Registers Register symbol Function 0x0A00 0400 R W HRTOTALREG Horizontal total register 0x0A00 0402 R W HRVISIBREG Horizontal visible register 0 0 00 0404 R W LDCLKSTREG Load clock start register 0 0 00 0406 R W LDCLKENDREG Load clock end register 0 0 00 0408 R W VRTOTALREG Vertical total register 0x0A00 040A R W VRVISIBREG Vertical visible register 0 0 00 040C R W FVSTARTREG FLM vertical start register 0x0A00 040E R W FVENDREG FLM vertical end register Ox0A00 0410 R W LCDCTRLREG LCD control register Ox0A00 0412 R W LCDINRQREG LCD interrupt request register 0 0 00 0414 R W LCDCFGREGO LCD configuration register 0 0x0A00 0416 R W LCDCFGREG 1 LCD configuration register 1 0x0AO00 0418 R W FBSTADREG1 Frame buffer start address 1 register 0x0A00 041A R W FBSTADREG2 Frame buffer start address 2 register 0 0 00 0420 R W FBENDADREG 1 Frame buffer end address 1 register 0 0 00 0422 R W FBENDADREG2 Frame buffer end address 2 register Ox0A00 0424 R W FHSTARTREG FLM horizontal start regi
239. cks 011 3 clocks Others Reserved 3 WT Wrap type for the burst cycles This bit should be always written to O 0 Sequential default 2100 BL 2 0 Burst length These bits should be always written to 111 111 Full page When WT 0 only Setting prohibited when WT 1 Note The CAS latency mode must be set according to the operation frequency of the SDCLK SDRAM clock This register is used to set the value output to ADD 13 0 pins during the SDRAM mode register setting cycle This register should be written before the Init bit of MEMCFG REG register is set to 1 User s Manual U14272EJ3VOUM 135 CHAPTER 6 BUS CONTROL 6 5 4 SDTIMINGREG 0x0A00 030C Name Reserved Reserved R W At reset At reset Bit Name Function 15 to 10 Reserved 0 is returned when read 9 Reserved Write 0 when write 9 8 Reserved Write 1 when write 7 6 TRAS 1 0 TRAS in clock cycles 00 3 SDCLK for 25 MHz SDCLK 01 5 SDCLK for 66 50 or 33 MHz SDCLK Others Prohibited TRC in clock cycles 00 4 SDCLK for 25 MHz SDCLK 01 7 SDCLK for 66 50 or 33 MHz SDCLK Others Prohibited TRP in clock cycles 00 1 SDCLK for 25 MHz SDCLK 01 Prohibited 10 3 SDCLK for 66 50 or 33 MHz SDCLK 11 Prohibited TRCD 1 0 TRCD in clock cycles 00 1 SDCLK for 25 MHz SDCLK 01 2 SDCLK for 66 50 or 33 MHz SDCLK Other
240. ction and function of the GPIO23 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 ROMCS1 output GP22MD 1 0 These bits control direction and function of the GPIO22 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 ROMCSO output GP21MD 1 0 These bits control direction and function of the GPIO21 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 RESET output GP20MD 1 0 These bits control direction and function of the GPIO20 pin as follows 00 General purpose input 01 RFU 10 LCD M output 11 UBE output GP19MD 1 0 Note Holds the value before reset These bits control direction and function of the GPIO19 pin as follows 00 General purpose input 01 1 OCS16 input 10 General purpose output 11 RFU Caution LCD M output can not be used in the Vn4181 of Rev 1 0 250 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 2 2 Function GP18MD 1 0 These bits control direction and function of the GPIO18 pin as follows 00 General purpose input 01 IORDY input 10 General purpose output 11 RFU GP17MD 1 0 These bits control direction and function of the GPIO17 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 IOWR output GP16MD 1 0 These bits control direction and function of the GPIO1
241. ction and function of the GPIO7 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 SIU2 DTR2 output GP6MD 1 0 These bits control direction and function of the GPIO6 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 SIU2 RTS2 output GP5MD 1 0 These bits control direction and function of the GPIOS pin as follows 00 General purpose input 01 SIU2 DCD2 input 10 General purpose output 11 RFU GP4MD 1 0 These bits control direction and function of the GPIOA pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 RFU GP3MD 1 0 Note Holds the value before reset 246 These bits control direction and function of the GPIO3 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 Programmable chip select 0 output User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 2 2 Function GP2MD 1 0 These bits control direction and function of the GPIO2 pin as follows 00 General purpose input 01 CSI SCK input 10 General purpose output 11 RFU GP1MD 1 0 These bits control direction and function of the GPIO1 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 CSI SO output GPOMD 1 0 These bits control direction and function of the GPIOO pin as follows 00 General purpose inpu
242. ction of an alternate function pin and the I O direction of the GPIO pins are selected by the registers in the GIU Be sure to set these registers in accordance with the unit or the function of the pin to be used Exercise care in setting the registers so that signals do not conflict on the board or that a signal whose level is required does not go into a high impedance state 106 User s Manual U14272EJ3VOUM CHAPTER 5 INITIALIZATION INTERFACE 5 4 3 Returning from power mode For initialization after the Vn4181 has returned from the Hibernate mode or Suspend mode refer to 10 6 DRAM Interface Control Users Manual U14272EJ3VOUM 107 CHAPTER 6 BUS CONTROL 6 1 MBA Host Bridge The MBA Modular Bus Architecture Host Bridge is an interface between the CPU core and the MBA bus and operates as an external agent to the CPU core It handles all requests from the CPU core if it is provided proper resources The MBA Host Bridge can decode the entire physical address space to start appropriate bus accesses such as MBA requests MBA ISA protocols or external ROM accesses through the peripheral bus It also has functions as a host bridge to implement proper cycle timings and bus transaction protocols Figure 6 1 Vr4181 Internal Bus Structure Vn4110 CPU Core MBA Peripherals LCD DMA T Memoty Controller MBA Host Bridge MBA Bus Internal ISA ISA Bridge Peripherals
243. ctions is enabled or disabled When the MIPS16 instruction execution is disabled either of the following addresses is contained in the ErrorEPC register e Virtual address of the instruction that caused the exception e Virtual address of the immediately preceding branch or jump instruction when the instruction associated with the error exception is in a branch delay slot and the BD bit in the Cause register is set to 1 When the MIPS16 instruction execution is enabled either of the following addresses is contained in the ErrorEPC register during a 32 bit instruction execution e Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs e Virtual address of the immediately preceding branch or jump instruction and ISA mode at which an exception occurs when the instruction associated with the error exception is in a branch delay slot and the BD bit in the Cause register is set to 1 When the 16 bit instruction is executed either of the following addresses is contained in the ErrorEPC register e Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs e Virtual address of the immediately preceding jump instruction or Extend instruction and ISA mode at which an exception occurs when the instruction associated with the error exception is in a branch delay slot of the jump instruction or is the instruction following the Extend instruction and the BD bit in th
244. cution is disabled either of the following addresses is contained in the EPC register e Virtual address of the instruction that caused the exception Virtual address of the immediately preceding branch or jump instruction when the instruction associated with the exception is in a branch delay slot and the BD bit in the Cause register is set to 1 When the MIPS16 instruction execution is enabled either of the following addresses is contained in the EPC register during a 32 bit instruction execution e Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs Virtual address of the immediately preceding branch or jump instruction and ISA mode at which an exception occurs when the instruction associated with the exception is in a branch delay slot of the jump instruction and the BD bit in the Cause register is set to 1 When the 16 bit instruction is executed either of the following addresses is contained in the EPC register e Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs Virtual address of the immediately preceding Extend or jump instruction and ISA mode at which an exception occurs when the instruction associated with the exception is in a branch delay slot of the jump instruction or in the instruction following the Extend instruction and the BD bit in the Cause register is set to 1 The EXL bit in the Status register is set to
245. cy Div2 mode immediately after RTC reset Software can change TClock Div mode by setting the PMUDIVREG register OxOB00 00 change becomes valid when the Vn4181 restores from the Hibernate mode after setting the PMUDIVREG register Users Manual U14272EJ3VOUM 117 CHAPTER 6 BUS CONTROL 6 3 ROM Interface The Vn4181 supports three ROM modes ordinary ROM PageROM and flash memory The mode setting is made via the BCUCNTREG1 registers Rtype 1 0 bits and ROMWENO bit Access speed setting in ordinary ROM or PageROM mode is made via the BCUSPEEDREG register Remark 4181 supports only 16 bit access for external ROM devices 6 3 1 External ROM devices memory mapping Physical address 32 Mbit ROM 64 Mbit ROM Ox1FFF FFFF to 0x1FCO 0000 Bank 3 ROMCS3 Bank 3 ROMCS3 Ox1FBF FFFF to 0x1F80 0000 Bank 2 ROMCS2 Ox1F7F FFFF to 0x1F40 0000 Bank 1 ROMCS1 Bank 2 ROMCS2 Ox1FSF FFFF to 0x1F00 0000 Bank 0 ROMCS0 Ox1EFF FFFF to 0x1E80 0000 Reserved Bank 1 ROMCS1 Ox1E7F FFFF to 0x1E00 0000 Reserved Bank 0 ROMCSO Bank 3 contains boot vector and has a dedicated pin for chip select ROMCS3 Chip select pins for Bank 2 1 and 0 ROMCS 2 0 are alternated with general purpose I O signals and are defined as general purpose inputs after RTC reset Set GPMD2REG and GPMD3REG registers in the GIU to use them as ROMCS 2 0 118 User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 6
246. cycles of 32 768 kHz clock have elapsed after the first setting Cautions 1 RTCLong1 timer is stopped when all zeros are written 2 Any combined setting of 0x0000 and 0x0001 0x0002 0x0003 or 0x0004 is prohibited 222 User s Manual U14272EJ3VOUM CHAPTER 11 REALTIME CLOCK UNIT 11 2 4 RTCLong1 count registers 1 RTCL1CNTLREG 0 0 00 00D4 Name RTCL1C15 RTCL1C14 RTCL1C13 RTCL1C12 RTCL1C11 RTCL1C10 RTCL1C9 RTCL1C8 R W R R R R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Name R W RTCRST Other resets 15100 Note Continues counting RTCL1C 15 0 RTCLong1 timer bits 15 to 0 User s Manual U14272EJ3VOUM 223 CHAPTER 11 REALTIME CLOCK UNIT 2 RTCL1CNTHREG 0 0 00 00D6 Name Reserved Reserved R W RTCRST Other resets RTCRST Other resets Function Reserved 0 is returned when read RTCL1C 23 16 RTCLong1 timer bits 23 to 16 Note Continues counting These registers indicate the RTCLong1 timer s values It counts down by a 32 768 kHz clock cycle and begins counting at the value set to the RTCLong1 registers An RTCLong1 interrupt occurs when the timer value reaches 0x00 0001 at which point the timer returns to the start value and continues counting These registers have n
247. d After that DRAM returns to the self refresh mode At this time the following phenomena may occur and the DRAM data may be lost e DRAM is in the normal operation mode while the RAS signal is high in Figure A 2 but a CBR refresh is not executed e The high level output of the CAS signal b in Figure 2 may be a spike Figure 2 Release of Self Refresh Mode by RSTSW Signal EDO DRAM RSTSW input RAS 1 0 output LCAS UCAS output Exit self refresh mode Resume self refresh mode Pulse width a 30 to 60 us 0 spike to 30 us c 30 us User s Manual U14272EJ3VOUM 437 APPENDIX RESTRICTIONS Vn4181 2 With SDRAM When the RSTSW signal goes low the CLKEN signal goes high While the CLKEN signal is high the self refresh mode of SDRAM may be released However because the SDCLK signal is kept low this problem does not occur in SDRAM that requires the rising edge of the SDCLK signal to release the self refresh mode Figure A 3 Release of Self Refresh Mode by RSTSW Signal SDRAM RSTSW input CLKEN output SDCLK output L SDCS 1 0 output SDRAS output CAS output Workaround Mask the RSTSW signal via an external circuit using the MPOWER signal and GPIO pin so that the RSTSW signal does go low in the Hibernate mode 438 User s Manual U14272EJ3VOUM APPENDIX B INDEX Numerics 16450
248. d tate ect erit eo rar tn 365 384 BGUGNTREG1 111 BGUREGNTREQG ird ti e eren 115 BCUSPEEDREG REPRE 113 jo DEN 34 399 DUS Control ecce ct eb EO ER CEU 108 bus control registers 22 110 bus cycles 16 242 bus Interface be eo 31 xj EE 352 arate e E eee god 44 106 cache algorithm eene 71 Cache Error register 87 card 350 352 338 347 status 338 347 Cause 79 CDSTCHGREG tis rettet qe e eher 338 CFG REG caine SS 333 GIKSPEEDRBEQG REIS 117 Clock Controla i ir tide a C etos 360 379 clock 47 clock interface 5 55 clock oscillator ite tege 48 clock supply minime 106 clocked serial interface unit 156 238 ier reete tread 112 Gold Reset rev e eve 104 color panel nhe net 409 420 CompactFlash controller 328 CompactFlash interface signals 56
249. d when only the number of double words set here is left in the FIFO Reserved 0 is returned when read ContCkE LCD controller clock enable 0 OFF 1 ON LOCLK clock polarity 0 Leading edge is rising 1 Leading edge is falling FLMPOL FLM clock polarity 0 Leading edge is rising 1 Leading edge is falling SCLKPOL Shift clock polarity 0 Leading edge is rising active edge is falling 1 Leading edge is falling active edge is rising 418 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 21 4 10 LCDINRQREG 0x0A00 0412 Reserved Reserved Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved VIReq FIFOOV Reserved Reserved 0 is returned when read VIReq Vertical retrace interrupt request 0 No request outside vertical blank 1 Requested vertical blank FIFOOVERR FIFO overrun interrupt request 0 No request 1 Requested Reserved 0 is returned when read Users Manual U14272EJ3VOUM 419 CHAPTER 21 LCD CONTROLLER 21 4 11 LCDCFGREGO 0x0A00 0414 LCD M signal configuration These bits specify the number of lines between M toggles 0 Once per frame 1 After every line 2 After every 2 lines 255 After every 255 lines Softreset Software reset for LCD controller The software reset is active only in test mode 0 Normal operation 1 Reset
250. data format of each double word depends on the color depth as shown in the following table Bit Bit 31 0 e o e e eee ros eT o s Fw uw o o o e on e o o or m v oe s 06 07 04 05 02 03 00 01 The frame buffer memory starts from the 32 bit address specified by the FBSA 31 0 bits of the FBSTADREG1 and FBSTADREG2 registers and ends at the address specified by the FBEA 31 0 bits of the FRENDADREG1 and FBENDADREG2 registers The FBEA field does not necessarily show where the last pixel is stored but it is the address of the first 32 byte page boundary that follows the memory location where the last pixel is stored starting from the address set in the FBSA field For example if FBSA field is 0x0B00 0408 and the frame buffer occupies 235 bytes then the FBEA field is 0 0 00 0508 FBSA plus the ceiling of 235 32 Data from the frame buffer is burst into the FIFO to conserve memory bandwidth Each burst transfers 32 bytes The FIFO is divided into three arrays and each burst fills exactly one array Bursts can not cross array borders nor can read from and write to the same array at the same time When the memory bandwidth is low the FIFO bursts only when there are only the number of double words left to be read that is displayed in the FIFOC 2 0 bits of the LCDCTRLREG register If the burst is not fast enough in relation to the refresh rate of the panel image irreversible image
251. decet 294 14 7 Mask Clear During Scan Sequencer Operation ssssssssesseeeeeeneee nennen nennen 295 15 1 AU Registers uttter ER tre i ee cd 302 15 2 ATIUIntertupEeglstets e debe Aine ie tn i b de ih ans vo fee 302 16 1 Settings of Keyboard Scan Mode nnns 318 16 2 KIUReglsters ep DECEDERE eR ds 321 16 3 Interrupt Registers ete Pete o ie de EP 321 Tete YECU Control Registers obe eaae gusanos 328 17 22 EGU Registers oer Pe ba rm e Do Eie un came 329 18 15 MEE SPEICHER 353 19 15 SIA Registets asd OR PERDU e RE RUNE DIE 361 19 2 Correspondence between Baud Rates and Divisors ssssssssseseeeeeeeeneeeneee nennen 365 19 3 INTERRUPT FUNCION xs eee t tre De ct b AON ee ee teen bcd be maire beet e Doa 367 204 5102 o REG E UE unde Ln E MEO SE REEL Ree dE 380 20 2 Correspondence between Baud Rates and Divisors 42224 00 00 384 20 9 Interrupt Function noh RR ERE ee P e Pee reos 386 21 1 LCD Panel Resolutions in Pixels essen nennen nnne rennen nnne 399 21 2 Redefining LCD Interface Pins When LCD Controller Is Disabled 2 400 21 37 LOD Gontroller Parameters is cendi aen t ge Ch
252. degradation occurs due to a lack of data to be displayed and an interrupt request is generated This interrupt request can be polled from the FIFOOVERR bit of the LCDINRQREG register It can be cleared only by stopping and then restarting controller clocks Because image degradation is a serious problem the value set to the FIFOC field should be carefully selected during development 406 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 21 3 5 Panel power ON OFF sequence Some panels use several power supplies and these supplies and interface logic signals must be turn on or off in sequences specified by the manufacturers The LCD controller has signals to control these power supplies Each power supply is controlled via the VPBIAS or VPLCD pin These pins are connected to a pull up or pull down resistor in addition to the power supply When the power is off these pins are placed into high impedance so that the resistor pulls the power supply on off input to the off state The power on off sequence is started by setting the PowerC bit of the 2 register Setting this bit to 1 starts the power on sequence In the power on sequence the power supply control pins are brought out of high impedance to a programmed state at a programmed time and the panel interface signals become active at a programmed time The following table lists the control pins and the programming register bits Power on time bit Power on state bit VP
253. ditions under which FIFO timeout interrupt requests occur Atleast one character is being stored in the FIFO The time required for sending four characters has elapsed since the serial reception of the last character includes the time for the second stop bit in cases where it is specified that two stop bits are required The time required for sending four characters has elapsed since the last read of the FIFO by the CPU The time between receiving the last character and issuing a timeout interrupt request is a maximum of 160 ms when operating at 300 baud and receiving 12 bit data The transfer time for a character is calculated based on the baud rate clock for reception internal which is why the elapsed time is in proportion to the baud rate Once a timeout interrupt request has occurred the timeout interrupt is cleared and the timer is reset as soon as the CPU reads one character from the receive FIFO If no timeout interrupt request has occurred the timer is reset when a new character is received or when the CPU reads the receive FIFO User s Manual U14272EJ3VOUM CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 When transmit FIFO is enabled and transmit interrupts are enabled transmit interrupt requests can occur as described below 1 When the transmit FIFO becomes empty a transmit holding register empty interrupt request occurs This interrupt request is cleared when a character is written to the transmit holding register
254. e 90 Connect to VDD IO GND via resistor A GPIO2 SCK Connect to VDD IO or GND via resistor A GPIO1 SO Connect to VDD IO or GND via resistor A GPIOO SI Connect to VDD IO or GND via resistor A LEDOUT Leave open A User s Manual U14272EJ3VOUM 65 CHAPTER 2 PIN FUNCTIONS 2 5 Pin I O Circuits 66 Type A t HE Output disable Input enable IN OUT Type B Output disable IN OUT IN OUT Output disable Input N ch enable Type E Analog output voltage User s Manual U14272EJ3VOUM CHAPTER 3 REGISTERS 3 1 Coprocessor 0 The Coprocessor 0 which is also called as System Control Coprocessor is implemented as an integral part of the CPU and supports memory management address translation exception handling and operation mode control Memory management address translation and operation mode control are provided by a block called memory management unit MMU The MMU contains a 32 entry TLB translation lookaside buffer that is used when translating virtual addresses to physical addresses The CPO has registers shown in Table 3 1 that are used to set various modes for memory management and exception handling and to indicate statuses of the processor Each CPO register has a unique number that is used as an operand to specify a CPO register to be accessed Cau
255. e 157 9 2 3 OS transfer tyDes si x ete e ae e boe Rte Pe ied edt a ee ele 159 8 2 4 Transmit ahd receive FIEOS e RP HABE SECO UR ED 160 8 3 5 e ECL LM IPTE 160 98 3 1 GSIMODE 0x0BO00 0900 2 need tentatio recte EKo KEN te ee 161 8 3 2 CSIRXDATA Ox0BO00 0902 DEO DE EUG nds 163 9 3 3 CSITXDATA 0x0B00 0904 2 erneute tete t tede degrade 163 8 3 46 51 0 0 00 090672 e tae re e ct tege 164 9 3 5 CSIINTMSK 0x0BOO 0908 encre e Ue ene eu Dee Deed nde re e Ee Ene det 166 8 3 6 CSIINTSTAT 0x0BOO 090A EU e rapere Sede dE oe 167 8 3 7 GSITXBEEN0Xx0BOO 0906 RUE e EAE aaae ahai 169 8 3 8 CSIRXBLEN 0x0BO0 090E dee ide didn Mian ce et 170 CHAPTER 9 INTERRUPT CONTROL UNIT ICU 22 111112 171 QD OVEN VIOW 171 9 2 Register M 173 9 2 1 SYSINT1REG 0 0 00 0080 174 9 2 2 MSYSINT1IREG 0 0 00 008 eoa 176 9 2 3 NMIREG 0x0A00 00998 2 teenage ive sade ead eed ine 178 16 User s
256. e Cause register is set to 1 The contents of the ErrorEPC register do not change when the ERL bit of the Status register is set to 1 This prevents the processor when other exceptions occur from overwriting the address of the instruction in this register that causes an error exception The ErrorEPC register never indicates the address of the instruction in a branch delay slot User s Manual U14272EJ3VOUM 89 CHAPTER 3 REGISTERS Figure 3 27 ErrorEPC Register When 516 ISA Is Disabled a 32 bit mode ErrorEPC b 64 bit mode ErrorEPC Virtual restart address after Cold reset Soft reset NMI exception Figure 3 28 ErrorEPC Register When MIPS16 ISA Is Enabled a 32 bit mode ErrorEPC ErIM ErrorEPC Bits 31 to 1 of virtual restart address after Cold reset Soft reset or NMI exception ErIM ISA mode at which an error exception occurs 1 gt MIPS16 ISA 0 gt MIPS III ISA b 64 bit mode o ErrorEPC ErIM ErrorEPC Bits 63 to 1 of virtual restart address after Cold reset Soft reset or NMI exception ErIM ISA mode at which an error exception occurs 1 gt MIPS16 ISA 0 gt MIPS III ISA 90 User s Manual U14272EJ3VOUM CHAPTER 4 MEMORY MANAGEMENT SYSTEM 4 1 Overview The 4181 provides a memory management unit MMU which uses a translation lookaside buffer TLB to translate vi
257. e boundary ADREQAIU Request for use of A D converter 1 Requesting 0 No request This register is used to control the AIU s microphone block The ADENAIU bit controls the connection of VDD AD and Vref input to ladder type resistors in the A D converter Setting this bit to 0 OFF allows low power consumption when not using the A D converter When using the A D converter this bit must be set following the sequence described in 15 3 Operation Sequence The content of the MSTATE bit is valid only when the AIUMEN bit of the SEQREG register is set to 1 The AIU has priority when a conflict occurs with the PIU in relation to A D conversion requests 310 User s Manual U14272EJ3VOUM CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 9 DVALIDREG 0 0 00 0178 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Function Reserved 0 is returned when read SODATV This indicates whether valid data has been stored in SODATREG 1 Valid data exists 0 No valid data This indicates whether valid data has been stored in SDMADATREG 1 Valid data exists 0 No valid data MIDATV This indicates whether valid data has been stored in MIDATREG 1 Valid data exists 0 No valid data This indicates whether valid data has been stored in MDMADATREG 1 Valid data exists 0 No valid data
258. e compared with ElapsedTime timer bits 15 to 0 ECMP29 ECMP28 ECMP27 ECMP26 ECMP25 ECMP24 R W R W R W R W R W R W R W R W R W RTCRST Other resets Name ECMP23 ECMP22 21 20 19 18 17 16 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 15100 31 16 Note Holds the value before reset Value to be compared with ElapsedTime timer bits 31 to 16 User s Manual U14272EJ3VOUM 219 CHAPTER 11 REALTIME CLOCK UNIT 3 0x0B00 00CC Name ECMP47 46 45 ECMP44 ECMP43 ECMP42 ECMP41 ECMP40 R W R W R W R W R W R W R W R W R W RTCRST Other resets ECMP39 ECMP38 ECMP37 ECMP36 ECMP35 ECMP34 ECMP33 ECMP32 RTCRST R W R W R W R W R W R W R W R W Other resets 15100 ECMP 47 32 Note Holds the value before reset Value to be compared with ElapsedTime timer bits 47 to 32 Use these registers to set the values to be compared with values in the ElapsedTime registers A write operation is valid once values have been written to all registers ECMPLREG ECMPMREG and ECMPHREG When setting these registers again wait until at least 100 us three cycles of 32 768 kHz clock have elapsed after the first setting 220 User s Manual U14272EJ3VOUM CHAPTER 11 REALTIME CLOCK
259. e mode All clocks other than the RTC clock 32 768 kHz are fixed to high level and the PLL operation stops An RTC and a monitor for activation factors in the PMU continue their operation To enter to Hibernate mode from Fullspeed mode execute a Hibernate mode sequence see 10 6 DRAM Interface Control first After the HIBERNATE instruction has passed the WB stage and DRAMs enter self refresh mode the Vn4181 waits until SysAD bus internal enters idle state Then MPOWER signal becomes inactive after internal clocks are shut down and pipeline operation stops 2 5 V power supply can be stopped during MPOWER signal is inactive If it is stopped however the contents of registers in the peripheral units other than PMU GIU LED and RTC are not retained To restore to Fullspeed mode from Hibernate mode one of the interrupt requests listed in Figure 10 1 When the processor restores to Fullspeed mode from Hibernate mode it starts a program execution from the Cold Reset exception vector OxBFCO 0000 10 3 Reset Control The operations of the RTC peripheral units and CPU core and PMUINTREG register bit settings during a reset are listed below Table 10 2 Operations During Reset Reset type Peripheral units CPU core PMUINTREG bits RTC reset Reset Reset Cold Reset RTCRST 1 RSTSW reset 1 Active Reset Cold Reset RSTSW 1 SDRAM 0 RSTSW reset 2 Active Active Cold Reset RSTSW 1 SDRAM 1 Deadman s Switch Active Reset C
260. e parity during transmission or check parity during reception 0 No parity during transmission or no checking during reception 2 LCR2 Stop bit specification 1 1 5 bits character length is 5 bits 2 bits character length is 6 7 or 8 bits 0 1 bit 1 0 LCR 1 0 Specifies the length of one character number of bits 11 8 bits 10 7 bits 01 6 bits 00 5 bits This register is used to specify the format for asynchronous data communication and exchange and to set the divisor latch access register The LCR6 bit is used to send the break status to the receive side s UART When the LCR6 bit 1 the serial output TxD1 is forcibly set to the spacing 0 state The setting of the LCR5 bit becomes valid according to settings in the LCR4 and bits Users Manual U14272EJ3VOUM 371 CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 9 SIUMC 1 0 0 00 0014 Name Reserved Reserved Reserved R W RTCRST Other resets Function Reserved 0 is returned when read MCR4 Use of diagnostic testing local loopback 1 Enable 0 Disable OUT2 signal internal setting 1 Low level 0 High level OUT signal internal setting 1 Low level 0 High level RTS1 output control 1 Low level 0 High level DTR1 output control 1 Low level 0 High level This register is used to control the interface with a modem or data set or a periphe
261. e receive FIFO User s Manual U14272EJ3VOUM 369 CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 370 When transmit FIFO is enabled and transmit interrupts are enabled transmit interrupt requests can occur as described below 1 When the transmit FIFO becomes empty a transmit holding register empty interrupt request occurs This interrupt request is cleared when a character is written to the transmit holding register from one to 16 characters can be written to the transmit FIFO during servicing of this interrupt or when the SIUIID 1 register is read 2 If there are not at least two bytes of character data in the transmit FIFO between one time when the LSR5 bit 1 transmit FIFO is empty in the SIULS 1 register and the next time when the LSR5 bit 1 transmit FIFO empty status is reported to the IIR bits after a delay period calculated as the time for one character the time for the last stop bit s When transmit interrupts are enabled the first transmit interrupt request that occurs after the FCRO bit FIFO enable bit in the SIUFC 1 register is overwritten is indicated immediately The priority level of the character timeout interrupt and receive FIFO trigger level interrupt is the same as that of the receive data ready interrupt The priority level of the transmit FIFO empty interrupt is the same as that of the transmit holding register empty interrupt Whether data to be transmitted exists or not in the transmit FIFO and the
262. e transition of the corresponding signals or write to transmit buffer is not notified to the Activity Timer User s Manual U14272EJ3VOUM 397 CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 20 3 17 SIUACTTMR 2 0 0 00 000 SIUTMO7 SIUTMO6 SIUTMO5 SIUTMO4 SIUTMO3 SIUTMO2 SIUTMO1 SIUTMOO R W RTCRST Other resets Function SIUTMO 7 0 SIU activity timeout period 11111111 255 x 30 5 11111110 254 x 30 5 us 01111111 127 x 30 5 us 00000001 30 5 us 00000000 Activity Timer disabled 398 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 21 1 Overview The Vn4181 includes an LCD control module that operates on the MBA bus under the Unified Memory Architecture UMA conventions The frame buffer resides in the main DRAM memory This module supports an STN LCD panel 21 1 1 LCD interface The Vn4181 LCD controller is UMA based controller and uses a part of DRAM memory as a frame buffer The LCD controller supports monochrome STN LCD panels having 4 bit data bus interfaces and color STN LCD panels having 8 bit data bus interfaces When interfacing to a color LCD panel GPIO pins must be allocated to provide the upper nibble of the 8 bit LCD data bus In monochrome mode the LCD controller supports 1 bpp bit per pixel mode mono 2 bpp mode 4 gray levels and 4 bpp mode 16 gray levels In color mode the LCD controller supports 4 bpp mode 16 colors and 8 bpp mode
263. e zero wait state can be enabled or disabled via the ZWSEN bit of the MEMWIDn REG register n 0 to 4 a If zero wait state is enabled A wait state is not added regardless of the bus size Therefore wait states are inserted only during the period set in the MEMWS 1 0 bits of the XISACTL register b If zero wait state is disabled The number of wait states selected in the M16W 1 0 bits of the MEMSELn REG register n 0 to 4 is added in the 16 bit access mode In the 8 bit access mode a 4 SYSCLK cycle wait is added 2 Wait when window is accessed a 16 bit access A 2 SYSCLK cycle wait is added if the IOnWT bit of the IOCTRL REG register 0 or 1 is set to 1 1 SYSCLK cycle wait is added if the IOnWT bit of the IOCTRL REG register 0 or 1 is cleared to 0 b 8 bit access A 4 SYSCLK cycle wait is added if the Wn IOWS bit of the IOCTRL REG register n 0 or 1 is set to 1 A SYSCLK cycle wait is added if the Wn IOWS bit of the IOCTRL REG register n 0 or 1 is cleared to 0 352 User s Manual U14272EJ3VOUM CHAPTER 18 LED CONTROL UNIT LED 18 1 General This unit switches ON and OFF of LEDs at a regular interval The interval can be set via software 18 2 Register Set The LED registers are listed below Table 18 1 LED Registers Physical address Register symbol Function 0x0B00 0240 LEDHTSREG LED ON time set register 0 0 00 0242 LEDLTSREG LED OFF time set register 0x0B00 0248 LEDCNTREG
264. ect 0 high address A programmable chip select 0 will be generated when all of the following conditions have been met e The system address bits A 15 0 are equal to or greater than PCSOSTRA 15 0 and equal to or less than PCSOSTPA 15 0 nee e The internal address bits A 27 16 are equal to PCSOHIA 27 16 e The read write qualifier conditions specified by the PCSMODE register have been met Notes 1 Holds the value before reset 2 When the PCSO has been defined as a 16 bit chip select bit 0 of the address is ignored User s Manual U14272EJ3VOUM 269 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 19 PCS1STRA 0 0 00 0326 Name PCS1STRA PCS1STRA PCS1STRA 515 PCS1STRA PCS1STRA PCSISTRA PCS1STRA 15 14 13 12 11 10 9 8 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note RTCRST Other resets 15to 0 PCS1STRA 15 0 Programmable chip select 1 start address These bits determine the starting address for the memory or I O chip select Note Holds the value before reset 13 3 20 PCS1STPA 0x0B00 0328 Name 515 PCS1STPA PCS1STPA PCS1STPA 15 14 13 11 PCS1STPA PCS1STPA R W R W R W R W R W RTCRST Other resets Name R W RTCRST Other resets 15100 515 15 0 Programmable chip select 1 stop address These bits d
265. ed R W R W 0 0 Function IOWEN 1 0 window enables Generates the card enable signals to the card when an I O access occurs within the corresponding I O address window 0 Does not generate 1 Generates l O addresses are output from the system bus directly to the card Caution The start and stop address register pairs must be set to values for the window to be used before setting these bits to 1 Reserved 0 is returned when read MWEN 4 0 Memory window enables Generates the card enable signals to the card when a memory access occurs within the corresponding memory address window 0 Does not generate 1 Generates When the system address is within the window the computed address is output to the card Caution The start stop and offset address register pairs must be set to values for the window to be used before setting these bits to 1 Remark A single bit corresponds to each window 340 User s Manual U14272EJ3VOUM CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 8 IOCTRL REG Index 0x07 W1 IOWS IO1 CS16 101DSZ WO IOWS 100 516 100054 R W R W 0 0 Function I O window 1 wait addition in 16 bit accesses 0 No additional wait state 1 Adds 1 wait state W1 IOWS I O window 1 wait addition in 8 bit accesses 0 No additional wait state 1 Adds 1 wait state 1 CS16MD window 1 IOCS16 source
266. ed 3 LCD module LCD Control Unit Ox0AOO OBFF to Ox0A000400 VO ange The LCD module is selected when the above I O range is accessed User s Manual U14272EJ3VOUM 109 CHAPTER 6 BUS CONTROL 4 ISA Bridge Physical address Device 0x17FF FFFF to 0x1400 0000 I O 64M range External ISA bus I O Ox13FF FFFF to 0x1000 0000 Memory 64M range External ISA bus Memory OxOBFF FFFF to 0 0 00 0000 16M range ISA internal I O 1 OxOCFF FFFF to 0x0C00 0000 I O 16M range ISA internal 2 The ISA Bridge is selected when the above address ranges are accessed 6 2 Bus Control Registers External ROM accesses and supply of clocks to several internal units are controlled by the bus control registers listed below Table 6 1 Bus Control Registers Physical address R W Register symbol Function 0 0 00 0000 BCUCNTREG 1 BCU control register 1 0 0 00 0004 CMUCLKMSK Clock mask register 0x0A00 000C BCUSPEEDREG BCU access time parameters register 0x0A00 0010 BCURFCNTREG BCU refresh control register 0x0A00 0014 REVIDREG Revision ID register 0x0AO00 0018 CLKSPEEDREG Clock speed register Caution Since these registers are powered by 2 5 V power supply the contents of these registers are cleared after Hibernate mode 110 User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 6 2 1 BCUCNTREG1 0x0A00 0000 Name Reserved Reserved R W At reset
267. ed Address LLAddr register is not used with the 4181 processor except for diagnostic purpose and serves no function during normal operation The LLAddr register is implemented just for compatibility between the Vn4181 and Vn4000 or Vn4400 The contents of the LLAddr register are undefined after a reset Figure 3 19 LLAddr Register 31 0 PAddr 32 bit physical address 84 User s Manual U14272EJ3VOUM CHAPTER 3 REGISTERS 3 2 17 WatchLo 18 WatchHi 19 registers The Vn4181 processor provides a debugging feature to detect references to a selected physical address load and store instructions to the location specified by the WatchLo and WatchHi registers cause a Watch exception The contents of these registers are undefined after a reset so that they must be initialized by software Figure 3 20 WatchLo Register 31 3 2 1 0 mus PAddrO Specifies physical address bits 31 to R Specifies detection of watch address references when load instructions are executed 1 Detect 0 Not detect W Specifies detection of watch address references when store instructions are executed 1 Detect 0 Not detect 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read Figure 3 21 WatchHi Register 31 0 4 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read
268. ed and the scanned data are stored in the data buffers dedicated to A D port scanning The following figure shows an A D port scan timing diagram Figure 14 7 A D Port Scan Timing State XXX ADPScan XXX d MS AUDIOIN 7 V V J 7 ADIN 2 0 ADINO ADIN1 ADIN2 AUDIOIN ADPSSTART bit PIUASCNREG Remark XXX Standby WaitPenTouch or Interval 298 User s Manual U14272EJ3VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 7 Data Loss Conditions The PIU issues a data lost interrupt request when any of the following four conditions exist 1 Data for one coordinate has not been obtained within the interval period 2 The A D port scan has not been completed within the time set via PIUSTBLREG register 3 Transfer of the next coordinate data starts while valid data for both pages remains in the buffer 4 The next data transfer starts while there is valid data in the ADPScan buffer Once a data lost interrupt request occurs the sequencer is forcibly changed to the Standby state The cause and response to each condition are as follows 1 When data for one coordinate has not been obtained within the interval period Cause This condition occurs when the AIU has exclusive use of the A D converter and the PIU is therefore unable to use the A D converter If this data loss condition occurs frequently implement a countermeasure that temporarily prohibits the AIU s use of the A D converter Response
269. ed on 4 byte word or 8 byte doubleword boundaries e Word access LWL LWR SWL SWR e Doubleword access LDL LDR SDL SDR These instructions are used in pairs of L and R Accessing unaligned data requires one additional instruction cycle 1 PCycle over that required for accessing aligned data Figure 1 7 shows the access of an unaligned word that has byte address 3 Figure 1 7 Unaligned Word Accessing Little Endian 31 24 23 16 15 87 0 High order address Low order address 42 User s Manual U14272EJ3VOUM CHAPTER 1 INTRODUCTION 1 44 CPOregisters The CPO has thirty two registers each of which has its own register number Table 1 6 shows simple descriptions of each register For the detailed descriptions of the registers refer to CHAPTER 3 REGISTERS Table 1 6 System Control Coprocessor Register Definitions Register Index Memory management Description Programmable pointer to TLB array Random Memory management Pseudo random pointer to TLB array read only EntryLoO Memory management Lower half of TLB entry for even VPN EntryLo1 Memory management Lower half of TLB entry for odd VPN Context Exception processing Pointer to kernel virtual PTE in 32 bit mode PageMask Memory management Page size specification Wired Memory management Number of wired TLB entries Reserved for future use BadVAddr
270. ee ennt trennen 351 5104 Block DIagralriss eet HF ere P ERE e mbi e et Hd cbe Ne 360 SIU2 Blocke Diagram 2 setts i ed Ue ee ed ug eb alerts 379 LCD Controller Block 401 View Rectangle and Horizontal Vertical Blank 402 Position of Load Glock LOGLK s o 403 Position of Frame Clock FLM 3 oe dae eed cem Oe a te ree E de 404 Monochrome Panel 5 2 ire tete rete eder ctt Rte ipe ed e tee etd teer 408 Color Panelin 8 Bit Data BUS neri in eter letale ere deep deca Ee dee Ee ta 409 Load Glock ais si at heave te are Deae due a tac i edt 410 Frame Glocks EEM inire E DM MU GB MENTRE 410 LCD Timing Paraimeters i nat rtt eric e ee Lee EE Ue e EE CQ ee Yo eL uae secre 411 FEM Penod eter ie beer ecelesie ett ata m dae este seater eed c 411 Example of Connection of PLL Passive Components 0 csceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseaeeeeaeeseaeeeeeeeseaeeeaeersas 430 Mask Circuit for RSTSW Signal sessssssssesseseeeen nennen enne nnns enne nnne nnne nne 436 Release of Self Refresh Mode by RSTSW Signal EDO DRAM 437 Release of Self Refresh Mode by RSTSW Signal SDRAM e ccesceeeeeeeeeeeeeeeeseeeeeeeteeeeeeeteeeeea
271. een the Vn4181 and an external matrix type keyboard This unit supports key matrix of 8 x 8 The interface to the keyboard consists of SCANOUT 3 state output and SCANIN input lines The SCANOUT lines are used to search the matrix for pressed keys The SCANIN lines are used to sense key press events and are read after each SCANOUT line being at low level to locate the pressed key SCANOUT and SCANIN lines are allocated by programming CompactFlash pins to support this function during the power on If those pins are set as for keyboard interface CompactFlash interface cannot be used 16 2 Functional Description When the keyboard is idle the SCANOUT lines are all driven to 0 volts and the SCANIN lines are pulled to Voo by external 4 7 resistors When any key in the matrix is pressed at least one SCANIN input is driven as low and signals a key press event to the KIU Once the key press event has been detected the KIU may be programmed to generate a key down interrupt request and to begin scanning the keyboard automatically or to wait until software enables the scan operation Keyboard scanning is performed by sequentially driving one SCANOUT line as low while the others remain high impedance and reading the state of the SCANIN lines and storing into keyboard data registers inside the KIU Once the last SCANOUT line has been driven as low and the SCANIN lines read the KIU may generate a Keyboard Data Ready interrupt request to inform system so
272. eereas 438 User s Manual U14272EJ3VOUM LIST OF TABLES 1 2 Table No Title Page 1 1 Supported PClock and TClock Frequencies sssssseeeeeeeeeeeenneee nennen nnnm 31 1 2 Devices Supported by System Bus nne tenen 31 1 3 GPIO 31 0 Pin FUNCIONS ERR e Ute Eo o c te Ee a oA 33 1 4 LCD Panel Resolutions in Pixels 34 1 5 Functions of LCD Interface Pins when LCD Controller Is Disabled 2 34 1 6 System Control Coprocessor CPO Register Definitions 2 43 1 7 List of Instructions Supported by Vn Series Processors 46 3 1 PO Registers tet ale iR E aati niin te cavere ri e ERSTE 68 3 2 Gache Algofithii s p eee en e deed eee e eed d 71 3 3 Mask Values and Page Sizes 20500 ene end Pe dee de ete one ve exe dees 72 3 4 Cause Register Exception Code Field 2 22 24 enne nnne neret rennen nnns 80 4 1 VR4181 Physical Address Space smiir heap rena ea aai arenai i eda 93 4 2 ROM Add ess Map ed RR EE ee Bp 93 4 3 Internalil O Spaces ce a e in eie one e te 94 4 4 Internal B ETo Te C 94 4 5 MBA Bus l O Sp ce ismin dee ede rette aet ed e tas et c ded e
273. efer to 4100 Series Architecture User s Manual 1 Translation lookaside buffer TLB Virtual memory mapping is performed using the translation lookaside buffer TLB The TLB translates virtual addresses to physical addresses It runs by a full associative method and has 32 entries each of which two successive pages are mapped The TLB of the 4181 holds both instruction addresses and data addresses so that it is called as joint TLB JTLB The page size can be configured on a per entry basis to map a page size of 1 KB to 256 KB in power of four A CPO register stores the size of the page to be mapped and that size is entered into the TLB when a new entry is written Thus operating systems can provide special purpose maps for example a typical frame buffer can be memory mapped using only one TLB entry Translating a virtual address to a physical address begins by comparing the virtual address from the processor with the physical addresses in the TLB There is a match when the virtual page number VPN of the address is the same as the VPN field of an entry and either the Global G bit of the TLB entry is set or the ASID field of the virtual address is the same as the ASID field of the TLB entry This match is referred to as a TLB hit If there is no match a TLB Miss exception is taken by the processor and software is allowed to refill the TLB from a page table of virtual physical addresses in memory 1 4 7 Cache Vn4181 chip i
274. efore accessing them after an RTC reset or RSTSW reset is canceled or after the 4181 restores from the Hibernate mode An initialization of SDRAMs must be executed until the Vn4181 issues the first CBR auto refresh cycle Remark During the 64 Mbit SDRAM mode register write A13 of the address bus is at high level On the other hand during the 16 Mbit SDRAM mode register write A13 is at low level In order to initialize 64 Mbit SDRAM correctly software must execute the following sequence 1 Set BOConfig 1 0 and B1Config 1 0 bits of MEMCFG REG register to 01 2 Set MODE REG register to appropriate value 0x00n7 n can be any value 3 Initialize SDRAM by setting Init bit of MEMCFG REG register 4 Set BOConfig 1 0 and B1Config 1 0 bits of MEMCFG REG register to 10 134 User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 6 5 3 MODE REG 0x0A00 0308 Name TE Ven1 R W R W At reset 0 2 R W LTMode2 LTMode1 LTModeO At reset Bit Name Function 15 to 12 Reserved 0 is returned when read 11 10 0 These bits should be always written to 00 9 BR SW Burst read single write This bit should be always written to 0 8 7 TE Ven 1 2 These two bits define a JEDEC test cycle and vendor specific cycles These bits should be always written to 00 Note 6 to 4 LTMode 2 0 CAS latency mode 010 2 clo
275. egister is set to 0 upon Cold Reset Writing this register also sets the Random register to the value of its upper bound see 3 2 2 Random register 1 Figure 3 7 Wired Register 31 54 0 Lowe Wired TLB wired boundary 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read User s Manual U14272EJ3VOUM 73 CHAPTER 3 REGISTERS 3 2 7 BadVAddr register 8 The Bad Virtual Address BadVAddr register is a read only register that saves the most recent virtual address that failed to have a valid translation or that had an addressing error Caution This register saves no information after a bus error exception because it is not an address error exception Figure 3 8 BadVAddr Register a 32 bit mode 31 0 b 64 bit mode 63 0 BadVAddr BadVAddr Most recent virtual address for which an addressing error occurred or for which address translation failed 3 2 8 Count register 9 The read write Count register acts as a timer It is incremented in synchronization with the MasterOut clock 1 8 1 12 or 1 16 frequencies of the PClock regardless of whether instructions are being executed retired or any forward progress is actually made through the pipeline This register is a free running type When the register reaches all ones it rolls over to zero and continues counting This register is used for self diagnostic test system initialization or the es
276. elect 1 stop address register 0 0 00 032A PCS1HIA Programmable chip select 1 high address register 0x0B00 032C PCSMODE Programmable chip select mode register 0 0 00 032E 244 LCDGPMODE LCD general purpose mode register User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU Physical address 0 0 00 0330 Table 13 11 GIU Registers 2 2 Register symbol MISCREGO General purpose register 0 0 00 0332 5 0 0 00 0334 MISCREG2 0 0 00 0336 MISCREG3 0 0 00 0338 MISCREG4 0x0B00 033A MISCREG5 0 0 00 033C MISCREG6 0 0 00 033E MISCREG7 0 0 00 0340 MISCREG8 0 0 00 0342 MISCREG9 0 0 00 0344 MISCREG10 0 0 00 0346 MISCREG11 0 0 00 0348 MISCREG12 0 0 00 034A MISCREG13 0x0B00 034C MISCREG14 0 0 00 034E MISCREG15 User s Manual U14272EJ3VOUM Function 245 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 1 GPMDOREG 0 0 00 0300 Name GP7MD1 GP7MDO GP6MD1 GP6MDO GP5MD1 GP5MDO GP4MD1 1 2 GP4MDO R W R W R W R W R W R W R W R W R W RTCRST Other resets GP3MD1 GP3MDO GP2MD1 GP2MDO GP1MD1 GP1MDO GPOMD1 GPOMDO RTCRST R W R W R W R W R W R W R W R W Other resets GP7MD 1 0 Function These bits control dire
277. en 1 is written 1 FIFO and its counter clear 0 Normal 1 FCR1 Receive FIFO and its counter clear Cleared to 0 when 1 is written 1 FIFO and its counter clear 0 Normal 0 FCRO Receive Transmit FIFO enable Cleared to 0 when 1 is written 1 Enable 0 Disable This register is used to control the FIFOs User s Manual U14272EJ3VOUM 387 CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 388 FIFO interrupt modes When receive FIFO is enabled and receive interrupt requests are enabled receive interrupts can occur as described below 1 When the FIFO is reached to the specified trigger level a receive data ready interrupt request is notified to the CPU This interrupt is cleared when the FIFO goes below the trigger level When the FIFO is reached to the specified trigger level the SIUIID 2 register indicates a receive data ready interrupt request Same as the interrupt above the SUIID 2 register is cleared when the FIFO goes below the trigger level The receive line status interrupt is assigned to a higher priority level than the receive data ready interrupt When characters are transferred from the shift register to the receive FIFO 1 is set to the LSRO bit of the SIULS 2 register The value of this bit returns to 0 when the FIFO becomes empty When receive FIFO is enabled and receive interrupts are enabled receive FIFO timeout interrupt requests can occur as described below Followings are the con
278. en of these GPIO 31 16 are available through pins allocated to other functions as shown in the following table The DCD14Z GPIO29 is the only one of the 16 pins that can cause the system s waking up from a low power mode if enabled by software The other pins have no functions other than those listed below The remaining 16 bits of general purpose GPIO 15 0 are allocated to pins by default Each of these pins can be configured to support a particular interface such as CSI secondary serial interface RS 232 C programmable chip selects or color LCD control Otherwise each of these pins can be also defined as one of the following e General purpose input General purpose output e Interrupt request input e Wake up input Table 1 3 GPIO 31 0 Pin Functions Pin designation GPIOO Alternate function GPIO16 Pin designation Alternate function IORD GPIO1 GPIO17 IOWR GPIO2 GPIO18 IORDY GPIO3 GPIO19 10 516 GPIO4 Note GPIO20 M UBE GPIO5 DCD2 21 RESET GPIO6 RTS2 GPIO22 ROMCSO GPIO7 DTR2 GPIO23 ROMCS1 GPIO8 DSR2 24 ROMCS2 GPIO9 CTS2 25 RxD1 GPIO10 FRM SYSCLK GPIO26 TxD1 GPIO11 PCS1 27 RTS1 GPIO12 FPD4 GPIO28 CTS1 GPIO13 FPD5 GPIO29 DCD1 GPIO14 FPD6 CD1 GPIO30 DTR1 GPIO15 Note This
279. en the HALTIMERRST bit is cleared to O just after set to 1 the HALTimer may not be reset Wait more than 6 RTC clock cycles from writing 1 to writing O 2 Verify that the HALTIMERRST bit is 0 before reset the HALTimer When this bit is 1 the HALTimer is not reset even if write 1 to this bit In this case write O to this bit first then write 1 after more than 6 RTC clock cycles This register is used to set CPU core shutdown and overall system operations management The HALTIMERRST bit must be reset within about four seconds after activation Resetting of the HALTIMERRST bit indicates that the VR4181 itself has been activated normally If the HALTIMERRST bit is not reset within about four seconds after activation program execution is regarded as abnormal possibly due to a runaway and an automatic shutdown is performed 212 User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 7 3 PMUWAITREG 0 0 00 00A8 Name Reserved Reserved WCOUNT WCOUNT WCOUNT WCOUNT WCOUNT WCOUNT 13 12 11 10 R W R W R W R W R W RTCRST Other resets RTCRST Other resets Reserved 0 is returned when read WCOUNT 13 0 Activation wait time timer count value Activation wait time WCOUNT 13 0 x 1 32 768 ms Note Holds the value before reset This register is used to set the activation wait time when the CPU core is activated This register is set to 0x2C00 i e 343 75 ms activation wa
280. er resets GPHST23 GPHST22 GPHST21 GPHST20 GPHST19 GPHST18 GPHST17 5 16 R W R W R W R W R W R W R W R W RTCRST Other resets Function GPHST 31 16 GPIO Hibernate pin state control There is a one to one correspondence between these bits and GPIO pins These bits determine the state of GPIO 31 16 pins during Hibernate mode as follows 0 Output pin is in high impedance Input pin is ignored during Hibernate mode Output pin remains actively driven Input pin is monitored during Hibernate mode Note Holds the value before reset Caution GPIO29 pin DCD1 can be input at high level and monitored during Hibernate mode and therefore the GPHST29 bit can be set to 1 The GPHST bits for all other GPIO pins configured as inputs should be reset to 0 User s Manual U14272EJ3VOUM 263 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 13 GPHIBSTL 0 0 00 0318 Name GPHST15 GPHST14 GPHST13 GPHST12 GPHST11 GPHST10 GPHST9 GPHST8 R W R W R W R W R W R W R W R W R W RTCRST Other resets GPHST7 GPHST6 GPHST5 GPHST4 GPHST3 GPHST2 GPHST1 GPHSTO R W R W R W R W R W R W R W R W RTCRST Other resets Function GPHST 15 0 GPIO Hibernate pin state control There is a one to one correspondence between these bits and GPIO pins These bits determine the state of GPIO 15 0 pins during Hibernate mode as follows 0 Output pin is in h
281. eral p 380 Modification of description in Table 20 1 SIU2 Registers pp 381 383 395 Modification of values at reset in 20 3 1 through 20 3 3 20 3 5 and 20 3 12 p 384 Addition of description in Table 20 2 Correspondence between Baud Rates and Divisors p 387 Modification of descriptions for bits 2 to 0 in 20 3 7 SIUFC 2 0 0 00 0002 Write p 392 Modification of R W and addition of description in 20 3 10 SIULS 2 0 0 00 0005 p 394 Modification of descriptions for bits 7 to 4 in 20 3 11 SIUMS 2 0 0 00 0006 p 395 Addition of description in 20 3 13 SIUIRSEL 2 0 0 00 008 p 397 Modification of R W for bit 1 in 20 3 16 SIUACTMSK 2 0 0 00 000C User s Manual U14272EJ3VOUM 9 Major Revisions in This Edition 5 5 Page Description 399 Modification of description in 21 1 1 LCD interface 401 Modification of bus width in Figure 21 1 LCD Controller Block Diagram 406 Modification of description in 21 3 4 Frame buffer memory and FIFO 420 Addition of Remark in 21 4 11 LCDCFGREGO 0 0 00 0414 428 Addition of Remark in 21 4 22 CPINDCTREG 0x0A00 047E 429 Addition of Caution in 21 4 23 CPALDATREG 0x0A00 0480 433 Addition of Caution in Table 23 1 Coprocessor 0 Hazards pp 436 to 438 Addition of APPENDIX RESTRICTIONS ON Vn4181 pp 439 to 444 Addition of APPENDIX B INDEX The mark shows major revised points 10 User s Manual U1
282. eral purpose I O or serial channel 2 clear to send output GPIO8 DSR2 General purpose or serial channel 2 data set ready input GPIO7 DTR2st General purpose or serial channel 2 data terminal ready input GPIO6 RTS2 GPIOS DCD2 General purpose I O or serial channel 2 request to send output General purpose or serial channel 2 data carrier detect input 4 General purpose 5 0 General purpose or programmable chip select 0 GPIO2 SCK General purpose or serial clock input for clocked serial interface GPIO1 SO General purpose or serial data output signal for clocked serial interface GPIOO SI 58 General purpose I O or serial data input signal for clocked serial interface User s Manual U14272EJ3VOUM CHAPTER 2 PIN FUNCTIONS 2 2 12 Dedicated Vpp GND signals Signal name Power Description of function supply VDD PLL 2 5 V Power supply dedicated for the PLL analog block GND_PLL 2 5 V Ground dedicated for the PLL analog block VDD_TP 3 3 V Power supply dedicated for the touch panel interface GND_TP 3 3 V Ground dedicated for the touch panel interface VDD_AD 3 3 V Power supply dedicated for the A D and D A converters The voltage applied to this pin becomes the maximum value for the A D and D A interface signals GND_AD 3 3 V Ground dedicated for the A D and D A conver
283. eral purpose registers are located in the address range of 0 0 00 0330 to 0 0 00 034F 13 2 Alternate Functions Overview 13 2 1 Clocked serial interface CSI The clocked serial interface is enabled by writing to the GPIO Mode registers and utilizes the following GPIO pins Table 13 3 CSI Interface Signals GPIO pin CSI signal GPIO2 Input GPIO1 Output GPIOO Input GPIO10 Input The GPIO10 FRM pin provides a multifunction control input option In one mode FRM determines data direction transmit or receive In the other mode FRM prohibits transfer depending on its input level This mode is set in bit 15 FRMEN of the CSIMODE register address 0 0 00 0900 see CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 238 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 2 2 Serial interface channels 1 and 2 The GIU also provides pin mapping for the serial interface equivalent to 16550 UART channels 1 and 2 The serial interface channel 1 SIU1 is enabled by writing to the GPIO Mode registers It utilizes the following GPIO pins Table 13 4 Serial Interface Channel 1 SIU1 Signals GPIO pin 5101 signal GPIO26 Output GPIO25 Input GPIO31 Input GPIO30 Output GPIO28 Input GPIO27 Output GPIO29 Input The GIU drives inputs to the serial interface channel 1 based on the settings in the GPIO Mode registers and bit 15 LOOPBK1 of the GPSICTL register
284. erface channels 1 42 nnns nnne 239 13 2 3 LGD interface ande EIE eg Lp Cae LU bec pere ce REC oues 241 19 2 4 Programmable chip selects iecit t dente rere e et uc n de d ee 242 13 2 5 16 Dit bus Cycles ei 242 13 2 6 General purpose input output ssssssssssseeeneneeneeneee nennen nennen nennen nnne entren nens 242 13 2 7 Interrupt requests and wake up EVENTS 243 13 3 AIT ICM DO 244 13 31 GPMDOREG 0x0B00 0900 oriri e n ertt gue dee qt qu te a re RE E edet 246 13 3 2 GPMD1REG 0 0 00 0302 402424204 0011 000000 anA EA A nenne enne 248 13 3 3 GPMD2REG 0 0 00 0304 220 edi eh eaten ieee 250 13 3 4 GPMDSREG 0 0 00 0306 252 13 3 5 GPDATHREG 0 0 00 0308 5 eo ERE RR RR RR 254 13 3 6 GPDATEREG 0x0BO0O0 030A 1 2 i ete re tb pete e eee eiue 255 13 3 7 GPINTEN 0X0B00 030G 22 2 oett one toa Dirt Cebu de eem oie soit 256 13 3 8 GPINTMSK 0 0 00 OS0E tnter entren nnns 257 133 9 GPINTTYPEL 0x0BO00 09 10 irit iere Rs ec ends ete 258 13 310 GPINTTYBL 0x0B00 08 12 2 5 ipn ro De Beas 260
285. ertion of MPOWER Assertion and then deassertion of RTCRST BATTINH high normal activation Assertion and then deassertion of RTCRST BATTINH low BATTINH shutdown User s Manual U14272EJ3VOUM 189 CHAPTER 10 POWER MANAGEMENT UNIT PMU Table 10 1 shows power mode overview and transaction Table 10 1 Overview of Power Modes Internal peripheral unit CPU core DMA LCDC Others Fullspeed On On On On Selectable On Standby On On On On Selectable Off Suspend On On Off Off Off Off Hibernate On Off Off Off Off Off Off Off Off Off Off Off Off 1 Fullspeed mode All internal clocks and bus clocks operate The 4181 can perform every function during the Fullspeed mode 2 Standby mode The pipeline clock PClock of the CPU core is fixed to high level PLL timer interrupt function of the CPU core interrupt clock MasterOut internal bus clock TClock and PCLK and RTC clock continue their operation Therefore all the on chip peripheral units continue their operation operation of the LCD controller and DMA also continue The contents of caches and registers in the CPU core are retained To enter to Standby mode from Fullspeed mode execute the STANDBY instruction After the STANDBY instruction has passed the WB stage the Vn4181 waits until SysAD bus internal enters idle state Then internal clocks are shut down and pipeline operation stops To restore to Fulls
286. eserved Reserved Reserved Reserved TPPSCAN ADPS START R W R R R R R R R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Function Reserved 0 is returned when read TPPSCAN Port selection for ADPScan 1 Select TPX 1 0 TPY 1 0 for touch panel as A D port 0 Select ADIN 2 0 general purpose as A D port and AUDIOIN as audio input port ADPSSTART ADPScan start 1 Start ADPScan 0 Do not perform ADPScan This register is used for ADPScan setting The ADPScan begins when the ADPSSTART bit is set After the ADPScan is completed the sequencer returns to the state when ADPScan was started and the ADPSSTART bit is cleared to 0 automatically If the ADPScan is not completed within the time period set via the STABLE bits of the PIUSTBLREG register a data lost interrupt request occurs as a timeout interrupt Caution Manipulation of the TPPSCAN bit is valid only in the standby state In the other states the operation is not guaranteed Some bits in this register cannot be set in a specific state of scan sequencer The combination of the setting of this register and the sequencer state is as follows User s Manual U14272EJ3VOUM 289 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU Table 14 4 PIUASCNREG Bit Manipulation and States PIUASCNREG bit Scan sequencer s state manipulation Disable Standby WaitPenTouch DataScan lote2 ADPSSTART ADPScan ADPScan TPPSCAN PIUCNTRE
287. eset to 0 and a GPIO pin has not been enabled to provide CTS1 the CTS1 input to the serial interface channel 1 is driven with the value of this bit REGDSR1 DSR1 data When the LOOPBK 1 bit is reset to 0 and a GPIO pin has not been enabled to provide DSR1 the DSR1 input to the serial interface channel 1 is driven with the value of this bit REGDCD1 Note Holds the value before reset DCD1 data When a GPIO pin has not been enabled to provide DCD1 the DCD1 input to the serial interface channel 1 is driven with the value of this bit User s Manual U14272EJ3VOUM REGDCD2 265 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 2 2 Function LOOPBK2 Loopback enable for serial interface channel 2 When GPIO pins have not be allocated for the line status signals DSR2 and or CTS2 of the serial interface channel 2 this bit can be set to 1 to allow the serial interface line status output signals to be connected to the line status input signals as follows DTR2 output from serial interface drives the DSR2 input to serial interface RTS2 output from serial interface drives the CTS2 input to serial interface Reserved 0 is returned when read REGCTS2 CTS2 data When the LOOPBK bit is reset to 0 and GPIO pin has not been enabled to provide CTS2 the CTS2 input to the serial interface channel 2 is driven with the value of this bit REGDSR2 DSR2 data When the LOOPBKO bit is reset to 0 and a GP
288. ess Stopped User s Manual U14272EJ3VOUM CHAPTER 16 KEYBOARD INTERFACE UNIT KIU 16 3 4 KIUWKS 0 0 00 0194 Name Reserved 4 2 0 Reserved Reserved R W RTCRST Other resets RTCRST Other resets 15 Reserved Function 0 is returned when read 14 to 10 T3CNT 4 0 Scan idle time These bit determine the wait time the scan sequencer waits following a deassertion of one SCANOUT pin before an assertion of the next SCANOUT pin 11111 960 us T3CNT 4 0 1 x 30 us 00001 60 us 00000 Setting prohibited 9to5 Reserved 0 is returned when read 4100 T1CNT 4 0 Scan data stabilization time These bits determine the time the scan sequencer waits following an assertion of a SCANOUT pin before return data is read 11111 960 us 22 T1CNT 4 0 1 x 30 us 00001 60 us 00000 Setting prohibited 325 User s Manual U14272EJ3VOUM CHAPTER 16 KEYBOARD INTERFACE UNIT KIU 16 3 5 KIUWKI 0 0 00 0196 Name Reserved Reserved Reserved Reserved Reserved Reserved WINTVL9 WINTVL8 R W RTCRST Other resets RTCRST Other resets Function 15 to 10 Reserved 0 is returned when read 9100 9 0 Scan interval time These bits determine the time the scan sequencer waits following completion of one scan operation before starting the
289. et an XTLB Refill exception occurs if a TLB miss occurs in the Kernel mode address space 64 bit addressing and operations are enabled for Supervisor mode when SX bit 1 If this bit is set an XTLB Refill exception occurs if a TLB miss occurs in the Supervisor mode address space e 64 bit addressing and operations are enabled for User mode when UX bit 1 If this bit is set an XTLB Refill exception occurs if a TLB miss occurs in the User mode address space 4 Status after reset The contents of the Status register are undefined after Cold Resets except for the following bits in the Diagnostic Status field e TS and SR bits are cleared to 0 SR bit is 0 after Cold Reset and is 1 after Soft Reset or NMI e ERL and BEV bits are set to 1 Remark Cold Reset and Soft Reset are resets for the CPU core see 5 3 Reset of CPU Core For the reset of all the Vn4181 including peripheral units refer to CHAPTER 5 INITIALIZATION INTERFACE and CHAPTER 10 POWER MANAGEMENT UNIT PMU 78 User s Manual U14272EJ3VOUM CHAPTER 3 REGISTERS 3 2 12 Cause register 13 The 32 bit read write Cause register holds the cause of the most recent exception 5 bit exception code indicates one of the causes see Table 3 4 Other bits hold the detailed information of the specific exception All bits in the Cause register with the exception of the IP1 and IPO bits are read only IP1 and IPO bits are used for software interrupts Figure 3 14 Ca
290. et and starts the Cold Reset sequence to activate the CPU core If the BATTINH signal is at low level the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown After the CPU core is restarted the BATTINH bit must be checked and cleared to 0 by software Remark Activation via Power Switch interrupt request never sets the POWERSWINTR bit in the PMUINTREG register to 1 Figure 10 3 Activation via Power Switch Interrupt Request BATTINH f ATC intema MMC POWER Input POWERON Output 1 7 MPOWER Output BATTINH BATTINT Input Figure 10 4 Activation via Power Switch Interrupt Request BATTINH L RTC Internal f f POWER Input POWERON Output MPOWER Output L Input User s Manual U14272EJ3VOUM 195 CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 5 2 Activation via CompactFlash interrupt request When the CF BUSY signal is asserted the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated After asserting the POWERON signal the PMU checks the BATTINH signal and then de asserts the POWERON signal If the BATTINH signal is at high level the PMU cancels peripheral unit reset and starts the Cold Reset sequence to activate the CPU core If the BATTINH signal is at low level
291. etermine the ending address for the memory or I O chip select Note Holds the value before reset 270 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 24 PCS1HIA 0 0 00 032A Name Reserved Reserved Reserved Reserved PCS1HIA PCS1HIA PCS1HIA PCS1HIA 27 26 25 R W R W R W R W R W RTCRST Other resets PCS1HIA PCS1HIA PCS1HIA PCS1HIA PCS1HIA PCS1HIA PCS1HIA PCS1HIA 23 22 21 20 19 18 17 16 R W R W R W R W R W R W R W R W RTCRST Other resets Function 15to 12 Reserved 0 is returned when read 11 to 0 PCS1HIA 27 16 Programmable chip select 1 high address A programmable chip select 1 will be generated when all of the following conditions have been met e The system address bits A 15 0 are equal to or greater than PCS1STRA 15 0 and equal to or less than PCS1STPA 15 0 iis e The internal address bits 27 16 are equal to PCS1HIA 27 16 e The read write qualifier conditions specified by the PCSMODE register have been met Notes 1 Holds the value before reset 2 When the PCS1 has been defined as a 16 bit chip select bit 0 of the address is ignored Users Manual U14272EJ3VOUM 271 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 22 PCSMODE 0 0 00 032C Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets Name PCS1MIOB
292. ets TIMOUT POWER RST SWINTR RTCRST Other resets 15 to 13 Reserved Function 0 is returned when read 12 GPWAKEUP GPIO interrupt request detection Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is restarted CompactFlash interrupt request detection Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is restarted DCD1 pin state 1 High level inactive 0 Low level active RTCINTR ElapsedTime RTC alarm interrupt request detection Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is restarted BATTINH Battery low detection during activation Cleared to 0 when 1 is written 1 Detected 0 Not detected This bit must be checked and cleared to 0 after the CPU core is restarted Reserved Write 0 when write 0 is returned when read SDRAM This bit determines whether the internal peripheral units are reset by RSTSW This bit must be clear to 0 when EDO DRAM is used 1 Not reset SDRAM data preserved during RSTSW 0 Reset SDRAM data lost during RSTSW User s Manual U14272EJ3VOUM 209 CHAPTER 10 POWER MANAGEMENT UNIT PMU 2 2 Function TIMOUTRST HALTimer reset request detection Cleared to
293. f the KO bit in the Config register is changed by executing an MTCO instruction within the 0 or ckseg0 area the change is reflected one to three instructions later from the MTCO instruction The instruction following an MTCO instruction must not be an MFCO instruction The five instructions following an MTCO instruction for the Status register that changes the KSU bit and sets the EXL and ERL bits may be executed in the new mode and not kernel mode This can be avoided by setting the EXL bit first leaving the KSU bit set to kernel and later changing the KSU bit If interrupts are disabled by setting the EXL bit in the Status register with an MTCO instruction an interrupt may occur immediately after the MTCO instruction without change of the contents of the EPC register This can be avoided by clearing the IE bit first and later setting the EXL bit There must be two non load non CACHE instructions between a store and a CACHE instruction directed to the same cache line to be stored The status during execution of the following instruction for which CPO hazards must be considered is described Destination The completion of writing to a destination register CPO of MTCO MFCO Source TLBR Source The confirmation of a source register CPO of MFCO The confirmation of the status of TLB and the Index register before the execution of TLBR Destination The completion of writing to a destination register CPO of TLBR TLBWI
294. from a CompactFlash card 0 Busy 1 Ready 4 WP Memory write protect switch status This bit indicates the current status of WP 101516 signal from a CompactFlash card 0 Off 1 3 2 CD 2 1 Complement of the values of 1 and 2 11 Active low level 00 Inactive high level Values other than above are not displayed 1 Reserved 0 is returned when read 0 BVD1 This bit indicates the current status of STSCHG CF_STSCHG signal from CompactFlash card Note card detect pins 1 and CD2 alternate with GPIO pins When the GPIO pins not programmed as card detect input the CD 2 1 bits of this register always return 11 active In this way the CompactFlash interface can be used without the card detect pins When the GPIO pins are programmed as card detect the CD 2 1 bits are reflected in actual status of the CD1 and CD2 pins User s Manual U14272EJ3VOUM 335 CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 3 PWRRSETDRV Index 0x02 Reserved Reserved Reserved Reserved Reserved Reserved R W 0 Function 7 OE Output enable If this bit is cleared to 0 the CompactFlash interface outputs from the VR4181 are driven to high impedance state and the CF_DEN and CF_AEN outputs are driven as high Caution This bit should not be set until this register has been written to set the CompactFlash card power enable 6 Rese
295. fter ANDed with IMSKOn bits in the INTMSKREG register n 0 to 15 17 3 3 CFG_REG_1 0x0B00 08FE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R R R R R R R 0 Reserved 0 0 0 0 0 is returned when read 0 0 WSE User s Manual U14272EJ3VOUM Internal ISA cycle 1 wait state insertion enable This bit controls wait insertion when accessing the ECU registers Write 1 to this bit when write 1 Enable 333 CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 ECU Registers 17 4 1 ID REV REG Index 0x00 Name IFTYP1 IFTYPO Reserved Reserved REV3 REV2 REV1 REVO R W R R R R R R Reset 1 0 0 0 0 0 1 1 Function IFTYP 1 0 PCSC interface type These bits indicate 10 to reflect that both memory and cards are supported Reserved 0 is returned when read REV 3 0 Revision level 0011 is always displayed 334 User s Manual U14272EJ3VOUM CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 2 IF STAT REG Index 0x01 Reserved RDY BSY Reserved R Undefined Undefined Undefined Function Reserved 1 is returned when read 6 PWRON CompactFlash card power status 0 Off 1 On 5 RDY BSY CompactFlash card ready busy status This bit indicates the current status of RDY BSY CF_BUSY signal
296. fter a read Reserved 0 is returned after a read This register indicates interrupt status of each DMA channel by end of process EOP Once an interrupt occurs clear the interrupt request by writing a zero to the corresponding status bit in this register User s Manual U14272EJ3VOUM 153 CHAPTER 7 DMA CONTROL UNIT DCU 7 2 12 DMACTLREG 0 0 00 0664 SpkCNT1 SpkCNTO MicCNT1 MicCNTO Reserved Reserved R W R W R W R W R W At reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W At reset Bit Name Function SpkCNT 1 0 Speaker channel source address count control 00 Increment 01 Decrement Others Reserved MicCNT 1 0 Microphone channel destination address count control 00 Increment 01 Decrement Others Reserved Reserved 0 is returned after a read Reserved Write 0 when write 0 is returned after a read 154 Users Manual U14272EJ3VOUM CHAPTER 7 DMA CONTROL UNIT DCU 7 2 13 DMAITMKREG 0x0A00 0666 Name Reserved Reserved R W At reset Bit 7 6 5 4 3 2 1 0 Reserved Reserved SpkEOPMsk MicEOPMsk Reserved Reserved Reserved Reserved R W At reset Reserved 0 is returned after a read SpkEOPMsk Speaker channel end of process EOP interrupt mask 0 Disable 1 Enable MicEOPMsk Microphone cha
297. ftware that one keyboard scan operation has been completed The KIU repeats this scan process until no further keys have been detected or until software disables the scan operation At this point the KIU enters to the keyboard idle state or key press wait state User s Manual U14272EJ3VOUM 317 CHAPTER 16 KEYBOARD INTERFACE UNIT KIU The following table illustrates the relationship between these bits Table 16 1 Settings of Keyboard Scan Mode ASTART MSTART Operation 0 0 0 0 Scanning disabled X X X 1 Scanning stopped 0 X 1 0 Manual Scan mode Scan operation starts as soon as a setting of the MSTART bit is detected by the scan sequencer and stops when the MSTOP bit is set to 1 1 X 1 0 Manual Scan with Auto Stop mode Scan operation starts as soon as a setting of the MSTART bit is detected by the scan sequencer and stops when no valid keyboard data has been read for STPREP 5 0 times of consecutive scan cycles 0 1 0 0 Auto Scan with Manual Stop mode Scan operation starts as soon as a key press is detected by the scan sequencer and stops when the MSTOP bit is set to 1 1 1 0 0 Auto Scan mode Scan operation starts as soon as a key press is detected by the scan sequencer and stops when no valid keyboard data has been read for STPREP 5 0 times of consecutive scan cycles 16 2 1 Automatic keyboard scan mode Auto Scan mode Automatic Scan mode is enabled through the ASTART and ASTOP bits of t
298. fword word or doubleword the byte ordering can be set as either big endian or little endian However the Vn4181 only support the little endian order Endianness refers to the location of byte 0 within the multi byte data structure Figure 1 6 show the configuration When configured as a little endian system byte 0 is always the least significant rightmost byte which is compatible with Pentium and DEC conventions 40 In this manual bit designations are always little endian User s Manual U14272EJ3VOUM CHAPTER 1 INTRODUCTION Figure 1 6 Byte Address in Little Endian Byte Order a Word data Word 31 24 23 16 15 87 0 address High order js address 8 4 Low order 0 address b Doubleword data W Half B i ord _ Byte Doubleword 63 32 31 1615 87 0 address High order i address 8 Low order 0 address Remarks 1 The lowest byte is the lowest address 2 The address of word data is specified by the lowest byte s address User s Manual U14272EJ3VOUM 41 CHAPTER 1 INTRODUCTION The CPU core uses the following byte boundaries for halfword word and doubleword accesses Halfword An even byte boundary 0 2 4 Word A byte boundary divisible by four 0 4 8 Doubleword byte boundary divisible by eight 0 8 16 The following special instructions are used to load and store data that are not align
299. g particular attention Remark Supplementary information Numeric representation binary decimal XXXX hexadecimal OXXXXX Prefixes representing an exponent of 2 for address space or memory capacity kilo 2 1024 mega 2 1024 G giga 2 1024 tera 2 1024 peta 2 1024 E exa 2 1024 User s Manual U14272EJ3VOUM 11 Related Documents When using this manual also refer to the following documents Document name Document number Vr4181 Hardware User s Manual This manual 30181 VR4181 Data Sheet U14273E VRA4100 Series Architecture User s Manual U15509E VR Series Programming Guide Application Note U10710E The related documents indicated here may include preliminary version However preliminary versions are not marked as such 12 User s Manual U14272EJ3VOUM CONTENTS CHAPTER 1 INTRODUCTION eee du ca nao te ya pce 29 JEEP 29 1 2 Ordering Information 30 1 3 Vn4181 Key Features eiue ua 30 diiit mt cte dee Doc ducta tet e cer or oft cfe 31 1 3 2 Bus Interface ore Ro PR RR ERR MER ET 31 1 3 3 ee p eet Hte ge ee ees 32 1 34 DMA controller DG e
300. g the auto stop counter LED blinking terminates when the auto stop counter reaches 0 Caution Setting the LEDENABLE and LEDSTOP bits to 0 is prohibited because it may cause undefined operation LED blinking operation termination gt LEDENABLE LED blinking operation is terminated by setting O to this bit LED blinking operation terminate interrupt request generation LEDINT An interrupt request to the ICU is generated when 1 is set to this bit Note Initial setting for each register must be performed when a power is supplied to device for the first time regardless whether LEDs blinking function is used or not User s Manual U14272EJ3VOUM 359 CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 1 General The SIU1 is a serial interface that conforms to the RS 232 C communication standard and is equipped with two one channel interfaces one for transmission and one for reception This unit is functionally compatible with the NS16550 except for the additional clock control logic to permit the 16650 core clock source to be stopped Figure 19 1 SIU1 Block Diagram Vg4181 TxD1 UART1 clock RxD1 RTS1 DCD1 DTR1 Activity Timer 1 seclk_siu clk32k Caution clock is supplied to the SIU1 in the initial state When using the SIU1 set the MSKSIU18M bit of the CMUCLKMSK register in the MBA Host Bridge to 1 in advance so that the clock is supplied
301. he KIUSCANREP register When the ASTART bit is set to 1 keyboard scanning starts automatically following a key down interrupt request When the ASTOP bit is set to 1 keyboard scanning stops automatically after no valid keyboard data i e all SCANIN lines are high level has been read for the number of scan cycles specified by the STPREP 5 0 bits of the KIUSCANREP register 16 2 2 Manual keyboard scan mode Manual Scan mode Manual Scan mode is enabled through the MSTART and MSTOP bits of the KIUSCANREP register Software initiates a keyboard scan operation by setting the MSTART bit to 1 and terminates keyboard scanning by setting the MSTOP bit to 1 When software sets the MSTOP bit to 1 the KIU will complete the current scan operation before disabling the scan logic 16 2 3 Key press detection All SCANIN lines are sampled by the KIU on the rising edge of the 32 768 kHz clock When any SCANIN line is sampled as low during a period of time from a rising edge to a falling edge of the 32 768 kHz clock a key down interrupt request is generated If the ASTART bit of the KIUSCANREP register is set to 1 at this time the KIU begins scanning the keyboard 318 User s Manual U14272EJ3VOUM CHAPTER 16 KEYBOARD INTERFACE UNIT KIU 16 2 4 Scan operation Scan operations are controlled by the T1CNT 4 0 and 4 0 bits of the KIUWKS register and the WINTVL 9 0 bits of the KIUWKI register The following diagram illustrates the relationship
302. he Reset signal is deasserted synchronously with the rising edge of MasterOut and the Cold Reset is completed Upon reset the CPU core becomes bus master and drives the SysAD bus internal After Reset is deasserted the CPU core branches to the Reset exception vector and begins executing the reset exception code Figure 5 8 Cold Reset 720 MasterClockNete ColdReset Interna Reset Interna MasterOut Internal 77777777727 a Undefined 5 lt lt lt lt lt lt 5 4 AAAF Undefined Note MasterClock is the basic clock used in the CPU core Its frequency is one forth of TClock frequency 104 User s Manual U14272EJ3VOUM CHAPTER 5 INITIALIZATION INTERFACE 5 3 2 Soft Reset Caution Soft Reset is not supported in the current Vn4181 A Soft Reset initializes the CPU core without affecting the output clocks in other words a Soft Reset is a logical reset In a Soft Reset the CPU core retains as much state information as possible all state information except for the following is retained The TS bit of the Status register is cleared to O The SR ERL and BEV bits of the Status register are set to 1 The IP7 bit of the Cause register is cleared to O Any interrupts generated on the SysAD bus are cleared NMI is cleared The Config register is initialized A Soft Reset is started by assertion of the Reset signal and is completed at
303. he SIURB 1 register wait for the stop bit width time since the LSRO bit is set User s Manual U14272EJ3VOUM 373 CHAPTER 19 SERIAL INTERFACE UNIT 1 SIU1 LSR7 bit is valid only in FIFO mode and it indicates always 0 in 16450 mode The value of LSR4 bit becomes 1 when the spacing status 0 of receive data input is held longer than the time required for transmission of one word start bit data bits parity bit stop bit When in FIFO mode if a break is detected for one character in the FIFO the character is regarded as an error character and the CPU is notified of a break when that character reaches the highest position in the FIFO When a break occurs one zero character is sent to the FIFO When the RxD1 enters marking status and the next valid start bit is received the next character can be transmitted The value of LSR3 bit becomes 1 when a zero spacing level stop bit is detected following the final data bit or parity bit When in FIFO mode if a framing error is detected for one character in the FIFO the character is regarded as an error character and the CPU is notified of a framing error when that character reaches the highest position in the FIFO When a framing error occurs the SIU1 prepares for synchronization again The next start bit is assumed to be the cause of the framing error and the next data is not accepted until the next start bit has been sampled twice The value of LSR2 bit becomes 1 when a received character d
304. he Vr4111 or the 412177 the Vn4181 will wake up after RTC reset without these wake up events 1 4 Vn4110 CPU Core Figure 1 2 shows the internal block diagram of the Vn4110 CPU core In addition to the conventional high performance integer operation units this CPU core has the full associative format translation lookaside buffer TLB which has 32 entries that provide mapping to 2 page pairs odd and even for one entry Moreover it also includes instruction cache data cache and bus interface Figure 1 2 Vn4110 CPU Core Internal Block Diagram Virtual address bus Internalldata bus Bus Instruction Control o interface cache Control i 4 KB Address Data o Address Data i Clock generator Internal clock User s Manual U14272EJ3VOUM 35 CHAPTER 1 INTRODUCTION 1 CPU The CPU has hardware resources to process an integer instruction They are the 64 bit register file 64 bit integer data path and multiply and accumulate operation unit 2 Coprocessor 0 The CPO incorporates a memory management unit MMU and exception handling function MMU checks whether there is an access between different memory segments user supervisor and kernel by executing address translation The translation lookaside buffer TLB translates virtual addresses to physical addresses 3 Instruction cache The instruction cache employs direct mapping virtual index and physical tag Its ca
305. he peripheral unit reset and starts the Cold Reset sequence to activate the CPU core If the BATTINH signal is at low level the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown After the CPU core is restarted the BATTINH bit must be checked and cleared to 0 by software The DCDST bit in the PMUINTREG register does not indicate whether a DCD interrupt has occurred but instead reflects the current status of the DCD1 pin Cautions1 The PMU cannot recognize changes in the DCD1 signal while the POWER signal is asserted If the DCD1 state when the POWER signal is asserted is different from that when the POWER signal is deasserted the change in the DCD1 signal is detected only after the POWER signal is deasserted However if the DCD1 state when the POWER signal is asserted is the same as that when the POWER signal is deasserted any changes in the DCD1 signal that occur while the POWER signal is asserted are not detected 2 The changes in the DCD1 signal are ignored while the POWERON signal is active 3 There is no indicator which shows an activation via DCD interrupt if DCD1 signal has already changed from active to inactive during power on sequence In other words if software can not find activation factor and if the DCDST bit indicates that DCD1 signal is active the above situation occurred 198 User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU Figure 10 9 Activation
306. he program compatibility to other VR Series processors However since it has some differences from other processors on their architecture it cannot necessarily execute all programs that can be executed in other Vn Series processors and also other VR Series processors cannot necessarily execute all programs that can be executed in the VR4110 core Matters that should be paid attention to when porting programs between the 4110 core and other Vn Series processors are listed below A 16 bit length MIPS16 instruction set is added in the VR4110 core e Multiply add instructions MADD16 DMADD16 are added in the VR4110 core Instructions for power modes HIBERNATE STANDBY SUSPEND are added in the 4110 core to support power modes e The VR4110 core does not support floating point instructions since it has no Floating Point Unit FPU e The VR4110 core does have the LL bit to perform synchronization of multiprocessing Therefore it does not support instructions that manipulate the LL bit LL LLD SC SCD e The CPO hazards of the VR4110 core are equally or less stringent than those of the VR4000 For more information about each instruction refer to VR4100 Series Architecture User s Manual and user s manuals of each product other than the VR4100 Series Instructions supported by each of the VR Series processors are listed below Table 1 7 List of Instructions Supported by VR Series Processors Products 4181 Vn4121 Va4
307. her resets RTCRST Other resets Function 15 12 Reserved 0 is returned after read MUNDRN Mask of transmit FIFO underrun interrupt requests 0 Unmasked 1 Masked MTXBEND Mask of Transmit Burst End interrupt requests 0 Unmasked 1 Masked MTXFIFOE Mask of Transmit FIFO Empty interrupt requests 0 Unmasked 1 Masked MTXBUSY Mask of Transmit Shift Register Busy interrupt requests 0 Unmasked 1 Masked Reserved 0 is returned after read MOVRRN Mask of Receive FIFO Overrun interrupt requests 0 Unmasked 1 Masked MRXBEND Mask of Receive Burst End interrupt requests 0 Unmasked 1 Masked MRXFIFOF Mask of Receive FIFO Full interrupt requests 0 Unmasked 1 Masked MRXBUSY Mask of Receive Shift Register Busy interrupt requests 0 Unmasked 1 Masked 166 User s Manual U14272EJ3VOUM CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 8 3 6 CSIINTSTAT 0 0 00 090A Name Reserved Reserved Reserved Reserved TXBEINT TXFEINT R W RTCRST Other resets RTCRST Other resets Function 15 12 Reserved 0 is returned after read 11 URNINT Transmit FIFO Underrun interrupt request status 0 Not pending 1 Pending This bit is cleared by writing 1 TXBEINT Transmit Burst End interrupt request status 0 Not pending 1 Pending This bit is cleared by writing
308. hrough the FLMPOL bit In this diagram the first edge is a rising edge The two FLM edges are on the same row in this diagram but they need not be The active edge of the LOCLK is programmable through the LPPOL bit In this diagram the first edge is a rising edge the falling edge is the active edge The polarity of the SHCLK is programmable through the SCLKPOL bit In this diagram the first edge is a rising edge the falling edge is the active edge Figure 21 10 FLM Period FLM Output T10 The definitions of parameters shown in the figures are given in the table below Users Manual U14272EJ3VOUM 411 CHAPTER 21 LCD CONTROLLER 412 Table 21 3 LCD Controller Parameters Definition gclk period This parameter is not one of the timing parameters but all timing parameters is calculated based on this gclk is controlled by the Pre scal field Tg 1 frequency of gclk Shift clock high level width Color T1 Tg x HpckH 4 bit bus monochrome T1 Tg x HpckH HpckL Shift clock cycle Color T2 Tg x HpckH HpckL 4 bit bus monochrome T2 Tg x HpckH HpckL x 2 Panel data setup time Color T3 2 Tg x HpckH 4 bit bus monochrome Tg x HpckH HpckL Panel data hold time Color T4 Tg x HpckL 4 bit bus monochrome T4 Tg x HpckH HpckL Row cycle time T5 Tg x HpckH HpckL x Htot Load clock start time T6 Tg x HpckH HpckL x LCS Load clo
309. icates some of the information provided in the BadVAddr register but the information is arranged in a form that is more useful for a software TLB exception handler Figure 3 4 Context Register a 32 bit mode 31 25 24 4 PTEBase BadVPN2 63 b 64 bit mode 25 24 4 PTEBase BadVPN2 PTEBase The PTEBase field is a base address of the PTE entry table BadVPN2 This field holds the value VPN2 obtained by halving the virtual page number of the most recent virtual address for which translation failed 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read 3 0 9 3 0 por The PTEBase field is used by software as the pointer to the base address of the PTE table in the current user address space The 21 bit Bad VPNe field contains bits 31 to 11 of the virtual address that caused the TLB miss bit 10 is excluded because a single TLB entry maps to an even odd page pair For a 1 KB page size this format can directly address the pair table of 8 byte PTEs When the page size is 4 KB or more shifting or masking this value produces the correct PTE reference address User s Manual U14272EJ3VOUM 71 CHAPTER 3 REGISTERS 3 2 5 PageMask register 5 The PageMask register is a read write register used for reading from or writing to the it holds comparison mask that sets the page size for each TLB entry as shown in Table 3 3 Five page sizes can be selected between 1 KB and
310. ified 10 Instruction fetch Source The confirmation of the operating mode and TLB necessary for instruction fetch Examples 1 When changing the operating mode from User to Kernel and fetching instructions after the KSU EXL and ERL bits of the Status register are modified 2 When fetching instructions using the modified TLB entry after TLB modification 11 Instruction fetch exception Destination The completion of writing to registers containing information related to the exception when an exception occurs on instruction fetch 12 Interrupts Source The confirmation of registers judging the condition of occurrence of interrupt when an interrupt factor is detected 13 Loads sores Source The confirmation of the operating mode related to the address generation of Load Store instructions TLB entries the cache mode set in the KO bit of the Config register and the registers setting the condition of occurrence of a Watch exception Example When Loads Stores are executed in the kernel field after changing the mode from User to Kernel 14 Load store exception Destination The completion of writing to registers containing information related to the exception when an exception occurs on load or store operation 15 TLB shutdown Destination The completion of writing to the TS bit of the Status register when a TLB shutdown occurs 434 User s Manual U14272EJ3VOUM CHAPTER 23 COPROCESSOR 0 HAZARDS Table 23 2 indicates examples
311. igh impedance Input pin is ignored during Hibernate mode 1 Output pin remains actively driven Input pin is monitored during Hibernate mode Note Holds the value before reset Remark In order to support wake up events on one of the GPIO 15 0 pins the associated GPHST bit must be set to 1 264 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 14 GPSICTL 0 0 00 031A Name LOOPBK1 Reserved 1 2 Reserved Reserved REGRXD1 REGCTS1 REGDSR1 REGDCD1 R W R W R W R W R W R W RTCRST Other resets LOOPBK2 REGCTS2 REGDSR2 RTCRST R W R W R W R W Other resets 15 LOOPBK1 Function Loopback enable for serial interface channel 1 When GPIO pins have not been allocated for the line status signals DSR1 and or CTS1 of the serial interface channel 1 this bit can be set to 1 to allow the serial interface line status output signals to be connected to the line status input signals as follows DTR1 output from serial interface drives the DSR1 input to serial interface RTS1 output from serial interface drives the CTS1 input to serial interface 14 to 12 Reserved 0 is returned when read 11 REGRXD1 RxD1 data When a GPIO pin has not been enabled to provide RxD1 the RxD1 input to the serial interface channel 1 is driven with the value of this bit 10 REGCTS1 CTS1 data When the LOOPBK1 bit is r
312. inate sampling period or the touch panel s release status After the touch panel status is detected the time period specified via PIUSIVLREG register elapses before the transition to the DataScan state If the PIU detects the release status within the specified time period a touch panel contact status change interrupt request occurs inside the PIU At this point the PIU enters the WaitPenTouch state if the PADATSTOP bit is active If the PADATSTOP bit is inactive it enters to the DataScan state after the specified time period has elapsed User s Manual U14272EJ3VOUM 279 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 3 Register Set The PIU registers are listed below Table 14 1 PIU Registers Physical address Register symbol Function 0 0 00 0122 PIUCNTREG PIU Control register 0 0 00 0124 0 0 00 0126 PIUINTREG PIUSIVLREG PIU Interrupt cause register PIU Data sampling interval register 0 0 00 0128 PIUSTBLREG PIU A D converter start delay register 0 0 00 012A PIUCMDREG PIU A D command register 0 0 00 0130 PIUASCNREG PIU A D port scan register 0x0B00 0132 PIUAMSKREG PIU A D scan mask register 0x0B00 013E PIUCIVLREG PIU data sampling period count register 0 0 00 02 0 PIUPBOOREG PIU page 0 buffer 0 register 0 0 00 02A2 PIUPBO1REG PIU page 0 buffer 1 register 0 0 00 02A4 PIUPBO2REG PIU page 0 buffer 2 register
313. internal 2 94 interrupt 172 interrupt control 171 interrupt 171 243 interval 285 286 326 INTMSKRBEQG inniti eit ette 332 INTREG Iu eEhssceshes MEA IRI 313 INTSTATREQG inei 331 aes 337 338 direction control GIU 238 WIDdOW teta eie Nee gt 351 IOADSHBnREG n 0 or 1 342 IOADSLBnREG 0 or 1 342 REG n de ER ebd 341 IOSHBnREG n 0 or 1 343 IOSLBnREG n O or 1 343 IRDA ueni apetece 32 395 396 IrDA interface signals eene 58 ISA Bridge oen eder t tle 137 ISABHGGOTL ne pU 138 ISABRGSTS eoa ee perdere 139 IT irent cocto ctis 337 K Key Dress imita eme ete 317 318 keyboard interface Signals 56 keyboard interface 317 KEYEN s E ai MM 267 um 317 KIU registers on nee eet e ege 321 KIUDATn n 0 to 7 322 ee heme 327 het e eee etes 184 KIUSGCANREP eruere eec Lic 323 5 e peste deeem etre enn 324 KIUW
314. ion of this pin differs depending on the operating status During RTC reset input This signal is used to set CPU core operation clock frequency During normal operation input output gt Serial channel 1 transmit data output or general purpose RTS1 GP1027 CLKSEL1 The function of this pin differs depending on the operating status lt During RTC reset input gt te This signal is used to set CPU core operation clock frequency During normal operation input output gt Serial channel 1 request to send output or general purpose CTS14 GPIO28 Serial channel 1 clear to send input or general purpose DCD14 GPIO29 Serial channel 1 data carrier detect input or general purpose DTR1 GPIO30 CLKSEL2 The function of this pin differs depending on the operating status lt During RTC reset input gt This signal is used to set CPU core operation clock frequency lt During normal operation input output gt Serial channel 1 data terminal ready output or general purpose DSR1 GPIO31 Serial channel 1 Data set ready input or general purpose Note CLKSEL 2 0 signals are used to set the frequency of the CPU core operation clock PClock These signals are sampled when the RTCRST signal goes high The relationship between the CLKSEL 2 0 pin settings and clock frequency is shown below CLKSEL 2 0 CPU core operation frequency PClock Reserved 98 1 MHz
315. is based on the TClock The refresh rate is obtained by following expression Refresh rate BRF 13 0 x TClock period For example to select a 15 6 us refresh rate with a 50 MHz TClock BRF 13 0 15600 ns 20 ns 0 30 Remarks 1 When the IORDY signal does not become high level though the DRAM refresh rate has elapsed during the external ISA memory or I O cycles a DRAM refresh cycle be lost 2 Refresh timing is generated from detecting match between values of the internal up counter and BCURFCNTREG register Therefore when the BCURFCNTREG register value is changed smaller than current value and if the internal counter value is larger than the new BCURFCNTREG register value the next CBR refresh timing is at next match after the counter rounds over Users Manual U14272EJ3VOUM 115 CHAPTER 6 BUS CONTROL 6 2 5 REVIDREG 0x0A00 0014 MJREV3 MJREV2 MJREV1 MJREVO Reserved Reserved Reserved Reserved R MNREV3 R MNREV2 R MNREV1 R MNREVO R R R R R R R R 15 to 12 RID 3 0 Processor revision ID Read Only 11108 MJREV 3 0 Major revision ID number Read only 7to4 Reserved 0 is returned when read 3 0 MNREV 3 0 Minor revision ID Read only This register is used to indicate the revision of the Vn4181 The relationship between the values and the revision of the VR4181 is as follows Vn4181 Revi
316. is shared with that of the keyboard interface unit To use this interface for CompactFlash control the KEYSEL bit of the KEYEN register in the GIU must be clear to 0 Also to use BUSY signal as an activation factor the CompactFlash interface must be enabled during Hibernate mode by writing 1 to the CFHIBEN bit of the KEYEN register 17 2 Register Set Summary This section provides details of the ECU registers Two of the ECU registers are located in the I O addressing space These registers as well as the Interrupt and Configuration registers are shown in the following table Physical address 0 0 00 08 0 Table 17 1 ECU Control Registers Register symbol ECUINDX Function Index register 1 space 0 0 00 08E1 ECUDATA Data register I O space 0 0 00 08 8 INTSTATREG Interrupt status register 0 0 00 08FA 0 0 00 08FE INTMSKREG CFG REG 1 Interrupt mask register Configuration register 1 The remaining ECU registers listed below are all 8 bit width and accessed through the Index register and the Data register 328 User s Manual U14272EJ3VOUM CHAPTER 17 COMPACTFLASH CONTROLLER 0x0000 Table 17 2 ECU Registers 1 2 Register symbol ID REV REG Function Identification and revision register 0x0001 IF STAT REG Interface status register 0x0002 PWRRSETDRV Power and RESETDRYV control register 0x0003 ITGENCT
317. ister to 1 to stop supplying TClock to the memory controller 10 Set the DRAM EN bit in the DRAMHIBCTL register to 1 so that the DRAM interface signals are latched 11 Execute a SUSPEND instruction Caution When entering Suspend mode set the BEV bit of the Status register in the CPO of the CPU core to 1 to make sure that the vector of the exception handler points the ROM area User s Manual U14272EJ3VOUM 205 CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 6 6 Entering Suspend mode SDRAM 1 2 lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt gt lt 8 gt lt 9 gt Stop operations of the DMA controller and LCD controller Set registers in the ICU and to allow notification of the interrupt requests used as wake up events to Fullspeed mode to the CPU core Copy the codes for the Suspend mode lt 4 gt through 12 below beginning at a 16 byte boundary into the cache by using a Fill operation of CACHE instruction and jump to the cached codes Stop all peripheral clocks by writing zero to the CMUCLKMSK register in the MBA Host Bridge Set the BCURFCNTREG register in the MBA Host Bridge to a value that determines refresh interval to maximum to prevent an interruption of a Suspend mode sequence If burst refreshes are needed set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge Then execute CBR auto refresh cycles for a specific ti
318. it time after RTC reset Therefore the 343 75 ms wait time is always inserted as an activation wait time when the CPU core is activated immediately after RTC reset The activation wait time can be changed by setting this register for the CPU core activation from the Hibernate mode When this register is set to 0x0 0x1 0x2 0x3 or 0x4 the operation is not guaranteed Software must set the value of this register to greater than 0x4 to assure reliable operation User s Manual U14272EJ3VOUM 213 CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 7 4 PMUDIVREG 0 0 00 00AC Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Reserved Function 0 is returned when read DIV 2 0 Note Holds the value before reset Divide mode 111 101 011 001 RFU 110 RFU 100 DIV3 mode 010 DIV1 mode 000 RFU RFU DIV2 mode Default mode DIV2 This register is used to set CPU core s Div mode The Div mode setting determines the division rate of the TClock in relation to the pipeline clock PClock frequency Since the contents of this register are cleared to 0 during an RTC reset the Div mode setting always DIV2 mode just after RTC reset Though the Div mode has been set via this register the setting does not become effective immediately in the processor s operation
319. ith the rising edge of SCK 3 When CKMD bit 1 and CKPOL bit 0 e Transmission The first transmit data bit is output synchronized with the first rising edge of SCK The second transmit data bit and those that follow are output synchronized with the rising edge of SCK Therefore the external master must sample the data synchronizing with the falling edge of SCK e Reception 4181 samples receive data synchronizing with the falling edge of SCK Therefore the external master must output data synchronizing with the rising edge of SCK 4 When CKMD bit 1 and CKPOL bit 1 e Transmission The first transmit data bit is output synchronized with the first falling edge of SCK The second transmit data bit and those that follow are output synchronized with the falling edge of SCK Therefore the external master must sample the data synchronizing with the rising edge of SCK e Reception The Vn4181 samples receive data synchronizing with the rising edge of SCK Therefore the external master must output data synchronizing with the falling edge of SCK 158 User s Manual U14272EJ3VOUM CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 8 2 3 CSI transfer types 1 Burst mode Burst mode is supported for both transmit and receive transfers Burst lengths for transmission and reception are independently programmable and can be set from 1 to 65535 bits The transmit and receive shift registers are both 8 bit lengths During burst mode when
320. k cycle Cycle interrupts can be occurred for up to every 512 seconds The RTC unit of the Vn4181 includes two RTCLong timers e ElapsedTime This is a 48 bit up counter that counts up by 32 768 kHz clock cycle It counts up to 272 years before returning to zero It includes 48 bit comparator ECMPLREG ECMPMREG and ECMPHREG and 48 bit alarm time register ETIMELREG ETIMEMREG and ETIMEHREG to enable interrupts to occur at specified times 11 2 Register Set The RTC registers are listed below Table 11 1 RTC Registers Physical address Register symbol Function 0x0B00 00 0 ETIMELREG ElapsedTime L register 0 0 00 00C2 ETIMEMREG ElapsedTime M register 0 0 00 00C4 ETIMEHREG ElapsedTime H register 0x0B00 00 8 ECMPLREG ElapsedTime compare L register 0x0B00 00CA ECMPMREG ElapsedTime compare M register 0 0 00 00CC ECMPHREG ElapsedTime compare H register 0x0B00 0000 RTCL1LREG RTCLong1 L register 0x0B00 0002 RTCL1HREG RTCLong1 register 0 0004 RTCL1CNTLREG RTCLong1 count L register 0x0B00 0006 RTCL1CNTHREG RTCLong1 count register 0x0B00 0008 RTCL2LREG RTCLong 2 L register 0 0 00 00DA RTCL2HREG RTCLong2 register 0 0 00 00DC RTCL2CNTLREG RTCLong 2 count L register 0 0 00 00DE RTCL2CNTHREG RTCLong 2 count register 0x0B00 01DE RTCINTREG Each register is
321. lank Figure 21 2 View Rectangle and Horizontal Vertical Blank Hvisible 1 0 View rectangle LCD panel Horizontal blank Hvisible 1 Vvisible 1 0 Vvisible 1 Vertical blank Htotal 1 Vtotal 1 Each parameter is defined using bit values in the LCD controller registers as follows Vtotal Vtot 8 0 VRTOTALREG 0x0A00 0408 Vvisible Vact 8 0 VRVISIBREG 0x0A00 040A Htotal Htot 7 0 x 2 HRTOTALREG 0x0A00 0400 e Hvisble Hact 5 0 x 8 HRVISIBREG 0 0 00 0402 Caution The following expressions must be satisfied 1 Vtotal gt Vvisible 2 Htotal gt Hvisible 6 402 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 2 Load clock The edge positions of the load clock LOCLK are programmable Each row in the rectangle specified with 0 0 and Htotal 1 Vvisible 1 must have two LOCLK edges The remaining rows in the frame rectangle form the vertical blank These rows also have two LOCLK edges if the DummyL bit of the VRVISIBREG register is 1 or none if DummyL bit is 0 The first LOCLK edge is defined by the LCS 7 0 bits of the LDCLKSTREG register The second edge is defined by the LCE 7 0 bits of the LDCLKENDREG register and is usually inside the horizontal blank The LPPOL bit of the LCDCTRLREG register controls the directions of toggles If the LPPOL bit is 0 the first LOCLK edge is positive and the second is negative If the LPPOL bi
322. lock PCLK frequency is 25 MHz the DAVREF 15 0 bits should be set to as follows DAVREF 15 0 5 x 10 25 x 10 0 0070 User s Manual U14272EJ3VOUM 305 CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 4 SODATREG 0 0 00 0166 Name Reserved Reserved Reserved Reserved Reserved Reserved SODAT9 SODAT8 R W RTCRST Other resets Name SODAT7 SODAT6 SODAT5 SODAT4 SODAT3 SODAT2 SODAT1 SODATO R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 15 to 10 Reserved 0 is returned when read 9to0 SODAT 9 0 Speaker output data This register is used to store 10 bit DMA data for speaker output Data is received from the SDMADATREG register and is sent to the D A converter Write is used for debugging and is enabled when the AIUSEN bit of the SEQREG register is set to 1 This register is initialized 0x0200 by resetting the AIUSEN bit of the SEQREG register to 0 306 User s Manual U14272EJ3VOUM CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 5 SCNTREG 0 0 00 0168 Name DAENAIU Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets DAENAIU Function Enables D A converter operation Vref connection 1 ON 0 OFF Reserved 0 is returned when read SSTATE Indicates speaker operation state 1 Operating 0 Stop
323. lor LCD panel interface is enabled by writing to the GPIO Mode registers and utilizes the following GPIO pins Table 13 8 STN Color LCD Interface Signals 2 External LCD controller pin mapping An interface to an external LCD controller can be configured by setting the LCDGPEN bit of the LCDGPMODE register to 1 In this mode the following internal LCD controller pins are redefined to support the external LCD controller interface Table 13 9 External LCD Controller Interface Signals External LCD controller interface signal SHCLK LCDCS Output LOCLK MEMCS16 Input VPLCD General purpose output VPGPIO1 Output VPBIAS General purpose output VPGPIOO Output The LCDCS output is generated by the address decode logic in the GIU The address range be specified by programming the LCDGPMODE register The following address ranges are supported 1 0x1338 0000 to 0x133F FFFF 512KB 2 0x133C 0000 to 0x133F FFFF 256KB 3 Ox133E 0000 to 0x133F FFFF 128KB 4 0x130A 0000 to 0x130A FFFF 64KB the address space of the PC AT is assumed ppm Remark All memory cycles that access the external LCD controller address space are treated as 16 bit cycles The MEMCS16 input is provided to support external memory devices besides the external LCD controller which need accesses 16 bit cycles During an external memory cycle if the MEMCS16 input is enabled and asserted the ISA bridge will generate a 16 bit c
324. mask PIU register 0 0 00 0090 MAIUINTREG Level 2 mask AIU register 0 0 00 0092 R W MKIUINTREG Level 2 mask KIU register Users Manual U14272EJ3VOUM 173 CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 1 SYSINT1REG 0 0 00 0080 Name Reserved Reserved DOZEPIU SOFTINTR INTR Reserved Reserved SIUINTR 1 2 GIUINTR R W RTCRST Other resets ETIMER INTR RTCRST Other resets Function 15 14 Reserved 0 is returned when read 13 DOZEPIUINTR PIU interrupt request during Suspend mode 0 Not occurred 1 Occurred 12 Reserved 0 is returned when read 11 SOFTINTR Software interrupt request 0 Not occurred 1 Occurred 10 Reserved 0 is returned when read 9 SIUINTR SIU interrupt request 0 Not occurred 1 Occurred 8 GIUINTR GIU interrupt request 0 Not occurred 1 Occurred 7 KIUINTR KIU interrupt request 0 Not occurred 1 Occurred 6 AIUINTR AIU interrupt request 0 Not occurred 1 Occurred 174 User s Manual U14272EJ3VOUM CHAPTER 9 INTERRUPT CONTROL UNIT ICU PIUINTR PIU interrupt request 0 Not occurred 1 Occurred Function 2 2 Reserved 0 is returned when read ETIMERINTR ElapsedTime interrupt request 0 Not occurred 1 Occurred RTCL1INTR RTCLong1 interrupt request 0 Not occurred 1 Occurred POWERINTR Power switch interrupt request 0
325. me Reserved Reserved R W RTCRST Other resets Function 7 6 FCR 7 6 Receive FIFO trigger level 11 14 bytes 10 8 bytes 01 4 bytes 00 O bytes 5 4 Reserved 0 is returned when read 3 FCR3 Switch between 16450 mode and FIFO mode 1 From 16450 mode to FIFO mode 0 From FIFO mode to 16450 mode 2 FCR2 Transmit FIFO and its counter clear Cleared to 0 when 1 is written 1 FIFO and its counter clear 0 Normal 1 FCR1 Receive FIFO and its counter clear Cleared to 0 when 1 is written 1 FIFO and its counter clear 0 Normal 0 FCRO Receive Transmit FIFO enable Cleared to 0 when 1 is written 1 Enable 0 Disable This register is used to control the FIFOs 368 User s Manual U14272EJ3VOUM CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 FIFO interrupt modes When receive FIFO is enabled and receive interrupt requests are enabled receive interrupts can occur as described below 1 When the FIFO is reached to the specified trigger level a receive data ready interrupt request is notified to the CPU This interrupt is cleared when the FIFO goes below the trigger level When the FIFO is reached to the specified trigger level the SIUIID 1 register indicates a receive data ready interrupt request Same as the interrupt above the SUIID 1 register is cleared when the FIFO goes below the trigger level The receive line status interrupt is assigned to a higher
326. me Reserved Reserved RxDMSK RTSMSK DCDMSK DTRMSK Reserved TxWRMSK R W R R R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Reserved Function 0 is returned when read RxDMSK Mask for notification of change on RxD1 1 Mask 0 Unmask RTSMSK Mask for notification of change on RTS1 1 Mask 0 Unmask DCDMSK Mask for notification of change on DCD1 1 Mask 0 Unmask DTRMSK Mask for notification of change on DTR1 1 Mask 0 Unmask Reserved Write 0 when write 0 is returned when read TxWRMSK Mask for notification of transmit buffer write 1 Mask 0 Unmask This register is used to set masks for notification of operation statuses to the Activity Timer of the SIU1 When 1 is set in this register state transition of the corresponding signals or write to transmit buffer is not notified to the Activity Timer User s Manual U14272EJ3VOUM 377 CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 15 SIUACTTMR 1 0 0 00 001E Name SIUTMO7 SIUTMO6 SIUTMO5 SIUTMO4 SIUTMO3 SIUTMO2 SIUTMO1 SIUTMOO R W RTCRST Other resets Function SIUTMO 7 0 SIU activity timeout period 11111111 255 x 30 5 11111110 254 x 30 5 us 01111111 127 x 30 5 us 00000001 30 5 us 00000000 Activity Timer disabled 378 User s Manual U14272EJ3VOUM CHAPTER 20 SERIAL INTERFACE UNIT 2 5102
327. me period i e OXGFFF x TClock period burst refresh interval required by DRAM Clear the BstRefr bit of the MEMCFG REG register in the memory controller to O to disable a burst refresh Then set SUSPEND bit in the DRAMHIBCTL register to 1 to put the DRAM into self refresh mode Poll the OK STOP CLK bit in the DRAMHIBCTL register to confirm that the memory controller puts the DRAM into self refresh mode Set the STOP CLK bit in the DRAMHIBCTL register to 1 to stop supplying TClock to the memory controller 10 Set the DRAM EN bit in the DRAMHIBCTL register to 1 so that the DRAM interface signals are latched 11 Clear the SUSPEND bit in the DRAMHIBCTL register to 0 after waiting for about 2 us 12 Execute a SUSPEND instruction Caution When entering Suspend mode set the BEV bit of the Status register in the CPO of the CPU core 206 to 1 to make sure that the vector of the exception handler points the ROM area User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 6 7 Exiting Suspend mode EDO DRAM 1 2 3 4 5 6 lt 7 gt lt 8 gt Generate a wake up event from Suspend mode such as a transition on the POWER DCD interrupt etc Software execution resumes at the General exception vector OXOBFC 0380 when BEV 1 Copy the codes for the restore 4 through 8 below beginning at a 16 byte boundary into the cache by using a Fill operation of
328. mmable chip select or the LOCLK MEMCS16 pin When one of the programmable chip selects has been defined as memory mapped and 16 bit data width the gpmemcs16 output is asserted while the memory cycle address is within the range specified for the programmable chip select When the LOCLK MEMCS16 pin has been configured as MEMCS16 the gpmemcs16 1 output follows the state of the MEMCS16 signal 13 2 6 General purpose input output Each one of the 32 GPIO pins can be defined as a general purpose input or a general purpose output When a pin is configured as a general purpose output a corresponding value written to the GPDATLREG register or the GPDATHREG register appears on the GPIO pin When a pin is configured as a general purpose input a value driven on the GPIO pin can be read from its corresponding data bit of the GPDATLREG or GPDATHREG register 242 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 2 7 Interrupt requests and wake up events Each of the lower sixteen GPIO pins GPIO 15 0 can be defined as an interrupt request input The GIU provides a single asynchronous interrupt request output to the MBA Host Bridge GPIOINTR The MBA Host Bridge is responsible for synchronizing this interrupt request with the MasterOut clock internal The GIU provides a total of five registers to support GPIO interrupt requests The interrupt enable register GPINTEN is used to enable interrupt requests on a particular GPI
329. mory space ISA memory 0 1000 0000 OxOFFF FFFF OxODOO 0000 OxOCFF FFFF Internal ISA I O space 1 0x0C00 0000 OxOBFF FFFF Internal ISA I O space 2 0 0 00 0000 OxOAFF FFFF MBA bus space 0 0 00 0000 OxO9FF FFFF 0 0400 0000 OxO3FF FFFF DRAM space 0 0000 0000 92 User s Manual U14272EJ3VOUM CHAPTER 4 MEMORY MANAGEMENT SYSTEM Table 4 1 VR4181 Physical Address Space Physical address OxFFFF FFFF to 0x2000 0000 Mirror image of Ox1FFF FFFF to 0x0000 0000 Capacity bytes Ox1FFF FFFF to 0x1800 0000 ROM space 0x17FF FFFF to 0x1400 0000 External system bus I O space ISA 1 0 0x13FF FFFF to 0x1000 0000 External system bus memory space ISA memory OxOFFF FFFF to 0 0000 0000 Space reserved for future use OxOCFF FFFF to 0x0C00 0000 Internal ISA I O space 1 OxOBFF FFFF to 0 0 00 0000 Internal ISA I O space 2 OxOAFF FFFF to 0x0A00 0000 MBA bus I O space OxO9FF FFFF to 0x0400 0000 Space reserved for future use OxOSFF FFFF to 0x0000 0000 4 2 1 ROM space DRAM SDRAM space The ROM space mapping differs depending on the capacity of the ROM being used The ROM capacity is set via the ROMs 1 0 bits in the BCUCNTREG1 register The physical addresses of the ROM space are listed below Table 4 2 ROM Address Map Physical address Ox1FFF FFFF to Ox1FCO 0000 When using 32 Mbit ROM Bank 3 ROMC
330. n l HL TPX1 L TPYO samp Y DataScan LH l TPX1 H TPXO L TPYO samp Y DataScan HL l Note states of pins are not guaranteed if the PADSTATE 2 0 immediately before the CPU s SUSPEND or HIBERNATE instruction execution is in a state other then the Disable state Remarks Low level input 1 High level input L Low level output H High level output A D converter input D Touch interrupt request input with a pull down resistor d No touch interrupt request input with a pull down resistor Dont care User s Manual U14272EJ3VOUM 297 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 6 Timing 14 6 1 Touch release detection timing Touch release detection is not determined via the A D converter but the voltage level of the TPY1 pin The following figure shows a timing of touch release detection and coordinate detection Figure 14 6 Touch Release Detection Timing State Standby WaitPenTouch DataScan Interval TPY 1 0 TPX 1 0 Touch detected V V v V V Note PADSCANTYPE 0 Touch detected X x X x X Y X Y detected BERT rrea K Ke kore PADSCANTYPE 1 Touch detected Release detected Note Determined according to the status of the TPY1 signal as follows High level touched Low level released 14 6 2 A D port scan timing During an A D port scan the four ports of A D converter s input channel are sequentially scann
331. nal EDO DRAM Configuration ssssssessseseseeeeneenenennneen nennen nenne nneee nere nnrnn 128 SDRAM Configuration 7 bis diete teri po oec oe ae eee edo oet toii to De tte f betae ee 130 SCKand SISO Relationship eret eee eo ualde Li ioca o aue tae edid 157 Outline of Interrupt Control 1 eren oett 172 Transition of 84181 Mode ner Re ERR 189 EDO DRAM Signals on RSTSW Reset SDRAM Bit 0 sese 192 Activation via Power Switch Interrupt Request BATTINH 195 Activation via Power Switch Interrupt Request BATTINH L 195 Activation via CompactFlash Interrupt Request BATTINH 196 Activation via CompactFlash Interrupt Request BATTINH 196 Activation via GPIO Activation Interrupt Request BATTINH 197 Activation via GPIO Activation Interrupt Request BATTINH 1 197 Activation via DCD Interrupt Request BATTINH 199 Activation via DCD Interrupt Request BATTINH L 2 199 Activation via ElapsedTime Interrupt Request 200 Activation via ElapsedTime Interrupt Request BATTINH 1 en 200 GPIO 15 0 Interrupt Request Detecting Logic sseeneeeneeeneneneennnenneen nennen 243 User s Manual U14272EJ3VOUM 25 Fig 14 1
332. nce causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function VR10000 Vn12000 Vn4000 VR4000 Series Vn4100 Vn4100 Series Vn4110 Vn4111 Vn4121 Vn4122 VR4181 Vn4300 Vn4305 Vn4310 Vn4400 VR5000A 5432 and Vn Series are trademarks of NEC Electronics Corporation MIPS is a registered trademark of MIPS Technologies Inc in the United States MBA is a trademark of Vadem Corporation Pentium Intel and StrataFlash are trademarks of Intel Corporation DEC VAX is a trademark of Digital Equipment Corporation
333. ncer s state Interval Disable ADPScan Disable CMDScan Disable PIUPWR PIUSEQEN Standby Standby PADATSTART PADATSTOP PADSCANSTART PADSCANSTOP Note4 Standby ted Standby Note4 Standby Notes 1 After 1 is written the bit is automatically cleared to 0 four TClock cycles later 2 State transition occurs during touch status 3 State transition occurs when the PIUSEQEN bit is set to 1 4 State transition occurs after one set of data is sampled The PADSCANSTOP bit is cleared to 0 after the state transition occurs Remark The bit change is retained but there is no state transition x Setting prohibited operation not guaranteed Combination of state and bit status before setting does not exist User s Manual U14272EJ3VOUM 283 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 3 2 PIUINTREG 0 0 00 0124 Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Name Reserved PADCMD PADADP PADPAGE1 PADPAGEO PADDLOST Reserved PENCHG INTR INTR INTR INTR INTR INTR R W R R W R W R W R W R W R R W RTCRST 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Function Valid page ID bit older valid page 1 Page 1 retains an older valid data 0 Page O retains an
334. ncorporates instruction and data caches which are independent of each other This configuration enables high performance pipeline operations Both caches have a 64 bit data bus enabling a one clock access These buses be accessed in parallel The instruction cache of the Vn4181 has a storage capacity of 4 KB while the data cache has a capacity of 4 KB For details about caches refer to 4100 Series Architecture User s Manual 1 4 8 Instruction pipeline The Vr4181 has a 5 stage instruction pipeline Under normal circumstances one instruction is issued each cycle For details refer to 4100 Series Architecture User s Manual 44 User s Manual U14272EJ3VOUM CHAPTER 1 INTRODUCTION 1 4 9 Power modes The Vn4181 supports four power modes Fullspeed mode Standby mode Suspend mode and Hibernate mode A detailed description of these power modes is also given in CHAPTER 10 POWER MANAGEMENT UNIT PMU 1 Fullspeed mode This is the normal operation mode The Vn4181 s default status sets operation under Fullspeed mode After a reset the Vn4181 returns to Fullspeed mode 2 Standby mode When a STANDBY instruction has been executed the processor can be set to Standby mode During Standby mode the pipeline clock PClock in the CPU core is held at high level The peripheral units all operate as they do during Fullspeed mode This means that DMA operations are enabled during Standby mode During Standby mode the processor
335. nd no writes have occurred to the transmit buffer within the programmed time out period specified in the Activity Timer block the UART2 clock is stopped The UART2 clock will remain stopped until the activity is detected on the monitored sources User s Manual U14272EJ3VOUM 379 CHAPTER 20 SERIAL INTERFACE UNIT 2 512 20 3 Register Set The SIU2 registers are listed below Table 20 1 SIU2 Registers Physical address Register symbol Function 0 0 00 0000 SIURB 2 Receive buffer register read SIUTH 2 Transmit holding register write SIUDLL 2 Divisor latch least significant byte register 0 0 00 0001 SIUIE 2 Interrupt enable register SIUDLM 2 Divisor latch most significant byte register 0 0 00 0002 SIUIID 2 Interrupt identification register read SIUFC 2 FIFO control register write 0x0C00 0003 SIULC 2 Line control register 0 0 00 0004 SIUMC 2 Modem control register 0 0 00 0005 SIULS 2 Line status register 0 0 00 0006 SIUMS 2 Modem status register 0 0 00 0007 SIUSC 2 Scratch register 0 0 00 0008 SIUIRSEL 2 SIU IrDA select register 0 0 00 0009 SIURESET 2 SIU reset register 0x0C00 000A SIUCSEL 2 SIU echo back control register 0 0 00 000C SIUACTMSK 2 SIU activity mask register 0 0 00 000E SIUADTTMR 2 SIU Activity Timer register Remark LCR7 is bit 7 of the SIULC 2 register 380 User s Manual U14272EJ3VOUM CHAPTER 20 SERI
336. nd the previous character is lost When in FIFO mode if the data continues to be transferred to the FIFO though it exceeds the trigger level even after the FIFO becomes full an overrun error will not occur until all characters are stored in the shift register The CPU is notified as soon as an overrun error occurs The characters in the shift register are overwritten and are not transferred to the FIFO User s Manual U14272EJ3VOUM 393 CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 20 3 11 SIUMS 2 0 0 00 0006 Name R W RTCRST Undefined Undefined Undefined Undefined Other resets Undefined Undefined Undefined Undefined Function 7 MSR7 DCD2 signal status 1 Low level 0 High level 6 MSR6 RI signal internal status 1 Low level 0 High level 5 MSR5 DSR2 input status 1 Low level 0 High level 4 MSR4 CTS2z input status 1 Low level 0 High level 3 MSR3 DCD2 signal change 1 Changed 0 No change 2 MSR2 RI signal internal change 1 Changed 0 No change 1 MSR1 DSR2 signal change 1 Changed 0 No change 0 MSRO CTS2 signal change 1 Changed 0 No change This register indicates the current status and change in status of various control signals that are input to the CPU from a modem or other peripheral device The MSR 3 0 bits are cleared to 0 if they are read when they are set to 1 394 User s Manual U14272EJ3VOUM CHAPTER 20 SERIAL INTERFACE UNIT 2 5102
337. next scan operation 1111111111 30690 us WINTVL 9 0 x 30 us 0000000001 30 us 0000000000 No wait 326 User s Manual U14272EJ3VOUM CHAPTER 16 KEYBOARD INTERFACE UNIT KIU 16 3 6 KIUINT 0 0 00 0198 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets Reserved Reserved Reserved Reserved Reserved KDATLOST KDATRDY KEYDOWN RTCRST Other resets Reserved Function 0 is returned when read KDATLOST Key data lost interrupt request This interrupt request occurs if the KIUDATO register is updated with the next key data prior to being read by the CPU core 1 Occurred 0 Not occurred This bit is cleared by writing 1 KDATRDY Key data ready interrupt request This interrupt request occurs when a set of scanning is completed and all the KIUDAT registers are updated 1 Occurred 0 Not occurred This bit is cleared by writing 1 KEYDOWN Key down interrupt request This interrupt request occurs when the KIU sequencer is idle and any of the SCANIN inputs has been sampled as low level 1 Occurred 0 Not occurred This bit is cleared by writing 1 User s Manual U14272EJ3VOUM 327 17 1 General CHAPTER 17 COMPACTFLASH CONTROLLER ECU The 4181 provides an ExCA compatible controller ECU supporting a single CompactFlash slot The interface for this controller
338. ng Status indication 13 Cause Exception processing Cause of last exception 14 EPC Exception processing Exception Program Counter 15 PRId Memory management Processor revision identifier 16 Config Memory management Configuration memory system modes specification 17 LLAddr Memory management Physical address for self diagnostics 18 WatchLo Exception processing Memory reference trap address low bits 19 WatchHi Exception processing Memory reference trap address high bits 20 XContext Exception processing Pointer to kernel virtual PTE in 64 bit mode 21 to 25 Reserved for future use 26 Note2 Parity Error Exception processing Cache parity bits 27 Note2 Cache Error Exception processing Index and status of cache error 28 TagLo Memory management Lower half of cache tag 29 TagHi Memory management Higher half of cache tag 30 ErrorEPC Exception processing Error Exception Program Counter 31 Reserved for future use Notes1 This register is defined to maintain compatibility with the VR4000 and 4400 This register is meaningless during normal operations 2 This register is defined to maintain compatibility with the VRA100 This register is not used in the Vn4181 hardware 68 User s Manual U14272EJ3VOUM CHAPTER 3 REGISTERS 3 2 Det
339. ng Then the states of the MIPS16EN and CLKSEL 2 0 pins are read after one RTC cycle Next the Vn4181 asserts the POWERON and checks the state of the BATTINH BATTINT signal If it is at high level the VRA181 asserts the MPOWER pin and activates the external agent s DC DC converter After the stabilization time period about 350 ms of the DC DC converter the 4181 begins PLL oscillation and starts all clocks a period of about 16 ms following the start of PLL oscillation is required for stabilization of PLL oscillation An RTC reset does not save any of the status information and it completely initializes the processor s internal state Since the DRAM is not switched to self refresh mode the contents of DRAM after an RTC reset are not at all guaranteed After a reset the processor becomes the system bus master which executes a Cold Reset exception sequence and begins to access the reset exception vectors in the ROM space Since only part of the internal status is reset when a reset occurs in the Vn4181 the processor should be completely initialized by software see 5 4 Notes on Initialization After power on the processor s pin statuses are undefined since the RTCRST is asserted until the 32 768 kHz clock oscillator starts oscillation The pin statuses after oscillation starts are described in CHAPTER 2 PIN FUNCTIONS in this document Figure 5 1 RTC Reset SO RTCRST Input POWER Input R e POW
340. nnel EOP interrupt mask 0 Disable 1 Enable Reserved 0 is returned after a read Reserved Write 0 when write 0 is returned after a read Reserved 0 is returned after a read User s Manual U14272EJ3VOUM 155 CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 8 1 Overview The CSI manages communication via a synchronous serial bus The CSI of the 4181 has the following key characteristics Slave only synchronous serial interface e Able to transmit and receive data simultaneously Supports fixed 8 bit character length Supports burst lengths of 1 to 65535 bits Continuous transfer mode for of peripherals supporting auto scan e Programmable clock phase and clock polarity The CSI interface shares pins with GPIO signals as follows When using the CSI set these pins to use as CSI signals in the registers of the GIU in advance GPIO Pin CSI Signal Definition GPIO10 Optional multifunction control input In one mode FRM determines data direction transmit or receive In the other mode FRM enables low level or inhibits high level transmissions Serial clock input Maximum frequency 1 6 MHz Serial data output Serial data input Caution clock is supplied to the CSI in the initial state When using the CSI set the MSKCSUPCLK bit of the CMUCLKMSK register in the MBA Host Bridge to 1 in advance so that a clock is supplied 8 2 Operation of CSI 8 2 1 Transmit recei
341. nsmit FIFO reaches to the empty level defined by TFIFOT bits 0 Transmit FIFO not empty 1 Transmit FIFO empty TXBUSY CSI transmit shift register status 0 Idle 1 Character transmission in progress RFIFOT 1 0 CSI receive FIFO threshold These bits select the level at which the receive FIFO full status is notified 00 1 or more words are valid in receive FIFO 01 2 or more words are valid in receive FIFO 10 4 or more words are valid in receive FIFO 11 Reserved 164 Reserved 0 is returned after read User s Manual U14272EJ3VOUM CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 2 2 Function FRMDIR FRM input pin status 0 Low level transmit direction 1 High level receive direction Reserved 0 is returned after read RXFIFOF CSI receive FIFO full status This bit is set to 1 when the receive FIFO reaches to the full level defined by RFIFOT bits 0 Receive FIFO not full 1 Receive FIFO full RXFIFOE CSI receive FIFO empty status This bit is set to 1 when the receive FIFO contains no valid data 0 Receive FIFO not empty 1 Receive FIFO empty RXBUSY CSI receive shift register status 0 Idle 1 Character reception in progress User s Manual U14272EJ3VOUM 165 CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 8 3 5 CSIINTMSK 0x0BOO 0908 Name Reserved Reserved Reserved Reserved MTXBEND MTXFIFOE MTXBUSY R W RTCRST Ot
342. nternal Block Diagram 35 CPU Registers en ecc ae RELIER ide eerie Se EN eei ere ot 37 CPU Instruction Formats 32 Bit Length 38 CPU Instruction Formats 16 Bit Length 39 Byte Address in Little Endian Byte Order ssssssssssssseseeeeee nenne nnne nennen nnne nnne nnne 41 Unaligned Word Accessing Little 42 External Circuits of Clock Oscillator 5 3 3 eh e mi en UP Ter 48 Incorrect Connection Circuits of Resonator ssssssssseseeeeeeeeeneennneee nennen nennen nter nnns 49 Index Register te Re b ee t ae eot I c et dcus 69 Random Register Cr 69 EntryLoO and Entrylo1 Registers eee 70 Context Register e a etude a dece de e A Led d edes 71 PageMask Register iem rene rca ER aoa duc seio 72 Positions Indicated by the Wired Register 73 5 eia ae uetus 73 BadVA ddr Register E a ay tee aed 74 Count Register obe Ie dte e e deed Hee 74 75 Gompare Reglslet lt x EO E UA Eae iu 76 Statuis Register 2 0 04 deed ee HU eben hee
343. ntrol Caution clocks are supplied to the PIU A D converter and D A converter in the initial state When using the PIU set the MSKPIUPCLK MSKADUPCLK and MSKADU18M bits of the CMUCLKMSK register in the MBA Host Bridge to 1 in advance so that clocks are supplied Users Manual U14272EJ3VOUM 275 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 14 1 1 Block diagrams Figure 14 1 PIU Peripheral Block Diagram Vn4181 AUDIOIN Battery etc 5 ADIN2 I O 8 I p ADIN1 Buffer 8 ADINO Touch panel TPY1 TPYO Touch panel A set of four pins are located at the edges of the X axis and Y axis resistance layers and the two layers have high resistance when there is no pen contact and low resistance when there is a pen contact The resistance between the two edges of the resistance layers is about 1 When a voltage is applied to both edges of the Y axis resistance layer the voltage Vv1 and Vv2 in the figure below is measures at the X axis resistance layer s pins to determine the Y coordinate Similarly when a voltage is applied to both edges of the X axis resistance layer the voltage Vx1 and Vx the figure below is measures at the Y axis resistance layer s pins to determine the X coordinate For greater precision voltages are again measured after switching plus and minus of the voltage applied to the resistance layers pins The obtained data is stored into the PIUPBnmREG register n
344. nverter is used frequently the time from when both pages become full until when the data loss occurs may be shorter than that of the normal operation Response In this case valid data contained in the pages when the data lost interrupt request occurs is never overwritten After two pages of valid data are processed clear the three interrupt requests by writing 1 to the PADDLOSTINTR PADPAGE1INTR and PADPAGEOINTR bits in the PIUINTREG register After clearing these interrupt requests set the PADATSTART or PADSCANSTART bit of the PIUCNTREG register to restart the coordinate detection operation 4 When the next data transfer starts while there is valid data in the ADPScan buffer 300 Cause This condition is caused when valid data is not processed even while the ADPScan buffer holds valid data A D port scan interrupt request occurrence Response In this case valid data contained in the buffer when the data lost interrupt request occurs is never overwritten After valid data in the buffer is processed clear the two interrupt requests by writing 1 to the PADDLOSTINTR and PADADPINTR bits in the PIUINTREG register After clearing these interrupt requests set the ADPSSTART bit of the PIUASCNREG to restart the general purpose A D port scan operation User s Manual U14272EJ3VOUM CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 1 General The AIU controls the analog output speaker output processing of the internal D A converter and
345. o buffers for read Therefore an illegal data may be read if the timer value changes during a read operation When using the read value as a data be sure to read the registers twice and check that two read vales are the same 224 User s Manual U14272EJ3VOUM CHAPTER 11 REALTIME CLOCK UNIT 11 2 5 RTCLong registers 1 RTCL2LREG 0x0B00 0008 2 15 RTCL2P14 RTCL2P13 RTCL2P12 RTCL2P11 RTCL2P10 RTCL2P9 RTCL2P8 R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Name RTCL2P7 RTCL2P6 RTCL2P5 RTCL2P4 RTCL2P3 RTCL2P2 RTCL2P1 RTCL2PO R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 15100 RTCL2P 15 0 Note Holds the value before reset Bits 15 to 0 for RTCLong2 timer count cycle User s Manual U14272EJ3VOUM 225 CHAPTER 11 REALTIME CLOCK UNIT 2 RTCL2HREG 0x0B00 00DA Name Reserved Reserved R W RTCRST Other resets RTCL2P23 RTCL2P22 RTCL2P21 RTCL2P20 RTCL2P19 RTCL2P18 RTCL2P17 RTCL2P16 R W R W R W R W R W R W R W R W RTCRST Other resets Function Reserved 0 is returned when read RTCL2P 23 16 Bits 23 to 16 for RTCLong2 timer count cycle Note Holds the value before reset Use these registers
346. o types of CPU instructions 32 bit length instructions MIPS and 16 bit length instructions MIPS16 Use of the MIPS16 instructions is enabled or disabled by setting MIPS16EN pin during a reset For details about instruction formats and their fields in each instruction set and operation of each instruction refer to VR4100 Series Architecture User s Manual 1 MIPS III instructions All the CPU instructions are 32 bit length when executing MIPS III instructions and they are classified into three instruction formats as shown in Figure 1 4 immediate type jump J type and register type Figure 1 4 CPU Instruction Formats 32 Bit Length Instruction 31 26 25 21 20 16 15 ype Immediate op 5 N J type Jump op target 31 26 25 21 20 16 15 11 10 6 5 0 R type Register The instruction set can be further divided into the following five groupings a Load and store instructions move data between the memory and the general purpose registers They are all immediate l type instructions since the only addressing mode supported is base register plus 16 bit signed immediate offset b Computational instructions perform arithmetic logical shift and multiply and divide operations on values in registers They include R type in which both the operands and the result are stored in registers and l type in which one operand is a 16 bit signed immediate value fo
347. ode For details refer to CHAPTER 10 POWER MANAGEMENT UNIT PMU Figure 5 4 Software Shutdown ft m POWER Input POWERON Output M S M MPOWER Output N 5 pun ColdReset Internal gt So Reset Internal oo Stable oscillation TW eee PLL Internal Stopped j Undefined RTC Internal 32 768 kHz Stable oscillation P lt 4 gt 32 MS a gt 16 a Note1 16MasterClock ete2 Notes 1 Wait time for activation It can be changed by setting the PMUWAITREG register 2 MasterClock is the basic clock used in the CPU core Its frequency is one forth of TClock frequency 100 User s Manual U14272EJ3VOUM CHAPTER 5 INITIALIZATION INTERFACE 5 1 5 HALTimer shutdown After an RTC reset or RSTSW reset is canceled if the HALTimer is not canceled the HALTIMERRST bit of the PMUCNTREG register is not set by software within about four seconds the Vn4181 enters reset status Recovery from reset status occurs when the POWER pin is asserted or when a ElapsedTime interrupt request occurs A reset by HALTimer initializes the entire internal state except for the RTC timer the GIU and the PMU After a reset the processor becomes the system bus master which executes a Cold Reset exception sequence and begins to access the reset vectors in the ROM space Since only part of the internal status is reset when a reset occur
348. oes not satisfy the even or odd parity specified in the LCR4 bit When in FIFO mode if a parity error is detected for one character within the FIFO the character is regarded as an error character and the CPU is notified of a parity error when that character reaches the highest position in the FIFO The value of LSR1 bit becomes 1 when a character is transferred to the receive buffer register before reading by the CPU and the previous character is lost When in FIFO mode if the data continues to be transferred to the FIFO though it exceeds the trigger level even after the FIFO becomes full an overrun error will not occur until all characters are stored in the shift register The CPU is notified as soon as an overrun error occurs The characters in the shift register are overwritten and are not transferred to the FIFO 374 User s Manual U14272EJ3VOUM CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 11 SIUMS 1 0 0 00 0016 Name R W RTCRST Undefined Undefined Undefined Undefined Other resets Undefined MSR7 Undefined Undefined Undefined DCD1 signal status 1 Low level 0 High level Function MSR6 RI signal internal status 1 Low level 0 High level MSR5 DSR1 input status 1 Low level 0 High level MSR4 CTS1 input status 1 Low level 0 High level MSR3 DCD1 signal change 1 Changed 0 No change MSR2 RI signal inte
349. of calculation Table 23 2 Calculation Example of CPO Hazard and Number of Instructions Inserted Contending Number of Destination internal instructions Formula resource inserted TLBWR TLBWI TLBP TLB Entry 2 5 2 1 TLBWR TLBWI Load or store using newly modified TLB TLB Entry 1 5 3 1 TLBWR TLBWI Instruction fetch using newly modified TLB TLB Entry 2 5 2 1 MTCO Status CU Coprocessor instruction that requires the setting Status CU 2 5 2 1 of CU TLBR MFCO EntryHi EntryHi 1 5 8 1 MTCO EntryLoO TLBWR TLBWI EntryLoO 2 5 2 1 TLBP Index Index 2 6 8 1 MTCO EntryHi TLBP EntryHi 2 5 2 1 MTCO EPC ERET EPC 2 MTCO Status ERET Status 2 MTCO Status IE 4 Instruction that causes an interrupt Status IE Note The number of hazards is undefined if the instruction execution sequence is changed by exceptions In such a case the minimum number of hazards until the IE bit value is confirmed may be the same as the maximum number of hazards until an interrupt request occurs that is pending and enabled Remark Brackets indicate a bit name or a field name of registers User s Manual U14272EJ3VOUM 435 APPENDIX RESTRICTIONS Vn4181 A 1 RSTSW During HALTimer Operation The Vn4181 ignores the RSTSW signal even if it is asserted while the HALTimer is operating counting If the Vn4181 is started while the RSTSW signal is low the RSTSW reset sequence is n
350. of the next location in the FIFO The software must recover the data loss caused by the overrun or underrun error 8 3 CSI Registers The CSI provides the following registers Table 8 1 CSI Registers Physical address Register symbol Function 0 0 00 0900 CSIMODE CSI mode register 0 0 00 0902 CSIRXDATA CSI receive data register 0 0 00 0904 CSITXDATA CSI transmit data register 0 0 00 0906 CSILSTAT CSI line status register 0 0 00 0908 CSIINTMSK CSI interrupt mask register 0 0 00 090A CSIINTSTAT CSI interrupt status register 0 0 00 090C CSITXBLEN CSI transmit burst length register 0 0 00 090E CSIRXBLEN CSI receive burst length register 160 User s Manual U14272EJ3VOUM CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 8 3 1 CSIMODE 0 0 00 0900 Name Reserved R W RTCRST Other resets RTCRST Other resets Function CSI FRM enable 0 Disabled FRM signal input is ignored 1 Enabled Mode is set by FRMMD bit CSI transmit enable 0 Disable 1 Enable Remark When using the transmit function only communication must be performed with the RXEN bit 0 and the RXCLR bit 1 CSI transmit burst mode 0 Continuous mode 1 Burst mode CSI transmit buffer clear 0 Enable transmit shift register and FIFO 1 Reset transmit shift register and FIFO Reserved 0 is returned after read RXEN CSI receive
351. old Reset DMSRST 1 reset Caution When bit 6 of the PMUINTREG register is set to 1 only the CPU core is reset during a RSTSW reset cycle and all internal peripheral units retain their current state Software must re initialize or reset all peripheral units in this case To preserve SDRAM data during a RSTSW reset bit 6 of the PMUINTREG register should be set to 1 when SDRAM is used 10 3 1 RTC reset When the RTCRST signal becomes active the PMU resets all internal peripheral units including the RTC unit It also resets Cold Reset the CPU core In addition the RTCRST bit in the PMUINTREG register is set to 1 After the CPU core is restarted the RTCRST bit must be checked and cleared to 0 by software For details of the timing of RTC reset refer to CHAPTER 5 INITIALIZATION INTERFACE Users Manual U14272EJ3VOUM 191 CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 3 2 RSTSW reset When the RSTSW signal becomes active the PMU resets Cold Reset the CPU core When bit 6 of the PMUINTREG register is cleared to 0 the PMU also resets all internal peripheral units except for the RTC and GIU In addition the RSTSW bit in the PMUINTREG register is set to 1 After the CPU core is restarted the RSTSW bit must be checked and cleared to 0 by software For details of the timing of RSTSW reset refer to CHAPTER 5 INITIALIZATION INTERFACE 10 3 3 Deadman s Switch reset When the Deadman s Switch function is enabled soft
352. older valid data Reserved 0 is returned when read PADCMDINTR PIU command scan interrupt request This interrupt request occurs when a valid data is obtained during a command scan Cleared to 0 when 1 is written 1 Occurred 0 Not occurred PADADPINTR PIU A D port scan interrupt request This interrupt request occurs when a set of valid data is obtained during an A D port scan Cleared to 0 when 1 is written 1 Occurred 0 Not occurred PADPAGE1INTR PIU data buffer page 1 interrupt request This interrupt request occurs when a set of valid data is stored in the page 1 of the data buffer Cleared to 0 when 1 is written 1 Occurred 0 Not occurred PADPAGEOINTR PIU data buffer page 0 interrupt request This interrupt request occurs when a set of valid data is stored in the page 0 of the data buffer Cleared to 0 when 1 is written 1 Occurred 0 Not occurred PADDLOSTINTR Data lost interrupt request This interrupt request occurs when a set of data cannot be obtained during a specified time period Cleared to 0 when 1 is written 1 Occurred 0 Not occurred Reserved 0 is returned when read 284 PENCHGINTR Touch panel contact status change interrupt request Cleared to 0 when 1 is written 1 Occurred 0 Not occurred User s Manual U14272EJ3VOUM CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU This register sets and indicates the interrupt request generation of
353. ontrol for VPLCD pin When the LCDGPEN bit is set to 1 the VPLCD pin is driven by the value of this bit Note Holds the value before reset User s Manual U14272EJ3VOUM 273 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 24 MISCREGn 0 0 00 0330 to 0x0B00 034E Remark Name n 0to15 MISCREGO MISCREG1 MISCREG2 MISCREG3 MISCREG4 MISCREG5 MISCREG6 MISCREG7 pc ee ES EE MISCnD15 0 0 00 0330 0 0 00 0332 0 0 00 0334 0 0 00 0336 0 0 00 0338 0 0 00 033A 0x0B00 033C 0 0 00 033E MISCnD14 rere ae YS wa x mH MISCnD13 MISCREG8 0 0 00 0340 MISCREGS 0 0 00 0342 MISCREG10 0 0 00 0344 0 0 00 0346 MISCREG12 0 0 00 0348 0 0 00 034A MISCREG14 0 0 00 034C MISCREG15 0x0B00 034 MISCREG 1 1 MISCREG13 MISCnD12 MISCnD 1 1 re aS x mH MISCnD10 MISCnD9 MISCnD8 R W R W R W R W R W R W R W R W R W RTCRST Other resets Name MISCnD7 MISCnD6 MISCnD5 MISCnD4 MISCnD3 MISCnD2 MISCnD1 MISCnDO R W R W R W R W R W R W R W R W R W RTCRST 0 0 0 0 0 0 0 0 Other resets 15 to 0 MISCnD 15 0 Miscellaneous data Note Holds the value before reset Remark nz0Oto 15 These registers are battery backed and its contents are retained even in Hibernate mode 274 User s Manual U14272EJ3
354. open dose iro tu Adige ded 32 1 3 5 Interrupt controller ICU Loreto ter Led tete D 32 1 3 6 Realtime ClOCK oit ee ta Ere Mr ER ERE EROR GN neces HERR 32 1 3 7 Audio output D A converter 32 1 3 8 Touch panel interface and audio input A D converter 32 1 3 9 CompactFlash interface ECU 2 2224 0 0 enne nnne nnne nnne nnne rennen nnne 32 1 3 10 Serial interface channel 1 5 32 1 3 11 Serial interface channel 2 5102 22 000404000 32 1 3 12 Clocked serial interface 33 1 3 13 Keyboard interface KIU 22242424440 nnne tnn nnne nnne 33 1 38 14 General purpose irte op nU EUR t oo e ae Et uu ee 33 1 3 15 Programmable chip selects eese eterne nennen neni inne 34 13 16 LCD interface ripe ce D re Le rec e UY Cep eee cei D ee 34 1 39 17 Wake p events tiere Ei te be et d i peo DE de aate C ter Der fa e Fe Ege 35 1 4 VRATIO CPU Cm n 35 1 4 1 CPU r amp gistels e RUE di DR det dt Se ud eU ees 37 1 4 2 CPU instruction set overview 38 1 4 3 Data formats and addressing nennen nennen nenne 40 1 4 4 CPO registers x ue ru cene e rdiet Ee Ca die 43 14 5 Floating point unit
355. or Window 1 STARTA15 STARTA14 STARTA13 STARTA12 STARTA11 STARTA10 STARTA9 STARTA8 R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 STARTA 15 8 window start address bits 15 to 8 High order address bits used to determine the start address of an I O address window Remark Address bits 25 to 16 of an I O window address are fixed to 0 Therefore an I O window is always mapped to the address space between 0x1400 0000 and 0x1400 FFFF which is the first 64 KB of the ISA IO space 342 User s Manual U14272EJ3VOUM CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 11 IOSLBnREG Index 0x0A OxOE Remark 0 1 IOSLBOREG 0x04 for Window 0 IOSLB1REG 0 0 for Window 1 Bie E cre STOPA7 STOPA6 STOPA5 STOPA4 STOPA3 STOPA2 STOPA1 STOPAO R W R W R W R W R W R W R W R W R W peer qno ee ee ee Bit Name Function STOPA 7 0 window stop address bits 7 to 0 Low order address bits used to determine the stop address of an I O address window 17 4 12 IOSHBnREG Index 0 0 OxOF Remark 0 1 IOSHBOREG 0x0B for Window 0 IOSHB1REG 0x0F for Window 1 STOPA15 STOPA14 STOPA13 STOPA12 STOPA11 STOPA10 STOPA9 STOPA8 R W R W R W R W R W R W R W R W 0 0 0 0 0
356. or exception data load or store System Call exception 2 3 4 5 6 7 8 9 Breakpoint exception Reserved Instruction exception un Coprocessor Unusable exception 12 Integer Overflow exception 13 Trap exception 14 to 22 Reserved for future use 23 Watch exception 24 to 31 Reserved for future use The Vn4181 has eight interrupt request sources IP7 to IPO They are used for the purpose as follows For the detailed description of interrupts of the CPU core refer to 4100 Series Architecture User s Manual 1 IP7 This bit indicates whether there is a timer interrupt request It is set when the values of the Count register and Compare register match 2 IP6 to IP2 IP6 to IP2 reflect the state of the interrupt request signals of the CPU core 3 IP1 and IPO These bits are used to set clear a software interrupt request 80 User s Manual U14272EJ3VOUM CHAPTER 3 REGISTERS 3 2 13 Exception Program Counter register 14 The Exception Program Counter EPC is a read write register that contains the address at which processing resumes after an exception has been serviced The contents of this register change depending on whether execution of MIPS16 instructions is enabled or disabled Setting the MIPS16EN pin after RTC reset specifies whether execution of the MIPS16 instructions is enabled or disabled When the MIPS16 instruction exe
357. ot executed and the Vn4181 continues operating until the HALTimer is reset Consequently the operation of the Va4181 may differ from the operation of the external peripheral circuits when the RSTSW signal is used as a reset signal to the external peripheral circuits Particularly when the reset signal to a flash memory that includes a boot vector and the RSTSW signal are shared the 4181 may not be able to read the correct program and hang up for 4 seconds between when the Vn4181 is started and when the HALTimer is shut down Workaround Do not share the reset signal to the external peripheral circuits with the RSTSW5 signal However if it is necessary to do so insert a circuit like the one shown in the figure below to mask the RSTSW signal between when the Vn4181 is started and when the HALTimer is cleared by using the GPIO pin Figure A 1 Mask Circuit for RSTSW Signal Mask control GPIO To the Vn4181 era flash memory and RSTSW signal external peripheral circuits RSTSW signal for actual use original 436 User s Manual U14272EJ3VOUM APPENDIX RESTRICTIONS Vn4181 2 RSTSWtit in Hibernate Mode The Vn4181 may release the self refresh mode of DRAM when the RSTSW signal is asserted the Hibernate mode As a result the DRAM data may be lost 1 With EDO DRAM When the RSTSW signal goes low the RAS and CAS signals go high and the self refresh mode is release
358. ow 1 MEMOFFH2REG 0x25 for Window 2 OFFSETA OFFSETA 25 24 0 0 Function OFFSETA 19 12 Card memory offset address bits 19 to 12 This register is defined to maintain compatibility with the ExCA Settings in this register have no meaning in the MEMOFFHSREG 0x2D MEMOFFH4REG 0x35 for Window 4 OFFSETA 23 OFFSETA 22 0 for Window 3 OFFSETA 21 0 OFFSETA 20 R W R W R W R W R W R W 0 0 0 0 0 0 Write protect to the card through a memory window 0 Write operation allowed 1 Write operation prohibited REG REG signal active of the CompactFlash This bit is used to set which memory is to be used on accesses to the CompactFlash card 0 Common memory 1 Attribute memory OFFSETA 25 20 Card memory offset address bits 25 to 20 Remark This is defined to maintain compatibility with the ExCA Settings in these bits have no meaning in the Vn4181 346 User s Manual U14272EJ3VOUM CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 19 DTGENCLREG Index 0x16 Reserved Reserved SWCDINT CDRSMEN Reserved Reserved CFGRSTEN DLY16INH Ww R W R W R W 0 0 0 0 Function Reserved 0 is returned when read SWCDINT Software card detect interrupt request 1 Generates interrupt request This bit is valid when the CD EN bit is set to 1 the CRDSTATREG register 0 is returned
359. ow becomes a mirror area occupying the lower 2 KB Figure 17 2 Mapping of CompactFlash Memory Space CompactFlash card Vn4181 Vn4181 Common memory space ISA memory space internal Space specified via ADD pins Attribute memory space 64 MB 4 MB 2 KB Ox13FF FFFF Ox3F FFFF 0 1 s000 Memory window m Memory window m Oxl1rrr r000 Oxlqqq 4000 Memory window n Memory window n Oxlppp p000 0 0000 0000 0 00 0000 Remark m n 0to4 q r s don t care 350 User s Manual U14272EJ3VOUM CHAPTER 17 COMPACTFLASH CONTROLLER ECU 2 VO window In the VR4181 the I O window be mapped to any address within the external ISA I O space s lower 64 KB The start address of a window is output without modification to the Vn4181 s ADD pins When using the CompactFlash card do not map a space for programmable chip select or another external device to the lower 64 KB within external ISA I O space where windows are assigned Figure 17 3 Mapping of CompactFlash Space Vn4181 Vn4181 ISA I O space internal Space specified via ADD pins 64 MB 4 MB 0 17 FFFF Ox3F FFFF CompactFlash card I O space 2 KB 0 1401 0000 0 01 0000 Ox7FF window m window m window m window n window n window n 0 000 0 1400 0000 0 00 0000 Remark m n Oor1 User s Manual U14272EJ3VOUM 351 CHAPTER 17 COMPACTFLA
360. own Register DSUCNTREG address 0 0 00 00 0 data 0x0000 User s Manual U14272EJ3VOUM 235 13 1 Overview CHAPTER 13 GENERAL PURPOSE UNIT GIU 13 1 1 GPIO pins and alternate functions The 4181 provides 32 general purpose I O divided into two groups of 16 pins each The first group GPIO 15 0 pins are capable of supporting the following types of functions Clocked serial interface CSI Serial interface channel 2 e Color LCD interface upper 4 bit data or CompactFlash Card Detect inputs General purpose outputs e Interrupt wake up inputs e Programmable chip selects e External ISA system clock output Any of GPIO 15 0 pins can be used as interrupt wake up inputs The assignment of interface signals to particular GPIO pins is shown in the following table GPIO pin GPIO15 Table 13 1 Alternate Functions of GPIO 15 0 Pins Alternate signal 1 Alternate signal 2 Definition Color LCD data bit output or Card Detect 2 input GPIO14 Color LCD data bit output or Card Detect 1 input 1 Color LCD data bit output GPIO12 Color LCD data bit output GPIO 1 1 Programmable chip select 1 output GPIO10 SYSCLK CSI FRM input or SYSCLK output GPIO9 SIU2 CTS input GPIO8 SIU2 DSR input GPIO7 SIU2 DTR output GPIO6 SIU2 RTS output GPIO5 SIU2 DCD input 4 GPIO3 Programmable chip select 0 output
361. p 4 bpp up to 16 gray scale Color Palette 18 bits High vertical refresh rates for flicker free LCD frame modulation The following is a block diagram of the LCD controller 400 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER Figure 21 1 LCD Controller Block Diagram MBA memory controller LCD Controller MBAGP interface Pixel packing LCD 256 x 18 slave registers palette interface Shift clock Data 4 bits MBA clock Timing Load clock Shift clock generato Load clock LCD interrupt request The LCD controller is a slave module of the MBA bus Its registers can be accessed via the MBA slave interface The frame data are read from main memory via the memory controller and the MBAGP MBA Graphic port Users Manual U14272EJ3VOUM 401 CHAPTER 21 LCD CONTROLLER 21 3 LCD Controller Specification 21 3 1 Panel configuration and interface 1 View rectangle and horizontal vertical blank Most parameters of the LCD controller are described using a coordinate system The x coordinate increases as a point moves to the right The y coordinate increases as a point moves down The origin is 0 0 The size of the bounding box is specified by Vtotal and Htotal The point Vtotal 1 Htotal 1 is the box s lower right corner and includes the horizontal and vertical blanks Vvisible and Hvisible define the view rectangle and outside of the view rectangle are the horizontal blank and vertical b
362. pacity is 4 KB 4 Data cache The data cache employs direct mapping virtual index physical tag and writeback Its capacity is 4 KB 5 CPU bus interface The CPU bus interface controls data transmission reception between the Vn4110 core and the MBA Host Bridge This interface consists of two 32 bit multiplexed address data buses one is for input and another is for output clock signal and control signals such as interrupt requests 6 Clock generator The following clock inputs are oscillated and supplied to internal units 32 768 kHz clock for RTC unit Crystal resonator input oscillated via an internal oscillator and supplied to the RTC unit 18 432 MHz clock for serial interface and the Vn4181 s reference operating clock Crystal resonator input oscillated via an internal oscillator and then multiplied by phase locked loop PLL to generate a pipeline clock PClock The internal bus clock TClock is generated from PClock and supplied to peripheral units 36 User s Manual U14272EJ3VOUM CHAPTER 1 INTRODUCTION 1 4 1 CPU registers The 4110 core has thirty two 64 bit general purpose registers GPRs In addition the processor provides the following special registers e 64 bit Program Counter PC e 64 bit HI register containing the integer multiply and divide upper doubleword result 64 bit LO register containing the integer multiply and divide lower doubleword result Two of the general purpose registers
363. ped Reserved 0 is returned when read SSTOPEN Speaker output DMA transfer page boundary interrupt 1 Stop DMA request at 1 page boundary 0 Stop DMA request at 2 page boundary Reserved 0 is returned when read This register is used to control the AIU s speaker block The DAENAIU bit controls the connection of VDD AD and Vref input to ladder type resistors in the D A converter Setting this bit to 0 OFF allows low power consumption when not using the D A converter When using the D A converter this bit must be set following the sequence described in 15 3 Operation Sequence The content of the SSTATE bit is valid only when the AIUSEN bit of the SEQREG register is set to 1 User s Manual U14272EJ3VOUM 307 CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 6 SCNVC END 0 0 00 016E SCNVC9 SCNVC8 RTCRST Other resets RTCRST Other resets 15100 SCNVC 15 0 Speaker sample rate control This register is used to select a conversion rate for the D A converter The following expression is used to calculate the value set to this register SCNVC 15 0 PCLK frequency sample rate For example if the desired conversion rate is 8 ksps and internal peripheral clock PCLK frequency is 25 MHz SCNVC 15 0 bits should be set to as follows SCNVC 15 0 25 x 10 8 x 10 0x0C35 Caution Set this register to a value that determines the conversion ra
364. peed mode generate an interrupt request of any kind When the processor restores to Fullspeed mode from Standby mode it starts a program execution from the General exception vector OXBFCO 0380 when BEV 0 or 0x8000 0180 when BEV 1 3 Suspend mode 190 The pipeline clock PClock of the CPU core and the internal bus clocks TClock and PCLK are fixed to high level PLL timer interrupt function of the CPU core interrupt clock MasterOut and RTC clock continue their operation The contents of caches and registers in the CPU core are retained The contents of connected DRAMs can be preserved by putting DRAMs into self refresh mode To enter to Suspend mode from Fullspeed mode execute a Suspend mode sequence see 10 6 DRAM Interface Control first After the SUSPEND instruction has passed the WB stage and DRAMs enter self refresh mode the VR4181 waits until SysAD bus internal enters idle state Then internal clocks are shut down and pipeline operation stops To restore to Fullspeed mode from Suspend mode one of the interrupt requests listed in Figure 10 1 interrupt requests that can be used are limited since the internal bus clocks TClock and PCLK stop When the processor restores to Fullspeed mode from Suspend mode it starts a program execution from the General exception vector OxBFCO 0380 when BEV 0 or 0x8000 0180 when BEV 1 User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU 4 Hibernat
365. pper byte enable output general purpose input or LCD modulation output During system bus accesses this signal is active when the high order byte is valid on the data bus 21 System bus reset output or general purpose 1 It is active when the 4181 resets the system bus controller when configured as RESET Note The Vn4181 utilizes different addressings depending on the types of the external accesses During ROM accesses bits 22 to 1 of the internal address lines are output to the ADD 21 0 pins the minimum transfer data width is a half word 1 word 32 bits During accesses other than ROM accesses bits 21 to 0 of the internal address lines are output to the ADD 21 0 pins the minimum transfer data width is 1 byte 52 User s Manual U14272EJ3VOUM CHAPTER 2 PIN FUNCTIONS 2 2 Signal name Description of function Note SYSDIR Output Data bus isolation buffer direction control This signal is valid only when ROM ISA or CompactFlash accesses are enabled This becomes low level during ROM ISA or CompactFlash read cycle or becomes high level during ROM ISA or CompactFlash write cycle SYSEN2 Data bus isolation buffer enable This signal is valid only when ROM ISA or CompactFlash accesses are enabled This becomes active during ROM or ISA cycle SDCS 1 0 RAS 1 0 Output SDRAM chip select for bank 0 and bank 1 or EDO DRAM row address strobes CAS Output SD
366. program Users Manual U14272EJ3VOUM 431 CHAPTER 23 COPROCESSOR 0 HAZARDS Operation Table 23 1 Coprocessor 0 Hazards Source Source name Destination Destination name MTCO CPU general purpose register 5 MFCO CPU general purpose register TLBR Index TLB PageMask EntryHi EntryLoO 5 EntryLo1 TLBWI Index or Random PageMask TLB 5 TLBWR EntryHi EntryLoO EntryLo1 TLBP PageMask EntryHi Index 6 ERET EPC or ErrorEPC TLB Status EXL Status ERL 4 Status CACHE Index Load TagLo TagHi PErr 5 Tag CACHE Index Store TagLo TagHi PErr Tag CACHE Hit operations cache line cache line 5 Coprocessor usable Status CU KSU EXL test ERL Instruction fetch EntryHi ASID Status KSU EXL ERL RE Config K0 TLB Instruction fetch Status 4 exception Cause BadVAddr Context 5 XContext Interrupts Cause IP Status IM IE EXL ERL Load Store EntryHi ASID Status KSU EXL ERL RE Config K0 TLB Config AD EP WatchHi WatchLo Load Store exception EPC Status Cause BadVAddr 5 Context XContext TLB shutdown Status TS 2 Inst 4 Data Remark Brackets indicate a bit name or a field name of registers 432 User s Manual U14272EJ3VOUM CHAPTER 23 COPROCESSOR 0 HAZARDS Cautions 1 below 1 2 3 4 5 6 7 MTCO If the setting o
367. put 01 RFU 10 General purpose output 11 Programmable chip select 1 output Remark When 15 and GPIO14 pins are not defined as CD2 and CD1 signals respectively the corresponding internal card detect signals to CompactFlash controller ECU are held to low level active 248 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 2 2 Function GP10MD 1 0 These bits control direction and function of the GPIO10 pin as follows 00 General purpose input 01 CSI FRM input 10 General purpose output 11 SYSCLK output GP9MD 1 0 These bits control direction and function of the GPIO9 pin as follows 00 General purpose input 01 SIU2 CTS2 input 10 General purpose output 11 RFU GP8MD 1 0 These bits control direction and function of the GPIO8 pin as follows 00 General purpose input 01 SIU2 DSR2 input 10 General purpose output 11 RFU User s Manual U14272EJ3VOUM 249 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 3 GPMD2REG 0 0 00 0304 Name GP23MD1 GP23MDO GP22MD1 GP22MDO GP21MD1 GP21MDO GP20MD1 1 2 GP20MDO R W R W R W R W R W R W R W R W R W RTCRST Other resets GP19MD1 GP19MDO GP18MD1 GP18MDO GP17MD1 GP17MDO GP16MD1 GP16MDO RTCRST R W R W R W R W R W R W R W R W Other resets GP23MD 1 0 Function These bits control dire
368. put to FRM In addition this figure illustrates the CSI cycles when bit 7 of a data is transmitted or received first i e when the LSBMSB bit of the CSIMODE register 0 User s Manual U14272EJ3VOUM 157 CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI The four modes of SCK are described below 1 When CKMD bit 0 and CKPOL bit 0 e Transmission The first transmit data bit is output before the first rising edge of SCK The second transmit data and those that follow are output synchronized with the falling edge of SCK Therefore the external master must sample the data synchronizing with the rising edge of SCK e Reception The external master must output the first data bit before the first rising edge of SCK The Vn4181 samples receive data synchronizing with the rising edge of SCK Therefore the external master must output data synchronizing with the falling edge of SCK 2 When CKMD bit 0 and CKPOL bit 1 e Transmission The first transmit data bit is output before the first falling edge of SCK The second transmit data bit and those that follow are output synchronized with the rising edge of SCK Therefore the external master must sample the data synchronizing with the falling edge of SCK e Reception The external master must output the first data bit before the first falling edge of SCK The Vn4181 samples receive data synchronizing with the falling edge of SCK Therefore the external master must output data synchronizing w
369. r and 15 3 2 Input microphone p 320 Modification of description in 16 2 6 Interrupts and status reporting p 321 Modification of description in Table 16 3 KIU Interrupt Registers p 324 Modification of description for bits 1 and 0 in 16 3 3 KIUSCANS 0 0 00 0192 p 325 Modification of descriptions for bits 14 to 10 and bits 4 to 0 in 16 3 4 KIUWKS 0 0 00 0194 p 327 Modification and addition of descriptions for bits 2 to 0 in 16 3 6 0x0BOO 0198 p 328 Modification of signal name in 17 1 General 8 User s Manual U14272EJ3VOUM Major Revisions in This Edition 4 5 Page Description p 333 Modification of signal names in Figure 17 1 CompactFlash Interrupt Logic p 333 Modification of description for bit 0 in 17 3 3 REG 1 0 0 00 08 p 336 Addition of Caution for bit 4 in 17 4 3 PWRRSETDRV Index 0x02 p 337 Modification of description for bit 7 in 17 4 4 ITGENCREG Index 0x03 p 338 Modification of description and addition of Caution for bit 0 in 17 4 5 CDSTCHGREG Index 0x04 p 341 Modification of descriptions for bits 7 4 3 and 0 in 17 4 8 IOCTRL REG Index 0x07 p 344 Modification of description for bit 6 in 17 4 14 MEMWIDn REG Index 0x11 0x19 0x21 0x29 0x31 p 345 Modification of description for bits 7 and 6 and addition of description in 17 4 16 MEMSELn REG Index 0x13 0x1B 0x23 0 2 0
370. r GND via resistor RESET GP1021 Connect to VDD IO or GND via resistor ROMCS 2 0 GPIO 24 22 Connect to VDD IO or GND via resistor ROMCS3 SHCLK LCDCS Leave open LOCLK MEMCS16 Leave open FLM MIPS16EN Connect to VDD IO or GND via resistor FPD 3 0 Leave open VPLCD VPGPIO1 Leave open VPBIAS VPGPIOO Leave open POWER Connect to GND_IO via resistor RTCRST RSTSW POWERON Leave open MPOWER BATTINH BATTINT TPX 1 0 gt ry rl rl rl rl rl rl rly rl rl rl rl rl rl ry rl rl r ry rye gt gt gt gt gt gt gt gt gt gt TPY 1 0 O Remark No specification in the Recommended Connection When Not Used column indicates that the pin is always connected User s Manual U14272EJ3VOUM 63 CHAPTER 2 PIN FUNCTIONS 2 3 Pin Name Recommended Connection When Not Used Circuit Type ADIN 2 0 Connect to GND AD D AUDIOIN Connect to GND AD D AUDIOOUT Leave open E WEZ SCANOUT7 Leave open A OEZ SCANOUT6 Leave open A CF_lOW SCANOUTS5 Leave open A CF_lIOR SCANOUT4 Leave open A CF_STSCHG SCANOUT3 Connect to VDD IO via resistor A CF_CE 2 1 SCANOUT 2 1 Leave open A CF_BUSY SCANOUTO Connect to VDD IO via resistor A CF_REG SCANIN7 Leave open A CF RESET SCANIN6 Leave open A
371. r Switch interrupt request occurs during modes other than the Hibernate mode However this bit is not set to 1 when the POWER signal becomes high during the Hibernate mode MPOWER L 210 User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 7 2 PMUCNTREG 0 0 00 00A2 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets STANDBY HALTIMER RST RTCRST Other resets Function 15 to 8 Reserved 0 is returned when read 7 STANDBY Standby mode setting This setting is performed only for software and does not affect hardware in any way 1 Standby mode 0 Normal mode 6 Reserved Write 0 when write 0 is returned when read 5 Selfrfresh Self refresh status 1 Completed 0 Not completed 4 Suspend Suspend mode status always 0 during Fullspeed mode 1 Suspend mode 0 Other than Suspend mode 3 Hibernate Hibernate mode status always 0 during Fullspeed mode 1 Hibernate mode 0 Other than Hibernate mode Note Holds the value before reset Users Manual U14272EJ3VOUM 211 CHAPTER 10 POWER MANAGEMENT UNIT PMU 2 2 Function HALTIMERRST HALTimer reset 1 Reset 0 Set Note1 2 This bit is cleared to 0 automatically after reset of the HALTimer Reserved 0 is returned when read Reserved Write 0 when write 0 is returned when read Notes1 Wh
372. r a voltage has been applied to the 2 5 V power supply when the RTC reset or Deadman s Switch reset has been cleared or when the Vn4181 has returned from the Hibernate mode Before accessing an address at which the cache can be used therefore be sure to initialize the contents of the tag RAM of both the instruction cache and data cache Use the TagLo register in CPO to initialize the tags 5 4 2 Internal peripheral units 1 HALTimer Set the HALTIMERRST bit of the PMUCNTREG register in the PMU to 1 within 4 seconds after clearing the RTC reset or RSTSW reset This resets the HALTimer 2 Memory controller Before accessing the DRAM space be sure to initialize the registers in the memory controller Especially when SDRAM is used initialize SDRAM by executing the procedure described 6 5 2 MEMCFG REG 0x0A00 0304 A function to operate SDCLK only when SDRAM is accessed for example is not valid unless a mode setting command is issued to SDRAM by using the MEMCFG REG register 3 Clock supply to peripheral units The clock is not supplied in the default status to the peripheral units such as CSI AIU PIU SIU1 and SIU2 and the A D and D A converters To start using these units and converters supply the necessary clock to them by setting the CMUCLKMSK register in the MBA Host Bridge If these units are not used or they have finished being used mask the clock supply by setting the CMUCLKMSK register 4 Alternate function pins The fun
373. r application please contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics America Inc U S Filiale Italiana NEC Electronics Hong Kong Ltd Santa Clara California Milano Italy Hong Kong Tel 408 588 6000 Tel 02 66 75 41 Tel 2886 9318 800 366 9782 Fax 02 66 75 42 99 Fax 2886 9022 9044 Fax 408 588 6130 800 729 9288 Branch The Netherlands NEC Electronics Hong Kong Ltd Eindhoven The Netherlands Seoul Branch NEC Electronics Europe GmbH Tel 040 244 58 45 Seoul Korea Duesseldorf Germany Fax 040 244 45 80 Tel 02 528 0303 Tel 0211 65 03 01 Fax 02 528 4411 Fax 0211 65 03 327 Tyskland Filial Taeby Sweden NEC Electronics Shanghai Ltd Sucursal en Tel 08 63 80 820 Shanghai P R China Madrid Spain Fax 08 63 80 388 Tel 021 6841 1138 Tel 091 504 27 87 Fax 021 6841 1137 Fax 091 504 28 60 United Kingdom Branch Milton Keynes UK NEC Electronics Taiwan Ltd
374. ral device that emulates a modem The settings of the MCR3 and MCR2 bits become valid only when the MCR4 bit is set to 1 enable use of local loopback Local Loopback The local loopback can be used to test the transmit receive data path in SIU1 The following operation local loopback is executed inside the 5101 when the MCR4 bit 1 The transmit block s serial output TxD1 enters the marking state 1 and the serial input RxD1 to the receive block is cut off The transmit shift register s output is looped back to the receive shift register s input The four modem control inputs DSR1 CTS1 RI internal and DCD1 are cut off and the four modem control outputs DTR1 RTS1 OUT1 internal and OUT2 internal are internally connected to the corresponding modem control inputs The modem control output pins are forcibly set as inactive high level During this kind of loopback mode transmitted data can be immediately and directly received When in loopback mode both transmit and receive interrupts can be used The interrupt sources are external sources in relation to the transmit and receive blocks Although modem control interrupts can be used the low order four bits of the modem control register can be used instead of the four modem control inputs as interrupt Sources As usual each interrupt is controlled by an interrupt enable register 372 User s Manual U14272EJ3VOUM CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 10 SIU
375. rammable chip select 0 mode 00 Disabled 01 Qualified also with I O or Memory read strobe 10 Qualified also with I O or Memory write strobe 11 Based on address decode only User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 23 LCDGPMODE 0 0 00 032E Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets LCDGPEN LCDCS1 LCDCSO GPVPBIAS GPVPLCD RTCRST R W R W R W R W R W Other resets 15 to 8 Reserved Function 0 is returned when read LCDGPEN Control unit of LCD interface signals 0 Controlled by internal LCD controller 1 Controlled by external LCD controller SHCLK LCDCS LOCLK MEMCS16 VPLCD driven by the GPVPLCD bit of this register VPBIAS driven by the GPVPBIAS bit of this register 6104 Reserved 0 is returned when read 3 2 LCDCS 1 0 External LCD controller frame buffer address select These bits determine the address range that will cause the LCDCS signal to be asserted 00 0x130A 0000 to 0x130A FFFF 64KB PC AT compatible address space 01 Ox133E 0000 to Ox133F FFFF 128KB 10 0x133C 0000 to 0x133F FFFF 256KB 11 0 1338 0000 to 0x133F FFFF 512KB GPVPBIAS Output control for VPBIAS pin When the LCDGPEN bit is set to 1 the VPBIAS pin is driven by the value of this bit GPVPLCD Output c
376. rate divisor low order byte Undefined This register is used to set the divisor division rate for the baud rate generator The data in this register and the data in SIUDLM 2 register as upper 8 bits are together handled as 16 bit data To access this register set the LCR7 bit bit 7 of the SIULC 2 register to 1 User s Manual U14272EJ3VOUM Undefined Undefined 381 CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 20 3 4 SIUIE 2 0x0CO00 0001 LCR7 0 Name Reserved Reserved Reserved Reserved R W RTCRST Other resets Function Reserved 0 is returned when read IE3 Modem status interrupt 1 Enable 0 Prohibit Receive status interrupt 1 Enable 0 Prohibit Transmit holding register empty interrupt 1 Enable 0 Prohibit Receive data ready interrupt or character timeout interrupt in FIFO mode 1 Enable 0 Prohibit This register is used to specify interrupt enable prohibit settings for the five types of interrupt requests used in the SIU2 An interrupt is enabled by setting the corresponding bit to 1 Overall use of interrupt functions can be halted by setting bits 0 to 3 of this register to 0 When interrupts are prohibited pending is not displayed in the IIRO bit in the SIUIID_2 register even when interrupt conditions have been met Other functions in the SIU2 are not affected even though interrupts are prohibited and the settings in
377. rations related to the CPO registers and the TLB Therefore contention of internal resources should be considered when composing a program that manipulates the CPO registers or the TLB The hazards define the number of instructions that is required to avoid contention of internal resources or the number of instructions unrelated to contention This chapter describes the CPO hazards The CPO hazards of the Vn4110 CPU core as or less stringent than those of the Vr4000 Table 23 1 lists the Coprocessor 0 hazards of the 4110 CPU core Code that complies with these hazards will run without modification on the Vn4000 The contents of the CPO registers or the bits in the Source column of this table can be used as a source after they are fixed The contents of the CPO registers or the bits in the Destination column of this table can be available as a destination after they are stored Based on this table the number of NOP instructions required between instructions related to the TLB is computed by the following formula and so is the number of instructions unrelated to contention Destination Hazard number of A Source Hazard number of B 1 As an example to compute the number of instructions required between an MTCO and a subsequent MFCO instruction this is 5 8 1 1 instruction The hazards do not generate interlocks of pipeline Therefore the required number of instruction must be controlled by
378. rcuits of Resonator p 52 Modification of Note in 2 2 1 System bus interface signals p 53 Modification of descriptions for SYSDIR and SYSEN and addition of description in Note 2 2 1 System bus interface signals p 58 Addition of description for IRDIN RxD2 in 2 2 10 IrDA interface signals p 60 Addition and modification in 2 3 Pin Status in Specific Status pp 63 to 66 Addition of 2 4 Recommended Connection of Unused Pins and I O Circuit Types and 2 5 Pin I O Circuits pp 67 to 90 Addition of CHAPTER 3 REGISTERS p 95 Modification of Table 4 6 DRAM Address Map p 97 Modification of description in 5 1 1 RTC reset pp 97 to 101 104 105 Addition of description in Note in Figure 5 1 through Figure 5 5 Figure 5 8 and Figure 5 9 p 98 Modification in Figure 5 2 RSTSW Reset p 101 Modification of description in 5 1 5 HALTimer shutdown p 104 Addition of description in 5 3 1 Cold Reset p 105 Modification of description in 5 3 2 Soft Reset pp 106 107 Addition of 5 4 Notes on Initialization 108 Modification in Figure 6 1 Vn4181 Internal Bus Structure 109 Modification of description in 6 1 2 3 LCD module LCD Control Unit 2111 Modification of description for bit 4 and addition of Caution and Remark 6 2 1 BCUCNTREG1 0x0A00 0000 2113 Modification of descriptions for bits 14 to 12 bits 3 to
379. read 9 PalRDI Palette index read status 0 No change after read 1 Incremented by 1 after read PalWRI Palette index write status 0 No change after write 1 Incremented by 1 after write Pallndex 7 0 Palette index Remark In the 4 bpp mode 16 gray scale for monochrome panels the Blue area of the color palette is used for displaying The palette is not used in the other modes 1 bpp and 2 bpp for monochrome panels 428 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 21 4 23 CPALDATREG 0x0A0 0480 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PalData17 PalData16 Undefined Undefined PalData15 PalData14 PalData13 PalData12 PalData1 1 PalData10 PalData9 PalData8 R W R W R W R W R W R W R W R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name PalData7 PalData6 PalData5 PalData4 PalData3 PalData2 PalData1 PalData0 R W R W R W R W R W R W R W R W R W Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 31 to 18 Reserved 0 is returned when read 17 to 0 PalData 17 0 Color palette data 6 6 6 format Caution Do not change palette data during LCD display User s Manual U14272EJ3VOUM 429 CHAPTER 22 PLL PASSIVE COMPONENTS The Vn4181 requires several external passive components for proper operation which are connected to VDD PLL as illus
380. read 9to4 STPREP 5 0 Scan sequencer stop count These bits select the number of scan operation performed after all keys have been released OxFF is loaded to KIUDAT registers 111111 63 times 000001 1 time 000000 64 times Scan stop manual mode This bit is sampled at the end of each scan operation and causes the scan sequencer to stop scanning when set to 1 1 Stop 0 Operate MSTART Manual scan start manual mode When this bit is set to 1 the scan sequencer starts scanning the keyboard 1 Start 0 Stop Auto scan stop auto mode When this bit is set to 1 the scan sequencer stops scanning automatically when all keys have been released for the number of scan operation specified by the STPREP 5 0 bits 1 Auto stop 0 Manual stop ASTART Auto Scan mode enable When this bit is set to 1 the scan sequencer starts scanning automatically following a key press event 1 Enable 0 Disable User s Manual U14272EJ3VOUM 323 CHAPTER 16 KEYBOARD INTERFACE UNIT KIU 16 3 3 KIUSCANS 0 0 00 0192 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Reserved Function 0 is returned when read 324 SSTAT 1 0 Scan sequencer status 11 10 01 00 During scan interval WINTVL Scanning T1CNT or T3CNT Waiting for key pr
381. red An auto stop interrupt request occurs when 1 has already been set to both the LEDSTOP bit and the LEDENABLE bit of the LEDCNTREG register if LEDASTCREG register is cleared to 0 When this interrupt occurs the LEDSTOP bit and the LEDENABLE bit of the LEDCNTREG register are both cleared to 0 358 User s Manual U14272EJ3VOUM CHAPTER 18 LED CONTROL UNIT LED 18 3 Operation Flow LEDs blinking operation start condition Software Start Register initial setting Note Set LEDHTSREG Set LEDLTSREG Set LEDASTCREG LEDCNTREG LEDSTOP 1 LEDCNTREG LEDENABLE 1 Register initial setting LEDHTSREG 0 0010 LED ON time available LEDLTSREG 0x0020 LED OFF time available LEDCNTREG 0 0002 LEDASTCREG 0 04 0 LED blinking time setting LEDHTSREG Set LED ON time LEDLTSREG Set LED OFF time LEDASTCREG Set number of LEDs blinking Caution Setting these registers to 0 is prohibited because it may cause undefined operation LED auto stop setting LEDSTOP Set this bit to enable the LED blink auto stop function This setting terminates LED blinking automatically after blinking time set above has elapaed LED blinking operation start LEDENABLE Set this bit to start LED blinking operation Hardware LEDs blink kam Auto stop counter 0 LEDENABLE 0 LEDSTOP 0 LEDINT 1 LEDs OFF End 3 LED blinking operation Supervisin
382. rmats c Jump and branch instructions change the control flow of a program Jumps are made either to an absolute address formed by combining a 26 bit target address with the higher bits of the program counter J type format or register specified address R type format The format of the branch instructions is type Branches have 16 bit offsets relative to the program counter JAL instructions save their return address in register 31 d System control coprocessor instructions perform operations on CPO registers to control the memory management and exception handling facilities of the processor e Special instructions perform system calls and breakpoint exceptions or cause a branch to the general exception handling vector based upon the result of a comparison These instructions occur in both R type and l type formats 38 User s Manual U14272EJ3VOUM CHAPTER 1 INTRODUCTION 2 MIPS16 instructions All the CPU instructions except for JAL and JALX are 16 bit length when executing MIPS16 instructions and they are classified into thirteen instruction formats as shown in Figure 1 5 Figure 1 5 CPU Instruction Formats 16 Bit Length Instruction E A EN N a N 15 1110 87 54 0 15 1110 87 54 21 0 15 1110 87 4 3 0 15 1110 87 54 21 0 15 1110 87 0 15 1110 87 54 0 15 1110 87 54 32 0 l8 MOVS2R type o 8 O funct r32 2 0 r32 4
383. rnal change 1 Changed 0 No change MSR1 DSR1 signal change 1 Changed 0 No change MSRO CTS1 signal change 1 Changed 0 No change This register indicates the current status and change in status of various control signals that are input to the CPU from a modem or other peripheral device The MSR 3 0 bits are cleared to 0 if they are read when they are set to 1 User s Manual U14272EJ3VOUM 375 CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 12 SIUSC 1 0 0 00 0017 Name SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCRO R W R W R W R W R W R W R W R W R W RTCRST Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Other resets Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Name Function 7100 SCR 7 0 General purpose data This register is a readable writable 8 bit register and can be used freely by users It does not affect control of the SIU1 19 3 13 SIURESET 1 0 0 00 0019 Reserved Reserved Reserved Reserved Reserved Reserved Reserved RTCRST Other resets Bit Name Function Reserved 0 is returned when read SIURESET SIU1 reset 1 Reset 0 Release reset This register is used to reset SIU1 forcibly 376 User s Manual U14272EJ3VOUM CHAPTER 19 SERIAL INTERFACE UNIT 1 5101 19 3 14 SIUACTMSK 1 0 0 00 001C Na
384. rpose pins The Vn4181 also supports up to 2 banks of 1M x 16 or 4M x 16 EDO type DRAM or SDRAM at bus frequencies of up to 66 MHz When both banks are EDO type DRAM bank mixing is supported 1 3 4 DMA controller DCU The Vn4181 provides 4 channel DMA controller to support internal DMA transfers The 4 channels are allocated as follows e Channel 1 Audio input e Channel 2 Audio output e Channel 3 4 Reserved 1 3 5 Interrupt controller ICU The Vn4181 provides an interrupt controller which combines all interrupt request sources into one of the Vn4110 core interrupt inputs NMI and Int 2 0 The interrupt controller also provides interrupt request status reporting 1 3 6 Real time clock The Vn4181 includes a real time clock RTC which allows time keeping based on the 32 768 kHz clock as a source The RTC operates as long as the 4181 remains powered 1 3 7 Audio output D A converter The Vn4181 provides a 1 channel 10 bit D A converter for generating audio output 1 3 8 Touch panel interface and audio input A D converter The Vn4181 provides an 8 channel 10 bit A D converter for interfacing to a touch panel an external microphone and other types of analog input 1 3 9 CompactFlash interface ECU The Vn4181 provides an ExCA compatible bus controller supporting a single CompactFlash slot This interface is shared with the keyboard interface logic and must be disabled when an 8 x 8 key matrix is connected to the Vn4
385. rror level 0 Normal 1 Error Sets and indicates the exception level 0 Normal 1 Exception Sets and indicates interrupt enabling disabling 0 Disabled 1 Enabled Reserved for future use Write 0 in a write operation When this bit is read 0 is read Figure 3 13 shows the details of the Diagnostic Status DS field All DS field bits other than the TS bit are writable Figure 3 13 Status Register Diagnostic Status Field 24 23 22 21 20 19 18 17 16 o s o e BEV Specifies the base address of a TLB Refill exception vector and common exception vector 0 gt Normal 1 Bootstrap TS Occurs the TLB to be shut down read only 0 Not shut down 1 Shut down This bit is used to avoid any problems that may occur when multiple TLB entries match the same virtual address After the TLB has been shut down reset the processor to enable restart Note that the TLB is shut down even if a TLB entry matching a virtual address is marked as being invalid with the V bit cleared SR Occurs Soft Reset or NMI exception 0 Not occurred 1 Occurred CH condition bit 0 False 1 True This bit can be read and written by software only it cannot be accessed by hardware CE DE These are prepared to maintain compatibility with the VR4100 and are not used in the Vn4181 hardware 0 Reserved for future use Write 0 in a write operation When this field is read
386. rtual addresses into physical addresses Virtual addresses are translated into physical addresses using an on chip TLB The on chip TLB is a full associative memory that holds 32 entries which provide mapping to 32 odd even page pairs for one entry The TLB is accessed through the CPO registers Note that the virtual address space includes areas that are translated to physical addresses without using a TLB and areas where the use of cache memory can be selected The Vn4181 has three operating modes User Supervisor and Kernel the manner in which memory addresses are mapped depends on these operating modes In addition the 4181 supports the 32 bit and 64 bit addressing modes the manner in which memory addresses are translated or mapped depends on these addressing modes For details about the memory management system and virtual address space refer to VR4100 Series Architecture User s Manual User s Manual U14272EJ3VOUM 91 CHAPTER 4 MEMORY MANAGEMENT SYSTEM 4 2 Physical Address Space Using a 32 bit address the processor physical address space encompasses 4 GB The Vn4181 uses this 4 GB physical address space as shown in Figure 4 1 Figure 4 1 4181 Physical Address Space OxFFFF FFFF Mirror image of 0x0000 0000 to Ox1FFF FFFF area 0x2000 0000 OxlFFF FFFF ROM space including a boot ROM 0 1800 0000 Ox17FF FFFF External system bus space ISA 1 0 1400 0000 Ox13FF FFFF External system bus me
387. rved 0 is returned when read 5 Reserved 1 is returned when read 4 PWREN Card power enable 0 Disabled Vcc is 0 V 1 Enabled Voltage selected in the VOLTSELREG register 0x2F is applied The power to the socked is turned on when a card is inserted and off when removed Caution The Vr4181 supports cards with the card voltage of 3 3 V only Do not set this bit to 1 unless the contents of the VOTSELREG register are 0x01 3 2 Reserved 0 is returned when read 1 Reserved Write 0 when write 0 is returned when read 0 Reserved 0 is returned when read 336 User s Manual U14272EJ3VOUM CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 4 ITGENCTREG Index 0x03 CRDRST CRDTYP Reserved IRQSEL3 IRQSEL2 IRQSEL1 IRQSELO R W R W R W R W R W R W 0 0 0 0 1 1 Function Ring indicate enable This bit is used to switch the function of the STSCHG RI signal from the I O card The ring indicator function cannot be used in the 4181 So that 0 must be written to this bit 0 Used as the STSCHG The current status of the signal is read from the IF_STAT_REG register if this signal is configures as a source for the card status change interrupt 1 Used as the RIZ For memory PC Cards this bit has no function CRDRST Card reset This bit is for a software reset to the PC Card to which the status of the CF_RESET signal is set 0 Active The CF RESET signal will be active until thi
388. rved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets Function Reserved 0 is returned when read LCDINTR LCD interrupt request 0 Not occurred 1 Occurred DMAINTR DMA interrupt request 0 Not occurred 1 Occurred Reserved 0 is returned when read CSUINTR CSI interrupt request 0 Not occurred 1 Occurred ECUINTR CompactFlash interrupt request 0 Not occurred 1 Occurred LEDINTR LED interrupt request 0 Not occurred 1 Occurred RTCL2INTR RTCLong2 interrupt request 0 Not occurred 1 Occurred This register indicates level 1 interrupt requests status 180 User s Manual U14272EJ3VOUM CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 6 MSYSINT2REG 0x0A00 0206 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets MRTCL2 INTR RTCRST Other resets Function Reserved 0 is returned when read MLCDINTR Enables LCD interrupt 0 Disable 1 Enable MDMAINTR Enables DMA interrupt 0 Disable 1 Enable Reserved Write 0 when write 0 is returned when read MCSUINTR Enables CSI interrupt 0 Disable 1 Enable MECUINTR Enables CompactFlash interrupt 0 Disable 1 Enable MLEDINTR Enables LED interrupt 0 Disable 1 Enable MRTCL2INTR En
389. s Prohibited Note Bits 9 and 8 must be set to 01 before using SDRAM Especially be sure to set 1 to bit 8 since its default value is 0 When these bits are not 01 the 4181 may not work correctly This register is used to set SDRAM timing parameters Software must set this register suitable before using SDRAM 136 User s Manual U14272EJ3VOUM CHAPTER 6 BUS CONTROL 6 6 ISA Bridge The Vn4181 has an external bus used for ROM flash memory DRAM and I O This bus s operation emulates an ISA bus at accesses to external memory and spaces The Vn4181 also uses an ISA bus internally for the slow embedded peripherals Among the pins used for accesses in the external ISA bus UBE 516 IORDY IOWR and IORD share the pins with GPIO 20 16 as well as MEMCS16 with LOCLK To use these pins as an external ISA bus interface make settings in the GIU in advance 6 7 ISA Bridge Register Set The following registers provide configuration and control of the ISA Bridge Table 6 4 ISA Bridge Registers Physical address Register symbol Function 0 0 00 02 0 ISABRGCTL ISA Bridge control register 0 0 00 02C2 ISABRGSTS ISA Bridge status register 0 0 00 02 4 XISACTL External ISA control register Users Manual U14272EJ3VOUM 137 CHAPTER 6 BUS CONTROL 6 7 1 ISABRGCTL 0 0 00 02 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST
390. s In order to change Div mode software has to put the CPU core into the Hibernate mode The Div mode will change when the CPU core wakes up from the Hibernate mode 214 User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 7 5 DRAMHIBCTL 0 0 00 00B2 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets Reserved OK_STOP SUSPEND DRAM_EN RTCRST Undefined Other resets Reserved Undefined 0 is returned when read Function Reserved An undefined value is returned when read 3 OK_STOP_CLK Ready to stop clocks 1 Ready DRAM is in self refresh mode 0 Not ready MEMC is busy to do burst refresh 2 STOP_CLK Clock supply for MEMC 1 Stop 0 Supply 1 SUSPEND Self refresh request This bit is for software request to MEMC to perform burst refresh and enter self refresh mode 1 Request 0 Not request 0 DRAM EN DRAM interface operation enable 1 Disabled 0 Enabled normal mode Note Holds the value before reset User s Manual U14272EJ3VOUM 215 CHAPTER 11 REALTIME CLOCK UNIT RTC This chapter describes the RTC unit s operations and register settings 11 1 General The RTC unit has a total of three timers including the following two types e RTCLong This is a 24 bit programmable counter that counts down by 32 768 kHz cloc
391. s bit is set to 1 1 Inactive CRDTYP Card type 0 Memory card 1 I O card Reserved 0 is returned when read IRQSEL 3 0 Interrupt request steering for the card IREQ CF_BUSY signal 0000 IRQ is not used 0001 RFU 0010 RFU 0011 IRQ3 is used 0100 IRQ4 is used 0101 IRQ5 is used 0110 RFU 0111 IRQ7 is used 1000 RFU 1001 IRQ9 is used 1010 IRQ10 is used 1011 IRQ11 is used 1100 IRQ12 is used 1101 RFU 1110 IRQ14 is used 1111 IRQ15 is used User s Manual U14272EJ3VOUM 337 CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 5 CDSTCHGREG Index 0x04 Reserved Reserved Reserved Reserved RDY CHG Reserved BAT DEAD R W R W 0 0 Function Reserved 0 is returned when read 3 CD CHG Card detect CD1 and CD2 signals status change 0 Not changed 1 Changed 2 RDY CHG Ready CF BUSY signal change 0 No change or I O card installed 1 A low to high change has been detected indicating that the memory card is ready to accept a new data transfer 1 Reserved 0 is returned when read 0 BAT DEAD Battery not usable or status change detection STSCHG signal status 0 For memory cards battery is good For I O cards the RI EN bit of the ITGENCTREG register is set to 1 or the 5 5 signal is at high level 1 For memory cards a battery dead condition has been detected For I O cards the RI EN bit of the
392. s contents when it is read are undefined 186 User s Manual U14272EJ3VOUM CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 12 MKIUINTREG 0 0 00 0092 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets MSKKDAT MSKKDAT MSKK LOST RDY DOWNINT RTCRST Other resets Function Reserved 0 is returned when read MSKKDATLOST Enables Keyboard Data Lost interrupt 0 Disable 1 Enable This bit may be used to temporarily mask the Keyboard Data Lost interrupt request and does not affect Keyboard Data Lost event detection MSKKDATRDY Enables Keyboard Data Ready interrupt 0 Disable 1 Enable This bit may be used to temporarily mask the Keyboard Data Ready interrupt request and does not affect Keyboard Data Ready event detection MSKKDOWNINT Enables Key Down interrupt 0 Disable 1 Enable This bit may be used to temporarily mask the Key Down interrupt request and does not affect Key Down event detection Users Manual U14272EJ3VOUM 187 CHAPTER 10 POWER MANAGEMENT UNIT PMU This chapter describes the Power Management Unit PMU operation register settings and power modes 10 1 General The PMU performs power management within the Vr4181 and controls the power supply throughout the system The PMU provides the following functions e Reset control e Shutdown control e Power on control e Low power
393. s has a distinct mapping of otherwise identical virtual page numbers R Space type 00 user 01 supervisor 11 kernel Matches bits 63 and 62 of the virtual address Fill Reserved Ignored on write When read returns zero 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read User s Manual U14272EJ3VOUM 75 CHAPTER 3 REGISTERS 3 2 10 Compare register 11 The Compare register causes a timer interrupt it maintains a stable value that does not change on its own When the value of the Count register see 3 2 8 Count register 9 equals the value of the Compare register the IP7 bit in the Cause register is set This causes an interrupt as soon as the interrupt is enabled Writing a value to the Compare register as a side effect clears the timer interrupt request For diagnostic purposes the Compare register is a read write register Normally this register should be only used for a write The contents of the Compare register are undefined after a reset Figure 3 11 Compare Register 31 0 Compare Value that is compared with the count value of the Count register 3 2 11 Status register 12 The Status register is a read write register that contains the operating mode interrupt enabling and the diagnostic states of the processor Figure 3 12 Status Register 1 2 29 28 27 26 25 24 16 15 Le pap s pep 5 I c CUO Enables
394. s in the Vn4181 the processor should be completely initialized by software see 5 4 Notes on Initialization Caution The Vn4181 does not sets the DRAM to self refresh mode by HALTimer shutdown Therefore the contents of DRAM after a HALTimer shutdown are not at all guaranteed Figure 5 5 HALTimer Shutdown POWER I t Input POWERON Output m MPOWER Output JE AN m ColdReset Internal Reset Internal _ X Stable oscillation PLL Internal Stopped E j Undefined Stable oscillation RTC Internal 32 768 kHz F8 P al about 4 s gt 32 MS a gt 16ms Note1 16MasterClockNete2 Notes 1 Wait time for activation It can be changed by setting the PMUWAITREG register 2 MasterClock is the basic clock used in the CPU core Its frequency is one forth of TClock frequency User s Manual U14272EJ3VOUM 101 CHAPTER 5 INITIALIZATION INTERFACE 5 2 Power on Sequence The factors that cause the Vr4181 to switch from Hibernate mode or shutdown mode to Fullspeed mode are called activation factors There five activation factors assertion of the POWER pin the DCD1 pin or the GPIO 15 0 pins or activation of the ElapsedTime or CompactFlash interrupt request When an activation factor occurs the 4181 asserts the POWERON pin to notify to external agents that the 4181 is ready for power on Three RTC clock cycles
395. s of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular applic
396. s the peripheral unit reset and starts the Cold Reset sequence to activate the CPU core If the BATTINH signal is at low level the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown After the CPU core is restarted the BATTINH bit must be checked and cleared to 0 by software The CPU core sets 1 to the GPWAKEUP bit in the PMUINTREG register regardless of whether activation succeeds or fails Caution The changes in the GPIO signals are ignored while POWERON signal is active Figure 10 7 Activation via GPIO Activation Interrupt Request BATTINH RTO 15 0 I O POWERON Output d n MPOWER C NY BATTINH BATTINT Input T Figure 10 8 Activation via GPIO Activation Interrupt Request BATTINH L RTC GPIO 15 0 I O POWERON Output MPOWER Output YY BATTINH BATTINT Input L User s Manual U14272EJ3VOUM 197 CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 5 4 Activation via DCD interrupt request When the DCD1 signal is asserted the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated After asserting the POWERON signal the PMU checks the BATTINH signal and then de asserts the POWERON signal If the BATTINH signal is at high level the PMU cancels t
397. sequencer operation Initialization via a reset sets particular values for the sequence interval etc which should be re set to appropriate values The following registers require initial settings SCANINTVAL 10 0 bit of PIUSIVLREG register STABLE 5 0 bit of PIUSTBLREG register Interrupt mask cancellation settings are required for registers other than the PIU registers Table 14 7 Mask Clear During Scan Sequencer Operation Setting Register Interrupt mask clear ICU MSYSINT1REG MPIUINTR ICU MPIUINTREG bits 6 to 0 Clock mask clear MBA Host Bridge CMUCLKMSK MSKPIUPCLK 1 Transition flow for voltage detection at A D general purpose ports and audio input port Standby WaitPenTouch or Interval state 1 PIUAMSKREG Mask setting for A D ports and audio input port 2 PIUASCNREG ADPSSTART 1 ADPScan state 3 PIUASCNREG ADPSSTART 0 Standby WaitPenTouch or Interval state 2 Transition flow for auto scan coordinate detection Standby state 1 PIUCNTREG PIUMODE 1 0 00 PADATSTART 1 PADATSTOP 1 2 PIUCNTREG PIUSEQEN 1 WaitPenTouch state User s Manual U14272EJ3VOUM 295 CHAPTER 14 TOUCH PANEL INTERFACE UNIT PIU 3 Transition flow for manual scan coordinate detection Disable state 1 PIUCNTREG PIUPWR 1 Standby state 2 PIUCNTREG PIUMODE 1 0 00 PADSCANSTART 1 3 PIUCNTREG PIUSEQEN 1 2 DataScan state 4 Transition flow when entering
398. serial interface channel 1 The GIU drives inputs to the serial interface channel 2 based on the settings in the GPIO Mode registers and bit 7 2 of the GPSICTL register address 0 0 00 031A for additional information see 13 3 14 GPSICTL 0 0 00 0314 When GPIO pins have been assigned to provide the serial interface channel 2 inputs DTR2 RTS2 and DCD2 the GIU simply passes the signals driven on the GPIO pins to the corresponding serial interface channel 2 inputs Otherwise the GIU drives these signals based on the value programmed in the GPSICTL register as follows Table 13 7 Serial Interface Channel 2 SIU2 Loopback Control LOOPBKQ bit value Source for driving SIU2 input DSR2 REGDSR2 bit 1 value 52 REGCTS2 bit 2 value DCD2 REGDCD2 bit 0 value DSR2 DTR2 output CTS2 RTS2 output DCD2 REGDCD2 bit 0 value Note that the GIU does not drive the RxD2 input This signal is always available to the serial interface as either IRDIN or RxD2 240 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 2 3 LCD interface The GIU supports two functions for the LCD interface The first is pin mapping for 8 bit STN color LCD panel support The second is pin mapping for support of an external LCD controller with integrated frame buffer RAM For additional details about the LCD registers see CHAPTER 21 LCD CONTROLLER 1 STN color LCD interface pin mapping The co
399. sh cycle SDRAM data will be destroyed 192 User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 4 Shutdown Control The operations of the RTC peripheral units and CPU core and PMUINTREG register bit settings during a reset are listed below For detail of the timing of each shutdown refer to CHAPTER 5 INITIALIZATION INTERFACE Table 10 3 Operations During Shutdown Shutdown type Peripheral units CPU core PMUINTREG bits HALTimer shutdown Active Cold Reset TIMOUTRST 1 Software shutdown Active Cold Reset BATTINH shutdown Active Cold Reset BATTINH 1 10 4 1 HALTimer shutdown After the CPU core is activated following the mode change from Shutdown or Hibernate mode to Fullspeed mode or the CPU core is reset by RSTSW reset software must write 1 to HALTIMERRST bit in the PMUCNTREG register within about four seconds to clear the Timer If the HALTimer is not reset within about four seconds after the CPU core is activated or the RSTSW reset is canceled the PMU resets all peripheral units except for RTC and PMU Then the PMU resets Cold Reset the CPU core In addition TIMOUTRST bit in PMUINTREG register is set to 1 After the CPU core is restarted TIMOUTRST bit must be checked and cleared to 0 by software 10 4 2 Software shutdown When the HIBERNATE instruction is executed the PMU checks for currently pending interrupt requests If there are no pending interrupt reque
400. sion MJREV 3 0 MINREV 3 0 Even if the CPU core or the peripheral unit has been changed there is no guarantee that REVIDREG register will be reflected or that the changes to the revision number necessarily reflect real changes of the CPU core or the peripheral unit characterize the units Caution Values of this register bits differ depending on the delivery date 116 User s Manual U14272EJ3VOUM For this reason software should not rely on the revision number in REVIDREG register to CHAPTER 6 BUS CONTROL 6 2 6 CLKSPEEDREG 0x0A00 0018 Reserved Reserved Reserved Reserved Reserved R R R R R 4 3 2 1 0 Reserved Reserved Reserved CLKSP4 CLKSP3 CLKSP2 CLKSP1 CLKSPO R R R R R R R R 15 to 13 DIV 2 4 Value used to calculate the TClock MBA clock and SDCLK operating frequency 12to5 Reserved 0 is returned when read 4 0 CLKSP 4 0 Value used to calculate the CPU core operating clock PClock frequency The following expression is used to calculate the PClock and TClock frequency 1 CPU core clock PClock PClock 18 432 MHz CLKSP 4 0 x 64 2 Peripheral clock TClock 111 TClock PClock 1 Divi mode 011 TClock PClock 2 Div2 mode 101 TClock PClock 3 Div3 mode Others Reserved Remark PClock frequency is decided by CLKSEL 2 0 pin statuses during RTC reset TClock frequency is always a half of PClock frequen
401. sion rate for the A D converter The following expression is used to calculate the value set to this register MCNVO 15 0 PCLK frequency sample rate For example if the desired conversion rate is 11 025 ksps and internal peripheral clock PCLK frequency is 25 MHz the MCNVC 15 0 bits should be set to as follows 15 0 25 x 10 11 025 x 10 0x08DC Caution Set this register to a value that determines the conversion rate as 50 ksps or less 314 User s Manual U14272EJ3VOUM CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 3 Operation Sequence 15 3 1 O 8 9 Output speaker Set conversion rate 0 0 00 016E SCNVC 15 0 any value Set D A converter Vref setup time 0 0 00 0164 any value to be DVAREF 15 0 PCLK frequency 5 us Enable DMA after setting DMA address in DCU Set D A converter s Vref to ON 0x0B00 0168 DAENAIU 1 Wait for Vref resistor stabilization time about 5 us use the RTC counter Even if speaker power is set to ON and speaker operation is enabled AIUSEN 1 without waiting for Vref resistor stabilization time speaker output starts after the period calculated with the formula below 5 1 conversion rate 44 1 22 05 11 025 or 8 us In this case however a noise may occur when speaker power is set to ON Set speaker power ON via GPIO Enable speaker operation 0 0 00 017A AIUSEN 1 DMA request Receive acknowledge and DMA data from DMA 0x0B00 0178 SDMAV SOD
402. space differs depending on the capacity of the DRAM being used The DRAM capacity is set via the B1Config 1 0 bits in MEMCFG REG register The physical addresses of the DRAM space are listed below Table 4 6 DRAM Address Map Physical address When using 16 Mbit DRAM When using 64 Mbit DRAM OxOOFF FFFF to 0x0080 0000 Reserved for future use Bank 1 SDCS1 RAS1 0x007F FFFF to 0x0040 0000 Bank 0 SDCSO RASO 0x003F FFFF to 0x0020 0000 Bank 1 SDCS1 RAS1 0x001F FFFF to 0x0000 0000 Bank 0 SDCSO RASO User s Manual U14272EJ3VOUM 95 CHAPTER 5 INITIALIZATION INTERFACE This chapter describes the reset signal descriptions and types signal and timing related dependence and the initialization sequence during each mode that can be selected by the user A detailed description of the operation during and after a reset and its relationships to the power modes are also provided in CHAPTER 10 POWER MANAGEMENT UNIT PMU Remark that follows signal names indicates active low 5 1 Reset Function There are five ways to reset the 4181 Each is summarized below 96 User s Manual U14272EJ3VOUM CHAPTER 5 INITIALIZATION INTERFACE 5 1 1 RTC reset During power on set the RTCRST pin as active After waiting about 600 ms for the 32 768 kHz oscillator to begin oscillating when the power supply is stable at 3 0 V or above setting the RTCRST as inactive causes the RTC unit to begin counti
403. status Interrupt set reset function Interrupt source Overrun error parity error framing error or break Interrupt reset control Read line status register 2nd Receive data ready Receive data exists or has reached the trigger level Read the receive buffer register or lower the data in the FIFO than trigger level Character timeout During the time period for the four most recent characters not one character has been read from the receive FIFO nor has a character been input to the receive FIFO During this period at least one character has been held in the receive FIFO Read receive buffer register Transmit holding register empty Transmit register is empty Read IIR if it is the interrupt source or write to transmit holding register Note FIFO mode only 386 Modem status CTS2 DSR2 or 2 User s Manual U14272EJ3VOUM Read modem status register CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 20 3 7 SIUFC 2 0 0 00 0002 Write Name Reserved Reserved R W RTCRST Other resets Function 7 6 FCR 7 6 Receive FIFO trigger level 11 14 bytes 10 8 bytes 01 4 bytes 00 0 bytes 5 4 Reserved 0 is returned when read 3 FCR3 Switch between 16450 mode and FIFO mode 1 From 16450 mode to FIFO mode 0 From FIFO mode to 16450 mode 2 FCR2 Transmit FIFO and its counter clear Cleared to 0 wh
404. ster Ox0A00 0426 R W FHENDREG FLM horizontal end register 0 0 00 0430 R W PWRCONREG1 Power control register 1 0x0A00 0432 R W PWRCONREG2 Power control register 2 Ox0A00 0434 R W LCDIMSKREG LCD interrupt mask register 0x0A00 047E R W CPINDCTREG Color palette index and control register 0 0 00 0480 R W CPALDATREG Color palette data register 32 bits wide Users Manual U14272EJ3VOUM 413 CHAPTER 21 LCD CONTROLLER 21 4 1 HRTOTALREG 0x0A00 0400 Reserved Reserved Bit Name Function Reserved 0 is returned when read Htot 7 0 Number of horizontal total columns Set this register to a value one half of the horizontal total Horizontal total horizontal visible width horizontal blank 21 4 2 HRVISIBREG 0x0A00 0402 Bit 15 14 13 12 11 10 9 8 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W R R R Reserved 0 is returned when read Hact 5 0 Number of horizontal visible pixels Set this register to a value one eighth of the horizontal visible pixels 414 Users Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 21 4 3 LDCLKSTREG 0x0A00 0404 Reserved Reserved Reserved 0 is returned when read LCS 7 0 X coordinate of the first edge of the LOCLK Set this register to a value one half of the first edge of the LOCLK Reserved Reserved
405. ster to 1 Check and clear the TIMOUTRST bit in the PMUINTREG register in the case a HALTimer Shutdown had occurred Copy the codes for the restore 6 through 12 below beginning at a 16 byte boundary into the cache by using a Fill operation of CACHE instruction and jump to the cached codes These codes can be executed on ROM Reinitialize all the registers and peripherals during Hibernate mode and restore those registers saved in the general purpose registers MISCREG 0 15 which retain values during Hibernate mode in the GIU or in external memory Clear the DRAM EN bit in the DRAMHIBCTL register to 0 so that the DRAM interface signals are again driven directly by the memory controller SDRAM exits the self refresh mode Set the MEMCFG REG MODE REG and SDTIMINGREG registers in the memory controller according to the SDRAM type to be used 11 If burst refreshes are needed set a value that determines the refresh count to every 250 ns to the BCURFONTREG register the MBA Host Bridge Then execute CBR auto refresh cycles for a specific time period i e OXGFFF x TClock period burst refresh interval required by DRAM 12 Restore to the BCURFCNTREG register in the MBA Host Bridge a value that determines refresh interval satisfying the conditions of DRAM type to be used User s Manual U14272EJ3VOUM CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 6 5 Entering Suspend mode EDO DRAM 1 2 lt 3 gt
406. strobe Note This signal supports input only The GPIO29 DCD1 pin be used as an activation wake up factor from Hibernate mode if enabled by software The other pins listed above are only capable of providing general purpose input or output or the alternate function listed User s Manual U14272EJ3VOUM 237 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 1 2 I O direction control For each GPIO pin the GIU provides register fields of one buffer enable GPENn one output data GPOn and one input data The function of each GPIO pin is decoded by 2 register bits in one of the GPIO Mode registers The most significant bit GPnMD1 controls the input output direction of the GPIO pin while the system is powered during Fullspeed Standby or Suspend mode When this bit is set to 1 the GPIO pin is normally configured as an output During Hibernate mode the GPIO buffer enables are controlled by the GPHIBSTH and GPHIBSTL registers Remark n 0 to 31 13 1 3 General purpose registers The GIU includes sixteen 16 bit general purpose registers Since the contents of these registers are preserved even during Hibernate mode these registers can be used by system software to save the state of selected registers located in the 2 5 V block prior to entering Hibernate mode Once the Vn4181 has resumed from Hibernate mode System software can then restore the state of those 2 5 V registers from the general purpose registers The gen
407. sts it stops the CPU core clock It then resets all peripheral units except for the RTC GIU and the PMU The PMU register contents do not change 10 4 3 BATTINH shutdown If the BATTINH signal is asserted when the CPU core is going to be activated the PMU stops CPU activation and resets all peripheral units except for the RTC GIU and the PMU Then it resets the CPU core In addition BATTINH bit in the PMUINTREG register is set to 1 After the CPU core is restarted BATTINH bit must be checked and cleared to 0 by software For details of the timing of BATTINH shutdown see 10 5 Power on Control below User s Manual U14272EJ3VOUM 193 CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 5 Power on Control The causes of CPU core activation mode change from shutdown mode or Hibernate mode to Fullspeed mode are called activation factors There are twenty activation factors a power switch interrupt POWER sixteen types of GPIO activation interrupts GPIO 15 0 DCD interrupt DCD a CompactFlash interrupt and an ElapsedTime interrupt Battery low detection BATTINH BATTINT pin check is a factor that prevents CPU core activation The period power on wait time in which the POWERON pin is active at power on can be specified by using PMUWAITREG register After RTCRST by which the CPU core is initialized the period is set as 343 75 ms Power on wait time can be specified when activation is caused by sources other than RTCRST When
408. t Function GPIO interrupt enable There is a one to one correspondence between these bits and GPIO pins When one of the GPIO 15 0 pins is defined as a general purpose input the corresponding bit in this register enables interrupts for that pin as follows 0 Interrupt disabled 1 Interrupt enabled Remark About the relationship between the GPINTEN and GPINTMSK registers refer to Figure 13 1 GPIO 15 0 Interrupt Request Detecting Logic 256 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 8 GPINTMSK 0 0 00 030 Name GIMSK15 GIMSK14 GIMSK13 GIMSK12 GIMSK1 1 GIMSK10 GIMSK9 GIMSK8 R W R W R W R W R W R W R W R W R W RTCRST Other resets GIMSK7 GIMSK6 GIMSK5 GIMSK4 GIMSK3 GIMSK2 GIMSK1 GIMSKO R W R W R W R W R W R W R W R W RTCRST Other resets Function GIMSK 15 0 GPIO interrupt mask There is a one to one correspondence between these bits and GPIO pins When a GPIO pin is defined as a general purpose input and interrupts is enabled on that pin the interrupt can be temporarily masked by setting the corresponding bit in this register as follows 0 Interrupt unmasked 1 Interrupt masked Note Holds the value before reset Remark About the relationship between the GPINTEN and GPINTMSK registers refer to Figure 13 1 GPIO 15 0 Interrupt Request Detecting Logic Users Manual U14272EJ3VOUM 257 CHAPT
409. t 01 CSI SI input 10 General purpose output 11 RFU Users Manual U14272EJ3VOUM 247 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 2 GPMD1REG 0 0 00 0302 Name GP15MD1 GP15MDO GP14MD1 GP14MDO GP13MD1 GP13MDO GP12MD1 1 2 GP12MDO R W R W R W R W R W R W R W R W R W RTCRST Other resets GP11MD1 GP11MDO GP10MD1 GP10MDO GP9MD1 GP9MDO GP8MD1 GP8MDO RTCRST R W R W R W R W R W R W R W R W Other resets GP15MD 1 0 Function These bits control direction and function of the GPIO15 pin as follows 00 General purpose input 01 CD2 input 10 General purpose output 11 Color LCD FPD7 output GP14MD 1 0 These bits control direction and function of the GPIO14 pin as follows 00 General purpose input 01 CD1 input 10 General purpose output 11 Color LCD FPD6 output GP13MD 1 0 These bits control direction and function of the 13 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 Color LCD FPD5 output GP12MD 1 0 These bits control direction and function of the GPIO12 pin as follows 00 General purpose input 01 RFU 10 General purpose output 11 Color LCD FPD4 output GP11MD 1 0 Note Holds the value before reset These bits control direction and function of the GPIO11 pin as follows 00 General purpose in
410. t L ColdReset Internal L Reset Internal L BATTINH BATTINT Input ch PLL Internal H RTC Internal 32 768 kHz Detection CPU not of activation activated factor Check BATTINH BATTINT pin User s Manual U14272EJ3VOUM 103 CHAPTER 5 INITIALIZATION INTERFACE 5 3 Reset of CPU Core This section describes the reset sequence of the Vn4110 CPU core 5 3 1 Cold Reset In the Vr4181 Cold Reset sequence is executed in the CPU core in the following cases RTC reset RSTSW reset Deadman s Switch reset e Software shutdown e HALTimer shutdown BATTINH shutdown shutdown according to battery state A Cold Reset completely initializes the CPU core except for the following register bits The TS and SR bits of the Status register are cleared to 0 e The ERL and BEV bits of the Status register are set to 1 e The upper limit value 31 is set in the Random register The Wired register is initialized to O The Count register is initialized to 0 Bits 31 to 28 of the Config register are set to 0 and bits 22 to 3 to 0x04800 the other bits are undefined e The values of the other registers are undefined Once power to the processor is established the ColdReset internal and the Reset internal signals are asserted and a Cold Reset is started After approximately 2 ms assertion the ColdReset signal is deasserted synchronously with the rising edge of MasterOut internal Then t
411. t 8 in 7 2 9 MICDMACFGREG 0x0A00 065E 152 Addition of description for bit 0 in 7 2 10 SPKDMACFGREG 0x0A00 0660 153 Addition of description for bits 5 and 4 in 7 2 11 DMAITRQREG 0x0A00 0662 156 Modification of description and addition of Caution in 8 1 Overview 157 Addition of Caution in Figure 8 1 SCK and SI SO Relationship pp 157 158 Addition and modification of descriptions in 8 2 2 SCK phase and CSI transfer timing p 159 Modification of description in 8 2 3 1 Burst mode pp 161 162 Addition of Remarks and description 8 3 1 CSIMODE 0 0 00 0900 p 171 Addition of description in 9 1 Overview p 173 Modification of description in Table 9 1 ICU Registers p 184 Modification of address and description for bits 2 and 1 and addition of description in 9 2 9 0 0 00 0086 186 Modification of R W and addition of description in 9 2 11 MAIUINTREG 0 0 00 0090 p 189 Modification of description in Figure 10 1 Transition of Vn4181 Power Mode pp 190 191 Addition and modification of descriptions in 10 2 1 Power mode and state transition p 191 Modification of description in Table 10 2 Operations During Reset p 192 Modification of location of 10 3 3 Deadman s Switch reset 192 Modification of Figure 10 2 EDO DRAM Signals on RSTSW Reset SDRAM Bit 0 192 Modification of description in 10 3 4 2 Preserving SDRAM data
412. t is 1 the reverse is true Figure 21 3 Position of Load Clock LOCLK Origin Hvisib e 1 0 Htotal 1 0 View rectangle Horizontal blank 0 Vvisible 1 Vertical blank 0 Vtotal 1 Y X 2 LCS x 2 X LCE x 2 LOCLK ll 1st edge 2nd edge Caution The following expression must be satisfied 1 Htotal LCE 7 0 x 2 LCS 7 0 x 2 User s Manual U14272EJ3VOUM 403 CHAPTER 21 LCD CONTROLLER 3 Frame clock The edge positions of the frame clock FLM are also programmable There must be exactly two FLM edges inside the bounding box The first FLM edge is defined by the FLMHS 7 0 bits of the FHSTARTREG register and the FLMS 8 0 bits of the FVSTARTREG register The location of the first edge is at FLMHS x 2 FLMS The second FLM edge is defined by the FLMHE 7 0 bits of the FHENDREG register and the FLME 8 0 bits of the FVENDREG register The location of second edge is at FLMHE x 2 FLME If the FLMPOL bit of the LCDCTRLREG register is 0 the first FLM edge is positive and the second is negative If the FLMPOL bit is 1 the reverse is true Figure 21 4 Position of Frame Clock FLM Origin Hvisib Htotal 1 0 View rectangle Horizontal blank 0 Vvisible 1 0 Vvisible 1 FLMHS x 2 FLMS Vertical blank FLMHE x 2 FLME 1 0 Vtotal 1 1 1 1 1 1 1 1 1 Y 1 1 Y y 1st edge 2nd edge Caution The following e
413. tablishment of inter process synchronization Figure 3 9 Count Register 31 0 Count Up to date count value that is compared with the value of the Compare register 74 User s Manual U14272EJ3VOUM CHAPTER 3 REGISTERS 3 2 9 EntryHi register 10 The EntryHi register is write accessible It is used to access the built in TLB The EntryHi register holds the high order bits of a TLB entry for TLB read and write operations If a TLB Refill TLB Invalid or TLB Modified exception occurs the EntryHi register holds the high order bit of the TLB entry The EntryHi register is also set with the virtual page number VPN2 for a virtual address where an exception occurred and the ASID See Vn4100 Series Architecture User s Manual for details of the TLB exception The ASID is used to read from or write to the ASID field of the TLB entry It is also checked with the ASID of the TLB entry as the ASID of the virtual address during address translation The EntryHi register is accessed by the TLBP TLBWR TLBWI and TLBR instructions The contents of the EntryHi register are undefined after a reset so that it must be initialized by software Figure 3 10 EntryHi Register a 32 bit mode 31 11 10 8 7 0 b 64 bit mode 63 62 61 40 39 11 10 8 7 0 VPN2 Virtual page number divided by two mapping to two pages ASID Address space ID An 8 bit ASID field that allows multiple processes to share the TLB each proces
414. te as 50 ksps or less 308 User s Manual U14272EJ3VOUM CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 7 MIDATREG 0 0 00 0170 Name Reserved Reserved Reserved Reserved Reserved Reserved MIDAT9 MIDAT8 R W RTCRST Other resets RTCRST Other resets Function 15 to 10 Reserved 0 is returned when read 9100 MIDAT 9 0 Microphone input data This register is used to store 10 bit speaker input data that has been converted by the A D converter Data is sent to the MDMADATREG register and is received from the A D converter Write is used for debugging and is enabled when the AIUMEN bit of the SEQREG register is set to 1 This register is initialized 0x0200 by resetting the AIUMEN bit of the SEQREG register to 0 User s Manual U14272EJ3VOUM 309 CHAPTER 15 AUDIO INTERFACE UNIT AIU 15 2 8 MCNTREG 0 0 00 0172 Name ADENAIU Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W RTCRST Other resets RTCRST Other resets ADENAIU Function Enables A D converter operation Vref connection 1 ON 0 OFF Reserved 0 is returned when read MSTATE Indicates microphone operation state 1 Operating 0 Stopped Reserved 0 is returned when read MSTOPEN Microphone input DMA transfer page boundary interrupt 1 Stop DMA request at 1 page boundary 0 Stop DMA request at 2 pag
415. ters The voltage applied to this pin becomes the minimum value for the A D and D A interface signals VDD_OSC 3 3 V Power supply dedicated for the oscillator GND OSC 3 3 V Ground dedicated for the oscillator VDD_LOGIC 2 5 V Ordinary power supply of 2 5 V GND_LOGIC 2 5 V Ordinary ground of 2 5 V VDD_IO 3 3 V Ordinary power supply of 3 3 V GND_IO 3 3 V Ordinary ground of 3 3 V Caution The Vr4181 has two types of power supplies The 3 3 V power supply should be turned on at first Turn on off the 2 5 V power supply depending on the status of the MPOWER pin User s Manual U14272EJ3VOUM 59 CHAPTER 2 PIN FUNCTIONS 2 3 Pin Status in Specific Status 1 3 Signal Name During RTC After RTC Reset After Reset by During Suspend During Reset Deadman s Mode Hibernate Mode Switch or or Shutdown by RSTSW HALTimer ADD 21 0 Hi Z 0 0 Note 1 0 DATA 15 0 Hi Z Hi Z Hi Z Hi Z Hi Z MEMRD Hi Z 1 1 1 Hi Z MEMWR Hi Z 1 1 1 1 SDCS 1 0 RAS 1 0 Hi Z 1 1 1 0 1 0 UDQM UCAS Hi Z 1 1 1 0 quom LDQM LCAS Hi Z 1 1 1 0 1 0 CAS Hi Z 1 1 0 0 SDRAS Hi Z 1 1 0 0 SDCLK Hi Z Run 0 0 0 CLKEN Hi Z 1 1 1 0 SYSDIR Hi Z 0 0 0 0 SYSEN Hi Z 0 0 0 0 IORD GPIO16 Hi Z Hi Z 1 Note 1 Hi Z Note 3 IOWR GPIO17 Hi Z Hi Z 1 Note 1 Hi Z Note 3 IORDY GPIO18 Hi Z Hi Z Note 1 Note 3 IOCS164 GPIO19 Hi Z Hi Z Note 1 Note 3 UBEZ G
416. ther a read or a write of 1 to the CD bit acknowledge cycle which causes the CD bit to be reset to 0 and the RIO signal to go from low level to high If the card status change is routed to any of the IRQ signals the setting of this bit to 1 prevents the IRQ signal from going active as a result of a hardware card detect status change Once the software detects a card detect status change interrupt request from the RIO signal by reading the CDSTCHGREG register it must issue a software card detect change interrupt request so that the card detect change condition generates an active interrupt request on the IRQ signal Users Manual U14272EJ3VOUM 347 CHAPTER 17 COMPACTFLASH CONTROLLER 17 4 20 GLOCTRLREG Index 0x1E Reserved Reserved Reserved Reserved Reserved EXWRBK Reserved Reserved R W 0 Bit Name Function 7to3 Reserved 0 is returned when read 2 EXWRBK Card status change interrupt request acknowledgement 0 Reading of the CDSTCHGREG register Each bit of the register is cleared after read 1 Writing 1 to the CDSTCHGREG register Each bit of the register is cleared after write of 1 1 0 Reserved 0 is returned when read 17 4 24 VOLTSENREG Index Ox1F Reserved Reserved Reserved Reserved Reserved Reserved R R R R R R 0 0 0 0 0 0 Function Reserved 0 is returned when read VS 2 1
417. tion 12 Stop applying 2 5 V power supply when the MPOWER signal becomes low level Caution When entering Hibernate mode set the BEV bit of the Status register in the CPO of the CPU core to 1 to make sure that the vector of the exception handler points the ROM area User s Manual U14272EJ3VOUM 201 CHAPTER 10 POWER MANAGEMENT UNIT PMU 10 6 2 Entering Hibernate mode SDRAM 1 2 lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt gt lt 8 gt lt 9 gt Copy contents of all 2 5 V registers i e DRAM type and configuration ROM type and configuration etc that must be preserved during Hibernate mode into the general purpose registers MISCREG 0 15 in the GIU or into external memory Remark 3 3 V peripheral units PMU GIU LED and RTC 2 5 V peripheral units all peripherals except PMU GIU LED and RTC Stop operations of the DMA controller and LCD controller Copy the codes for the Hibernate mode lt 4 gt through lt 12 gt below beginning at a 16 byte boundary into the cache by using a Fill operation of CACHE instruction and jump to the cached codes Stop all peripheral clocks by writing zero to the CMUCLKMSK register in the MBA Host Bridge Set the BCURFCNTREG register in the MBA Host Bridge to a value that determines refresh interval to maximum to prevent an interruption of a Hibernate mode sequence If burst refreshes are needed set a value that determines the refresh count to every
418. tion When accessing the registers some instructions require consideration of the interval time until the next instruction is executed because there is a delay from when the contents of the register change to when this change is reflected in the CPU operation This time lag is called a hazard For details refer to CHAPTER 23 COPROCESSOR 0 HAZARDS For details about functions of the refer to 4100 Series Architecture User s Manual User s Manual U14272EJ3VOUM 67 Number Register Index CHAPTER 3 REGISTERS Table 3 1 Registers Memory management Description Programmable pointer to TLB array Random Memory management Pseudo random pointer to TLB array read only EntryLoO Memory management Lower half of TLB entry for even VPN EntryLo1 Memory management Lower half of TLB entry for odd VPN Context Exception processing Pointer to kernel virtual PTE in 32 bit mode PageMask Memory management Page size specification Wired Memory management Number of wired TLB entries Reserved for future use BadVAddr Exception processing Virtual address where the most recent error occurred Count Exception processing Timer count 10 EntryHi Memory management Higher half of TLB entry including ASID 11 Exception processing Timer compare value 12 Status Exception processi
419. tline of Interrupt Control Level 2 registers and signals from peripheral units dozepiuint siuint giuint ecuint etimerint rtclong1int Level 1 registers NMIREG SOFTINTREG SYSINT1REG powerint battint KIUINTREG 3 3 MKIUINTREG 3 AIUINTREG 3 MAIUINTREG 6 PIUINTREG 6 MPIUINTREG AND OR AND OR AND OR ledint rtclong2int 4 Dual Stage Synchronizer MSYSINT1REG Icdint dmaint csuint A Dual Stage Synchronizer Y NMI gt Selector eJ T IntO AND OR Inti AND TClock Int2 AND MasterClock 172 User s Manual U14272EJ3VOUM CHAPTER 9 INTERRUPT CONTROL UNIT ICU 9 2 Register Set Physical address Table 9 1 ICU Registers Register symbol Function 0x0A00 0080 R SYSINT1REG Level 1 system register 1 0x0A00 008C R W MSYNT1REG Level 1 mask system register 1 0 0 00 0098 R W NMIREG NMI register 0 0 009A R W SOFTINTREG Software interrupt register 0x0A00 0200 R SYSINT2REG Level 1 system register 2 0x0A00 0206 R W MSYSINT2REG Level 1 mask system register 2 0 0 00 0082 R PIUINTREG Level 2 PIU register 0 0 00 0084 R AIUINTREG Level 2 AIU register 0 0 00 0086 R W KIUINTREG Level 2 KIU register 0x0B00 008E R W MPIUINTREG Level 2
420. to 0 0 00 0260 A D test 0 0 00 025F to 0 0 00 0240 0 0 00 023F to 0 0 00 01 0 Reserved for future use 0x0B00 01DF to 0 0 00 01 0 RTC 2 0 0 00 01BF to 0x0B00 01A0 Reserved for future use 0 0 00 019F to 0 0 00 0180 KIU 0 0 00 017F to 0 0 00 0160 AIU 0x0B00 015F to 0x0B00 0140 Reserved for future use 0x0B00 013F to 0x0B00 0120 PIU 1 0x0B00 011F to 0 0 00 0100 Reserved for future use 0 0 00 to 0x0B00 00 0 DSU 0 0 00 00DF to 0 0 00 00CO RTC 1 0 0 00 00 to 0x0B00 00 0 0 0 00 009F to 0 0 00 0080 ICU 3 0 0 00 007F to 0 0 00 0000 Reserved for future use User s Manual U14272EJ3VOUM CHAPTER 4 MEMORY MANAGEMENT SYSTEM Table 4 5 MBA Bus Space Physical address Internal 0x0A00 O6FF to 0 0 00 0600 DCU 2 0x0AO00 O5FF to 0 0 00 0500 Reserved for future use 0 0 00 04FF to 0 0 00 0400 LCD controller 0x0A00 to 0 0 00 0300 Memory controller 0 0 00 2 to 0 0 00 0220 Reserved for future use 0 0 00 021F to 0x0AO00 0200 ICU 2 0x0AO00 01FF to 0 0 00 00A0 Reserved for future use 0 0 00 009F to 0x0A00 0080 ICU 1 0x0A00 007F to 0 0 00 0050 Reserved for future use 0 0 00 004F to 0 0 00 0020 DCU 1 0 0 00 001F to 0 0 00 0000 MBA Host Bridge 4 2 4 DRAM space The DRAM
421. to 12 Reserved 0 is returned when read 11 10 B1Config 1 0 Bank 1 capacity 00 Bank 1 is not installed 01 16 Mbits 10 64 Mbits 11 Reserved Reserved 0 is returned when read Bstreftype Burst refresh type This bit determines the number of CBR burst refresh cycles executed before entering and exiting self refresh mode 0 8 rows refreshed 1 All rows refreshed BstRefr Burst refresh enable This bit enables or disables burst CBR refresh cycles when entering or exiting self refresh mode 0 Disable CBR burst refresh 1 Enable CBR burst refresh Burst and distributive CBR refresh are mixed if this bit is set to 1 For some kind of DRAMs mix use of burst and distributive CBR refresh may not be allowed EDOAsym EDO DRAM configuration 0 Asymmetrical 16 Mbit EDO DRAM 12 rows by 8 columns 64 Mbit EDO DRAM 13 rows by 9 columns 1 Symmetrical 16 Mbit EDO DRAM 10 rows by 10 columns 64 Mbit EDO DRAM Setting prohibited User s Manual U14272EJ3VOUM 133 CHAPTER 6 BUS CONTROL 2 2 Function Reserved 0 is returned when read BOConfig 1 0 Bank 0 Capacity 00 Bank 0 is not installed 01 16 Mbit 10 64 Mbit 11 Reserved EDO SDRAM DRAM Type 0 EDO DRAM 1 SDRAM This register is used to set DRAM type capacity type organization etc of Bank 0 and Bank 1 Caution When using SDRAMs set the Init bit to 1 to initialize SDRAMs b
422. to Fullspeed mode User s Manual U14272EJ3VOUM 267 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 16 PCSOSTRA 0 0 00 0320 Name PCSOSTRA PCSOSTRA PCSOSTRA PCSOSTRA PCSOSTRA PCSOSTRA 15 14 18 11 R W R W R W R W R W RTCRST Other resets RTCRST Other resets 15100 PCSOSTRA 15 0 Programmable chip select 0 start address These bits determine the starting address for the memory or I O chip select Note Holds the value before reset 13 3 17 PCSOSTPA 0 0 00 0322 Name PCSOSTPA PCSOSTPA PCSOSTPA PCSOSTPA PCSOSTPA PCSOSTPA 15 14 18 11 R W R W R W R W R W RTCRST Other resets Name R W RTCRST Other resets 15100 505 15 0 Programmable chip select 0 stop address These bits determine the ending address for the memory or I O chip select Note Holds the value before reset 268 User s Manual U14272EJ3VOUM CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 3 18 PCSOHIA 0 0 00 0324 Name Reserved Reserved Reserved Reserved PCSOHIA PCSOHIA PCSOHIA PCSOHIA 27 26 25 R W R W R W R W R W RTCRST Other resets PCSOHIA PCSOHIA PCSOHIA PCSOHIA PCSOHIA PCSOHIA PCSOHIA PCSOHIA 23 22 21 20 19 18 17 16 R W R W R W R W R W R W R W R W RTCRST Other resets Function 15 12 Reserved 0 is returned when read 11100 PCSOHIA 27 16 Programmable chip sel
423. to set the RTCLong2 timer count cycle The RTCLong2 timer begins its countdown at the value written to these registers A write operation is valid once values have been written to both registers RTCL2LREG and RTCL2HREG When setting these registers again wait until at least 100 us three cycles of 32 768 kHz clock have elapsed after the first setting Cautions 1 The RTCLong2 timer is stopped when all zeros are written 2 Any combined setting of RTCL2HREG 0x0000 and RTCL2LREG 0x0001 0x0002 0x0003 or 0x0004 is prohibited 226 User s Manual U14272EJ3VOUM CHAPTER 11 REALTIME CLOCK UNIT 11 2 6 RTCLong2 count registers 1 RTCL2CNTLREG 0 0 00 00DC Name RTCL2C15 RTCL2C14 RTCL2C13 RTCL2C12 RTCL2C11 RTCL2C10 RTCL2C9 RTCL2C8 R W R R R R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets Note Note Note Note Note Note Note Note Name R W RTCRST Other resets 15100 Note Continues counting RTCL2C 15 0 RTCLong2 timer bits 15 to 0 User s Manual U14272EJ3VOUM 227 CHAPTER 11 REALTIME CLOCK UNIT 2 RTCL2CNTHREG 0x0B00 00DE Name Reserved Reserved R W RTCRST Other resets RTCRST Other resets Function Reserved 0 is returned when read RTCL2C 23 16 RTCLong2 timer bits 23 to 16 Note Continues counting These registers indicate the RTCLong2 timer s values It coun
424. to specify the format for asynchronous data communication and exchange and to set the divisor latch access register The LCR6 bit is used to send the break status to the receive side s UART When the LCR6 bit 1 the serial output TxD2 is forcibly set to the spacing 0 state The setting of the LCR5 bit becomes valid according to settings in the LCR4 and bits 390 User s Manual U14272EJ3VOUM CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 20 3 9 SIUMC 2 0 0 00 0004 Name Reserved Reserved Reserved R W RTCRST Other resets Function Reserved 0 is returned when read MCR4 Use of diagnostic testing local loopback 1 Enable 0 Disable OUT2 signal internal setting 1 Low level 0 High level OUT signal internal setting 1 Low level 0 High level RTS2 output control 1 Low level 0 High level DTR2 output control 1 Low level 0 High level This register is used to control the interface with a modem or data set or a peripheral device that emulates a modem The settings of the MCR3 and MCR2 bits become valid only when the MCR4A bit is set to 1 enable use of local loopback Local Loopback The local loopback can be used to test the transmit receive data path in SIU2 The following operation local loopback is executed inside the SIU2 when the MCR4 bit 1 The transmit block s serial output TxD2 enters the marking state 1 and the
425. transmit FIFO during FIFO mode Transmit holding register empty 1 Character is transferred to transmit shift register during 16450 mode Transmit FIFO is empty during FIFO mode 0 Character is stored in transmit holding register during 16450 mode Transmit data exists in transmit FIFO during FIFO mode Break interrupt 1 Detected 0 No break Framing error 1 Detected 0 No error Parity error 1 Detected 0 No error Overrun error 1 Detected receive data is overwritten 0 No error Receive data ready 1 Receive data exists in FIFO 0 No receive data in FIFO The CPU uses this register to get information related to data transfers When LSR7 and LSR 4 1 bits are 1 reading this register clears these bits to 0 Caution The LSRO bit receive data ready bit is set before the serial data reception is completed Therefore the LSRO bit may not be cleared if the serial receive data is read from the SIURB 2 register immediately after this bit is set When reading data from the SIURB 2 register wait for the stop bit width time since the LSRO bit is set 392 User s Manual U14272EJ3VOUM CHAPTER 20 SERIAL INTERFACE UNIT 2 5102 LSR7 bit is valid only in FIFO mode and it indicates always 0 16450 mode The value of LSR4 bit becomes 1 when the spacing status 0 of receive data input is held longer than the time required for transmission of one word start bit data bits parity
426. trated in Figure 22 1 Figure 22 1 Example of Connection of PLL Passive Components VDD LOGIC 4181 C1 C2 VDD_PLL A NA GND GND LOGIC Remarks 1 Capacitors C1 and C2 and resistor R are mounted on the printed circuit board 2 Since the value for the components depends upon the application system the optimum values for each system should be decided after repeated experimentation It is essential to isolate the analog power and ground for the PLL circuit VDD PLL GND PLL from the regular power and ground VDD LOGIC GND LOGIC The following values are an example for each component R 100Q C1 2 0 1 uF C2 1 0 uF Since the optimum values for the filter components depend upon the application and the system noise environment these values should be considered as starting points for further experimentation within your specific application In addition the choke inductor L can be considered for use as an alternative to the resistor for use in filtering the power supply 430 User s Manual U14272EJ3VOUM CHAPTER 23 COPROCESSOR 0 HAZARDS The Vn4110 CPU core avoids contention of its internal resources by causing a pipeline interlock in such cases as when the contents of the destination register of an instruction are used as a source in the succeeding instruction Therefore instructions such as NOP must not be inserted between instructions However interlocks do not occur on the ope
427. ts down by a 32 768 kHz clock cycle and begins counting at the value set to the RTCLong2 registers An RTCLong2 interrupt occurs when the timer value reaches 0x00 0001 at which point the timer returns to the start value and continues counting These registers have no buffers for read Therefore an illegal data may be read if the timer value changes during a read operation When using the read value as a data be sure to read the registers twice and check that two read vales are the same 228 User s Manual U14272EJ3VOUM CHAPTER 11 REALTIME CLOCK UNIT 11 2 7 RTC interrupt register 1 RTCINTREG 0 0 00 01DE Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved R W R R R R R R R R RTCRST 0 0 0 0 0 0 0 0 Other resets 0 0 0 0 0 0 0 0 Name Reserved Reserved Reserved Reserved Reserved RTCINTR2 RTCINTR1 RTCINTRO R W R W R W R W RTCRST 0 0 0 Other resets Bit Name Function 15to3 Reserved 0 is returned when read 2 RTCINTR2 RTCLong2 interrupt request Cleared to 0 when 1 is written 1 Occurred 0 Normal 1 RTCINTR1 RTCLongl interrupt request Cleared to 0 when 1 is written 1 Occurred 0 Normal 0 RTCINTRO ElapsedTime interrupt request Cleared to 0 when 1 is written 1 Occurred 0 Normal Note Holds the value before reset This register indicates the occurrences of interrupt requests of RTC User s Manual U14272EJ3VOUM 229
428. turned after a read SpkDsize 1 0 Indicates Speaker channel data size 01 16 bits Values other than above do not appear SpkSrctype Indicates Speaker channel source address type 0 Memory 1 does not appear SpkDestype Indicates Speaker channel destination address type 1 1 0 0 does not appear Reserved 0 is returned after a read SpkLoad DMA auto stop auto load mode setting for Speaker channel 0 Auto stop 1 Auto load When this bit is set to 1 the DCU automatically begins transferring data from the secondary buffer when the primary buffer is empty When this bit is set to 0 the DCU uses the primary buffer only 152 User s Manual U14272EJ3VOUM CHAPTER 7 DMA CONTROL UNIT DCU 7 2 11 DMAITRQREG 0x0A00 0662 Reserved Reserved R W At reset Bit 7 6 5 4 3 2 1 0 Reserved Reserved SpkEOP MicEOP Reserved Reserved Reserved Reserved R W At reset Reserved 0 is returned after a read SpkEOP Speaker channel end of process EOP interrupt status 0 None 1 Speaker channel EOP interrupt pending The interrupt request is cleared when this bit is written to 1 MicEOP Microphone channel EOP interrupt status 0 None 1 Microphone channel EOP interrupt pending The interrupt request is cleared when this bit is written to 1 Reserved 0 is returned after a read Reserved Write 0 when write 0 is returned a
429. us interface The Vn4181 incorporates single bus architecture All external memory and devices are connected to the same 22 bit address bus and 16 bit data bus These external address and data bus are together called the system bus When the external bus operates at a very high speed the DRAM data bus must be isolated from other low speed devices such as ROM array Vn4181 provides two pins SYSEN and SYSDIR to control the data buffers for this isolation The Vn4181 supports the following types of devices connected to the system bus Table 1 2 Devices Supported by System Bus Device Data width ROM flash memory 16 bits only DRAM 16 bits only CompactFlash 8 or 16 bits External 1 8 or 16 bits External memory 8 or 16 bits Six of the external bus interface signals IORD IOWR IORDY 616 MEMCS16 and RESET can be individually defined as general purpose pins or LCD interface pin if they are not needed by external system components User s Manual U14272EJ3VOUM 31 CHAPTER 1 INTRODUCTION 1 3 3 Memory interface The Vn4181 provides control for both ROM flash memory and DRAM Up to four 16 bit ROM flash memory banks may be supported utilizing either 32 Mbit or 64 Mbit single cycle or page mode devices Bank mixing is not supported for ROM flash memory When a system implements less than the maximum 4 banks of ROM flash memory unused ROM chip select pins can be defined as general pu
430. use Register 31 30 29 28 27 16 15 8 7 6 2 1 0 ce 0 Pro 0 J o BD Indicates whether the most recent exception occurred in the branch delay slot 1 In delay slot 0 Normal CE Indicates the coprocessor number in which a Coprocessor Unusable exception occurred This field will remain undefined for as long as no exception occurs IP Indicates whether an interrupt is pending 1 Interrupt pending 0 No interrupt pending IP7 A timer interrupt IP 6 2 Ordinary interrupts 4 0 However Int 4 3 never occurs in the Va4181 IP 1 0 Software interrupts Only these bits cause an interrupt exception when they are set to 1 by means of software Note 1 4 0 are internal signals of the VR4110 CPU core For details about connection to the on chip peripheral units refer to CHAPTER 9 INTERRUPT CONTROL UNIT ICU ExcCode Exception code field refer to Table 3 4 for details 0 Reserved for future use Write 0 in a write operation When this field is read 0 is read User s Manual U14272EJ3VOUM 79 CHAPTER 3 REGISTERS Table 3 4 Cause Register Exception Code Field Exception code Mnemonic Description Interrupt exception TLB Modified exception TLB Refill exception load or fetch TLB Refill exception store Address Error exception load or fetch Address Error exception store Bus Error exception instruction fetch Bus Err
431. ve operations Transmit and receive operations are initiated by an external master to drive the serial clock SCK The characteristics of the protocol are controlled by the CSIMODE register in particular by CKPOL CKMD FRMEN and FRMMD bits CKPOL and CKMD bits control the relationship between data driven on SO and SI and the phase of the serial clock input to SCK FRMEN and FRMMD bits enable and control the FRM input 156 User s Manual U14272EJ3VOUM CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT CSI 8 2 2 SCK phase and CSI transfer timing The external master drives SCK and SI and samples data driven on SO The CSI supports 4 basic operating modes of SCK depending on the settings of CKPOL and CKMD bits These are illustrated in the following figure Figure 8 1 SCK and SI SO Relationship a When CKMD bit 0 SCK input when CKPOL 0 SCK input when CKPOL 1 T gt ECE b When CKMD bit 1 SCK input when CKPOL 0 SCK input when CKPOL 1 COCO en Coe C7 Xd Caution When the CKMD bit is set to 1 the next byte data is output during the latter half of the cycle for the eighth bit of a transmit data This figure illustrates CSI cycles when the FRM input is disabled FRMEN bit 0 or configured to provide direction control FRMEN bit 1 and FRMMD bit 0 When FRMEN bit 1 and FRMMD bit 1 SO is driven as high impedance during a high level in
432. ware must write 1 to DSWCLR bit in the DSUCLRREG register each set time to clear the Deadman s Switch counter for more information refer to CHAPTER 12 DEADMAN S SWITCH UNIT DSU If the Deadman s Switch counter is not cleared within the set time the PMU resets all peripheral units except for RTC GIU and PMU Then the PMU resets Cold Reset the CPU core In addition DMSRST bit in the PMUINTREG register is set to 1 After the CPU core is restarted DMSRST bit must be checked and cleared to 0 by software 10 3 4 Preserving DRAM data on RSTSW reset 1 Preserving EDO DRAM data When an RSTSW reset takes place the PMU activates the CAS RAS pins to generate CBR self refresh request to EDO DRAM Remark There is no burst CBR refresh before and after CBR self refresh by RSTSW reset Figure 10 2 EDO DRAM Signals on RSTSW Reset SDRAM Bit 0 RSTSW Input Obss e CAS Output og RAS 1 0 Output 7727 2 Preserving SDRAM data The SDRAM bit of the PMUINTREG register can be used to preserve the contents of SDRAM connected to the VR4181 during an RSTSW reset When the SDRAM bit is set to 1 the PMU does not reset the memory controller Therefore the memory controller completes current SDRAM access and performs CBR refresh cycle on an RSTSW reset On the other hand when the SDRAM bit is set to 0 the memory controller is reset regardless of accesses under processing and does not perform CBR refre
433. with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as GND Do not ground the capacitor to a ground pattern through which a high current flows e Do not fetch signals from the oscillator 2 Ensure that no load such as wiring capacity is applied to the CLKX2 or RTCX2 pin when inputting an external clock 48 Figure 1 9 shows examples of the incorrect connection circuit of the resonator User s Manual U14272EJ3VOUM CHAPTER 1 INTRODUCTION Figure 1 9 Incorrect Connection Circuits of Resonator a Connection circuit wiring is too long b There is another signal line crossing Note 1 Note 1 Note2 Note c A high fluctuating current flows near a signal line d A current flows over the ground line of the oscillator The potentials of points A B and C change VoD Note 1 Large current e A signal is fetched Note 2 Notes1 CLKX2 RTCX2 2 CLKX1 RTCX1 3 GND OSC User s Manual U14272EJ3VOUM 49 2 2 1 Pin Configuration 160 pin plastic LQFP fine pitch 24 x 24 PIN FUNCTIONS GPIO27 CLKSEL1 28 GPIO26 CLKSELO GP1029 GPIO25 aa 2 gt 2 90 Q n OO
434. x33 p 346 Addition of description in 17 4 17 MEMOFFLnREG Index 0x14 0x1C 0x24 Ox2C 0x34 p 346 Modification of Remark for bits 5 to 0 in 17 4 18 MEMOFFHnREG Index 0x15 0x1D 0x25 0x2D 0x35 p 348 Modification of description for bit 2 in 17 4 20 GLOCTRLREG Index Ox1E p 349 Modification of description for bits 1 and 0 and addition of description in 17 4 22 VOLTSELREG Index Ox2F pp 350 351 Addition of 17 5 Memory Mapping of CompactFlash Card p 352 Addition of 17 6 Controlling Bus When CompactFlash Card Is Used p 356 Addition of function for bit 2 in 18 2 3 LEDCNTREG 0 0 00 0248 p 357 Modification of description in 18 2 4 LEDASTCREG 0 0 00 024A p 359 Modification of figure in 18 3 Operation Flow p 360 Addition of Caution in 19 1 General p 361 Modification of description in Table 19 1 SIU1 Registers pp 362 364 376 Modification of values at reset in 19 3 1 through 19 3 3 19 3 5 and 19 3 12 p 365 Addition of description in Table 19 2 Correspondence between Baud Rates and Divisors p 368 Modification of descriptions for bits 2 to 0 in 19 3 7 SIUFC 1 0 0 00 0012 Write p 373 Modification of R W and addition of description in 19 3 10 SIULS 1 0 0 00 0015 p 375 Modification of descriptions for bits 7 to 4 in 19 3 11 SIUMS 1 0 0 00 0016 p 377 Modification of R W for bit 1 in 19 3 14 SIUACTMSK 1 0 0 00 001C p 379 Addition of description and Caution in 20 1 Gen
435. xpressions must be satisfied 1 Htotal gt FLMHE 7 0 x 2 gt FLMHS 7 0 x 2 2 Vtotal FLME 8 0 Vtotal FLMS 8 0 404 User s Manual U14272EJ3VOUM CHAPTER 21 LCD CONTROLLER 4 Shift clock The shift clock SHCLK edges can be programmed only indirectly The SHCLK is also output in rows of the vertical blank if the DummyL bit of the VRVISIBREG register is 1 The position of SHCLK edges are controlled by the Panelcolor PanDbus bits of the LCDCFGREGO register The SCLKPOL bit of the LCDCTRLREG register determines whether data is latched into the panel on the rising or falling edges If the SCLKPOL bit is 0 data is latched on the falling edges 5 M signal Some panels also need a modulation signal M to operate properly The modulation rate is controlled by MOD 7 0 bits of the LCDCFGREGO register If the MOD field is 0 the M signal toggles once per frame If the MOD field is not 0 then the M signal toggles once every rows set in the MOD field The M signal toggles at the position specified in the LCE field the same time as the second LOCLK edge When the MOD field is 0 the M signal toggles when the LOCLK latches the FLM 6 Vertical retrace interrupt When the LCD controller goes through the vertical blank a status signal bit VIReq of the LCDINRQREG register becomes 1 This signal can be configured to be polled or to generate an interrupt request To enable the interrupt set the MVIReq bit of the LCDIMSKREG register to 1
436. y 1 mapping start address high byte register 0x001A SYSMEMEL1REG System memory 1 mapping stop address low byte register 0x001B MEMSEL1 REG System memory 1 mapping stop address high byte register 0x001C MEMOFFL1REG Card memory 1 offset address low byte register 0x001D MEMOFFH1REG Card memory 1 offset address high byte register 0x001E GLOCTRLREG Global control register 0x001F VOLTSENREG Card voltage sense register User s Manual U14272EJ3VOUM 329 CHAPTER 17 COMPACTFLASH CONTROLLER 0x0020 Table 17 2 ECU Registers 2 2 Register symbol SYSMEMSL2REG Function System memory 2 mapping start address low byte register 0x0021 MEMWID2 REG System memory 2 mapping start address high byte register 0x0022 SYSMEMEL2REG System memory 2 mapping stop address low byte register 0x0023 MEMSEL2 REG System memory 2 mapping stop address high byte register 0x0024 MEMOFFL2REG Card memory 2 offset address low byte register 0x0025 MEMOFFH2REG Card memory 2 offset address high byte register 0x0028 SYSMEMSL3REG System memory 3 mapping start address low byte register 0x0029 MEMWID3_REG System memory 3 mapping start address high byte register 0x002A SYSMEMEL3REG System memory 3 mapping stop address low byte register 0x002B MEMSEL3_REG System memory 3 mapping stop address high byte register 0x002C MEMOFFL3REG
437. ycle Users Manual U14272EJ3VOUM 241 CHAPTER 13 GENERAL PURPOSE I O UNIT GIU 13 2 4 Programmable chip selects The GIU provides two programmable chip select signals PCS 1 0 These chip select signals are available on the following GPIO pins Table 13 10 Programmable Chip Select Signals GPIO pin Programmable chip select GPIO11 PCS1 Output GPIO3 PCSO Output Each programmable chip select signal can be defined individually as memory or l O mapped 8 or 16 bit data width and 1 to 64K bytes of address ranges The chip selects can also be qualified with I O or memory read strobes 13 2 5 16 bit bus cycles The GIU generates two internal outputs gpiocs16 and gpmemcs16 1 to the internal ISA bus to signal the data width of the target of an external ISA cycle The internal ISA bus uses these outputs as the IOCS162 and MEMCS16 signals that are AND ed with the outputs from other internal ISA units The gpiocs16 output is controlled by either a programmable chip select set in the PCSMODE register 0 0 00 032C or IOCS164Z GPIO19 pin When one of the programmable chip selects has been defined as I O mapped and 16 bit data width the gpiocs16 output is asserted while the I O cycle address is within the range specified for the programmable chip select When the IOCS164 GPIO19 pin has been configured as OCS16 the gpiocs16 output follows the state of the IOCS16 signal The gpmemcs16 output is controlled by a progra

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