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V1724 & VX1724 User Manual

1. M M 58 3 13 OPTICAL LINK EE 59 5 POWER ON SEQUENGE a Ea a E E e EE ees Regen 63 3 2 POWER OON AT cta 63 5 3 FIRMWARE ee CN 5 3 1 V1724 Upgrade files description LIST OF FIGURES FIG 1 1 MOD V 1724 BLOCK DIAGRAM intei ete Erro eraso aane e nTa E REEE EE ERES EE EEEE i pre aS EEE Fe eS Yee RAE e 10 FIG 2 1 MOD V1724 FRONT PANEL eire etetete there htt eret here eto eee rue Lee er eed esee ge aeo caacebeesesdbsessssaatecesssns 12 FIG 2 2 MCX CONNECTOR eet SEV NE ERE MENU EE RESERVE EE EEEE EEEE E a 13 FIG 2 3 AMP DIFFERENTIAL CONNECTOR ssesesseeseeeseteesetetttetettttsttssttsstessesetesetesttestesstenstesstessesetesetesesnsteeseesseese 13 FIG 2 4 AMP CLK IN OUT CONNECTOR ssssseseseeeeeeseststrtetttsterettettttstetsrtttnttttntstnstntsttttstatertstateeretenestnreten esenee 14 FIG 2 5 PROGRAMMABLE IN OUT CONNECTOR sssseessesssesseesreeresrtssrtssressetsesetetesestesstesstesstesseseesetesesestessesseee 14 FIG 2 6071EC OPTICAL CONNECTOR Lunner arna an ES eege E 15 FIG 2 7 ROTARY AND DIP SWITCHES LOCATION 18 FIG 3 1 SINGLE ENDED INPUT DIAGRAM sscrirdeiso erronee ee redertEr enei iee neee as aE Ane eA E Sake E E KEEK Ee EENE eaa Ees i eRe 20 FIG 3 2 DIFFERENTIAL INPUT DIAGRAM EEN 20 FIG 3 3 CLOCK DISTRIBUTION DIAGRAM 5 55 ee et epe rese pere e po odeveecednoveashcessnsvbasessanssdentese SEE E KAR E EE 21 FIG 3 4 TRIGGER OVERLAP osorernrrnovne
2. Where n 0 4 8 12 bits n 3 n 0000 bits n 3 n 0001 bits n 3 n 0010 bits n 3 n 0011 IE IE REGISTER TRIGGER NBUSY NVETO OLD STYLE NOTE Whatever option is set the LVDS l Os are always latched with the trigger and the relevant status of the 16 signals is always written into the header s Pattern field see 3 3 3 1 the user can then choose to readout it or not Table 3 3 Features description when LVDS group is configured as INPUT REGISTER TRIGGER nBUSY nVETO OLD STYLE 15 nRunin 15 reserved LVDS IN e 14 nTriggerln 14 reserved 15 12 Peolt5 12 Not available 13 nvetoln 13 reserved 12 nBusyIn 12 nClear_TTT 11 nRunin 11 reserved LVDS IN a 10 nTriggerln 10 reserved 11 8 Regi 11 6 Ke 9 nVetoln 9 reserved 8 nBusyln 8 nClear_TTT 7 nRunin 7 reserved LVDS IN 6 nTriggerln 6 reserved 7 4 Reg 7 4 Vee 5 nVetoln 5 reserved 4 nBusyln 4 nClear TTT 3 nRunin 3 reserved LVDS IN 2 nTriggerln 2 reserved 3 0 Reg 3 0 Nor AVANADE 1 nVetoln 1 reserved 0 nBusyln 0 nClear TTT Table 3 4 Features description when LVDS group is configured as OUTPUT 00103 05 V1724x MUTx 31 REGISTER TRIGGER nBUSY nVETO OLD STYLE 3 nRun 15 Run LVDS OUT ul 2 nTrigger 14 Trigger 15 12 Re9015 12 TrigOut Ch 7 4 4 nveto 13 DataReady 0 nBusy 12 Busy 7
3. Nth 4samples Nth 4samples 3 THRESHOLD CHO IN Nth 4samples Nth 4samples HF THRESHOLD CH1 IN 2 5mV li 25mV MAJORITY NPO Fig 3 19 Majority logic 2 channels over threshold bit 6 of Ch Config Register 0 In this mode the MON output provides a signal whose amplitude is proportional to the number of channels over the trigger threshold The amplitude step 1 channel over threshold is 125mV Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 48 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 7 2 Test Mode Monitor Mode 1 In this mode the MON output provides a sawtooth signal with 1 V amplitude and 24 41kHz frequency 3 7 3 Analog Monitor Inspection Mode Monitor Mode 2 In this mode the MON output provides a signal whose amplitude is proportional to the sum of the board channels The following diagram shows the way the channels data are processed Vref 1V MONL r 11 bit absolute 7 1 bit allia x1 32 x4 x8 Analog Monitor Register Analog Monitor Register Analog Monitor Register INVERT field OFFSET field MAGHIFY field Fig 3 20 Inspection Mode diagram Data converted by channel ADC are brought to the FPGA via a 2 bit BUS Data transfer timing is provided by TRG CLK the availa
4. ADC amp MEMORY CONTROLLER BUFFERS 9 gt o 7 2 E an Re lt x cc ul O C5 9 MER y E LU gt ROC FPGA Readout control VME interface control Optical link control Trigger control External interface control Fig 1 1 Mod V1724 Block Diagram The function of each block will be explained in detail in the subsequent sections NPO Filename Number of pages Page 00103 05 V1724x MUTx 3 I V1724 REV31 DOC 66 10 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 2 Technical specifications 2 1 Packaging and Compliancy 2 1 1 Supported VME Crates The module is housed in a 6U high 1U wide VME unit The board hosts the VME P1 and P2 connectors and fits into both VME VME64 standard and V430 backplanes VX1724 versions fit VME64X compliant crates 2 2 Power requirements The power requirements of the module are as follows Table 2 1 Model V1724 power requirements 5 V 4 50 A 12 V 0 2 A 12V 0 2A NPO Filename Number of pages Page 00103 05 V 1724x MUTx 31 V1724 REV31 DOC 66 11 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 2
5. 0 Ns lt Nirwo lt N5 then the readout event is N s 3 control words 1 size Skip N Good N s No N3 N4 Niewo N o words with samples over threshold Skip Ns Niewo NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 36 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 4 If the algorithm works in positive logic and Ns lt Niek lt N Nirwo 0 Fig 3 12 Example with positive logic and overlapping Ni gx then the readout event is N s N 4 control words 1 size Skip Ny Nigk Good N s Ni gx N2 N s words with samples over threshold Good Na N3 Na N words with samples over threshold Skip Ns NOTE In this case there are two subsequent GOOD intervals 5 If the algorithm works in positive logic and 0 lt Nisx lt N Nirwo lt N5 Niek Nifwo 2 N then the readout event is N gt N 4 4 control words 1 size Skip N Ni oe Good N s Nygk Ne Niewo N 2 words with samples over threshold Good N Ns Nyrwo Na Nyrwo N 4 words with samples over threshold Skip Ns NLewo NOTE In this case there are two subsequent GOOD intervals These examples are reported with positive logic the compression algorithm is the same also working in negative logic NPO Filename Number of page
6. Software relocation of base address 3 11 Data transfer capabilities The board supports D32 single data readout Block Transfer BLT32 and MBLT64 2eVME and 2eSST cycles Sustained readout rate is up to 60 MB s with MBLT64 up to 100 MB s with 2eVME and up to 160 MB s with 2eSST NPO Filename Number of pages Page 00103 05 V 1724x MUTx 31 V1724 REV31 DOC 66 54 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 12 Events readout 3 12 1 Sequential readout NPO The events once written in the SRAMs Memory Event Buffers become available for readout via VME During the memory readout the board can continue to store more events independently from the readout on the free buffers The acquisition process is therefore deadtimeless until the memory becomes full Although the memories are SRAMs VMEBus does not handle directly the addresses but takes them from a FIFO Therefore data are read from the memories sequentially according to the selected Readout Logic from a memory space mapped on 4Kbytes 0x0000 0x0FFC The events are readout sequentially and completely starting from the Header of the first available event followed by the Trigger Time Tag the Event Counter and all the samples of the channels from 0 to 7 Once an event is completed the relevant memory buffer becomes free and ready to be written aga
7. l 225 0120m 223 IE dcboz Fig 2 7 Rotary and dip switches location NPO 00103 05 V1724x MUTx 31 Filename V1724 REV31 DOC Number of pages 66 Page 18 CAEN Q Tools for Discovery Document type User s Manual MUT 2 7 Package Title Mod V1724 8 Channel 14bit 100MS s Digitizer Revision 31 Revision date 11 03 2015 Technical specifications table Table 2 3 Mod V1724 technical specifications 1 unit wide VME 6U module Analog Input 8 channels single ended or differential depending on version 2 25Vpp nominal input range 10Vpp and 500mVpp Single ended on request positive or negative 50 Q nominal input impedance single ended 1 kQ with customized input ranges 40MHz Bandwidth Programmable DAC for Offset Adjust on each channel Single ended versions only Digital Conversion ADC Sampling Clock generation CLK_IN Resolution 14 bit Sampling rate 32 2 MS s to 100 MS s simultaneously on each channel Multi board synchronisation one board can act as clock master The V1724 sampling clock generation supports three operating modes PLL mode internal reference 50 MHz local oscillator PLL mode external reference on CLK_IN Frequency 50MHz 100ppm Other reference frequency values are available in 32 2 100MHz range PLL Bypass mode External clock on CLK_IN drives directly ADC clocks External clock Frequency from
8. 3 Front Panel O Mod V1724 EXTERNAL gt CLOCK IN INTERNAL gt CLOCK OUT LOCAL gt TRIGGER OUT EXTERNAL TRIGGER IN SYNC SAMPLE START ANALOG INPUT ANALOG MONITOR OUTPUT o hd L zi v TT D s DIGITAL Li VO s z e hd 8 CH 14 BIT 100 MS s DIGITIZER Fig 2 1 Mod V1724 front panel NPO Filename Number of pages 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 2 4 External connectors NPO 2 4 1 ANALOG INPUT connectors CHO Fig 2 2 MCX connector Single ended version see options in 1 1 Function Analog input single ended input dynamics 2 25Vpp Zin 50Q Mechanical specifications MCX connector CS 85MCX 50 0 16 SUHNER CHO Fig 2 3 AMP Differential connector Differential version see options in S 1 1 Function Analog input differential input dynamics 2 25Vpp Zin 100Q Mechanical specifications AMP 3 102203 4 AMP MODUII N B absolute max analog input voltage 6Vpp with Vrail max to 6V or 6V for any DAC offset value 2 4 2 CONTROL connectors Function e TRG OUT Local trigger output NIM TTL on Rt 500 e TRG IN External trigger input NIM TTL Zin 500 e SYNC SAMPLE START Sample front panel input NIM TTL Zin 50Q e MON Z DAC output 1Vpp on Rt 500 not available
9. 3 1 Buffer Organization REGISTER BUFFER NUMBER SIZE of one BUFFER samples SRAM 1MB ch 512KS SRAM 8MB ch 4MS 0x00 1 512K 4M 0x01 2 256K 2M 0x02 4 128K IM 0x03 8 64K 512K 0x04 16 32K 256K 0x05 32 16K 128K 0x06 64 8K 64K 0x07 128 4K 32K 0x08 256 2K 16K 0x09 512 IK 8K 0x0A 1024 512 4K An event is therefore composed by the trigger time tag pre and post trigger samples and the event counter Overlap between acquisition windows may occur a new trigger occurs while the board is still storing the samples related to the previous trigger this overlap can be either rejected or accepted programmable via VME If the board is programmed to accept the overlapped triggers as the overlapping trigger arrives the current active buffer is filled up then the samples storage continues on the subsequent one In this case events will not have all the same size see Fig 3 4 Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 25 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 EVENT n j EVENT n 1 EVENT n 2 Recorded Not Recorded TRIGGER PRE POST gt ACQUISITION WINDOW Overlapping Triggers Fig 3 4 Trigger Overlap A trigger can
10. As soon as one buffer is readout and becomes free the board exits the FULL condition and acquisition restarts IMPORTANT NOTICE When the acquisition restarts no trigger is accepted until at least the entire buffer is written This means that the dead time is extended for a certain time depending on the size of the acquisition window after the board exits the FULL condition A way to eliminate this extra dead time is by setting bit 5 1 in the Acquisition Control register The board is so programmed to enter the FULL condition when N 1 buffers are filled no trigger is then accepted but samples writing continues in the last available buffer As soon as one buffer is readout and becomes free the boards exits the FULL condition and can immediately accept a new trigger This way the FULL reflects the BUSY condition of the board i e inability to accept triggers if required the BUSY signal can be provided out on the digitzer front panel through the TRG OUT LEMO connector bits 19 18 and bits 17 16 of Front Panel I O Control register address 0x811C or the LVDS I Os see 3 6 NOTE when bit 5 1 the minimum number of circular buffers to be programmed is N 2 In some cases the BUSY propagation from the digitizer to other parts of the system has some latency and it can happen that one or more triggers occur while the digitizer is already FULL and unable to accept those triggers This condition causes event loss and it is particu
11. CAEN has developed a software tool which allows to handle easily the clock parameters the CAENupgrader see www caen it path Home Products Firmware Software Digitizer Software Configuration Tools CAENUpgrader Filename Number of pages Page 22 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 NPO 3 2 6 PLL programming In CAENUpgrader GUI the User must select the PLL clock mode then select the value of the input clock frequency from the Input Clock menu The VCXO frequency 1GHz ca be also read from the board In case of a desired sampling frequency different from the nominal 100 MHz the ADC Sampling Frequency menu allows to select the permitted values NOTE Changing the ADC sampling frequency only the frequency values in the range 32 2 100 MHz are supported the board cannot be operated at lower frequencies Output Clock selection enables a clock signal to be provided out on CLK OUT connector This setting allows the clock propagation in multi board systems where both the Frequency and a Delay parameter can be set in the software interface in order to perform the clock sinchronization among multiple boards see 3 2 9 3 2 7 Direct Drive programming In Direct Drive BYPASS clock mode the User can directly set the input frequency Input Clock field real
12. DC offset is adjustable via a 16 bit DAC on each channel in the 11 125 V 5 V 250 mV range The module features a front panel clock reference In Out and a PLL for clock synthesis from internal external references The data stream is continuously written in a circular memory buffer When the trigger occurs the FPGA writes further N samples for the post trigger and freezes the buffer that then can be read via VME or Optical Link The acquisition can continue without dead time in a new buffer Each channel has a SRAM memory buffer see Table 1 1 for the available memory sizes divided in buffers of programmable size 1 1024 The readout from VME or Optical link of a frozen buffer is independent from the write operations in the active circular buffer ADC data storage V1724 supports multi board synchronization allowing all ADCs to be synchronized to a common clock source and ensuring Trigger time stamps alignment Once synchronized all data will be aligned and coherent across multiple V1724 boards VME and Optical Link accesses take place on independent paths and are handled by the on board controller therefore when accessed through Optical Link the board can be operated outside the VME Crate see 2 1 The trigger signal can be provided via the front panel input as well as via the software but it can also be generated internally with threshold auto trigger capability The trigger from one board can be propagated to the
13. DESCRIPTION eegene 20 Sack A A OS 20 3 1 1 KOENEN 20 3 1 2 Differential input ccceccccesccesssecesecesscecesecesscecssccesacecseeeeaeecseceeseecseeeeaeecsaeceeaeecaeeeeaeeceaeeeeaeeeneeeees 20 3 2 CLOCK DISTRIBUTION taaan aaa 21 3 2 1 Direret Pre LL c eessen EE SEENEN REE E enge 22 3 2 2 IDE EEE EN EE KNE RR EEA 22 3 2 3 Trigger CLOCK EE 22 3 2 4 QI e CERERI 22 KG OTA 22 3 2 6 RNB 23 3 2 7 Direct Drive programming 23 3 2 8 UI AA afedunssnbeiwedvemszenpeanensesce 23 3 2 9 Multiboard synchronisation eee eee esee eee teinte nennen nennen ener en nennen entren ne enne nennen 23 3 3 ACQUISITI N MODES unne ae ene Eegen 24 SE 24 3 3 2 Acquisition Triggering Samples and Events 25 3 3 2 1 Custom sIze LE 27 3 3 3 VAT PACA To 1T o ET 27 SES SEM MEM o M 27 DBD AMES oiim emisti edam obisdbeu aet e 27 3 3 3 3 Bv nt format examples nonien ee teer ore re ei dre d oie ee de ida edd 28 NPO Filename Number of pages Page 3 V1724 REV31 DOC 66 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 3 4 Acquisition Synchronization Sak ZERO SUPPRESSION unik OM EEN 3 4 1 Zero Suppression Algorithm 3 4 1 1 Full Suppression based on the integral of the stenge 30 3 4 1 2 Full Suppression based on the amplitude of the signal
14. Ns is programmable by the Channel n ZS_NSAMP register address 0x1n28 It is also possible to configure the algorithm with negative logic in this case the data from that channel are discarded if the signal does not remain under the programmed threshold for Ns subsequent data at least Fig 3 6 shows an example of Full Suppression based on the amplitude of the signal the algorithm has positive logic CHO CH3 are enabled for acquisition therefore the Channel Mask field in the Header allows to acknowledge which channel the data are coming from see also 3 3 3 for data format details Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 30 CAEN Q Tools for Discovery Document type Title User s Manual MUT Channel Configuration bits 19 16 0x3 ZS_AMP mode CH Enable Mask OxF Trigger Source Enable Mask bits 31 16 0x4000 Trigger Source Enable Mask bits 15 0 0x0 Channel n ZS_THRES bit 31 0 Channel n ZS_THRES bits 13 0 Threshold Channel n ZS_NSAMP bits 31 0 Ns Threshold Threshold OUTPUT DATA Mod V1724 8 Channel 14bit 100MS s Digitizer pA Thfeshold Threshold e Revision date Revision 11 03 2015 31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1615 14 1211 10 9 NPO 00103 05 V1724x MUTx 31 OHO VIVA Fig 3 6 Zero Suppression based on the a
15. Q Tools for Discovery 00103 05 V1724x MUTx 31 Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 TABLE OF CONTENTS IL GENERAL DESCRIPTION sises scsscsssscscacsseenssseacsssesctasesscesseasssssesesdessecsseetssenesssesadseueesessdeocssesastesasesesssvsesreete 7 E e EEN H 12 BEOCKBDIAGRAM E 10 2 TECHNICAL SPECIFICATIONS svsiscsssctecsssscssscccescassovnsnatvestecsoscassoossnsteceonssenstssovescslassnctoseesvsceesenassonecseess 11 21 PACKAGING AND COMPLIANGY E 11 2 1 1 Supported e 11 2 2 POWER REQUIREMENTS isc 11 2 39 LS IN calle E EE EE ERU R ANE S RE ERE CHUEE EES 12 2 44 EXTERNAL CONNECTORS eesceest aste eser xe Eee R eben EUN ede ee aee Ee EE RS Eee pe Ee ee ERE EU ges e Fee LE NER Saee euge Pene 13 2 4 1 ANALOG INPUT connectors eie eed AEN 13 2 4 2 CONTROL EIERE 13 2 4 3 ADC REFERENCE CLOCK connectors eese sees eene eese nein nn nn nest en eate ipi ieie 14 2 4 4 Digital VO CONNCCIONS ici m 14 2 4 5 Optical LINK CONNECT A aaret sei AA 15 2 5 OTHER FRONT PANEL COMPONENTS ssseseeeeeeeseteteeeetttttttssrtsstessresttsetetetnttrnsttnsttsstenteneteneteneeeneeeneeesreee 16 KG EE Jn C 16 2 6 SEN EG OG 10 WP S 17 St TECHNICAL SPECIFICATIONS TABLE 5 2 tees yet eto r orte Seege sr neon diene 19 3 FUNCTIONAL
16. Run signal The Run signal is active high and represents the inverse of the nRun signal see 3 6 3 4 Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 47 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 7 Analog Monitor The board houses a 12bit 100MHz DAC with 0 1 V dynamics on a 50 Ohm load see Fig 1 1 whose input is controlled by the ROC FPGA and the signal output driving 50 Ohm is available on the MON 2 output connector MON output of more boards can be summed by an external Linear Fan In This output is delivered by a 12 bit DAC The DAC control logic implements five operating modes Trigger Majority Mode Monitor Mode 0 Test Mode Monitor Mode 1 Analog Monitor Inspection Mode Monitor Mode 2 Buffer Occupancy Mode Monitor Mode 3 Voltage Level Mode Monitor Mode 4 Operating mode is selected via Monitor Mode register NOTE this feature is not available on the Mod V1724LC 3 7 1 Trigger Majority Mode Monitor Mode 0 It is possible to generate a Majority signal with the DAC a voltage signal whose amplitude is proportional to the number of channels under over threshold 1 step 125mV this allows via an external discriminator to produce a global trigger signal as the number of triggering channels has exceeded a particular threshold
17. VX2718 VME PCI Bridge WK2718LCXAAA WK2718XAAAAA NPO Filename Number of pages Page 00103 05 V 1724x MUTx 31 V1724 REV31 DOC 66 8 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 VX2718KIT VME PCI Bridge VX2718 PCI OpticalLink A2818 WKX2718XAAAA optical Fibre 5m duplex AY2705 VX2718KITB VME PCI Bridge VX2718 PCle Optical Link A3818A WKX2718XBAAA optical Fibre 5m duplex AY2705 EE See SE PCI Optical Link A2818 WA317XAAAAAA A317 Clock Distribution Cabl WAI2730XAAAA A12730 Optical Fibre 30 m simplex WAI2720XAAAA DEE Optical Fibre 20 m simplex WAI2705XAAAA A12705 Optical Fibre 5 m simplex WAI2703XAAAA DESS Optical Fibre 30cm simplex WAY2730XAAAA AY2730 Optical Fibre 30 m duplex WAY2720XAAAA AY2720 Optical Fibre 20 m duplex WAY2705XAAAA AY2705 Optical Fibre 5 m duplex PP NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 9 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 1 2 Block Diagram FRONT PANEL x8 channels AMC FPGA
18. Z Analog Monitor ENABLE 0xFF gt MON Output dec voltage V CHO CH1 CH2 CH3 CH4 CH5 CHE CH7 CHO CH1 CH2 CH3 CH4 CH5 CH6 CH7 MAGNIFY 0 x1 OFFSET 0 2048 1 CHO CH1 CH2 CH3 CH4 CH5 CH6 CH7 MAGNIFY 1 x2 OFFSET 0 1792 0 875 CHO CH1 CH2 CH3 CH4 CH5 CH6 CH7 MAGNIFY 3 x8 OFFSET 0xB80 896 1536 0 750 1280 0 625 1024 0 500 e 4 768 0 375 analog digital 512 0 250 displacement dac above ground displacement 437 5 mV 896 steps 256 0 125 0 0 Time Fig 3 22 Example of Magnify and Offset parameters use on single channel The assumption is an input signal on CHO using th whole dynamics and all channels participating to Analog Monitor The ADC on the mezzanine produces data in the 0 16383 range 14 bit All channels have O offset and therefore the ADC converted value is 8192 The triangular waveform is shown as example The FPGA AMC of channel 0 sends the 8 MSB to FPGA ROC with a 25 Mhz rate one sample out of four If no output is added and MAGNIFY factor 1x the DAC produces a copy of the signal on channel 0 with 125 mV dynamics 1 8 of DAC dynamics and 500 mV average value If a larger dynamics is desired it is necessary to modify OFFSET and MAGNIFY factor in order to avoid saturation it is necessary to subtract to the channel sum a value equal to the minimum of the channel sum displacement 3 7 4 Buffer Occupancy Mode Monitor Mode 3 In this mode MON out provides
19. nRun 11 Run LVDS OUT em 6 nTrigger 10 Trigger 11 8 Reg 11 8 TrigOut_Ch 3 0 5 nVeto 9 DataReady 4 nBusy 8 Busy 11 nRun 7 Run LVDS OUT i 411 10 nTrigger 6 Trigger 7 4 Reg 7 4 TrigOut_Ch 7 4 9 nVeto 5 DataReady 8 nBusy 4 Busy 15 nRun 3 Run LVDS OUT en 14 nTrigger 2 Trigger 3 0 Reg 3 0 TrigOut_Ch 3 0 13 nVeto 1 DataReady 12 nBusy 0 Busy Filename Number of pages Page V1724_REV31 DOC 66 45 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 6 1 Mode 0 REGISTER Direction is INPUT the logic level of the LVDS I O signals can be read through the Front Panel I O Data register address 0x8118 Direction is OUTPUT the logic level of the LVDS I O signals can be written through the Front Panel I O Data register address 0x8118 3 6 2 Mode 1 TRIGGER Direction is INPUT Not available Direction is OUTPUT the TrgOut_Gr n 3 n signals n 0 4 consist of the local channel triggers coming directly from the mezzanines 3 6 3 Mode 2 nBUSY nVETO 3 6 3 1 nBusy signal nBusyln INPUT is an active low signal which if enabled is used to generate the nBusy signal OUTPUT as below The Busy signal fed out on LVDS I Os or TRG OUT LEMO connector is Almost Full OR LVDS Busyln AND Busyln_enable where A Almost Full indicates the filling of the Buffer Memory up to a programmab
20. other boards through the front panel TRG OUT An Analog Output allows to reproduce a Majority signal a Test signal a Buffer Occupancy signal an Analog Inspection function and a programmable Voltage Level The Modules VME interface is VME64X compliant and the data readout can be performed in Single Data Transfer D32 32 64 bit Block Transfer BLT MBLT 2eVME 2eSST and 32 64 bit Chained Block Transfer CBLT The built in daisy chainable Optical Link is able to transfer data at 80 MB s thus it is possible to connect up to eight V1724 64 ADC channels or thirty two 256 ADC Filename Number of pages Page 7 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 channels to a single Optical Link Controller Mod A2818 A3818 see Table 1 1 CAEN provides also for this model a Digital Pulse Processing firmware for Physics Applications This feature allows to perform on line processing on detector signal directly digitized V1724 is well suited for data acquisition and processing of signals from Charge Sensitive Preamplifiers or photomultiplier and implement a digital replacement of Shaping Amplifier and Peak Sensing ADC Multi Channel Analyzer NOTE The Mod V1724LC a simplified version of the Mod V1724 without Optical Link and Analog Monitor features is dismissed Table 1 1 Av
21. this case the global trigger is issued if at least two of the enabled local channel auto triggers are in coincidence within 1 clock cycle NOTE a practical example of making coincidences with the digitizer in the standard operating is detailed in the document GD2817 How to make coincidences with CAEN digitizers web available NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 42 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 5 4 Trigger distribution The OR of all the enabled trigger sources after being synchronised with the internal clock becomes the global trigger of the board and is fed in parallel to all the channels which store an event A Trigger Out is also generated on the relevant front panel TRG_OUT connector NIM or TTL and allows to extend the trigger signal to other boards For example in order to start the acquisition on all the channels in the crate as one of the channels ramps over threshold the Local Trigger must be enabled as Trigger Out the Trigger Out must then be fed to a Fan Out unit the obtained signal has to be fed to the External Trigger Input of all the boards in the crate including the board which generated the Trigger Out signal CLOCK REF CLOCK DISTRIB SYNC S_IN TRIGGER External of generated Progr Phase shift Simultaneous start of run Common
22. to all by a master board and time reference channels OPTICAL LINK Readout and or control 80MB s up to 3 boards ANALOG OU B om PCI TRIGGER LOGIC The V1495 ANALOG OUTPUT Linear Sum Majority TRIGGER SUS Coincidence matrix ADCs data stream Fig 3 18 Trigger integration NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 43 CAEN Tools for Discover y Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 6 Front Panel l Os The V1724 is provided with 16 general purpose programmable LVDS I O signals see 2 4 4 From the ROC FPGA firmware revision 3 8 on a more flexible configuration management has been introduced which allows these signals to be programmed in terms of direction INPUT OUTPUT and functionality by groups of 4 IN ORDER TO KEEP THE COMPATIBILITY WITH FIRMWARE REVISIONS LOWER THAN 3 8 ALL PREVIOUS CONFIGURATIONS ARE STILL AVAILABLE IN THE FIRMWARE SEE 3 6 4 SINCE THIS COULD BE NO LONGER GUARANTEED IN THE FUTURE THE USER IS HEARTLY RECOMMENDED TO TAKE THE NEW CONFIGURATION MANAGEMENT AS REFERENCE NPO The direction of the signals are set by the bits 5 2 in the Front Panel I O Control register address 0x811C Bit 2 gt LVDS 1 0 3 0 Bit 3 gt LVDS 1 0 7 4 Bit 4 gt LVDS 1 0 11 8 Bit 5 gt LVDS 1 0 15 12 Where setting the bit
23. upload different firmware versions on CAEN boards to upgrade the VME digitizers PLL to get board information and to manage the firmware license CAENUpgrader requires the installation of 2 CAEN libraries CAENComm CAENVMELib and Java SE6 or later CAENComm allows CAENUpgrader to access target boards via USB or via CAEN proprietary CONET optical link CAEN Upgrader GUI Upgrade CAEN Front End Hardware Jo rs CAEN n Electronic Instrumentation IS About E Bridge Upgrade Available actions Connection Type Config Options o Standard Page 3 Backup Page Board Model Le LINK number S L B Skip Verify Firmware binary file I2 Browse VME Base Address Ox 0 cvUpgrade Ready Fig 4 4 CAENUpgrader Graphical User Interface DPP Control Software is an application that manages the acquisition in the digitizers which have DPP firmware installed on it The program is made of different parts there is a GUI whose purpose is to set all the parameters for the DPP and for the acquisition the GUI generates a textual configuration file that contains all the parameters This file is read by the Acquisition Engine DPPrunner which is a C console application that programs the digitizer according to the parameters starts the acquisition and manage the data readout The data that can be waveforms time stamps energies or other quantities of interest can be saved to output files or plotted using gnuplot as an
24. values are allowed Given an input frequency it is possible to set the parameters in order to provide the required signals 3 2 8 Configuration file Once all parameters are set the tool allows to save the configuration file which includes all the AD9510 device settings see CAENupgrader documentation lt is also possible to browse and load into the AD9510 device a pre existing configuration file see CAENupgrader documentation For this purpose it is not necessary the board power cycle 3 2 9 Multiboard synchronisation In cases when multi board systems are involved in an experiment it is necessary to synchronize different boards In this way the user can acquire from N boards with Y channel each like if they were just one board with N x Y channels The main issue in the synchronization of a multi board system is to propagate the sampling clock among the boards This is made through input output daisy chain connections among the digitizers One board has to be chosen to be the master board that propagates its own clock to the others A programmable phase shift can adjust possible delays in the clock propagation This allows to have both the same ADC sampling clock and the same time reference for all boards Having the same time reference means that the acquisition starts stops at the same time and that the time stamps of different boards is aligned to the same absolute time There are several ways to implement the trigger log
25. 24 are all the boards the file is compliant to DT5724 N6724 V1724 VX1724 e X Y is the major minor revision number of the mainboard FPGA e W Zis the major minor revision number of the channel FPGA WARNING in case of programming failures that compromise the communication with the board a first recovering attempt can be performed by setting the SW1 switch on the mainboard in the BKP position If the communication is retrieved when the board is powered on in backup mode the standard page of the FLASH can be then reprogrammed If the problem still remains please contact CAEN technical support see 6 for further instructions Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 65 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 6 Technical support CAEN makes available the technical support of its specialists at the e mail addresses below support nuclear caen it for questions about the hardware support computing caen it for questions about software and libraries NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 66
26. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10918 7 66 1543 2110 Channel Mask 0x5 OHO V LVG Fig 3 7 Zero Length Encoding samples storage NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 33 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 4 2 Zero Suppression Examples If the input signal is the following Fig 3 8 Zero Suppression example If the algorithm works in positive logic and Nigk lt Ni Nirwo lt Ns Ne Nuirwo lt N3 Hex N LBK Fig 3 9 Example with positive logic and non overlapping Ni sx Nurwp then the readout event is N s N 4 5 control words 1 size Skip Ny Nigk Good N s Niek Neo Nyrwo N s words with samples over threshold Skip Ns Nyrwo Ne Good N s Nigk Na Niewp N 4 words with samples over threshold Skip Ns Nirwp NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 34 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 NPO If the algorithm works in negative logic and Niek Nifwo lt No Niek Nyrwo lt Na Nirwo Nek Fig 3 10 Examp
27. 3 Optical Link NPO The board houses a daisy chainable Optical Link communication path which uses optical fiber cables as physical transmission line able to transfer data at 80 MB s therefore it is possible to connect up to eight V1724 to a single Optical Link Controller by using the A2818 PCI card or up to thirty two V1724 with the A3818 PCle card for more information see www caen it path Products Front End PCI PCle Optical Controller The parameters for read write accesses via optical link are the same used by VME cycles Address Modifier Base Address data Width etc wrong parameter settings cause Bus Error VME Control Register bit 3 allows to enable the module to broadcast an interrupt request on the Optical Link the enabled Optical Link Controllers propagate the interrupt on the PCI bus as a request from the Optical Link is sensed VME and Optical Link accesses take place on independent paths and are handled by board internal controller with VME having higher priority anyway it is better to avoid accessing the board via VME and Optical Link simultaneously Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 59 CAEN Tools for Discovery Document type User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 Title Revision date Revision 4 Software tools NPO CONET2 Optical Link Fig 4 1 Block diagram of the software layers CAEN provides d
28. 32 2 to 100MHz AC coupled differential input clock LVDS ECL PECL LVPECL CML CLK_OUT Memory Buffer Trigger Trigger Time Stamp DC coupled differential LVDS output clock locked to ADC sampling clock Frequency values in 32 2 100MHz range are available 512k sample ch or 4M sample ch see Table 1 1 Multi Event Buffer with independent read and write access Programmable event size and pre post trigger Divisible into 1 1024 buffers Common External TRGIN NIM or TTL and VME Command Individual channel autotrigger time over under threshold TRGOUT NIM or TTL for the trigger propagation to other V1724 boards 31 bit counter 20ns resolution 21s range AMC FPGA Optical Link One Altera Cyclone EP1C4 or EP1C20 per channel see Table 1 1 Data readout and slow control with transfer rate up to 80 MB s to be used instead of VME bus Daisy chainable A2818 PCI and A3818 PCle cards can control and read respectively up to eight and thirty two V1724 boards in a chain not available on Mod V1724LC VME interface VME64X compliant D32 BLT32 MBLT64 CBLT32 64 2eVME 2eSST Multi Cast Cycles Transfer rate 60MB s MBLT64 100MB s 2eVME 160MB s 2eSST Sequential and random access to the data of the Multi Event Buffer The Chained readout allows to read one event from all the boards in a VME crate with a BLT access Upgrade Software V1724 firmware can be upgraded via VME Gen
29. 41 FIG 3 17 LOCAL TRIGGER RELATIONSHIP WITH MAJORITY LEVEL I AND TT VAW st 42 FIG 3 18 TRIGGER INTEGRATION ee ee aa 43 FIG 3 19 MAJORITY LOGIC 2 CHANNELS OVER THRESHOLD BIT 6 OF CH CONFIG REGISTER 0 48 FIG 3 20 INSPECTION MODE DIAGRAM ssssssssessseeeseterertetsstretssreesesttrttrtessrtetsstresettertetetsstrtessreeresteetereessreetssereeee 49 FIG 3 21 EXAMPLE OF MAGNIFY PARAMETER USE ON SINGLE CHANNEL 50 FIG 3 22 EXAMPLE OF MAGNIFY AND OFFSET PARAMETERS USE ON SINGLE CHANNEL eere 51 FIG 3 23 A24 ADDRESSING cccsesceceessececesscececsaceecsesaececsecaececeeeceesaeeeceesaeeecsaeeecsesueeecsesaececseaeeseeaeeecseaeeessesaeenees 53 FIG 3 24 A32 ADDRESSING EE EE 53 FIG 3 25 CR CSR ADDRESSING cui EEN ae aea EE REENEN AE E EES 54 FIG 3 26 SOFTWARE RELOCATION OF BASE ADDRESS 54 FIG 3 27 EXAMPLE OF BLT READOUT ccscccessssceceeseeecsscaececsneeecsesaeeeceesaeeeceaeeecseaueeecseaaececseaeesesaeeecseaeeeeseaaeeeees 56 FIG 3 28 EXAMPLE OF RANDOM RBRADOUT tettre tettette test t tettet tt ttes Strt essee restre tereesereeee sereen 57 FIG 4 1 BLOCK DIAGRAM OF THE SOFTWARE LAYERS cesses enne eene enne enter seen rennen nennen nennen nnne 60 FIG 4 2 WAVEDUMP OUTPUT WANVEPORMS 61 FIG 4 3 CAENSCOPE OSCILLOSCOPE TAB ocooccccoconnncnononnncnnonnnnnnnnnnncnnn nn enne nn seen th nr tettette tE Etes se ente rr sene nn eren nens entr serete 61 FIG 4 4 CAENUPGRADER GRAPHICAL USER INTER
30. 5V with 10Vpp or 0 25V with 0 5Vpp customized dynamics in order to preserve the full dynamic range also with unipolar positive or negative input signals The input bandwidth ranges from DC to 40 MHz with 2 order linear phase anti aliasing low pass filter AH Input Dynamic Range 1 Vpp MCX Positive Unipolar Input AW WW 1467 2 25 DAC FSR ll 500 ww aw I 1 125 ITT Vref FPGA 0 B L cu 1 125 2 25 Negative Unipolar i DAC 0 Bipolar DAC FSR 2 Fig 3 1 Single ended input diagram 3 1 2 Differential input Input dynamics is 1 125V Zdiff 100 Q The input bandwidth ranges from DC to 40 MHz with 2 order linear phase anti aliasing low pass filter Differential Mode B T d M NNV MT Input E za gu pe am T 14 bit MODUM LAM Se FPGA T DAC Fig 3 2 Differential input diagram NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 20 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 2 Clock Distribution egeesgteebegr egregegege ee Je wm MEZZANINES x4 nav 2 ov highar only for PCB Pac E uon L mE E Acquisition H B amp Memory Control Local Bus Interface Fig 3 3 Clock distribution diagram The module clock distribution take
31. 724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 7 3 2 Applications examples These examples show the effect of the channel offset magnify parameters over MON output Single channel amplified on 0 1 V dynamics DAC MONI dec voltage V Analog Monitor ENABLE 0x01 gt MON Output CHO S 1536 CHO Full Scale signal MAGNIFY 0 x1 OFFSET 0 CHO Full Scale signal MAGNIFY 1 x2 OFFSET 0 CHO Full Scale signal MAGNIFY 2 x4 OFFSET 0 _____CHO0 Full Scale signal MAGNIFY 3 x8 OFFSET 0 1280 1024 768 512 256 Time Fig 3 21 Example of Magnify parameter use on single channel The assumption is an input signal on CHO using the whole dynamics Only such channel is enabled for Analog Monitor the triangular waveform is just as example FPGA AMC of CHO sends 8MSB to FPGA ROC with 25 Mhz rate one sample out of four If no output is added and MAGNIFY factor 1x the DAC produces a copy of the signal on channel 0 with 0 125 mV dynamics 1 8 of DAC dynamics If a larger dynamics is desired it is necessary increase MAGNIFY factor with MAGNIFY 8x one channel covers all the DAC available dynamics NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 50 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 Channel sum with maximum dynamics DAC MON
32. FACE eese eene enne enne rennen nennen nennen nennen na 62 FIG 4 5 DPP CONTROL SOFTWARE GRAPHICAL USER INTERFACE AND ENERGY PLOT 62 LIST OF TABLES TABLE 1 1 AVAILABLE MODELS RELATED PRODUCTS AND ACCRSSORIES 8 TABLE 2 1 MODEL V 1724 POWER RBEOUIREMENTS 11 TABLE 2 2 FRONT PANEL LEDS eessen DOEN Eed CARA RR deed 16 TABLE 2 3 MOD V1724 TECHNICAL SPECIFICATIONS enne nnne rennen entere en rennen nennen inneren rennen ni 19 TABLE 3 1 BUFFER ORGANIZATION seser ran 15530 pear EEEE EEE pe ukes bedere eir ue eus mms a e pU bad eas sa resa EHS 25 TABLE 3 2 FRONT PANEL LVDS I OS DEFAULT SETTINO enne enne enne en rennen nennen nenne innen enne 44 TABLE 3 3 FEATURES DESCRIPTION WHEN LVDS GROUP IS CONFIGURED AS INPUTT esee 45 TABLE 3 4 FEATURES DESCRIPTION WHEN LVDS GROUP IS CONFIGURED AS OUTRUT eee 45 NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 6 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 1 General description 1 1 NPO Overview The Mod V1724 is a 1 unit wide VME 6U module housing a 8 Channel 14 bit 100 MS s Flash ADC Waveform Digitizer with 2 25 Vpp dynamic range on single ended MCX coaxial connectors Versions featuring differential inputs as well as customizations of 10 Vpp and 500 mVpp input range are also available see Table 1 1 For single ended versions the
33. MPLE 3 CH 7 00 SAMPLE 2 CH 7 5 gt eee O 3 ojo SAMPLE N 1 CH 7 ofo SAMPLE N 2 CH 7 ZERO LENGHT ENCODING enabled 31f80 29 pa 27 pe 5 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o SIZE CONTROL WORD 4 ofo SAMPLE 1 CH 1 0 0 SAMPLE 0 CH 1 S ooo O CONTROL WORD ES 0 0 SAMPLE N 1 CH 1 0 0 SAMPLE N 2 CH 1 le H KA SIZE CONTROL WORD z ojo SAMPLE 1 CH 7 0 0 SAMPLE 0 CH 7 SENS 5 CONTROL WORD m 0 0 SAMPLE N 1 CH 7 0 0 SAMPLE N 2 CH 7 Fig 3 5 Event Organization NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 28 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 3 4 Acquisition Synchronization NPO Each channel of the digitizer is provided with a SRAM memory that can be organized in a programmable number N of circular buffers N 1 1024 see Table 3 1 When the trigger occurs the FPGA writes further a programmable number of samples for the post trigger and freezes the buffer so that the stored data can be read via VME or Optical Link The acquisition can continue without dead time in a new buffer When all buffers are filled the board is considered FULL no trigger is accepted and the acquisition stops i e the samples coming from the ADC are not written into the memory so they are lost
34. Technical Information Manual Revision n 31 11 March 2015 MOD V1724 8 CHANNEL 14 BIT 100 MS S DIGITIZER MANUAL REV 31 NPO 00103 05 V1724x MUTx 31 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation LE CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products MADE IN ITALY We stress the fact that all the boards are made in Italy because in this globalized world where getting the lowest possible price for products sometimes translates into poor pay and working conditions for the people who make them at least you know that who made your board was reasonably paid and worked in a safe environment this obviously applies only to the boards marked MADE IN ITALY we can not attest to the manufacturing process of third party boards CAEN
35. The Stop acquisition must be SW controlled i e reset of bit 2 LVDS I Os CONTROLLED this mode acts like the GIN CONTROLLED bits 1 0 01 but using the configurable features of the signals on the LVDS l Os connector see 3 6 Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 24 CAEN Q Tools for Discovery Document type User s Manual MUT NPO Title Revision date Revision Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 Acquisition Triggering Samples and Events When the acquisition is running a trigger signal allows to store a 31 bit counter vaule of the Trigger Time Tag TTT The counter representing a time reference like so the Trigger Logic Unit see 3 2 operates at a frequency of 100 MHz i e 10 ns that is to say 1 ADC clock cycle Due to the way the acquired data are written into the board internal memory i e in 4 sample bunches the TTT counter is read every 2 trigger logic clock cycles which means the trigger time stamp resolution results in 20 ns i e 50 MHz Basing on that the LSB of the TTT is always 0 increment the EVENT COUNTER fill the active buffer with the pre post trigger samples whose number is programmable via Post Trigger Setting register the Acquisition window width is determined via Buffer Organization 0x800C register setting then the buffer is frozen for readout purposes while acquisition continues on another buffer Table
36. a voltage value proportional to the number of buffers filled with events step 1 buffer 0 976 mV This mode allows to test the readout efficiency in fact if the average event readout throughput is as fast as trigger rate then MON out value remains constant otherwise if MON out value grows in time this means that readout rate is slower than trigger rate 3 7 5 Voltage Level Mode Monitor Mode 4 In this mode MON out provides a voltage value programmable via the N parameter written in the SET MONITOR DAC register with Vmon 1 4096 N Volt NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 51 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 8 Test pattern generator The FPGA AMC can emulate the ADC and write into memory a ramp 0 1 2 3 3FFF 3FFF 3FFE 0 for test purposes It can be enabled via Channel Configuration register 3 9 Reset Clear and Default Configuration NPO 3 9 1 Global Reset Global Reset is performed at Power ON of the module or via a VME RESET SYS_RES It allows to clear the data off the Output Buffer the event counter and performs a FPGAs global reset which restores the FPGAs to the default configuration It initialises all counters to their initial state and clears all detected error conditions 3 9 2 Memory Reset The Memory Reset clea
37. ailable models related products and accessories Description WV1724XAAAAA vi 724 8 Ch 14 bit 100 MS s Digitizer 512KS ch C4 SE WV1724BXAAAA V1724B 8 Ch 14 bit 100 MS s Digitizer 4MS ch C4 SE WV1724CXAAAA vi 724C 8 Ch 14 bit 100 MS s Digitizer 512KS ch C4 DIFF WV1724DXAAAA V1724D 8 Ch 14 bit 100 MS s Digitizer 4MS ch C4 DIFF WV1724EXAAAA vi 724E 8 Ch 14 bit 100 MS s Digitizer 4MS ch C20 SE WV1724FXAAAA V1724F 8 Ch 14 bit 100 MS s Digitizer 4MS ch C20 DIFF WV1724GXAAAA V1724G 8 Ch 14 bit 100 MS s Digitizer 512KS ch C20 SE WVX1724XAAAA VX1724 8 Ch 14 bit 100 MS s Digitizer 512KS ch C4 SE WA659XAAAAAA A659 Single Channel MCX to BNC Cable Adapter WA659K4AAAAA A659 KIT4 4 MCX TO BNC Cable Adapter WA659K8AAAAA A659 KIT8 8 MCX TO BNC Cable Adapter WV1718XAAAAA v1718 VME USB 2 0 Bridge WV1718LCXAAA V1718LC VME USB 2 0 Bridge Rohs Compliant WVX1718XAAAA VX1718 VME USB 2 0 Bridge WVX1718LCXAA VX1718LC VME USB 2 0 Bridge WV2718XAAAAA v2718 VME PCI Bridge WV2718LCXAAA V2718LC VME PCI Bridge Rohs compliant V2718KITLC VME PCI Bridge V2718 PCI Optical Link A2818 Optical Fibre 5m duplex AY2705 Rohs V2718KIT VME PCI Bridge V2718 PCI OpticalLink A2818 Optical Fibre 5m duplex AY2705 V2718KITB VME PCI Bridge V2718 PCle Optical Link A3818A WK2718XBAAAA optical Fibre 5m duplex AY2705 WVX2718LCXAA VX2718LC VME PCI Bridge WVX2718XAAAA
38. ary toverify that the used VME crate supports such cycles Several contiguous boards in order to be daisy chained must be configured as first intermediate or last via MCST Base Address and Control Register A common Base Address is then defined via the same register when a BLT cycle is executed at the address CBLT Base 0x0000 OxOFFC the first board starts to transfer its data driving DTACK properly once the transfer is completed the token is passed to the second board via the IACKIN IACKOUT lines of the crate and so on until the last board which completes the data transfer and asserts BERR which has to be enabled the Master then ends the cycle and the slave boards are rearmed for a new acquisition If the size of the BLT cycle is smaller than the events size the board which has the token waits for another BLT cycle to begin from the point where the previous cycle has ended 3 12 2 Random readout to be implemented Events can be readout partially not necessarily starting from the first available and are not erased from the memories unless a command is performed In order to perform the random readout it is necessary to execute an Event Block Request via VME Indicating the event to be read page number 12 bit datum the offset of the first word to be read inside the event 12 bit datum and the number of words to be read size 10 bit datum At this point the data space can be read starting fr
39. be refused for the following causes acquisition is not active memory is FULL and therefore there are no available buffers the required number of samples for building the pre trigger of the event is not reached yet this happens typically as the trigger occurs too early either with respect to the RUN ACQUISITION command see 3 3 1 or with respect to a buffer emptying after a MEMORY FULL status the trigger overlaps the previous one and the board is not enabled for accepting overlapped triggers As a trigger is refused the current buffer is not frozen and the acquisition continues writing on it The Event Counter can be programmed in order to be either incremented or not If this function is enabled the Event Counter value identifies the number of the triggers sent but the event number sequence is lost if the function is not enabled the Event Counter value coincides with the sequence of buffers saved and readout NPO Filename Number of pages Page 00103 05 V 1724x MUTx 31 V1724 REV31 DOC 66 26 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 3 2 1 Custom size events NPO It is possible to make events with a number of Memory locations which depends on Buffer Organization register setting smaller than the default value One memory location contains two ADC samples and the maximum number of memory locat
40. ble bandwidth is 200 Mb s The FPGA ROC handles 8 bit data Data rate is Y of TRG CLK Chx DATA represents 8 bit of the converted sample selected via the Analog Monitor Polarity amp Shift register on modules with Piggy Back revision older than 0 B Chx DATA represents the 8 MSB of the converted sample Data from 8 channels are summed each channel can be enabled see Analog Monitor Register to participate or not to the sum The sum value is provided on 11 bit bit 31 of Analog Monitor register allows to invert the sum a positive negative offset also encoded on 11bit can be added to the sum there is a sign bit in the Analog Monitor Register to select offset polarity The sum value can be multiplied by a fixed factor MAGNIFY x1 x2 x4 x8 The final result 11 bit dynamics allows to drive the DAC The DAC output has 1V dynamics and drives 50 Ohm 3 7 3 1 Procedure to enable Analog Monitor mode In order to enable Analog Monitor mode is necessary to enable the channels to send data to FPGA ROG by setting to 1 bit 7 of Channel Configuration register If this bit is set the datum sent is always 0 Configure the Analog Monitor register with the desired settings Enable Analog Monitor mode set to 2 the Monitor Mode register NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 49 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1
41. d ODD DOE 20 vio MIROR I Ka HODE S9 SNE ESSA a Us B P el ws T c CES i ER 6 ol ER C6 ne JPI cim ME id _ n 338 m u15 IN R92 E B EE E o d gr E e emir 2 Beh i 3 El Er SI BIR exe rw sm E progres HERE port ran 1 gml mes 1 99 RTO2 8 r m 00 00 em J HRZ J 23 88 U17 o swal c ER S mm e R Me GND o o H 28 cus weu pp SS Sele um BEE oe PE O me E gt sap 4 e EZ En ERR A X E Ki R117 ER ss Bx 3 I d u21 C R124 cS Ez sue Rize EBI 61264 Ei 227 VCCINT PB RIZ 5128 ES R127 SE C135 ma Ri S0 ra oe woo cum E L R135 En 1391 Gale era C737 EX L L R 37 GS fa TAS R136 GO See i5 S A BBBB as znni Ice gt canal IK RTASRTAA qd sv ag je SE 1 such ay al ER EX 5 u25g H u23 i 53R1521 E dl en E i C759 U24 l Kop 2 9 3 SLOT 2 o al ens 8 S fi Ei B E CR o 1 9 li C186 90187 p sl EE G R159 le 82 RIS 17 io E m Lx R162 171 GND lez Cl7e gt P2 c3 mo 2 cis cis C176 BR Z u27 Q2 R166 R167 ques EB yes ha ag SEY a BB dei RIZZ Ger C179 RS dica eut y 2 gt WE tok C185 L EH C X183o n 0184 Oe G RIBI Sms R180 E vae la cm sg sel ze 5VA VEE U31 5VA use 5m coo E a DU s Emu i E B Ba ul ie NO OP E er DIS SIR uiuos 1 C VAD 235
42. echanical specifications LC type connector to be used with Multimode 62 5 125um cable with LC connectors on both sides not featured on Mod V1724LC Electrical specifications Optical link for data readout and slow control with transfer rate up to 80MB s daisy chainable NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 15 CAEN Tools for Discovery Document type User s Manual MUT n Title Revision date Revision Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 2 5 Other front panel components 2 5 1 Displays The front panel hosts the following LEDs Table 2 2 Front panel LEDs Name Colour Function DTACK green VME read write access to the board CLK_IN green External clock enabled NIM green Standard selection for CLK I O V1724LC Rev 0 TRG OUT TRG IN S IN TTL green Standard selection for CLK I O V1724LC Rev 0 TRG OUT TRG IN S IN LINK green yellow Network present Data transfer activity PLL_LOCK green The PLL is locked to the reference clock PLL_BYPS green The reference clock drives directly ADC clocks the PLL circuit is switched off and the PLL_LOCK LED is turned off RUN green RUN bit set TRG green Trigger accepted DRDY green Event data depending on acquisition mode are present in the Output Buffer BUSY red All the buffers are full OUT_LVDS green Signal group OUT direction enabled NPO Filename Numb
43. ed by as many data as those indicated in the stored skipped words field if the control word type is skip then it will be followed by a good control world unless the end of event is reached IMPORTANT NOTE the maximum allowed number of control words is 62 14 for piggy back release 0 6 and earlier therefore the ZLE is active within the event until the 14 transition between a good and a skip zone or between a skip and a good zone All the subsequent samples are considered good and stored Fig 3 7 shows an example of Zero Length Encoding the algorithm has positive logic CHO CH3 are enabled for acquisition therefore the Channel Mask field in the Header allows to acknowledge which channel the data are coming from see also 3 3 3 for data format details Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 32 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 Settings CH Enable Mask OxF Channel Configuration bits 19 16 0x2 ZLE mode Trigger Source Enable Mask bits 31 16 0x4000 Trigger Source Enable Mask bits 15 0 OxO Channel n Z8 THRES bit 31 0 Channel n Z8 THRES bits 13 0 Threshold Channel n Z8 NSAMP bits 31 16 Nifwd Channel n Z8 NSAMP bits 15 0 NIbk Threshold Threshold Threshold OUTPUT DATA 31 30 29
44. eere 30 34 13 ero Length Encoding D on n REO ia E 32 3 4 2 Zero Suppression Examples insonini entente then neen eene enne nette tene tree tenerent enne 34 3 3 TRIGGER MANAGEMENT erret rebut e o seeders Severe rebel entes eo see Ee Et p EE 38 3 5 1 External trigger 3 5 2 Software trigger 3 5 3 Local channel duto trigg r uicit e decens 39 3 5 3 1 Erigger comcidence level aiU pn DERE A ere Re RU Ro Re esee eve erp EE 40 3 5 4 Trigger distrib tor sepisan beret o e Re io ide 43 300 FRONT PANEG VO Secession npe DURS REB ERR TREEEIER EROR HER GARE DUREE GR ERO RR IEEE ERES 44 3 6 1 Mode 0 REGISTER esses eene ne enne RR RR RR entren tenet nenne tete tree trennen nnne enne 46 3 6 2 Mode 1 ETOILE 46 3 6 3 Mode 2 n US Kan VMEITO 46 3 6 3 1 EE 46 BiG 32s nVETO Sinaloa 46 3 06 33 e EE 46 004 TR ee 47 3 6 4 Mode 3 OLD STEE 47 ERENNERT 47 3642 Busy SIgn l 56e iret idad 47 3 64 3 D taR dy signal eee ada iia ii aves Die ee o Tea 47 E EN E EE 47 KREE EE 47 34 ANALOG IN acca bens Gh een teens 48 3 7 1 Trigger Majority Mode Monitor Mode 0 sse eene en rennen 46 3 7 2 Test Mode Monitor Mode 1 eee enne nnne entrer nano nn rn entres e innen rennen 49 3 73 Analog Monitor Inspection Mode Monitor Mode 2 essent eene 49 3 7 3 1 Procedure to enable Analog Monitor mode sess 49 3132 e Applications examples icio oe red teu a eem Doct E ter ir d D
45. er of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 1 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 2 6 Internal components SW2 4 5 6 Base Addr 31 16 Type 4 rotary switches Function Set the VME base address of the module SW3 CLOCK SOURCE Type Dip Switch Function Select clock source External or Internal SW1 FW Type Dip Switch Function it allows to select whether the Standard STD or the Back up BKP firmware must be loaded at power on default position STD NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 17 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 d c baz E E Le al Om D I ou 33 Ja PRE g Ip H KH us ul CG J5 cno BE E Us all ee 5 ll e el ga Es ES al d m2 2 B H RI c B wes POROUS ARARENRRS 3 BB El S R23 e SE B BB d DU I di om cds eke 7 QOQUQU0000000000 0 Store Ras CO R48 y nas y go 7 OG R56 li IJ d be l SES Y Gd ess e QJ AD 00 OY ek E N ER
46. er s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 Fig 3 16 shows the trigger management in case the coincidences are enabled with Majority level 1 and Trvawis a value different from 0 CHO THRESHOLD CHO enabled IN N LOCAL TRG CH0 CH1 THRESHOLD CH1 enabled IN LOCAL TRG CH1 OR signal Trivaw TRIGGER l Maj lev 1 Fig 3 16 Local trigger relationship with Majority level 1 and TrvwwX 0 NOTE with respect to the position where the global trigger is generated the portion of input signal stored depends on the programmed length of the acquisition window and on the post trigger setting NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 41 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 Fig 3 17 shows the trigger management in case the coincidences are enabled with Majority level 1 and Trvaw 0 i e 1 clock cycle CHO THRESHOLD CHO enabled IN LOCAL TRG CHO CH1 THRESHOLD CH1 enabled IN LOCAL TRG CH1 OR signal Trivaw TRIGGER l Maj lev 1 Fig 3 17 Local trigger relationship with Majority level 1 and Trvaw 0 In
47. eral purpose C Libraries and Demo Programs CAENScope Analog Monitor not available in V1724LC 12bit 100MHz DAC controlled by ROC FPGA supports five operating modes Waveform Generator 1 Vpp ramp generator Majority MON 2 output signal is proportional to the number of ch under over threshold 1 step 125mV Analog Inspection data stream from one channel ADC drives directly the DAC input producing the channel input signal 1 Vpp Buffer Occupancy MON 2 output signal is proportional to the Multi Event Buffer Occupancy 1 buffer 1mV Voltage level MON 2 output signal is a programmable voltage level LVDS I O NPO 00103 05 V1724x MUTx 31 16 general purpose LVDS UO controlled by the FPGA Busy Data Ready Memory full Individual Trig Out and other function can be programmed An Input Pattern from the LVDS I O can be associated to each trigger as an event marker Filename Number of pages Page V1724_REV31 DOC 66 19 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 Functional description 3 1 Analog Input The module is available either with single ended on MCX connector or on request differential on Tyco MODU II 3 pin connector input channels 3 1 1 Single ended input Nominal Input dynamics is 2 25Vpp Zin 50 Q A 16bit DAC allow to add up to 1 125V DC offset
48. ernvrsennesnnrrsennesnnrssenevsnnrrssnnesnnrssenevsnnrnsennesnnrssenevsnnrssennssnnrssennesnnrnsennesnnvssensesnner 26 FIG 3 5 EVENT Re EE KE 28 FIG 3 6 ZERO SUPPRESSION BASED ON THE AMPLITUDE enonnvvrnvennvnrnrrvenvnnenrnvennnnenrnsennnnsnrnssnnenenrsvsnnnnsnrssensnnsnrnsensen 31 FIG 3 7 ZERO LENGTH ENCODING SAMPLES STORAGE eerrnnvvrnvenvvnrnrnvennnnsnrnvenvnnsnrnsennnnnnrnsenvnnsnrnsennnsnnrnsensnnsnrnsensee 33 FIG 3 8 ZERO SUPPRESSION SAMPLE 34 NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 5 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 FIG 3 9 EXAMPLE WITH POSITIVE LOGIC AND NON OVERLAPPING Ny gx Ny rem 34 FIG 3 10 EXAMPLE WITH NEGATIVE LOGIC AND NON OVERLAPPING Ni gx Ny rwn 35 FIG 3 11 EXAMPLE WITH POSITIVE LOGIC AND NON OVERLAPPING Ne 36 FIG 3 12 EXAMPLE WITH POSITIVE LOGIC AND OVERLAPPING Ny gx sssssssssceeeesssseeceeececsesssaeeecececeessasseseeecsensennaeees 37 FIG 3 13 BLOCK DIAGRAM OF TRIGGER MANAGEMENT 38 FIG 3 14 LOCAL TRIGGER GENERATION s 0 0 seciecsstecccssececsesteseceesssecessscecessccsscessnccesessceneseetsctesenceceesecnedeetacteceen 39 FIG 3 15 LOCAL TRIGGER RELATIONSHIP WITH MAJORITY LEVEL 0 cccssccesssececseseececseceecessneeecsesaeeeesseeeenees 40 FIG 3 16 LOCAL TRIGGER RELATIONSHIP WITH MAJORITY LEVEL I AND TTVAW 0
49. essing 0x00000000 0xFFFF0000 A32 mode 31 24 23 1615 0 OFFSET lY I X SW2 SW3 SW4 SW5 d 7 183 Bg Wy lo RE INE ifi 2 Fig 3 24 A32 addressing The Base Address of the module is selected through four rotary switches see 2 6 then it is validated only with either a Power ON cycle or a System Reset see 3 8 NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 53 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 10 1 2 CR CSR address GEO address is picked up from relevant backplane lines and written onto bit 23 19 of CR CSR space indicating the slot number in the crate the recognised Address Modifier for this cycle is 2F This feature is implemented only on versions with 160pin connectors 31 2423 19118 16115 0 GEO OFFSET Fig 3 25 CR CSR addressing 3 10 1 3 Address relocation Relocation Address register allows to set via software the board Base Address valid values 0 Such register allows to overwrite the rotary switches settings its setting is enabled via VME Control Register The used addresses are 31 2423 1615 0 FFSET o OFFS Ee software ADER H ADERL lt relocation 31 2423 1615 0 OFFSET N zs st software ADER L 4 relocation Fig 3 26
50. ession based on the signal amplitude ZS_AMP Zero Length Encoding ZLE The algorithm to be used is selected via Configuration register and its configuration takes place via two more registers CHANNEL n ZS_THRES and CHANNEL n ZS_NSAMP When using ZS_AMP and ZS_ZLE algorithms it must be noticed that that one datum 32 bit long word contains 2 samples therefore depending also on trigger polarity settings of bit 31 of Channel n ZS_THRES register threshold is crossed if Positive Logic one datum is considered OVER threshold if at least one sample is higher or equal to threshold Negative Logic one datum is considered UNDER threshold if at least one sample is lower than threshold 3 4 1 Zero Suppression Algorithm NPO 3 4 1 1 Full Suppression based on the integral of the signal Full Suppression based on the integral of the signal allows to discard data from one channel if the sum of all the samples from this channel is smaller than the threshold set by the User It is also possible to configure the algorithm with negative logic in this case the data from that channel are discarded if the sum of all the samples from that channel is higher than the threshold set by the User 3 4 1 2 Full Suppression based on the amplitude of the signal Full Suppression based on the signal amplitude allows to discard data from one channel if the signal does not exceed the programmed threshold for Ns subsequent data at least
51. external plotting tool exactly like in WaveDump NOTE so far DPP Control Software is developed for 724 720 and 751 digitizer series DPP PHA Control Software A CAEN n Electronic Instrumentation IE onuplot graph Channel Jha Energy Histogram I General Settings Channel Enabled DCOfset 4003 Trigger and Timing Filter Threshold 100 7 LSB Smoothing Factor 4 D Delay b 025 us Holdoft d i us RT Discrimination Window RB Enabled Width lr AB DH InputDigital Gain sl Decimation 1 w Pulse Polarity POSITIVE v Energy Filter Decay Time Rise Time Flat Top Baseline Mean Trapezoid Gain Peaking Delay Peak Mean Baseline Holdof Peak Holdoff Basic Settings Mode Advanced Copy Settings sole us 25 us AE us iE osf us 043 us 115 us Como 0 4000 ADC channels 8165 49 7022 17 ES SEN Fig 4 5 DPP Control Software Graphical User Interface and Energy plot Filename V1724_REV31 DOC Number of pages 66 Page 62 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 5 Installation The Mod V1724 fits into all GU VME crates VX1724 versions require VME64X compliant crates Turn the crate OFF before board insertion removal Remove all cables connected to the front panel before board insertion rem
52. ftware on their own are suggested to start with this demo and modify it according to their needs For more details please see the WaveDump User Manual and Quick Start Guide Doc nr UM2091 GD2084 Fig 4 2 WaveDump output waveforms CAENScope is a fully graphical program that implements a simple oscilloscope it allows to see the waveforms set the trigger thresholds change the scales of time and amplitude perform simple mathematical operations between the channels save data to file and other operations CAENscope is provided as an executable file the source codes are not distributed NOTE CAENScope does not work with digitizers running DPP firmware and it is not compliant with x742 digitizer family For more details please see the CAENScope Quick Start Guide GD2484 Tools for Discover Ce O CAEN Q cae mam uan Ga pi Lei Ci Dei uum usn Des i MI re al lea le ple ale ale ge AUTO TRIG RISING EDGE am Fig 4 3 CAENScope oscilloscope tab Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 61 CAEN Tools for Discovery Document type User s Manual MUT NPO 00103 05 V1724x MUTx 31 Title Mod V1724 8 Channel 14bit 100MS s Digitizer Revision 31 Revision date 11 03 2015 CAENUpgrader is a software composed of command line tools together with a Java Graphical User Interface for Windows and Linux OS CAENUpgrader allows in few easy steps to
53. ic The synchronization tool allows to propagate the trigger to all boards and acquire the events accordingly Moreover in case of busy state of one or more boards the acquisition is inhibited for all boards For a detailed guide to multi board synchronization refer to the web available document AN2086 Synchronization of CAEN Digitizers in Multiple Board Acquisition Systems Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 23 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 3 3 3 1 Acquisition Modes Acquisition run stop The acquisition can be started and stopped in different ways according to bits 1 0 setting of Acquisition Control register and bit 2 of the same register NPO SW CONTROLLED bits 1 0 00 Start and Stop take place by software command Bit 2 0 means stopped while bit 2 1 means running S IN CONTROLLED bits 1 0 01 bit 2 1 arms the acquisition and the Start is issued as the S IN signal is set high and the Stop occurs when it is set low If bit 2 0 disarmed the acquisition is always off FIRST TRIGGER CONTROLLED bits 1 0 10 bit 2 1 arms the acquisition and the Start is issued on the first trigger pulse rising edge on the TRG IN connector This pulse is not used as a trigger actual triggers start from the second pulse on TRG IN
54. in old data are lost After the last word in an event the first word Header of the subsequent event is readout It is not possible to readout an event partially see also 3 3 3 3 12 1 1 SINGLE D32 This mode allows to readout a word per time from the header actually 4 words of the first available event followed by all the words until the end of the event then the second event is transferred The exact sequence of the transferred words is shown in 3 3 3 We suggest after the 1 word is transferred to check the Event Size information and then do as many D32 cycles as necessary actually Event Size 1 in order to read completely the event Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 55 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 NPO 3 12 1 2 BLOCK TRANSFER D32 D64 2eVME BLT32 allows via a single channel access to read N events in sequence N is set via the BLT Event Number register The event size depends on the Buffer Size Register setting namely Event Size 8 Block Size 16 bytes Smaller event size can be achieved via Custom Size setting Then it is necessary to perform as many cycles as required in order to readout the programmed number of events We suggest to enable BERR signal during BLT32 cycles in order to end the cycle avoiding filler
55. ions Nioc is therefore half the maximum number of samples per block NS 512K Nblocks Smaller Nioc values can be achieved by writing the number of locations No into the Custom Size register Nioc 0 means default size events i e the number of memory locations is the maximum allowed Nioc N1 with the constraint OxN1 2NS means that one event will be made of 2 N1 samples 3 3 3 Event structure An event is structured as follows Header four 32 bit words Data variable size and format The event can be readout either via VME or Optical Link data format is 32 bit long word therefore each long word contains 2 samples 3 3 3 1 Header It is composed by four words namely Size of the event number of 32 bit long words Board ID GEO Bit24 data format 0 normal format 1 Zero Length Encoding data compression method enabled see 3 4 16 bit pattern latched on the LVDS I O see 3 6 as one trigger arrives Channel Mask 21 channels participating to event ex CH5 and CH7 participating Ch Mask 0xAQ this information must be used by the software to acknowledge which channel the samples are coming from Event Counter It is the trigger counter it can count either accepted triggers only or all triggers Trigger Time Tag It is a 31 bit counter 31 bit count 1 bit as roll over flag which is reset either as acquisition starts or via front panel Reset signal and is incremented at each sam
56. larly unsuitable when there are multiple digitizers running synchronously because the triggers accepted by one board and not by other boards cause event misalignment In this cases it is possible to program the BUSY signal to be asserted when the digitizer is close to FULL condition but it has still some free buffers Almost FULL condition In this mode the digitizer remains able to accept some more triggers even after the BUSY assertion and the system can tolerate a delay in the inhibit of the trigger generation When the Almost FULL condition is enabled by setting the Almost FULL level Memory Almost FULL Level register address 0x816C to X the BUSY signal is asserted as soon as X buffers are filled although the board still goes FULL and rejects triggers when the number of filled buffers is N or N 1 depending on bit 5 in the Acquisition Control Register as described above In case of multi board set up the BUSY signal can be propagated among boards through the front panel LVDS I O connectors see 3 6 Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 29 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 4 Zero suppression The board implements three algorithms of Zero Suppression and Data Reduction Full Suppression based on the integral of the signal ZS_INT Full Suppr
57. ld ramping up or down depending on VME settings and remains under or over threshold for Nth quartets of samples at least Nth is programmable via VME The Vth digital threshold the edge type and the minimum number Nth of couples of samples are programmable via VME register accesses actually local trigger is delayed of Nth quartets of samples with respect to the input signal NOTE the local trigger signal does not start directly the event acquisition on the relevant channel such signal is propagated to the central logic which produces the global trigger which is distributed to all channels see 3 5 4 Nth 4samples lt gt Nth 4samples Nth 4samples 3 d THRESHOLD x CHO IN Local Trigger CHO Channel Configuration register 6 0 Local Trigger CHO Channel Configuration register 6 1 Fig 3 14 Local trigger generation NPO Filename Number of pages Page 00103 05 V 1724x MUTx 31 V1724 REV31 DOC 66 39 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 5 3 1 Trigger coincidence level In the standard operating the board s acquisition trigger is a global trigger generated as in 3 5 4 This global trigger allows the coincidence acquisition mode to be performed through the Majority operation Enabling the coincidences is possible by writing i
58. le level 12 bit range set in the Memory Buffer Almost Full Level register address 0x816C LVDS Busyln is available in nBUSY nVETO configuration see Table 3 3 Busyln enable is set in the Acquisition Control register address 0x8100 bit 8 3 6 3 2 nVETO signal Direction is INPUT nVETOIn is an active low signal which if enabled i e Acquisition Control register address 0x8100 bit 9 1 is used to veto the generation of the global trigger propagated to the channels for the event acquisition Direction is OUTPUT the nVETO signal is the copy of nVETOIn 3 6 3 3 nTrigger signal Direction is INPUT nTriggerln is an active low signal which if enabled is a real trigger able to cause the event acquisition It can be propagated to TRG OUT LEMO connector or to the individual triggers Direction is OUTPUT nTrigger signal is the copy of the trigger signal propagated to the TRG OUT LEMO connector NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 46 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 6 3 4 nRun signal NPO Direction is INPUT nRunin is an active low signal which can be used as Start for the digitizer i e Acquisition Control register address 0x8100 bits 1 0 11 It is possible to program the start on the level or on the edge of the nRunln signal Acquisi
59. le with negative logic and non overlapping Nie Nyrwp then the readout event is N N s N s 5 control words 1 size Good N Ny Nyrwo N words with samples under threshold Skip N2 Nirwo Nik Good N 3 Niek N3 Nirwo N g words with samples under threshold Skip Na Nirwo Niek Good N 5 Nek Ne N s words with samples under threshold In some cases the number of data to be discarded can be smaller than Ni gk and Niewo 1 If the algorithm works in positive logic and Ni lt Niek lt Ns Nirwo 0 Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 35 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 Fig 3 11 Example with positive logic and non overlapping Nyx then the readout event is N ANS N 4 5 control words 1 size Good N N2 Ny Ne words with samples over threshold Skip Ns Nik Good Na Nee Na N 4 words with samples over threshold Skip Ns 2 If the algorithm works in positive logic and Ne 0 Ns lt Nirwo lt N3 then the readout event is N s N Ns 5 control words 1 size Skip N Good N No Nirwo N gt words with samples over threshold Skip Ns Nyrwo Good N Ns N4 Ns words with samples over threshold 3 If the algorithm works in positive logic and Nigk
60. mplitude Filename V1724_REV31 DOC Channel Mask 0x5 Number of pages 66 Page 31 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 4 1 3 Zero Length Encoding ZLE NPO Zero Length Encoding allows to transfer the event in compressed mode discarding either the data under the threshold set by the User positive logic or the data over the threshold set by the User negative logic With Zero length encoding it is also possible to set Nigx LOOK BACK the number of data to be stored before the signal crosses the threshold and or Nirwo LOOK FORWARD the number of data to be stored after the signal crosses the threshold set in the Channel n ZE_THRES register address 0x1n24 In this case the event of each channel has a particular format which allows the construction of the acquired time interval Total size of the event total number of transferred data Control word stored valid data if control word is good Control word stored valid data if control word is good The total size is the number of 32 bit data that compose the event including the size itself The control word has the following format Bit _ Function 0 skip 31 1 good 30 21 0 20 0 stored skipped words If the control word type is good then it will be follow
61. n the Trigger Source enable Mask register address 0x810C Bits 7 0 enable the specific channel to participate to the coincidence Bits 23 20 set the coincidence window Trvaw Bits 26 24 set the Majority i e Coincidence level the coincidence takes place when Number of enabled local auto triggers Majority level Supposing bits 7 0 FF i e all channels are enabled and bits 26 24 01 i e Majority level 1 a global trigger is issued whenever at least two of the enabled local channel auto triggers are in coincidence within the programmed Trvaw The Majority level must be smaller than the number of channels enabled via bits 7 0 mask By default bits 26 24 00 i e Majority level 2 0 which means the coincidence acquisition mode is disabled and the Trvawis meaningless In this case the global trigger is simple OR of the enabled local channel auto triggers Fig 3 15 shows the trigger management in case the coincidences are disabled CHO THRESHOLD CHO enabled IN LOCAL TRG CHO CH1 THRESHOLD CH1 enabled IN LOCAL TRG CH1 OR signal TRIGGER I I Maj lev 0 Fig 3 15 Local trigger relationship with Majority level 0 NPO Filename Number of pages Page 00103 05 V 1724x MUTx 31 V1724 REV31 DOC 66 40 CAEN Tools for Discovery Document type Title Revision date Revision Us
62. ne if both revision are simultaneously updated and a failure occurs it will not be possible to upload the firmware via VME or Optical Link again IMPORTANT NOTE all modules featuring PCB Rev 0 do not support firmware release v1724 revX1 2 0 4 rbf and later PCB revision Revision Field can be read at Configuration ROM see the document V1724 Registers Description Contact CAEN technical support see 6 in order to upgrade firmware of modules featuring PCB Rev 0 Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 64 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 NPO 5 3 1 V1724 Upgrade files description The board hosts one FPGA on the mainboard and two FPGA on each mezzanine i e one FPGA per channel The channel FPGAs firmware is identical A unique file is provided that will updated all the FPGA at the same time ROC FPGA MAINBOARD FPGA Readout Controller VME interface FPGA Altera Cyclone EP1C20 AMC FPGA CHANNEL FPGA ADC readout Memory Controller FPGA Altera Cyclone EP1C4 or EP1C20 see 2 7 The programming file has the extension CFA CAEN Firmware Archive and is a sort of archive format file aggregating all the standard firmware files compatible with the same family of digitizers CFA and its name follows this general scheme x724 revX Y W Z CFA where e x7
63. ocet ipt es dre es 50 3 7 4 Buffer Occupancy Mode Monitor Mode 3 nennen nenne 51 3 7 5 Voltage Level Mode Monitor Mode 4 sss enne nennen nenne 5I 3 5 TEST PATTERN GENERATOR eegene Eed EENEG 52 3 9 RESET CLEAR AND DEFAULT CONMPIOGURATION cono nene nnn 52 3 9 1 Global RE 52 3 9 2 Memory E 52 3 9 3 RT EE 52 3 10 bilia MIU OM 53 340 1 Addressing c pabilities eee tet a ote RH E Ram E Ren RE sed rad Pe es Eon open erased 53 3 10 1 1 hr cnn NG 53 NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724 REV31 DOC 66 4 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 10 1 2 CR CSR address unnsette REED bona 54 3 10 1 3 Address relocation cti te ei dace a eee ates doen ede a ene ete Eae 54 3 11 DATA TRANSFER CAPABILITIES sccescceessscesneecssecesceecsaecesneecsacesceeceaceseeecsaeeeeeeeceaeeeeeeecsaeeseaeecsaeeenees 54 3 12 E CR 25 IZA Sequential reddit ora IE UE 55 3 12 1 1 SINGLE D3 EE 55 STT BLOCK TRANSFER D32 D64 2e VME ccceseecceseescceseeeecesecseeeeeseeesecseceaeeseceaecaeseaesaeeeaesseeeaeeeeeeaeeas 56 3 12 1 3 CHAINED BLOCK TRANSFER D32 D64 essent nenne tne tnter enne nnt nns 57 3 12 2 Random readout to be implemented esee eene ne 57 3123 Event IS E
64. om the header which reports the required size not the actual one of the event the Trigger Time Tag the Event Counter and the part of the event required on the channel addressed in the Event Block Request After data readout in order to perform a new random readout it is necessary a new Event Block Request otherwise Bus Error is signalled In order to empty the buffers it is necessary a write access to the Buffer Free register the datum written is the number of buffers in sequence to be emptied BUFFERS SELECT THE BUFFER NUMBER SELECT THE STARTING OFFSET READUT f DATA lt lt BERR SELECT THE BLOCK LENGHT Fig 3 28 Example of random readout Filename Number of pages Page 00103 05 V 1724x MUTx 31 V1724 REV31 DOC 66 57 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 12 3 Event Polling A read access to Event Size register allows polling the number of 32 bit words composing the next event to be read this permits to perform a properly sized according to the Event Size information BLT readout from the Memory Event Buffer NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 58 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 1
65. on Mod V1724LC Mechanical specifications 00 type LEMO connectors Filename Number of pages Page 00103 05 V 1724x MUTx 31 V1724 REV31 DOC 66 13 CAEN Q Tools for Discovery Document type User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 Title Revision date Revision 31 2 4 3 ADC REFERENCE CLOCK connectors GND CLK CLK m Fig 2 4 AMP CLK IN OUT Connector Function CLK IN External clock Reference input AC coupled diff LVDS ECL PECL LVPECL CML Zdiff 1000 Mechanical specifications AMP 3 102203 4 connector Function CLOCK OUT Clock output DC coupled diff LVDS Zdiff 1000 Mechanical specifications AMP 3 102203 4 AMP MODUII 2 4 4 Digital I O connectors NPO 00103 05 V1724x MUTx 31 V1724_REV31 DOC a GE 9 0 Ce per o Fig 2 5 Programmable IN OUT Connector Function N 16 programmable differential LVDS I O signals Zdiff_in 100 Ohm Four Indipendent signal group 0 3 4 7 8 11 12 15 In Out direction control see also 3 6 Mechanical specifications 3M 7634 5002 34 pin Header Connector Number of pages Page Filename 66 14 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 2 4 5 Optical LINK connector LINK o TX red wrap RX black wrap Fig 2 6 LC Optical Connector M
66. oval A CAUTION ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL BEFORE EXTRACTING THE BOARD FROM THE CRATE 5 1 Power ON sequence To power ON the board follow this procedure 1 insert the V1724 board into the crate 2 power up the crate 5 2 Power ON status At power ON the module is in the following status e the Output Buffer is cleared e registers are set to their default configuration NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 63 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 5 3 Firmware upgrade NPO The firmware of the V1724 is stored on an on board FLASH memory Two copies of the firmware are stored in two different pages of the FLASH called Standard STD and Backup BKP at Power On a microcontroller reads the Flash memory and programs the module with the firmware version selected via the SW1 switch see 2 6 which can be placed either on the STD position left or in the BKP position right It is possible to upgrade the board firmware via VME or Optical Link by writing the FLASH with CAENUpgrader software see 4 For instructions to use the program please refer to the document GD2512 CAENUpgrader QuickStart Guide web available It is strongly suggested to upgrade ONLY one of the stored firmware revisions generally the STD o
67. pling clock cycle It represents the trigger time reference TTT resolution is 20 ns and ranges up to 21 s i e 10 ns 231 1 3 3 3 2 Samples Stored samples data from masked channels are not read Filename Number of pages Page 27 00103 05 V 1724x MUTx 31 V1724 REV31 DOC 66 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 3 3 3 Event format examples The event format is shown in Fig 3 5 case of 8 channels enabled with Zero Length Encoding disabled and enabled respectively ZERO LENGHT ENCODING disabled 31 30 29 28 27 26 25 24 23 2221 20 19 18 17 16 15 14 13 1201 10 9 8 7 6 15 4 3 2 1 0 ofo SAMPLE 1 CH 0 0 0 SAMPLE 0 CH 0 0 0 SAMPLE 3 CH 0 0 0 SAMPLE 2 CH 0 El gt O 3 SAMPLE _ N 1 CH 0 SAMPLE N 2 CH 0 p 0 0 SAMPLE 1 CH 7 olol SAMPLE 0 CH 7 010 SA
68. readout The last BLT32 cycle will not be completed it will be ended by BERR after the N event in memory is transferred see example in the figure below READOUT DATA 7 o Block size 1024 bytes BERR enabled BLT size 16384 bytes N 4 BUFFERS OiN BERR Fig 3 27 Example of BLT readout Since some 64 bit CPU s cut off the last 32 bit word of a transferred block if the number of words composing such block is odd it is necessary to add a dummy word which has then to be removed via software in order to avoid data loss This can be achieved by setting the ALIGN64 bit in the VME Control register MBLT64 cycle is similar to the BLT32 cycle except that the address and data lines are multiplexed to form 64 bit address and data buses The 2eVME allows to achieve higher transfer rates thanks to the requirement of only two edges of the two control signals DS and DTACK to complete a data cycle Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 56 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 NPO 3 12 1 3 CHAINED BLOCK TRANSFER D32 D64 The V1724 allows to readout events from more daisy chained boards Chained Block Transfer mode The technique which handles the CBLT is based on the passing of a token between the boards it is necess
69. requency submultiple The only requirement over the SAMP CLK is to remain within the ADCs range By design sampling frequency values in the range 32 2 100 MHz are supported 3 2 2 PLL Mode The AD9510 features an internal Phase Detector which allows to couple REF CLK with VCXO 1 GHz frequency for this purpose it is necessary that REF CLK is a submultiple of 1 GHz AD9510 default setting foresees the board internal clock 50MHz as clock source of REF CLK This configuration leads to Ndiv 100 Rdiv 5 thus obtaining 10MHz at the Phase Detector input and CLK INT 1GHz The required 100 MHz Sampling Clock is obtained by processing CLK INT through Sdiv dividers When an external clock source is used if it has 50MHz frequency then AD9510 programming is not necessary otherwise Ndiv and Rdiv have to be modified in order to achieve PLL lock A REF CLK frequency stability better than 100ppm is mandatory 3 2 3 Trigger Clock TRG CLK signal has a frequency equal to Y of SAMP CLK therefore a 2 samples uncertainty occurs over the acquisition window 3 2 4 Output Clock Front panel Clock Output is User programmable Odiv and Odel parameters allows to obtain a signal with the desired frequency and phase shift in order to recover cable line delay and therefore to synchronise daisy chained boards CLK OUT default setting is OFF itis necessary to enable the AD9510 output buffer to enable it 3 2 5 AD9510 programming
70. rivers for both the physical communication channels the proprietary CONET Optical Link managed by the A2818 PCI card or A3818 PCle cards and the VME bus accessed by the V1718 and V2718 bridges refer to the related User Manuals a set of C and LabView libraries demo applications and utilities Windows and Linux are both supported The available software is the following CAENComm library contains the basic functions for access to hardware the aim of this library is to provide a unique interface to the higher layers regardless the type of physical communication channel Note for VME access CAENcomm is based on CAEN s VME bridges V1718 USB to VME and V2718 PCI PCle to VME In the case of third part bridges or SBCs the user must provide the functions contained in the CAENcomm library for the relevant platform The CAENComm requires the CAENVMELib library to be installed even in the cases where the VME is not used CAENDigitizer is a library of functions designed specifically for the digitizer family and it supports also the boards running special DPP Digital Pulse Processing firmware The purpose of this library is to allow the user to open the digitizer program it and manage the data acquisition in an easy way with few lines of code the user can make a simple readout program without the necessity to know the details of the registers and the event data format The CAENDigitizer library implements a common interface to the higher software la
71. rs the data off the Output Buffer The Memory Reset can be forwarded via either a write access to Software Clear Register or with a pulse sent to the front panel Memory Clear input see 3 9 3 9 3 Timer Reset The Timer Reset allows to initialize the timer which allows to tag an event The Timer Reset can be forwarded with a pulse sent to Trigger Time Tag Reset input see 3 6 Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 52 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 10 VMEBus interface The module is provided with a fully compliant VME64 VME64X interface see S 1 1 whose main features are EUROCARD 9U Format J1 P1 and J2 P2 with either 160 pins 5 rows or 96 3 rows connectors A24 A32 and CR CSR address modes D32 BLT MBLT 2eVME 2eSST data modes MCST write capability CBLT data transfers RORA interrupter Configuration ROM 3 10 1 Addressing capabilities 3 10 1 1 Base address The module works in A24 A32 mode The Base Address of the module can be fixed through four rotary switches see 2 6 and is written into a word of 24 or 32 bit The Base Address can be selected in the range 0x000000 OXxFF0000 A24 mode 31 24 23 1615 0 OFFSET 1 swa sws Fig 3 23 A24 addr
72. s Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 37 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 5 Trigger management All the channels in a board share the same trigger this means that all the channels store an event at the same time and in the same way same number of samples and same position with respect to the trigger several trigger sources are available Mother Board Mezzanines Memory Buffers Logic 8 L TRG Digital l Thresholds VME Local Bus Interface I Interface Fig 3 13 Block diagram of Trigger management 3 5 1 External trigger External trigger can be NIM TTL signal on LEMO front panel connector 50 Ohm impedance The external trigger is synchronised with the internal clock see 3 2 3 if External trigger is not synchronised with the internal clock a one clock period jitter occurs 3 5 2 Software trigger Software trigger are generated via VME bus write access in the relevant register NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 38 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 3 5 3 Local channel auto trigger Each channel can generate a local trigger as the digitised signal exceeds the Vth thresho
73. s place on two domains OSC CLK and REF CLK the former is a fixed 50MHz clock provided by an on board oscillator the latter provides the ADC sampling clock OSC CLK handles both VME and Local Bus communication between motherboard and mezzanine boards see red traces in the figure above REF CLK handles ADC sampling trigger logic acquisition logic samples storage into RAM buffer freezing on trigger through a clock chain Such domain can use either an external via front panel signal or an internal via local oscillator source selection is performed via dip switch SW1 see 2 6 in the latter case OSC CLK and REF CLK will be synchronous the operation mode remains the same anyway REF CLK is processed by AD9510 device which delivers 6 clock out signals 4 signals are sent to ADCs one to the trigger logic and one to drive CLK OUT output refer to AD9510 data sheet for more details http www analog com UploadedFiles Data Sheets AD9510 pdf two operating modes are foreseen Direct Drive Mode and PLL Mode NPO Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 21 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 NPO 3 2 1 Direct Drive Mode The aim of this mode is to drive externally the ADCs Sampling Clock generally this is necessary when the required sampling frequency is not a VCXO f
74. tion Control register bit 11 Direction is OUTPUT nRun signal is the inverse of the internal Run of the board 3 6 4 Mode 3 OLD STYLE Old Style mode has been introduced in order the LVDS connector properly programmed to be able to feature the same I O signals available in the ROC FPGA firmware revisions lower than 3 8 NOTE for old configuration registers description please refer to the document V1724 Registers Description as indicated in the file text file V1724 User Manual Release Notes downloadable at the V1724 and VX1724 web pages 3 6 4 1 nClear_TTT signal It is the only signal available as INPUT It is the Trigger Time Tag TTT reset like in the old configuration 3 6 4 2 Busy signal The Busy signal is active high and it is exactly the inverse of the nBusy signal see 3 6 4 2 In case the Memory Buffer Almost Full Level register is set to 0x0 and the Busyln signal is disabled the Busy is the FULL signal present in the old configuration 3 6 4 3 DataReady signal The DataReady is an active high signal indicating that the board has data available for readout the same as the DataReady front panel LED does 3 6 4 4 Trigger signal The active high Trigger signal is the copy of the acquisition trigger global trigger sent from the motherboard to the mezzanines it is neither the signal provided out on the TRG OUT LEMO connector nor the inverse of the signal sent to the LVDS connector see 3 6 3 3 3 6 4 5
75. to O enables the relevant signals in the group as INPUT while 1 enables them as OUTPUT The LVDS I O new modes are enabled by setting to 1 the bit 8 of the Front Panel I O Control register address 0x811C By default the new modes are disabled i e bit 8 0 and the status of the LVDS WO signals is congruent with the old Programmed l O mode Table 3 2 Front Panel LVDS I Os default setting Nr Direction Description 0 out Ch 0 Trigger Request 1 out Ch 1 Trigger Request 2 out Ch 2 Trigger Request 3 out Ch 3 Trigger Request 4 out Ch 4 Trigger Request 5 out Ch 5 Trigger Request 6 out Ch 6 Trigger Request 7 out Ch 7 Trigger Request 8 out Memory Full 9 out Event Data Ready 10 out Channels Trigger 11 out RUN Status 12 in Trigger Time Tag Reset active low 13 in Memory Clear active low 14 reserved 15 reserved Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 44 CAEN Q Tools for Discovery Document type User s Manual MUT NPO Title Mod V1724 8 Channel 14bit 100MS s Digitizer Revision date 11 03 2015 Revision 31 When enabled i e bit 8 1 the new management allows each group of 4 signals of the LVDS I O 16 pin connector to be configured in one of the 4 following modes according to bits 15 0 in the Front Panel LVDS I O New Features register address 0x81A0 Mode 0 Mode 1 Mode 2 Mode 3
76. yers masking the details of the physical channel and its protocol thus making the libraries and applications that rely on the CAENDigitizer independent from the physical layer The library is based on the CAENComm library that manages the communication at low level read and write access CAENVMELib and CAENComm libraries must be already installed on the host PC before installing the CAENDigitizer however both CAENVMELib and CAENComm libraries are completely transparent to the user Filename Number of pages Page 00103 05 V1724x MUTx 31 V1724_REV31 DOC 66 60 CAEN Q Tools for Discove Document type ry Title Revision date Revision User s Manual MUT Mod V1724 8 Channel 14bit 100MS s Digitizer 11 03 2015 31 NPO WaveDump is a Console application that allows to program the digitizer according to a text configuration file that contains a list of parameters and instructions to start the acquisition read the data display the readout and trigger rate apply some post processing such as FFT and amplitude histogram save data to a file and also plot the waveforms using the external plotting tool gnuplot available on internet for free This program is quite basic and has no graphics but it is an excellent example of C code that demonstrates the use of libraries and methods for an efficient readout and data analysis NOTE WaveDump does not work with digitizers running DPP firmware The users who intend to write the so

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