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Model PCL-722 144 Bit DIO Card

1. 7 2 2 Base Address Setting 0 0 0 ee 9 2 3 Address Parameters 0 cece eee eee 11 2 4 Interrupt Settings 13 CHAPTER 3 OPERATION 15 3 1 Configuration 15 3 2 Interrupt Handling 0 0000 17 CHAPTER 4 PROGRAMMING 21 4 1 Programming Notes 21 4 2 Programming Examples 22 CHAPTER 1 GENERAL INFORMATION 1 1 Introduction The PCL 722 144 bit DIO card is a generalized 144 line parallel digital I O board that has six channels Each channel emulates mode 0 of a 8255 programmable peripheral interface chip and has 24 lines of digital input and or output Every channel has an individual connector with OPTO 22 compatible pin assignment Two lines of each connector can be used to generate a hardware interrupt These inputs are buffered and can be connected to IRQ 2 3 4 5 6 and 7 The PCL 722 is a full size PC add on card and can fit any full length expansion slot in the IBM PC XT AT or compatible computer running at any clock rate PCL 722 General Information VDOZHMON MON 4Qammmnuu mou AWVHOVIT MOOTH 224 TOd aedumy
2. gotoxy 25 6 Programming PCL 722 printf 2x 3 portB box CN i portB read back gotoxy 53 6 printf 32x portB if portB I j printf 7 beep textattr 0x87 gotoxy 1 20 cprintf CN d port B readback error i getch exit 1 quit to dos outportb CN i portC j out j to port C gotoxy 25 8 printf amp 2x 3 portC inportb CN i portC read back x gotoxy 53 8 printf 2x portC if portC j printf N7 ys beep gotoxy 1 20 textattr 0x87 cprintf CN d port C readback error i getch exit 1 quit to dos printf ininPass test Press any key to quit n getch DEMO2 C This demo program demonstrates how to use the capability of interrupt handling of the PCL 722 card HARDWARE SETTING In this program the BASE ADDRESS is set at 0x2C0 and the interrupt level is set at IRQ2 associated to INT OAH ISR and all the interrupt setting jumpers of each channel are set at the P position i e the interrupt request of each channel can be programmed to N xc up 3 be enabled or disabled PROGRAM DESCRIPTION In this program the original INT OAH ISR is replaced by a new ISR named alarm If a hardwa
3. LINES OF I O BASE ADDRESS SWITCH SETTING EXAMPLES in hex PCL 722 Installation I O ADDRESS DEVICE I O ADDRESS DEVICE 000 0FF System I O 380 38F SDLC 2 200 207 Game I O 3B0 3BF Monochrome card 278 27F LPT 2 3C0 3CF EGA card 2F8 2FF COM 2 3D0 3DF Color graphics 300 31F Prototype card 3F0 3F7 Floppy disk 378 37F LPT 1 3F8 3FF COM 1 Fig 2 1 IBM PC XT AT I O map in hex 2 3 Address Parameters The PCL 722 can limit the 32 required addresses to 16 therefore the digital I O is limited to 96 bits SW2 see Fig 2 2 below sets the number of useable I O The PCL 722 card should be left in the 144 bit mode unless this address conflicts with the addresses of other peripherals already installed or those to be installed in neighboring slots Fig 2 2 Select 144 or 96 I O By selecting 96 bit mode two or more boards can be mapped consecutively on adjacent addresses By selecting 144 bit mode a minimum gap of 8 addresses will exist between each board The following address list provides examples of multiple board addressing with consecutive addresses Note that these are not the only addresses available because other combinations can be used Installation PCL 722 Example Board 1 Board 2 200 20F 210 21F 230 23F 240 24F 250 25F 260 26F Note In 144 bit mode base address line A4 is not in functional status therefore A4 of SW1 does not need to be set The following base addresses are available 200 220 240 260 280 2A0
4. a rising edge interrupt Programming PCL 722 getch outportb 0x21 0xfb IMR set IRQ2 nonmasked printf NnWMnCNO Port C x inportb 0x2c2 generate a rising edge signal at CNO PCO outportb 0x2c2 0x9 printf AinincN0 Port C x inportb 0x2c2 printf n npress any key to continue getch clrscr gt printf Press any key to generate a falling edge interrupt getch outportb 0x21 0xfb IMR set IRQ2 nonmasked outportb 0x2c2 0x08 CNO PC4 0 gt interrupt enable 03 1 ie PCO 0 ey printf NnWMnCNO Port C x inportb 0x2c2 generate a falling edge signal at CN O PC3 outportb 0x2c2 OXO printf inincN0 Port C x inportb 0x2c2 printf n npress any key to quit getch set CNO as INPUT to release IRQ2 line outporthb 0x2c3 0x9b restore old INT OAH ISR setvect OxOa Int A Old Vector outportb Ox21 IMR restore 8259 interrupt mask PCLD 7224Q USER S NOTE To use the PCL 722 144 bit DIO card with the PCLD 7224Q you have to apply a 3 8 volts of external DC power into the and terminal of TBP The DC power would supply to the logic side of the SSR module PCLD 7224Q also allows you to use the 5V DC power of PC In this situation you have to short the FVCC besides the TBP by a conductor or fuse like the Fl 8 00 2 25 6 3 i ss 7 500 190 50 1 3 13 C 1
5. voltage 0 0 V 0 80 V High level input current 20 0 uA Low level input current 0 2 mA General Information PCL 722 b Output signal specifications Port A and Port B output logic high voltage 2 4 V min output logic low voltage 0 5 V max High level output current 2 6 mA Low level output current 24 0 mA Port C output logic high voltage 2 4 V min output logic low voltage 0 4 V max High level output current 15 0 mA Low level output current 24 0 mA c Operating environment Temperature 0 C to 70 C Relative Humidity 5 to 9096 noncondensing d Storage environment Temperature 55 C to 150 C Relative Humidity 5 to 90 noncondensing 1 5 Physical Specifications 1 Dimensions 333 5 mm by 99 06 mm 2 connector 50 pin male ribbon cable connector PCL 722 General Information 1 6 Power Requirements PC XT AT I O channel Typical power 1 3 A at 5V DC 5 Maximum power 1 8 A at 5V DC 5 1 7 Transfer Rate Typical 300 K bytes sec Maximum 500 K bytes sec CHAPPER 2 INSTALLATION 2 1 Initial Inspection CAUTION Do not install or remove the PCL 722 I O board while the power is ON as this may damage the plug in board computer or both Always ensure that the power has been turned OFF before proceeding with installation or removal Installation J0 J1 02 53 34 05 BASE ADDR swe l SWZ Z SIS NOLDSNN
6. 2C0 2E0 300 320 340 360 380 3A0 3C0 3E0 The following base addresses are illegal 210 230 250 270 290 2B0 2D0 2F0 310 330 350 370 390 3B0 3D0 3F0 You can set the address according to the information given in the following table I O ADDRESS RANGE SWITCH POSITION SW1 1 2 3 4 9 6 HEXADECIMAL A9 A8 A7 A6 A5 AS 200 20F 1 0 0 0 0 0 220 22F dl 0 0 0 1 0 300 30F 1 1 0 0 0 0 3EO 3EF I 1 1 1 1 0 NOTE 02 ON 1 OFF A4 through A9 correspond to your PC s address lines PCL 722 Installation 2 4 Interrupt Settings Pins PC 0 and PC 3 of each channel of the PCL 722 generate hardware interrupts and can be set to any of the interrupt request lines IRQ2 3 4 5 6 and 7 The IRQ signal is TRI STATED allowing multiple PCL 722 boards to share the same interrupt line For example two PCL 722 boards in a system can have IRQ2 selected The following diagram shows the locations of interrupt enable selection jumpers J2 kk Interrupt Interrupt enabled Interrupt disabled when PC 4 is low enabled Fig 2 3 Interrupt Enable selection CHAPTER3 OPERATION The PCL 722 card emulates MODE 0 of 8255 PPI and is pin compatible with popular industrial solid state I O racks and modules such as those manufactured by OPTO 22 Potter Brumfield Gordos and others The PCL 722 has six 50 pin male IDC connectors that interface with position OPTO 22 racks 8 16 and 24 Two of the I O lines PC 0 PC 3 of each channel can
7. 5 e 19 21 C 23 2 C 4 10 12 14 C 16 18 C 20 22 C 24 mhend d 0 4 0 0 0 0 al lal Gat O O U U 16 19 20 23 00 152 4 00 00 a 99 Oo 00 oo 50 PIN CARD EDGE CONNECTOR
8. Model PCL 722 144 Bit DIO Card PCL 722 144 BIT DIGITAL I O CARD USER S MANUAL This documentation is copyrighted 1993 by Advantech Co Ltd All rights are reserved Advantech Co Ltd reserves the right to make improvements in the products described in this manual at any time without notice No part of this manual may be reproduced copied translated or transmitted in any form or by any means without the prior written permission of Advantech Co Ltd Information provided in this manual is intended to be accurate and reliable However Advantech Co Ltd assumes no responsibility for its use nor for any infringements of rights of third parties which may result from its use PC LabCard is a trademark of Advantech Co Ltd IBM PC PC XT and PC AT are trademarks of International Business Machines Corporation OPTO 22 is a trademark of OPTO 22 Corporation Part No 2003722010 Rev A2 Printed in Taiwan Aug 1993 TABLE OF CONTENTS CHAPTER 1 GENERAL INFORMATION 1 1 1 Introduction 2 0 0 0 0 0 cece E 1 1 2 ESAS co tod a mes e aoa eee Atos es 3 1 3 Applications ove pense be ERR Bethe ds 3 1 4 Electrical Specifications oooooooomooooo oo 3 1 5 Physical Specifications 4 1 6 Power Requirements PC XT AT I O channel 5 1 7 Transfer Rate osculo Mae Nae oe 5 CHAPTER 2 INSTALLATION 7 2 1 Initial Inspection
9. OO 22 OldO CN1 JE WOLOSNNOO 22 OldO ac BIS HOLOHNNOD 22 Oldo 2 e fo ENE 8 HOLOHNNOO OLdO hil gt xJ 8 5 22 OldO iD 2 T zZ 2 OldO PCL 722 PCL 722 Installation CONNECTOR PIN ASSIGNMENT PC 7 GND PC 6 GND PC 5 GND PC 4 GND PC 3 GND PC 2 GND PC 1 GND PC 0 GND PB 7 GND PB 6 GND PB 5 GND PB 4 GND PB 3 GND PB 2 GND PB 1 GND PB 0 GND PA 7 GND PA 6 GND PA 5 GND PA 4 GND PA 3 GND PA 2 GND PA 1 GND PA 0 GND T5V GND 2 2 Base Address Setting The PCL 722 requires 32 consecutive address locations within the I O space Some I O address locations will be occupied by internal I O and your peripherals In order to avoid conflict with these devices the PCL 722 address can be set by a 6 position DIP switch and placed anywhere in the IBM PC decoded external UO space The 200 3FF hex 512 1023 decimal address range provides extensive unused areas of I O space though you should check with the IBM Standard Technical Reference Manual for possible conflicts with commonly installed peripherals PCL 722 Installation 144 LINES OF 1 0 7 x v E n 3 x ul o z E N r Q E Uu Uv o 4 a a lt 3 200 6 4 Sw1 k 1 A 9 200 6 A 4 Swi 1 A 9 Note While selecting 144 lines A4 is not in functional status 96
10. bal LOM e 4 9 31 chal J J Jl o ef 3 3 Lj 1 E H donpuea SurpueH SurpueH SurpueH Suypuey SurpueH y 4dnzige3uT EK 3dn111930 L 3 yin 3dniirsju LS 3dninreju LS 34 14 1370 Lp i Tt 1 1 aes FF I FT 1 Ma m E uo 0 1 e axo 0 1 py 130 0 1 gt 130 0 1 faq AIT gay dad de eos SOIOSNNOS MOLOSNNOO HOIOSNNOO NOLOSNNOO HOIOSNNOO AQLOANNOD zg 0LdO 22 0Ld0 26 OldO 22 040 zg OldO 9 NO NO END ZNO TNO OND gd seg 6 0585 CT essg Tl aseg 4 9584 aseg 4 o 0 o og 9584 91 9554 51 9585 g aseg p seg Q aseg wod Woy uod uroiy BESUITY ssaaaay ssauaavy ssaaaav ssaaaaqv ssauadv PCL 722 General Information 1 2 Features 44 TTL digital I O lines 6 connectors each with 24 I O lines The 24 I O lines of each connector are configured to port PA 8 bit PB 8 bit PC Upper 4 bit and PC Lower 4 bit Each port can be programmed to digital input or digital output Emulates mode O of 8255 PPI Programmable interrupt handling OPTO 22 compatible 50 pin connector Direct interface to wide range of peripherals 1 3 Applications Industrial AC DC I O module monitoring and control Relay and switch monitoring and control Parallel data transfer Sensing the signals of TTL DTL CMOS logic Driving indicator LED s 1 4 Electrical Specifications a Input signal specifications Input logic high voltage 2 0 V 5 25 V Input logic low
11. be used to generate a hardware interrupt Note The PCL 722 emulates MODE 0 of 8255 PPI therefore it is in effect the same as a 8255 controller card and all packages or programs that support the 8255 in MODE 0 can be used on PCL 722 without reconfiguring software 3 1 Configuration Mode 0 of 8255 provides simple input and output for each of the three ports and no handshaking is required as data is written directly to or read from a specified port see 8255 MODE 0 Function Definitions Read back is another useful function of the PCL 722 and this allows the user to monitor each output port of each channel 8255 MODE 0 FUNCTION DEFINITIONS Two 8 bit ports Port A Port B Two 4 bit ports Port C upper Port C lower Any port can be used for input or output Outputs are latched whereas inputs are not latched 16 different input output configurations are available in this mode Operation PCL 722 Address Function BASE ADDRESS 0 Read Write PASE ADDRESS Read Write Port C BASE ADDRESS 2 Read Write CFG REG EXAMPLE Base address set at 300 Fig 3 1 8255 address map pes pes ee ee Ten Ten Pere x soo ser 1 se aio ase BASE ADDRESS 3 l input 0 output for Port C low nibble l input OQ output for Port B l input O output for Port C high nibble l input O zoutput for Port A Fig 3 2 CFG register format mode 0 The following table lists all p
12. l station i e PC 0 should be set at 0 and PC 3 should be set at 1 before such signals can be inputed For example 1xx0 1000 1010 1100 1110 Although interrupt signals are normally received from external peripherals the PCL 722 can also execute a test output signal to simulate an interrupt being inputed from an external device See the example in next chapter CHAPTER 4 PROGRAMMING 4 1 Programming Notes The signal direction of PCL 722 can be INPUT or OUTPUT by software programming However after power on or hardware front panel RESET button of the PC is pressed reset all the ports of the PCL 722 are automatically configured as INPUT direction The user can OUTPUT data to the port which is configured as INPUT without affecting the input data The output data is latched internally and not transmitted to the part until the port is configured as OUTPUT It is recommended that before initiating the direction configuration of the PCL 722 be sure to set the wanted initial output status first This means that if you want the initial output data of port N is AD in hex FIRST output port N the data AD here then configure port N as output function Refer to the following examples for details INPUT OUTPUT Select From Data Bus gt OUTPUT WR LATCH To Data Bus INPUT RD BUFFER lt 1 The output driver is disabled high impedance when the
13. ossible configured commands to configure 8255 in mode 0 PCL 722 Operation 8255 Mode O Configuration Table PAO PAT7 PC4 PC7 PBO PB7 PCO PC3 n f om input output input 9BH 3 2 Interrupt Handling The PCL 722 has two lines PC 0 PC 3 for each channel to generate hardware interrupt The interrupts are edge triggered 0 traps a rising edge signal while PC 3 traps a falling edge signal To use the interrupts simply insert the appropriate IRQ jumper to select the desired interrupt level IRQ 2 7 Operation PCL 722 To determine which input generated the interrupt read Port C lower bits 0 and 3 to locate the current state of inputs Note that the inputs are not latched and no first event trapping is provided to determine which input was active first The user can select which channel is to be interrupt enable by setting interrupt enable jumpers JO J1 J2 J3 J4 and J5 Refer to the table below NO INTERRUPT REQUEST BUS STATUS RESPONSE NO INTERRUPT REQUEST INTERRUPT REQUEST NO INTERRUPT REQUEST UPT REQUEST if PC 4 Low ERER Interrupt enabled if PC 4 High Interrupt disabled PCL 722 Operation Note In the event that an interrupt signal is generated from a rising edge or a falling edge change and if additional interrupt signals are still to be inputed the bit status must be reset to its origina
14. port is set to INPUT or after RESET Outside 2 The output data written to the port is latched in the OUTPUT DATA LATCH no matter the port is set as INPUT or OUTPUT 3 When the port is set as OUTPUT the input circuit is used as output status read back Programming PCL 722 4 The data in the OUTPUT DATA LATCH is in a random status after power on It must be initialized before setting the port to output direction 4 2 Programming Examples The PCL 722 is easily programmed and the following section lists some program examples All the program examples below have been fully tested on PC XT AT or compatible computers Note The following programs should be run under Turbo C version 1 5 or 2 0 DEMOI C This demo program demonstrates how to use the read back function of the PCL 722 to monitor the output status as HARDWARE SETTING E E 1 Base address set at 0x2C0 i 2 select 144 lines I O by adjusting SW2 include lt stdio h gt include lt conio h gt include lt process h gt include dos h struct channel define channel structure int porta int portB int portC int config main struct channel CN 6 there are si
15. re interrupt Signal is generated the PC will beep alarm PCL 722 Programming include lt dos h gt include lt stdio h gt include lt conio h gt new INT OAH ISR void interrupt alarm void char Port61_Old_Status char Port61_New_Status int DelayTime 0x300 int Count 0 ine i get original port 61H status and save it Port61 New Status Port61 Old Status inportb 0x61 set port 61h bitl 0 Port61 New Status amp Oxfd 1111 1101 in binary for Count 0 Count lt 0x300 Count DelayTime Port61 New Status 0x02 On Off bitl outportb 0x61 Port61 New Status for i 0 i lt DelayTime i outportb 0x61 Port61 Old Status outportb 0x20 0x20 send EOI to 8259 void main int IMR void interrupt Int A Old Vector Int A Old Vector getvect 0x0a get old int Oah ISR setvet OxOa alarm set new int Oah ISR IMR inportb 0x21 get 8259 interrupt mask register initialization outportb 0x2c0 OxO CNO port A outportb 0x2c1 OxO CNO port B outportb 0x2c2 0x08 CNO PC4 O interrupt enable PC3 1 pA PCO O J outportb 0x2c3 0x80 set CNO as output function clrscr printf Press any key to generate
16. x connectors ES int base 0x2c0 set base address at 2CO in hex int portA save read back value of port A int portB save read back value of port B int portC save read back value of port C int i j screen handle x PCL 722 Programming clrscr gotoxy 25 1 textattr 0x70 cputs PCL 722 DEMO PROGRAME gotoxy 1 2 printf Testing CN for i1 0 1 lt 3 1 gotoxy 1 4 1 2 printf Port c output value gt A i i gotoxy 40 4 1 2 printf ReadBack gt calculate port addresses of each CN for i 0 1 lt 6 1 CN i portA base i 4 0 CN i portB base i 4 1 CN i portC base 1 4 2 CN i config base 1 4 3 Initialization outportb CN i portA 0x00 outportb CN i portB 0x00 outportb CN i portC 0x00 outportb CN i config 0x80 all as OUTPUT AAA AA RARA KK KK RARA main program A for i 0 i lt 6 i gotoxy 13 2 73 xf textattr 0x09 print CN number cprintf for 3 0 3 lt 0x100 3 outportb CN i portA j out j to port A gotoxy 25 4 printf 2x j portA inportb CN i portA read back gotoxy 53 4 printf 2x portA if portA j printf 7 beep gotoxy 1 20 textattr 0x09 cprintf CN d port A readback error i getch exit 1 quit to dos outportb CN i portB j out j to port B

Model PCL-722 144 Bit DIO Card

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