MAXQ615 16-Bit MAXQ Microcontroller with Hardware
Contents
1. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Vpp 3 6V lop 11mA 0 4 0 5 V Output Low Voltage Note 7 VoL Vpp 2 4V loL 8mA 0 4 0 5 V Output High Voltage VOH loH 2mA Note 7 Vpp 0 5 VDD V nput Leakage Current I Internal pullup disabled 100 100 nA nput Capacitance Clo 15 pF nput Pullup Resistance Rpy Vpp 3 0V VoL 0 4V 16 28 39 kQ FLASH MEMORY ae Clock During Flash 2 MHz rogramming B i tue Mass erase 20 40 Flash Erase Time ms tERASE Page erase 20 40 Flash Programming Time Per Word tpMG 20 100 Us Write Erase Cycles 20 000 Cycles Data Retention Ta 25 C 100 Years SPI ELECTRICAL CHARACTERISTICS Vpp 1 7V to 3 6V Ta 40 C to 85 C unless otherwise noted AC electrical specifications are guaranteed by design and are not production tested Figures 1 2 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SPI Master Operating Frequency tick fcK 2 MHz SPI Slave Operating Frequency i tsck fck 4 MHz SPI I O Rise Fall Time tsp RE CL 15pF pullup 560Q 8 3 23 6 ns SCLK Output Pulse Width High is 2 MCH MCL MCK 2 SPI_RF ns OSI Output Hold Time After i i 2 t is SCLK Sample Edge MOH MCK SPIRE OSI Output Valid to Sample Edge tMOv twck 2 SPI_RF ns ISO Input Valid to SCLK Sample Edge Rise Fall Setup wis ee ns ISO Input to SCLK Sample t 0 ne Edge Rise Fall Hold MIH SCLK Inactive to MO2. Maxim Integrated Products 19 MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier Revision History REVISION REVISION PAGES NUMBER DATE DESCRIPTION CHANGED 0 3 12 Initial release Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product No circuit patent licenses are implied Maxim reserves the right to change the circuitry and specifications without notice at any time The parametric values min and max limits shown in the Electrical Characteristics table are guaranteed Other parametric values quoted in this data sheet are provided for guidance Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 20 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc
3. gt 2 tp INTERNAL RESET ACTIVE HIGH Figure 5 Power Fail Detection During Normal Operation MAXIM Maxim Integrated Products 14 MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier Table 2 Power Fail Detection States During Normal Operation INTERNAL CRYSTAL SRAM STATE POWER FAIL REGULATOR OSCILLATOR RETENTION COMMENTS A On Off Off Vpp lt Vpor Vpor lt Vpp lt VRST B On On On Crystal warmup time txTaL_RDY CPU held in reset VDD gt VRST 2 am on on E CPU normal operation Power drop too short B gn On on E Power fail not detected Vast lt Vop lt VPFW PFI is set when Vast lt Vpp lt Vpfw and maintains E On On On this state for at least tppw at which time a power fail interrupt is generated if enabled CPU continues normal operation Vpor lt VpD lt VRST On Power fail detected F Periodically o of Yes CPU goes into reset Power fail monitor turns on periodically Vop gt VRST G On On On Crystal warmup time txTaL_RDY CPU resumes normal operation from 8000h VPoR lt Vpop lt VRST On Power fail detected Periodically or oi yes CPU goes into reset Power fail monitor is turned on periodically VoD lt VPOR Off Off Off Device held in reset No operation allowed If a reset is caused by a power fail the power fail moni detection Vpp is monitored for an additional nan
4. ts iss a F a sH lt N ts0v a SE MSB LSB Figure 2 SPI Slave Communications Timing 12C ELECTRICAL CHARACTERISTICS Vpp Vast to Vppomax Ta 40 C to 85 C unless otherwise noted AC electrical specifications and all specifications to Ta 40 C are guaranteed by design and are not production tested Figure 3 PARAMETER SYMBOL CONDITIONS 2 DEED MORE EAST MODE UNITS MIN MAX MIN MAX Supply voltages that mismatch 12C bus levels Input Low Voltage VILI2C must relate input levels to 0 5 0 3 x Vpp 0 5 0 3 x Vpp V the Rp pullup voltage Supply voltages that Input High Voltage v mismatch PCOS fizy 0 7xVpp Vpp 0 5 v P 9 9 IH_I2C must relate input levels to i ur i Do DO i the Rp pullup voltage Output Logic Low Open f Drain or Open Collector VoL2c Vpp gt 2V 3mA sink current 0 0 4 0 0 4 V tR F_12C exceeds tor jac Output Fall Time from which permits Rg to be ViH_MIN to Vit_max with connected as shown in 20 Bus Capacitance from OF_l2c 2C Bus Controller Timing eae 0 1Cg aa i 10pF to 400pF table Cg SDA or SCL capacitance in pF MAAILM Maxim Integrated Products 5 MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier 12C ELECTRICAL CHARACTERISTICS continued Vpp Vast to Vppimax Ta 40 C to 85 C unless otherwise noted AC electrical specifications and all specificat
5. after Vpp exceeds Vast a power on reset the internal oscillator stabilzes and code execu tion begins In Circuit Debug Embedded debug hardware and software are developed and integrated to provide full in circuit debugging capa bility in a user application environment These hardware and software features include e A debug engine e A set of registers providing the ability to set break points on register code or data using debug service routines stored in ROM MAXIM Hardware Multiplier Collectively these hardware and software features sup port two modes of in circuit debug functionality e Background mode CPU is executing the normal user program Allows the host to configure and set up the in circuit debugger e Debug mode The debugger takes over the control of the CPU Read write accesses to internal registers and mem ory Single step of the CPU for trace operation The interface to the debug engine is the JTAG interface To prevent unauthorized access the debug engine pre vents access to system memory Operating Modes Idle Mode The idle mode suspends the processor so that no instructions are fetched and no processing occurs Setting the IDLE bit in the CKCN register to 1 invokes the idle mode The instruction that executes this step is the last instruction prior to halting the program counter Once in idle mode all resources are preserved and all clocks remain active with the enabled peripheral
6. specific MAXQ615 errata sheet e The MAXQ615 User s Guide which contains detailed information on core features and operation including programming Development and Technical Support A variety of highly versatile affordably priced develop ment tools for this microcontroller are available from Maxim and third party suppliers including e Compilers e n circuit emulators e Integrated development environments IDEs A partial list of development tool vendors can be found at www maxim ic com MAXQ_tools For technical support go to https support maxim ic com micro Maxim Integrated Products 18 MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier Ordering Information OPERATING FLASH DATA MEMORY PART VOLTAGE V TEMP RANGE MEMORY KB KB PIN PACKAGE MAXQ615 F00 2 4 to 3 6 40 C to 85 C 48 2 16 TQFN EP Denotes a lead Pb free RoHS compliant package EP Exposed pad Chip Information Package Information PROCESS BiCMOS MAXIM For the latest package outline information and land patterns footprints go to www maxim ic com packages Note that a or in the package code indicates RoHS status only Package drawings may show a different suffix character but the drawing pertains to the package regardless of ROHS status PACKAGE PACKAGE OUTLINE LAND TYPE CODE NO PATTERN NO 16 TQFN EP T1644 4 21 0139 90 0070
7. 01 Sysclk x 216 3 27 25 6 10 Sysclk x 217 6 55 25 6 11 Sysclk x 218 13 4 25 6 MAAXILAVI Maxim Integrated Products 11 MAXQ615 16 Bit MAXQ Microcontroller with General Purpose I O The general purpose I O pins have the following features e CMOS output drivers e Schmitt trigger inputs e Optional weak pullup to VDD when operating in input mode While the microcontroller is in a reset state all port pins become high impedance with input buffers and weak pullups disabled unless otherwise noted From a software perspective each port appears as a group of peripheral registers with unique addresses Special function pins can also be used as general pur pose O pins when the special functions are disabled For a detailed description of the special functions avail able for each pin refer to the user manual for this device 16 Bit Timers Counters The microcontroller provides three timers counters that support the following functions e 16 bit timer counter e 16 bit up down autoreload e Counter function of external pulse e 16 bit timer with capture e 16 bit timer with compare e input output enhancements for pulse width modulation e Set reset toggle output state on comparator match e Prescaler with 2n divider for n O 2 4 6 8 10 Serial Peripherals Serial Peripheral Interface SPI The device provides two SPI ports The SPI is an inter device bus protocol that provides fast synchronous full duple
8. 9 External Interrupt 9 14 P1 1 MISO1 SPI1 Master In Slave Out TBBO Timer BO Pin B INT10 External Interrupt 10 SCLK1 SPI1 SPI Clock 15 P1 2 SCL 12C Clock TBA1 Timer B1 Pin A INT14 External Interrupt 11 SSEL1 SPI1 Slave Select 16 P1 3 SDA 12C Clock TBB1 Timer B1 Pin B EXPOSED PAD EP Exposed Pad Leave EP electrically unconnected MAKII Maxim Integrated Products 9 MAXQ615 16 Bit MAXQ Microcontroller with Block Diagram MAXIM MAXQ615 16 BIT MAXQ REGULATOR RISC CPU VOLTAGE MONITOR 20MHz RING 16 BIT TIMER OSCILLATOR 3x GPIO 16 x 16 MAC SPI 2x JTAG WATCHDOG 12C 48KB 6KB UTILITY FLASH ROM 2KB SRAM Detailed Description The MAXQ615 is a MAXQ20S based microcontroller that supports a variety of applications One application would be power supply sequencing and default voltage programming It could also perform host interface control backlight algorithm fading control and gas gauge algo rithm functions The microcontroller can add bootloader functionality to an application making field updates much simpler Additionally a low power sleep mode makes this device ideal for battery powered equipment Microprocessor The MAXQ20S core supports the Harvard memory archi tecture with separate 16 bit program and data address buses A fixed 16 bit instruction word is standard but data can be arranged in 8 or 16 bits The MAXQ core is implemented as a pi
9. MAKI IVI INNOVATION DELIVERED 19 6254 Rev 0 3 12 MAXQ615 16 Bit MAXQ Microcontroller with General Description Hardware Multiplier Features The MAXQ615 is a low power 16 bit MAXQ microcon troller designed for low power applications The device combines a powerful 16 bit RISC microcontroller and integrated peripherals including multiple high speed serial communication interfaces and flexible port I O High speed communication interfaces include dual SPI and l2C The device also provides three instances of the 16 bit timer B peripheral A 16 x 16 hardware multiply accumulate with 48 bit accumulator provides support for computationally intensive applications The device provides 48KB of flash memory and 2KB of data SRAM For the ultimate in low power performance the device includes an ultra low power stop mode 0 2uA typ In this mode the minimum amount of circuitry is powered Wake up sources include external interrupts the power fail interrupt and a timer interrupt The microcontroller runs from a single 2 4V to 3 6V power supply operating voltage Applications Portable Computing Battery Powered Portable Equipment Consumer Electronics Home Appliances White Goods MAXQ is a registered trademark of Maxim Integrated Products Inc Core Functionality lt High Performance Low Power 16 Bit MAXQ20S RISC Core lt DC to 20MHz Operation Across Entire Operating Range lt 2 4V to 3 6V Operat
10. ROM is a block of internal ROM that defaults to a starting address of 8000h The utility ROM consists of subroutines that can be called from application software These include the following e In system programming using bootstrap loader e Read chip revision or manufacturer ID e Test routines internal memory tests memory loader etc e User callable routines for in application flash pro gramming and fast table lookup Following any reset execution begins in the utility ROM The ROM software determines whether the program execution should immediately jump to location OOOOh the start of system code or to one of the special routines mentioned Routines within the utility ROM are user accessible and can be called as subroutines by the application software More information on the utility ROM functions is contained in the user manual Loading Flash Memory with the Bootstrap Loader An internal bootstrap loader allows the device to be reloaded over the JTAG interface This allows software to be upgraded in system eliminating the need for a costly Hardware Multiplier hardware retrofit when updates are required Remote software uploads are possible that enable physically inaccessible applications to be frequently updated If in system programmability is not required a commercial gang programmer can be used for mass programming Watchdog Timer An internal watchdog timer greatly increases system reli ability The timer rese
11. SI Inactive MLH tMCK 2 tsp RFE ns MAXIM Maxim Integrated Products MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier SPI ELECTRICAL CHARACTERISTICS continued Vpp 1 7V to 3 6V Ta 40 C to 85 C unless otherwise noted AC electrical specifications are guaranteed by design and are not production tested Figures 1 2 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Input Pulse Width High Low i tscH tscL tscK 2 ns SSEL Active to First Shift t t ma Edge SSE SPI_RF MOSI Input to SCLK Sample t t Edge Rise Fall Setup SIS SPIRE MOSI Input from SCLK Sample t t Edge Transition Hold SiH SPIRE MISO Output Valid After SCLK i ot ce Shift Edge Transition SOV SPILRE SSEL Inactive tssH tck tsp RF ns SCLK Inactive to SSEL Rising tsp tSPI_ RF ns MISO Output Disabled After t Stew 2t SSEL Edge Rise SLH CK 2 SPI_RF SHIFT SAMPLE SHIFT SAMPLE SCLK j CKPOL CKPHA i i 4 DESTES SCLK me ss CKPOL CKPHA MoH P e iin a MSB MSB 1 Figure 1 SPI Master Communications Timing MAAXILAVI Maxim Integrated Products 4 o dJa tSsE Bi MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier SHIFT SAMPLE SHIFT SAMPLE 1 0 lt tscK y SCLK CKPOL CKPHA SCLK CKPOL CKPHA 0 1 m SCH Bet SCL D gt gt lt lt
12. e device into stop mode The nanopower ring oscillator is an internal ultra low power 400nA 8kHz ring oscillator that can be used to drive a wake up timer that exits stop mode The wake up timer is programmable by software in steps of 125us up to approximately 8s The power fail monitor is always on during normal oper ation However it can be selectively disabled during stop mode to minimize power consumption This feature is enabled using the power fail monitor disable t lt tPFw gt lt lt gt Pw Hardware Multiplier PFD bit in the PWCN register The reset default state for the PFD bit is 1 which disables the power fail monitor function during stop mode If power fail monitoring is dis abled PFD 1 during stop mode the circuitry respon sible for generating a power fail warning or reset is shut down and neither condition is detected Thus the Vpp lt Vrst condition does not invoke a reset state However in the event that Vpp falls below the POR level a POR is generated The power fail monitor is enabled prior to stop mode exit and before code execution begins If a power fail warning condition Vpp lt VpFw is then detected the power fail interrupt flag is set on stop mode exit If a power fail condition is detected Vpp lt VRST the CPU goes into reset Power Fail Detection Figure 5 6 and 7 show the power fail detection and response during normal and stop mode operation gt t gt tprw lt
13. e not production tested PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD VRST 3 6 V 1 8V Internal Regulator VREG18 1 62 1 7 1 98 V Power Fail Warning Voltage VPFW Monitors Vpp Notes 1 2 2 45 2 6 2 75 V Power Fail Reset Voltage VRST Monitors Vpp Note 3 2 35 2 4 2 45 V Power On Reset Voltage VPOR Monitors Vpp 1 0 1 45 V Supply Current IDD1 fck 20MHz Note 4 2 6 4 5 mA Idle Current IDLE Note 5 1 0 750 850 UA Ta 25 C 0 3 3 0 i Ta 0 C to 70 C 1 12 Ta 40 C to 85 C 2 16 Stop Mode Current HA Ta 25 C 22 0 35 0 sl Ta 0 C to 70 C 220 42 0 Ta 40 C to 85 C 22 0 45 Stop Mode Resume Time ton 300 Us Power Fail Monitor Startup Time term on Note 6 150 Us A i Warning Detection DEN 10 us CLOCK SOURCE E Oscillator fck 15 20 MHz Ring Oscillator Duty Cycle CLK DUTY 45 55 System Clock Frequency tek fck MHz System Clock Period fck I foK ns DIGITAL I O Input Hysteresis VIHYS Vpp 3 3V Ta 25 C 300 mV Input Low Voltage VIL VGND 0 3 x VDD V Input High Voltage VIH 0 7 x VDD VDD V MAXIM Maxim Integrated Products 2 MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier RECOMMENDED DC OPERATING CONDITIONS continued Vpp Vast to Vopimax Ta 40 C to 85 C unless otherwise noted Typical values are m easured at Ta 25 C AC electrical specifications and all specifications to Ta 40 C are guaranteed by design and are not production tested
14. ep any bypass capacitor leads short for best noise rejection and place the capaci tors as close to the leads of the devices as possible CMOS design guidelines for any semiconductor require that no pin be taken above Vpp or below GND Violation of this guideline can result in a hard failure damage to the silicon inside the device or a soft failure uninten tional modification of memory contents Voltage spikes above or below the device s absolute maximum ratings can potentially cause a catastrophic latchup of the device Microcontrollers commonly experience negative volt age spikes through either their power pins or general purpose I O pins Negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses Devices such as keypads can con duct electrostatic discharges directly into the microcon troller and seriously damage the device System design ers must protect components against these transients that can corrupt system memory MAXIM Designers must have the following documents to fully use all the features of this device This data sheet contains pin descriptions feature overviews and electrical specifications Errata sheets contain deviations from published specifications The user s guide offers detailed information about device features and operation e This MAXQ615 data sheet which contains electrical timing specifications and pin descriptions e The revision
15. event is detected Refer to the user manual for detailed information Note 7 The maximum total current Ion max and loL max for all listed outputs combined should not exceed 32mA to satisfy the maximum specified voltage drop MAAXIAVI Maxim Integrated Products 7 MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier Pin Configuration TOP VIEW P0 7 TDO INT7 P0 6 TMS INT P0 5 TDI INT5 PO4 TCK INT4 P1 0 MOSI1 TBAO INTS 13 PI MISOV TBBOINTS 14 a LAA MAXQ6IG p PL2 SCLKY SCL TBAT INTIO 15 16 Voo P1 3 SSEL1 SDA TBBY INTI1 16 4 gt 15 PO INT3 SSELO PO A INT1 MISOO PO 2 INT2 SCLKO P0 0 INTO Mosio 5 Pin Description PIN NAME FUNCTION POWER PINS 6 Vpp Digital Supply Voltage 8 GND Digital Ground Regulator Capacitor This pin must be connected to ground through an external 1uF external 7 REG18 ceramic chip capacitor This capacitor should be placed as close as possible to this pin No other device may be attached to this pin RESET PINS Active Low Reset This bidirectional pin recognizes external active low reset inputs and employs an internal pullup resistor to allow for a combination of wired OR external reset sources An RC is not required for power up as this function is provided internally This pin also acts as an output when the source of the reset is internal to the device e g watchdog timer power fail etc I
16. ing Voltage lt Three Independent Data Pointers Accelerate Data Movement with Automatic Inc Dec lt Dedicated Pointer for Direct Read from Code Space lt 16 Bit Instruction Word 16 Bit Data Bus lt 16 x 16 Bit General Purpose Working Registers lt Optimized for C Compiler Memory lt 48KB Flash Memory 1KB Page Sectors 20 000 Erase Write Cycles per Sector lt 2KB Data SRAM lt Masked ROM Available I O and Peripherals lt Power Fail Warning lt Power On Reset Brownout Reset lt Three 16 Bit Programmable Timers Counters with Prescaler lt Programmable Watchdog Timer lt Internal 20MHz Clock 5 lt Dual SPI Ports with 16 Byte FIFO lt 2C Communication Port lt Up to 12 General Purpose I O Pins Low Power Consumption lt 0 2pA typ in Stop Mode lt 2 6mA typ at 20MHz lt Divided System Clock Modes Available Ordering Information appears at end of data sheet For related parts and recommended products to use with this part refer to www maxim ic com MAXQ615 related Note Some revisions of this device may incorporate deviations from published specifications known as errata Multiple revisions of any device may be simultaneously available through various sales channels For information about device errata go to www maxim ic com errata MAXIM Maxim Integrated Products 1 For pricing delivery and ordering information please contact Maxim Direct at 1 888 629 4642
17. ions to Ta 40 C are guaranteed by design and are not production tested Figure 3 STANDARD MODE FAST MODE PARAMETER SYMBOL CONDITIONS UNITS MIN MIN MAX Pulse Width of Spike Filtering That Must Be tsp_l2c 0 50 ns Suppressed by Input Filter Input voltage from Input Current on I O lIN_12C 0 1 x Vpn to 0 9 x Vpp 10 10 10 10 pA I O Capacitance Cio_12C 10 10 pF 12C BUS CONTROLLER TIMING Figure 4 STANDARD MODE FAST MODE PARAMETER SYMBOL UNITS MIN MAX MIN MAX 12C Bus Operating Frequency floc 0 100 0 400 kHz System Frequency fsys 0 90 3 60 MHz 12C Bit Rate floc fsys 8 fsys 8 Hz Hold Time After Repeated START tHD STA 4 0 0 6 Us Clock Low Period tLlow_l2c 4 7 1 3 Us Clock High Period tHIGH_l2C 4 0 0 6 Us Setup Time for Repeated START tsu STA 4 7 0 6 Us Hold Time for Data tHD DAT 0 3 45 0 0 9 Us Setup Time for Data tsU DAT 250 100 ns SDA SCL Fall Time tF_12C 300 20 0 1Cg 300 ns SDA SCL Rise Time tR lec 1000 20 0 1CB 300 ns Setup Time for STOP tsu STO 4 0 0 6 Us Bus Free Time Between STOP and START tBUF 4 7 1 3 Us Capacitive Load for Each Bus Line Cp 400 400 pF Noise Margin at the Low Level for Each Connected Device Including VnL_l2c 0 1 x Vpp 0 1 x VDD V Hysteresis Noise Margin at the High Level for Each Connected Device Including VnH_I2C 0 2 x Vpp 0 2 x VDD V Hysteresis MAXIM Maxim Integrated Produc
18. n this case the pin is low while the processor is in a reset state and returns high as the processor exits this state MAAXILAVI Maxim Integrated Products 8 MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier Pin Description continued PIN NAME FUNCTION GENERAL PURPOSE I O PINS General Purpose Digital I O Pins These port pins function as general purpose I O pins with their input and output states controlled by the PDO POO and PIO registers All port pins default to high impedance mode after a reset Software must configure these pins after release from reset to remove the high impedance condition All alternate functions must be enabled from software before they can be used ALTERNATE FUNCTION DESCRIPTION INTO External Interrupt O 2 PO O MOSIO SPIO Master Out Slave In INT1 External Interrupt 1 3 PO 1 MISOO SPIO Master In Slave Out INT2 External Interrupt 2 4 PO 2 SCLKO SPIO SPI Clock INT3 External Interrupt 3 5 P0 3 SSELO SPIO Slave Select INT4 External Interrupt 4 9 PO 4 TCK JTAG Test Clock INT5 External Interrupt 5 10 PO 5 TDI JTAG Data In INT6 External Interrupt 6 1A P0 6 TMS JTAG Test Mode Select INT7 External Interrupt 7 12 POT TDO JTAG Data Out INT8 External Interrupt 8 13 P1 0 MOSI1 SPI1 Master Out Slave In TBAO Timer BO Pin A INT
19. ons require preventative measures to protect against simple access and viewing of program code memory To address this need for code protection the device permits full access to in system programming in application programming or in circuit debugging only after a password has been supplied The password is defined as the 16 words of physical program memory at addresses 0010h 001Fh These memory locations can be used for general code space if a unique password is not needed When the password lock bit PWL is set to 1 password is required in order to access the ROM loader utilities that support read write accessing of internal memory and debug functions When PWL is cleared to O these utili ties are fully accessible through the utility ROM without password The PWL bit defaults to 1 by a power on reset In order to access the ROM utilities a correct password is needed otherwise access of ROM utilities is denied Once the correct password has been supplied by the user the ROM clears the password lock The PWL remains clear until a power on reset occurs or it is set by application software Maxim Integrated Products 10 MAXQ615 16 Bit MAXQ Microcontroller with The password can be entered through the bootloader interface selected by the PSS1 and PSSO bits in sys tem programming when the SPE bit is set to logic 1 or selected through the TAP interface directly by issuing a password unlock command Utility ROM The utility
20. opow tor can be set to one of the following intervals e Always on continuous monitoring e 211 nanopower ring oscillator clocks 256ms e 212 nanopower ring oscillator clocks 512ms e 213 nanopower ring oscillator clocks 1 024s In the case where the power fail circuitry is periodically turned on the power fail detection is turned on for two nanopower ring oscillator cycles If Vpp gt Vrst during MAXIM er ring oscillator period If Vpp remains above Vast for the third nanopower ring period the CPU exits the reset state and resumes normal operation from utility ROM at 8000h after satisfying the crystal warmup period If a reset is generated by any other event such as the RESET pin being driven low externally or the watchdog timer the power fail internal regulator and crystal remain on during the CPU reset In these cases the CPU exits the reset state in less than 20 crystal cycles after the reset source is removed Maxim Integrated Products 15 MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier t lt tpew ea te Pret i i t gt tprw m INTERNAL RESET ACTIVE HIGH Figure 6 Stop Mode Power Fail Detection States with Power Fail Monitor Enabled Table 3 Stop Mode Power Fail Detection States with Power Fail Monitor Enabled INTERNAL CRYSTAL SRAM STATE REWER rae REGULATOR OSCILLATOR RETENTION CONMENTS Application enters stop mode A On Off Off Yes V
21. or visit Maxim s website at www maxim ic com MAXQ615 16 Bit MAXQ Microcontroller with ABSOLUTE MAXIMUM RATINGS All voltages relative to GND Voltage Range ON Vp iriiria 0 3V to 3 6V Voltage Range on Any Lead 0 3V to Vpp 0 5V Continuous Output Current Any SinGle O Pit sigs cesssesssnes anene see eases 32mA All 1 0 Pins COMPING isiecss isuti ntria 32mA Hardware Multiplier Continuous Power Dissipation Ta 70 C TQEFN derate 16 9mW C above 70 C ee 1349mW Operating Temperature Range ee 40 C to 85 C Storage Temperature Range 65 C to 150 C Lead Temperature soldering 10S eeeeeee 300 C Soldering Temperature refloW 0 eceeeeee eee 260 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional opera tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability RECOMMENDED DC OPERATING CONDITIONS Vpp Vast to Vpp max Ta 40 C to 85 C unless otherwise noted Typical values are measured at Ta 25 C AC electrical specifications and all specifications to Ta 40 C are guaranteed by design and ar
22. pelined processor with performance approaching 1MIPS per MHz The 16 bit data path is implemented around register modules and each register module contributes specific functions to the core The accumulator module consists of sixteen 16 bit registers and is tightly coupled with the arithmetic logic unit ALU Program flow is supported by a configurable soft stack Execution of instructions is triggered by data transfer between functional register modules or between a func tional register module and memory Since data movement MAXIM Hardware Multiplier involves only source and destination modules circuit switching activities are limited to active modules only For power conscious applications this approach localizes power dissipation and minimizes switching noise The modular architecture also provides a maximum of flexibil ity and reusability that are important for a microprocessor used in embedded applications The MAXQ instruction set is highly orthogonal All arith metic and logical operations can use any register in conjunction with the accumulator Data movement is sup ported from any register to any other register Memory is accessed through specific data pointer registers with auto increment decrement support Memory The microcontroller incorporates several memory types e 48KB flash memory e 2KB SRAM e 6KB utility ROM e RAM based software stack Password Protected Memory Access Some applicati
23. pp gt VRST CPU in stop mode Power drop too short B on om oi ves Power fail not detected Vast lt Vpp lt VpFw Power fail warning detected C On On On Yes Turn on regulator and crystal Crystal warmup time txTAL_RDY Exit stop mode Application enters stop mode D On Off Off Yes VDD gt VRST CPU in stop mode VPoR lt Vpp lt VRST On Power fail detected E Periodically oF on ues CPU goes into reset Power fail monitor is turned on periodically VDD lt Vpor j ort oti of E Device held in reset No operation allowed MAAXIAVI Maxim Integrated Products 16 MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier INTERNAL RESET ACTIVE HIGH INTERRUPT Figure 7 Stop Mode Power Fail Detection with Power Fail Monitor Disabled Table 4 Stop Mode Power Fail Detection States with Power Fail Monitor Disabled STATE POWER FAIL Off INTERNAL REGULATOR Off CRYSTAL OSCILLATOR Off SRAM RETENTION Yes COMMENTS Application enters stop mode VDD gt VRST CPU in stop mode Off Off Off Yes Vpp lt VpFw Power fail not detected because power fail monitor is disabled On Yes Vast lt Vop lt VpFw An interrupt occurs that causes the CPU to exit stop mode Power fail monitor is turned on detects a power fail warning and sets the po
24. s and power monitor continue to work so the processor can exit the idle state using any of the interrupt sources that are enabled The IDLE bit is cleared automatically once the idle state is exited allowing the processor to execute the instruction that immediately follows the instruction that set the IDLE bit To conserve power consumption application can put the processor into idle mode when code execution is not required One example of use is for SP communication The application code can preload SPI FIFO with desired number of bytes for transmission and then put the pro cessor into idle mode The device continues with the SPI transaction and only interrupts the processor when the enabled SPI interrupts are generated Another use is to configure one of the timers to interrupt the device at a predetermined interval The application code can finish its task and then put the processor into idle mode The timer then wakes up the processor when the specified interval has elapsed Maxim Integrated Products 13 MAXQ615 16 Bit MAXQ Microcontroller with Stop Mode The lowest power mode of operation for the device is stop mode In this mode CPU state and memories are preserved but the CPU is not actively running Wake up sources include external O interrupts the power fail warning interrupt or a power fail reset Any time the microcontroller is in a state where code does not need to be executed the user software can put th
25. s can be performed with out requiring direct intervention of the microcontroller core e Unsigned 16 bit multiplication e Unsigned 16 bit multiplication and accumulation e Unsigned 16 bit multiplication and subtraction e Signed 16 bit multiplication e Signed 16 bit multiplication and negate e Signed 16 bit multiplication and accumulation e Signed 16 bit multiplication and subtraction Each of these operations is controlled and accessed through six SFR registers The 8 bit multiplier control reg ister MCNT selects the operation data type operand count optional hardware based square function write option on the MC register the overflow flag and the clear control for operand registers and accumulator Loading and unloading of the data is achieved through five 16 bit SFR registers Only one cycle is needed for computation This means that the result of an operation is ready in the next cycle immediately following the loading of the last operand Back to back operations can be performed without wait states between operations independent of data type and operand count Clock Sources All operations are synchronized to a single internal sys tem clock The clock runs at approximately 20MHz More information on the clock timing is contained in the electri cal tables of this data sheet Internal clock divisors are available to reduce power consumption and or improve compatibility with slower peripherals Approximately 25us
26. the selected slave must drive MISO I2C Bus The microcontroller provides an internal 12C bus master slave for communication with a wide variety of other I2C enabled peripherals The 2C bus is a 2 wire bidirec tional bus using two bus lines the serial data line SDA and the serial clock line SCL and a ground line Both the SDA and SDL lines must be driven as open collector drain outputs External resistors are required to pull the lines to a logic high state The device supports both the master and slave proto cols In the master mode the device has ownership of the 12C bus drives the clock and generates the START and STOP signals This allows it to send data to a slave or receive data from a slave as required In slave mode the device relies on an externally generated clock to drive SCL and responds to data and commands only when requested by the 12C master device Hardware Multiplier The internal hardware multiplier supports high speed multiplications The multiplier can complete a 16 bit x 16 bit multiply and accumulate subtract operation in a single cycle with the support of a 48 bit accumulator The multiplier is a fixed point arithmetic unit The operands can be either signed or unsigned numbers but the data type must be defined by the application software prior to loading the operand registers Maxim Integrated Products 12 MAXQ615 16 Bit MAXQ Microcontroller with Seven different multiply operation
27. ts 6 MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier VDD t 2c MAXIM DEVICE MAXQ615 ttc xt gt tLow_I2c gt tHD STA tHD DAT gt NOTE TIMING REFERENCED TO Vin_j2c min AND VIL_I2C MAX Figure 4 IC Bus Controller Timing Diagram Note 1 The user application must check the status of the power fail warning flag before writing to flash memory to ensure com plete write operations Writes to flash memory must not be performed when the supply voltage drops below the power fail warning levels Note 2 The power fail warning monitor and the power fail reset monitor track each other with a typical delta between the two of 0 13V at minimum power fail warning selection Note 3 The power fail reset and POR detectors operate in tandem so one or both of these signals is active at all times when Vpp lt Vast ensuring the device maintains the reset state until minimum operating voltage is achieved Note 4 Measured on the Vpp pin and the part not in reset All inputs are connected to GND or Vpp Outputs do not source sink any current Part is executing code from flash memory Note 5 Measured on the Vpp pin and the part not in reset All inputs are connected to GND or Vpp Outputs do not source sink any current Program execution is halted in idle mode Note 6 The minimum amount of time that Vpp must be below Vpp before a power fail
28. ts the device if software execution is disturbed The watchdog timer is a free running coun ter designed to be periodically reset by the application software If software is operating correctly the counter is periodically reset and never reaches its maximum count However if software operation is interrupted the timer does not reset triggering a system reset and option ally a watchdog timer interrupt This protects the system against electrical noise or electrostatic discharge ESD upsets that could cause uncontrolled processor opera tion The internal watchdog timer is an upgrade to older designs with external watchdog devices reducing sys tem cost and simultaneously increasing reliability The watchdog timer functions as the source of both the watchdog timer timeout and the watchdog timer reset The timeout period can be programmed in a range of 215 to 232 system clock cycles An interrupt is gener ated when the timeout period expires if the interrupt is enabled All watchdog timer resets follow the pro grammed interrupt timeouts by 512 system clock cycles If the watchdog timer is not restarted for another full interval in this time period a system reset occurs when the reset timeout expires Table 1 Watchdog Timer Intervals fsyscLk 20MHz CD 1 0 00 WD 1 0 WATCHDOG INTERRUPT WATCHDOG INTERRUPT WATCHDOG RESET AFTER TIMEOUT PERIOD ms WATCHDOG INTERRUPT ps 00 Sysclk x 215 1 62 25 6
29. wer fail interrupt flag Turn on regulator and crystal Crystal warmup time txTAL_RDY On stop mode exit CPU vectors to the higher priority of power fail and the interrupt that causes stop mode exit MAXIM Maxim Integrated Products 17 MAXQ615 16 Bit MAXQ Microcontroller with Hardware Multiplier Table 4 Stop Mode Power Fail Detection States with Power Fail Monitor Disabled continued Applications Information INTERNAL CRYSTAL SRAM STATE POWERS ME REGULATOR OSCILLATOR RETENTION COMMENTS Application enters stop mode D Off Off Off Yes Vpp gt VRST CPU in stop mode Vpor lt Vpp lt VRST An interrupt occurs that causes the CPU to exit On stop mode E Periodically Of alt Li Power fail monitor is turned on detects a power fail puts CPU in reset Power fail monitor is turned on periodically VDD lt VPOR j am on on _ Device held in reset No operation allowed Additional Documentation The low power high performance RISC architecture of this device makes it an excellent fit for many portable or applications requiring security Grounds and Bypassing Careful PCB layout significantly minimizes system level digital noise that could interact with the microcontroller or peripheral components The use of multilayer boards is essential to allow the use of dedicated power planes The area under any digital components should be a continu ous ground plane if possible Ke
30. x communications between devices The integrated SPI interface acts as either an SPI master or slave device The master drives the synchronous clock and selects which of several slaves is being addressed Every SPI peripheral consists of a single shift register and control circuitry so that an addressed serial peripheral interface SPI peripheral is simultaneously transmitting and receiv ing The maximum SPI master transfer rate is Sysclk 2 When operating as an SPI slave the device can support up to Sysclk 4 SPI transfer rate Data can be transferred MAXIM Hardware Multiplier as an 8 bit or 16 bit value MSB first In addition the SPI module supports configuration of the active SSEL state through the slave active select pin Four signals are used in SPI communication e SCLK The synchronous clock used by all devices The master drives this clock and the slaves receive the clock Note that SCLK can be gated and need not be driven between SPI transactions e MOSI Master out slave in This is the main data line driven by the master to all slaves on the SPI bus Only the selected slave clocks data from MOSI e MISO Master in slave out This is the main data line driven by the selected slave to the master Only the selected slave may drive this circuit In fact it is the only circuit in the SPI bus arrangement that a slave is ever permitted to drive e SSEL This signal is unique to each slave When active generally low
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