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Correction for Incorrect Description Notice RL78/L1C Descriptions in

1. STOP instruction execution N Standby release signal interrupt request 2014 Renesas Electronics Corporation All rights reserved ENESAS Date September 17 2014 New 34 9 RAM Data Retention Characteristics Ta 40 to 85 C Vss 0 V Data retention supply VDDDR 1 46Note 3 6 V voltage Note This depends on the POR detection voltage For a falling voltage data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated STOP mode e Operation mode STOP instruction execution Standby release signal interrupt request E A Page 16 of 17 RENESAS TECHNICAL UPDATE TN RL A033A E 10 35 9 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Page 1294 Old 0 D OP J ata Memo MOE OM DR DITaQqe ata Y AIAN SIA gt Y AS A ARA Y Ta PARANA Ta 40 to 105 C Data retention supply VDDDR 1 44 3 6 V voltage Note The value depends on the POR detection voltage When the voltage drop data is retained before a POR reset is effected but data is not retained when a Sg POR r is effected 1 STOP mode Operation mode Data retention mode STOP instruction execution o Standby release signal interrupt request 2014 Renesas Electronics Corporation All rights reserved E
2. 2014 Renesas Electronics Corporation All rights reserved ENESAS Date September 17 2014 Correct Figure 15 95 Timing Chart of SNOOZE Mode Operation EOCm1 0 SSECm 0 1 CPU operation status Normal operation STOP model lt 4 gt Normal operation SS01 lt 3 gt ST01 lt 1 gt a A SWCO EOC01 L O SSECO L Clock request signal ANA internal signal Receive data 2 SDRO1 Receive data 1 f9 gt 4 Reade RxDO pin E Receive data 1 X P SP ST Receive data2 X P SP Shift register 01 2 Sin operation SA 20 Sfi operafon y INTSRO INTSREO L Data reception Data TSFO1 lt 2 gt lt 8 gt omitted Page 10 of 17 RENESAS TECHNICAL UPDATE TN RL A033A E It is correction of CPU operation status Clock request signal internal signal INTSRO and TSF01 in this Figure Incorrect Figure 15 96 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 0 CPU operation status Normal operation STOP mode SNOOZE mode Normal operation gt lt 4 SSo1 lt 3 gt lt 12 gt STo1 lt 1 gt po 10 gt AAA SWCO EOCO1 SSECO L Clock request signal O y internal signal Receive data 2 SDRO1 o E ee Receive data 1 IA ira Read RxDO pin a __ Receive data1 AP SP ST f___ Receive data2___XP SP Shift p qu su register 01 PO KX Shit operation X Xt Shit peration XX INTSRO y i l I 9 TSFO1 lt 2 gt lt 5 gt lt b gt lt B gt
3. conversontine Seow arrasa zmr or se Differential linearity error 2 12 bit resolution 09 12 LB Notes 1 TYP Value is the average value at AVpp AVrerr 3 V and Ta 25 C MAX value is the average value 30 at normalized distribution 2 These values are the results of characteristic evaluation and are not checked for shipment 3 Excludes quantization error 1 2 LSB Cautions 1 Route the wiring so that noise will not be superimposed on each power line and ground line and insert a capacitor to suppress noise In addition separate the reference voltage line of AVrerr from the other power lines to keep it free from the influences of noise 2 During A D conversion keep a pulse such as a digital signal that abruptly changes its level from being input to or output from the pins adjacent to the converter pins and P20 to P27 and P150 to P154 O 2014 Renesas Electronics Corporation All rights reserved 2ENESAS E RENESAS TECHNICAL UPDATE TN RL A033A E Date September 17 2014 New 1 When reference voltage AVrerrP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 target for conversion ANI2 to ANI12 Ta 40 to 85 C 2 4 V lt AVrerr lt AVop Voo lt 3 6 V Vss 0 V AVss 0 V Reference voltage AVrerr Reference voltage AVrerm 0 V HALT mode Fean e O Tra earn CO sn O MECA wea ts conversion tine Seow arrasa zmr ar se Differential lineari
4. Incorrect descriptions 21 4 3 Multiple interrupt servicing Table 19 5 Relationship Between Interrupt Requests Page 1029 Incorrect descriptions Enabled for Multiple Interrupt Servicing g revised During Interrupt Servicing 34 6 1 34 6 1 A D converter characteristics Specifications Page 1221 changed 34 9 Data Memory STOP Mode Low Supply Voltage Data Page 1234 Content change Retention Characteristics 35 8 Data Memory STOP Mode Low Supply Voltage Data Page 1294 Content change Retention Characteristics Document Improvement The above corrections will be made for the next revision of the User s Manual Hardware 2014 Renesas Electronics Corporation All rights reserved Page 1 of 17 ENESAS RENESAS TECHNICAL UPDATE TN RL A033A E Date September 17 2014 Corrections in the User s Manual Hardware Corrections and Applicable Items Pages in this E document for English RO1UHO409EJO200 Illia 3 3 4 Special function registers SFRs Table 3 8 SFR List Pages 82 and 83 Page 3 and 4 6 3 3 Timer mode register mn TMRmn Figure 6 17 Format of Timer mode register mn TMRmn 4 4 mage Zhe Pages 5 3 9 High speed on chip oscillator trimming register HIOTRM Page 186 15 5 7 SNOOZE mode function Timing Chart of SNOOZE Mode Operation Figure 14 74 and Pages 663 and 665 Page 7 and 8 Figure 14 76 5 15 6 3 SNOOZE mode function Page 688 15 6 3 SNOOZE mode function Pages 690 691 and Timing Chart of SNOOZE Mode Operation
5. MBW Setting other bits is invalid due to normal mode Setting other bits is invalid due to normal mode DTBLSj 01H Sz 0 Max Packet Size DTBLSj 01H Sz 0 Max Packet Size DTC block size Sz 0 1 byte Sz 1 2 bytes Sz 1 Max Packet Size 2 DTC block size Sz 0 1 byte Sz 1 2 bytes Sz 1 Max Packet Size 2 DTCCTj Any value Max 256 times Any value Max 256 times precy Any value Max 256 times Any value Max 256 times DTDARI FIFO Read direction Data transfer destination address Destination address FIFO Write direction DOFIFODO0 D1FIFODOO DTSARI FIFO Read direction DOFIFODOO D1FIFODOO Source address FIFO Write direction Data transfer source address Caution j DOFIFO D1FIFO are assigned to activation source 0 23 For details of DTC setting see CHAPTER 19 DATA TRANSFER CONTROLLER O 2014 Renesas Electronics Corporation All rights reserved RENESAS Page 13 of 17 E RENESAS TECHNICAL UPDATE TN RL A033A E Date September 17 2014 8 34 6 1 A D converter characteristics p 1221 Voltage Range of A D conversion was extended Old 1 When reference voltage AVrerrP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 target for conversion ANI2 to ANI12 Ta 40 to 85 C 2 7 V lt AVrere lt AVop Von lt 3 6 V Vss 0 V AVss 0 V Reference voltage AVrerr Reference voltage AVrerm 0 V HALT mode re TOO Tra earn a sn O MECA we te
6. Figure 15 95 Figure 693 i 15 96 and Figure 15 96 7 17 4 5 3 DTC Transfers DOFIFO and D1FIFO Ports 21 4 3 Multiple interrupt servicing Table 19 5 Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing 34 6 1 34 6 1 A D converter characteristics Page 1221 Page 16 and 17 EM 10 34 9 Data Memory STOP Mode Low Supply Voltage Data Retention Page 1234 Page 18 Characteristics 41 35 8 Data Memory STOP Mode Low Supply Voltage Data Retention Page 1294 Page 20 Characteristics Incorrect Bold with underline Correct Gray hatched Page 10 to 12 Page 1029 Page 14 Revision History RL78 L1C Correction for incorrect description notice Document Number Issue Date TN RL A033A E Sep 17 2014 First edition issued Corrections No 1 to No 11 revised this document 2014 Renesas Electronics Corporation All rights reserved Page 2 of 17 ENESAS RENESAS TECHNICAL UPDATE TN RL A033A E Date September 17 2014 1 3 3 4 Special function registers SFRs Table 3 7 SFR List Page 82 and 83 Incorrect Correct Table 3 7 SFR List 1 4 Table 3 7 SFR List 1 4 Address Special Function Register SFR Name Symbol R W a Bit Manipulable Bit Range After Reset Address Special Function Register SFR Name Symbol R W ae Bit Manipulable Bit Range After Reset 16 bit 16 bit omitted omitted FFF10H Serial data register 00 TXDO SDROO a oe Mi y 0000H F
7. Incorrect Correct Operation mode setting of starting counting and interrupt Operation mode MD Setting of starting counting and interrupt mn 0 Value set by the MDmn3 to MDmn1 bits Value set by the MDmn3 to MDmn1 bits 0 see the table above see the table above Timer interrupt is not generated when counting is started e Interval timer mode Timer interrupt is not generated when counting is started timer output does not change either 0 0 0 timer output does not change either Timer interrupt is generated when counting is started e Capture mode 1 Timer interrupt is generated when counting is started timer output also changes 0 1 0 timer output also changes e Interval timer mode 0 O 0 e Capture mode 0 1 0 Timer interrupt is not generated when counting is started timer output does not change either N 2 e One count mode 1 0 0 At that time interrupt is not generated 1 0 0 At that time interrupt is not generated Note a Note 3 Start trigger is valid during counting operation i i r 1 Start trigger is valid during counting operation At that time interrupt is not generated o Start trigger is invalid during counting operation e One count mode i Start trigger is invalid during counting operation e Capture amp one count mode 1 1 0 timer output does not change either 1 1 0 timer output does not change either Start trigger is invalid during coun
8. chip Oscillator HOCO Clock Frequency Correction RO1AN0464 2014 Renesas Electronics Corporation All rights reserved ENESAS Date September 17 2014 Correct 5 3 9 High speed on chip oscillator trimming register HIOTRM omitted Figure 5 14 Format of High Speed On Chip Oscillator Trimming Register HIOTRM Address FO0AOH After reset undefined R W Symbol HIOTRM res HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO High speed on chip oscillator Minimum speed Minimum speed ACI ICI CI CO CI CT E IS AAA AAA ee Note The value after reset is the value adjusted at shipment Remarks 1 The HIOTRM register holds a six bit value used to adjust the high speed on chip oscillator with an increment of 1 corresponding to an increase of frequency by about 0 05 Remark 2 For the usage example of the HIOTRM register see the application note for RL78 MCU series High speed On chip Oscillator HOCO Clock Frequency Correction RO1AN0464 Page 6 of 17 RENESAS TECHNICAL UPDATE TN RL A033A E 4 15 5 7 SNOOZE mode function Timing Chart of SNOOZE Mode Operation Fi 15 76 Pages 663 and 665 It is correction of CPU operation status Clock request signal internal signal and TSF00 in this Figure ure 15 74 and Figure Incorrect Figure 15 74 Timing Chart of SNOOZE Mode Operation once startup Type 1 DAP
9. omitted O 2014 Renesas Electronics Corporation All rights reserved Date September 17 2014 Correct Figure 15 96 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 0 CPU operation status Normal operation STOP mode Normal operation lt 12 gt SS01 lt 3 gt sTO1 lt 1 gt 10 gt A se __ i rr ISO EOC01 SSECO L Clock request signal MO internal signal MO Receive data 2 SDRO1 Receive data 1 RxDO pin o Receive data 1 X P sP ST Receive data 2 P SP Shift a E register 01 gt gt gt TP A A Shift operation A A flShiftoperationX oo NEEDS ERA wrsreo O ta ec O Data eco TSFO1 lt 2 gt lt 8 gt omitted RENESAS Page 11 of 17 RENESAS TECHNICAL UPDATE TN RL A033A E It is correction of CPU operation status Clock request signal internal signal INTSRO and TSF01 in this Figure Incorrect Figure 15 98 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 1 Normal operation CPU operation status Normal operation STOP mode SNOOZE mode STOP mode SNOOZE mode lt 4 gt SS01 lt 3 gt sTo1 lt 1 gt l a AAA EOCO1 intemal signal Receive data y 1 SDRO1 IAE RxDO pin Receivedatal Xp sp E Receive data 2 Shift a Sim operation Op A T INTSRO TSFO1 lt 2 gt lt 5 gt lt 6 gt lt T gt lt 5 gt lt 6 gt lt 7 gt lt 11 gt lt 8 gt omitted 2014 Renesas Electronics Corpora
10. Date Sep 17 2014 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product MPumcu Document TN RL A033A E Rev 1 00 Category No Correction for Incorrect Description Notice RL78 L1C Information Category Technical Notification Title Descriptions in the User s Manual Hardware Rev 2 00 RL78 L1C User s Manual Hardware Changed Reference Rev 2 00 All lots Pocument R01UH0O409EJ0200 Feb 2014 Applicable Product RL78 L1C Group This document describes misstatements found in the RL78 L1C User s Manual Hardware Rev 2 00 R0O1UHO409EJO0O200 Corrections age 3 3 4 Special function registers SFRs Table 3 8 SFR List Pages 82 Incorrect descriptions and 83 revised 6 3 3 Timer mode register mn TMRmn Figure 6 17 Format Page 248 Incorrect descriptions of Timer mode register mn TMRmn 4 4 g revised 5 3 9 High speed on chip oscillator trimming register Page 186 Incorrect descriptions HIOTRM g revised ne T E nenen Pages 663 Incorrect descriptions Timing Chart of SNOOZE Mode Operation Figure 14 74 g i p and 665 revised and Figure 14 76 15 6 3 SNOOZE mode function Incorrect descriptions Page 688 revised PS SNOOZE MOCE een Pages 690 Incorrect descriptions Timing Chart of SNOOZE Mode Operation Figure 15 95 691 and 693 revised Figure 15 96 and Figure 15 96 17 4 5 3 DTC Transfers DOFIFO and D1FIFO Ports
11. FF10H Serial data register 00 TXDO SDROO R W HT 0000H sos FFF11H FFF11H rer ES FFF12H Serial data register 01 sono e y 0000H FFF12H Serial data register 01 RXDO SDRO1 gen 0000H FFF13H FFF14H Serial data register 12 TXD3 SDR12 R W y y 0000H ris data register 12 ox oda y 0000H da a Haga FFF16H Serial data register 13 ES nn y e eee data register 13 SDR13 R W NI 0000H A PEA ee SS er omitted omitted 2014 Renesas Electronics Corporation All rights reserved RENESAS Page 3 of 17 RENESAS TECHNICAL UPDATE TN RL A033A E Date September 17 2014 Incorrect Correct Table 3 7 SFR List 2 4 Table 3 7 SFR List 2 4 Address Special Function Register SFR Name Symbol R W Manipulable Bit Range After Reset Address Special Function Register SFR Name Symbol R W Manipulable Bit Range After Reset 16 bit 16 bit omitted omitted risas po soja TT iris po sin TT Serial data register 02 Ea Serial data register 02 A S a FFFASH FFFASH FFFA7H FFFA7H aaa data register 10 aa y 0000H Serial data register 10 R W F y 0000H FFF49H T aH D fr TC omitted FEF4BH omitted O 2014 Renesas Electronics Corporation All rights reserved RENESAS Page 4 of 17 E RENESAS TECHNICAL UPDATE TN RL A033A E Date September 17 2014 2 6 3 3 Timer mode register mn TMRmn Figure 6 17 Format of Timer mode register mn TMRmn 4 4 p 248
12. Fmn FEFmn or OVFmn flag before setting the SWCO bit to 1 and read the value in bits 7 to 0 RxDq register of the SDRm1 register Cautions 5 The CPU shifts from the STOP mode to the SNOOZE mode on detecting the valid edge of the RxDq signal Note however that transfer through the UART channel may not start and the CPU may remain in the SNOOZE mode if an input pulse on the RxDq pin is too short to be detected as a start bit In such cases data may not be received correctly and this may lead to a framing error or parity error in the next UART transfer Page 9 of 17 RENESAS TECHNICAL UPDATE TN RL A033A E 6 15 6 3 SNOOZE mode function Timing Chart of SNOOZE Mode Operation Figure 15 95 Fiqure 15 96 and Figure 15 98 Pages 690 691 and 693 It is correction of CPU operation status Clock request signal internal signal INTSRO and TSF01 in this Figure Incorrect Figure 15 95 Timing Chart of SNOOZE Mode Operation EOCm1 0 SSECm 0 1 CPU operation status Normal operation STOP mode SNOOZE mode SS01 lt 3 gt ST01 lt 1 gt SE01 SWCO lt 11 gt EOC01 L Normal operation SSECO L Clock request signal IE o o internal signal SDRO Recewe daia i lo gt a Read RxDO pin Receive data 1 Xp a ST Receive data2 P sp Shift register 01 ae Shift operation i Shift operation X INTSRO INTSREO L ET __ TSFO1 lt 2 gt lt 5 gt lt 6 gt lt 8 gt omitted
13. NESAS Date September 17 2014 New 35 9 RAM Data Retention Characteristics Ta 40 to 105 C Data retention supply VODDR q 44Note 3 6 V voltage Note This depends on the POR detection voltage For a falling voltage data in RAM are retained until the voltage reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is generated STOP mode Eag Operation mode STOP instruction execution Standby release signal interrupt request 7 q A A Page 17 of 17
14. ation STOP ai ae mode STOP Ki SS00 lt 3 gt STOO lt 1 gt pH sso gt M i SWCO lt 10 gt a y Clock request signal SDROO pp Receive data _______ SNOOZE mode aig f neag T S100 pin Receive data 1 EN Receive data 2 Shift register 00 7 Reception amp shift operation Reception shift op ration INTCSIOO mM Data reception e reception TSFOO lt 2 gt lt 5 gt lt 6 gt lt 7 gt lt 5 gt lt 6 gt omitted 2014 Renesas Electronics Corporation All rights reserved ENESAS Date September 17 2014 Correct Figure 15 76 Timing Chart of SNOOZE Mode Operation continuous startup Type 1 DAPmn 0 CKPmn 0 CPU operation status Normal operation STOP mode Normal operation STOP mode lt 4 gt Ss00 lt 3 gt Clock request signal internal signal Receive data 2 Receivedatat SORDO EAN sala DS PULL S00 pin presos Fh ernest Shift register 00 See Ee ce INTCSIOO o TSFOO MN lt 2 gt lt 5 gt lt 6 gt lt 7 gt lt 2 gt lt 5 gt lt 6 gt PO Cs id ana E FER Data reception Data reception omitted Page 8 of 17 RENESAS TECHNICAL UPDATE TN RL A033A E 5 15 6 3 SNOOZE mode function Page 688 Incorrect 15 6 3 SNOOZE mode function The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode However using the SNOOZE mode enables the UART to pe
15. mn 0 CKPmn 0 CPU operation status Normal operation STOP mode SNOOZEmode mode SNOOZE mode Normal operation lt 4 gt SS00 lt 3 gt lt 11 gt STOO lt 1 gt _ SE00 E H m SWCO Zips SSECO L be ee Receive data 2 Fe Receive data 1 S100 pin 2 ee Receive data 1 Receive data 2 le re Sc Oh Reventon X shi opgan Y AA lt 2 gt lt 5 gt lt 6 gt lt gt Clock request signal internal signal SDROO SCKOO pin TSFOO omitted O 2014 Renesas Electronics Corporation All rights reserved Correct Date September 17 2014 Figure 15 74 Timing Chart of SNOOZE Mode Operation once startup Type 1 DAPmn 0 CKPmn 0 CPU operation status Clock request signal internal signal SDRDO SCKOO pin S00 pin Shift register 00 INTCSIOO TSFOO ENESAS Normal operation STOP mode Normal operation Receive data 2 HO TO ar Ss sana A O Receive data 1 Teton ey YX ee El A l y Data reception Receive data 2 Reception amp shift operation Data reception lt 2 gt lt 5 gt lt 6 gt lt gt omitted Page 7 of 17 RENESAS TECHNICAL UPDATE TN RL A033A E It is correction of CPU operation status Clock request signal internal signal and INTCSI00 in this Figure Incorrect Figure 15 76 Timing Chart of SNOOZE Mode Operation continuous startup Type 1 DAPmn 0 CKPmn 0 CPU operation status Normal oper
16. rform reception Normally the UART stops communication in the STOP mode operations without CPU operation omitted Cautions 1 The SNOOZE mode can only be used when the high speed on chip oscillator clock fin is selected for fcLk omitted Cautions 4 If a parity error framing error or overrun error occurs while the SSECm bit is set to 1 the PEFmn FEFmn or OVFmn flag is not set and an error interrupt INTSREq is not generated Therefore when the setting of SSECm 1 is made clear the PEFmn FEFmn or OVFmn flag before setting the SWCO bit to 1 and read the value in bits 7 to 0 RxDq register of the SDRm1 register 2014 Renesas Electronics Corporation All rights reserved ENESAS Date September 17 2014 Correct 15 6 3 SNOOZE mode function The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode However using the SNOOZE mode enables the UART to perform reception Normally the UART stops communication in the STOP mode operations without CPU operation omitted Cautions 1 The SNOOZE mode can only be used when the high speed on chip oscillator clock fin is selected for fcuk omitted Cautions 4 If a parity error framing error or overrun error occurs while the SSECm bit is set to 1 the PEFmn FEFmn or OVFmn flag is not set and an error interrupt INTSREq is not generated Therefore when the setting of SSECm 1 is made clear the PE
17. ting operation Start trigger is invalid during counting operation At that time interrupt is not generated At that time interrupt is not generated Other than above Setting prohibited Other than above Setting prohibited MD mn e Event counter mode Timer interrupt is not generated when counting is started e Event counter mode 0 1 1 timer output does not change either 0 1 1 Timer interrupt is not generated when counting is started e Capture amp one count mode Timer interrupt is not generated when counting is started 2014 Renesas Electronics Corporation All rights reserved RENESAS Page 5 of 17 a RENESAS TECHNICAL UPDATE TN RL A033A E 3 5 3 9 High speed on chi oscillator trimmin register HIOTRM Page 186 Incorrect 5 3 9 High speed on chip oscillator trimming register HIOTRM omitted Figure 5 14 Format of High Speed On Chip Oscillator Trimming Register HIOTRM Address FO0AOH After reset undefined R W Symbol HIOTRM rata HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRMO High speed on chip oscillator Minimum speed Minimum speed Note The value after reset is the value adjusted at shipment Remark ne HIOTRM register can be used to adjust the high speed on chip oscillata clock n r within ab 0 05 Remark2 For the usage example of the HIOTRM register see the application note for RL78 MCU series High speed On
18. tion All rights reserved ENESAS Date September 17 2014 Correct Figure 15 98 Timing Chart of SNOOZE Mode Operation EOCm1 1 SSECm 1 Normal operation CPU operation status Normal operation STOP mode STOP mode SS01 lt 3 gt sTo1 lt 1 gt CO SE01 Ooo SWCO SSECO Clock request signal internal signal SDRO1 SS Receive data 1 A i E RxDO pin Receive data 1 X P SP Shift register 01 INTSRO INTSREO L Data reception AR Data reception TSFO1 lt 2 gt lt 5 gt lt 7 gt lt 5 gt lt 7 gt lt 11 gt lt 8 gt omitted Page 12 of 17 RENESAS TECHNICAL UPDATE TN RL A033A E Date September 17 2014 7 17 4 5 3 DTC Transfers DOFIFO and D1FIFO Ports Table 17 22 DTC Settings p 895 Old New Table 17 22 DTC Settings Table 17 22 DTC Settings yc steatvansior Block ransier JT yet teat tanster electrones DTCCRj MODE 0 Use this setting in normal mode MODE 0 Use this setting in normal mode SAMOD FIFO read direction 0 FIFO write direction 1 SAMOD FIFO read direction 0 FIFO write direction 1 DAMOD FIFO read direction 1 FIFO write direction 0 DAMOD FIFO read direction 1 FIFO write direction 0 Fix the address of the FIFO side Fix the address of the FIFO side CHNE 0 Disable chain transfers CHNE 0 Disable chain transfers Specify the setting according to the setting of Sz MBW Specify the setting according to the setting of Sz
19. ty errores t 3 12 bit resolution 409 12 LB Notes 1 TYP Value is the average value at AVpp AVrerr 3 V and Ta 25 C MAX value is the average value 30 at normalized distribution 2 These values are the results of characteristic evaluation and are not checked for shipment 3 Excludes quantization error 1 2 LSB Cautions 1 Route the wiring so that noise will not be superimposed on each power line and ground line and insert a capacitor to suppress noise In addition separate the reference voltage line of AVrerr from the other power lines to keep it free from the influences of noise 2 During A D conversion keep a pulse such as a digital signal that abruptly changes its level from being input to or output from the pins adjacent to the converter pins and P20 to P27 and P150 to P154 O 2014 Renesas Electronics Corporation All rights reserved 2ENESAS E RENESAS TECHNICAL UPDATE TN RL A033A E 9 349 Data Memo STOP Mode Low Supply Voltage Data Retention Characteristics Page 1234 Old 4 9 Data Memor Characteristics Ta 40 to 85 C Vss 0 V Symbol TOP M Low ly Vol Data Retention Data retention supply VODDR 1 46 3 6 voltage Note The value depends on the POR de ion voltage When the voltage drop data is retained before a POR reset is effected but data no ined when a POR reset is effected 1 STOP mode lt Operation mode Data retention mode gt Vpop

Correction for Incorrect Description Notice RL78/L1C Descriptions in

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