User manual
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1. User clock programmable between 20MHz and 500MHz e Stable low jitter 200MHz clock for precision IO delays e User front panel adapter with up to 146 free IO signals e User rear panel PMC connector with 64 free IO signals e Programmable 2 5V or 3 3V I O on front and rear interfaces e Supports 3 3V PCI or PCI X at 64 bits ADM XRC 5LX User Manual Version 2 0 Page 1 ADM XRC 5LX User Manual 2 Hardware Installation This chapter explains how to install the ADM XRC 4 LX SX onto a PMC motherboard 2 1 Motherboard requirements The ADM XRC 5LX supports 3 3V only signalling on the PCI Bus It is not compatible with systems that use 5V signalling The ADM XRC 5T1 must be installed in a PMC motherboard that supplies 5 0V and 3 3V power to the PMC connectors Ensure that the motherboard satisfies this requirement before powering it up 12V and 12V may also be required for certain XRM modules 2 2 Handling instructions Observe SSD precautions when handling the cards to prevent damage to components by electrostatic discharge Avoid flexing the board 2 3 Installing the ADM XRC 5LX onto a PMC motherboard Note This operation should not be performed while the PMC motherboard is powered up The ADM XRC 4 LX SX must be secured to the PMC motherboard using M2 5 screws in the four holes provided The PMC bezel through which the I O connector protrudes should be flush with the front panel of the PMC motherboard 2 4 Installing the AD2. af Bridge Control as User FPGA Bus g ra i q FPGA Idreg_1 3 0 Virtex5 Virtex4 LX25 idack I 3 0 LX55 80 110 l fhold fholda j Ireset E Iclk ali Figure 2 Local Bus Interface Signal Type Purpose Table 1 Local Bus Interface Signal List ADM XRC 5LX User Manual Version 2 0 Page 4 ADM XRC 5LX User Manual 4 2 Flash Memory The ADM XRC 5LX is fitted with two separate Flash memories one connected to the Bridge Control FPGA and the other to the User FPGA 4 2 1 Board Control Flash An Intel PC28F256P30 flash memory is used for storing a configuration bitstream for the User FPGA Once the Bridge Control FPGA is configured it checks for a valid bitstream in flash and if present automatically loads it into the User FPGA This process can be inhibited by setting a jumper on the JTAG connector See the description of the FBS signal in Section 4 4 for further information Access to this flash device is only possible through control logic registers The flash is not directly mapped onto the local bus Programming erasing and verification of the flash are supported by the ADM XRC SDK and driver Utilities are provided to load bitstreams into the flash These also verify the bitstream is compatible with the target FPGA 4 2 2 User FPGA Flash An ST M25P32 flash memory with SPI interface is connected to the User FPGA for the storage of application specific information Note Thi
3. delay clock buffer is used to route the PCI clock to the two different clock inputs The clock buffer has a PLL with a minimum input frequency of 24MHz potentially causing problems in applications that use the PCI 33MHz mode with a slow clock In this case the buffer can be removed to provide full PCI 33MHz compatibility 4 6 User FPGA 4 6 1 Configuration The ADM XRC 5LX performs configuration from the host at high speed using SelectMAP The FPGA may also be configured from flash or by JTAG via header J5 Download from the host is the fastest way to configure the User FPGA with 8 bit SelectMAP mode enabled This permits a configuration speed of up to 40MB s The ADM XRC 5LX can be configured to boot the User FPGA from flash on power up if a valid bit stream is detected in the flash Booting from flash will also configure the clocks and I O voltages as appropriate 4 6 2 I O Bank Voltages Bank X Voltage Lera aeaeo Configuration I F 5 12 15 16 19 20 23 24 DDRII DRAM I O pri Table 5 User FPGA I O Bank Voltages ADM XRC 5LX User Manual Version 2 0 Page 9 ADM XRC 5LX User Manual 4 6 3 Memory Interfaces The ADM XRC 5LX has 4 independent banks of DDRII SDRAM Each bank consists of two memory devices in parallel to provide a 32 bit datapath 1Gb Micron MT47H64M16 devices are fitted as standard to provide 256MB per bank The board will support higher capacity devices when they become available Details of t
4. including the configuration of the target FPGA programmable clock setup and the monitoring of on board voltage and temperature DDR2 SDRAM and serial flash memory connect to the target FPGA and are supported by Xilinx or third party IP IO functionality is provided using XRM modules connecting to a 180 pin SAMTEC QSH connector Bridge aso Programmable Config emon Clocks 16MB PCI X XRM pn1 PCI64 66 u BILE an E Bridge Control FPGA Local Bus 64 bit Virtex5 i ma t gt Virtex4 LX25 LX50 80 110 I O Pn3 XRM Serial Flash 4MB Pn4 Rear I O 64 bit System ET DDR2 DDR2 DDR2 DDR2 JTAG Monitor ME AER SDRAM SDRAM SDRAM SDRAM LM87 256MB 256MB 256MB 256MB Figure 1 ADM XRC 5LX Block Diagram ADM XRC 5LX User Manual Version 2 0 Page 3 ADM XRC 5LX User Manual 4 1 Local Bus The ADM XRC 5LX implements a multi master local bus between the bridge and the target FPGA using a 32 or 64 bit multiplexed address and data path The bridge design is asynchronous and allows the local bus to be run faster or slower than the PCI bus clock to suit the requirements of the user design lad_1 63 0 Ibe I 7 0 La lads La Iblast I Ibterm I ra p lready_ PCI ae
5. 1 pins marked CC are clock capable and may be used to access the regional clocking resources in the FPGA Banks 11 amp 13 are fitted with resistors to allow DCI terminations on Pn4 signals ADM XRC 5LX User Manual Version 2 0 Page 15 ADM XRC 5LX User Manual 4 8 1 Pn4 Signalling Voltage User FPGA Banks 11 amp 13 and Pn4 can use 3 3V or 2 5V signalling standards selectable by switch SW2B SW2B Pn4 voltage Table 12 Pn4 Voltage Selection It should be noted that the switch does not directly route power to Banks 11 amp 13 The link position is monitored by the board control logic which in turn sets a power multiplexer to be either 2 5V or 3 3V ADM XRC 5LX User Manual Version 2 0 Page 16 ADM XRC 5LX User Manual 5 XRM 10146 Interface The following tables provide the user with information on the pin out of the XRM IO146 when fitted to an ADM XRC 5LX card The signal names P_1 N_1 etc are internal to the ADM XRC 5LX The important mapping is between the Mictor pin and the FPGA pin Table 14 10146 Mictor Connector Pins 39 76 ADM XRC 5LX User Manual Version 2 0 Page 17 ADM XRC 5LX User Manual Samtec FPGA Pin Signal 100 re A io XL E A Vee D MEME TS IE RC NIA NL NENNEN SE ARRE ccc SUPE 128 MB NSB 190 AA6 v P40 n ME B NNNM ME 136 ABD sp Ae 434 ACS N42 LLL A A crea te LS A A l A a BE JAMIE KL NN AF6 S AO oe 142 LAGO LN 46 152 AUS LL EA eii n 1500 AHS o NA
6. 48 i Su o us AAA 1 CLK4 lt EM T QM i GURS l 45V a G G TERE RR E RC TRE LE a a ms NL RR RR RARE Samtec FPGA Pin Signal 146 alal ai 2 AA 148 Va N 590 ______ll 186 B MENT l SE 494 cuc cecs S e 160 AB8 P 54 s 198 0 AAS N54 VOD NAE BC NEN IL RENE 102 2 CAD o os 168 AFS J 41BR 58 i 166 AES J M N58 i A72 OO AGS 2 P 60 v BA ns AHS NO NIG a NO rl P G2 cod 1 4 1AP2___ 2 0 N62 1 180 OA li 1 8 LANS NGA 102 LAGI CERE 104 2 AG2 CLK7 Ll 5V Table 16 10146 Mictor Connector Pins 115 152 ADM XRC 5LX User Manual Version 2 0 Page 18 ADM XRC 5LX User Manual 6 Revision History 22 08 2006 First Release 17 12 2007 Revised wording of motherboard power requirements 16 01 2008 2 0 Updated to reflect changes to Iclk and Front IO voltage selection on Rev2 PCBs ADM XRC 5LX User Manual Version 2 0 Page 19
7. 5LX55 80 110 A Connector CLK1 N A Samtec CLK2 P CLK3 N LK4 P IST a KEY CLK6 P A x Global Clock Inputs CLK7 N A Clock Capable I O Figure 4 Clock Structure 4 5 1 LCLK The Local Bus can be used at up to 80 MHz and all timing is synchronised to LCLK between the Bridge and User FPGAs LCLK is generated from a 200MHz reference by a DCM within the bridge FPGA The minimum LCLK frequency determined by the DCM specification is 32MHz The LCLK frequency is set by writing to the board control logic See SDK for details and example application Note If the user FPGA application includes a DCM driven by LCLK or one of the other programmable clocks the clock frequency should be set prior to FPGA configuration ADM XRC 5LX User Manual Version 2 0 Page 7 ADM XRC 5LX User Manual 4 5 2 MCLK MCLK is an LVPECL clock generated by an IC S8430 61 synthesiser with a base 25MHz crystal The svnthesiser has two outputs of the same clock one of which is routed to the User FPGA whilst the other is routed to the XRM connector Both are terminated using LVPECL terminations MCLK can be programmed to between 20MHz and 500MHz 4 5 3 REFCLK In order to make use of the IODELAY features of Virtex M 5 a stable low jitter clock source is required to provide the base timing for tap delay lines in each IOB in the User FPGA The ADM XRC 5LX is fitted with a 200MHz LVPECL LVDS optional oscillator connected to global clock resource p
8. ADM XRC 5LX PCI Mezzanine Card User Guide Version 2 0 ADM XRC 5LX User Manual Copyright O 2006 2007 2008 Alpha Data Parallel Systems Ltd All rights reserved This publication is protected by Copyright Law with all rights reserved No part of this publication may be reproduced in any shape or form without prior written consent from Alpha Data Parallel Systems Limited Alpha Data Alpha Data 4 West Silvermills Lane 2570 North First Street Suite 440 Edinburgh EH3 5BD San Jose CA 95131 UK USA Phone 44 0 131 558 2600 Phone 408 467 5076 Fax 44 0 131 558 2700 Fax 866 820 9956 Email support alphadata co uk Email support alpha data com ADM XRC 5LX User Manual Version 2 1 ADM XRC 5LX User Manual Table of Contents lk o aa 1 1 1 SDOCINIC ON i TO A 1 2 Hardware Instala Nassau ated nieve nak teh added 2 2 1 Motherboard requirements siii lic 2 2 2 wi inre p e NSIUGCIOIS sbranato 2 2 3 Installing the ADM XRC 5LX onto a PMC motherboard 2 2 4 Installing the ADM XRC 5LX if fitted to an ADC PMC i 2 Be sollwareInsitallalio NOTET ariano 2 A Board Desci plonikes ET mom mE 3 4 1 HV CI A 4 4 2 Fa Ie IO V islandesi 5 4 2 1 Board Gontrol Fasa 5 4 2 2 US CREC CEIC enact let roto b ect ior enatis ae Ga Se ll crate s aa a net it 5 4 3 ECO IO RO OE Eom 5 4 4 UR RE HM 6 4 5 Sh fole l A OE meme 7 4 5 1 FOEK T nal h
9. M XRC 5LX if fitted to an ADC PMC The ADM XRC 4 LX SX can be supplied for use in standard PC systems fitted to an ADC PMC carrier board The ADC PMC can support up to two PMC cards whilst maintaining host PC PCI compatibility If you are using a ADC PMC refer to the supplied documentation for information on jumper settings All that is required for installation is a PCI slot that has enough space to accommodate the full length card The ADC PMC is compatible with 5V and 3V PCI 32 and 64 bit and PCI X slots It should be noted that the ADC PMC uses a standard bridge to provide a secondary PCI bus for the ADM XRC 4 LX SX and that some older BIOS code does not set up these devices correctly Please ensure you have the latest version of BIOS appropriate for your machine 3 Software Installation Please refer to the SDK installation CD The SDK contains drivers examples for host control and FPGA design and comprehensive help on application interfacing ADM XRC 5LX User Manual Version 2 0 Page 2 ADM XRC 5LX User Manual 4 Board Description The ADM XRC 5LX follows the architecture of the ADM XRC series and decouples the target FPGA from the PCI interface allowing user applications to be designed with minimum effort and without the complexity of PCI design A separate Bridge Control FPGA interfaces to the PCI bus and provides a simpler Local Bus interface to the target FPGA It also performs all of the board control functions
10. Z U U Z UIZ NiN NINININ N NEN Ou on I N ADM XRC 5LX User Manual Version 2 0 Page 13 ADM XRC 5LX User Manual de Elm Col col co o co 1 O1 C1 N C N O lt NI U Q 00 de ie 3 iS LS Ala alo l2 218 Appl O O N lt lt lt gt N Wwd K x A on lE ES ei ei or on ES sms MI oo Ojaol BlBloja Ro R5 69 co U U Ol U al Z SLi KOL U Z al U Z al pa SLE KON Z 101 COICO NI XI OU Ol OC w DI ZI U DJO ZI U oo no O C2 Table 10 XRM Interface part 3 ADM XRC 5LX User Manual Version 2 0 Page 14 ADM XRC 5LX User Manual 4 8 Pn4 I O Up to 32 pairs of differential or 64 single ended signals are available on Pn4 and are sourced from Banks 11 8 13 of the User FPGA AII of the signal traces are routed as 100 Ohm differential pairs and each pair is matched in length The worst case difference in trace length between any two pairs is 10mm PN4 N4 PN4 P6 PN4 N6 PN4 P8 PN4 N8 PN4 P10 PN4 N10 PN4 P12 PN4 N12 PN4 N14 PN4 P16 PN4 N16 PN4 P17 PN4 P18 PN4 N17 PN4 N18 PN4 P19 PN4 P20 PN4 N19 PN4 N20 PN4 P21 PN4 P22 PN4 N21 PN4 N22 PN4 P23 L34 CC PN4 P24 PN4 N23 K34 CC PN4 N24 PN4 P25 J32 CC PN4 P26 U Z U PN4 N25 H33 CC PN4 N26 PN4 P27 E32 53 54 F33 4 P28 PN4 N27 PN4 N28 PN4 P29 PN4 P30 PN4 N29 PN4 N30 PN4 P31 PN4 P32 PN4 N31 PN4 N32 Table 11 Pn4 to FPGA Assignments In Table 1
11. ded in the main from three banks of the User FPGA Banks 9 11 and 13 These banks share a common VCCO that can be 2 5V or 3 3V powered selectable under user control al IMEI VCCI 8 8 AM10 memo Pao AP7__ 17 ANT N9 AP6 fia CAM 33V APIO ei BY ooo 4 a XRMESERID BY a _ a RESERVED AY JAS a po XRPMVREF 5V 48 XBMVCCO LVBAT ooo 9 ps XRMVCCO AV 81 82 XRPMvCCO AR BA 2V y PRESENCE L J 55 5e6 EXAMI XRM_TCK J 87 588 XRMIRST O XRM_TMS 59 60 XRPMIDO O Table 8 XRM Interface part 1 ADM XRC 5LX User Manual Version 2 0 Page 12 ADM XRC 5LX User Manual Signal 7 FPGAPin____ Samtec Pin Samtec Pin_ FPGAPin_____ Signal Nao AS SADT ND R21 AY 6e AEP N23 jaa 6 ro JACO N24 N27 para va j80 AO pas X N31 JAH v 8 Jee O JAEN Na Clik _____ E8 89 90 X AH WIRESA O WIRES 3S ACe 95 v X ACGS v RES CLKA AM far j98 ww N34 CLK5 AB5 99 OO X W9 OPA S PRESERVED 109 110 AH 9 XRBMCLKNP amp PRESERVED J AFI O xRMSDA O XRM PECLN J 113 urta Ara XRMSCL O XRM_PECLP 1105 j1t RESERVED PRESERVED J 1t 1i8 RESERVED RESERVED tt9 120 RESERVED Table 9 XRM Interface part 2 Z I
12. e 7 4 5 2 MEL c X ti lan 8 4 5 3 NERO quem 8 4 5 4 AnMGbcSa lella 8 4 5 5 eal RIA CIOC RS T a a E coa ala a 8 4 5 6 PA eii Unt coatulon Scene Gel cosi cetilemant gats i 9 4 6 ESSI DO Ata eiie cachatescet ctu tenuia test oca frames ef idea 9 4 6 1 COMMOUFATION A MP 9 4 6 2 O Bank VOltag8S oui idas ln 9 4 6 3 Memory IMC Te RETO m nat cit 10 4 7 ARM BUS and Front Panella ni serna 11 4 7 1 XRM Si nallina V Ola dE escisiones 11 4 7 2 XRM Interface Connector PiNOUt ii 12 4 8 aane 15 4 8 1 FAL SIG ALlMMO VONIG E ee A a ia Ba tl 16 Ds IBMJOTAO Inter Tae Ocio netta sil B a aa aa 17 bi REVISION FIS LOL V sea ask he ita ra eb tame data ia e sta ati ama ii na ci oar Llame idea ba 19 ADM XRC 5LX User Manual Version 2 1 ADM XRC 5LX User Manual Table of Tables Table dl Local Bus Interface Signal Stata hana eod mee n dan hi eode 4 Table 2 Voltage and Temperature MONItOrs 6 Table 3 ARM Bus Regional OIOGKS utet dicas eaae Seas etc sae 8 Table 4 Rear Pn4 Regional CloCKSa itn eor clio ra cota tie 8 Table 5 User FPGA TO Bank Vola GES scusate oco dida 9 Table 6 DDR Memory Bank Configuration ii 10 Table ARNO Voltage oe eclesial 11 Tables RMintertace pan llas coto nilo coda ica 12 able 9 XEM interface span 2 us cat
13. enae latu Scam con a a dan ctas 13 Fable 10 XRM menace Panta tesina a tacita 14 Mable T1 PA IO FEGAASSIINMEN S erat hr a aa mit cod a lk 15 Table 12 PHA Voltage Selecionar disi n cine madii idas 16 Table 13 10146 Mictor Connector PINS 1 BB saint ie neci aes a pe s FE cc la ea a e E ca 17 Table 14 10146 Mictor Connector Pins 39 76 cccccsssececcscssseteccsenseeecesasseeeccseasseesesseases 17 Table 15 10146 Mictor Connector Pins 77 114 iii 18 Table 16 10146 Mictor Connector Pins 115 152 ii 18 Table of Figures Figure 1 ADM XRC 5LX Block Diagram e ii 3 Foue 2 local BUS Mtera ceuta o 4 Figures ITA o it 6 A S 7 ADM XRC 5LX User Manual Version 2 1 ADM XRC 5LX User Manual 1 Introduction The ADM XRC 5LX is a high performance PCI Mezzanine Card PMC designed for supporting development of applications using the Virtex 5LX series of FPGAs from Xilinx The card uses an FPGA PCI bridge developed by Alpha Data supporting PCI X and PCI A high speed multiplexed address data bus connects the bridge to the target user FPGA 1 1 Specifications The ADM XRC 5LX supports high performance PCI X PCI operation without the need to integrate proprietary cores into the user FPGA e Physically conformant to IEEE P1386 2001 Common Mezzanine Card standard e High performance PCI and DMA controllers e Local bus speeds of up to 80 MHz e Four banks of 64Mx32 DDRII SDRAM 1GB total e
14. he signalling standards bank numbers etc are given in the tables below I O Standard DDRI ad 15 0 Output SSTL18 I DDRI ba 2 0 DDRI rasn DDRI casn DDHR1 wen DDRI csn DDRI cke DDR1 odt DDHR1 ckO Output DIFF SSTL18 II DDR1 cknO DDR1 dq 15 0 SSTL18 Il DDR1 dm 1 0 SSTL18 I DDR1 dgsn 1 0 DDR1 ckn1 DDR1 dgsn 3 2 DDR read en out Output DDRI read en in Input I Table 6 DDR Memory Bank Configuration ADM XRC 5LX User Manual Version 2 0 Page 10 ADM XRC 5LX User Manual 4 7 XRM Bus and Front Panel I O A major benefit of the ADM XRC series of boards that use the XRM Bus interface is the versatility of I O options that result The ADM XRC 5LX maintains this interface and thus compatibility with a wide range of l O modules to suit many diverse needs The XRM interface uses the 180 pin Samtec QSH series connector CN1 4 7 1 XRM Signalling Voltage The signalling voltage on the XRM connector and User FPGA Banks 14 18 22 amp 26 is selectable by jumper J6 XRM I O voltage Link p1 amp p2 Link p3 amp p4 Link p5 amp p4 Table 7 XRM I O Voltage Selection ADM XRC 5LX User Manual Version 2 0 Page 11 ADM XRC 5LX User Manual 4 7 2 XRM Interface Connector Pinout The XRM interface is implemented on CN1 a 180 pin Samtec connector type QSH with the pin out as detailed in tables Table 8 to Table 10 In turn the signals that connect to CN1 are provi
15. ins This reference clock can also be used for application logic if required 4 5 4 XRM Clocks Global Clock Input The XRM interface provides a differential input to the User FPGA global clocking resources The default on board terminations are suitable for an LVPECL clock Hegional Clocks The XRM interface provides 8 clock lines that can be either be used single ended or as 4 LVDS differential pairs These clocks are routed to Clock Capable I O on the User FPGA providing access to its regional clock capabilities Each clock pair is in a different clock region alongside 16 pairs of XRM bus signals as shown in Table 3 below XRM Clocks FPGA Bank XRM bus pairs 0 amp 1 Pair 0 2 amp 3 Pair 1 17 32 4 amp 5 Pair 2 33 48 6 amp 7 Pair 3 49 64 Table 3 XRM Bus Regional Clocks 4 5 5 Rear Pn4 Clocks There are no dedicated clock lines between the Pn4 connector and the user FPGA However the following signal pairs are routed to clock capable I O on the User FPGA providing access to its regional clock capabilities FPGA Bank Pn4 bus pairs 22 23 24 amp 25 6 7 8 amp 9 Table 4 Rear Pn4 Regional Clocks ADM XRC 5LX User Manual Version 2 0 Page 8 ADM XRC 5LX User Manual 4 5 6 PCI Clocks The PCI Interface within the bridge FPGA requires a regional clock input for 66MHz PCI operation or a global clock input for PCI X To comply with the single load requirement in the PCI specification a zero
16. ng the Xilinx tools and serial download cables This also allows the use of ChipScope PRO ILA to debug an FPGA design It should be noted that four devices will be detected when the SCAN chain is initialised lt X moe cep cep Q w ayu y 2895 0000000 Figure 3 JTAG Header The VCC supply provided on J5 to the JTAG cable is 2 5V and is protected by a poly fuse with a rating of 350mA FBS The FBS signal is an input to the control logic and provides control of the cold boot process By default with no link fitted the control logic will load a bitstream from flash into the FPGA if one is present Shorting FBS to the adjacent GND pin will disable this process and can be used to recover situations where rogue bitstreams have been stored in flash ADM XRC 5LX User Manual Version 2 0 Page 6 ADM XRC 5LX User Manual 4 5 Clocks The ADM XRC 5LX is provided with numerous clock sources as shown in Figure 4 below PCI PCI Bus RefClk PCI X CLK Zero delay Buffer Bridge Cfg Ctl Ca Aa PCI PLL Bridge FPGA CLK V4LX25 ds MHz po REFCLK 200M qm SC Z Ctl e So LCLK Local Bus 25 0 MH 1 0 MHZ XTAL ICS8430 x5 A MCLK MCLK A O q A XRM CLKIN A Pn4 Connector O ok UserFPGA A V
17. s device is not connected to the SPI configuration pins on the User FPGA and cannot be used for configuration 4 3 Health Monitoring The ADM XRC 5LX has the ability to monitor temperature and voltage of key parts of the PMC to maintain a check on the operation of the board The monitoring is implemented by a National Semiconductor LM87 and is supported by the board control logic connected using IFC The Control Logic scans the LM87 when instructed by host software and stores all current voltage and temperature measurements in a blockram This allows the values to be read without the need to communicate directly with the monitor The following supplies and temperatures as shown in Table 2 are monitored ADM XRC 5LX User Manual Version 2 0 Page 5 ADM XRC 5LX User Manual Monitor Purpose User FPGA Core Supply Bridge FPGA Core Supply 1 8V Memories User FPGA Memory I O Local Bus I O Config CPLD Core Suppl Source voltage for Front Rear I O Board Input Supply PCI VIO Monitors the PCI signalling supply VIO XRM VCCI Either 2 5V or 3 3V Front Panel I O Voltage O User FPGA die temperature LM87 on die temperature for board ambient Table 2 Voltage and Temperature Monitors An application is provided in the SDK that permits the reading of the health monitor The typical output of the monitor is shown below provided by the SV SMON program 4 4 JTAG A JTAG header is provided to allow download of the FPGA usi
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