Home

8-bit Microprocessor Synthesizable Verilog HDL Model User Manual

1. register LSB 0 1 2 3 4 5 6 7 9 A B D E F MSB 0 ADD IY BC 1 ADD 2 LD LD INC ADD LD DEC mn Y Y IY 3 INC DEC LD ADD IY d IY d n IX SP 4 LD LD B IY d C IY d 5 LD LD D IY d E IY d 6 LD LD H IY d L IY d 7 LD LD LD LD LD LD LD LD IY d B IY d C IY d E IY d H IY d L IY d A A IY d 8 ADD ADC A IY d A IY d 9 SUB SBC IY d A IY d A AND XOR IY d IY d B OR CP IY d IY d esc D E POP EX PUSH JP SP IY LD Systemyde International Corporation Y180 02 96 Rev 1 0 Page 14 3 4 5 CB Code Page This table shows the code page for instructions whose first byte is CBh The instructions on this code page are the majority of the shift rotate and bit manipulation instructions LSB 1 2 3 4 5 6 7 8 9 A B D E F MSB 0 RLC RLC RLC RLC RLC RLC RLC RRC RRC RRC RRC RRC RRC B C D E H L HL A B C D E H L HL A 1 RL RL RL RL RL RL RL RL RR RR RR RR AR RR RR RR B D E H L HL A B C D E H L HL A 2 SLA SLA SLA SLA SLA SLA SLA SLA SRA SRA SRA SRA SRA SRA SRA SRA B C D E H
2. Instruction if1 dly if2 of1 of2 if3 iop sif1 sdly sif2 rd1 rd2 siop wr1 wr2 fiop LD A BC PC BC LDA DE DE LDA mn PC PC PC mn LD AJ PC PC LD A R PC PC LD dd mn PC PC PC PC mn mn LD dd mn PC PC PC LD HL mn PC PC PC mn mn LD IA PC PC LD IX mn PC PC PC PC mn mn LD IX mn PC PC PC PC LD IY mn PC PC PC PC mn mn LD IY mn PC PC PC PC LD PC HL LD r IX d PC PC PC xx IX d LD r IY d PC PC PC x IY d LD R A PC PC LD r n PC PC LD PC LD SP HL PC xx LD SP IX PG PG xx LD SP IY PC PC xx LDD PC PC HL DE LDDR PG PC HL DE xx LDI PC PC HL DE LDIR PC PC HL DE xx MLT w PC PC xx NEG PG PG NOP PG OR HL PC HL OR 1 4 PC PC PC xx IX d OR IY d PC PC PC xx IY d ORn PC PC ORr PC xx OTDM PG PG xx HL 0C xx OTDMR PG PG xx HL xx 0C xx OTDR PG PG HL BC xx OTIM PG PG xx HL 0C xx OTIMR PG PG xx HL xx 0C xx OTIR PG PG HL BC xx OUT C r PC PC xx BC OUT n A PC PC xx An OUTO n r PC PC PC xx On OUTD PC PC HL BC OUTI PC PC HL BC POP IX PC PC SP SP 1 POP IY PC PC SP SP 1 POP zz PC SP SP 1 PUSH IX PC PC xx SP 1 SP 2 PUSH IY PC PC xx SP 1 SP 2 PUSH zz PG xx SP 1 SP 2 Systemyde International Corporation Y180 02 96 Rev 1 0 Page 26
3. Instruction if1 dly if2 of1 of2 if3 iop sif1 sdly sif2 rd1 rd2 siop wr1 wr2 fiop DEC IX PC PC xx DEC IY PC PC xx DEC r PG xx DEC ss PC xx DI PG DJNZ j PC xx PG xx El PG EX SP HL PG SP SP 1 x 5 1 SP EX SP IX PC PC SP SP 1 x 5 1 SP EX SP IY PC PC SP SP 1 x 5 1 SP EX AF AF PC xx EX DE HL PC EXX PG HALT PC IM 0 PG PG IM 1 PC PC IM2 PC PC IN A n PC PC An IN r C PC PC BC INO r n PC PC PC On INC HL PC HL xx HL INC IX d PC PC PG xx IX d xx IX d INC IY d PC PC PC xx IY d xx IY d INC IX PC PC xx INC IY PC PC xx INC r PC xx INC ss PC xx IND PC PC BC HL INDR PC PC BC HL xx INI PG PG BC HL INIR PC PC BC HL xx JP HL PC JP IX PG PG JP IY PC PC JP f mn PC PC PC JP mn PC PC PC JR cc jj PC PC LD BC A BC LD DE A PC x DE LD HL n PC PC HL LD HL r PC x HL LD IX d n PC PC PC PC IX d LD IX d r PC PC PC xx IX d LD IY d n PC PC PC PC IY d LD IY d r PC PC PC xx 0 LD mn LD mn HL PC PC PC xx mn mn 1 LD IX PC PC PC PC xx mn mn 1 LD mn IY PC PC PC PC xx mn mn 1 LD mn ss PC PC PC PC xx mn mn 1 Systemyde International Corporation Y180 02 96 Rev 1 0 Page 25
4. Instruction if1 dly if2 of1 of2 if3 iop sif1 sdly sif2 rd1 rd2 siop wr1 wr2 fiop RES b HL PC PC HL xx HL RES b IX d PC PC PC PC IX d xx IX d RES b IY d PC PC PC PC IY d xx IY d RES b r PC PC xx RET PC SP SP RET f PC xx SP SP xx RETI PC PC xx PC xx PC SP SP RETN PC PC SP SP RL HL PC PC HL xx HL RL IX d PG PC PC PC IX d xx IX d RL IY d PC PC PC PC IY d xx IY d RLr PC PC xx RLA PG RLC HL PC PC HL x HL PC PC PC PC IX d xx IX d IY d PC PC PC PC IY d xx IY d RLCr PC PC xx RLCA PC RLD PC PC HL xx HL RR HL PC PC HL x HL RR IX d PC PC PC PC IX d xx IX d RR IY d PC PC PC PC IY d xx IY d RRr PC PC xx RRA PC RRC HL PC PC HL xx HL RRC IX d PC PC PC PC IX d xx IX d RRC IY d PC PC PC PC IY d xx IY d RRCr PC PC xx RRCA PC RRD PC PC HL xx HL RST v PC xx SP 1 SP 2 SBC IX d PC PG PC xx HL SBC IY d PG PC PC xx IX d SBC A HL PC IY d SBC PC PC SBCA r PG xx SBC HL ss PC PC xx SCF PC SET b HL PC PC HL xx HL SET b IX d PC PC PC PC IX d xx IX d SET b IY d PC PC PC PC IY d xx IY d SET b r PC PC xx SLA HL PC PC HL xx HL SLA IX d PC PC PC PC IX d xx IX d SLA IY d PC PC PC PC IY d xx IY d SLAr PC PC xx SLP PC PC xx SRA HL PC PC HL xx HL SRA IX d PC PC PC PC IX d xx IX d SRA IY d PC PC PC PC IY d xx IY d SRAr PC PC xx
5. Systemyde International Corporation Y180 02 96 Rev 1 0 Page 27 Instruction if1 dly if2 of1 of2 if3 iop sif1 sdly sif2 rd1 rd2 siop wr1 wr2 fiop SRL HL PC PC HL xx HL SRL IX d PG PC PC PC IX d xx IX d SRL IY d PC PC PC PC IY d xx IY d SRLr PC PC xx SUB HL PC HL SUB IX d PC PC PG xx IX d SUB IY d PC PC PC xx IY d SUBn PC PC SUBr PC x TST HL PC PC xx HL TSTn PC PC PC TSTr PC PC xx TSTIOn PC PC PC 0C XOR HL PC HL XOR IX d PC PC PC xx IX d XOR IY d PC PC PC xx IY d XORn PC PC xx ZIACK0 ZIACK1 SP 1 SP 2 ZIACK2 VT VT 1 xx SP 1 SP2 ZNMIACK xx SP 1 SP 2 ZTRAP2 xx SP 1 SP 2 ZTRAP3 xx SP 1 SP 2 Systemyde International Corporation Y180 02 96 Rev 1 0 Page 28 3 5 4 Next Machine State The execution table below shows the sequence of machine cycles for each instruction or exception condition All instructions start with the IF1 instruction fetch 1 state while exception conditions start with some kind of interrupt acknowledge state or the instruction fetch where the illegal opcode was fetched which are not shown in the table In each column is listed the next machine cycle for each instruction or exception The word done in a column means that the corresponding machine cycle is the last one for that particular instruction or exception con
6. Instruction Opcode Opcode Opcode Opcode Addr Mach Clock cycles PIN Operation byte 1 byte 2 byte 3 byte 4 Mode State DEC IX 11011101 00101011 reg 3 7 8 3 1 IX IX 1 DEC IY 11111101 00101011 reg 3 7 8 3 1 IY IY 1 DECr 00 r 101 reg 2 4 3 1 Vid rer 1 DEC ss 00ss1011 reg 2 4 8 1 ss ss 1 DI 11110011 none 1 3 ce a IEF1 0 IEF2 0 DJNZe 00010000 e 2 relative pp b 545 B 1 if BI 0 PC e EI 11111011 none 1 3 ZEE IEF1 21 IEF2 1 SP HL 11100011 implied 6 16 3 3 3 1 3 3 s H lt gt SP 1 L lt gt SP EX SP IX 11011101 11100011 implied 7 19 3 3 3 3 1 3 3 IXH lt gt SP 1 IXL lt gt SP SP IY 11111101 11100011 implied 7 19 3 3 3 3 1 3 3 zu IYH lt gt SP 1 IYL lt gt SP EX AF AF 00001000 implied 2 4 3 1 AF lt gt AF EX DE HL 11101011 implied 1 3 ss DE lt gt HL EXX 11011001 implied 1 3 lt gt lt gt DES HL lt gt HL HALT 01110110 none 1 3 CPU halted IM 0 11101101 01000110 none 2 6 3 3 1 Interrupt mode 0 IM 1 11101101 01010110 none 2 6 3 3 Interrupt mode 1 IM2 11101101 01011110 none 2 6 3 3 Interrupt mode 2 IN A n 11011011 n direct 3 9 3 3 3 muss A An IN r C 11101101 01 r 000 indirect 3 9 3 3 3 INO r n 11101101 00 r 000 4 12 3 3 3 3 0 r n INC HL 00110100 regind 4 10 3 3 1 3 vio HL
7. B 1 C 1 OTIR 11101101 10110011 implied if B 0 repeat HL HL HL 1 B 1 OUT C r 11101101 01 r 001 indirect 4 10 3 3 1 3 1 1 1 1 OUT 11010011 n direct 4 10 3 3 1 3 1 1 OUTO n r 11101101 00 r 001 n direct 5 13 3 3 3 1 3 efor inher Systemyde International Corporation Y180 02 96 Rev 1 0 Page 21 Instruction Opcode Opcode Opcode Opcode Addr Mach Clock cycles H P N Operation byte 1 byte 2 byte 3 byte 4 Mode State OUTD 11101101 10101011 implied 4 12 3 3 3 3 sz ale BC HL HL HL 1 B B 1 OUTI 11101101 10100011 implied 4 12 3 3 3 3 HL HL HL 1 B 1 POP IX 11011101 11100001 reg 4 12 3 3 3 3 1 1 IXL SP IXH SP 1 SP SP 2 POP IY 11111101 11100001 reg 4 12 3 3 3 3 Up em IYL SP SP 1 SP SP 2 POP zz 11zz0001 reg 3 9 3 3 3 1 1 221 5 221 5 1 5 5 2 PUSH IX 11011101 11100101 reg 5 14 3 3 2 3 3 SP 1 IXH SP 2 IXL SP 5 2 PUSHIY 11111101 11100101 reg 5 14 3 3 2 3 3 1 1 SP 1 SP 2 IYL SP SP 2 PUSHzz 11220101 reg 4 11 3 2 3 3 epe SP 1 zzh SP 2 zzl SP SP 2 RESb HL 1100
8. HL 1 INC IX d 11011101 00110100 d index 7 18 3 3 3 2 3 1 3 IX d IX d 1 INC IY d 11111101 00110100 d index y 18 3 3 3 2 3 1 3 I d IY d 1 11011101 00100011 3 7 3 3 1 ers IX 2 IX 1 INC IY 11111101 00100011 reg 3 7 3 3 1 As IY21Y 1 INC r 00 r 100 reg 2 4 3 1 V 0 r r 1 INC ss 00ss0011 reg 2 4 3 1 3708 ss ss 1 IND 11101101 10101010 implied 4 12 3 3 3 3 e HL BC HL HL 1 B B 1 INDR 11101101 10111010 implied if B 0 repeat HL BC HL HL 1 B B 1 INI 11101101 10100010 implied 4 12 3 3 3 3 HL BC HL 1 B 1 INIR 11101101 10110010 implied gt if B 1 0 repeat HL BC HL HL 1 B B 1 JP HL 11101001 implied 1 3 PC HL JP IX 11011101 11101001 implied 2 6 3 3 lt PC IX JP IY 11111101 11101001 implied 2 6 3 3 es 11 010 n ms immed Sm 035 ets if f PC mn JP mn 11000011 n m immed 3 9 3 3 3 1 mn JRecj 001 000 3 2 relative sm 5022 liffec PC j JRj 00011000 3 2 relative 3 8 3 3 2 1 LD BC A 00000010 implied 3 7 3 1 3 1 BC A LD DE A 00010010 implied 3 7 8 1 3 DE A LD HL n 00110110 n immed 3 9 3 3 3 1 HL 2n LD HL 01110 r reg 3 7 8 1 3 HL r LD IX d n 110
9. wr2 fone done JP HL done JP IX if2 done JP IY if2 done ofi done done JP mn ofi of2 done JR cc jj of1 pn done JRj of1 iop2 done LD BC A iop1 wr2 done LD DE A iop1 wr2 done LD HL n wr2 done LD HL r iop1 wr2 done Systemyde International Corporation Y180 02 96 Rev 1 0 Page 30 Instruction if1 dly if2 of1 of2 if3 iop sif1 sdly sif2 rd1 rd2 siop wrt wr2 fiop LD IX d n if2 of1 of2 wr2 done LD IX d r if2 iop3 wr2 done LD IY d n if2 of2 wr2 done LD IY d r if2 iop3 wr2 done LD mn A of1 of2 iop1 wr2 done LD mn HL of1 of2 iop1 wr1 wr2 done LD mn IX if2 of1 of2 1 wr1 wr2 done LD mn IY if2 of1 of2 1 wrt wr2 done LD mn ss if2 of2 1 wrt wr2 done LD A BC rd2 done LD A DE rd2 done LD A mn of1 of2 rd2 done LD AJ if2 done LD A R if2 done LD dd mn if2 of2 rdi rd2 done LD dd mn of1 of2 done LD HL mn of1 of2 rd1 rd2 done LD I A if2 done LD IX mn if2 ofi of2 rdi rd2 done LD IX mn if2 ofi of2 done LD IY mn if2 ofi of2 rd1 rd2 done LD IY mn if2 ofi of2 done LD r HL rd2 done LD r IX d if2
10. A 15 0 dec Hac X r Xx IORQB_ RDB_ WRB_ WAITB_ DOEB_ E Read E Write Systemyde International Corporation Y180 02 96 Rev 1 0 Page 46 5 7 Bus Request Acknowledge Entry The timing of the release of processor control of the bus is shown below The 180 can release the bus after completion of any machine cycle None of the Y 180 signals actually go floating rather the various output enable signals go inactive and the BUSACKB signal is activated T2 or Ti T3 or Ti TX TX CLK CLKB A_ 15 0 DIN 7 0 DOUT 7 0 BUSREQB _ BUSACKB _ AOEB _ COEB DOEB _ Systemyde International Corporation Y180 02 96 Rev 1 0 Page 47 5 8 Bus Request Acknowledge Exit The timing for resumption of processor control of the bus is shown below The Y180 can reacquire the bus during any clock cycle of the bus release phase The various output enable signals go active and the BUSACKB signal is deactivated CLK CLKB A 15 0 DIN 7 0 DOUT 7 0 BUSREQB BUSACKB _ AOEB _ COEB DOEB _ Systemyde International Corporation Y180 02 96 Rev 1 0 Page 48 5 9 Trap second opcode byte The timing of an undefined second byte opcode trap is shown below The fetch of the undefined opcode is followed by the Trap cycle five internal operation cycles and two normal
11. 39 39 40 40 4l 4l 42 43 44 45 46 47 48 49 50 5 52 53 54 55 56 57 58 59 60 61 63 64 64 64 65 65 65 65 65 66 66 67 67 68 68 68 68 02 96 Rev 1 0 Page 4 Table of Contents continued 9 7 Trap on Third Byte Operation 68 9 8 BIT OPS Manipulation Operation 68 9 9 JMP OPS Jump Operation 69 9 10 IO OPS I O Operation 69 10 Installation 70 10 1 File Structure E 71 Systemyde International Corporation Y180 02 96 Rev 1 0 Page 5 1 Introduction The Y180 is a synthesizable Verilog HDL model of the Z80180 CPU It is software and hardware compatible with the Z80180 CPU and is software compatible with several other industry standard processors The Y180 is an original design based on publically available documentation that employs design techniques suitable for a technology independent implementation It is a fully synchronous design that does not use 3 state busses The design is structured in a way that allows its use either with or without modification by the customer The combinatorial logic portions of the design may be implemented in either random logic or as a PLA and control signals are treated symbolically in the design to allow either encoded or unencoded implementations the default is encoded The Y180 is accompanied by full design documentation in the form of a large spreadsheet which describes nearly e
12. DOEB_ Systemyde International Corporation Y180 02 96 Rev 1 0 Page 44 5 5 O Read Write without Wait State The timing for an I O read or I O write cycle is shown below These bus cycles are four clock cycles long three plus an automatic Wait state with the WAITB input sampled at the falling edge of CLK in TW In the case of I O read the DIN bus sampled at the falling edge of CLK in and the RDB signal is activated In the case of I O write the DOUT bus is driven with valid data for the duration of a I O write cycle and the WRB_ and DOEB signals are activated The IORQB signal is used to distinguish I O read and write cycles from memory read and write cycles Note that the timing of the leading edge of IORQB and RDB are controlled by the IOCB input Also note that the timing of the E_ signal is different for I O read and I O write T2 xd z CLK_ L f L f L IORQB RDB WRB WAITB DOEB _ E Read E Write Systemyde International Corporation Y180 02 96 Rev 1 0 Page 45 5 6 I O Read Write with Wait State The timing for an I O read or I O write cycle with one inserted Wait state is shown below These bus cycles are five clock cycles long three plus one automatic and one inserted Wait state with the WAITB input sampled at the falling edge of CLK_ in TW All of the control signals are stretched by the insertion of the Wait state CLKB
13. mesg direc 4 12 3 3 3 3 A mn LD AJ 11101101 01010111 implied 2 6 3 3 IA 1 LD A R 11101101 01011111 implied 2 6 3 3 LD dd mn 11101101 01441011 m direc 6 18 3 3 3 3 3 3 ddl mn ddh mn 1 LD dd mn 00dd0001 n m direc 3 9 3 3 3 dd mn LD HL mn 00101010 m direc 5 15 3 3 3 3 3 L mn mn 1 LD I A 11101101 01000111 implied 2 6 3 3 flea LD IX mn 11011101 00101010 m direc 6 18 3 3 3 3 3 3 mn IXH mn 1 LDIX mn 11011101 00100001 n m direc 4 12 3 3 3 3 IX mn LD IY mn 11111101 00101010 m direc 6 18 3 3 3 3 3 3 YL mn 1 LDIY mn 11111101 00100001 n m direc 4 12 3 3 3 3 LD r HL 01 r 110 reg ind 2 6 3 3 LD r IX d 11011101 01 r 110 4 index 5 14 3 3 3 2 3 r IX d LD r IY d 11111101 01 r 110 4 index 5 14 3 3 3 2 3 LD R A 11101101 01001111 implied 2 6 3 3 ReA LD 00 r 110 n immed 2 6 3 3 5105 2 4 3 1 inet LD SP HL 11111001 implied 2 4 3 1 1 1 1 185 LD 11011101 11111001 implied 3 7 3 3 1 1 1 1 15 1 LD SP IY 11111
14. 150 8 bit Microprocessor Synthesizable Verilog HDL Model User Manual Systemyde International Corporation Y180 02 96 Rev 1 0 1 Disclaimer Systemyde International Corporation reserves the right to make changes at any time without notice to improve design or performance and provide the best product possible Systemyde International Corporation makes no warrant for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make any commitment to update the information contained herein Systemyde International Corporation products are not authorized for use in life support devices or systems unless a specific written agreement pertaining to such use is executed between the manufacturer and the President of Systemyde International Corporation Nothing contained herein shall be construed as a recommendation to use any product in violation of existing patents copyrights or other rights of third parties No license is granted by implication or otherwise under any patent patent rights or other rights of Systemyde International Corporation All trademarks are trademarks of their respective companies Copyright 1995 Systemyde International Corporation Livermore Ca All rights reserved Systemyde International Corporation http www systemyde com y180Gsystemyde com Systemyde International Corporation Y180 02 96 Rev 1 0 Page 2 Table of Contents Introduction 2 Features 3
15. Wait Request 4 27 WRB_ Write 5 Bus Cycles 5 1 Instruction Fetch Wait state 5 2 Instruction Fetch with Wait state 5 3 Memory Read Write without Wait state 5 4 Memory Read Write with Wait state 5 5 I O Read Write without Wait state 5 6 I O Read Write with Wait state 5 7 Bus Request Acknowledge Entry 5 8 Bus Request Acknowledge Exit 5 9 Trap Second Opcode 5 10 Trap Third Opcode 5 11 Non Maskable Interrupt Aknswledas 5 12 Mode 0 Interrupt Acknowledge 5 13 Mode 1 Interrupt Acknowledge 5 14 Mode 2 Interrupt Acknowledge 5 15 Return From Interrupt RETI 5 16 Halt Entry and Exit 5 17 Sleep Entry and Exit 5 18 E Signal during Sleep 5 19 E Signal during Bus Remiestinckuowledse 5 20 Reset and Clear 6 Differences 7 Future Enhancements 8 Model Organization 8 1 Y180 TOP Top Level Module 8 2 PARAMS Parameter Definition include file 8 3 IO CTRL I O Interface Module 8 4 M STATE Machine State Module 8 5 Central Control Module 8 6 DATA IO Address and Data Module 8 7 REG BYTE Byte wide Register in the Register File 8 8 8BIT Byte wide General Purpose Register 9 Test Suite 9 TOP LEV Top Level for Simulation 9 2 SETUP HL Initialization Pattern 9 3 INT OPS Interrupt Operation 9 4 ALU_OPS ALU Operation 9 5 DAT MOV Data Movement 9 6 2ND Trap on Second Byte Operation Systemyde International Corporation Y180
16. 3 1 3 0 P O IY d IY d 6 0 IY d 7 CY IY d 7 RLCr 11001011 00000 r reg 3 7 8 3 1 0 PO r r 6 0 r 7 r 7 RLCA 00000111 implied 1 3 01 10 A 6 0 A 7 CY RLD 11101101 01101111 implied 5 16 3 3 3 4 3 A 3 0 HL 7 4 HL HL 3 0 A 3 0 RR HL 11001011 00011110 reg ind 5 13 3 3 3 1 3 HL CY CY HL RR IX d 11011101 11001011 d 00011110 index 7 19 3 3 3 3 3 1 3 IX d CY CY IX d RR IY d 11111101 11001011 d 00011110 index 7 19 3 3 3 3 3 1 3 IY d CY CY IY d 11001011 00011 r reg 3 7 3 3 1 0 P0 r CY RRA 00011111 implied 1 3 0 0 A CY CY A RRC HL 11001011 00001110 reg ind 5 13 3 3 3 1 3 HL HL 0 HL 7 1 CY HL 0 IX d 11011101 11001011 d 00001110 index 7 19 3 3 3 3 3 1 3 IX d IX d 0 IX d 7 1 IX d 0 RRC IY d 11111101 11001011 d 00001110 index 7 19 3 3 3 3 3 1 3 IY d IY d 0 IY d 7 1 CY 9 0 RRC r 11001011 00001 r reg 3 7 8 3 1 olplo r 01 7 1 CY qo RRCA 00001111 implied 1 3 01 10 A 0 A 7 1 CY A 0 RRD 11101101 01100111 implied 5 16 3 3 3 4 3 A 3 0 HL 3 0 HL A 3 0 HL 7 4 RSTv 11 v 111 implied 4 11 3 2 3 3 tua ess SP 1 PCH SP 2 PCL SP SP 2 PC v SBC IX d 11011101 10011
17. 4 PE HL PE mn DE HL PE mn n 5 F RET POP JP DI CALL PUSH OR RST RET LD JP El CALL esc CP RST P AF n 6 M SP HL M mn M mn n T Systemyde International Corporation Y180 02 96 Rev 1 0 Page 11 3 4 2 ED Code Page This table shows the code page for instructions whose first byte is EDh These are miscellaneous instructions that will usually not be used as often as those on the main code page LSB 1 2 3 4 5 6 7 8 9 n B D E F MSB 0 INO OUTO TST INO OUTO TST B n 0 8 B nC 1 INO OUTO TST INO OUTO TST 0 0 n D D E n E 2 INO OUTO TST INO OUTO TST H n 0 H L n n L L 3 TST INO OUTO TST HL A n mA A 4 IN OUT SBC LD NEG REN IM LD IN OUT ADC LD MT RETI LD B C HL BC mn BC 0 LA C O C C HL BC BC mn BC RA 5 IN OUT SBC LD IM LD IN OUT ADC LD MT IM LD D C HL DE mn DE 1 Al DE mn DE 2 AR 6 IN OUT SBC LD TST RRD IN OUT ADC LD MLT RLD H C n L C HLHL HL mn HL 7 SBC LD TSTIO SLP IN OUT ADC LD MIT HLSP mn SP m A C HLSP SP mn SP 8 OTIM OTDM 9 OTIMR OTDMR A LD OUT LDD CPD IND OUTD B LDR NIR LDDR CPDR INDR OTDR D E F Sys
18. Functional Desctipton 3 1 3 2 3 3 3 4 3 5 Block Diagram Register Description Flags Description Instruction Maps 3 4 1 Main Code page 3 4 2 ED Code page 3 4 3 DD Code page 3 4 4 FD Code page 3 4 5 CB Code page 3 4 6 DD CB Code page 3 4 7 FD CB Code page Execution Tables 3 5 1 Execution Table conventions i 3 5 2 Instruction Opcode Timing and Operation 3 5 3 Address Bus Contents 3 5 4 Next Machine State 4 Pin Descriptions 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 4 19 4 20 4 21 4 22 4 23 15 0 T Address Bus AOEB Address Output Enable BUSACKB Bus Acknowledge BUSREQB Bus Request CLEARB Master Clear CLK Clock CLKB Clock Bar COEB Control Output Enable DIN 7 0 Data Input Bus DOEB_ Data Output Enable DOUT 7 0 Data E Bus E Enable HALTB Halt Mode INTB_ Interrupt Request IOCB_ Control Select IORQB I O Request MIB Machine Cycle 1 MIE Machine Cycle 1 Enable MREQB Memory Request NMIB Non Maskable d Request RDB_ Read RESETB Master Reset SLPB Sleep Mode Systemyde International Corporation Y180 W O 9 10 11 11 12 13 14 15 16 17 18 18 19 24 29 34 35 35 35 35 35 36 36 36 36 36 37 37 37 37 37 38 38 38 38 38 39 39 39 02 96 Rev 1 0 Page 3 Table of Contents continued 4 24 ST Status 4 25 TRAPB Trap 4 26 WAITB_
19. Sleep In the Sleep mode the E_ signal is continuously generated with a four clock cycle period The timing of the E signal is synchronized with the start of the Sleep mode and terminates cleanly at the end of the Sleep mode as shown below This behavior is controlled by a small state machine in the IO CTRL section of the design and can be eliminated if unnecessary or for further power savings during Sleep mode Systemyde International Corporation Y180 02 96 Rev 1 0 Page 58 5 19 Signal during Bus Request Acknowledge During the release of processor control of the bus the E_ signal is continuously generated with a four clock cycle period The timing of the E signal is synchronized with the start of the bus release and terminates cleanly when the processor reacquires control of the bus as shown below This behavior is controlled by a small state machine in the IO CTRL section of the design and can be eliminated if unnecessary Systemyde International Corporation Y180 02 96 Rev 1 0 Page 59 5 20 Reset and Clear The Reset state is entered when the RESETB pin is Low for two consecutive rising edges of CLKB as shown below On the next rising edge of CLK after RESETB has been sampled Low twice the Y 180 enters the Reset state independent of the current machine cycle or clock cycle It remains in the Reset state until after RESETB _ is sampled High At that time the Y 180 begins fetching instructions from location 0000h The Reset s
20. during the synthesis process 9 1 TOP LEV Top Level for Simulation TOP LEV is the top level module for simulation It contains the Y180 module itself a read memory which is loaded with the program to be executed a compare memory which is loaded with the compare data for the program the clock generator a pair of reset tasks a couple of tasks useful for debugging interrupt and NMI generators a Wait generator a Bus Request generator and a compare error flag and counter The top level as supplied runs through the entire test suite without Wait or Bus Request followed by a pass with one wait state in every bus cycle followed by a pass where Bus Request is active all the time and is released for one clock cycle at a time to allow only one machine cycle to be executed between bus requests The Bus Request pass is several times longer than an individual pass and can be eliminated if necessary by editing the file so that the patterns are not executed while the variable DISABLE is zero 9 2 SETUP HL initialization Pattern SETUP HL is a short pattern used to initialize the HL register pair before starting the first pattern Executing this pattern first makes it possible to rearrange the order of the remaining patterns This is because several of the patterns require HL to contain a jump address at the start of the pattern In a similar fashion the HL register pair is initialized at the end of every pattern Every pattern ends with wha
21. edge of CLK for instruction fetch cycles and for the interrupt acknowledge cycles in interrupt mode 0 In all other cases the DIN 7 0 is sampled by the rising edge of CLKB The DIN 7 0 and the DOUT 7 0 may be combined externally to the Y180 with the direction of this bus controlled by the DOEB signal 4 10 DOEB Data Output Enable The Data Output Enable signal can be used to control 3 state buffers on DOUT 7 0 external to the Y 180 or to control the 3 state buffers on a bidirectional data bus external to the Y 180 This signal will be active Low when the Y180 should be Systemyde International Corporation Y180 02 96 Rev 1 0 Page 36 driving the data bus and inactive High when the Y 180 is either reading data from the bus or releasing the bus for another bus master to drive 4 11 DOUT 7 0 Data Output Bus The 8 bit Data Output Bus is used to communicate data from the Y180 DOUT 7 0 changes on the rising edge of CLK_ and is valid only for the duration of the write cycle 4 12 E Enable The Enable signal is a synchronous machine cycle clock that is active High during bus transactions It can be used by some peripheral families as a data strobe 4 13 HALTB Halt Mode The Halt Mode signal is active Low while the Y180 is in Halt mode or Sleep mode Halt mode is entered when the HALT instruction is executed while Sleep mode is entered when the SLP instruction is executed In either case the Y180 will remain in th
22. if2 En 511 sdly sif2 rdi rd2 done RETN if2 rd1 rd2 done RL HL if2 rd2 siop wr2 done RL IX d if2 rd2 siop wr2 done RL IY d if2 of1 if3 rd2 siop wr2 done RL r if2 iop1 done RLA done RLC HL if2 rd2 siop wr2 done RLC IX d if2 if3 rd2 siop wr2 done RLC IY d if2 if3 2 siop wr2 done RLCr if2 iop1 done RLCA done RLD if2 rd2 siop4 wr2 done RR HL if2 rd2 siop wr2 done RR IX d if2 if rd2 siop wr2 done RR IY d if2 if rd2 siop wr2 done RRr if2 iop1 done RRA done RRC HL if2 rd2 siop wr2 done RRC IX d if2 if rd2 siop wr2 done RRC if2 if rd2 siop wr2 done RRCr if2 iop1 done RRCA done RRD if2 rd2 siop4 wr2 done RST v iop2 wri wr2 done SBC IX d 12 ofi iop2 rd2 done SBC IY d if2 ofi iop2 rd2 done SBC A HL rd2 done SBC A n done SBC A r iop1 done SBC HL ss if2 iop4 done SCF done SET b HL if2 rd2 siop1 wr2 done SET b IX d if2 2 siop1 wr2 done SET b IY d if2 2 siop1 wr2 done SET b r if2 iop1 done Systemyde International Corporation Y180 02 96 Rev 1 0 Page 32 Instruction if1 dly if2 of1 of2 if3 iop sif1 sdly sif2 rd1 rd2 siop wr1 wr2 fiop SLA HL if2 rd2 siop wr
23. invalid opcode is fetched during the Mode 0 interrupt acknowledge cycle CLK_ A_ 15 0 DIN_ 7 0 RSTiinstruction DOUT 7 0 MIB IORQB_ MREQB_ k RST nsir Systemyde International Corporation Y180 02 96 Rev 1 0 Page 52 5 13 Mode 1 Interrupt Acknowledge The timing of a Mode 1 interrupt acknowledge cycle is shown below The Mode 1 interrupt acknowledge cycle consists of a three clock cycle plus two automatic Wait states special bus cycle followed by two normal write cycles to push the contents of the PC onto the stack The processor then jumps to location 0038h for the service routine TI T2 TW TW CLK 15 0 DIN 7 0 DOUT 7 0 Y180 02 96 Rev 1 0 Page 53 Systemyde International Corporation 5 14 Mode 2 Interrupt Acknowledge The timing of a Mode 2 interrupt acknowledge cycle is shown below The Mode 2 interrupt acknowledge cycle consists of a three clock cycle plus two automatic Wait states special bus cycle which reads a vector from the data bus an internal operation cycle followed by two normal write cycles to push the contents of the PC onto the stack followed by two normal read cycles to fetch the interrupt jump table entry corresponding to the vector fetched during the special bus cycle The processor then jumps to the address fetched from the interrupt jump table for the service routine The upper eight bits of the interrupt jump table starting addres
24. 101 11111001 implied 3 7 3 3 1 1 1 1 15 1 LDD 11101101 10101000 implied 4 12 3 3 3 3 0 0 DE HL BC 1 DE DE 1 HL HL 1 1 24101 025 10111099 implied 50 14 33332 947242 HL BC 1 DE 1 HL HL 1 LDI 11101101 10100000 implied 4 12 3 3 3 3 0 0 DE HL BC BC 1 DE DE 1 HL HL 1 FD 19110000 implied 50 14 33332 HL BC 5 BC 1 DE DE 1 HL HL 1 MLT ww 11101101 01ww1100 reg 3 16 8 3 10 ww wwl wwh NEG 11101101 01000100 implied 2 6 3 3 V 1 0 NOP 00000000 none 1 3 operation OR HL 10110110 regind 2 6 3 3 0 P 0 0 A A HL OR IX d 11011101 10110110 4 index 5 14 3 3 3 2 3 0 0 IX d 11111101 10110110 4 index 5 14 3 3 3 2 3 0 0 IY d ORn 11110110 n immed 2 6 3 3 A A n ORr 10110 r reg 2 4 3 1 0 0 OTDM 11101101 10001011 implied 6 14 3 3 1 3 3 1 P C HL HL HL 1 1 1 OTDMR 11101101 10011011 implied 2m 1 0 P 0 BS see s HL 1 B B 1 C 1 OTDR 11101101 10111011 implied 1503502 if fB 0 repeat BC HL HL HL 1 B 1 OTIM 11101101 10000011 implied 6 14 3 3 1 3 3 1 P C HL HL HL 1 1 C 1 OTIMR 11101101 10010011 implied 57 ic Sen 0 HL 1
25. 1011 10 b 110 regind 5 13 3 3 3 1 3 HL HL 8 bit RES b IX d 11011101 11001011 4 10 110 index 7 19 3 3 3 3 3 1 3 1 IX d amp bit RES b IV d 11111101 11001011 4 10 110 index 7 19 3 3 3 3 3 1 3 5 25258 IY d IY d amp bit RES b r 11001011 10 b r reg 3 7 3 3 1 1 1 r r amp bit RET 11001001 implied 3 9 3 3 3 1 1 PCL SP PCH SP 1 SP SP 2 11 000 implied 41 100133 sees if f PCL SP PCH SP 1 SP SP 2 RETI 11101101 01001101 implied rn PCL SP PCH SP 1 SP SP 2 RETN 11101101 01000101 implied 4 12 3 3 3 3 PCL SP PCH SP 1 SP SP 2 IEF2 IEF1 RL HL 11001011 00010110 regind 5 13 3 3 3 1 3 o P o CY HL HL CY RL IX d 11011101 11001011 d 00010110 index 7 19 3 3 3 3 3 1 3 CY IX d IX d CY RL 9 11111101 11001011 d 00010110 index 7 19 3 3 3 3 3 1 3 CY IY d IY d CY RL r 11001011 00010 r reg 3 7 8 3 1 r CY RLA 00010111 implied 1 3 01 10 CY A A CY RLC HL 11001011 00000110 reg ind 5 13 3 3 3 1 3 HL HL 6 0 HL 7 CY HL 7 RLC IX d 11011101 11001011 d 00000110 index 7 19 3 3 3 3 3 1 3 IX d IX d 6 0 IX d 7 CY IX d 7 IY d 11111101 11001011 d 00000110 index 7 19 3 3 3 3
26. 110 4 index 5 14 3 3 3 2 3 51 11 A A IX d CY SBC IY d 11111101 10011110 4 index 5 14 8 3 3 2 3 51 11 A A IY d CY SBC A HL 10011110 reg ind 2 6 3 3 1 HL CY SBC A n 11011110 n immed 2 6 3 3 1 SBC A r 10011 r reg 2 4 3 1 Vi1 A A r CY SBC HL ss 11101101 01550010 reg 3 10 3 3 4 HL HL ss CF SCF 00110111 none 1 3 01 10 1 SET b HL 11001011 11 b 110 regind 4 13 3 3 3 1 3 1 1 HL HL bit SET b IX d 11011101 11001011 d 11 b 110 index 7 19 3 3 3 3 3 1 3 IX d IX d bit SET b IY d 11111101 11001011 d 11 b 110 index 7 19 3 3 3 3 3 1 3 E IY d IY d bit SET b r 11001011 11 b r reg 3 7 3 3 1 54 r r bit Systemyde International Corporation Y180 02 96 Rev 1 0 Page 22 Instruction Opcode Opcode Opcode Opcode Addr Mach Clock cycles H P N C Operation byte 1 byte 2 byte 3 byte 4 Mode State SLA HL 11001011 00100110 reg ind 5 13 3 3 3 1 3 HL HL 6 0 0 CY HL 7 SLA IX d 11011101 11001011 d 00100110 index 7 19 3 3 3 3 3 1 3 0 P 0 IX d IX d 6 0 0 CY IX d 7 SLA IY d 11111101 11001011 d 00100110 index f 19 3 3
27. 110 0030h 111 0038h XX word register select 00 BC 01 DE 10 IX 11 SP yy word register select 00 BC 01 DE 10 IY 11 SP ZZ word register select 00 BC 01 DE 10 HL 11 AF The conventions used in the flag columns of the execution tables are as follows No change E Updated per convention 0 1 Reset to zero or set to one IE Set to value of IEFI bit P V Reports the parity P or overflow V status of the result Systemyde International Corporation Y180 02 96 Rev 1 0 Page 18 3 5 2 Instruction Opcode Timing and Operation The execution table below shows the instruction or exception the opcode the addressing mode the number of machine cycles the number and organization of the clock cycles the flags affected by the instruction and the operation performed by the instruction or exception Instruction Opcode Opcode Opcode Opcode Addr Mach Clock cycles N Operation byte 1 byte 2 byte 3 byte 4 Mode State A HL 10001110 regind 2 6 3 3 0 CF ADC A IX d 11011101 10001110 4 index 5 14 3 3 3 2 3 V 0 A A IX d CF ADC A IV d 11111101 10001110 4 index 5 14 3 3 3 2 3 V 0 A A IY d ADC 11001110 n immed 2 6 3 3
28. 11101 00110110 immed 5 15 3 3 3 3 3 Ak IX d n LD IX d r 11011101 01110 r 4 reg 5 15 3 3 3 3 3 IX d LD IY d n 11111101 00110110 immed 5 15 3 3 3 3 3 go os IY d n LD IY d r 11111101 01110 r reg 5 15 3 3 3 3 3 1 ly d r LD mn A 00110010 m direct 5 13 3 3 3 1 3 1 mn A Systemyde International Corporation Y180 02 96 Rev 1 0 Page 20 Instruction Opcode Opcode Opcode Opcode Addr Mach Clock cycles H P N C Operation byte 1 byte 2 byte 3 byte 4 Mode State LD mn HL 00100010 n mass direc 6 16 3 3 3 1 3 3 mn mn 1 H LD mn IX 11011101 00100010 m direct 7 19 3 3 3 3 1 3 3 mn mn 1 IXH LD mn IY 11111101 00100010 n m direct 7 19 3 3 3 3 1 3 3 mn mnet LD mn ss 11101101 01550011 n m direc 7 19 3 3 3 3 1 3 3 mn ssl mn 1 ssh LD A BC 00001010 implied 2 6 3 3 LD A DE 00011010 implied 2 6 3 3 1 1 1 LDA mn 00111010 n
29. 2 done SLA IX d if2 rd2 siop wr2 done SLA IY d if2 if rd2 siop wr2 done SLA if2 iop1 done SLP if2 iop2 done SRA HL if2 rd2 siop wr2 done SRA 1 4 if2 3 rd2 siop wr2 done SRA IY d if2 rd2 siop wr2 done SRAr if2 iop1 done SRL HL if2 rd2 siop wr2 done SRL IX d if2 2 siop wr2 done SRL IY d if2 of1 if3 rd2 siop wr2 done SRL r if2 iop1 done SUB HL rd2 done SUB 1 0 if2 of1 iop2 rd2 done SUB IY d if2 of1 iop2 rd2 done SUBn of1 done SUB iop1 done TST HL if2 iop1 rd2 done TSTn if2 of done if2 iop1 done TSTIOn if2 of1 rd2 done XOR HL rd2 done XOR IX d if2 of1 iop2 rd2 done XOR IY d if2 of1 iop2 rd2 done XORn of1 done XORr iop1 done ZIACKO ZIACK1 wrt wr2 done ZIACK2 wrt rd2 done wr2 done ZNMIACK wrt wr2 rdi ZTRAP2 wrt wr2 done wrt wr2 done 1 2 and are instruction fetch cycles for the first second and third opcode respectively dly is used only with DJNZ to speed operation by decrementing and checking b before fetching the displacement ofl and of2 the operand fetch cycles lop are Internal operation cycles and can be up to 10 clocks long sifl and sif2 are the RETI instruction refetch cycles sdly is a delay cycle needed between the RETI instruction refetch cycles rdl and rd2 memory or I O read cycles rd2 is used for byte reads and both and rd2 are used for word reads siop are internal operati
30. 3 3 3 1 3 0 P 0 IY d IY d 6 0 0 CY IY d 7 SLAr 11001011 00100 r reg 3 7 8 3 1 r r 6 0 0 CY r 7 SLP 11101101 01110110 none 3 8 3 3 2 1 1 1 SRA HL 11001011 00101110 regind 5 13 3 3 3 1 3 0f Pf 0f HL HL 7 HL 7 1 CY HL 0 SRA IX d 11011101 11001011 00101110 index 7 19 3 3 3 3 3 1 3 o P 0 IX d IX d 7 IX d 7 1 CY IX d 0 SRA IY d 11111101 11001011 00101110 index 7 19 3 3 3 3 3 1 3 o P 0 IY d I d 7 IY d 7 1 CY IY d 0 SRAr 11001011 00101 r reg 3 7 8 3 1 0 P O 7 7 1 CY qo SRL HL 11001011 00111110 regind 5 13 3 3 3 1 3 o HL 0 HL 7 1 CY HL 0 SRL IX d 11011101 11001011 00111110 index 7 19 3 3 3 3 3 1 3 0 PO IX d 0 IX d 7 1 CY IX d 0 SRL IY d 11111101 11001011 4 00111110 index 7 19 3 3 3 3 3 1 3 0 P 0 IY d 0 IY d 7 1 IY d 0 SRL r 11001011 00111 r reg 3 7 3 3 1 r 0 r 7 1 CY r 0 SUB HL 10010110 2 6 3 3 1 HL SUB IX d 11011101 10010110 index 5 14 3 3 3 2 3 Vi1 A A IX d SUB IY d 11111101 10010110 4 index 5 14 3 3 3 2 3 VIi1 0 SUBn 11010110 n immed 2 6 3 3 1 SUBr 10010 r reg 2 4 3 1 Vi1
31. A A r TST HL 11101101 00110100 reg ind 4 10 3 3 1 3 11 10 10 A amp C HL TSTn 11101101 01100100 immed 3 9 3 3 3 amp 11101101 00 r 100 reg 3 7 3 3 1 11 1010 A amp r TSTIO n 11101101 01110100 n direct 4 12 3 3 3 3 11 10101 0 8 XOR HL 10101110 reg ind 2 6 3 3 0 amp HL A amp HL XOR IX d 11011101 10101110 4 index 5 14 3 3 3 2 3 0 0 amp IX d A amp IX d XOR IY4d 11111101 10101110 index 5 14 3 3 3 2 3 0 P 0 0 A A amp IV d A amp IY d XORn 11101110 n immed 2 6 3 3 amp amp 10101 r reg 2 4 3 1 0 amp 1 A amp r ZIACKO none 1 3 1 0 IEF2 0 ow 1 4 ZIACK2 none 6 16 31 33 3 3 e a o pee Pas n SP SP2 ZNMIACK 4 11 3 2 3 3 S esl al Pen t SP 2 ZTRAP2 none 3 12 6 3 3 SP 1 SP 2 PCL SP SP 2 0000h ZTRAP3 none 3 10 4 3 3 SP 1 PCH SP 2 PCL SP SP 2 PC 0000h Systemyde International Corporation Y180 02 96 Rev 1 0 Page 23 3 5 3 Address Bus Contents The execution table below shows the contents of the Address Bus for each machine cycle The Address Bus is only valid during memory I O and interrupt acknowledge cycles and will be undefi
32. BUSACKB Bus Acknowledge The Bus Acknowledge signal is active Low when the Y180 has relinquished control of the address bus data bus and control signals to another bus master in response to a request on the BUSREQB signal 4 4 BUSREQB Bus Request When the Bus Request signal is active Low the Y180 will relinquish control of the address bus data bus and control signals upon completion of the current machine cycle and then signal that it has done so by activating the BUSACKB signal An external bus master may then take control of these buses The BUSREQB is the highest priority request except for RESETB that will be accepted by the Y180 BUSREQB cannot be masked and is higher priority than NMIB 4 5 CLEARB Master Clear The Master Clear signal should be activated Low on power up at the same time as the RESETB signal but only if the contents of the register file need to be initialized to known values CLEARB will reset all register file contents to all zeros as opposed to RESETB which only initializes a few registers Do not active CLEARB at any other time unless you really want to clear the register file In particular if you are exiting Halt mode or Sleep mode with reset use RESETB only unless register file data does not need to be preserved Systemyde International Corporation Y180 02 96 Rev 1 0 Page 35 4 6 CLK Clock This is the master Clock input All internal signals change state on the rising edge of this cl
33. D 6 6H 6L 6 H 6A 7B 7C 7D ZE 7H 7L 7 H ZA SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET OB 0 OE OH OL O H OA tB tC 1D 1E tH tL t H 1A D SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET 2B 2c 2D 2E 2H 2L 2 H 2A 30 3E 3H 3L 3 H E SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET 4B 4C 4D 4E 4H 4L 4 HD 5B 5C 5D 5E 5H 5L 54 F SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET 6B 6C 6D 6E 6H 6L 6 H 6A 7B ZC 7D ZE 7H 7L 7 H 7A Systemyde International Corporation Y180 02 96 Rev 1 0 Page 15 3 4 6 DD CB Code Page This table shows the code page for instructions whose first two bytes are DDh followed by CBh All instructions on this code page imply the use of the IX register in one way or another Note that wherever the HL register is used in a CB code page instruction the corresponding instruction on this code page uses either the IX register or the indexed addressing mode using the IX register LSB 0 1 2 3 4 5 6 7 8 9 A B D E F MSB 0 RLC RRC IX d IX d 1 RL RR IX d IX d 2 SLA S
34. IB or INTB_ the processor will resume instruction execution after the interrupt service routine at the address of the instruction following the HALT instruction CLK_ A_ 15 0 DIN_ 7 0 MIB MREQB_ RDB_ HALTB_ INTB_ HALT J kK Interrupt Acknowledge Systemyde International Corporation Y180 02 96 Rev 1 0 Page 56 5 17 Sleep Entry and Exit The Sleep mode is entered when the SLP instruction is executed as shown below In the Sleep mode the processor continuously performs Sleep cycles which are single clock cycle bus cycles identical to internal operation cycles except that both the HALTB_ output and SLPB_ outputs are Low In the Sleep mode Bus release through BUSREQB _ BUSACKB can still occur but the only way to exit the Sleep mode is with either interrupt NMIB_ or INTB or via reset The timing for exiting the Sleep mode via INTB is shown below Note that INTB_ can only be used to exit the Sleep mode interrupts are enabled when the SLP instruction is executed If the Sleep mode is exited via NMIB_ or INTB the processor will resume instruction execution after the interrupt service routine at the address of the instruction following the SLP instruction CLK_ A_ 15 0 DIN_ 7 0 MIB MREQB_ RDB_ SLPB_ HALTB_ INTB_ k Sleep mode Interrupt Acknowledge Systemyde International Corporation Y180 02 96 Rev 1 0 Page 57 5 18 Signal during
35. L HL A B C D E H L HL A 3 SRL SRL SRL SRL SRL SRL SRL SRL B C D E H L HL A 4 BT Br BT BT BT BT BT oc OE OH OL OA 1B 1 1 1E tH tL iHD 1A 5 BT BT BT BT BT BT BT BT 2B 2c 2D 2E 2H 2L aly 2A 30 3E 3L 6 BT BT BT BT BT BT BT BT 4B 4C 4D 4E 4H 4L 4H 4A 5B 5C 5D 5E 5H 5L 5 H 7 BT BT BT BT BT BT BT BT 6B 6 6D 6E 6H 6L 6A 7B 7C 7D ZE 7H 7L 7 H 7A 8 RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES oc oD OE OH OL OA 1B 1C 1 1E 1H tL 1H 1A 9 RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES 2B 2C 2D 2E 2H 2L 2 H 2A 3B 30 3E 3H 3L 3 H A RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES 4B 4C 4D 4E 4H 4L 4 HD 4A 5B 5c 5D 5E 5H 5L 5 B RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES 6B 6C 6
36. L HL HL mn HL L L L n 3 JR LD LD INC INC DEC LD SCF JR ADD LD DEC INC DEC LD CCF NC e SP mn mn A SP HL HL HL n HL SP A mn SP A A 4 10 LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD B B B C B D B E B H B L B HL B A CB c D CE C H CL C HL 5 LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD D B D D D E D H DE D HL D A EB E C ED RE E HL E A 6 LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD H B H C H D H H H L H HL LB L C L D L H L HL LA 7 LD LD LD LD LD LD HALT LD LD LD LD LD LD LD LD LD HL B HL C HL D HL E HL H HL L HL A A B AE A H A HL 8 ADD ADD ADD ADD ADD ADD ADD ADD ADC ADC ADC ADC ADC ADC ADC ADC AC AD AE A HL AC AD AE A HL 9 SUB SUB SUB SUB SUB SUB SUB SUB SBC SBC SBC SBC SBC SBC SBC SBC B D E H k HL A AC AD AE A HL AND AND AND AND AND AND AND AND XOR XOR XOR XOR XOR XOR XOR XOR B D E H L HL A B D E H HL A B OR OR OR OR OR OR OR OR CP CP CP CP CP CP CP CP B C D E H L HL A B C D E H L HL A RET POP JP JP CALL PUSH ADD RST RET RET JP esc CALL CALL ADC RST NZ BC NZ mn mn NZ mn BC A n 0 Z Z mn Z mn nn A n 1 D RET POP JP OUT CALL PUSH SUB RST RET EXX JP IN CALL esc SBC RST NC DE NC mn n A NC mn DE n 2 C C mn A n C mn A n 3 E RET POP JP EX CALL PUSH AND RST RET JP JP EX CALL esc XOR RST PO HL PO mn SP HL PO mn HL n
37. Master Reset The Master Reset signal should be activated Low on power up and at any other time where initializing the Y180 to a known state is necessary RESETB_ forces all output signals inactive resets all internal state machines clears the Program Counter Stack Pointer I register and R register If the remaining registers need to be initialized to known states the CLEARB_ signal should be simultaneously active 4 23 SLPB Sleep Mode The Sleep Mode signal is active Low while the Y180 is in Sleep mode Sleep mode is entered when the SLP instruction is executed The Y180 will remain in Sleep mode until either a RESETB_ INTB or NMIB occurs 4 04 ST Status The Status signal is used to aid in decoding of the current machine cycle especially when the MIE has disabled the activation of the MIB signal The ST signal is always active Low during the first instruction fetch cycle of an instruction and also during the Halt Mode 4 25 TRAPB Trap The Trap signal is active Low for one clock cycle whenever the Y180 has encountered an undefined opcode If TRAPB is active while the RDB signal is High the undefined opcode occured in the second byte of the instruction while if TRAPB is Active while the RDB signal is Low the undefined opcode occured in the third byte of the instruction Systemyde International Corporation Y180 02 96 Rev 1 0 Page 39 4 26 WAITB Wait Request When the Wait Request input is active Low during a
38. P PCH SP 2 PCL PC mn SP SP 2 CALL mn 11001101 m immed 6 16 3 3 3 1 3 3 SP 1 SP 2 PCL PC mn SP SP 2 CCF 00111111 none 1 3 0 CF CF CP HL 10111110 2 6 3 3 V 4 A HL CP IX d 11011101 10111110 4 index 5 14 8 3 3 2 3 V 1 A IX d 9 11111101 10111110 4 index 5 14 3 3 3 2 3 V 1 A IY d CPn 11111110 n immed 2 6 3 3 Vi 1 10111 r reg 2 4 3 1 Vi 1 CPD 11101101 10101001 implied 4 12 3 3 3 3 11 A HL BC 1 HL HL 1 CPDR 11101101 10111001 implied m 03522 JA e 5 SCHEME CPI 11101101 10100001 implied 4 12 3 3 3 3 1f A HL BC 1 HL HL 1 CPIR 11101101 10110001 implied 5522 11 10 CPL 00101111 implied 1 3 1 DAA 00100111 implied 2 4 8 1 Decimal Adjust Accumulator DEC HL 00110101 regind 4 10 3 3 1 3 V 1 HL HL DEC IX d 11011101 00110101 a index 7 18 3 3 3 2 3 1 3 v 1 IX d IX d 1 DEC IY4d 11111101 00110101 index 7 18 3 3 3 2 3 1 3 V 1 IY d IY d 1 Systemyde International Corporation Y180 02 96 Rev 1 0 Page 19
39. RA IX d IX d 3 SRL IX d 4 BIT BIT 0 IX d 1 IX d 5 BIT BIT 2 IX d 3 IX d 6 BIT BIT 4 IX d 5 IX d 7 BIT BIT 6 IX d 7 IX d 8 RES RES 0 IX d 1 IX d 9 RES RES 2 IX d 3 IX d A RES RES 4 IX d 5 IX d B RES RES 6 IX d 7 IX d SET SET 0 IX d 1 IX d D SET SET 2 IX d 3 IX d E SET SET 4 IX d 5 IX d F SET SET 6 IX d 7 IX d Systemyde International Corporation Y180 02 96 Rev 1 0 Page 16 3 4 7 FD CB Code Page This table shows the code page for instructions whose first two bytes are FDh followed by CBh All instructions on this code page imply the use of the IY register in one way or another This code page is identical to the DD CB code page with the IY register substituted for the IX register LSB 0 1 2 3 4 5 6 7 8 9 A B D E F MSB 0 RLC RRC IY d IY d 1 RL RR IY d 2 SLA SRA 3 SRL IY d 4 BIT BIT 0 IY d 1 IY d 5 BIT BIT 2 IY d 3 IY d 6 BIT BIT 4 IY d 5 IY d 7 BIT BIT 6 IY d 7 IY d 8 RES RES 0 1 9 1 IY d 9 RES RES 2 IY d 3 IY d A RES RES 4 IY d 5 IY d B RES RES 6 IY d 7 IY d 0 IY d 1 9 D SET SET 2 IY d 3 IY d E SET SET 4 IY d 5 IY d F SET SET 6 IY d 7 IY d Systemyde International Corporation Y180 02 96 Rev 1 0 Page 17 3 5 Execution Tab
40. V 0 A A n CF ADCA r 10001 r reg z 4 3 1 0 A A r CF ADC HL ss 11101101 01851010 reg 3 10 8 3 4 V 0 HL HL CF ADD A HL 10000110 2 6 3 3 015 HL ADD A IX d 11011101 10000110 4 index 5 14 3 3 3 2 3 V O IX d ADD A IY d 11111101 10000110 4 index 5 14 3 3 3 2 3 V 0 9 ADD 11000110 n immed 2 6 3 3 V 0 A A n ADD A r 10000 r reg 2 4 3 1 V 0 A A r ADD HL ss 00ss1001 reg 2 7 8 4 V 0 HL HL ss ADD IX xx 11011101 00xx1001 reg 3 10 8 3 4 V 0 IX IX xx ADD IY yy 11111101 00 1001 reg 3 10 3 3 4 V 0 IYzIY yy AND HL 10100110 2 6 3 3 P 0 0 A A amp HL AND IX d 11011101 10100110 4 index 5 14 3 3 3 2 3 P 0 amp 1 AND IY d 11111101 10100110 4 index 5 14 3 3 3 2 3 P 0 amp 1 9 AND n 11100110 n immed 2 6 3 3 P 0 amp AND 10100 r reg 2 4 3 1 0 BIT b HL 11001011 01 b 110 reg ind 3 9 3 3 3 0 HL amp bit BIT b IX d 11011101 11001011 01 b 110 index 5 15 3 3 3 3 3 10 IX d amp bit BIT b IY d 11111101 11001011 01 b 110 index 5 15 3 3 3 3 3 O IY d amp bit BIT b r 11001011 01 b r reg 2 6 3 3 0 r amp bit CALL 11 100 gt immed m 16 333133 SA S
41. am The figure below shows a simplified block diagram of the Y 180 organized in the same fashion as the Verilog HDL model is organized The I O Interface Module controls all of the pins of the Y 180 and translates the internal busses and signals into the externally visible pins The Machine State Module contains the machine cycle and clock cycle state machines which control the sequence and timing of everything that happens within the Y180 The Central Control Module decodes the instruction and state information to generate all of the internal control signals And the Address and Data Module contains the actual address and data manipulation portions of the Y180 including the ALU the register file and the various busses and special purpose registers BUSREQB CLEARB CLK CLKB DIN 7 0 INTB_ IOCB_ MIE_ NMIB_ RESETB_ WAITB_ A 15 0 _ _ COEB_ DOEB_ DOUT 7 0 E HALTB_ IORQB_ MIB_ MREQB_ RDB_ SLPB_ ST TRAPB_ IO CTRL Interface Module MACH ST Machine State Module CTR CTL DATA IO Central Control Module Address and Data Module Systemyde International Corporation Y180 02 96 Rev 1 0 Page 8 3 2 Register Description The figure below shows the registers contained in the Y180 that are visible to the programmer The main registers have both a primary and an alternate version The primary register set consists of A F B C D E H and L while the alternate register set co
42. and should not be modified 8 5 CTR CTL Central Control Module CTR CTL is the Central Control Module for the device This module is purely combinatorial and can be implemented as either random logic microcode or a combination of both The only inputs to this module are the page register the instruction register the machine cycle state and the clock cycle state 8 6 DATA IO Address and Data Module DATA IO is the Address and Data Module for the device This module contains the ALU Program Counter Instruction Register Page Register Flag Registers register file and temporary registers This is where all of the address and data manipulation is done in the Y180 This is the only module in the Y 180 other than the Top Level Module which contains other modules 8 7 REG BYTE Byte wide Register in the Register File REG BYTE is a byte wide register for use in the register file A unique register is used for the register file to allow it to be replaced with something other than flip flops if desired Note that the majority of registers in the register file are reset by the clearb signal which is derived from the CLEARB_ input If CLEARB_ is not used in your design these registers do not need to allow for reset The Stack Pointer I and R registers are reset by the resetb signal however Systemyde International Corporation Y180 02 96 Rev 1 0 Page 65 8 8 REG SBIT Byte wide General Purpose Register 8BIT is a byte wide gen
43. ation Y180 02 96 Rev 1 0 Page 71 Systemyde International Corporation Y180 02 96 Rev 1 0 Page 72
44. compatible with several industry standard processors 181 Instructions plus an undefined opcode trap Eight addressing modes 64K byte addressing capability 8 bit ALU with bit byte and BCD operations 8x8 multiply instruction Powerful vectored interrupt capability Static fully synchronous design Designed without 3 state busses Easily modified external interface Architectural upgrade path to 16 or 32 bits possible Full design documentation included Verilog simulation and test suite included Systemyde International Corporation Y180 02 96 Rev 1 0 Page 7 3 Functional Description The Y180 is a general purpose 8 bit microprocessor that is compatible with the Zilog Z80180 CPU The device contains an 8 bit ALU numerous 8 and 16 bit registers a 64K byte addressing range and a powerful vectored interrupt capability The device executes 181 instructions and performs an undefined opcode trap on all illegal instructions The Y180 is completely software compatible with several industry standard processors The Y180 is designed without using 3 state buses internally for maximum technology independence and is a static fully synchronous design Architectural upgrades to a wider ALU wider registers or a wider address bus are possible The Y 180 is supplied in the form of a synthesizable Verilog HDL model which is independent of technology clock speed within the limits of the chosen technology and vendor 3 1 Block Diagr
45. de International Corporation Y180 02 96 Rev 1 0 Page 61 NMIB RESETB SLPB TRAPB The Y180 requires that NMIB_ be Low for two consecutive rising edges of CLKB after being sampled High The latest that these two rising edges of CLKB can occur and still be accepted at the end of the current machine cycle is during the two clocks preceding the last clock cycle of a machine cycle This different than the timing for the Z80180 which catches the falling edge of NMI as late as one half clock before the last clock cycle of a machine cycle The Y180 timing is more robust acting as glitch filter on this edge sensitive input The Y180 requires that RESETB be Low for two consecutive rising edges of CLKB_ and responds on the next rising edge of CLK after it is sampled Low for the second time On exiting the Reset state the Y180 starts fetching the instruction at location 0000h one and one half clock cycles after sampling RESETB_ High This is different from the six clock cycle minimum Low time requirement and the two and one half clock cycle response time for the Z80180 The Y180 provides a separate SLPB_ output to indicate that the device is in the Sleep mode The Z80180 requires decoding of the state of several outputs to indicate that the device is in Sleep mode Note that the Y180 provides the same encoding on the outputs but using the SLPB output is easier The Y 180 provides a separate TRAPB output to indicate that the device has f
46. dition and the next state will be either IF1 for execution of another instruction or an interrupt acknowledge cycle if an interrupt condition is present Where there are two entries listed in a column for an instruction the next state depends on the condition being tested in the instruction The top entry corresponds to the condition being false while the bottom entry corresponds to the condition being true Shaded entries are not used for that particular instruction or exception condition The names and descriptions of the machine cycles are listed following the table Instruction if1 dly if2 of1 of2 if3 iop sif1 sdly sif2 rd1 rd2 siop wri wr2 fiop ADC A HL rd2 done ADC 1 if2 of1 iop2 rd2 done ADC A IY d if2 of1 iop2 rd2 done ADC of1 done ADCA r iop1 done ADC HL ss if2 iop4 done ADD A HL rd2 done ADD A IX d of1 iop2 rd2 done ADD A IY d if2 of1 iop2 rd2 done ADD of1 done ADD A r iop1 done ADD HL ss iop4 done ADD IX xx if2 iop4 done ADD IY yy if2 iop4 done AND HL rd2 done AND IX d if2 off iop2 rd2 done AND 1 9 if2 off iop2 rd2 done AND n done AND iop1 done BIT b HL if2 rd2 done BIT b IX d 2 ofi if3 rd2 done BIT b IY d if2 of1 if3 rd2 done BIT b r if2 done CALL f mn ofi i iop1 wrt wr2 done CALL mn ofi of2 iopl wrt wr2 done CCF done CP HL rd2 don
47. e IX d if2 ofi iop2 rd2 done CP IY d if2 of1 iop2 rd2 done CP n ofi done CPr iop1 done Systemyde International Corporation Y180 02 96 Rev 1 0 Page 29 Instruction if1 dly if2 of1 of2 if3 iop sif1 sdly sif2 rd1 rd2 siop wrt wr2 fiop CPD if2 rd2 siop3 done CPDR it2 siop3 done CPI if2 rd2 siop3 done CPIR it2 siop3 12 CPL done DAA iop1 done DEC HL rd2 siop1 wr2 done DEC IX d if2 iop2 rd2 siop1 wr2 done DEC IY d if2 of1 iop2 rd2 siop1 wr2 done DEC IX if2 iop1 done DEC IY if2 iop1 done DECr iop1 done DEC ss iop1 done DI done DJNZ j dy off xis done EI done EX SP HL rdi rd2 siop1 wr wr2 done EX SP IX if2 rdi rd2 siop1 wri wr2 done EX SP IY if2 rdi rd2 siop1 wri wr2 done EX AF AF iop1 done EX DE HL done EXX done HALT done IMO if2 done IM 1 if2 done IM2 if2 done IN A n rd2 done IN r C if2 rd2 done INO r n if2 rd2 done INC HL rd2 1 wr2 done INC if2 iop2 rd2 siop1 wr2 done INC IY d if2 2 2 1 wr2 done INC IX if2 iop1 done INC IY if2 iop1 done INC r iop1 done INC ss iop1 done IND if2 rd2 wr2 done INDR if2 wr ie done INI if2 rd2 wr2 done INIR if2
48. entifies the particular clock cycle within a machine cycle must not be modified This encoding was chosen very specifically to minimize the number of bits which change where the next state is conditional on some signal The register address encoding should not be modified unless the encoded register address generators in the Central Control Module are also modified because a portion of the address is taken directly from bits in the opcode in these address generators Obviously the definition of TRUE and FALSE should not be changed Systemyde International Corporation Y180 02 96 Rev 1 0 Page 64 8 3 IO CTRL I O Interface Module IO CTRL is the I O Interface Module for the device This module translates between the external pins and the internal busses and signals of the Y 180 This is the only module which uses CLKB and consists primarily of flip flops to translate timing This is where RESETB is translated into the internal signal resetb Because resetb goes to nearly every flip flop in the Y180 it will be heavily loaded This is the only signal besides the clock that will require special attention when implemented 8 4 M STATE Machine State Module M STATE is the Machine State Module for the device This module contains the machine cycle state machine the clock cycle state machine and the interrupt enable and mode flip flops As mentioned previously the clock cycle state machine was carefully designed to minimize state transitions
49. eral purpose register for use other than in the register file It is merely a grouping of eight flip flops that is used for convenience in the Verilog HDL description Systemyde International Corporation Y180 02 96 Rev 1 0 Page 66 9 Test Suite The Y180 Verilog HDL model includes a complete test suite to verify proper operation of the device both before and after implementation The test suite verifies the proper operation of every valid instruction trap on every illegal opcode proper operation with and without Wait states for every instruction proper operation with Bus Request before and after every possible machine cycle all interrupt modes and proper flag operation Running the test suite requires virtually no user intervention The test suite does not test every instruction in conjunction with interrupt and NMI but rather checks every group of instructions sharing a common interrupt or NMI Verilog description The test suite does not currently check for the proper timing of every input and output This was done manually during the development of the test suite and the model is believed correct as supplied If exhaustive input and output timing verification is desired the top level model can be modified to check this It is a relatively straightforward process to trace the inputs and output during simulation to generate vector files suitable for use with ATE testers Another alternative is to allow the synthesizer to insert scan test logic
50. etched an illegal opcode The two different cases of a Trap can be distinguished by the state of the RDB_ signal when TRAPB is Low The Z80180 provides a register outside of the CPU to hold the trap information This external register can be easily created and written via the TRAPB signal for compatibility Systemyde International Corporation Y180 02 96 Rev 1 0 Page 62 7 Future Enhancements The basic Z80 architecture has plenty of room for expansion having been created when transistor budgets were extremely limited The Y180 as a Verilog HDL model is quite simple to upgrade or change Some of the possible variants of the Y180 are described below One possible performance enhancement would be in the area of the ALU If it were widened to 16 bits for example the two clock cycle penalty for calculating the indexed address would be reduced to one clock cycle This would also allow the instruction set to be expanded to provide a full complement of 16 bit instructions Similarly dedicated multiply logic can be added to reduce the time required for the multiply instruction It currently uses a shift and add technique Another straightforward enhancement is an expansion of the address space beyond the current 64K byte limit This requires widening at least some of the registers and modifying such instructions as PUSH POP CALL and RETURN but this is a much cleaner solution than adding an MMU like the Z80180 does This is the first extension plan
51. he RETI instruction if the MIE signal is Low The MIB signal is always activated during interrupt acknowledge cycles 4 18 MIE Machine Cycle 1 Enable The Machine Cycle 1 Enable signal controls the operation of the MIB signal If the MIE signal is High the MIB signal will be activated for every instruction fetch If the MIE signal is Low the MIB signal will only be active during the refetch of the RETI instruction This signal has no effect on the operation of the MIB signal during interrupt acknowledge cycles where it is always active 4 19 MREQB Memory Request The Memory Request signal is active Low during memory cycles and also during non maskable interrupt acknowledge cycles 4 20 NMIB Non Maskable Interrupt Request When the Non Maskable Interrupt Request input is active Low for two successive rising edges of CLKB this information is latched and at the end of the current instruction the Y180 will perform a non maskable interrupt acknowledge cycle and jump to location 0066h for the NMI service routine The NMI service routine should be terminated with the RETN instruction for proper handling of the maskable interrupt If BUSREQB is active concurrently with the NMIB BUSREQB will be given priority Systemyde International Corporation Y180 02 96 Rev 1 0 Page 38 4 21 Read The Read signal is active Low during memory and I O read cycles and also during non maskable interrupt acknowledge cycles 4 22 RESETB
52. he timing of a Non Maskable interrupt acknowledge cycle is shown below The NMIB input is edge sensitive and cannot be masked by software NMIB must be sampled Low for two consecutive falling edges of CLK_ to be recognized by the processor The NMI acknowledge cycle looks exactly like an instruction fetch for the first three clock cycles except that the data bus is ignored These three clock cycles are followed by two internal operation cycles and two write cycles to push the contents of the program counter onto the stack Execution then begins at 0066h with an instruction fetch The NMI service routine must end with the RETN instruction to properly restore the state of the interrupt enable flag prior to the NMI A 15 0 DIN 7 0 Systemyde International Corporation Y180 02 96 Rev 1 0 Page 51 5 12 Mode 0 Interrupt Acknowledge The timing of a Mode 0 interrupt acknowledge cycle is shown below The Mode 0 interrupt acknowledge cycle fetches an instruction from the data bus but does not increment the PC because this instruction is not part of the program The data bus is sampled by the rising edge of CLK at the beginning of T3 just as in a normal instruction fetch cycle Any instruction can be used but the most convenient are the Restart RST instructions because they are only one byte and push the PC onto the stack The figure below shows an RST instruction being fetched during the acknowledge cycle Note that a Trap is possible if an
53. icant bit of the result of an arithmetic operation This is useful for implementing multiple precision arithmetic in software Systemyde International Corporation Y180 02 96 Rev 1 0 Page 10 3 4 Instruction Maps The following sections contain the opcode maps for the Y180 The most significant nibble is indexed vertically in the tables while the least significant nibble is indexed horizontally in the tables Shaded opcodes are invalid and attempted execution of these opcodes will result in a Trap In these maps d is an 8 bit signed displacement e is an 8 bit signed relative address n is an 8 bit constant and mn is a 16 bit constant 3 4 1 Main Code Page This table shows the main code page for the Y 180 These instructions are all one byte long unless they contain immediate data or addresses The four bytes marked as esc for escape are the first byte of multi byte instructions which are shown in subsequent tables LSB 0 1 2 3 4 5 6 7 8 9 A B D E F MSB 0 NOP LD LD INC INC DEC LD RLCA EX ADD LD DEC INC DEC LD RRCA BC mn BC A BC B B B n AF AF HL BC A BC BC C C C n 1 DJNZ LD LD INC INC DEC LD RLA JR ADD LD DEC INC DEC LD RRA e DE mn DE A DE D D D n e HL DE A DE DE E E E n 2 JR LD LD INC INC DEC LD DAA JR ADD LD DEC INC DEC LD CPL NZe HL mn mn HL HL H H H n Ze H
54. ired to match the timing characteristics of the Z80180 which changes outputs and samples inputs on both edges of the clock The Y180 provides a COENB output for control of external 3 state buffers on the control signals Y 180 control signals are always driven The Z80180 control signals are 3 state The Y180 employs separate data input and output busses DIN 7 0 and DOUT 7 0 and a Data Output Enable signal DOENB to control an external bidirectional bus if desired The DOUT bus changes only on the rising edge of CLK The Z80180 employs a bidirectional data bus and in the output mode the leading edge of the data changes on the falling edge of the clock The timing of the Y180 s DOENB signal is such that the timing of an external bidirectional bus if implemented will match that of the Z80180 The Y180 utilizes an IOCB input to control the timing of the RDB and IORQB outputs during I O operations In the Z80180 the timing of these two signals is controlled by a bit in a register external to the CPU This register can be created for complete compatibility and its output tied to the IOCB input of the Y180 The Y180 utilizes an MIE input to control the operation of the MIB _ signal for compatibility with the Z80180 In the Z80180 the operation of the M1 signal is controlled by a bit in a register external to the CPU This register can be created for complete compatibility and its output tied to the MIE input of the Y180 Systemy
55. is mode until either a RESETB_ INTB or NMIB occurs 4 14 INTB Interrupt Request When the Interrupt Request input is active Low at the end of the current instruction and neither BUSREQB_ or NMIB is active the Y180 will perform an interrupt acknowledge cycle and go to the interrupt service routine The particular interrupt acknowledge cycle depends on the interrupt mode of the Y 180 and the request will be ignored if interrupts are not enabled in the Y 180 4 15 IOCB I O Control Select The I O Control Select signal controls the timing of and RDB_ signals during an I O transaction If the IOCB signal is Low these two control signals go active Low during I O transactions on the rising edge of CLK If the IOCB signal is High these two control signals go active one half of a clock cycle earlier in the I O transaction on the rising edge of CLKB The trailing edge of these two control signals is not affected by the state of the signal Systemyde International Corporation Y180 02 96 Rev 1 0 Page 37 4 16 IORQB I O Request The I O Request signal is active Low during I O cycles and also during interrupt acknowledge cycles when the interrupt vector or instruction should be placed on the DIN 7 0 4 17 MIB Machine Cycle 1 The Machine Cycle 1 signal is active Low during instruction fetch cycles It will be active during all instruction fetch cycles if the MIE signal is High and only during the refetch of t
56. les The tables below show the operation of the Y 180 in detail for all instructions and exception conditions These tables are a part of the spreadsheet included in the full electronic documentation for the Y180 which contains things like ALU operations bus contents internal register addresses etc The tables below should be sufficient for the majority of users of the Y 180 but if you intend to modify the Y 180 for your application or merely want to understand the internal workings of the design refer to the full spreadsheet for more detailed information 3 5 1 Execution Table Conventions The conventions used in the instruction opcode and operation columns of the execution tables are as follows b bit select 000 bit 0 001 bit 1 010 bit 2 011 bit 3 100 bit 4 101 bit 5 110 bit 6 111 bit 7 cc condition code select 00 NZ 01 Z 10 NC 11 C d 8 bit signed displacement dd word register select 00 BC 01 DE 10 IX 11 SP e 8 bit signed displacement f condition code select 000 NZ 001 Z 010 NC 011 C 100 PO 101 PE 110 111 2 M m MSB of a 16 bit constant mn 16 bit constant n 8 bit constant or LSB of a 16 bit constant rr byte register select 000 B 001 010 D 011 E 100 H 101 L 111 A SS word register select 00 BC 01 DE 10 HL 11 SP V Restart address select 000 0000h 001 0008h 010 0010h 011 0018h 100 0020h 101 0028h
57. ned during internal operation cycles The default address output is the Program Counter so this is what will usually be on the Address Bus during internal operation cycles Instruction if1 dly if2 of1 of2 if3 iop sif1 sdly sif2 rd1 rd2 siop wr1 wr2 fiop ADC A HL PC HL ADC A IX d PC PC PC xx IX d ADC A IY d PC PC PC xx IY d ADC PC PG ADCA r PC xx ADC HL ss PC PC xx ADD A HL PC HL ADD A IX d PC PC PC xx IX d ADD A IY d PC PC PC xx IY d ADD PC PC ADD A r PC xx ADD HL ss PC xx ADD IX xx PC PC xx ADD IY yy PC PC xx AND HL PC HL AND IX d PC PC PC xx IX d AND IY d PC PC PC xx IY d ANDn PC PC ANDr PC xx BIT b HL PC PC HL BIT b IX d PC PC PC PC IX d BIT b IY d PC PC PC PC IY d BIT b r PC PC CALL f mn PC PC PC xx SP 1 SP 2 CALL mn PC PC PC xx SP 1 SP 2 CCF PC CP HL PG HL CP IX d PC PC PC xx IX d CP PC PC PC xx IY d CPn PC PC CPr PC xx CPD PG PC HL xx CPDR PC PC HL xx xx CPI PC PC HL xx CPIR PG PC HL xx xx CPL PC DAA PC xx DEC HL PC HL x HL DEC PC PC PC xx IX d xx IX d DEC IY d PC PC PC xx IY d xx IY d Systemyde International Corporation Y180 02 96 Rev 1 0 Page 24
58. ned for the Y180 Note that an MMU even your own design can still be easily added to the basic Y180 All of the registers in the Y180 can be widened to a full 32 bits In addition it is a simple modification to add more banks of registers or dedicated registers that interface to specialized logic to perform some application specific function such as a text search encryption decryption independent I O transfer and so on Of course it is a simple matter to modify the interface of the Y 180 to fit specific requirements of timing signal polarity and so on Even the automatic wait state inserted for I O access requires only a single line of Verilog HDL code to be changed The Y 180 is just the first in a series of designs Specific future versions are already planned but if you have a requirement please let us know Systemyde International Corporation Y180 02 96 Rev 1 0 Page 63 8 Model Organization The organization of the Y180 Verilog HDL model is identical to that shown in the block diagram of section 3 1 That is there is a Top Level Module which contains the four main modules of the device Each module is flat except for the Address and Data Module which uses two byte wide register modules Even though there are only three hierarchical levels in the overall model each module is structured into a number of self contained sections for easy modification Symbolic label definitions are used rather than hard encoding in almost all case
59. no adverse consequences 9 7 TRP_3RD Trap on Third Byte Operation TRP_3RD checks all of the three byte illegal opcodes Each three byte illegal opcode is individually checked for a trap and no adverse consequences 9 8 BIT_OPS Bit Manipulation Operation BIT_OPS checks all of the bit operations Each bit operation instruction is individually checked for both proper operation and proper flag results with no adverse consequences Systemyde International Corporation Y180 02 96 Rev 1 0 Page 68 9 9 JMP OPS Jump Operation JMP OPS checks all of the program flow instructions Each Jump or Call instruction is individually checked including the taken not taken case if it is a conditional instruction This is where Restart Return and DJNZ are checked 9 10 IO OPS I O Operation IO OPS checks all of the individual and block I O instructions The block move instructions are also checked here Both the looping and terminating case of the block instructions are checked Systemyde International Corporation Y180 02 96 Rev 1 0 Page 69 10 Installation The Y180 Verilog HDL Model was developed on a PC using Microsoft Works for Windows 2 0 for the spreadsheet Microsoft Publisher for the text and Veriwell for Windows 2 0 for the verification The model uses only synthesizeable constructs and contains nothing unique to the simulator used for the development The standard method of providing the Y180 Verilog HDL Model is as text files on a
60. nsists of A F B C D E and L At any given time only one bank is active and care must be used when switching between banks as there is no way for the programmer to check which bank is active The accumulator A is the destination for all 8 bit arithmetic and logic operations while the Flag register F contains the flag results of arithmetic and logic operations The other general purpose registers can be paired BC or DE or HL to form 16 bit registers There are two index registers IX and IY used for indexed addressing mode The I register holds the upper eight bits of the interrupt vector table address for use in Interrupt Mode 2 The R register is left over from the original Z80 architecture where it was used to hold a refresh address for DRAMs In the Y 180 it is just another general purpose register The Stack pointer SP holds the address of the stack and the Program Counter PC holds the address of the currently executing instruction Main Register Bank Alternate Register Bank Systemyde International Corporation Y180 02 96 Rev 1 0 Page 9 3 3 Flags Description The figure below shows the flags contained in the F register which report the results of instruction execution S Sign Z Zero U5 User s z us u vsr The Sign flag stores the most significant bit of the result This is used with signed arithmetic where the MSB is zero for positive numbers and one for negative numbers The Zer
61. o flag is set to one if the result of the operation is 0 This is a user defined flag It is difficult to use however because the only way to access it is to Push the AF register pair onto the stack and then Pop it back into some other register pair before testing the bit H Half Carry The Half Carry flag is used only by the DAA Decimal Adjust U3 User Accumulator instruction to properly adjust the result of an arithmetic operation on BCD numbers This is a user defined flag It is difficult to use however because the only way to access it is to Push the AF register pair onto the stack and then Pop it back into some other register pair before testing the bit P V Parity Overflow The Parity Overflow flag reports the parity of the result for logical N Negative C Carry operations with the flag set to one if the result has even parity and zero if the result has odd parity This bit reports the overflow status of arithmetic operations Overflow occurs when the two operands have the same sign but the sign of the result is different This means that the actual result cannot be represented in the eight or sixteen bits allocated for the result The Negative flag records the type of the last arithmetic operation add or subtract for use with the DAA instruction The bit is set to one for subtract operations and set to zero for add operations The Carry flag is set to one whenever there is a carry or borrow from the most signif
62. ock as it goes to the clock input of all internal flip flops A separate CLKB input is present on the Y180 to allow for compatibility with the Z180 timing on some inputs as well as some outputs But CLK_ is used exclusively for internal flip flops Care should be exercised when routing CLK_ to minimize skew and the buffer chosen must have sufficient drive for the load presented by all of these flip flops Timing analysis should always be performed after layout to verify proper operation 4 7 CLKB Clock Bar This is the master Clock Bar input It is used only in the IO CTRL module of the Y180 to provide compatible timing CLKB is the inverse of CLK and is only lightly loaded Only the rising edge of CLKB which corresponds to the falling edge of CLK is ever used The design of the CLK_ and CLKB buffers depends on the target technology for the Y 180 and cannot be overemphasized 4 8 COEB Control Output Enable The Control Output Enable signal can be used to control 3 state buffers on the various control signals external to the Y 180 This signal will be active Low when the Y180 should be driving these control signals and inactive High when the Y180 is releasing the bus for another bus master to drive these control signals Typically these control signals would consist of MREQB IORQB RDB and WRB 4 9 DIN 7 0 Data Input Bus The 8 bit Data Input Bus is used to communicate data into the Y180 DIN 7 0 is latched by the rising
63. ofi iop2 rd2 done LD r IY d if2 ofi iop2 rd2 done if2 done LD r n done LD iop1 done LD SP HL iop1 done LD SP IX if2 iop1 done LD SP IY if2 iop1 done LDD if2 rd2 wr2 done LDDR if2 wr 452 done LDI if2 rd2 wr2 done LDIR if2 wr2 done MLT ww if2 iop10 done NEG if2 done NOP done OR HL rd2 done OR IX d if2 ofi iop2 rd2 done OR IY d if2 ofi iop2 rd2 done ORn of1 done ORr iop1 done OTDM if2 iop rd2 wr2 iop1 done OTDMR if2 iop rd2 wr2 58 done OTDR it2 wr foe done OTIM if2 iop rd2 wr2 iop1 done OTIMR if iop rd2 wr2 done OTIR if2 rd2 wr2 fone done OUT C r if2 iop wr2 done OUT n A ofi iop1 wr2 done OUTO if2 ofi iop1 wr2 done Systemyde International Corporation Y180 02 96 Rev 1 0 Page 31 Instruction if1 dly if2 of1 of2 if3 iop sif1 sdly sif2 rd1 rd2 siop wrt wr2 fiop OUTD if2 rd2 wr2 done OUTI if2 rd2 wr2 done POP IX if2 rdi rd2 done POP IY if2 rd1 rd2 done POP zz rdi rd2 done PUSH IX if2 iop2 wrt wr2 done PUSH IY if2 iop2 wrt wr2 done PUSH zz iop2 wri wr2 done RES b HL if2 rd2 1 wr2 done RES b IX d of1 if3 rd2 1 wr2 done RES b IY d of1 if3 rd2 1 wr2 done RES b r if2 iop1 done RET rdi rd2 done RET f ie gore rd2 done RETI
64. on cycles and can be up to 5 clocks wrl and wr2 fiop are memory or I O write cycles wr2 is used for byte writes and both wrl and wr2 are used for word writes are internal operation cycles and can be up to 3 clocks long Systemyde International Corporation Y180 02 96 Rev 1 0 Page 33 4 Pin Descriptions This section describes the pins of the Y180 model All input pins are sampled by CLK CLKB or both All output pins come from flip flops although if a pin changes on both edges of CLK the pin will be a simple combination of two flip flop outputs The table below shows pin names direction function and sampling or changing CLK edge Pin name Direction Function Sampled on Systemyde International Corporation Y180 02 96 Rev 1 0 Page 34 4 1 A 15 0 Address Bus The 16 bit Address Bus is used to address memory and I O The address on this bus will be valid throughout a memory or I O cycle but the contents are undefined during internal operation cycles The default address output is the Program Counter so this is what will usually be on the 15 0 during internal operation cycles 4 2 AOEB Address Output Enable The Address Output Enable signal can be used to control 3 state buffers on the address bus external to the Y 180 This signal will be active Low when the Y 180 should be driving the address bus and inactive High when the Y180 is releasing the bus for another bus master to drive the address bus 4 3
65. read write or interrupt acknowledge cycle the cycle is extended for the duration of the WAITB_ Low time one clock cycle at a time The cycle then finishes when the WAITB signal returns High This allows slow memory or peripheral device time to respond to bus cycles 4 27 WRB_ Write The Write signal is active Low during memory and I O write cycles Systemyde International Corporation Y180 02 96 Rev 1 0 Page 40 5 Bus Cycles The figures below show the various bus cycles for the Y180 Throughout the figures only the relevant pins are shown 5 1 Instruction Fetch without Wait state The timing for an instruction fetch cycle is shown below This bus cycle is three clock cycles long with the WAITB input sampled at the falling edge of CLK_ in T2 and the DIN bus sampled at the rising edge of CLK in The ST signal is Low only for the fetch of the first byte of an instruction and the MIB signal is asserted Low during instruction fetch cycles only if the MIE input is High xw _ CLKB DIN 7 0 MIB MREQB RDB WAITB ST Systemyde International Corporation Y180 02 96 Rev 1 0 Page 41 5 2 Instruction Fetch with Wait state The timing for an instruction fetch cycle with one Wait state is shown below This bus cycle is now four clock cycles long with the WAITB_ input sampled at the falling edge of CLK in both T2 and TW and the DIN bus sampled at the ri
66. s in the design Those cases where the hard encoding is used are listed below In all cases where hard encoding is not used the symbolic label definitions can be changed to provide unencoded signals or just different encodings When modifying symbolic label definitions only the include file that contains all of the parameter definitions needs to be modified 8 1 Y180 TOP Top Level Module Y180 TOP is the Top Level Module for the device It contains only the pins and the four main modules of the Y180 Note that no symbolic labels are used at this level and all of the pins of the device use capital letters followed by an underscore 8 2 PARAMS Parameter Definition include File PARAMS is the parameter definition include file for the device It contains all of the symbolic label definitions used in the design and is called with an include in each of the four main modules of the device If you want to modify the symbolic label definitions only this file needs to be modified As mentioned previously some of the encodings must not be modified These are described below and are clearly marked with warning comments in this file The page register encoding which identifies which code page the instruction is on must not be modified as it seldom treated symbolically The encoding for the page register has been carefully chosen to simplify the decoding of groups of similar instructions on different pages The clock cycle encoding which id
67. s are held in the I register in the processor Note that the vector must be an even number That is the least significant bit of the vector must be a Zero A 15 0 DIN 7 0 Systemyde International Corporation Y180 02 96 Rev 1 0 Page 54 5 15 Return From Interrupt RETI The timing of the RETI instruction sequence is shown below The Y180 refetches the two byte opcode of the RETI to allow peripheral controllers to recognize the RETI instruction Proper operation of those peripheral controllers that recognize the RETI instruction requires that the MIE input be Low so that only one RETI is recognized 15 0 DIN 7 0 MIE 1 MIB MIE 0 MREQB RDB ST Systemyde International Corporation Y180 02 96 Rev 1 0 Page 55 5 16 Halt Entry and Exit The Halt mode is entered when the HALT instruction is executed as shown below In the Halt mode the processor continuously performs Halt cycles which are three clock cycle bus cycles identical to instruction fetch cycles except that the HALTB_ output is Low In the Halt mode Bus release through BUSREQB_ and BUSACKB can still occur but the only way to exit the Halt mode is with either an interrupt NMIB or INTB or via reset The timing for exiting the Halt mode via INTB_ is shown below Note that INTB_ can only be used to exit the Halt mode interrupts are enabled when the HALT instruction is executed If the Halt mode is exited via NM
68. sing edge of T3 All of the control signals are stretched by the insertion of the Wait state m mw DIN 7 0 MIB MREQB_ RDB WAITB_ ST_ Systemyde International Corporation Y180 02 96 Rev 1 0 Page 42 5 3 Memory Read Write without Wait State The timing for a memory read or memory write cycle is shown below These bus cycles are three clock cycles long with the WAITB input sampled at the falling edge of CLK in T2 In the case of memory read the DIN bus sampled at the falling edge of CLK in T3 and the RDB signal is activated In the case of memory write the DOUT_ bus is driven with valid data for the duration of a memory write cycle and the WRB and DOEB signals are activated The DOEB_ signal can be used to control buffer direction if a 3 state bus is used externally to the model _ CLKB DIN 7 0 MREQB RDB_ WRB_ WAITB_ DOEB_ Systemyde International Corporation Y180 02 96 Rev 1 0 Page 43 5 4 Memory Read Write with Wait State The timing for a memory read or memory write cycle with one Wait state is shown below These bus cycles are now four clock cycles long with the WAITB_ input sampled at the falling edge of CLK_ in both T2 and TW All of the control signals are stretched by the insertion of the Wait state T1 T2 TW 3 CLK_ ee ie ERR MREQB_ RDB_ WRB_ WAITB_
69. single 3 5 HD disk since this will be compatible with the majority of destinations The file structure of this disk is shown below The design spreadsheet will be provided in Microsoft Works for Windows 2 0 format files zipped on a 3 5 HD disk Should the documentation this manual be required in machine readable format other than the default Acrobat Portable Document Format pdf it will be provided in Microsoft Publisher format zipped on a 3 5 HD disk Systemyde International Corporation Y180 02 96 Rev 1 0 Page 70 10 1 File structure design ctr_ctl v data io v io ctrl v Asas ends m state v params v uie reg 8bit v M reg byte v PEE top lev v y180 top v memory alu_ops vm benenys alu opsd vm Mcd bit ops vm bit opsd vm pM dat mov vm M dat movd vm Betas a int ops vm MN int opsd vm FEDERER io ops vm tas io opsd vm PUES jmp ops vm jmp opsd vm setup hl vm trp 2nd vm PEE trp 2ndd vm DNE trp_3rd vm nto trp 3rdd vm testing alu_ops s A alu opsd s bit ops s siens ns bit opsd s TEE dat mov s stele dat movd s m int_ops s ORI as int_opsd s 10 ODps s jmp ops s xat a Jmp_opsd s Qui essi setup hl s Pie 2nd s NEC E EM trp_2ndd s Systemyde International Corpor
70. t would be an infinite loop at location OCOh This loop is detected by a test in TOP LEV and used to load the next pattern Any patterns that you add to the test suite should attempt to follow this convention Systemyde International Corporation Y180 02 96 Rev 1 0 Page 67 9 3 INT OPS Interrupt Operation INT OPS checks all of the interrupt modes and NMI for all of the possible cases This pattern is also used to check that the two input options Enable and I O Control are functioning correctly Sleep mode and Halt mode are also checked in this pattern 9 4 ALU OPS ALU Operation ALU OPS checks all of the data manipulation instructions and flag results Every data manipulation instruction is individually checked usually more than once to ensure both proper operation and flag results Both byte and 16 bit instructions are checked in this pattern 9 5 DAT Data Movement Operation DAT MOV checks all of the data movement instructions both internal and external Every data movement instruction is individually checked usually more than once to ensure both proper operation and no adverse consequences improper decoding for example Both byte and 16 bit instructions are checked in this pattern but the block move instructions are checked in a separate pattern 9 6 TRP_2ND Trap on Second Byte Operation TRP_2ND checks all of the two byte illegal opcodes Each two byte illegal opcode is individually checked for a trap and
71. tate clears all of the state machines internal to the Y 180 It also resets the PC SP I and R registers selects Interrupt Mode 0 and disables the maskable interrupts If CLEARB is asserted Low coincident with RESETB all of the other registers in the Y180 are reset also RESETB should always be asserted on power up and may be used to exit from the Halt mode or Sleep mode also A 15 0 Address AOEB _ _ DOEB_ HALTB_ SLPB_ RESETB_ CLEARB_ Reset state xk Instruction fetch at location 0000h Systemyde International Corporation Y180 02 96 Rev 1 0 Page 60 6 Differences This section describes the differences between the Y 180 and 780180 of the differences are related to input or output timing or operation All instruction results and clock cycle timing are identical between the two devices AOENB _ CLEARB _ CLK_ COENB _ DOENB IOCB _ MIE The Y180 provides an AOENB output for control of an external 3 state Address bus The Y180 Address Bus A 15 0 is always driven The 780180 address bus is 3 state The Y180 provides a CLEARB input to initialize all of the register file This input can be quite useful for simulation but is not strictly necessary for the final design and can be tied High with no ill effect The Z80180 has no such reset mechanism The Y180 requires both CLK_ and CLKB although the CLKB input is used only in the I O interface module CLKB_ is requ
72. temyde International Corporation Y180 02 96 Rev 1 0 Page 12 3 4 3 DD Code Page This table shows the code page for instructions whose first byte is DDh AII instructions on this code page imply the use of the IX register in one way or another Note that wherever the HL register is used in a main code page instruction the corresponding instruction on this code page uses either the IX register or the indexed addressing mode using the IX register LSB 0 1 2 3 4 5 6 7 8 9 A B D E MSB 0 ADD IX BC 1 ADD IX DE 2 LD LD INC ADD LD DEC IX mn mn IX IX IX IX IX mn IX 3 INC DEC LD ADD IX d IX d IX d n 5 4 LD LD B IX d C IX d 5 LD LD D IX d E IX d 6 LD LD H IX d L IX d 7 LD LD LD LD LD LD LD LD IX d B IX d C IX d D IX d E 1 IX d L IX d A A IX d 8 ADD ADC A IX d A IX d 9 SUB SBC IX d A IX d A AND XOR IX d IX d B OR CP IX d IX d esc D E POP EX PUSH JP IX IX IX F LD SP IX Systemyde International Corporation Y180 02 96 Rev 1 0 Page 13 3 4 4 FD Code Page This table shows the code page for instructions whose first byte is FDh AII instructions on this code page imply the use of the IY register in one way or another This code page is identical to the DD code page with the IY register substituted for the IX
73. very facet of the internal operation of the processor This provides knowledgable users the opportunity to customize the design for unique application requirements The Y180 is a powerful medium performance processor that executes 181 instructions and includes an undefined opcode trap for illegal opcodes The device contains a full complement of 8 bit arithmetic and logical instructions and enough 16 bit instructions to properly handle the 16 bit address range Included are bit manipulation instructions as well as an 8x8 multiply instruction The device allows for other bus masters and includes a powerful vectored interrupt capability The Y 180 can be easily integrated with RAM ROM or other application specific logic to create a single chip product The technology independent nature of the design provides the full spectrum of design alternatives relative to cost power consumption and speed Although currently limited to 8 bit data and 16 bit addresses the architecture of the Y180 can be upgraded to 16 bit data and 32 bit addresses with relative ease The Y180 is written in Verilog HDL and can be synthesized using any Verilog compatible logic synthesizer The Y180 package includes full design documentation including a Verilog simulation and test suite Systemyde International Corporation Y180 02 96 Rev 1 0 Page 6 2 Features Fully functional synthesizable Verilog HDL model of the Z80180 CPU Vendor and technology independent Software
74. write cycles to push the PC of the undefined opcode to the stack The processor then jumps to location 0000h and starts fetching instructions The TRAPB information should be latched outside the CPU to distinguish this case from the normal reset case The second byte opcode trap can be distinguished from the third byte opcode trap by the timing of the TRAPB signal The start of the illegal instruction in this case is the stacked PC value minus one A 15 0 DIN 7 0 Systemyde International Corporation Y180 02 96 Rev 1 0 Page 49 5 10 Trap third opcode byte The timing of an undefined third byte opcode trap is shown below The fetch of the undefined opcode is followed by the normal Read cycle all three byte instructions use indexed addressing with an embedded Trap cycle four internal operation cycles and two normal write cycles to push the PC of the undefined opcode to the stack The processor then jumps to location 0000h and starts fetching instructions The TRAPB information should be latched outside the CPU to distinguish this case from the normal reset case The third byte opcode trap can be distinguished from the second byte opcode trap by the timing of the TRAPB signal The start of the illegal instruction in this case is the stacked PC value minus two A 15 0 DIN 7 0 DOUT 7 0 MIB MREQB_ Systemyde International Corporation Y180 02 96 Rev 1 0 Page 50 5 11 Non Maskable Interrupt Acknowledge T

8-bit Microprocessor Synthesizable Verilog HDL Model User Manual

Contents

Download Pdf Manuals

Related Search

Related Contents