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LC872600 SERIES USER`S MANUAL

1. 1 6 1 4 System Block Diagram 1 7 1 5 Pin Description 1 8 1 6 Port Output Types 1 9 1 7 Recommended Unused Pin Connections 1 9 1 8 User Options 1 9 Chapter 2 Internal Configuration mE EBENEN 2 1 2 1 Memory Space 2 1 22 Counter PC
2. 3 43 3 7 3 Circuit Configuration eee eee eee eee eee eee eee eee eee ee eee ere eee eee eee eee 3 44 3 7 4 Related Registers eee eee eee eee eee eee etree ee eee eee eee eee eee eee eee eee 3 46 3 8 High speed Pulse Width Period Measurement Counter 2 HCT2 e 3 48 3 8 1 Overview 3 48 3 8 2 Functions rere rrr irre 3 48 3 8 3 Circuit Configuration See eee eee eee eee eee eee eee eee eee eee ere eee eee eee eee eee 3 49 Contents 3 8 4 Related Registers mme 3 53 3 9 AD Converter ADC12 mmm 3 57 3 9 1 C 3 57 3 57 3 9 3 Circuit Configuration mmm 3 58 3 9 4 Related Registers mmm eee 3 58 3 9 5 AD Conversion Example mmm 3 62 39 6 Hints on the Use of the ADC HH nnn nnn 3 63 3 10 Analog Comparator ACMP emen 3 65 ROSEO EL 3 65 3 10 2 3 65 3 10 3 Circuit Configuration mmm 3 65 3 10 4 Related Registers mmm 3 66 Chapter 4 Control Functions eere 4 1 41 Interrupt Function mme 4 1 4 1 1 4 1 41 2 PFunctiOns rrr rrr rrr rrr 4 1 4 1 3 Circuit Configuration mme 4 2 4 1 4 Related Registers mmm 4 3 4 2 System Clock Generator Function mmm 4 5
3. 2 5 2 11 Addressing Modes 2 6 2 1 1 Immediate Addressing 2 6 2 11 2 Indirect Register Indirect Addressing Rn 88 2 7 2 11 3 Indirect Register C Register Indirect Addressing Rn C 2 7 2 11 4 Indirect Register RO Offset Value indirect Addressing off 2 8 2 11 5 Direct Addressing dst mmm HH 2 8 2 11 6 ROM Table Look up Addressing 2 9 2 11 7 External Data Memory Addressing HH HH 2 9 Chapter 3 Peripheral System Configuration CPP CCP E ER DATE 3 1 3 1 Port 1 3 1 3 1 Overview 3 1 3 1 2 Functions 3 1 3 1 3 Related Registers
4. 3 29 3 5 3 Circuit Configuration eee eee eee eee eee eee eee eee eee eee eee eee eee 3 29 3 5 4 Related Registers eee eee eee ee eee eee eee eee eee ee eee eee ee eee ee eee eee eee eee 3 31 3 5 5 SIO7 Transmission Examples 3 32 3 5 6 307 HALT Mode Operation eee etree ite 3 33 3 6 High speed 12 bit PWM HPWM 3 34 3 6 1 Overview Pere etre rere rrr errr errr rrr rrr rrr errr errr irre errr reir 3 34 3 6 2 Functions II reer errr errr r rrr errr retire r errr rrr rrr irre errr 3 34 3 6 3 Circuit Configuration eee eee eee eee eee eee eee eee eee eee eee eee eee 3 35 3 6 4 Related Registers Peete terete terre rere errr errr reer terre rrr r ire 3 39 3 7 High speed Pulse Width Period Measurement Counter 1 1 3 43 3 7 1 Overview 3 43 3 7 2 Functions
5. 2 1 2 3 Memory ROM 2 2 24 Internal Data Memory RAM 2 2 2 5 Accumulator A Register ACC A 2 3 2 6 Register B 2 3 27 Register C 2 4 2 8 Status Word PSW 2 4 2 9 Stack Pointer SP 2 5 2 10 Indirect Addressing Registers
6. Edge detector circuit 2 Counter operation control Trigger shift counter TRGSFTCT Read HCT22HR bits 3 0 HCT22MR HCT22LR Capture trigger Set TRGSFT2 0 to nonzero value TRGSFT2 0 Pm gt HCT2PR HC2CKSL E HC2PRSL1 0 V Measurement Ik Capture register HCT21HR HCT21MR f HCT21LR HCT2CT HCT20V High speed RC oscillation clock System clock Operation start detector circuit Write HCT2ST 1 Figure 3 8 1 High speed Pulse Width Period Measurement Counter 2 Block Diagram 3 51 HCT2 L level width period measurement HCT2 input trigger L level width measurement Period measurement A A A A A Start HCT2 operation Measurement start Measurement start condition L level width Period measurement end HCT2ST 1 condition 1 detected 2 detected measurement end condition detected Clear HCT2CT to 0 H level detected falling edge detected condition detected falling edge detected HCT2CT counting start rising edge detected Stop HCT2CT counting HCT2CT HCT21xR Set HCT2END flag count value captured Clear HCT2ST to 0 The width of the H level signal to be input needs to be not narrower than that of the noise filter output HCT2PR output clock width x 6 for the measurement start condition 1 H level to be detected Figure 3 8 2 Sample High speed Pulse Width Period Mea
7. vobi 9 P32 INTC CMPO DBGP1 1 3 8 P33 INTD HPWM DBGP12 4 7 P41 S17 SB7 INTE IN HCT2IN AN1 5 P12 SCK7 INTF IN AN2 S SANYO MFP10S Lead Halogen free type 5 CHU 1411 VDD1 2 13 P32 INTC CMPO DBGP11 3 12 P33 INTD HPWM DBGP12 IL 4 P11 SI7 SB7 INTE IN HCT2IN AN1 5 10 P12 SCK7 INTF IN AN2 6 9 20 8 DBGP21 S J SANYO MFP14S for debugging only Lead free type 1 6 1 4 System Block Diagram LC872600 Chapter 1 Interrupt control 4 gt IR PLA Standby control gt Flash ROM A Hi speed Freq divider pe gt Medium Bees speed RES WDT Reset ACC Low speed RC control Reset circuit LVD POR gt B register o aL Jl S C register F 7 0 5107 Bus interface gt y Port 1 ALU INTE to INTF Ti Port 3 INTA to INTD 2 6 PSW _ Hi speed PWM ADC HCT1 HCT2 gt Analog comparator Stack pointer 1 7 On chip debugger 1 5 Pin Description Name Description VSSI power supply VDDI PER power supply Port 1 IO 3 bit I O port I O specifiable in 1 bit units
8. 3 1 3 3 3 2 Functions eer rete rere errr errr errr rire rere r errr 3 1 3 3 3 3 Circuit configuration ee eee eee eee eee eee etree eee eee eee eee eet eee eee eee 3 15 3 3 4 Related Registers eee eee eee eee eee eee eee eee eee eee eee eee eee eee eee eee eee 3 19 3 4 Timer Counter 1 T1 eee Eee eee eee eee eee eee treet eee eee ee eee eee eee eet eee eee 3 22 3 4 1 Overview 3 22 3 4 2 Functions rere errr errr errr rire 3 22 3 4 3 Configuration eee eee eee eee eee eee eee eee eee eee eee ere eee eee eee eee eee 3 23 3 4 4 Related Registers 3 26 35 Serial Interface 7 SIO7 3 29 3 5 1 Overview II rer reer rrr reer trier irre 3 29 3 5 2 Functions
9. 3 2 3 1 4 Options 3 6 3 1 5 HALT and HOLD Mode Operation 3 6 Contents 3 2 Port 3 3 7 3 2 1 Overview ee rere errr rire r errr rir r rrr rrr rire 3 7 3 2 2 Functions 3 7 3 2 3 Related Registers eee eee eet eee eee 3 9 3 2 4 Options 3 1 2 3 2 5 HALT and HOLD Mode Operation 3 12 3 3 Timer Counter 0 TO ePPPP A 3 13 3 3 1 Overview
10. 2 OFFOIH lies outside the basic area In this case since SFR is confined in an 8 bit address space the part of the address data addressing outside the 8 bit address space is ignored and the contents of register are placed in the ACC as the result of the computation OFFO1H amp OFFH OFEO1H 2 7 2 11 4 Indirect Register RO Offset Value indirect Addressing off In this addressing mode the results of adding the 7 bit signed offset data off 64 to 63 to the contents of the indirect register RO designate an address in RAM or SFR If RO contains 2 and off has a value of 7EH 2 for example the A register FE02H 2 is designated Examples When contains 123H RAM address 0 23H RAM address 1 01H LD 10H Transfers the contents of RAM address 133H to the accumulator Li STW 10H Transfers the contents of the BA register pair to RAM address 133H PUSH 10H Saves the contents of RAM address 133H in the stack SUB Subtracts the contents of RAM address 133H from the accumulator 10H DBZ L1 Decrements the contents of RAM address 133H by 1 and causes a branch if Zero Notes on this addressing mode The internal data memory space is divided into three closed functional areas as explained in Section 2 1 namely 1 system reserved area FF00H to FFFFH 2 SFR area FEOOH to FEFFH and 3 RAM stack area 0000H to FDFFH Consequently i
11. Figure 4 5 2 Reset Circuit Configuration Using only the internal POR Function 2 When temporary power interruption or voltage fluctuations shorter than several hundreds us are anticipated The response time measured from the time the LVD senses a power voltage drop at the option selected level till it generates a reset signal is defined as the minimum low voltage detection width tLVDW shown in Figure 4 5 3 For details refer to the latest SANYO Semiconductor Data Sheet If temporary power interruption or power voltage fluctuations shorter than this minimum low voltage detection width are anticipated be sure to take preventive measures shown in Figure 4 5 4 or other necessary measures LVD release voltage N LVD reset voltage A LVDET LVDET 0 5V Figure 4 5 3 Example of Power Interruption or Voltage Fluctuation Waveform 4 19 Internal reset Microcontroller VDD1 1 Figure 4 5 4 Example of Power Interruption Voltage Fluctuation Countermeasures 4 5 7 Figure 4 5 5 Sample Reset Circuit Configuration Using an N channel Open Drain Type Reset IC Notes to be Taken When Not Using the Internal Reset Circuit When configuring the external reset IC without using the internal reset circuit The POR function is activated and the capacitor discharging N channel transistor connected to the RESET pin turns on when power is turned on even if the internal reset circuit is not used For this reason wh
12. 1 PWMXHR bits 3 to 0 and and the PWM1BR have the same value See note 4 in Subsection 3 6 3 5 HPWM DUTY period high byte register for details on the update procedure for the buffer registers when PWMST is set to 1 HPWM period buffer register PWM2BR 12 bit buffer register The PWM2BR is a buffer register for storing the period match data that matches the value of the HPWCT It stores the 12 bit data from PNMXHR bits 7 to 4 and PWM2LR The data in this buffer register is updated as follows If PWMST 0 or PWMST 1 and PWMCTOV 1 and PWMDSL 1 PWMXHR bits 7 to 4 and PWM2LR and the PWM2BR have the same value See note 4 in Subsection 3 6 3 5 HPWM DUTY period high byte register for details on the update procedure for the buffer registers when PWMST is set to 1 HPWM prescaler HPWPR 12 bit counter Operation start stop PWMST I PWMST 0 Enabled in modes other than HOLD Count clock PWCK Match signal A match signal is generated when the HPWPR count value matches the decoded value of the PWMPBR data Resetting PWMST 0 match signal generated or PWMST 1 and PWMCTOV 1 and PWMDSL 1 HPWM DUTY period counter HPWCT 12 bit counter Operation start stop PWMST I PWMST 0 Enabled in modes other than HOLD Count clock HPWPR match signal DUTY match signal A match signal is generated when the HPWCT count value matches the PWM IBR value A set signal to HPWOLT is
13. HPWM period Period defined by PWMCKR Period register value 1 Continuous PWM output mode The operation described in 1 above is repeated PWM set value output automatic stop mode The 11 bit up counter HPWSTCT runs in synchronization with the PWMOV set signal which described in operation 1 above is used as a clock When the value of the HPWSTCT matches the value of the period count register PWMCTHR bits 2 to 0 and PWMCTLR the period count match flag PWMCTOV is set and the HPWM stops operation Period up to automatic stop HPWM period x bits 2 to 0 and PWMCTLR 1 11 bits Interrupt generation An interrupt request to vector address 0043H is generated if an interrupt request is generated by the HPWM while the corresponding interrupt request enable bit is set 3 34 LC872600 Chapter 3 5 control the high speed 12 bit PWM HPWM it is necessary to manipulate the following special function registers PWMCNT PWMCKR PWMILR PWM2LR PWMXHR PWMCTLR PWMCTHR PSDDR Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FEAO 0000 0000 R W PWMCNT PWMST PWMOE PWMINV RLDBSY PWMCTIE PWMOV PWMIE reat wwmwon pwnicros 3 6 3 Circuit Configuration 3 6 3
14. Pull up resistors can be turned on and off in 1 bit units Multiplexed pin functions P10 SIO7 data output INTE input HOLD release input timer 1 event input timer OL capture input timer OH capture input P11 SIO7 data input bus I O high speed pulse width period measurement counter 2 input INTE input HOLD release input timer event input timer OL capture input timer OH capture input P12 5107 clock I O INTF input HOLD release input timer event input timer OL capture input timer OH capture input AD converter input ports ANO to AN2 Analog comparator input port IN IN On chip debugger pin 1 DBGP02 Interrupt acknowledge type Falling amp Falling INTE X x INTF x x 4 bit I O port I O specifiable in 1 bit units BA DEOS Pull up resistors can be turned on and off in 1 bit units Multiplexed pin functions P30 INTA input HOLD release input timer OL capture input high speed pulse width period measurement counter 1 input P31 INTB input HOLD release input timer OH capture input high speed pulse width period measurement counter 2 input P32 INTC input HOLD release input timer 0 event input timer OL capture input analog comparator output P33 INTD input HOLD release input timer 0 event input timer OH capture input high speed PWM output On chip debugger pin 1 DBGPXO to DBGPOI On chip debugger pin 2 DBGPX0 to DBGP12 Interrupt acknowledge type Rising Rising Falling amp H level L level Falling x
15. WDT reset detection flag This bit is cleared when a reset is effected by applying a low level to the external RES pin or using the internal reset POR LVD function This bit is set when a WDT triggered reset occurs This flag can be rewritten with an instruction FIXO bit 6 Test bit This bit is available for testing purposes and must always be set to 0 4 24 LC872600 Chapter 4 WDTRUN bit 5 WDT operation control Setting this bit to 0 stops the WDT operation Setting this bit to 1 starts the WDT operation IDLOP 1 bit 4 WDT standby mode operation selection IDLOPO bit 3 WDT Standby Mode Operation IDLOP1 IDLOPO 0 0 Continue operation 3 See Figure 4 6 2 for details of the operating modes There are notes to be taken when running by specifying Hold operation See Subsection 4 6 5 Notes on the Use of the Watchdog Timer WDTSL2 bit 2 WDTSL1 bit 1 WDT counter WDTCT control WDTSLO bit 0 WDTSL2 WDTSL1 WDTSLO WDT Counter Count Value 17 06 ms 0 0 0 o a oa pow a o9 oa Time values enclosed in parentheses refer to the time for WDTCT overflow to occur when low speed RC oscillation frequency is 30 kHz typical The low speed RC oscillation frequency varies from IC to IC For details refer to the latest SANYO Semicon
16. CLKDV1 bits 7 to 3 These bits do not exist 1 is always read when these bits are read CLKDV2 bit 2 CLKDV1 bit 1 Define the division ratio of the system clock CLKDVO bit 0 CLKDV2 CLKDV1 CLKDVO Division Ratio 0 0 0 0 0 1 1 0 1 0 1 0 1 1 i 1 0 0 x 1 0 1 E 1 1 0 er 1 1 1 i 4 9 Standby 4 3 Standby Function 4 3 1 Overview This series of microcontroller supports two standby modes called the HALT and HOLD modes which are used when power failed or to reduce current consumption in program standby mode In a standby mode the execution of all instructions is suspended 4 3 2 Fun ctions 1 HALT mode The microcontroller suspends the execution of instructions but its peripheral circuits continue processing The HALT mode is entered by setting bit 0 of the PCON register to 1 Bit 0 of the PCON register is cleared and the microcontroller returns to the normal operating mode when a reset occurs or an interrupt request is accepted 2 HOLD mode Note All oscillators are suspended The microcontroller suspends the execution of instructions and its peripheral circuits stop processing The HOLD mode is entered by setting bit 1 of the PCON register to 1 In this case bit 0 of the PCON register HALT mode flag is automatically set When a reset occurs or a HOLD mode release signal INTA INTB INTC INTD INTE or INTF occurs bit 1 of
17. HCT2 Medium speed RC clock 10 5 1 2 RCSTOP Medium speed RC oscillator fSCLK System clock frequency fCYC Cycle clock frequency minimum instruction cycle fCYC fSCLK 3 Figure 4 2 1 System Clock Generator Block Diagram 4 2 4 Related Registers 4 2 41 Power Control Register PCON 2 bit register 1 The power control register is a 2 bit register used to specify the operating mode normal HALT HOLD See Section 4 3 Standby Function for the procedures to enter and exit the microcontroller operating modes rey PCON pn bits 7to 2 These bits do not exist They are always read as 1 PDN bit 1 HOLD mode setting flag Operating mode 0 Normal or HALT mode 1 These bits must be set with an instruction When the microcontroller enters the HOLD mode all oscillations high speed RC oscillator medium speed RC oscillator are stopped and bits 1 4 and 5 of the OCR register are set to 0 When the microcontroller returns from the HOLD mode medium speed RC oscillator resumes oscillation and high speed RC oscillator restores the state that is established before the HOLD mode is entered and the medium speed RC oscillator is designated as the system clock source 2 PDNiscleared when a HOLD mode resetting signal INTA INTB INTC INTD INTE or INTF is generated or a reset occurs 3 IDLE b
18. High speed Pulse Width Period Measurement Counter 2 for the description of this bit INTCINSL bit 6 INTC input signal select INTCINSL INTC External Interrupt Circuit Input Signal 0 P32 INTC Analog comparator output FIXO bit 5 Test bit This bit is used only for testing and must always be set to 0 P320TSL1 bit 4 P320TSLO bit 1 P32O0TSL1 P320TSLO P32 CMPO multiplexed pin output select P32 CMPO Output Signal 0 0 Multiplexing disabled EF GM EC Analog comparator output signal Low INTC noise filtered output signal 3 66 LC872600 Chapter 3 When P32OTSL1 0 0 0 the output of the selector designated by these bits is fixed at a low level see Figure 3 10 1 for details control the P32 CMPO multiplexed pin output it is also necessary to configure 2 IADSL bit 3 P32 P3 bit 2 and P32DDR P3DDR bit 2 see Figure 3 10 1 for details If P32DDR is set to 1 P32 output mode do not set INTCINSL to 0 and P32OTSL1 0 to 1 0 at the same time CMPON bit 3 ACMP operation control Setting this bit to 0 stops the ACMP operation Setting this bit to 1 starts the ACMP operation ACMP also runs in standby modes HALT and HOLD modes Note that several hundreds pA of operating current always flows in the standby mode Refer to the latest SANYO Semiconductor Data Sheet for confirmation before using this IC CMPOUT bit 2 ACMP output dat
19. off that use the contents of indirect registers indirect addressing modes See Section 2 11 for the addressing modes Used for these addressing modes are 64 2 byte indirect registers RO to R63 allocated to RAM addresses 0 to 7EH The indirect registers can also be used as general purpose registers e g for saving 2 byte data Naturally these addresses can be used as ordinary RAM on a byte 9 bits basis if they are not used as indirect registers RO to R63 are system reserved words to the assembler and need not be defined by the user 2 5 2 11 2 11 1 Address 7FH 7EH 03H 02H 01H 00H RAM R63 upper RO lower Reserved for system R63 7EH R1 2 R0 0 Fig 2 10 1 Allocation of Indirect Registers Addressing Modes The LC870000 series microcontrollers support the following seven addressing modes 1 Immediate immediate data refers to data whose value has been established at program preparation assembly time 2 Indirect register Rn indirect 0 n 5 63 3 Indirect register Rn C register indirect 0 n 63 4 Indirect register RO Offset value indirect 5 Direct 6 table look up 7 External data memory access The rest of this section describes these addressing modes Immediate Addressing The immediate addressing mode allows 8 bite 1 byte or 16 bit 1 word immediate data to be handled Examples are given below Examples LD Li LDW P
20. 0000 0000 R TIL TIL7 TILS TIL3 TIL2 TILO 3 27 Ti 3 4 4 4 Timer 1 high byte T1H 1 This is a read only 8 bit timer It counts up on every prescaler output clock Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO 0000 0000 R T1H T1H7 T1H6 T1H5 T1H4 T1H3 TIH2 T1HO 3 4 4 5 Timer 1 match data register low byte T1LR 1 This register is used to store the match data for TIL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the value of timer 1 low byte 2 The match buffer register is updated as follows and the match register has the same value when in inactive TILRUN 0 If active TILRUN 1 the match buffer register is loaded with the contents of TILR when the value of TIL reaches 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FEIC 0000 0000 R W TILR TILR7 TILR6 TILRS TILR4 TILR3 TILR2 TILRI TILRO 3 4 4 6 Timer 1 match data register high byte T1HR 1 This register is used to store the match data for T1H It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the value of timer 1 high byte 2 The match buffer register is updated as follow
21. 1 HPWM control register PWMCNT 8 bit register 1 The HPWM control register controls the operation and interrupts of HPWM 2 Bit RLDBSY PWMCNT bit 4 is read only 3 6 3 2 HPWM reference clock register PWMCKR 5 bit register 1 The HPWM reference clock register is used to select the PWCK and define the count value to be stored in the HPWPR Note 1 Setting bit PWCKSL PWMCKR bit 4 while the HPWM is active PWMST 1 is inhibited 3 6 3 8 HPWM DUTY low byte register PWM1LR 8 bit register 1 This register and bits 3 to 0 PWMIII to PWM108 of the PWMXHR are used to define the duty cycle of the HPWM 3 6 3 4 HPWM period low byte register PWM2LR 8 bit register 1 This register and bits 7 to 4 PWM211 to PWM208 of the PWMXHR are used to define the period of the HPWM 3 6 3 5 HPWM DUTY period high byte register PWMXHR 8 bit register 1 This register and PWMILR and PWM2LR are used to define the duty cycle and period of the HPWM Note 2 Setting PWMXHR bits 3 to 0 and PWMILR and PWMXHR bits 7 to 4 and PWM2LR to 000 H is inhibited Note 3 The output level from the HPWM remains unchanged while PWMXHR bits 3 to 0 and PWMILR Z PWMXHR bits 7 to 4 and PWM2LR 3 35 HPWM Note 4 If PWMXHR is loaded with data when PWMST is set to 1 the reload wait flag RLDBSY is set and PWMCKR PWMILR PWM2LR and PWMXHR are disabled for writes When the next HPWM period match signal occurs under this condition
22. 1 prescaler high byte 8 bit counter 1 Start stop The start stop of timer 1 prescaler high byte is controlled by the 1 0 value of TIHRUN timer 1 control register bit 7 2 Count clock Varies with the operating mode Mode T1LONG T1H Prescaler Count Clock 0 0 2 Tcyc 2 1 TIL match signal 3 Prescaler count Determined by the TIPRR value The count clock for T1H is generated at the intervals determined by the prescaler count T1HPRE T1HPRC2 T1HPRC1 T1HPRCO T1H Prescaler Count 0 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 4 Reset When the timer 1 stops operation or a T1H reset signal is generated 3 4 3 5 Timer 1 low byte TTL 8 bit counter 1 Start stop The start stop of the timer 1 low byte is controlled by the 0 1 value of TILRUN timer 1 control register bit 6 2 Count clock TIL prescaler output clock 3 Match signal A match signal is generated when the count value matches the value of the match buffer register 4 Reset The timer 1 low byte is reset when it stops operation or a match signal occurs 3 4 8 6 Timer 1 high byte T1H 8 bit counter 1 Start stop The start stop of the timer 1 high byte is controlled by the 0 1 value of TIHRUN timer 1 control register bit 7 2 Count clock prescaler output clock 3 Match signal A match signal is generated when the count value matches the value of the match buffer register 4 Reset The timer 1 high byte is rese
23. 12 and 8 bit conversion modes so that the appropriate conversion resolution can be selected according to the operating conditions of the application The AD mode register ADMRC is used to select the AD conversion mode 3 channel analog input The signal to be converted is selected using the AD converter control register ADCRC out of 3 types of analog signals that are supplied from P10 to P12 pins Conversion time select The AD conversion time can be set to 1 1 to 1 128 frequency division ratio The AD mode register ADMRC and AD conversion results register low byte ADRLC are used to select the conversion time for appropriate AD conversion Automatic reference voltage generation control The ADC incorporates a reference voltage generator that automatically generates the reference voltage when the AD converter is started Generation of the reference voltage stops automatically at the end of AD conversion which dispenses with the deed to manually provide on off control of the reference voltage There is also no need to supply the reference voltage externally 3 57 ADC12 6 It is necessary to manipulate the following special control registers to control the AD converter ADCRC ADMRC ADRLC ADRHC Address Initial value R W AD AD AD AD AD FES8 0000 0000 R W ADCRC ADCR3 CHSEL3 CHSEL2 CHSEL1 CHSELO START 3 9 8 Circuit Configuration 3 9 3 1 AD conversion control circuit 1 The AD conversion control circuit
24. 4 3 are set to 0 1 e PCON bit 0 set to 1 OCR register FEOE bits 5 4 and 1 are cleared Stopped Stopped Stopped Data preserved Stopped e Interrupt request from INTA to INTF generated Reset entry conditions established HALT PCON register bit 1 0 Notel The microcontroller switches into the reset state if it exits the current mode on establishment of reset entry conditions Table 4 3 2 Reset Time Normal Mode Pin States and Operating Modes this series HALT Mode HOLD Mode On Exit from HOLD Input g P10 P12 Input mode e Pull up resistor off P30 P33 Input mode e Pull up resistor off Input output pull up resistor controlled by a program Input output pull up resistor controlled by a program Standby Reset state entry conditions All modes Low level applied to RES pin Reset signal generated by internal reset function POR LVD Reset signal generated by watchdog timer HOLD mode entry conditions PCON register FEO7 bit 1 set to 1 HOLD mode All oscillators stopped Since OCR register bits 1 4 and 5 are cleared the medium speed RC oscillator is activated and designated as system clock when the HOLD mode is released When the HOLD mode is released high speed RC oscillator returns to the state established when HOLD mode is entered CPU and peripher
25. Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE10 0000 0000 R W TOCNT TOHRUN TOLRUN TOLONG TOLEXT TOHIE TOLCMP TOHRUN bit 7 TOH count control When this bit is set to 0 timer counter 0 high byte TOH stops on a count value of 0 The match buffer register of TOH has the same value as TOHR When this bit is set to 1 timer counter 0 high byte TOH performs the required counting operation The match buffer register of TOH is loaded with the contents of TOHR when a match signal is generated TOLRUN bit 6 TOL count control When this bit is set to 0 timer counter 0 low byte TOL stops on a count value of 0 The match buffer register of TOL has the same value as TOLR When this bit is set to 1 timer counter 0 low byte TOL performs the required counting operation The match buffer register of TOL is loaded with the contents of TOLR when a match signal is generated TOLONG bit 5 Timer counter 0 bit length select When this bit is set to 0 timer counter 05 higher and lower order bytes serve as independent 8 bit timers counters When this bit is set to 1 timer counter 0 functions as a 16 bit timer counter A match signal is generated when the count value of the 16 bit counter comprising TOH and TOL matches the contents of the match buffer register of TOH and TOL TOLEXT bit 4 TOL input clock select When this bit is set to 0 the count clock for TOL i
26. Address Initial value RAW Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEA3 0000 0000 R W PWM2LR PWM207 PWM206 PWM205 PWM204 PWM203 PWM202 PWM201 PWM200 3 6 4 5 HPWM DUTY period high byte register PWMXHR 1 This register PWMILR and PWM2LR are used to define the duty cycle and period of the HPWM Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEA4 00000000 R W PWMXHR PWM211 PWM210 PWM209 PWM208 PWM110 PWM109 PWM108 HPWM duty period Period defined by PWMCKR x PWMXHR bits 3 to 0 and PWMILR 1 12 bits HPWM period Period defined by PWMCKR x PWMXHR bits 7 to 4 and PWM2LR 1 12 bits Note Setting PWMXHR bits 3 to 0 and PWMILR and PWMXHR bits 7 to 4 and PWM2LR to 000 H is inhibited The level of the output from the HPWM remains unchanged while PWMXHR bits 3 to 0 and PWMILR Z PWMXHR bits 7 to 4 and PWM2LR If PWMXHR is loaded with data when PWMST is set to 1 the reload wait flag RLDBSY is set and the PWMCKR PWMILR PWM2LR and PWMXHR are disabled for writes When the next HPWM period match signal occurs under this condition the contents of the PWMCKR PWMILR PWM2LR and PWMXHR are reloaded into the respective buffer registers and RLDBSY is cleared For this reason since a write into PWMXHR will trigger the reload when changing the duty cycle or period while the HPWM is active code the
27. BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO FE70 ooo o T E zu a ee ES FE76 FE77 FE Pure IERI ee ere x n EE 2 2 FE7E 0000 0000 FSRO FLASH control bit4 is R 0 E23 ee FSAERR FSWOK INTHIGH FSROB2 FSPGL FSWREQ ee ee 1 1 Address Initial value R W 6872600 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO FEAO 0000 0000 R W PWMCNT 12bit PWM bit4 is R O PWMST PWMOE PWM INV RLDBSY PWMCTOV PWMCTIE PWMOV PWMIE Fw Wow mg 2 West Parsi res 2 FE 0000 0000 ww O Po Pis Pos prios Por Fus 00000 Rw ewar zo Pos Pico 20 moa Poor FEM 00000 mw O mio Pos mcos PRO Pros Piros re 000 wt emet fT ERST Proc emori FEA6 OHHH H000 R W PWMCTHR PWMDSL PWMCT10 PWMCTO9 PWMCTO8 AI 3 87 register map Address Initial value 10872600 Remarks BIT2 BITI BITO FECO 0000 0000 ESSI Mite per tod m
28. Comparator Registers IABCR FE5Dh ICDCR FE5Eh IADSL FE5Fh IEFCR FE4Ah and TOPRR IEFSL FE4Bh need setting TOCAL TOCAH Clock m Clock TOH Clear c in register E p IADS L FE5Fh Comparator Comparator Match buffer V i ragister TOLCMP pM TOHCMP Reload flag set Heload flag set TOLR TOHR 8 bit programmable counter gt S 8 bit programmable timer wit programmable prescaler Figure 3 3 2 Mode 1 Block Diagram TOLONG 0 TOLEXT 1 3 17 Clear Prescaler TOCAH Capture Capture trigger Clear Registers ICDCR FE5Eh IADSL FE5Fh IEFCR FE4Ah and IEFSL FE4Bh need setting TOLCMP TOHCMP flag set Match buffer register Reload TOHR TOLR 16 bit programmable timer with programmable prescaler Figure 3 3 3 Mode 2 Block Diagram TOLONG 1 TOLEXT 0 TOCAH Capture External Capture trigger Clock input Registers IABCR FE5Dh Set in register ICDCR FESEh IADS L FE5Fh IADSL FE5Fh IEFCR FE4Ah and IEFSL FE4Bh need setting TOLCMP TOHCMP flag set TOHR TOLR v lt 16 bit programmable counter gt Figure 3 3 4 Mode Block Diagram TOLONG 1 TOLEXT 1 LC872600 Chapter 3 3 3 4 Related Registers 3 3 4 1 Timer counter 0 control register TOCNT 1 This register is an 8 bit register that controls the operation and interrupts of TOL and
29. Figure 4 4 1 The external circuit connected to the reset pin shows an example that the internal reset function is disabled and an external power on reset circuit is configured Interior of microcontroller Exterior of microcontroller Watchdog Internal low speed timer WDT RC oscillator Int reset signal Internal reset circuit POR LVD Figure 4 4 1 Sample Reset Circuit Block Diagram 4 13 Reset 4 4 3 Reset State When a reset is generated by the RES pin internal reset circuit or watchdog timer the hardware functional blocks of the microcontroller are initialized by a reset signal that is in synchronization with the system clock Since the system clock is switched to the internal medium speed RC oscillator when a reset occurs hardware initialization is also carried out immediately even at power on time The system clock must be switched to high speed RC oscillator when the high speed RC oscillator gets stabilized The program counter is initialized to 0000H on a reset See Appendix AD 87 Register Map for the initial values of the special function registers SFR Notes and precautions The stack pointer is initialized to 0000H Data RAM is never initialized by a reset Consequently the contents of RAM are unpredictable at power on time When using the internal reset function it is necessary to implement and connect an external circuit to the reset pin according to the user s operating en
30. Fortes FREI Yr FREULS FREQLI FREQLI FRERLO rer xx ar R fortes RET FREOHA FREOHO FREOH2 FREOHT FREOHO Address Initial value R W 6872600 Remarks BIT8 BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITI BITO FEF8 0000 0000 R W SCON7 SCN7B7 5 7 5 7RUN FIXO SI7DIR 51 7 5 1 7 SI7IE FeFo 0000 0000 ew sur seum 875 seur7o rr 0000 0000 a sey seer sense seraa 58 672 AI 4 LC872600 APPENDIX I FUNCTION outputs 2 0 P1FCR FE46 bits 2 0 abet W P1FCR 5 f R P1FCR 9 P1 44 bits 2 0 D CMOS B Q Nch OD Pin W P1 C OR P12 P10 S lt lt Special input 1 INTE INTF P1DDR FE45 bits 2 0 HCT2 input P11 D Q W P1DDR 6 AD input input P11 P12 PPIDDR SIO7 clock input SIO7 clock output SIO7 data input SIO7 data output P10 None SIO7 data output Table of Port 1 Multiplexed Pin Functions Port 1 Block Diagram 1 Option Output type CMOS or Nch OD selectable on a bit basis ot P12 we IEFSL FE4B P11 gt E rcs A Port 1 Interrupt Block Diagram Timer 1 count clock Timer OL capture signal Timer OH capture signal Int request to vector 00013 Int request to vector 0001B Timer 1 count
31. HCTIOPI and HCTIOPO are and are 0 Enabled in modes other than HOLD 2 Count clock HCICK 3 Output clock Generates a clock whose frequency division ratio is selected by bits HC1PRSL1 and HCIPRSLO HCTICNT bits 5 and 4 4 Resetting and HCT1OPO are 0 3 7 3 5 HCT1 measurement counter HCT1CT 15 bit counter 1 Operation starUstop When the measurement start conditions 1 and 2 are detected after and HCTIOPO are set to a nonzero value HCTIOPI and are set to 0 Enabled in modes other than HOLD See Figure 3 7 2 for details 2 Countclock Output clock from HCTIPR 3 Overflow occurrence Set signal to HCT1OV generated 4 Resetting Reset immediately after HCT1OP1 are set to a nonzero value HCTIOV is reset at the same time 3 44 LC872600 Chapter 3 HCT10P1 0 HCT1END P30 HCT1IN Noise filter PRENA Edge counter set signal circuit circuit Edge selector HCT10P1 0 clear signal HCT1HR HCT1LR read HC1CKSL High speed RC oscillator clock Prescaler Counter HCT1CT HCT1PR HCT10V System clock HC1PRSL1 0 Operation start detector circuit Write other than HCT10P1 0 0 Figure 3 7 1 High speed Pulse Width Period Measurement Counter 1 Block Diagram H level width measurement P30 HCT1IN H level width measurement A A Measurement end condition detected falling edge de
32. OCR register bits 1 4 and 5 are cleared the medium speed RC oscillator is activated and designated as system clock when the HOLD mode is released When the HOLD mode is released high speed RC oscillator returns to the state established when the HOLD mode is entered e Reset Medium speed RC oscillator starts High speed RC oscillator stopped e Normal operating mode Start stop of all oscillators programmable e HALT mode All oscillators retain the state established when HALT mode is entered System Clock 5 To control the system clock it is necessary to manipulate the following special function registers PCON CLKDIV OCR Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE07 HHHH HHOO R W PCON PDN IDLE nooo ww Jero ocr cxscr mcox ckces rm ro mxo reson 4 2 3 Circuit Configuration 4 2 3 1 Internal medium speed RC oscillator 1 The medium speed RC oscillator oscillates according to the internal resistor and capacitor 2 Theclock from the medium speed RC oscillator is designated as the system clock after the reset state or HOLD mode is released 3 Unlike high speed RC oscillator medium speed RC oscillator starts normal oscillation immediately after oscillation starts 4 2 3 2 Internal high speed RC oscillator HRC 1 internal high speed RC oscillator o
33. R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE44 HHHH H000 R W P1 P12 P11 FIXO FIXO INTFLEG INTHIF INTFIE Bits 7 5 and 0 of PITST FE47 are available for test purposes They must always be set to 0 ESSEN EET ae mooo rw PIER PI0FCR ON INTELEG INTHIE 3 1 3 Related Registers 3 1 3 1 Port 1 data latch P1 1 The port 1 data latch is 3 bit register used to control the port 1 output data and pull up registers 2 When this register is read with an instruction data at pins P10 to P12 is read in If P1 FE44 is manipulated with an instruction NOTI CLR1 SET1 DBZ DBNZ INC or DEC the contents of the register are referenced instead of the data at port pins 3 Port 1 data can always be read regardless of the I O state of the port Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE44 HHHH H000 R W P12 Pll P10 3 1 3 2 Port 1 data direction register P1DDR 1 The port 1 data direction register is 3 bit register that controls the I O direction of port 1 data on a bit basis Port P1n are placed in the output mode when bit PInDDR is set to 1 and in the input mode when bit PInDDR is set to 0 2 Port PIn becomes an input with a pull up resistor if bit PInDDR is set to 0 and the bit P1n of the port 1 data latch is set to 1 Address Initial value RW Name BIT7
34. after the end of a measurement to determine if the measurement is successful HCT2 measurement period Period Period defined by bits 6 to 4 of HCT2CNT HCT22HR bits 2 to 0 HCT21MR HCT21LR value 19 bits 3 55 HCT2 Note Note Note Setting bits 7 to 4 of the HCT2HR when HCT2ST is set to 1 is inhibited Since HCT2CT and HCT2OV are reset immediately after HCT2ST is set to 1 be sure to read the current count value from the HCT2CT before configuring it for the next operation Read bits 3 to 0 of HCT22HR HCT22MR and HCT22LR after the measurement using the HCT2 is completed after confirming that HCT2END is set to 1 3 56 3 9 3 9 1 LC872600 Chapter 3 AD Converter ADC12 Overview This series of microcontrollers incorporates a 12 bit resolution AD converter that has the features listed below It allows the microcontroller to take in analog signals easily 1 2 3 4 5 6 3 9 2 2 3 4 5 12 bit resolution Successive approximation AD conversion mode select resolution switching 3 channel analog input Conversion time select Automatic reference voltage generation control Functions Successive approximation The ADC has a resolution of 12 bits Requires some conversion time The conversion results are placed in the AD conversion results registers ADRLC ADRHC AD conversion select resolution switching The AD converter supports two AD conversion modes
35. also generated Period match signal A match signal is generated when the HPWCT count value matches the PWM2BR value A set signal to PWMOV PWMCNT bit 1 and a clear signal to HPWOLT are also generated Resetting PWMST 0 period match signal generated or PWMST 1 and PWMCTOV and PWMDSL 1 HPWM auto stop counter HPWSTCT 11 bit counter Operation start stop PWMST 1 and PWMDSL I PWMST 0 or PWMDSL 0 Enabled in modes other than HOLD Count clock HPWCT period match signal 3 37 HPWM 3 Match signal A match signal is generated when the HPWSTCT count value matches the contents of PWMCTHR bits 2 to 0 and PWMCTLR A set signal to PWMCTOV is also generated 4 Resetting PWMST 0 PWMDSL 0 match signal generated or PWMST 1 and PWMCTOV 1 and PWMDSL 1 PWCKSL High speed RC oscillation clock DUTY DUTY register buffer register IPWMXHR bits PWM1BR 3 0 PWM1LR Prescaler Clock DUTY period counter Comparator dtu HPWCT System clock PWMOV set signal 3 Output latch compare decoder buffer register PWM2BR PWM signal Prescaler register Prescaler buffer PWMINV PWMOE PWMCKR register Laas bits 3 0 PWMPBR S 7 4 PWM2LR PWM operation stop Auto stop x counter Clock HPWSTCT PWMDSL E J Period count register PWMST DUTY period high byte register PWM
36. bit register that controls external interrupts A and B Address Initial value RW Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FESD 0000 0000 R W IABCR INTBLH INTBLV INTBIF INTBIE INTALH INTALV INTAIF INTAIE INTBLH bit 7 INTB detection polarity select INTBLV bit 6 INTB detection level edge select INTBLV INTB Interrupt Conditions Pin Data 0 Falling edge detected INTBIF bit 5 INTB interrupt source flag This bit is set when the conditions specified by INTBLH and INTBLV are satisfied When this bit and the INTB interrupt request enable bit INTBIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 000BH are generated This bit must be cleared with an instruction as it is not cleared automatically 3 9 PORTS INTBIE bit 4 INTB interrupt request enable When this bit and INTBIF are set to 1 a HOLD mode release signal and an interrupt request to vector address are generated INTALH bit 3 INTA detection polarity select INTALV bit 2 INTA detection level edge select INTALH INTALV INTA Interrupt Conditions Pin Data 0 Falling edge detected Low level detected 0 a Rising edge sees INTAIF bit 1 INTA interrupt source flag This bit is set when the conditions specified by INTALH and INTALV are satisfied When this bit and the INTA interrupt request enable bit INTAIE are set to 1 a HOLD mode release sig
37. clock Timer OL capture signal Timer OH capture signal 1 Port Block Diagrams P3 FE4C bits 1 0 P31 P30 INTA INTB HCT1 input P30 P3DDR FE4D bis HCT2 input P31 W PSDDR FUNCTION outputs 3 2 d P3 FE4C bits 3 2 D CMOS W P3 C Q Nch OD EH OR sng P33 P32 S E INTC INTD L R P3 P3DDR FE4D bits 3 2 D Q W P3DDR C R P3DDR FUNCTION Output HPWM output ACMP output Table of Port 3 Multiplexed Pin Functions Port 3 Block Diagram Option Output type CMOS or Nch OD selectable on a bit basis AII 2 LC872600 APPENDIX I IADSL FE5F f L INTD JT B Timer 0 clock input B Timer capture signal Int request to L ICDCR FESE vector 00013 Int request to vector 0001B E xx INTC Noisefiter 3 gt Noise fitter filter Timer OL capture signal s INTB Int request to vector 00003 IABCR FE5D Int request to vector 0000B INTA Port 3 Interrupt Block Diagram AII 3 Port Block Diagrams 4 LC872600 Revision History Revision History B Major amendments made to Rev 1 00 Location Page Description Chapter 1 Overview Standby function HOLD mode Additional information added to the description in paragraph 2 3 On chip Debugger function Changes made to the description of the on chip debugger function Package Form Additional informa
38. entered 3 12 LC872600 Chapter 3 3 3 Timer Counter 0 TO 3 3 1 Overview The timer counter O TO incorporated in this series of microcontrollers is a 16 bit timer counter that provides the following four functions 1 Mode0 Two channel 8 bit programmable timer with a programmable prescaler equipped with an 8 bit capture register 2 Model 8 bit programmable timer with a programmable prescaler equipped with an 8 bit capture register 8 bit programmable counter equipped with an 8 bit capture register 3 Mode2 16 bit programmable timer with a programmable prescaler equipped with a 16 bit capture register 4 Mode3 16 bit programmable counter equipped with a 16 bit capture register 3 3 2 Functions 1 0 Two channel 8 bit programmable timer with a programmable prescaler equipped with an 8 bit capture register Two independent 8 bit programmable timers TOL and TOH run on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on external input detection signals from P30 INTA P32 INTC P10 P12 timer OL capture input pins The contents of TOH are captured into the capture register TOCAH on external input detection signals from P31 INTB P33 INTD P10 P12 timer 0H capture input pins TOL period TOLR 1 x TOPRR 1 x Tcyc TOH period TOHR 1 x TOPRR 1 x Tcyc Tcyc Period of cycle clock 2 M
39. following three types of memory space 1 Program memory space 256K bytes 128K bytes x 2 banks 2 Internal data memory space 64K bytes 0000H to FDFFH out of 0000H to FFFFH is shared with the stack area 3 External data memory space 16M bytes External data memory space Program memory space Address Address FFFFFFH SFFFFH Intermal data Add ROM bank 1 tied RAM i Reserved for 16 Syslem FEFFH i SFR 8 bit 1FFFFH some 9 bit i FEO0H ROM bank 0 FDFFH 1 1 128KB RAM Stack i i 64 KB i 9 bit config 00000H 0000H 000000H Note SFR is the area in which special registers such as the accumulator are allocated see Appendixes 1 Figure 2 1 1 Types of Memory Space 2 2 Program Counter PC The program counter PC is made up of 17 bits and a bank flag BNK The value of BNK determines the bank The lower order 17 bits of the PC allows linear access to the 128K ROM space in the current bank Normally the PC advances automatically in the current bank on each execution of an instruction Bank switching is accomplished by executing a Return instruction after pushing necessary addresses onto the stack When executing a branch or subroutine instruction when accepting an interrupt or when a reset is generated the value corresponding to each operation is loaded into the PC Table 2 2 1 lists the values that are loaded into the PC when the res
40. of microcontrollers is provided with an analog comparator ACMP that has the following features 1 Output to the P32 CMPO pin output polarity selectable 2 Edge detection the pin is shared with the INTC and allows the noise filter feature to be selected 3 10 2 Functions 1 Analog comparator function The ACMP serves as a comparator that compares the input voltages from the P11 IN and P12 IN pins The comparator output can be output through the P32 CMPO pin and its polarity can also be selected This output can also be routed into the INTC external interrupt circuit or used as the input trigger for the high speed pulse width period measurement counter 2 HCT2 For input to the INTC the comparator output signal is multiplexed with the input signal from the P32 INTC pin in which case the noise filter and HOLD mode release functions are available 2 To control the analog comparator ACMP it is necessary to manipulate the following special function registers CMPCNT IADSL PIDDR PSDDR Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITO FECC 0000 0000 R W CMPCNT HCT2INSL INTCINSL P32OTSL1 CMPON CMPOUT P320TSLO CMPOTIV 3 10 3 Circuit Configuration 3 10 3 1 ACMP control register CMPCNT 8 bit register 1 ACMP control register is used to select the HCT2 input trigger signal to select the INTC input signal to select the comparator input channel to select
41. program so that PWMXHR be loaded with reload data in the last place It is possible to write data into PWMCKR PWMILR PWM2LR and PWMXHR when PWMST 1 PWMDSL 1 set value output mode and PWMCTOV PWMCNT bit 3 1 In this case RLDBSY is not set even when a write is attempted 3 41 HPWM 3 6 4 6 HPWM period count low byte register PWMCTLR 1 This register and bits 2 to 0 of the PVMCTHR are used to define the period count of the HPWM 2 The value of this register exerts no influence on the operation of the HPWM if PWMDSL is set to 0 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEA5 0000 0000 R W PWMCTLR PWMCTO07 PWMCT06 PWMCTOS5 PWMCT04 PWMCTO2 PRMCTOI 3 6 4 7 HPWM period count high byte register PWMCTHR 1 The HPWM period count high byte register is used to select the HPWM operating mode and to define the period count with PWMCTHR bits 2 to 0 and PWMCTLR 2 Bits 2 to 0 of the PVMCTHR exert no influence on the operation of the HPWM if PWMDSL is set to 0 Address Initial value RAW Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEA6 OHHH H000 R W PWMDSL PWMCT10 PWMCTO9 PWMCTO8 PWMDSL bit 7 HPWM operating mode select Setting this bit to 0 places the HPWM in the continuous output mode Setting this bit to 1 places the HPWM in the preset count output automatic stop mode Period u
42. runs in two modes 12 and 8 bit AD conversion modes 3 9 3 2 Comparator circuit 1 The comparator circuit consists of a comparator that compares the analog input with the reference voltage and a control circuit that controls the reference voltage generator circuit and the conversion results The end of conversion bit ADENDF of the AD control register ADCRC is set when an analog input channel is selected and the AD conversion terminates in the conversion time designated by the conversion time control register The conversion results are placed in the AD conversion results registers ADRHC ADRLC 3 9 3 3 Multiplexer 1 MPX1 1 Multiplexer 1 is used to select the analog signal to be subject to AD conversion from 3 channels of analog signals 3 9 3 4 Automatic reference voltage generator circuit 1 The reference voltage generator circuit consists of a network of ladder resistors and a multiplexer MPX2 and generates the reference voltage that is supplied to the comparator circuit Generation of the reference voltage is automatically started when an AD conversion starts and stopped when the conversion ends The reference voltage output ranges from VDD to VSS 3 9 4 Related Registers 3 9 4 1 AD control register ADCRC 1 The AD control register is an 8 bit register that controls the operation of the AD converter Address Initial value BIT7 BIT4 AD AD CHSEL3 CHSEL2 CHSEL1 CHSELO FES8 0000 0000 ADCHSELG bit 7 ADCH
43. the P32 CMPO multiplexed pin output and to control comparator operation 2 CMPOUT CMPCNT bit 2 is a read only 3 10 3 2 Analog comparator ACMP Comparator 1 Compares the input voltages from the P11 IN and P12 IN pins 2 comparator generates a high level signal when the input voltage level is gt and a low level signal when the input voltage level is lt 3 65 ACMP P11 IN P12 IN CMPON Comparator ACMP CMPOTIV To HCT2 INTCINSL P32 INTC NFSL1 0 IADSL bits 2 and 1 CMPOUT Synchronizer Noise filter circuit INTC edge detection circuit P11 HCT2IN P31 HCT2IN 2 P320TSL1 0 2 IADSL bit 3 HCT2INSL P32 CMPO output P32DDR P32 P3 bit 2 P3DDR bit 2 Figure 3 10 1 Analog Comparator and P32 CMPO Multiplexed Pin Output Block Diagram 3 10 4 Related Registers 3 10 4 1 ACMP control register CMPCNT 1 The ACMP control register is used to select the HCT2 input trigger to select the INTC input signal to select the comparator input channel to select the P32 CMPO multiplexed pin output and to control comparator operation 2 CMPOUT is read only Address Initial value RW Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FECC 0000 0000 R W CMPCNT HCT2INSL INTCINSL FIXO P320TSL1 CMPON CMPOUT P32OTSLO CMPOTIV HCT2INSL bit 7 HCT2 input trigger select See Section 3 8
44. the PCON register is cleared and the microcontroller switches to the HALT mode Do not allow the microcontroller to enter into the HALT or HOLD mode while AD conversion is in progress Make sure that ADSTART is set to 0 before placing the microcontroller into HALT or HOLD mode 4 3 3 Related Registers 4 3 3 1 Power Control Register PCON 2 bit register 1 The power control register is a 2 bit register that specifies the operating mode normal HALT HOLD Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE07 HHHH HH00 R W PCON PDN IDLE bits 7 to 2 These bits do not exist They are always read as 1 PDN bit 1 HOLD mode setting flag PDN Operating mode 0 Normal or HALT mode 1 This bit must be set with an instruction When the microcontroller enters the HOLD mode all oscillations high speed RC oscillator medium speed RC oscillator are stopped and bits 1 4 and 5 of the OCR register are set to 0 When the microcontroller returns from the HOLD mode medium speed RC oscillator resumes oscillation and high speed RC oscillator restores the state that 1s established before the HOLD mode is entered and the medium speed RC oscillator is designated as the system clock source 4 10 LC872600 Chapter 4 2 is cleared when a HOLD mode resetting signal INTA INTB INTC INTD INTE or INTF is generated or a reset occurs 3 IDLE bit 0 is automaticall
45. the analog comparator output is assigned to the INTC input On chip Debugger Function Supports software debugging with the IC mounted on the target board selectable from 3 series 1 LC87D2708A All terminal function of LC87F2608A can be used 2 LC87F2708A All terminal function of LC87F2608A can be used The debug feature is limited 3 LC87F2608A The debugger terminal function when an On chip debugger is used cannot be used The debug feature is limited e Two channels of on chip debugger pins are available LC87F2608A 1 4 LC872600 Chapter 1 Data security feature Protects the program data stored in flash memory from unauthorized read or copy Note This data security feature does not necessarily provide absolute data security Package Form 105 Lead Halogen free type e MFPIAS for debugging only Lead free type Development tools On chip debugger 1 87 LC87D2708A or LC87F2708A 2 TCB87 Type B LC87F2608A 3 TCB87 Type C 3 wire version LC87D2708A or LC87F2708A 4 TCB87 Type C 3 wire version LC87F2608A 1 5 1 3 Pinout P31 INTB HCT2IN DBGP01 P30 INTA HCT1IN DBGPXO RES P10 SO7 INTE ANO DBGPO2 VSS1 P31 INTB HCT2IN DBGPO1 P30 INTA HCT1IN DBGPXO RES P10 SO7 INTE ANO DBGP02 vsst NC DBGP22
46. to control the conversion time 2 Since the data in this register is not established during an AD conversion the conversion results must be read out only after the AD conversion is completed Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FESA 0000 0000 R W ADRLC DATAL3 DATAL2 DATALI DATALO ADRL3 ADRL2 ADRLI ADTM2 DATALS bit 7 DATAL2 bit 6 DATAL1 bit 5 DATALO bit 4 Lower order 4 bits of AD conversion results ADRL3 bit 3 Fixed bit This bit must always be set to 0 ADRL2 bit 2 Fixed bit This bit must always be set to 0 ADRL1 bit 1 Fixed bit This bit must always be set to 0 ADTM bit 0 AD conversion time control This bit and AD mode register ADMRC bits ADTMI bit 1 and ADTMO bit 0 are used to control the conversion time See the subsection on the AD mode register for the procedure to set the conversion time Note The conversion results data contains some errors quantization error combination error Be sure to use only valid conversion results while referring to the latest SANYO Semiconductor Data Sheet 3 9 4 4 conversion results register high byte ADRHC 1 The AD conversion results register high byte is used to hold the higher order 8 bits of the results of an AD conversion that is carried out in the 12 bit AD conversion mode The register stores the whole 8 bits of an AD conversion that is carried out in the 8 bit AD con
47. to select the HCICK to select the frequency division ratio for the HCTIPR and to control the operation and interrupts of HCTI Address Initial value RAW Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FECO 0000 0000 R W HCTICNT HCIPRSLI HCIPRSLO HCTIOPI HCTIOPO HCTIEND FIXO bit 7 Test bit This bit is used only for testing and must always be set to 0 HC1CKSL bit 6 HCT1 reference clock HC1CK select HC1CKSL Reference Clock HC1CK 0 High speed RC oscillation clock HC1PRSL1 bit 5 HC1PRSLO bit 4 HCT1 prescaler HCT1PR control HCT1 Prescaler HC1PRSL1 HC1PRSLO Frequency Division Ratio Select 1 0 1 4 1 1 bit 3 HCT1 operation control 1 bit 2 HCT10OP1 HCT1OPO HCT1 Operation Select operation stopped 1 H level width measurement from rising edge to falling edge L level width measurement from falling edge to rising edge Period measurement from falling edge to falling edge The measurement starts when the specified measurement start condition is detected after and are set to a nonzero value see Figure 3 7 2 for details HCT1END bit 1 End of HCT1 measurement flag This bit is set to 1 when the end of HCT1 measurement condition is detected see Figure 3 7 2 for details This flag bit must be cleared with an instruction bit 0 End
48. to the next entry into a standby mode is less than low speed RC oscillator clock x 4 however the low speed RC oscillator circuit may not stop oscillation when the CPU enters a standby mode In such a case a standby mode is on several nA of operating current flows because the low speed RC oscillator circuit is active though the watchdog timer is inactive To minimize the standby power requirement of the set code the program so that an interval of low speed RC oscillator clock x 4 or longer be provided between release from a standby mode and entry into the next standby mode Note that the oscillation frequency of the low speed RC oscillator may fluctuate See the latest SANYO Semiconductor Data Sheet for details 4 26 Appendixes Table of Contents Appendix Special Functions Register SFR Appendix ll Port 1 Block Diagram Port 3 Block Diagram LC872600 APPENDIX I Address Initial value R W 6872600 Remarks 78 BIT7 BIT6 BITS BIT4 2 BITI BITO O OIFF XXXXX XXXX R W RAM 512B 9 bits long E Lo pe pe Esc 2 P 1 23 DENN mL m4 FE05 PUN xus Wis mis E i ims re irs ra ra ET EXIT E x sa En FEOF Prescaler is 8 bits long FE11 00
49. x O O External reset input internal reset output 1 8 LC872600 Chapter 1 1 6 Port Output Types The table below lists the types of port outputs and the presence absence of a pull up resistor Data can be read from an input output port even if it is in the output mode Option Port Name Selection Output Type Pull up Resistor Unit CMOS Programmable P10 to P12 1 bit RES N channel open drain Programmable Ede CMOS Programmable P30 to P33 1 bit N channel open drain Programmable 1 7 Recommended Unused Pin Connections Recommended Unused Pin Connections Software Pin Name P10 to P12 P30 to P33 OPEN Set output low Set output low 1 8 User Options Flash Options Option Name Option Type Version Switched in Description Units of CMOS P10 to P12 1 bit N channel open drain type Port output type PeO CMOS P30 to P33 1 bit N channel open drain type 00000H Program start address 01E00H Brown out Enable Used Brown out detector reset detector fo Disable Not used Brown out trip level Power on reset Power on reset 3 levels function level High speed RC oscillator Oscillation 20 MHz circuit frequency 40 MHz MFP10S LC87F2608A Package type MFP14S Debugged by using LC87D2708A or LC87F2708A 1 9 function 3 levels 1 10 LC872600 Chapter 2 2 Internal Configuration 2 1 Memory Space This series of microcontrollers have the
50. 00 0000 TOPRR 256 rez m 9 PS X 0000 0000 5 SP7 5 6 55 SP2 si 0000 0000 5 SP9 o 7 f CLKSGL HRCON CLKCES Fixo Fixo Fixo RCSTOP pL TOPRR7 TOPRR6 TOPRR5 TOPRR4 TOPRR3 TOPRR2 TOPRR1 TOPRRO res 0000 m SSCS 0000 0000 00000000 RAM TOR 1 TORS TOHRI TOHRO T T T W OV 5 7 so st 5 N 2 CR T P 4 rei R TO Timer 0 capture register L Toca TOCALS Tocana Toca s Tocat TocaLo R O0 Timer 0 capture register H Tocana Tocana Tocant TOOMO re amp oom sw rmm ritu rio rome rie rto res 0000 0000 R O TIMPRCO TILPRE TILPRGE TiLPRCI TILPROO re oom R rmt ms ma ns m nu res oom R m8 mm nw rm nes ne rec 0000 0000 ru O TN Tum rus rue rus rim rep 0000 0000 ww rm ne res res TIHRO 87 register map A
51. 16 bits of data need match in the 16 bit mode 2 The match buffer register is updated as follows The match register matches TOLR when it is inactive TOLRUN 0 When the match register is running TOLRUN 1 it is loaded with the contents of TOLR when a match signal is generated 0000 0000 TOLR6 TOLRS TOLR3 TOLR1 TOLRO 3 20 LC872600 Chapter 3 3 3 46 Timer counter 0 match data register high byte 1 This register is used to store the match data for It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the higher order byte of timer counter 0 16 bits of data need match in the 16 bit mode 2 The match buffer register is updated as follows The match register matches TOHR when it is inactive TOHRUN 0 When the match register is running TOHRUN 1 it is loaded with the contents of TOHR when a match signal is generated Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE15 0000 0000 R W TOHR TOHR7 TOHR6 TOHRS TOHR4 TOHR3 2 1 TOHRO 3 3 47 0 capture register low byte TOCAL 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 low byte TOL on an external input detection signal Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEI6 XXXX XXXX R TOCAL TOCAL7 TOCAL
52. 2ST is set to 1 see Figure 3 8 2 for details HCT2END bit 1 End of HCT2 measurement flag This bit is set to 1 when the end of HCT2 measurement condition is detected see Figure 3 8 2 for details This flag bit must be cleared with an instruction 2 bit 0 End of HCT2 measurement interrupt request enable control When this bit and HCT2END are set to 1 an interrupt request to vector address 003BH is generated Note Writing bits 7 to 4 of the HCT2CNT while the is active HCT2ST 1 is inhibited 3 53 3 8 4 2 HCT2 capture low byte register HCT21LR 1 The HCT2 capture low byte register stores bits 7 to 0 of the L level width measured by the HCT2 2 Thisregister is read only 3 Thecontents of the HCT2CT are captured into this register if the end of L level width measurement condition is detected while HCT2ST is set to 1 see Figure 3 8 2 for details Address Initial value RW Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEC6 XXXX XXXX R HCT21LR HCT21RO7 HCT21R06 21 5 21 4 21 21 02 21 HCT21R00 3 8 4 3 2 capture middle byte register 21 1 The HCT2 capture middle byte register stores bits 15 to 8 of the L level width measured by the HCT2 2 This register is read only 3 The contents of the HCT2CT are captured into this register if the end of L level width measurement condition is detected while HCT2ST is set to 1 see Fig
53. 3 5 4 Related Registers 3 5 4 1 5107 control register SCON7 1 The SIO7 control register is an 8 bit register that controls the operation and interrupts of SIO7 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEF8 0000 0000 R W SCON7 SCN7B7 SI7REC 517803 FIXO SI7DIR SI7OVR SITEND SCN7B7 bit 7 User bit 1 Thisbit can be read and written with instructions The user can use this bit freely SI7REC bit 6 Setting SIO7 reception mode 1 A 1 in this bit places 5107 into the reception mode The contents of SIOSF7 are placed in SBUF7 at the end of serial transmission 2 this bit places 5107 into the transmission mode SI7RUN bit 5 SIO7 operation flag 1 Alinthis bit indicates that 5107 is running 2 This bit must be set with an instruction 3 This bit is automatically cleared at the end of serial transmission on the rising edge of the last clock involved in the transfer FIXO bit 4 Test bit 1 Thisbit is used for only test This bit must always be set to 0 SI7DIR bit 3 MSB LSB first select 1 Alinthis bit places 5107 into the MSB first mode 2 0 in this bit places 5107 into the LSB first mode SI7OVR bit 2 SIO7 overrun flag 1 This bit is set when a falling edge of the input clock is detected with SITRUN 0 2 Read this bit and judge if the communication is performed normally at the end of the communication 3 This bit must be cleared with
54. 421 E MJ 4 5 422 FuncCliOns 4 5 4 2 3 Circuit Configuration meme 4 6 4 2 4 Related Registers mme 4 7 43 Standby Function 4 10 4 3 1 E 4 10 4 3 2 Veale ttt 4 10 433 Related Registers mmm 4 10 44 Reset Function Ree 4 13 4 4 1 4 13 4 4 2 gt 4 13 4 4 3 Reset State tttttttttsetesecesescseceseceseseseseseeeseseseseseseeeseseeeseseseeseeseseessesenesens 4 14 4 5 Internal Reset Function eruere 4 15 4 5 1 RN 4 15 452 SINT LP 4 15 4 5 3 Circuit Configuration meme 4 15 3 Contents 4 5 4 Options eee eee rere reer e rere tree reer ee reer etree reer eee eee eee eee 4 1 6 4 5 5 Sample Operating Waveforms of the Internal Reset Circuit 4 18 4 5 6 Notes on the Use of the Internal Reset Circuit mH 4 19 4 5 7 Notes to be Taken When Not Using the Internal Reset Circuit 4 20 4 6 Watchdog Timer WDT eee eee ee eee eee eee eee etree reer eee eee eee eee eee eee eee eee eee 4 22 4 6 1 Overview eee eee eee eee eee eee eee ee eee eee eee eee eee eee eee eee eee eee 4 22 4 6 2 Functions eee eee reer etree reer etree ree reer tree reer tree reer etree reer tree n 4 22 463 Circuit Configuration eee eee eee eee eee eee eee eee eee reer eee eee eee eee eee eee e
55. 6 TOCALS TOCALA TOCAL3 TOCAL2 TOCALI TOCALO 3 3 4 8 Timer counter 0 capture register high byte TOCAH 8 bit register 1 This register is a read only 8 bit register used to capture the contents of timer counter 0 high byte TOH on an external input detection signal Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEI7 XXXX XXXX R TOCAH TOCAH7 TOCAH6 TOCAHS TOCAH3 TOCAH2 TOCAHI TOCAHO 3 2 3 4 Timer Counter 1 T1 3 4 1 Overview The timer counter 1 1 incorporated in this series of microcontrollers is a 16 bit timer counter that provides the following two functions 1 4 0 8 bit programmable timer with an 8 bit prescaler 8 bit programmable timer counter with an 8 bit prescaler 2 Mode 2 16 bit programmable timer counter with an 8 bit prescaler 3 4 2 Functions 1 4 0 8 bit programmable timer with an 8 bit prescaler 8 bit programmable timer counter with an 8 bit prescaler TIL functions as an 8 bit programmable timer counter that counts the number of signals obtained by dividing the cycle clock by 2 or external events while T1H functions as an 8 bit programmable timer that counts the number of signals obtained by dividing the cycle clock by 2 TIL period TI1LR 1 x TILPRC count x 2Tcyc or TILR 1 x TILPRC count events detected period T1HR 1 x TIHPRC count x 2Tcyc 2 Mode 2 16 bit programmable tim
56. BIT6 5 BIT4 BIT3 BIT2 BIT1 BITO 45 HHHH H000 R W PIDDR P12DDR PIIDDR PIODDR LC872600 Chapter 3 Register Data Port Pin State Built in Pull up Resister Enabled Open Enabled Internal pull up resistor Enabled High open CMOS N channel open drain 3 1 3 3 Port 1 function control register P1FCR 1 The port 1 function control register is a 3 bit register that controls the multiplexed pin outputs of port 1 Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE46 HHHH H000 R W PIFCR P12FCR P10FCR Pin Pin Data in Output Mode PinDDR 1 Value of port data latch P12 SIO7 clock output data High output Value of port data latch P11 The high data output at a pin that is selected as an N channel open drain output through a user option is represented by an open circuit Eo eee 1 Of sto7ouputdata NI ERN T E Er px 4 P12FCR bit 2 P12 function control SIO7 clock output control This bit controls the output data at pin P12 When P12 is placed in the output mode PI2DDR 1 and P12FCR is set to 1 the OR of the SIO7 clock output data and the port data latch data is placed at pin P12 P11FCR bit 1 P11 function control SIO7 data output control This bit controls the output data at pin P11 When bit P11 is placed in the output mode P11DDR 1 and P11FCR
57. CMOS 8 BIT MICROCONTROLLER LC872600 SERIES eel USER S MANUAL iim REV 1 00 ON Semiconductor Digital Solution Division Microcontroller amp Flash Business Unit ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body o
58. DR 3 43 HCT1 Initial value 0000 0000 HCICKSL HCIPRSLI HCIPRSLO HCTIOPI HCTIOPO HCTIEND 3 7 3 Circuit Configuration 3 7 3 1 HCT1 control register HCT1CNT 8 bit register 1 The HCT1 control register is used to select the HC1CK to select the frequency division ratio for the HCTIPR and to control the operation and interrupts of HCT1 Note Writing bits 7 to 4 of HCTICNT while the is active to HCTIOPO set to a nonzero value is inhibited 3 7 3 2 HCT1 measurement counter low byte register HCT1LR 8 bit register 1 The measurement counter low byte register is a register to read out the lower order 8 bits of HCTICT data 2 Thisregister is read only 3 7 8 3 HCT1 measurement counter high byte register HCT1HR 8 bit register 1 This HCT1 measurement counter high byte register is a register to read out the HCTICT overflow detection flag and the higher order 7 bits of the HCTICT data 2 Thisregister is read only Note Since HCTICT and HCTIOV HCTIHR bit 7 are reset immediately when none of bits HCTIOPI and HCTIOPO HCTICNT bits 3 and 2 are set to 0 be sure to read the current count value from the HCTICT before configuring it for the next operation Note Read HCTIHR and HCTILR after the measurement of is completed after confirming that HCTIEND is set to 1 3 7 34 prescaler HCT1PR 3 bit counter 1 Operation start stop None of
59. DR bit 3 and P33 0 P3 bit 3 Note that since the P33 signal and the PWM signal are ORed the PWM signal is set to and held at the H level if P33 is set to 1 PWMINV bit 5 HPWM output polarity control If this bit is set to 0 the PWM output signal starts at the L level If this bit is set to 1 the PWM output signal starts at the H level See Figure 3 6 2 RLDBSY bit 4 HPWM reload wait flag If an attempt is made to write data into the PWMXHR when PWMST is set to 1 the RLDBSY bit is set and PWMCKR PWMILR PWM2LR and PWMXHR are disabled for writes The conditions for clearing the RLDBSY flag are 1 The HPWM is suspended PWMST 0 2 A next HPWM period match signal is generated after RLDBSY is set Tt is allowed to write data into PWMCKR PWMILR PWM2LR and PWMXHR if PWMST 1 and PWMDSL and PWMCTOV 1 In this case the state of RLDBSY remains unchanged when a write is attempted PWMCTOV bit 3 HPWM period count match flag This bit is set if a match occurs between the HPWSTCT count value and the value of PWMCTHR bits 2 to 0 and PWMCTLR and a match signal is generated when PWMST is set to 1 and PWMDSL bit 7 is set to 1 This flag must be cleared with an instruction PWMCTIE bit 2 HPWM period count interrupt request enable control When this bit and PWMCTOV are set to 1 an interrupt request to vector address 0043H is generated 3 39 HPWM PWMOV bit 1 HPWM period match
60. F are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated 3 2 3 5 Input signal select register IADSL 1 The input signal select register is a 6 bit register used to select the timer 0 inputs noise filter sampling clock and the polarity of P32 multiplexed pin output esr 0000 rw rabsL sOHCP sTOLCP Ps20mV nesti STOHCP bit 7 Timer OH capture signal input port select Selects the port for the timer OH capture signal input If this bit is set to 1 a timer OH capture signal is generated when an input that will satisfy the INTB interrupt detection conditions is supplied to P31 If the level sense interrupt mode is selected for INTB a capture signal is generated every 1 Tcyc while the specified level of input signal is present at P31 If this bit is set to 0 a timer OH capture signal is generated when an input that will satisfy the INTD interrupt detection conditions is supplied to P33 3 11 PORTS STOLCP bit 6 Timer OL capture signal input port select Selects the port for the timer OL capture signal input If this bit is set to 1 a timer OL capture signal is generated when an input that will satisfy the INTA interrupt detection conditions is supplied to P30 If the level sense interrupt mode is selected for INTA a capture signal is generated every 1 Tcyc while the specified level of input signal is present at P30 If this bit is set to 0 a timer OL
61. H level X level X level None unable to reset with interrupt Figure 4 3 1 Standby Mode State Transition Diagram 4 12 LC872600 Chapter 4 4 4 Reset Function 4 4 1 Overview The reset function initializes the microcontroller when it is powered on or while it is running 4 4 2 Functions This series of microcontrollers provides the following three types of resetting function 1 External reset via the RES pin The microcontroller is reset without fail by applying and holding a low level to the RES pin for 200us or longer Note however that a low level of a small duration less than 2008 is likely to trigger a reset The RES pin can serve as a power on reset pin when it is provided with an external time constant element 2 Internal reset The internal reset function is available in two types the power on reset POR that triggers a reset when power is turned on and the low voltage detection reset LVD that triggers a reset when the power voltage falls below a certain level Options are available to set the power on reset resetting level to Enable use and Disable disuse the low voltage detection reset function and its threshold level 3 Reset function using a watchdog timer The watchdog timer of this series of microcontroller can be used to generate reset by the internal low speed RC oscillator at a predetermined time intervals An example of a resetting circuit is shown in
62. LCMP 1 1 set flag set bit programmabl lt P ian on 5 lt 8 bit programmable timer gt Figure 3 4 1 Mode 0 T1LONG 0 Block Diagram Clock 2Tcyc 5 TiLprescaler or external events Set in Clear Clock IEFCR FE4Ah TIL IEFSL FE4Bh Match Comparator registers Match buffer register Match buffer register Reload Reload T1LCMP T1HCMP TILR flag set TIRA flag set 16 bit programmable timer counter Figure 3 4 2 Mode 2 T1LONG 1 Block Diagram 3 25 3 4 4 Related Registers 3 4 41 Timer 1 control register T1CNT 1 Timer 1 control register is an 8 bit register that controls the operation and interrupts of TIL and Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE18 0000 0000 R W TICNT TIHRUN TILRUN TILONG TILCMP T1HRUN bit 7 count control When this bit is set to 0 timer 1 high byte T1H stops on a count value of 0 The match buffer register of T1H has the same value as TIHR When this bit is set to 1 timer 1 high byte T1H performs the required counting operation T1LRUN bit 6 T1L count control When this bit is set to 0 timer 1 low byte T1L stops on a count value of 0 The match buffer register of TIL has the same value as When this bit is set to 1 timer 1 low byte T1L performs the requir
63. M stops operation and enables bits 2 to 0 of the PWMCTHR and the PWMCTLR to be written When rewriting bits 2 to O of the PWMCTHR or the PWMCTLR after the HPWM is automatically stopped do so after making sure that PWMCTOV is set to I or that an HPWM period count interrupt has occurred To resume the set value output mode processing after the HPWM is automatically stopped it is necessary to clear PWMCTOV to 0 HPWM prescaler buffer register PWMPBR 4 bit buffer register The PWMPBR is a buffer register for storing the preset count value to be loaded into the HPWPR It stores the bits 3 to 0 of the PWMCKR PWPRSL3 to PWPRSLO The data in this buffer register is updated as follows If PWMST 0 or PWMST 1 and PWMCTOV 1 and PWMDSL 1 bits 3 to 0 of the PWMCKR and the PWMPBR have the same value See note 4 in Subsection 3 6 3 5 HPWM DUTY period high byte register for details on the update procedure for the buffer registers when PWMST is set to 1 3 36 3 6 3 9 1 2 3 6 3 10 1 2 3 6 3 11 2 3 4 3 6 3 12 2 3 4 5 3 6 3 13 2 LC872600 Chapter 3 HPWM DUTY buffer register PWM1BR 12 bit buffer register The PWMIBR is a buffer register for storing the duty cycle match data that matches the value of the HPWCT It stores the 12 bit data from PWMXHR bits 3 to 0 and PWMILR The data in this buffer register is updated as follows If PWMST 0 or PWMST 1 and PWMCTOV 1 and PWMDSL
64. M that is actually incorporated in the microcontroller varies with the series of the microcontroller 9 bits are used to access addresses 0000H to FDFFH of the 128K ROM space and 8 or 9 bits are used to access addresses to FFFFH The 9th bit of RAM is implemented by bit 1 of the PSW and can read and written The 128 bytes of RAM from 0000H to 007FH are paired to form 64 2 byte and can also be used as 64 indirect address registers The bit length of these indirect registers is normally 16 bits 8 bits x 2 When they are used by the ROM table lookup instruction LDCW however their bit length is set to 17 bits 9 higher order bits 8 lower order bits As shown in Figure 2 4 1 the usable instructions vary depending on the address of RAM The efficiency improvement of use ROM and execution speed can be attempted by using these instructions properly 2 2 FFFFH FFOOH FEFFH FEOOH FDFFH 2000H 0200 01FFH 0100H 0000H Reserved for system SFR space Stack space 9 bit L lt gt Bit instruction direct short Note Some registers are 9 bit Bit instruction direct long LC872600 Chapter 2 Non bit instruction direct long indirect 16 bit operation instruction direct indirect Non bit instruction direct short Fig 2 4 1 RAM Addressing Map When the value of the PC is stored in RAM during the execution of a subroutine call instruction or interrup
65. Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FECA XXXX XXXX HCT2MR HCT2RIS HCT2RI4 HCT2RI3 HCT2RI2 HCT2RI1 HCT22R10 HCT22RO9 22 3 54 LC872600 Chapter 3 3 8 4 7 HCT2 measurement counter high byte register HCT22HR 1 The HCT2 measurement counter high byte register is a register for HCT2 input trigger selection trigger signal sampling shift selection HCT2CT overflow detection flag and to read out bits 18 to 16 of HCT2CT 2 Bits3 to 0 of this register are read only Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FECB 0000 R W 22 TRGSL TRGSFT2 TRGSFTI TRGSFTO 2 HCT2RIS HCT22RI7 HCT22RI6 TRGSL bit 7 HCT2 input trigger select This bit and HCT2INSL CMPCNT bit 7 are used to select the input signal to be measured HCT2INSL TRGSL HCT2 Input Trigger Selection P11 HCT2IN TRGSFT2 bit 6 TRGSFT1 bit 5 HCT2 trigger shift counter TRGSFTCT control TRGSFTO bit 4 TRGSFT2 TRGSFT1 TRGSFTO HCT2 Tyger lt Shift Counter Count _ _ e See Figure 3 8 2 for details Period from detection of an edge to generation of a sampling clock Period defined by bits 6 to 4 of HCT2CNT Count defined by bits 6 to 4 of HCT22HR HCT2OV bit 3 HCT2CT overflow detection flag This bit is set if the HCT2CT detects an overflow condition while the HCT2 is active HCT2ST 1 Read this bit
66. OLCMP and TOHCMP are set at the same time in the 16 bit mode 3 3 4 2 Timer 0 programmable prescaler match register TOPRR 1 Timer 0 programmable prescaler match register is an 8 bit register that is used to define the clock period Tpr of timer counter 0 The count value of the prescaler starts at when is loaded with data 8 1 Period of cycle clock 00000000 rw TOPRR ToPRR7 5 TOPRR3 3 3 4 3 Timer counter 0 low byte TOL 1 This is a read only 8 bite timer counter It counts the number of match signals from the prescaler external signals Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE12 0000 0000 R TOL TOL7 TOL6 TOLS TOL4 TOL3 TOL2 TOLO 3 3 44 Timer counter 0 high byte 1 This is a read only 8 bite timer counter It counts the number of match signals from the prescaler overflows occurring in TOL Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE13 0000 0000 R TOH TOH7 TOH6 TOHS TOH4 TOH3 TOH2 TOHO 3 3 4 5 Timer counter 0 match data register low byte TOLR 1 This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the lower order byte of timer counter 0
67. R6 TIHR5 TIHR4 TIHR3 TIHR2 TIHRI TIHRO 3 22 LC872600 Chapter 3 3 4 3 Circuit Configuration 3 4 81 Timer 1 control register T1CNT 8 bit register 1 timer 1 control register controls the operation and interrupts of the TIL and 3 4 3 2 Timer 1 prescaler control register T1PRR 8 bit counter 1 This register sets the clocks for and 3 4 8 3 Timer 1 prescaler low byte 8 bit counter 1 Start stop The start stop of timer 1 prescaler low byte is controlled by the 0 1 value of TILRUN timer 1 control register bit 6 2 Countclock 2 Tcyc events Note 1 Note 1 TIL serves as an event counter when INTE or INTF is specified as the timer 1 count clock input in the external interrupt E F pin select register IEFSL It serves as a timer that runs using 2Tcyc as its count clock if both INTE and INTF are not specified as the timer 1 count clock input 3 Prescaler count Determined by the TIPRR value The count clock for is generated at the intervals determined by the prescaler count T1LPRE TILPRC2 TILPRC1 T1LPRCO T1L Prescaler Count 0 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 4 Reset When the timer 1 stops operation or a T1L reset signal is generated 3 23 Ti 3 4 3 4 Timer
68. RG76 SBRG75 SBRG74 SBRG73 SBRG72 SBRG71 SBRG70 3 5 5 58107 Transmission Examples 3 5 5 1 Synchronous 8 bit mode 1 Setting the clock Setup SBR7 when using an internal clock 2 Setting the transmission mode e Set as follows SI7DIR 517 SI7IE 1 3 Setting up the ports Clock Port P12 Internal clock Output Data Output Port Data I O Port P10 P11 Data transmission only Output Data reception only ppt Data transmission reception 3 wire Output Data transmission reception 2 wire ee he sil N channel open drain output 4 Setting up output data Write the output data into SBUF7 in the data transmission or data transmission reception mode 5 Starting operation Set SITRUN 6 Reading data after an interrupt Read SBUF7 in the reception mode e Clear 517 Return to step 4 when repeating transmission reception processing 3 32 LC872600 Chapter 3 3 5 6 SIO7 HALT Mode Operation 1 5107 processing is enabled in the HALT mode 2 The HALT mode can be reset by an interrupt that is generated during SIO7 processing 3 33 HPWM 3 6 3 6 1 High speed 12 bit PWM HPWM Overview This series of microcontrollers is provided with a high speed 12 bit PWM HPWM that has the following features 1 2 3 3 6 2 2 3 4 System clock or high speed RC oscillation clock 20 MHz or 40 MHz based operation selectable Programmable v
69. SEL2 bit 6 ADCHSEL1 bit 5 ADCHSELO bit 4 AD conversion input signal select These 4 bits are used to select the signal to be subject to AD conversion 3 58 LC872600 Chapter 3 AD AD AD AD CHSEL3 CHSEL2 CHSEL1 CHSELO 0 0 0 0 P10 ANO bit 3 Fixed bit Signal Input Pin This bit must always be set to 0 ADSTART bit 2 AD converter operation control This bit starts 1 and stops 0 AD conversion processing AD conversion starts when this bit is set to 1 This bit is automatically reset when AD conversion terminates The conversion time is defined using the ADTM2 bit 0 of the AD conversion results register low byte ADRLC and bits ADTMI bit 1 and bit 0 of the AD mode register ADMRC AD conversion stops when this bit is set to 0 Correct conversion results cannot be obtained if this bit is cleared during AD conversion processing This bit must never be cleared or the microcontroller must never be placed in the HALT or HOLD mode while AD conversion processing is in progress ADENDF bit 1 End of AD conversion flag This bit identifies the end of AD conversion It is set when AD conversion is finished Then an interrupt request to vector address 0043H is generated if ADIE is set to 1 If ADENDF is set to 0 it indicates that no AD conversion is in progress This flag must be cleared with an instruction ADIE bit 0 AD conversion interrupt request enable control An interrup
70. Select the appropriate detection level according to the user s operating conditions 3 release level option The POR release level can be selected out of 3 levels only when the LVD reset function is disabled When not using the internal reset circuit set the POR release level to the lowest level 2 87V Note3 No operating current flows when the POR reset state is released 4 16 LC872600 Chapter 4 e Selection example 1 Selecting the optimum LVD reset level to keep the microcontroller running without resetting it until VDD falls below 4 0V according to the set s requirements Set the LVD reset function option to Enable and select 3 79V as the LVD reset level Set operating range VDD 4 0V LVD release voltage LVDET LVHYS Sy Se Si SS LVD reset voltage LVDET Typ 3 79V e Selection example 2 Selecting the optimum LVD reset level that meets the guaranteed operating conditions of VDD 2 7V Tcyc 300ns Set the LVD reset function option to Enable and select 2 81V as the LVD reset level option Microcontroller guaranteed operating range VDD 2 7V to 5 5V tCYC 300ns release voltage LVDET LVHYS LVD reset voltage LVDET Typ 2 81V Operation guarantee voltage VDD 2 7V tCYC 300ns e Selection example 3 Disabling the internal reset circuit and using an external reset IC that can detect and react at 3 0V see also paragraph 1 of Subsection 4 5 7 Set the LVD reset fu
71. USH ADD BE 12H 1234H 34H 56 78H 11 Loads the accumulator with byte data 12H Loads the BA register pair with word data 1234H Loads the stack with byte data 34H Adds byte data 56H to the accumulator Compares byte data 78H with the accumulator for a branch 2 6 LC872600 Chapter 2 2 11 2 Indirect Register Indirect Addressing Rn In the indirect register indirect addressing mode it is possible to select one of the indirect registers RO to R63 and use its contents to designate an address in RAM or SFR When the selected register contains for example FE02H it designates the C register Example When R3 contains 123H RAM address 6 23H RAM address 7 01H LD R3 Transfers the contents of RAM address 123H to the accumulator Li STW R3 Transfers the contents of BA register pair to RAM address 123H PUSH R3 Saves the contents of RAM address123H in the stack SUB R3 Subtracts the contents of RAM address 123H from the accumulator DBZ R3 L1 Decrements the contents of RAM address 123H by 1 and causes a branch if Zero 2 11 3 Indirect Register Register Indirect Addressing Rn C In the indirect register C register indirect addressing mode the result of adding the contents of one of the indirect registers RO to R63 to the contents of the C register 128 to 127 with MSB being the sign bit designates an address in RAM or SFR For example if the selected indirect reg
72. XHR PWMCTOV Write signal register RLDBSY signal PWMCKR PWM1LR PWM2LR PWMXHR write inhibited Reload signal generator circuit PWMDSL PWMCTHR bits 2 0 PWMCTLR Figure 3 6 1 High speed 12 bit PWM Block Diagram P33 HPWM Period Period A A A A Start PWM operation Change DUTY period Reload buffer registers Set PWMOV flag Set RLDBSY flag Clear RLDBSY flag When a write to PWMXHR is Set PWMOV flag performed Figure 3 6 2 Sample Continuous Output Mode Waveform PWMINV 0 P33 HPWM Periodx Period count value 1 A A A Start PWM operation Set PWMCTOV flag Change Clear PWMCTOV flag Stop PWM operation DUTY period Resume PWM operation Figure 3 6 3 Sample Preset Value Output Auto Stop Mode Waveform PWMINV 0 3 38 LC872600 Chapter 3 3 6 4 Related Registers 3 6 4 1 HPWM control register PWMCNT 1 The HPWM control register controls the operation of and interrupts for the HPWM 2 Bit RLDBSY is read only PWMST bit 7 HPWM operation conirol Setting this bit to 0 stops the operation of the HPWM Setting this bit to 1 starts the operation of the HPWM Note that the HPWM stops operation when PWMST 1 and PWMCTOV and PWMDSL 1 PWMOE bit 6 HPWM output control Setting this bit to 0 disables the PWM signal to be output Setting this bit to enables the PWM signal to be output To have the PWM signal output from the P33 HPWM pin set PWMOE 1 P33DDR 1 P3D
73. a read bit This bit allows the application to read the ACMP output data If the ACMP output signal is selected as the input to the INTC external interrupt circuit and both edge interrupt is set this bit is read to identify rising or falling of the edge after interrupt generation CMPOTIV bit 0 ACMP output polarity control If this bit is set to 0 a high level output is generated when the levels of the input voltages to the ACMP are such that gt and a low level output is generated when lt If this bit is set to 1 a low level output is generated when the levels of the input voltages to the ACMP are such that gt and a high level output is generated when lt 3 10 4 2 Input signal select register IADSL 1 The input signal select register is a 6 bit register that controls the selection of the polarity of the P32 multiplexed pin outputs and other functions Address Initial value RW Name BIT7 BIT6 BITS BIT4 BIT2 BIT1 BITO FESF 00HH 0000 R W IADSL STOHCP STOLCP 2 NFSLI NFSLO STOIN STOHCP bit 7 Timer OH capture signal input port select STOLCP bit 6 Timer OL capture signal input port select NFSL1 bit2 Noise filter sampling clock select NFSLO bit 1 Noise filter sampling clock select STOIN bit 0 Timer 0 counter clock input port select See Section 3 2 Port 3 for the description of these bits P320TIV bit 3 P32 CMPO multiplexed pin out
74. al modules are Stopped HOLD mode resetting conditions INTA or INTB level interrupt request generated Interrupt request for INTC INTD INTE or INTF generated Resetting conditions established Note 1 HALT mode entry conditions PCON register FE07 bit 1 set to 0 and bit O to 1 Reset Medium speed RC oscillator started High speed RC oscillator Reset state cancellation conditions Lapse of predetermined time after reset entry conditions are released stopped All registers initialized Normal operating mode Start stop of oscillators programmable CPU and peripheral modules run normally HALT mode All oscillators retain the state established when the HALT mode is entered CPU stopped Peripheral modules keep running HALT mode release conditions Interrupt request accepted Note 2 Resetting conditions established Note 1 Note 1 The CPU enters the reset state when the resetting conditions are established Note 2 The CPU cannot return from the HALT mode since no interrupt request can be accepted unless its interrupt level is higher than the interrupt level that placed the CPU into the HALT or HOLD mode Interrupt level at which the CPU entered HALT or HOLD mode HALT mode Interrupt request level that can release No interrupt request present L level X level H level and L level X and H levels
75. an instruction SI7END bit 1 End of serial transmission flag 1 This bit is set at the end of serial transmission on the rising edge of the last clock involved in the transfer 2 This bit must be cleared with an instruction SI7IE bit 0 107 interrupt request enable control 1 When this bit and SI7END are set to 1 an interrupt request to vector address 0023H is generated 3 31 3 5 4 2 8107 data buffer SBUF7 1 5107 data buffer is an 8 bit buffer register that stores the 5107 serial transmission data 2 The data to be transmitted received is transferred from this serial buffer to the shift register at the beginning of transmission 3 In the reception mode the data in the shift register is transferred to the serial buffer at the end of serial transmission Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO FEF9 0000 0000 R W SBUF7 SBUF77 SBUF76 SBUF75 SBUF74 SBUF73 SBUF72 SBUF71 SBUF70 3 5 4 3 SIO7 baudrate generator register SBR7 1 5107 baudrate generator register is an 8 bit register that defines the baudrate of 5107 2 The baudrate is computed as follows TSBR7 SBR7 value 1 x 2 Tcyc SBR7 can take a value from 1 to 255 and the valid value range of TSBR7 is from 4 to The SBR7 value of OO H is disallowed Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEFA 0000 0000 R W SBR7 SBRG77 SB
76. and B register to store the results of computation during the execution of a multiplication or division instruction In addition during a C register offset indirect instruction the C register stores the offset data 128 to 127 to the contents of an indirect register The C register is allocated to address 2 of the internal data memory space and initialized to on a reset Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO 2 0000 0000 R W CREG CREG7 CREG6 CREGS CREG4 CREG3 CREG2 CREGI CREGO 2 8 Program Status Word PSW The program status word PSW is made up of flags that indicate the status of computation results a flag to access the 9th bit of RAM and a flag to designate the bank during the LDCW instruction The PSW is allocated to address FEO6H of the internal data memory space and initialized to on a reset Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE06 0000 0000 R W PSW CY AC PSWBS5 PSWB4 LDCBNK OV Pl PARITY CY bit 7 Carry flag CY is set to 1 when a carry occurs as the result of a computation and cleared to 0 when no carry occurs There are the following types of carries 1 resulting from an addition 2 Borrow resulting from a subtraction 3 Borrow resulting from a comparison 4 resulting from a rotation There are some instructions that do not affect this flag at all AC bit 6 Auxil
77. and P32 INTC P10 P12 when TOLONG timer 0 control register bit 5 is set to 0 External input detection signals from pins P31 INTB and P33 INTD P10 P12 when TOLONG timer 0 control register bit 5 is set to 1 2 Capture data Contents of timer counter 0 low byte TOL 3 3 3 9 Timer counter 0 capture register high byte TOCAH 8 bit register 1 Captureclock External input detection signals from pins P31 INTB P33 INTD 10 12 2 Capturedata Contents of timer counter 0 high byte TOH Table 3 3 1 Timer 0 TOH TOL Count Clocks Mode TOLONG TOLEXT Count Clock TOL Count Clock TOL Count Clock 0 0 0 TOPRR match signal TOPRR match signal 1 Pore neh signal External signal OOOO 3 ee 1 2 signa Prescaler Comparator TOCAL Capture TOL Clock Clear Match Comparator Match buffer 1ULGMP register flag set Reload TOLR 8 bit programmable timer with programmable prescaler lt lt ES LC872600 Chapter 3 Capture trigger Registers IABCR FE5Dh IADSL FE5Fh IEFCR FE4Ah and IEFSL FE4Bh need setting TOCAH Capture Clear Match buffer register IUHUMP flag set TOHR 8 bit programmable timer wit programmable prescaler Figure 3 3 1 Mode 0 Block Diagram TOLONG 0 TOLEXT 0 Toy es Prescaler plear Capt i trigger
78. appropriate external low pass filter RC which is appropriated to reject noise interferences or capacitors close to each analog input pin To preclude adverse coupling influences use a ground that is free of noise interferences as a guideline R approx 5kQ or less C 1000pF to 0 1 uF Do not lay analog signal lines close to in parallel with or in a crossed arrangement with digital pulse signal lines or signal lines in which large current changes can occur Shield both ends of analog signal lines with noise free ground shields Make sure that no digital pulses are applied to or generated out of pins adjacent to the analog input pin that is being subject to conversion Correct conversion results may not be obtained because of noise interferences if the state of port outputs is changing To minimize the adverse influences of noise interferences it is necessary to keep the line resistance across the power supply and the VDD pins of the microcontroller at minimum This should be kept in mind when designing an application circuit Adjust the I O voltage at each pin so that it falls within the voltage range between VDD and VSS 3 63 ADC12 10 obtain valid conversion data perform conversion operations on the input several times discard the maximum and minimum values of the conversion results and take an average of the remaining data 3 64 LC872600 Chapter 3 3 10 Analog Comparator ACMP 3 10 1 Overview This series
79. ariable duty cycle period Continuous PWM output mode or PWM set value output automatic stop mode selectable Functions High speed 12 bit PWM operation The 12 bit prescaler HPWPR performs count operation on either the system clock or high speed RC oscillation clock reference clock PWCK is selected from 2 clock sources When a match occurs between the count value in the HPWPR and the value that is defined by the prescaler buffer register PWMPBR a match signal is generated which serves as a clock signal and drives the 12 bit up counter HPWCT When a match occurs between the value in the HPWCT and the value that is defined by the DUTY buffer register PWMIBR the output latch HPWOLT is set And when a match occurs between the value in the HPWCT and the value that is defined by the period buffer register PWM2BR the HPWOLT is cleared and the HPWM period match flag PWMOV is set When the HPWM is active the buffer registers are reloaded at the time the next HPWM period match signal is generated after the HPWM DUTY period high byte register PWMXHR is loaded with write data In this case the contents of bits 3 to 0 of the reference clock register PWMCKR are reloaded into the PWMPBR the contents of the DUTY register PWMXHR bits 3 to 0 and PWMILR into the PWMIBR and the contents of the period register PWMXHR bits 7 to 4 and PWM2LR into the PWM2BR HPWM s DUTY cycle Period defined by PWMCKR x DUTY register value 1
80. arily with internal pull up resistors and port P30 is temporarily set low when the microcontroller is reset Do not apply a clock or intermediate level voltage to ports P32 and P33 while the reset sequence is in progress 3 2 2 Functions 1 TO port 4 bits P30 to P33 The port output data is controlled by the port 3 data latch P3 FEAC and the I O direction is controlled by the port 3 data direction register P3DDR FEAD Each port bit is provided with a programmable pull up resistor 2 Multiplexed pin function e P33 is also used as HPWM output P32 as the analog comparator output P31 as the HCT2 input and P30 as the HCT1 input 3 Interrupt input pin function e P30 and P31 are used as INTA and INTB respectively to detect L or level an L or H edge and set the corresponding interrupt flag e P32 and P33 are used as INTC and INTD respectively to detect L edge or both edges and set the corresponding interrupt flag 4 Timer 0 count input function A count signal is sent to the timer 0 each time a signal change that will set an interrupt flag is applied to one port selected out of P32 and P33 5 Timer OL capture input function timer OL capture signal is generated each time a signal change that will set an interrupt flag is applied to one port selected out of P30 and P32 If a signal with a selected level is applied to and held at pin P30 that is configured for level interrupts a tim
81. both POR and LVD functions are used RESET pin Pull up resistor Regs only LVD hysteresis width LVD release voltage LVHYS LVDET LVHYS LVD reset voltage LVDET D pong Exil Sete ei J PE Reset period Reset period Reset period te pent hy M gt e gt gt 1 ool Unknown state LVUKS There also exists an unknown state LVUKS before the POR transistor starts functioning normally when both POR and LVD functions are used Resets are generated both when power is turned on and when the power level lowers The reset release voltage and entry voltage in this case may have some range Refer to the latest SANYO Semiconductor Data sheet for details A hysteresis width LVHYS is provided to prevent the repetitions of reset release and entry cycles near the detection level 4 18 LC872600 Chapter 4 4 5 6 Notes on the Use of the Internal Reset Circuit 1 When generating resets only with the POR function When generating resets using only the POR function do not short the RESET pin directly to VDD as when using it with the LVD function Be sure to use the external capacitor of an appropriate capacitance Test the circuit completely under the anticipated power supply conditions to verify that resets are reliably generated Interior of microcontroller Rres RESET CRES 2
82. capture signal is generated when an input that will satisfy the INTC interrupt detection conditions is supplied to P32 P320TIV bit 3 P32 multiplexed output polarity control See Section 3 10 Analog Comparator for a description of this bit NFSL 1 bit 2 Noise filter sampling clock select NFSLO bit 1 Noise filter sampling clock select NFSL1 NFSLO Noise Filter Sampling Clock Noise filter function disabled STOIN bit 0 Timer 0 counter clock input port select Selects the port for the timer 0 counter clock signal input If this bit is set to 1 a timer count clock is generated when an input signal that will satisfy the INTD interrupt detection conditions is supplied to P33 If this bit is set to 0 a timer 0 count clock is generated when an input signal that will satisfy the INTC interrupt detection conditions is supplied to P32 Note The signal from port 3 is ignored if the timer OL capture signal input or timer OH capture signal input is assigned to both port 3 and INTE or INTF Note When using the INTC s HOLD mode release function turn off the noise filter function NFSLI NFSLO 0 0 3 2 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 2 5 HALT and HOLD Mode Operation When in the HALT or HOLD mode port 3 retains the I O state that is established when the HALT or HOLD mode is
83. cember 26 2009 ON Semiconductor Digital Solution Division Microcontroller amp Flash Business Unit
84. circuit capacitor Cggs discharging transistor external capacitor Cres internal pull up resistor Regs The circuit diagram of the internal reset circuit is given in Figure 4 5 1 Pulse stretcher circuit The pulse stretcher circuit stretches the POR and LVD reset signals It is used to stretch the internal reset period and discharge the external capacitor Cres connected to the RESET pin The stretching time is from 30ps to 100us Capacitor Cres discharging transistor This is an N channel transistor used to discharge the external capacitor Cggs connected to RESET pin If the capacitor Cres is not to be connected to the RESET pin it is possible to monitor the internal reset signal by only the internal pull up resistor Option selector circuit The option selector circuit is used to configure the LVD options This circuit selects Enable use or Disable disuse of LVD and its detection level See Subsection 4 5 4 External capacitor Cres Internal pull up resistor After the reset signal from the internal reset circuit is released the reset period is further stretched according to the external CR time constant This enables the microcontroller to avoid the repetitive entries and releases of the reset state from occurring when the power on chatter occurs The circuit configuration shown in Figure 4 5 1 using the external capacitor Crrs and internal pull up resistor Rrrs is recommended when both POR and LVD functions are
85. cumulator 2 byte instruction LDL 123H Transfers the contents of RAM address 123H to the accumulator 3 byte instruction Li STW 123H Transfers the contents of the BA register pair to RAM address 123H PUSH 123H Saves the contents of RAM address 123H in the stack SUB 123H Subtracts the contents of RAM address 123H from the accumulator DBZ 123H L1 Decrements the contents of RAM address 123H by 1 and causes a branch if zero 2 8 LC872600 Chapter 2 2 11 6 Table Look up Addressing The LC870000 series microcontrollers can read 2 byte data into the BA register pair at once using the LDCW instruction Three addressing modes Rn Rn C and off are available for this purpose In this case only Rn are configured as 17 bit registers 128K byte space For models with banked ROM it is possible to reference the ROM data in the ROM bank 128K bytes identified by the LDCBNK flag bit 3 in the PSW Consequently when looking into the ROM table on a series model with banked ROM execute the LDCW instruction after switching the bank using the SET1 or CLRI instruction so that the LDCBNK flag designates the ROM bank where the ROM table resides Examples TBL DB 34H DB 12H DW 5678H LDW TBL Loads the BA register pair with the TBL address CHGP3 TBL gt gt 17 amp 1 Loads LDCBNK in PSW with bit 17 of the TBL address Note 1 TBL gt gt 16 amp 1 Loads P1 in PSW with bit 16 of TBL address STW RO Loa
86. d indirect register RO with the TBL address bits 16 to 0 LDCW 1 Reads the ROM table B 78H ACC 12H MOV 1 C Loads C register with 01H LDCW RO C Reads the ROM table B 78H ACC 12H INC C Increments the C register by 1 LDCW _ RO Reads the ROM table B 56H ACC 78H Note 1 LDCBNK bit 3 of PSW need to be set up only for models with banked ROM 2 11 7 External Data Memory Addressing The LC870000 series microcontrollers can access external data memory spaces of up to 16M bytes 24 bits using the LDX and STX instructions To designate a 24 bit space specify the contents of the B register 8 bits as the highest order byte of the address and the contents 16 bits of Rn Rn C or RO off either one as the lower order bytes of the address Examples LDW 3456H Sets up the lower order 16 bits STW RO Loads the indirect register RO with the lower order 16 bits of the address 12H B Sets up the higher order 8 bits of the address LDX 1 Transfers the contents of external data memory address 123457H to the accumulator 2 9 Table 2 4 2 Instruction Chart of State Transitions of Bit 8 RAM SFR and P1 BIT8 RAM SFR P1 PSW BIT 1 Remarks LD LDW w rrentGHs 2 PICREGS PICREGHS pe REG8 RAMS 1 lt 8 POPW REGH8 REGL8 lt RAML8 PI RAMI GU PRAMS INC INC 9 bits P1 l
87. d state of the PC and interrupt level Multilevel interrupt control The interrupt function supports three levels of interrupts that is the low level L high level H and highest level X The interrupt function will not accept any interrupt requests of the same level or lower than that of the interrupt that is currently being processed Interrupt priority When interrupt requests to two or more vector addresses occur at the same time the interrupt request of the highest level takes precedence over the other interrupt requests Among the interrupt requests of the same level the one whose vector address is the smallest is prioritary Interrupt request enable control The master interrupt enable register IE can be used to control the enabling disabling of H and L level interrupt requests Interrupt requests of the X level cannot be disabled Interrupt disable period Interrupts are held disabled for a period of 2Tcyc after a write is made to the IE 8 or IP FEO9 register or the HOLD mode is reset No interrupt can occur during the interval between the execution of an instruction that loads the PCON 7 register and the execution of the next instruction No interrupt can occur during the interval between the execution of a RETI instruction and the execution of the next instruction Interrupt level control Interrupt levels can be selected on a vector address basis 4 Interrupt Table
88. d to manipulate bit 8 of 9 bit internal data RAM 0000H to Its behavior varies depending on the instruction executed See Table 2 4 2 for details PARITY bit 0 Parity flag This bit shows the parity of the accumulator A register The parity flag is set to 1 when there are an odd number of 1s in the A register It is cleared to 0 when there are an even number of 1s in the A register 2 9 Stack Pointer SP The LC870000 series microcontrollers can use RAM addresses 0000H to FDFFH as a stack area The size of RAM however varies depending on the model of the microcontroller The SP is 16 bits long and made up of two registers SPL at address FEOA and SPH at address It is initialized to OOOOH on a reset The SP is incremented by 1 before data is saved in stack memory and decremented by 1 after the data is restored from stack memory FEOA 0000 0000 R W SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SPO The value of the SP changes as follows 1 When the PUSH instruction is executed SP SP 1 RAM SP DATA 2 When the CALL instruction is executed SP SP 1 RAM SP ROMBANK ADL SP SP 1 RAM SP ADH 3 When the POP instruction is executed DATA RAM SP SP SP 1 4 When the RET instruction is executed ADH RAM SP SP SP 1 ROM BANK ADL RAM SP SP SP 1 2 10 Indirect Addressing Registers The LC870000 series microcontrollers are provided with three addressing schemes Rn Rn C
89. d voltage I O ports Ports whose I O direction can be designated in bit units 7 P10 to P12 P30 to P33 e Reset pin 1 RES e Power pins 2 VSS1 VDD1 Timers Timer 0 16 bit timer counter with capture registers Mode 0 8 bit timer with an 8 bit programmable prescaler with 8 bit capture registers x 2 channels Mode 1 8 bit timer with an 8 bit programmable prescaler with 8 bit capture registers 8 bit counter with 8 bit capture registers Mode 2 16 bit timer with an 8 bit programmable prescaler with 16 bit capture registers Mode 3 16 bit counter with 16 bit capture registers Timer 1 16 bit timer counter Mode 0 8 bit timer with an 8 bit prescaler 8 bit timer counter with an 8 bit prescaler Mode 2 16 bit timer counter with an 8 bit prescaler Serial interface 5107 8 bit synchronous serial interface 1 LSB first MSB first mode selectable 2 Built in 8 bit baudrate generator maximum transfer clock cycle 4 High speed 12 bits PWM System clock or high speed RC oscillator clock 20 MHz or 40 MHz selectable Programmable duty cycle and period Continuous PWM output or PWM set value output automatic stop selectable High speed pulse width period measurement counters e HCT1 High speed pulse width period measurement counter 1 1 System clock or high speed RC oscillator clock 20 MHz or 40 MHz selectable 2 High level width low level width or period measurement selectable 3 Input tr
90. data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when INTC or INTD data which is established when the HOLD mode is entered is in the low state Consequently to release the HOLD mode with INTC or INTD it is recommended that INTC or INTD be used in the both edge interrupt mode 8 INTC noise filter function The INTC has a noise filter stage before the interrupt detector circuit so that it is possible to detect interrupts using a filtered signal The HOLD mode release function however is disabled if the noise filter function is used The noise filter circuit samples the signal that is input to the INTC pin on the output clock from the input signal select register ADSL When a match in signal level occurs 4 consecutive times the noise filter circuit holds that signal level Otherwise the noise filter circuit retains the old signal level Noise or INTC input signal Filter clockx3 Filter clockx4 Address Initial value R W BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE4C HHHH 0000 R W P3 P33 P32 P31 P30 rep 0000 rw DDR f Psor PSIDDR P3ODDR INTBLH INTBLH rese 0000 ranse srorce jPs20TIV nesti NESLO 3 8 LC872600 Chapter 3 3 2 8 Related Registers 3 2 3 1 Port 3 data latch P3 1 The port 3 data latch is a 4 bit
91. ddress Initial value R W LC872600 Remarks BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BITI BITO FE40 ra ra ras Wero Pio 46 HHHH H000 R W P1FCR P12FCR P11FCR P10FCR 4 RS C URL dE I FEAA 0000 0000 R EF INTE INTF contro WIRES INTERES INTELEG FB 0000 0000 RA is KO Isi isto Fio esto Wero m M 0000 Pb 900 PS PSIDUR 200 a Fese 0000 0000 RA contre ADGHSELZ ADGHSELO 68S ADSTART ADENOF ADIE Fee 0000 0000 Rm AONE ama amos ADID2 ADIDO 0 0 FE5A 0000 0000 R W ADRLC 12bit AD conversion results DATAL3 DATAL2 DATAL1 DATALO ADRL3 ADRL2 ADRL1 ADTM2 un ea IER RENE 0 rae cede crue R W R W R W R W R W 0000 0000 R W eR INTG INTD contro INTOREG INTDLEG iWrbir irit INToHEG INTCIF res 0000 wA rost smi ston AI 2 LC872600 APPENDIX I Address Initial value R W 6872600 Remarks
92. ddress 0000BH to the X level XCNTO bit 0 00003H Interrupt level control flag e Alin this bit sets all interrupts to vector address 00003H to the L level e A in this bit sets all interrupts to vector address 00003H to the X level 4 3 Interrupt 4 1 4 2 Interrupt priority control register IP 1 The interrupt priority control register is an 8 bit register that selects the interrupt level H L of interrupts to vector addresses 00013H to 0004 BH Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE09 0000 0000 R W IP IP4B IP43 IP3B IP33 IP2B IP23 IP13 Interrupt Vector Address Interrupt Level L 0004BH 00043H E 0003BH IP3B DN UN M ro ES of INT E Da w 00023H IP23 efjo dh 3 0001BH IPIB EC SNNT NN Note This series does not have an interrupt source for interrupt vector address 0004BH IP4B bit 7 may be used as a general purpose flag myer myer 4 4 LC872600 Chapter 4 4 2 System Clock Generator Function 4 2 1 Overview This series of microcontroller incorporates two systems of oscillator circuits 1 high and medium speed RC oscillators as system clock generator circuits The high and medium speed RC oscillator circuits have built in resistors and capacitors so that no external circuit is required The system clock can be selected from these two types of clock s
93. direction register a function control register and a control circuit Control of the input output signal direction is accomplished by the data direction register on a bit basis Port 1 can also be used as a serial interface I O port by manipulating its function control register Port 1 can also serve as an input port for external interrupts It can also be used as an input port for the timer 1 count clock timer 0 capture signal or HOLD mode release signal As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type on a bit basis Note Port P10 is equipped temporarily with an internal pull up resistor when the microcontroller is 2 3 4 reset Do not apply a clock or intermediate level voltage to port P10 while the reset sequence is in progress Functions I O port 3 bits P10 to P12 The port output data is controlled by the port 1 data latch 1 FE44 and the I O direction is controlled by the port 1 data direction register PIDDR FE45 Each port bit is provided with a programmable pull up resistor Multiplexed pin function e P11 is also used as the HCT2 input and P12 to P10 for 5107 I O Interrupt input pin functions One port INTE selected out of ports P10 and P11 and the port P12 INTF are assigned the pin interrupt function They are used to sense the low high or both edges of an interru
94. ductor Data Sheet Note The WDTCNT is initialized with 00H when a low level signal is applied to the external RES pin or a reset is triggered by the internal reset POR LVD function Bits 4 to 0 of the WDTCNT are not initialized however when a WDT triggered reset occurs Note The WDTCNT is disabled for writes once the WDT is started WDTRUN set to I If the instruction MOV 55 WDTCNT is executed in this case the WDTCT is cleared and counting is restarted at a count value of 0 the WDTCT is not cleared when it is loaded with 55H with any other instruction Note The low speed RC oscillator circuit is started and stopped by setting bit WDTRUN WDTCNT bit 5 to 1 and 0 respectively Once the oscillator starts oscillation an operating current of several uA flows at all times For details refer to the latest SANYO Semiconductor Data Sheet 4 25 WDT 4 6 5 1 Notes Use of the Watchdog Timer When Hold operation is selected in the standby mode operation IDLOP1 IDLOPO 2 When the CPU is placed in a standby mode HALT HOLD after the watchdog timer 15 started with Hold operation selected the low speed RC oscillator circuit stops oscillation and the watchdog timer stops counting and retains the count value When the CPU subsequently exits the standby mode the low speed RC oscillator circuit resumes oscillation and the watchdog timer starts counting If the period between the release of the standby mode
95. easure HCICKSL HCIPRSL1 HCTPRSLO HCT1END ment counter 1 control nam RGTIRD4 otimos FE BGTIRIO HCTIROD Eug qe pure EE ee dE ed recs 0000 Hooo R W Pulse width period measure FIXO HC2CKSL HC2PRSL1 HC2PRSLO HCT2ST HCT2END HCT2IE ment counter 2 control R Wm RCTZIROS OTZIROA WOTZIROZ rp o xw GTAIRIS weno l LL sez Fes xu xe ek ROTZ2ROS HGT22805 HGT2280 WcTz2802 HCTZ2ROO TZ2RT2 oTz2RT0 Hcr2aRo9 orzznos rece 0000 RAV TRGSFTZ TRGSFTI TRGSFTO HOT2OV WOTZ2RTS Wcr2oRi7 HCTZ2RIG FECC 0000 0000 CMPCNT eras INTCINSL FIXO P320TSL1 CMPOUT P320TSLO CMPOTIV JE NN al rl FE
96. ed counting operation T1LONG bit 5 Timer 1 bit length select When this bit is set to 0 timer 15 higher and lower order bytes serve as independent 8 bit timers When this bit is set to 1 timer 1 serves as a 16 bit timer since the timer 1 high byte T1H counts up at the interval of the timer 1 low byte T1L Independent match signals are generated from and when their count value matches the contents of the corresponding match buffer register regardless of the value of this bit FIXO bit 4 Test bit This bit is used for testing only Must always be set to 0 T1HCMP bit 3 T1H match flag This flag is set if TIH reaches 0 when is active TIHRUN 1 This flag must be cleared with an instruction T1HIE bit 2 interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and TIHCMP are set to 1 T1LCMP bit 1 T1L match flag This flag is set if TIL reaches 0 when TIL is active TILRUN 1 This flag must be cleared with an instruction T1LIE bit 0 T1L interrupt request enable control An interrupt request is generated to vector address 002BH when this bit and TILCMP are set to 1 3 26 Note TIHCMP and TILCMP must be cleared to 0 with an instruction LC872600 Chapter 3 3 4 4 2 Timer 1 prescaler control regist
97. ee eee 4 22 4 6 4 Related Registers eee reer e eee etree rere tree reer ree etree reer ere eee eee eee eee 4 24 4 6 5 Notes on the Use of the Watchdog Timer 4 26 Appendixes A 87 Register Map enne nnne nnne nennen Al 1 4 1 Port Block Diagrams mmn All 1 4 Revision History LIII R 1 1 1 1 1 2 LC872600 Chapter 1 Overview Overview The SANYO LC872600 series is an 8 bit microcontroller that centered around a CPU running at a minimum bus cycle time of 100 ns integrate on a single chip a number of hardware features such as 8K bytes of flash ROM onboard programmable 512 bytes of RAM an on chip debugger two 16 bit timer counters may be divided into 8 bit timers a synchronous SIO interface a high speed 12 bit PWM module two high speed pulse width period measurement counters a 3 channel AD converter with a 12 8 bit resolution selector an analog comparator a watchdog timer an internal reset circuit a system clock frequency divider and 16 source 10 vector interrupt feature Features ROM LC872600 series LC87F2608A 8192 x 8 bits flash ROM Onboard programmable with wide range of supply voltages 3 0 to 5 5V e Block erasable in 128 byte units RAM LC872600 series LC87F2608A 512 x 9 bits Minimum bus cycle time e 100 ns 10 MHz Note The bus cycle time here refers to the ROM read speed Minimum instruction cycle time Tcyc e 300 ns 10 MHz 1 1 Ports Normal withstan
98. en connecting an external reset IC adopt the reset IC of a type whose detection level is not lower than the minimum guaranteed operating voltage level and select the lowest POR release level 2 87V The figures given below show sample reset circuit configurations that use reset ICs of Nch open drain and CMOS types respectively Reset IC Interior of microcontroller Several hundreds kQ N channel open drain type Rres RESET From POR Insert a protective resistor of several to scores of kQ to prevent through current Reset IC Interior of microcontroller CMOS type Rres RESET Figure 4 5 6 Sample Reset Circuit Configuration Using a CMOS Type Reset IC 4 20 2 LC872600 Chapter 4 When configuring the external POR circuit without using the internal reset circuit The internal POR is active at power on time even if the internal reset circuit is not used as in the case 1 in Subsection 4 5 7 When configuring an external POR circuit with a value of 0 luF or larger to obtain a longer reset period than with the internal POR however be sure to connect an external diode Dggs as shown in Figure 4 5 7 Interior of microcontroller Rres Dres RESET From POR Cres Connect an external diode Figure 4 5 7 Sample External POR Circuit Configuration 4 21 WDT 4 6 Watchdog Timer WDT 4 6 1 Overview This series of
99. er T1PRR 1 Thisregister sets up the count values for the timer 1 prescaler 2 When the register value is changed while the timer is running the change is reflected in the prescaler operation at the same timing when the match buffer register for the timer T1L T1H is updated Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FE19 0000 0000 R W TIHPRE TIHPRC2 TIHPRCI TILPRE TILPRC2 TILPRCI TILPRCO T1HPRE bit 7 Controls the timer 1 prescaler high byte T1HPRC2 bit 6 Controls the timer 1 prescaler high byte T1HPRC1 bit 5 Controls the timer 1 prescaler high byte T1HPRCO bit 4 Controls the timer 1 prescaler high byte T1HPRE T1HPRC2 1 T1HPRCO T1H Prescaler Count 0 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 T1LPRE bit 3 Controls the timer 1 prescaler low byte T1ILPRC2 bit 2 Controls the timer 1 prescaler low byte T1LPRC1 bit 1 Controls the timer 1 prescaler low byte T1LPRCO bit 0 Controls the timer 1 prescaler low byte TILPRE T1LPRC2 TILPRC1 T1LPRCO T1L Prescaler Count 0 1 1 0 0 0 2 1 0 0 1 4 1 0 1 0 8 1 0 1 1 16 1 1 0 0 32 1 1 0 1 64 1 1 1 0 128 1 1 1 1 256 3 4 43 Timer 1 low byte T1L 1 This is a read only 8 bit timer It counts up on every T1L prescaler output clock Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BITS BIT2 BIT1 BITO
100. er OL capture signal is generated every 1 Tcyc while the signal remains present at that pin 3 7 PORTS 6 Timer OH capture input function A timer capture signal is generated each time a signal change that will set an interrupt flag is applied to one port selected out of P31 and P33 If a signal with a selected level is applied to and held at pin P31 that is configured for level interrupts a timer OH capture signal is generated every 1 Tcyc while the signal remains present at that pin 7 HOLD mode release function When both of the interrupt flag and interrupt enable flag are set by INTA to INTD a HOLD mode release signal is generated causing the CPU to switch from HOLD mode to HALT mode system clock assigned to intermediate speed RC oscillation When the interrupt request is accepted the CPU switches from HALT mode to normal operating mode When a signal change such that an interrupt flag is set is input to level interrupt assigned INTA or INTB in the HOLD mode the interrupt flag is set In this case the CPU exits the HOLD mode if the corresponding interrupt enable flag is set When a signal change such that an interrupt flag is set is input to INTC noise filter function turned off or INTD in the HOLD mode the interrupt flag is set In this case the CPU exits the HOLD mode if the corresponding interrupt enable flag is set The interrupt flag however cannot be set by a rising edge occurring when INTC or INTD
101. er counter with an 8 bit prescaler A 16 bit programmable timer counter runs that counts the number of signals whose frequency is equal to that of the cycle clock divided by 2 or the number of external events Since interrupts can occur from the lower order 8 bit timer T1L at the interval of TIL period lower order 8 bits of this 16 bit programmable timer counter can be used as the reference timer TIL period TILR 1 x TILPRC count x 2Tcyc or TILR 1 x TILPRC count events detected period T1HR 1 x TIHPRC count x TIL period 3 Interrupt generation TIL interrupt request is generated at the counter period of the TIL or timer if the interrupt request enable bit is set 4 control timer counter 1 it is necessary to manipulate the following special function registers TICNT TIPRR TIL TIH TILR TIHR PI PIDDR IEFCR IEFSL Address Initial Value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE18 0000 0000 R W TICNT TIHRUN TILRUN TILONG FIXO TILCMP FE19 0000 0000 R W TIPRR TIHPRE TIHPRC2 TIHPRCI TILPRE TILPRC2 TILPRCI TILPRCO 0000 0000 R TIL TIL7 T1L6 TILS TIL2 TILI TILO FEIB 0000 0000 R T1H7 T1H6 T1H5 T1H4 T1H3 T1H2 T1HO FEIC 0000 0000 R W TILR TILR7 TILR6 TILRS TILR4 TILR3 TILR2 TILRI TILRO FEID 0000 0000 R W TIHR TIHRT7 TIH
102. ess 003BH is generated 4 To control the high speed pulse width period measurement counter 2 HCT2 it is necessary to manipulate the following special function registers HCT2CNT HCT21LR HCT21MR HCT21HR HCT22LR HCT22MR HCT22HR CMPCNT e PI PIDDR P3 PSDDR Address Initial value R W Name BIT7 BIT6 5 BIT4 BIT3 BIT2 BIT1 BITO 5 0000 H000 R W HCT2CNT FIXO HC2CKSL HC2PRSLI1 HC2PRSLO HCT2ST HCT2END HCT2IE recs r nerie rican ncrioe cromos ncraisos acra rec roms acram creen acram ncrz os recs mmn mox esaerari rcs uera reca 3 8 3 Circuit Configuration 3 8 3 1 HCT2 control register HCT2CNT 7 bit register 1 The HCT2 control register is used to select the HC2CK to select the frequency division ratio for the HCT2PR and to control the operation and interrupts of HCT2 Note Setting bits 7 to 4 of the HCT2CNT while HCT2 is active HCT2ST 1 is inhibited 3 8 3 2 2 capture low byte register HCT21LR 8 bit register 1 The HCT2 capture low byte
103. flag This bit is set if a match signal is generated as the result of the HPWCT count value matching the PWNGBR value when PWMST is set to 1 This flag must be cleared with an instruction PWMIE bit 0 HPWM period interrupt request enable control When this bit and PWMOV are set to 1 an interrupt request to vector address 0043H is generated 3 6 4 2 HPWM reference clock register PWMCKR 1 The HPWM reference clock register is used to select the PWCK and define the count value to be stored in the HPWPR Address Initial value RAW Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEA1 HHHO 0000 R W PWMCKR 2 z PWCKSL PWPRSL3 PWPRSL2 PWPRSLI PWPRSLO PWCKSL bit 4 HPWM reference clock PWCK select PWCKSL Reference Clock PWCK 0 High speed RC oscillation clock PWPRSL3 bit 3 PWPRSL2 bit 2 PWPRSLU IC ee control PWPRSLO bit 0 Se CENE ES CEA ceed _ Note Setting PWCKSL is disabled while PWMST is set to 1 The HPWPR holds a count value of 4096 when PWPRSL3 to PWPRSLO are set to a value between 1101 and 1111 3 40 LC872600 Chapter 3 3 6 4 3 HPWM DUTY low byte register PWM1LR 1 This register and bits 3 to 0 of are used to define the duty cycle of the HPWM Address Initial value m 3 6 4 4 HPWM period low byte register PWM2LR 1 This register and bits 7 to 4 of the PWMXHR are used to define the period of the HPWM
104. flow WDTSL2 0 set count value WDTCT Count value 0 Time set in WDTSL2 0 A WDT operation start MOV 55H WDTCNT WDT reset signal generated WDTRUN 1 instruction executed WDTRUN cleared to 0 Low speed RC WDTCT cleared to 0 RSTFLG set to 1 oscillator start Low speed RC oscillator stopped Operation performed when IDLOP1 0 are set to 1 operation stopped Standby mode entered V WDTSL2 0 set count value WDTCT Count value 0 WDT operation start WDTRUN cleared to 0 WDTRUN 1 Low speed RC Low speed RC oscillator stopped oscillator start Operation performed when IDLOP1 0 are set to 2 operation held Standby mode entered Standby mode exited Overflow Low speed RC oscillator Low speed RC oscillator Vv stopped WDTSL2 0 set count value WDTCT Count value 0 Time set in WDTSL2 0 Standby mode time WDT operation start WDT reset signal generated WDTRUN 1 WDTRUN cleared to 0 Low speed RC RSTFLG set to 1 oscillator start Low speed RC oscillator stopped Figure 4 6 2 Sample Watchdog Timer Operation Waveforms 4 6 4 Related Registers 4 6 4 1 WDT control register WDTCNT 1 The WDT control register is used to manipulate the reset detection flag to select the standby mode operation to select the overflow time and to control the operation of the WDT Address Initial value BIT4 BIT3 BIT2 BITO FE79 0000 0000 R W WDTCNT RSTFLG IDLOP1 IDLOPO WDTSL2 WDTSLI WDTSLO RSTFLG bit 7
105. iary carry flag AC is set to 1 when a carry or borrow occurs in bit 3 bit 3 of the higher order byte during a 16 bit computation as the result of an addition or subtraction and cleared to 0 otherwise There are some instructions that do not affect this flag at all PSWB5 PSWBA bits 5 and 4 User bits These bits can be read and written through instructions They can be used by the user freely LDCBNK bit 3 Bank flag for the table lookup instruction LDCW This bit designates the ROM bank to be specified when reading the program ROM with a table lookup instruction 0 ROM ADR 0 to IFFFF 1 ROM ADR 20000 to 3FFFF OV bit 2 Overflow flag OV is set to 1 when an overflow occurs as the result of an arithmetic operation and cleared to 0 otherwise An overflow occurs in the following cases 1 When MSB is used as the sign bit and when the result of negative number negative number or negative number positive number is a positive 2 When MSB is used as the sign bit and when the result of positive number positive number or positive number negative number is a negative number LC872600 Chapter 2 3 When the higher order 8 bits of a 16 bits x 8 bits multiplication is nonzero 4 When the higher order 16 bits of a 24 bits x 16 bits multiplication is nonzero 5 When the divisor of a division is 0 There are some instructions that do not affect this flag at all P1 bit 1 RAM bit 8 data flag is use
106. iggering noise filter function e HCT2 High speed pulse width period measurement counter 2 1 System clock or high speed RC oscillator clock 20 MHz or 40 MHz selectable 2 measure the low level width and period at the same time 3 Input triggering noise filter function 4 Input trigger selectable from P11 HCT2IN P31 HCT2IN and analog comparator output AD converter 12 bits x 3 channels 12 8 bits AD converter resolution selectable Analog comparator Canoutput data to the P32 CMPO port output polarity selectable Edge detection function multiplexed with INTC noise filter feature selectable 1 2 LC872600 Chapter 1 Watchdog timer Can generate an internal reset signal on an overflow of a timer that runs on the WDT dedicated low speed RC oscillator clock 30 kHz Continuation termination or holding mode is selectable as the watchdog timer operating when the CPU enters the HALT or HOLD mode Interrupts 16 sources 10 vector addresses 1 Provides three levels low L high H and highest X of multiplex interrupt control Any interrupt requests of the level equal to or lower than the current interrupt are not accepted 2 When interrupt requests to two or more vector addresses occur at the same time the interrupt of the highest level takes precedence over the other interrupts For interrupts of the same level the interrupt into the smallest vector address takes precedence Vector Addres
107. input or timer OH capture signal input signals from both pins are accepted If the INTE and INTF events occur at the same time they are regarded as a single event 3 If at least one of INTE and INTF is assigned to timer I count clock input the timer IL servers as an event counter If timer 1 count clock input is assigned to none of INTE and INTF the timer 1L counts every 2 Tcyc 3 5 PORTS 3 1 4 Options Two user options are available 1 CMOS output with a programmable pull up resistor 2 N channel open drain output with a programmable pull up resistor 3 1 5 HALT and HOLD Mode Operation When in the HALT HOLD mode port 1 retains the state that is established when the HALT or HOLD mode is entered 3 6 LC872600 Chapter 3 3 2 Port3 3 2 1 Overview Port 3 is a 4 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data direction register and a control circuit Control of the input output signal direction is accomplished by the data direction register on a bit basis Port 3 can serve as an input port for external interrupts It can also be used as an input port for the timer 0 count clock timer 0 capture signal or HOLD mode release signal As a user option either CMOS output with a programmable pull up resistor or N channel open drain output with a programmable pull up resistor can be selected as the output type on a bit basis Note Ports P32 and P33 are equipped tempor
108. ion control bit ADSTART is reset The end of conversion condition can be identified by monitoring ADENDF An interrupt request to vector address 0043H is generated by setting ADIE The conversion time is doubled in the following cases The AD conversion is carried out in the 12 bit AD conversion mode for the first time after a system reset The AD conversion is carried out for the first time after the AD conversion mode is switched from 8 bit to 12 bit AD conversion mode The conversion time determined by the formula given in the paragraph entitled How to calculate the conversion time is taken in the second and subsequent conversions or in the AD conversions that are carried out in the 8 bit AD conversion mode The conversion results data contains some errors quantization error combination error Be sure to use only valid conversion results while referring to the latest SANYO Semiconductor Data Sheet Make sure that only input voltages that fall within the specified range are supplied to pins P10 ANO to P12 AN2 Application of a voltage greater than VDD or lower than VSS to an input pin may exert adverse influences on the converted value of the channel in question or other channels Take the following measures to prevent reduction in conversion accuracy due to noise interferences Add external bypass capacitors of several uF and thousands pF near the VDD1 and VSSI pins as close as possible 5 mm or less is desirable Add an
109. is set to 1 the OR of the SIO7 output data and the port data latch data is placed at pin P11 If SIO7 is active SIO7 input data is taken in from pin P11 regardless of the I O mode of P11 P10FCR bit 0 P10 function control SIO7 data output control This bit controls the output data at pin P10 When bit P10 is placed in the output mode PIODDR 1 and P10FCR is set to 1 the OR of the SIO7 output data and the port data latch data is placed at pin P10 3 3 PORTS 3 1 34 External interrupt E F control register IEFCR 1 The external interrupt E F control register is an 8 bit register that controls external interrupts E and Address Initial value INTFHEG INTFHEG bit 7 INTF rising edge detection control INTFLEG bit 6 INTF falling edge detection control INTFHEG INTFLEG INTF Interrupt Conditions Pin Data No edge detected Falling edge detected Rising edge detected Both edges detected INTFIF bit 5 INTF interrupt source flag This bit is set when the conditions specified by INTFHEG and INTFLEG are satisfied When this bit and the INTF interrupt request enable bit INTFIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 001BH are generated The interrupt flag however cannot be set by a rising edge occurring when INTF data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when INTF data which is establi
110. ister contains FE02H and the C register contains 1 the address B register FE02H 1 FEO1H is designated Examples When R3 contains 123H and the C register contains 02H LD R3 C Transfers the contents of RAM address 125H to the accumulator 11 STW R3 C Transfers the contents of the BA register pair to RAM address 125H PUSH R3 C Saves the contents of 125H in the stack SUB R3 C Subtracts the contents of RAM address 125H from the accumulator DBZ R3 CL L1 Decrements the contents of RAM address 125H by 1 and causes a branch if Zero Notes on this addressing mode The internal data memory space is divided into three closed functional areas as explained in Section 2 1 namely 1 system reserved area FF00H to FFFFH 2 SFR area FEOOH to FEFFH and 3 RAM stack area 0000H to FDFFH Consequently it is disallowed to point to a different area using the value of the C register from the basic area designated by the contents of Rn For example if the instruction LD R5 C is executed when R5 contains OFDFFH and the C register contains 1 since the basic area is 3 RAM stack area 0000H to FDFFH the intended address OFDFFH 1 OFEOOH lies outside the basic area and OFFH is consequently placed in the ACC If the instruction LD R5 C is executed when 5 contains OFEFFH and register contains 2 since the basic area is 2 SFR area to FEFFH the intended address
111. it 0 is automatically set when PDN is set IDLE bit 0 HALT mode setting 1 Setting this bit places the microcontroller into the HALT mode 2 This bit is automatically set whenever PDN bit 1 is set 3 This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal 4 7 System Clock 4 2 4 2 Oscillation Control Register OCR 7 bit register 1 oscillation control register is a 7 bit register that controls the operation of the oscillator circuits and selects the system clock Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FEOE 0000 000H R W CLKSGL HRCON CLKCB5 FIXO FIXO FIXO RCSTOP CLKSGL bit 7 Clock division ratio select 1 2 When this bit is set to 1 the clock selected by CLKCBS bit 5 is used as the system clock as is When this bit is set to 0 the clock having a clock rate of i of the clock selected by CLKCBS5 bit 5 is used as the system clock HRCON bit 6 Internal high speed RC oscillator circuit control 1 2 3 4 Setting this bit to 1 starts the oscillation of the internal high speed RC oscillator circuit Setting this bit to O stops the oscillation of the internal high speed RC oscillator circuit When 20 MHz is chosen for the source clock frequency by configuring options i of the clock is supplied to the system clock selector When 40 MHz is chosen for the source clock frequency by configuring
112. ler Programmable prescaler 8 bit counter Start stop Count clock Match signal Reset This register runs in modes other than the HOLD mode Cycle clock period 1 Tcyc A match signal is generated when the count value matches the value of register TOPRR period 1 to 256 Tcyc The counter starts counting from 0 when a match signal occurs or when data is written into TOPRR Timer counter 0 low byte TOL 8 bit counter Start stop Count clock Match signal Reset This counter is started and stopped by the 0 1 value of TOLRUN timer 0 control register bit 6 Either prescaler s match signal or external signal must be selected through the 0 1 value of TOLEXT timer 0 control register bit 4 A match signal is generated when the count value matches the value of the match buffer register 16 bits of data need to match in the 16 bit mode This counter is reset when it stops operation or a match signal is generated Timer counter 0 high byte 8 bit counter Start stop Count clock Match signal Reset This counter is started and stopped by the 0 1 value of TOHRUN timer 0 control register bit 7 Either prescaler s match signal or TOL match signal must be selected through the 0 1 value of TOLONG timer 0 control register bit 5 A match signal is generated when the count value matches the value of the match buffer register 16 bits of data need to match in the 16 bit mode This co
113. microcontrollers is provided with a watchdog timer WDT that has the following features 1 Generates an internal reset on an overflow of a timer that runs on a WDT dedicated low speed RC oscillation clock 2 The continuation termination or holding count value of operation on entry into the standby mode is programmable 4 6 2 Functions 1 Watchdog timer function The 16 bit up counter WDTCT runs on a low speed RC oscillation clock and generates a WDT reset signal internal reset signal when it reaches the count equivalent to the overflow time one selected out of 8 levels selected through the watchdog time control register WDTCNT Then the reset detection flag RSTFLG is set Since the WDTCT is cleared under program control it is necessary to code the program so that the WDTCT be cleared periodically Since the WDT used in this series of microcontrollers uses a dedicated low speed RC oscillator the system continues operation even when the system clock is stopped due to a program hangup making it possible to detect any system runaway conditions The WDT operation mode on entry into the standby mode can be selected from three modes i e continuation of operation termination of operation and holding of WDTCT count value and resume WDT operation at the holding count value when the standby mode is exited In the continuation of operation mode the low speed RC oscillator circuit continues oscillation even i
114. mode with INTD it is recommended that INTD be used in the both edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically 3 10 LC872600 Chapter 3 INTDIE bit 4 INTD interrupt request enable When this bit and INTDIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 001BH are generated INTCHEG bit 3 INTC rising edge detection control INTCLEG bit 2 INTC falling edge detection control INTCHEG INTCLEG INTC Interrupt Conditions Pin Data No edge detected Falling edge detected 0 0 epe INTCIF bit 1 INTC interrupt source flag This bit is set when the conditions specified by INTCHEG and INTCLEG are satisfied When this bit and the INTC interrupt request enable bit INTCIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated The interrupt flag however cannot be set by a rising edge occurring when INTC data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when INTC data which is established when the HOLD mode is entered is in the low state Consequently to reset the HOLD mode with INTC it is recommended that INTC be used in the double edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INTCIE bit 0 INTC interrupt request enable When this bit and INTCI
115. must always be set to 0 ADMD1 bit 4 Fixed bit This bit must always be set to 0 bit 3 Fixed bit This bit must always be set to 0 ADMR2 bit 2 Fixed bit This bit must always be set to 0 ADTM1 bit 1 bit 0 These bits and bit 0 ADTM2 of the AD conversion results register low byte define the conversion time AD conversion time control ADRLC ADMRC Register TP Register Frequency Division Ratio 0 0 0 1 1 lt How to calculate the conversion time gt 12 bit AD conversion mode Conversion time 52 division ratio 2 x 1 3 x e 8 AD conversion mode Conversion time 32 division ratio 2 x 1 3 x 3 60 LC872600 Chapter 3 Notes The conversion time is doubled in the following cases 1 The AD conversion is carried out in the 12 bit AD conversion mode for the first time after a system reset 2 The AD conversion is carried out for the first time after the AD conversion mode is switched from 6 bit to 12 bit AD conversion mode The conversion time determined by the above formula is taken in the second and subsequent conversions or in the AD conversions that are carried out in the 8 bit AD conversion mode 3 9 4 3 AD conversion results register low byte ADRLC 1 The AD conversion results register low byte is used to hold the lower order 4 bits of the results of an AD conversion carried out in the 12 bit AD conversion mode and
116. n the standby mode allowing an operating current of several pA to flow at all times For details refer to the latest SANYO Semiconductor Data Sheet 2 To control the watchdog timer WDT it is necessary to manipulate the following special function register WDTCNT Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE79 00000000 R W WDTCNT RSTFLG WDTRUN IDLOP1 IDLOPO WDTSL2 WDTSL1 WDTSLO 4 6 3 Circuit Configuration 4 6 3 1 control register WDTCNT 8 bit register 1 The WDT control register is used to manipulate the reset detection flag to select operations in the standby time mode to select the overflow time and to control the operation of WDT Note The WDTCNT is initialized with 00H when a low level signal is applied to the external RES pin or a reset is triggered by the internal reset POR LVD function Bits 4 to 0 of the WDTCNT are not initialized however when a WDT triggered reset occurs Note The WDTCNT is disabled for writes once the WDT is started WDTRUN set to 1 If the instruction MOV 55H WDTCNT is executed in this case the WDTCT is cleared and counting is restarted at a count value of 0 the WDTCT is not cleared when it is loaded with 55H with any other instruction 4 22 LC872600 Chapter 4 Note The low speed RC oscillator circuit is started and stopped by setting bit WDTRUN WDTCNT bit 5 to 1 and 0 respectively Once the oscillator
117. nal and an interrupt request to vector address 0003H are generated This bit must be cleared with an instruction as it is not cleared automatically INTAIE bit 0 INTA interrupt request enable When this bit and INTAIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 0003H are generated 3 2 34 External interrupt C D control register ICDCR 1 Theexternal interrupt C D control register is an 8 bit register used to control external interrupts C and D FESE 0000 0000 R W ICDCR INTDHEG INTDLEG INTDIF INTDIE INTCHEG INTCLEG INTCIF INTCIE INTDHEG bit 7 INTD rising edge detection control INTDLEG bit 6 INTD falling edge detection control INTDHEG INTDLEG INTD Interrupt Conditions Pin Data No edge detected Falling edge detected 0 0 a 1 O INTDIF bit 5 INTD interrupt source flag This bit is set when the conditions specified by INTDHEG and INTDLEG are satisfied When this bit and the INTD interrupt request enable bit INTDIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 001BH are generated The interrupt flag however cannot be set by a rising edge occurring when INTD data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when INTD data which is established when the HOLD mode is entered is in the low state Consequently to reset the HOLD
118. nction option to Disable and select 2 87V as the POR release level option Set operating range VDD 3 1V External 3 0V detection circuit 0 66 66 POR release voltage PORRL Typ 2 87V Note4 The operation guarantee values voltage operating frequency shown in the examples vary with the microcontroller type Refer to the latest SANYO Semiconductor Data sheet 4 17 Internal reset 4 5 5 Sample Operating Waveforms of the Internal Reset Circuit 1 Waveform observed when only POR is used LVD not used RESET pin Pull up resistor Rggs only POR release voltage PORRL Reset gt Unknown state POUKS RES There exists an unknown state POUKS before the POR transistor starts functioning normally The POR function generates a reset only when power is turned on starting at the VSS level The reset release voltage in this case may have some range Refer to the latest SANYO Semiconductor Data sheet for details No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in a If such a case is anticipated use the LVD function together with the POR function as explained in 2 or implement an external reset circuit A reset is generated only when the power level goes down to the VSS level as shown in b and power is turned on again after this condition continues for 10015 or longer 2 Waveform observed when
119. nt start condition is detected the 19 bit up counter HCT2CT starts count operation When the L level width measurement end condition is subsequently encountered the value of the HCT2CT is captured into the L level width capture registers HCT21HR HCT21MR and HCT21LR When the period measurement end condition is detected the HCT2CT stops counting and holds the count value At this moment the end of measurement flag HCT2END is set HCT2 measurement period L level width Period defined by bits 6 to 4 of HCT2CNT x HCT21HR HCT21MR and HCT21LR value 19 bits HCT2 measurement period period Period defined by bits 6 to 4 4of HCT2CNT HCT22HR bits 2 to 0 HCT21MR HCT21LR value 19 bits Input triggering noise filter function The HCT2 has a noise filter stage before the edge detector circuit This circuit supplies the filtered signal to the edge detector circuit The noise filter circuit samples the HCT2 input trigger signal on the output clock from the HCT2PR When a match in signal level occurs 6 consecutive times the noise filter circuit holds that signal level Otherwise the noise filter circuit retains the old signal level Noise or Noise HCT2 trigger HCT2 trigger signal signal A A Filter clockx5 Filter clockx6 3 48 LC872600 Chapter 3 3 Interrupt generation If an interrupt request is generated from the HCT2 while the interrupt request enable bit is set an interrupt request to vector addr
120. nt start conditions 1 and 2 are detected after HCT2ST is set to 1 HCT2ST 0 Enabled in modes other than HOLD See Figure 3 8 2 for details Count clock Output clock from HCT2PR Overflow occurrence Set signal generated to HCT20V Resetting Reset immediately after HCT2ST is set to 1 HCT2OV is reset at the same time 3 50 LC872600 Chapter 3 3 8 3 10 HCT2 trigger shift counter TRGSFTCT 8 bit counter 1 TRGSFTCT starts operation on the output clock from the HCT2PR if an edge of the HCT2 input trigger signal is detected while HCT2ST is set to 1 and not all of bits TRGSFT2 to TRGSFTO HCT22HR bits 6 to 4 are set to 0 When the TRGSFTCT reaches the count value defined by bits TRGSFT2 to TRGSFTO it generates a clock output by which the signal output through the noise filter is sampled The TRGSFTCT is then cleared and stops operation until the next edge of the HCT2 input trigger signal is detected any HCT2 input trigger signal edges detected while the TRGSFTCT is active are ignored This feature serves primarily as a noise filter that is used when switching the analog comparator outputs see Figure 3 8 3 for details HCT2INSL CMPCNT bit 7 Set TRGSFT2 0 P11 HCT2IN to nonzero value HCT2ST Edge counter Edge selector P31 HCT2IN Edge detector circuit 1 Noise filter circuit HCT2END set signal HCT2ST clear signal Comparator output D TRGSL
121. odel 8 bit programmable timer with a programmable prescaler equipped with an 8 bit capture register 8 bit programmable counter equipped with an 8 bit capture register TOL serves as an 8 bit programmable counter that counts the number of external input detection signals from pins P32 INTC and P33 INTD TOH serves as an 8 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL are captured into the capture register TOCAL on external input detection signals from P30 INTA P32 INTC P10 P12 timer OL capture input pins The contents of TOH are captured into the capture register TOCAH on external input detection signals from P31 INTB P33 INTD P10 P12 timer 0H capture input pins TOL period TOLR 1 TOH period TOHR 1 x TOPRR 1 x Tcyc 3 2 16 bit programmable timer with a programmable prescaler equipped with a 16 bit capture register n this mode timer counter serves as a 16 bit programmable timer that runs on the clock with a period of 1 to 256 Tcyc from an 8 bit programmable prescaler The contents of TOL and TOH are captured into the capture registers TOCAL and TOCAH at the same time on external input detection signals from P31 INTB P33 INTD P10 P12 timer 0H capture input pins TO period TOHR TOLR 1 x TOPRR 1 x Tcyc 16 bits 4 Mode3 16 bit programmable counter equipped with a 16 bit capture regi
122. of HCT1 measurement interrupt request enable control When this bit and HCTIEND are set to 1 an interrupt request to vector address 0033H is generated 3 46 LC872600 Chapter 3 Note Writing bits 7 to 4 of the HCTICNT while the HCT1 is active to set to nonzero value is inhibited 3 7 4 2 HCT1 measurement counter low byte register HCT1LR 1 The measurement counter low byte register is a register to read out the lower order 8 bits of HCTICT data 2 Thisregister is read only Lc r nerie nero nerro nerro nerie cri 3 7 4 8 HCT1 measurement counter high byte register HCT1HR 1 This HCT1 measurement counter high byte register is a register to read out the HCTICT overflow detection flag and the higher order 7 bits of the HCTICT data 2 Thisregister is read only Address Initial value RW Name 7 Bre 5 BITO FEC2 1 12 HCTIR11 HCTIRIO HCTIRO HCTIRO8 bit 7 1 overflow detection flag This bit is set when the HCT1CT detects an overflow condition while the HCT1 is active neither are set to 0 In such a case read this bit after the measurement ends to verify that the measurement is successful HCT1 measurement period Pe
123. of Interrupts Vector Selectable Address Level 00003H XorL 1 00013 INTC TOL INTE Interrupt Sources wem tein 1 wem Her mm s period Priority levels X gt H gt L Of interrupts of the same level the one with the smallest vector address takes precedence 7 enable interrupts and to specify their priority it is necessary to manipulate the following special function registers JE IP Initial value BIT2 BIT1 BITO 0000 XCNTI XCNTO Es Paw me me m P23 PIB 4 1 3 Circuit Configuration 4 1 3 1 Master interrupt enable control register IE 6 bit register 1 master interrupt enable control registers enables and disables H and L level interrupts 2 The interrupt level flag of the register can be read 3 Theregister selects the level L or X of interrupts to vector addresses 00003H and 0000BH 4 1 3 2 Interrupt priority control register IP 8 bit register 1 The interrupt priority control register selects the level H or L of interrupts to vector addresses 00013H to 0004BH 4 2 LC872600 Chapter 4 4 1 4 Related Registers 4 1 4 1 Master interrupt enable control register IE 1 The master interrupt enable control register is a 6 bit register for controlling the interrupts Bits 6 to 4 of this register are read only Address Initial
124. options i of the clock is supplied to the system clock selector Note As oscillation is unstable immediately after oscillation starts the system requires the oscillation stabilization wait time For details refer to the latest SANYO Semiconductor Data Sheet CLKCBB5 bit 5 System clock select D 2 CLKCBS is used to select the system clock CLKCBS is automatically cleared at reset time or when the HOLD mode is entered CLKCB5 System clock 0 Internal medium speed RC oscillator 1 Internal high speed RC oscillator FIXO bits 4 3 2 Test bits These bits must always be set to 0 RCSTOP bit 1 Internal medium speed RC oscillator control 1 2 3 Setting this bit to 1 stops the oscillation of the internal medium speed RC oscillator circuit Setting this bit to O starts the oscillation of the internal medium speed RC oscillator circuit When a reset occurs or the HOLD mode is entered this bit is cleared and the internal RC oscillator circuit is enabled for oscillation bit 0 This bit does not exist 1 is always read when this bit is read 4 8 LC872600 Chapter 4 4 2 4 3 System clock divider control register CLKDIV 3 bit register 1 The system clock divider control register is a 3 bit register that controls the frequency division processing of the system clock Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEOC HHHH H000 R W CLKDIV CLKDV2
125. ources under program control 4 2 2 Functions 1 System clock select Allows the system clock to be selected under program control from two types of the clock generated by high speed RC oscillator and medium speed RC oscillator 2 System clock frequency division Divides frequency of the oscillator clock selected as the system clock and supplies the resultant clock to the system as the system clock The frequency divider circuit is made up of two stages 1 The first stage allows selection of division ratios of i and 1 TR 1 The second stage allows the selection of division ratios of uc E and 64 128 3 Oscillator circuit control Allows the start stop control of the two systems of oscillators to be executed independently through microcontroller instructions 4 Oscillator circuit states and operating modes Medium Mode Clock speed RC Oscillator speed RC Oscillator Pigh System Clock Running Normal operation HALT HOLD Stopped Medium speed RC oscillator Programmable Programmable Programmable State established at entry State established at entry State established at entry time time time Stopped Stopped Stopped Immediately after exit from State established at entry Note See Section 4 3 Standby Function for the procedures to enter and exit the microcontroller operating modes e HOLD mode All oscillators stopped Since
126. p to automatic stop HPWM period x PWMCTHR bits 2 to 0 and PWMCTLR 1 11 bits Note Setting PWMDSL is inhibited if PWMST is set to 1 Writing data into bits 2 to 0 of the PWMCTHR and the PWMCTLR is inhibited if PWMST is set to 1 If both PWMDSL and PWMCTOV are set to 1 however the HPWM stops operation and enables bits 2 to 0 of the PWMCTHR and the PWMCTLR to be written When rewriting bits 2 to of the PWMCTHR or the PWMCTLR after the HPWM is automatically stopped do so after making sure that PWMCTOV is set to that an HPWM period count interrupt has occurred To resume the set value output mode processing after the HPWM is automatically stopped it is necessary to clear PWMCTOV to 0 3 42 3 7 3 7 1 LC872600 Chapter 3 High speed Pulse Width Period Measurement Counter 1 HCT1 Overview This series of microcontrollers is provided with a high speed pulse width period measurement counter 1 HCT1 that has the following features 1 2 3 3 7 2 2 3 4 System clock high speed RC oscillation clock 20 MHz or 40 MHz selectable High level width low level width and period measurements selectable Input trigger noise filter function Functions High speed pulse width period measurement counter function A 3 bit prescaler runs on the system clock or high speed RC oscillation clock reference clock HCICK selected from 2 clock sources and generates a clock whose frequency di
127. pective operations are performed 2 1 Table 2 2 1 Values Loaded in the PC Operation PC value BNK value 00000H mm imm ws 9 Imwpmwm eem mum wmu 9 cn wem 9 uc wma 9 ADCIHPWM automatic topliPWM period 9 mem 9 instructions BZW BNZW BP BN BPC nb of i instruction Return instructions RET RETI PC16 to 08 SP BNK is set PC07 to 00 SP 1 to bit 8 of SP denotes the contents of RAM SP 1 address designated by the value of the stack pointer SP Standard instructions NOP MOV ADD PC PC nb Unchanged nb Number of instruction bytes 2 3 Program Memory ROM This series of microcontrollers have a program memory space of 256K bytes but the size of the ROM that is actually incorporated in the microcontroller varies with the CPU type of the microcontroller The ROM table lookup instruction LDCW can be used to refer all ROM data within the bank Of the ROM space the 256 bytes in ROM bank 0 O1FOOH O1FFFH for this series of microcontrollers are reserved as the option area Consequently this area is not available as a program area 2 4 Internal Data Memory RAM The LC870000 series microcontrollers have an internal data memory space of 64K bytes but the size of the RA
128. pt request signal and set the corresponding interrupt flag These two ports that are selected can also be used as timer 1 count clock input or timer capture signal input HOLD mode release function When both of the interrupt flag and interrupt enable flag are set by INTE or INTF a HOLD mode release signal is generated causing the CPU to switch from HOLD mode to HALT mode system clock assigned to intermediate speed RC oscillation When the interrupt request is accepted the CPU switches from HALT mode to normal operating mode 3 1 PORTS When a signal change such that an interrupt flag is set is input to INTE or INTF in the HOLD mode the interrupt flag is set In this case the CPU exits the HOLD mode if the corresponding interrupt enable flag is set The interrupt flag however cannot be set by a rising edge occurring when INTE or INTF data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when INTE or INTF data which is established when the HOLD mode is entered is in the low state Consequently to release the HOLD mode with INTE or INTF it is recommended that INTE or INTF be used in the both edge interrupt mode 5 Analog comparator voltage input function The analog voltage inputs to the analog comparator are supplied from P11 P12 6 AD converter voltage input function The analog voltages to the AD converter are supplied from P10 to P12 Address Initial value
129. ption Chapter 1 Overview Standby function HALT mode Additional information added to the description in paragraph 2 Standby function HOLD mode Additional information added to the description in paragraph 2 Added Section 1 7 User Options table Chapter 4 Control Functions 4 6 Watchdog Timer WDT 4 6 5 Notes on the Use of the Watchdog Timer added R 1 amendments made to Rev 0 91 Location Page Description Chapter3 Peripheral System Configuration 3 10 Analog Comparator ACMP 3 10 4 1 ACMP control register CMPCNT Additional information added to the description of 2 5 and P32OTSLO bits bits 4 and 1 3 10 4 2 Input signal select register IADSL Additional information added to the description of P32OTIV bit bit 3 R 2 Important Note This document is designed to provide the reader with accurate information in easily understandable form regarding the device features and the correct device implementation procedures The sample configurations included in the various descriptions are intended for reference only and should not be directly incorporated in user product configurations ON Semiconductor shall bear responsibility for obligations concerning patent infringements safety or other legal disputes arising from prototypes or actual products created using the information contained herein LC872600 SERIES USER S MANUAL Rev 1 00 De
130. put polarity control If this bit is set to 0 the selector output selected by P32OTSL 1 0 is output as is If this bit is set to 1 the selector output selected by P32O0TSL 1 0 is inverted before being output to the P32 CMPO pin The signal controlled by this bit is ORed with the signal of the P32 P3 bit 2 before being sent to the P32 CMPO pin 3 67 ACMP 3 68 4 4 1 4 1 1 LC872600 Chapter 4 Control Functions Interrupt Function Overview This series of microcontrollers has the capabilities to control three levels of multiple interrupts 1 low level L high level H and highest level X The master interrupt enable resister IE interrupt priority control register IP are used and enable or disable interrupts and determine the priority of interrupts 4 1 2 1 2 3 4 5 6 Functions Interrupt processing e Peripheral modules generate an interrupt request to the predetermined vector address when the interrupt request and interrupt request enable flags are set to 1 e When the microcontroller receives an interrupt request from a peripheral module it determines the priority and interrupt enable status of the interrupt If the interrupt request is legitimate for processing the microcontroller saves the value of PC in the stack and causes a branch to the predetermined vector address The return from the interrupt routine is accomplished by the RETI instruction which restores the ol
131. r is a register to read out bits 7 to 0 of the HCT2CT This register is read only HCT2 measurement counter middle byte register HCT22MR 8 bit register The HCT2 measurement counter middle byte register is a register to read out bits 15 to 8 of the HCT2CT This register is read only HCT2 measurement counter high byte register HCT22HR 8 bit register The HCT2 measurement counter high byte register is a register to read out the HCT2 input trigger selection the trigger signal sampling shift selection the state of the HCT2CT overflow detection flag and bits 18 to 16 of the HCT2CT Bits 3 to 0 of this register are read only Writing bits 7 to 4 of the HCT2HR when HCT2ST HCT2CNT bit 2 is set to 1 is inhibited Since HCT2CT and HCT20V HCT22HR bit 7 are reset immediately after HCT2ST is set to 1 be sure to read the current count value from the HCT2CT before configuring it for the next operation Read bits 3 to 0 of HCT22HR HCT22MR and HCT22LR after the measurement using the HCT2 is completed after confirming that HCT2END is set to 1 HCT2 prescaler HCT2PR 4 bit counter Operation start stop HCT2ST I HCT2ST 0 Enabled in modes other than HOLD Count clock HC2CK Output clock Generates a clock whose frequency division ratio is selected by bits HC2PRSL and HC2PRSLO HCT2CNT bits 5 and 4 Resetting HCT2ST 0 HCT2 measurement counter HCT2CT 19 bit counter Operation start stop When the measureme
132. r other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner Contents Chapter 1 1 1 1 Overview 1 1 1 2 Features 1 1 1 3 Pinout
133. register stores bits 7 to 0 of the L level width measured by the HCT2 2 This register is read only 3 contents of the HCT2CT are captured into this register if the end of L level width measurement condition is detected when the HCT2ST is set to 1 see Figure 3 8 2 for details 3 8 3 3 HCT2 capture middle byte register HCT21MR 8 bit register 1 The HCT2 capture middle byte register stores bits 15 to 8 of the L level width measured by the HCT2 2 Thisregister is read only 3 Thecontents of the HCT2CT are captured into this register if the end of L level width measurement condition is detected when HCT2ST is set to 1 see Figure 3 8 2 for details 3 49 HCT2 3 8 3 4 2 3 Note 3 8 3 5 2 3 8 3 6 1 2 3 8 3 7 2 Note Note Note 3 8 3 8 2 3 4 3 8 3 9 1 2 3 4 HCT2 capture high byte register HCT21HR 3 bit register The HCT2 capture high byte register stores bits 18 to 16 of the L level width measured by the HCT2 This register is read only The contents of the HCT2CT are captured into this register if the end of L level width measurement condition is detected when HCT2ST is set to 1 see Figure 3 8 2 for details HCT21HR HCT21MR and HCT21LR must be read after the end of a HCT2 measurement after confirming that HCT2END is set to 1 HCT2 measurement counter low byte register HCT22LR 8 bit register The HCT2 measurement counter low byte registe
134. register used to control the port 3 output data and pull up registers 2 When this register is read with an instruction data at pins P30 to P33 is read in If P3 FE4C is manipulated with an instruction NOTI CLRI SET1 DBZ DBNZ INC or DEC the contents of the register are referenced instead of the data at port pins 3 Port 3 data can always be read regardless of the I O state of the port Address Initial value RW Name BIT7 5 BIT4 BIT3 BIT2 BITI BITO rac 000 Rw ps a pu P30 3 2 3 2 Port 3 direction register P3DDR 1 The port 3 data direction register is a 4 bit register that controls the I O direction of port 3 data on a bit basis Port P3n are placed in the output mode when bit P3nDDR is set to 1 and in the input mode when bit P3nDDR is set to 0 2 Port P3n becomes an input with a pull up resistor if bit P3nDDR is set to 0 and the bit P3n of the port 3 data latch is set to 1 Address RW Name 7 Bme Bms Bm2 FE4D HHHH 0000 R W P3DDR P33DDR P32DDR P31DDR P30DDR Register Data Port P3n State Built in Pull up Resistor Enabled Open OFF Enabled Internal pull up resistor 0 Enabled High open CMOS N channel open drain 3 2 3 3 External interrupt A B control register IABCR 1 The external interrupt control register is an 8
135. riod defined by HCT1CNT bits 6 to 4 x HCT1HR bits 6 to 0 HCTILR value 15 bits Note Since HCTICT and HCTIOV are reset immediately when none of bits and HCTIOPO are set to 0 be sure to read the current count value from the HCTICT before configuring it for the next operation Note Read HCTIHR and HCTILR after the measurement of HCTI is completed after confirming that HCTIEND is set to 1 3 47 HCT2 3 8 3 8 1 High speed Pulse Width Period Measurement Counter 2 HCT2 Overview This series of microcontrollers is provided with a high speed pulse width period measurement counter 2 2 that has the following features 1 2 3 4 3 8 2 2 System clock high speed RC oscillation clock 20 MHz or 40 MHz selectable Can measure both L level width and period at the same time Input trigger noise filter function Input trigger selection function selectable from 3 signals i e PLI HCT2IN P31 HCT2IN and analog comparator output Functions High speed pulse width period measurement counter function A 4 bit prescaler HCT2PR runs on the system clock or high speed RC oscillation clock reference clock HC2CK selected from 2 clock sources and generates a clock whose frequency division ratio is selected by HCT2 control register HCT2CNT This clock is used to detect the edge of the HCT2 input trigger signal selected from P11 HCT2IN P31 HCT2IN or analog comparator output When the measureme
136. rupt request to vector address 0013H are generated 3 1 3 5 External interrupt E F pin select register IEFSL 1 The external interrupt E F pin select register is an 8 bit register used to select the pins for external interrupts E and F FIXO bits 7 6 and 3 These bits are available for test purposes They must always be set to 0 IFSL1 bit 5 INTF pin function select IFSLO bit 4 INTF pin function select A timer count clock input or timer 0 capture signal is generated when a data change that is designated by the external interrupt E F control register IEFCR is applied to the pin that is assigned to INTF IFSL1 IFSLO Function other than INTF Interrupt IESL2 bit 2 INTE pin select Pin Assigned to INTE 0 Port P10 IESL1 bit 1 INTE pin function select IESLO bit 0 INTE pin function select A timer count clock input or timer 0 capture signal is generated when a data change that is designated by the external interrupt E F control register IEFCR is applied to the pin that is assigned to INTE Function other than INTE Interrupt None Timer 1 count clock input Timer OL capture signal input Timer OH capture signal input Notes 1 The signal from port is ignored if the timer OL capture signal input or timer OH capture signal input is assigned to both port 3 and INTE or INTF 2 If both of pins INTE and INTF are assigned to timer 1 count clock input timer OL capture signal
137. s and the match register has the same value when in inactive TIHRUN 0 If active TIHRUN 1 the match buffer register is loaded with the contents of TIHR when the value of T1H reaches 0 Address Initial Value R W Name BIT7 BIT6 BIT5 BIT4 BITS BIT2 BIT1 BITO FEID 0000 0000 R W TIHR TIHR7 TIHR6 TIHRS TIHR4 TIHR3 TIHR2 TIHRI TIHRO 3 28 LC872600 Chapter 3 3 5 Serial Interface 7 5107 3 5 1 Overview The serial interface SIO7 incorporated in this series of microcontrollers has the following function 1 Synchronous 8 bit serial I O 2 or 3 wire system clock rates of 4 to 512 3 5 2 Functions 1 Synchronous 8 bit serial I O Performs 2 or 3 wire synchronous serial communication The clock may be an internal or external clock The clock rate of the internal clock is programmable within the range of n 1 x 2 Tcyc n to 255 Note n 0 is inhibited 2 Interrupt generation An interrupt request is generated at the end of transmission when the interrupt request enable bit is set 3 To control serial interface 7 SIO7 it is necessary to manipulate the following special function registers SCONT SBUF7 SBR7 PI PIDDR PIFCR Address Initial Value BIT7 BIT6 BITS BIT3 BIT2 BIT1 0000 0000 SCN7B7 SI7REC SI7TRUN SI DIR SI7OVR SI7TEND 3 5 3 Circuit Configuration 3 5 3 1 107 control register SCON7 8 bit regi
138. s Interrupt Source 00003H 00013H INTC TOL INTE wem nor 3 wem nor mm s period e Priority levels X gt H gt L Ofinterrupts of the same level the one with the smallest vector address takes precedence Subroutine stack levels 256 levels maximum The stack is allocated in RAM High speed multiplication division instructions e 6bitsx8 bits 5 Tcyc execution time e 24 bits x 16 bits 12 Tcyc execution time e 16bits 8bits 8 Tcyc execution time e 24 bits 16 bits 12 Tcyc execution time Oscillation circuits Medium speed RC oscillation circuit internal For system clock 1 MHz Low speed RC oscillation circuit internal For watchdog timer only 30 kHz High speed RC oscillation circuit internal For system clock 20 MHz or 40 MHz 1 The source oscillation frequency of the high speed RC oscillation circuit can be selected from 2 sources 20 MHz and 40 MHz by configuring options System clock frequency divider function Canrunon low current The minimum instruction cycle selectable from 300ns 600ns 1 215 2 48 4 8 5 9 6 19 215 38 4us and 76 8 5 when high speed RC oscillation is selected as the system clock source 1 3 Internal reset circuit e Power on reset POR function 1 reset is generated only at power on time 2 POR release le
139. s the match signal for the prescaler When this bit is set to 1 the count clock for TOL is an external input signal TOHCMP bit 3 TOH match flag This bit is set when the value of TOH matches the value of the match buffer register for TOH while TOH is running TOHRUN 1 and a match signal is generated Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match needs to occur in all 16 bits of data for a match signal to occur TOHIE bit 2 TOH interrupt request enable control When this bit and TOHCMP are set to 1 an interrupt request to vector address 0023H is generated TOLCMP bit 1 TOL match flag This bit is set when the value of TOL matches the value of the match buffer register for TOL while TOL is running TOLRUN 1 and a match signal is generated Its state does not change if no match signal is generated Consequently this flag must be cleared with an instruction In the 16 bit mode TOLONG 1 a match needs to occur in all 16 bits of data for a match signal to occur TOLIE bit 0 TOL interrupt request enable control When this bit and TOLCMP are set to 1 an interrupt request to vector address 0013H is generated 3 19 Notes TOHCMP and TOLCMP must be cleared to 0 with an instruction When the 16 bit mode is to be used TOLRUN must be set to the same value to control operation T
140. scillates according to the built in resistor and capacitor 2 The source oscillation frequency can be chosen between 20 MHz and 40 MHz by selecting options The source oscillation clock is supplied to HPWM and HCT2 and the frequency divided clock is supplied to the system clock selector i As oscillation is unstable immediately after oscillation starts the system requires the oscillation stabilization wait time For details refer to the latest SANYO Semiconductor Data Sheet 4 2 3 3 Power control register PCON 2 bit register 1 power control register specifies the operating mode normal HALT HOLD 4 2 3 4 Oscillation control register OCR 7 bit register 1 oscillation control register controls the start stop operation of the oscillator circuits 2 Thisregister selects the system clock 3 The register sets the frequency division ratio of the oscillation clock to be used as the system clock to m E 1 2 4 2 3 5 System clock frequency division control register CLKDIV 3 bit register 1 The system clock division control register controls the operation of the system clock frequency divider circuit The frequency division ratios of 2 S and are allowed 1 2 4 8 16 32 64 128 4 6 LC872600 Chapter 4 20MHz 40MHz CLKCB5 option CLKSGL CLKDV2 to 0 HRCON High speed RC High speed RC clock oscillator System clock gt SCLK To HPWM HCT1
141. shed when the HOLD mode is entered is in the low state Consequently to reset the HOLD mode with INTF it is recommended that INTF be used in the both edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically INTFIE bit 4 INTF interrupt request enable When this bit and INTFIF are set to 1 a HOLD mode release signal and an interrupt request to vector address 001BH are generated INTEHEG bit 3 INTE rising edge detection control INTELEG bit 2 INTE falling edge detection control INTEIF bit 1 INTE interrupt source flag This bit is set when the conditions specified by INTEHEG and INTELEG are satisfied When this bit and the INTE interrupt request enable bit INTEIE are set to 1 a HOLD mode release signal and an interrupt request to vector address 0013H are generated The interrupt flag however cannot be set by a rising edge occurring when INTE data which is established when the HOLD mode is entered is in the high state or by a falling edge occurring when INTE data which is established when the HOLD mode is entered is in the low state Consequently to reset the HOLD mode with INTE it is recommended that INTE be used in the both edge interrupt mode This bit must be cleared with an instruction as it is not cleared automatically 3 4 LC872600 Chapter 3 INTEIE bit 0 INTE interrupt request enable When this bit and INTEIF are set to 1 a HOLD mode release signal and an inter
142. starts oscillation an operating current of several flows at all times For details refer to the latest SANYO Semiconductor Data Sheet 4 6 3 2 WDT counter WDTCT 16 bit counter 1 Operation start stop Places the CPU into the standby mode when WDTRUN is set to 1 and WDTRUN is set to 0 or when WDTRUN is set to 1 and IDLOP1 and IDLOPO WDTCNT bits 4 and 3 are set to 1 2 Count clock Low speed RC oscillation clock 3 Overflow Generated when the WDTCT count value matches the count value designated by WDTSL2 through WDTSLO WDTCNT bits 2 to 0 Generates a signal to set the RSTFLG flag bit WDTCNT bit 7 Generates the WDT reset signal and the WDTRUN clear signal 4 Resetting Places the CPU into the standby mode when WDTRUN is set to 0 overflow occurs WDTRUN is set to 1 and instruction 55H WDTCNT is executed or WDTRUN is set to 1 and IDLOPI and IDLOPO are set to 1 See Figure 4 6 2 for details on the WDT operation WDTRUN Oscillation control WDT counter WDTCT Low speed RC Clock WDTRUN DADA oscillation circuit Stop oscillation WDTRST 1 WDTRUN clear signal WDT reset signal RSTFLG set signal WDTSL2 0 IDLOP1 0 2 WDTRST Standby mode sen IDLOP1 0 1 WDTRUN clear signal Enter standby mode Figure 4 6 1 Watchdog Timer Operation Block Diagram 4 23 WDT Operation performed when IDLOP1 0 are set to 0 or 3 continued operation Over
143. ster n this mode timer counter 0 serves as a 16 bit programmable counter that counts the number of external input detection signals from pins P32 INTC and P33 INTD The contents of TOL and TOH are captured into the capture registers TOCAL and TOCAH at the same time on external input detection signals from P31 INTB P33 INTD P10 P12 timer 0H capture input pins TO period TOHR TOLR 1 16 bits 5 Interrupt generation TOL or TOH interrupt requests are generated at the counter interval for timer counter TOL or TOH if the interrupt request enable bit is set 6 To control timer counter 0 TO it is necessary to manipulate the following special function registers TOCNT TOL TOLR TOHR PI PIDDR IABCR ICDCR IADSL P3DDR IEFCR IEFSL 0000 0000 TOCNT TOHRUN TOLRUN TOLONG TOLEXT TOHCMP TOHIE TOLCMP eoo x m mc me ma Cen x rr rons rens ro 3 14 3 3 3 3 3 3 1 1 3 3 3 2 1 3 3 3 3 1 2 3 4 3 3 3 4 2 3 4 3 3 3 5 2 3 4 3 3 3 6 2 LC872600 Chapter 3 Circuit Configuration Timer counter 0 control register TOCNT 8 bit register This register controls the operation and interrupts of TOL and TOH Programmable prescaler match register TOPRR 8 bit register This register stores the match data for the programmable presca
144. ster 1 5107 control register controls the operation and interrupts of 5107 3 5 3 2 SIO7 shift register SIOSF7 8 bit shift register 1 SIO7 shift register is used to transmit and receive data 5107 2 The register cannot be accessed directly with an instruction It must be accessed through SBUF7 3 5 8 3 SIO7 data buffer SBUF7 8 bit register 1 The contents of SBUF7 are transferred to SIOSF7 at the beginning of data transmission 2 In the data reception mode the contents of SIOSF7 are placed in SBUF7 at the end of data transmission 3 5 3 4 107 baudrate generator register SBR7 8 bit register 1 Thisis an 8 bit register that defines the baudrate for 5107 serial transmission 2 It can generate clocks at intervals of n 1 x 2 Tcyc n to 255 Note 0 is inhibited 3 29 Data input At time At time transfer operation Starts SIO7 output contro P10 port latch P10 output control P10 SBUF7 FEF9h SIO7 output control P11 port latch P11 output contro Clock Clock generation ee circuit SIO7 output control gt P12 P12 port latch P12 Baud MSB LSB first control ERE DER generator Serial transfer end flag AY A y V SBR7 FEFAh Overrun flag re oe eos eno SCON7 FEF8h Interrupt request Figure 3 5 1 5107 Synchronous 8 bit Serial I O Block Diagram 3 30 LC872600 Chapter 3
145. surement Counter 2 Waveforms HCT2 trigger shift operation Comparator output Edge Sampling Edge Sampling Edge Sampling detected detected detected TRGSFTCT A A A A Start counting Start counting Start counting Signal after trigger shift This feature should be used when the comparator output signal is not fully filtered out with the noise filter Figure 3 8 3 Sample Input Trigger Signal Shift Operation Waveforms TRGSFT2 to TRGSFTO set to a nonzero value 3 52 LC872600 Chapter 3 3 8 4 Related Registers 3 8 4 1 HCT2 control register HCT2CNT 1 The HCT2 control register is used to select the HC2CK to select the frequency division ratio for the HCT2PR and to control operation and interrupts of HCT2 Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BITO 5 0000 H000 R W 2 HC2CKSL HC2PRSLI HC2PRSLO HCT2ST HCT2END HCT2IE FIXO bit 7 Test bit This bit is used only for testing and must always be set to 0 HC2CKSL bit 6 HCT2 reference clock HC2CK select HC2CKSL Reference Clock HC2CK 0 High speed RC oscillation clock HC2PRSL1 bit 5 HC2PRSLO bit 4 HCT2 prescaler HCT2PR control HCT2 Prescaler Frequency Division HC2PRSL1 HC2PRSLO Ratio Select HCT2 Operation Select Stop HCT2 operation The measurement starts when the specified measurement start condition is detected after HCT
146. t REG8 after computation INCW INC 17 bits REGL8 lt lower byte of CY P1 lt REGH8 after computation DEC DEC 9 bits P1 REGS after computation DECW DEC 17 bits REGL8 lt lower byte of CY P1 REGHS after inverted computation DBNZ DEC 9 bits P1 lt REG8 DEC 9 bits P1 lt REG8 em f SOS MUL24 8 lt 1 DIV24 Note A I is read if the processing target is an 8 bit register no bit 8 lt P1 lt bitl when PSW is popped P1 lt bit1 when higher order address of PSW is popped BITS ignored INC 9 bits INC 17 bits DEC 9 bits DEC 17 bits DEC 9 bits check lower order 8 bits DEC 9 bits check lower order 8 bits Bit 8 of RAM address for storing results is set to 1 Legends REGS Bit 8 of a RAM or SFR location REGHS REGLS Bit 8 of the higher order byte of a RAM location or SFR bit 8 of the lower order byte RAMS Bit 6 of a RAM location RAMHS8 RAMLS 8 of the higher order byte of a RAM location bit 8 of the lower order byte 2 10 LC872600 Chapter 3 3 Peripheral System Configuration This chapter describes the built in functional blocks peripheral system of this series microcontrollers except the CPU core RAM and ROM Port block diagrams are provided in Appendix for reference 3 1 3 1 1 Port 1 Overview Port is a 3 bit I O port equipped with programmable pull up resistors It is made up of a data latch a data
147. t assuming that SP represents the current value of the stack pointer the value of BNK and the lower order 8 bits of the 17 bit PC are stored in RAM address SP 1 and the higher order 9 bits in SP 2 after which SP is set to SP 2 2 5 initialized to OOH on a reset Accumulator A Register ACC A The accumulator ACC also called the A register is an 8 bit register that is used for data computation transfer and I O processing It is allocated to address in the internal data memory space and Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO 0000 0000 R W AREG AREG7 AREG6 AREGS AREG4 AREG3 AREG2 AREGI AREGO 2 6 B Register B The B register is combined with the ACC to form a 16 bit arithmetic register during the execution of a 16 bit arithmetic instruction During a multiplication or division instruction the B register is used with the ACC and C register to store the results of computation In addition during an external memory access instruction LDX or STX the B register designates the higher order 8 bits of the 24 bit address The B register is allocated to address FEO1H of the internal data memory space and initialized to on a reset Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FEO1 0000 0000 R W BREG BREG7 BREG6 BREG5 BREG4 BREG3 BREG2 BREGI BREGO 2 7 C Register C The C register is used with the ACC
148. t is disallowed to point to a different area using an offset value from the basic area designated by the contents of RO For example if the instruction LD 1 is executed when RO contains OFDFFH since the basic area is 3 RAM stack area OOOOH to FDFFH the intended address OFDFFH 1 lies outside the basic area and OFFH is placed in the ACC as the results of LD If the instruction LD 2 is executed when RO contains since the basic area is 2 SFR FEOOH to FEFFH the intended address OFEFFH 2 OFFO1H lies outside the basic area In this case since SFR is confined in an 8 bit address space the part of the address data addressing outside the 8 bit address space is ignored and the contents of OFEO1H B register are placed in the ACC as the result of computation OFFO1H amp OFFH OFEO1H 2 11 5 Direct Addressing dst The direct addressing mode allows a RAM or SFR address to be specified directly in an operand In this addressing mode the assembler automatically generates optimum instruction code from the address specified in the operand the number of instruction bytes varies according to the address specified in the operand Long middle range instructions identified by an L M at the end of the mnemonic are available to make the byte count of instructions constant align instructions with the longest one Examples LD 123H Transfers the contents of RAM address 123H to the ac
149. t request to vector address 0043H is generated when this bit and ADENDF are set to 1 Notes Setting ADCHSEL3 to ADCHSELO to any value from 0011 to 1111 Do not place the microcontroller the HALT or HOLD mode with ADSTART set to 1 Make sure that ADSTART is set to 0 before putting the microcontroller in the HALT or HOLD mode 3 9 4 2 mode register ADMRC 1 The AD mode register is an 8 bit register for controlling the operation mode of the AD converter Address Initial value R W Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO FE59 0000 0000 R W ADMRC ADMD4 ADMD3 ADMD2 ADMDI ADMDO ADMR2 ADTMI ADTMO ADMD4 bit 7 Fixed bit This bit must always be set to 0 3 59 ADC12 bit 6 AD conversion mode control resolution select This bit selects the AD converter s resolution between 12 bit AD conversion mode 0 and 8 bit AD conversion mode 1 When this bit is set to 1 the AD converter serves as an 8 bit AD converter The conversion results are placed only in the AD conversion results register high byte ADRHC the contents of the AD conversion results register low byte ADRLC remain unchanged When this bit is set to 0 the AD converter serves as a 12 bit AD converter The conversion results are placed in the AD conversion results register high byte ADRHC and the higher order 4 bits of the AD conversion results register low byte ADRLC ADMD2 bit 5 Fixed bit This bit
150. t when it stops operation or a match signal occurs 3 4 3 7 Timer 1 match data register low byte T1LR 8 bit register with a match buffer register 1 This register is used to store the match data for TIL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with that of timer 1 low byte T1L 2 The match buffer register is updated as follows and the match register has the same value when in inactive state TILRUN 0 If active TILRUN 1 the match buffer register is loaded with the contents of TILR when the value of TIL reaches 0 3 24 LC872600 Chapter 3 3 4 38 Timer 1 match data register high byte T1HR 8 bit register with a match buffer register 1 This register is used to store the match data for T1H It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with that of timer 1 high byte T1H 2 The match buffer register is updated as follows and the match register have the same value when in inactive state TIHRUN 0 If active TIHRUN 1 the match buffer register is loaded with the contents of TIHR when the value of T1H reaches 0 2T Clock 2Teve gt external events Set in IEFCR FE4Ah IEFSL FE4Bh registers Clock 2Tcyc gt T1H prescaler T1L prescaler Match buffer register Match buffer register Reload Reload n
151. tected HCT1CT counting stop HCT1END flag set 1 1 0 0 clear A A HCT1 operation start Measurement start Measurement start condition HCT10P1 0 1 condition 1 detected 2 detected HCT1CT 0 clear H level detected rising edge detected HCT1CT counting start L level width measurement P30 HCT1IN L level width measurement A A A Measurement start Measurement start condition Measurement end condition 2 detected detected falling edge detected rising edge detected HCT1CT counting start HCT1CT counting stop HCT1END flag set HCT10P1 0 0 clear A HCT1 operation start HCT10P1 0 2 condition 1 detected HCT1CT 0 clear H level detected Period measurement P30 HCT1IN Period measurement A A A A Measurement start Measurement start condition Measurement end condition condition 1 detected 2 detected detected falling edge detected falling edge detected HCT1CT counting start HCT1CT counting stop flag set HCT10OP1 0 0 clear The width of the H level signal to be input needs to be not narrower than that of the noise filter output HCT1PR output clock width x 3 for the measurement start condition 1 H level to be detected Figure 3 7 2 Sample High speed Pulse Width Period Measurement Counter 1 Waveforms HCT1 operation start HCT10P1 0 3 HCT1CT 0 clear H level detected 3 45 HCT1 3 7 4 Related Registers 3 7 4 1 HCT1 control register HCT1CNT 1 The HCTI control register is used
152. the AD mode register ADCRC until it is set to 1 After verifying that bit 1 ADENDE is set to 1 clear it to zero 6 Reading the AD conversion results Read the contents of the AD conversion results registers high byte ADRHC and low byte ADRLC The read conversion data contains some errors quantization error combination error Be sure to use only valid conversion results while referring to the latest SANYO Semiconductor Data Sheet Pass the read data to the application software Return to step 4 to repeat the conversion processing 3 62 3 9 6 1 2 3 4 5 6 7 8 9 LC872600 Chapter 3 Hints on the Use of the ADC The conversion time that the user can select varies depending on the frequency of the cycle clock When preparing a program refer to the latest edition of SANYO Semiconductor Data Sheet to select an appropriate conversion time Setting ADSTART to 0 while conversion is in progress will stop the conversion function Do not place the microcontroller in the HALT or HOLD mode while AD conversion processing is in progress Make sure that ADSTART is set to 0 before putting the microcontroller in the HALT or HOLD mode ADSTART is automatically reset and the AD converter stops operation if a reset is triggered while AD conversion processing is in progress When conversion is finished the end of AD conversion flag ADENDF is set and at the same time the AD conversion operat
153. the contents of the PWMCKR PWMILR PWM2LR and PWMXHR are reloaded into the respective buffer registers and RLDBSY is cleared For this reason since a write into PWMXHR will trigger the reload when changing the duty cycle or period while the HPWM is active code the program so that PWMXRR be loaded with reload data in the last place Note 5 It is possible to write data into PWMCKR PWMILR PWM2LR and PWMXHR when 3 6 3 6 1 2 3 6 3 7 1 2 PWMST 1 PWMDSL I set value output mode and PWMCTOV PWMCNT bit 3 1 In this case RLDBSY is not set even when a write is attempted HPWM period count low byte register PWMCTLR 8 bit register This register and bits 2 to 0 of the PWMCTHR PWMCTIO to PWMCTO08 are used to define the period count value of the HPWM The value of this register exerts no influence on the operation of the HPWM if PWMDSL PWMCTHR bit 7 is set to 0 HPWM period count high byte register PWMCTHR 4 bit register The HPWM period count high byte register is used to select the HPWM operating mode and to define the period count with PWMCTHR bits 2 to 0 and PWMCTLR Bits 2 to 0 of the PWMCTHR exert no influence on the operation of the HPWM if PWMDSL is set to 0 Note 6 Setting bit PWMDSL is inhibited if PWMST is set to 1 Note 7 Writing data into bits 2 to 0 of the PWMCTHR and the PWMCTLR is inhibited if PWMST is 3 6 3 8 2 set to 1 If both PWMDSL and PWMCTOV are set to 1 however the HPW
154. tion added to the description of MFP10S Development tools Changes made to the description of the development tools 13 Pinout Additional information added to the description of 105 1 7 Recommended Treatment of Unused Pins added 1 8 User Options Changes made to the description of the package type 14 Chapter3 Peripheral System Configuration 3 6 High speed 12 bit PWM HPWM 3 34 3 6 2 Functions Changes made to the description of paragraph 1 High speed 12 bit PWM function 3 36 3 6 3 5 HPWM DUTY period high byte register PWMXHR Changes made to Note 4 3 6 3 7 HPWM period count high byte register PWMCTHR Additional information added to Note 7 3 6 3 8 HPWM prescaler buffer register PWMPBR Changes made to the description of paragraph 2 3 6 3 9 HPWM DUTY buffer register PWMIBR Changes made to the description of paragraph 2 3 6 3 10 HPWM period buffer register PWM2BR Changes made to the description of paragraph 2 Figure 3 6 2 Sample Continuous Output Mode Waveform Changes made to the Sample Continuous Output Mode Waveform 3 6 4 1 HPWM control register PWMCNT Changes made to the description of RLDBSY bit 4 and PWMCTOV bit 3 3 6 4 5 HPWM DUTY period high byte register PWMXHR Changes made to the notes 3 6 4 7 HPWM period count high byte register PWMCTHR Additional information added to the notes Major amendments made to Rev 0 93 Location Page Descri
155. to be used The recommended constant value of Cres is 0 0228 4 15 Internal reset Interior of microcontroller Rres 360kQ typ Reset Cres 0 022uUF Power on reset POR Low voltage detection reset LVD Figure 4 5 1 Internal Reset Circuit Configuration Pulse stretcher Options 4 5 4 Options The POR and LVD options are available for the reset circuit 1 LVD Reset Function Options Enable Use Disable Disuse 2 LVD Reset Level Option 3 POR Release Level Option Typical Value of Min Operating Typical Value of Min Operating Selected Option VDD Value Selected Option VDD Value The minimum operating VDD value specifies the approximate lower limit value of the VDD value beyond which the selected POR release level or LVD reset level can be effected without generating a reset 1 LVD reset function option When the LVD reset function is enabled a reset is generated at the voltage that is selected by the LVD reset level option Notel In this configuration an operating current of several uA always flows in all modes No LVD reset is generated when Disable is selected Note2 In this configuration no operating current will flow in all modes See the sample operating waveforms of the reset circuit shown in Subsection 4 5 5 for details 2 LVD reset level option The LVD reset level can be selected from 3 level values only when the LVD reset function is enabled
156. unter is reset when it stops operation or a match signal is generated Timer counter 0 match data register low byte TOLR 8 bit register with a match buffer register This register is used to store the match data for TOL It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the lower order byte of timer counter 0 16 bits of data need to match in the 16 bit mode The match buffer register is updated as follows The match register matches TOLR when it is inactive TOLRUN 0 When the match register is running TOLRUN 1 it is loaded with the contents of TOLR when a match signal is generated 3 3 8 7 X Timer counter 0 match data register high byte TOHR 8 bit register with a match buffer register 1 This register is used to store the match data for It has an 8 bit match buffer register A match signal is generated when the value of this match buffer register coincides with the higher order byte of timer counter 0 16 bits of data need to match in the 16 bit mode 2 The match buffer register is updated as follows The match register matches TOHR when it is inactive TOHRUN 0 When the match register is running TOHRUN 1 it is loaded with the contents of TOHR when a match signal is generated 3 3 8 8 Timer counter 0 capture register low byte TOCAL 8 bit register 1 Capture clock External input detection signals from pins P30 INTA
157. ure 3 8 2 for details Initial value 3 8 4 4 1 2 3 HCT2 capture high byte register HCT21HR The HCT2 capture high byte register stores bits 18 to 16 of the L level width measured by the HCT2 This register is read only The contents of the HCT2CT are captured into this register if the end of L level width measurement Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 Address FEC8 condition is detected while HCT2ST is set to 1 see Figure 3 8 2 for details BITO HCT21R16 HHHH HXXX HCT21HR HCT2IRIS8 HCT2IRI7 HCT2 measurement period L level width Period defined by bits 6 to 4 of HCT2CNT x HCT21HR HCT21MR HCT21LR value 19 bits Note HCT21HR HCT21MR and HCT21LR must be read after the end of a HCT2 measurement after confirming that HCT2END is set to 1 3 8 4 5 HCT2 measurement counter low byte register HCT22LR 1 The HCT2 measurement counter low byte register is a register to read out bits 7 to 0 of the HCT2CT data 2 Thisregister is read only rita value 9 HCT22LR 22607 22 6 22 5 22 4 22 22 2 HCT22RO1 22 3 8 4 6 2 measurement counter middle byte register HCT22MR 1 The HCT2 measurement counter middle byte register is a register to read out bits 15 to 8 of the HCT2CT data 2 Thisregister is read only Address Initial value R W
158. value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FE08 0000 R W IE IE7 XFLG HFLG LFLG XCNTI XCNTO IE7 bit 7 H L level interrupt enables disables control e in this bit enables H and L level interrupt requests to be accepted e AQ in this bit disables H and L level interrupt requests to be accepted e X level interrupt requests are always enabled regardless of the state of this bit XFLG bit 6 X level interrupt flag R O This bit is set when an X level interrupt is accepted and reset when execution returns from the processing of the X level interrupt This bit is read only No instruction can rewrite the value of this bit directly HFLG bit 5 H level interrupt flag R O This bit is set when an H level interrupt is accepted and reset when execution returns from the processing of the H level interrupt This bit is read only No instruction can rewrite the value of this bit directly LFLG bit 4 L level interrupt flag R O This bit is set when an L level interrupt is accepted and reset when execution returns from the processing of the L level interrupt This bit is read only No instruction can rewrite the value of this bit directly Bits 3 2 These bits do not exist They are always read as 1 XCNT1 bit 1 0000BH Interrupt level control flag e Alin this bit sets all interrupts to vector address 0000BH to L level e A in this bit sets all interrupts to vector a
159. vel can be selected from 3 levels 2 87V 3 86V and 4 35V by configuring options e Low voltage detection reset LVD function 1 LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level 2 use disuse of the LVD function and the low voltage threshold level can be selected from 3 levels 2 81V 3 79V and 4 28V by configuring options Standby function e HALT mode Halts instruction execution while allowing the peripheral circuits to continue operation 1 Oscillation is not stopped automatically 2 There the following three ways of resetting the HOLD mode 1 Setting the Reset pin to the low level 2 Generating a reset signal via the watchdog timer or brown out detector 3 Having an interrupt generated e HOLD mode Suspends instruction execution and the operation of the peripheral circuits 1 The medium and high speed RC oscillators automatically stop operation 2 There are the following four ways of resetting the HALT mode 1 Setting the Reset pin to the low level 2 Generating a reset signal via the watchdog timer or brown out detector 3 Setting at least one of the INTA INTB INTC INTD INTE and INTF pins to the specified level INTA and INTB HOLD mode reset is available only when level detection is set 4 Applying input signals to the IN and IN pins so that the analog comparator output is set to the specified level when
160. version mode 2 Since the data in this register is not established during an AD conversion the conversion results must be read out only after the AD conversion is completed Address Initial value R W Name BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO FESB 0000 0000 R W ADRHC DATA7 DATA6 5 DATA4 DATA3 DATA2 DATAO 3 61 ADC12 3 9 5 AD Conversion Example 3 9 5 1 12 bit AD conversion mode Setting up the 12 bit AD conversion mode Set the ADMD3 bit 6 of the AD mode register ADMRC to 0 2 Setting up the conversion time To set the conversion time to 1 32 set bit 0 ADTM2 of the AD conversion results register low byte ADRLC to 1 bit 1 ADTM1 of the AD mode register ADMRC to 0 and bit 0 ADTMO of the AD mode register to 1 3 Setting up the input channel When using AD channel input AN2 set AD control register ADCRC bit 7 ADCHSEL3 to 0 bit 6 ADCHSEL2 to 0 bit 5 ADCHSEL 1 to 1 and bit 4 ADCHSELO to 0 4 Starting AD conversion Set bit 2 ADSTART of the AD mode register ADCRC to 1 The conversion time will be twice the normal conversion time immediately after a system reset and for the first AD conversion that is carried out after the AD conversion mode is switched from 8 bit to 12 bit conversion mode In the second and subsequent AD conversions the normal conversion time is taken 5 Testing the end of AD conversion flag Monitor bit 1 ADENDF of
161. vironment Be sure to review and observe the operating specifications circuit configuration precautions and considerations discussed in section 4 5 Internal Reset Function 4 14 LC872600 Chapter 4 4 5 Internal Reset Function 4 5 1 Overview This series of microcontroller incorporates internal reset functions called the power on reset POR and low voltage detection reset LVD The use of these functions will contribute to the reduction in the number of externally required reset circuit components reset IC etc 4 5 2 Functions 1 Power on reset POR function POR is a hardware feature that generates a reset to the microcontroller at power on time This function allows the user to select the POR release level by option only when the disuse of the low voltage detection reset function is selected It is necessary to use the undermentioned low voltage detection reset function together with this function or configure an external reset circuit if there are possibilities that chatter can occur or a momentary power loss occur at power on time 2 Low voltage detection reset LVD function This function when used together with the POR function can generate a reset when power is turned on and when the power level lowers As a user option Enable use or Disable disuse and the detection level of this function can be specified 4 5 3 Circuit Configuration The internal reset circuit consists of POR LVD pulse stretcher
162. vision ratio is selected by HCT1 control register HCTICNT This clock is used to detect the edge of the signal input from the P30 HCTIIN pin When the measurement start condition is detected the 15 bit up counter HCTICT starts count operation After that on the detection of measurement end condition the HCTICT stops counting and holds the count value At this moment measurement end flag is set measurement period Period defined by bits 6 to 4 of HCTICNT HCTI1HR bits 6 to 0 HCTILR value 15 bits Input trigger noise filter function The has a noise filter stage before the edge detector circuit This circuit supplies the filtered signal to the edge detector circuit The noise filter circuit samples the signal that is input from the P30 HCTIIN pin on the output clock from the HCTIPR When a match in signal level occurs 3 consecutive times the noise filter circuit holds that signal level Otherwise the noise filter circuit retains the old signal level Noi Noise or signal Filter clockx2 Filter clockx3 Interrupt generation If an interrupt request is generated from the HCT1 while the interrupt request enable bit is set an interrupt request to vector address 0033H is generated To control the high speed pulse width period measurement counter 1 HCT1 it is necessary to manipulate the following special function registers HCTICNT HCTILR HCTIHR e P3 PBD
163. y set when PDN is set IDLE bit 0 HALT mode setting flag 1 Setting this bit places the microcontroller into the HALT mode 2 This bit is automatically set whenever PDN bit 1 is set 3 This bit is cleared on acceptance of an interrupt request or on receipt of a reset signal Table 4 3 1 Standby Mode Operations ltem mode Reset State HALT Mode HOLD Mode Entry conditions e RES applied PCON register PCON register e Reset from brown out Bit 1 0 0 1 Bit 121 Data changed on entry Internal medium speed RC oscillator Internal high speed RC oscillator CPU I O pin state RAM Peripheral modules Exit conditions Returned mode Data changed on exit detector Reset from watchdog timer Initialized as shown in separate table Running Stopped Initialized See Table 4 3 2 RES Unpredictable Brown out detector Unpredictable or data preserved dependent on supply voltage When watchdog timer reset Data preserved Stopped Entry conditions canceled Normal operation mode None WDTCNT bit 5 is cleared if WDTCNT register FE79 bits 4 3 are set to 0 1 State established at entry time State established at entry time Stopped lt Data preserved State established at entry time e Interrupt request accepted Reset entry conditions established Normal operation mode Note1 PCON register bit 0 0 WDTCNT bit 5 is cleared if WDTCNT register FE79 bits

LC872600 SERIES USER`S MANUAL

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