MAX24101 15Gbps Octal Linear Equalizer
Contents
1. Vcc 0 2 Open State Current Tolerance Hiz VIH MIN lt VIN lt VIH MAX all other 450 Input Logic High Current Iu CMOS pins u Vun lt Vin lt masc PGM_IN VIL MIN lt VIN lt VIL MAX all other Ap Input Logic Low Current liL CMOS pins uA VIL MIN lt VIN lt ViL Mmax HGM IN 18 www maximintegrated com Maxim Integrated 4 MAX24101 15Gbps Octal Linear Equalizer Electrical Characteristics continued Typical values are at Vecer Voct Vecer 2 5V Ta 25 C See Figure 1 for typical supply filtering Note 2 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GC CHARACTERISTICS SDA SCL Note 7 CC CC Output Low Voltage SDA planes rt ft Note 2 The MAX24101 is 100 production tested at T 25 C and T 85 C Specification at Ta 40 C is guaranteed by design or characterization unless otherwise noted Note 3 Guaranteed by design and characterization Note 4 Measured with circuit board loss optimized for best DJ Residual jitter is the difference in deterministic jitter between the reference data source and device output DJRESIDUAL DJOUTPUT DJSOURCE The deterministic jitter at the output of the transmission line must be from media induced loss Measured at point D in Figure 2 Test Patter 66 Zeroes 1010 PRBS7 66 ones 0101 Inverted PRBS7 Note 5 The output voltage range in which a linear relationship between the input and output maintains less than or equal to 1dB compression No2. Figure 11 Slave Address Configuration www maximintegrated com MAX24101 1 2 PGM_OUT MAX24101 MAX24101 N 1 N PGM_IN PGM_OUT PGM_IN PGM_OUT Maxim Integrated 20 MAX24101 Startup Sequence In this example a chain of MAX24101s are loaded with the required 12C slave address 1 Power up the devices 2 Write 12C sequence lt A2h ack 3Ch ack address and OU ack gt 3 The first device is now accessible at its given address address and 0 for the lower channels and address 1 and 0 for the upper channels 4 By accessing the first device the SCL pin is tog gled and hence the program reset signal is propa gated through the devices using the PGM_IN and PGM_OUT pins For long chains a number of access es may be needed before all devices have an assigned address since each access results in 27 SCL transi tions and hence 13 devices are allocated an address To reset the slave address requires a power cycle or setting the ENABLE pin low www maximintegrated com 15Gbps Octal Linear Equalizer Programming Tables Table 6 EQ PEAKING Bit Control EQx 3 0 EQPEAKINGGAIN UNITS ma Ia Table 7 FLAT_GAIN Bit Control re Maxim Integrated 21 MAX24101 15Gbps Octal Linear Equalizer Register Map Table 9 Register Configuration mm 1 Beseeiiesten 1 Reserved read ony EE The register map is split into two sections depending on the I2C address
3. an unpredictable value in the case of a read During burst mode accesses destination addresses are tested on a byte by byte basis Slave Address Configuration The slave address of the MAX24101 I2C can be set using an initialization procedure involving PGM_IN and PGM_OUT in conjunction with the standard 12C signals This procedure facilitates the assignment of a large num ber of slave addresses enabling several MAX24101s to be controlled by a single 12C serial bus and commands All transactions on the 12C bus follow standard protocol allowing simple firmware development SDA DIRECTION TO SLAVE lt _ FROM SLAVE __ _ rr DIRECTION TO SLAVE Figure 10 Read Transaction www maximintegrated com eege S FROM SLAVE 15Gbps Octal Linear Equalizer There is little difference between a normal 12C serial bus and the MAX24101 solution except that there is a new signal which controls the programming of the device addresses This signal is daisy chained through all of the devices on the 12C bus via the PGM_IN and the PGM OUT pins The programming of device addresses is done as a single parallel write to all devices 1 to N The SC bus is the usual SCL and bidirectional SDA with the pullup The program_reset signal is a single bit passed through each device as a flying enable The input pin for this signal is PGM_IN and the corresponding output pin is PGM_OUT The PGM_IN pin on the first MAX24101 in the
4. EQx 3 0 0111 FGx 1 0 10 TXAx 1 0 11 EQx 3 0 0000 25 20 15 10 5 0 5 10 0 2 4 6 8 10 INPUT AMPLITUDE dBV FREQUENCY GHz FREQUENCY RESPONSE FREQUENCY RESPONSE WITH 18in of FR4 5 toc06 5 toc07 d Ee FR4 with EQx 3 0 EQxx 3 0 0111 EQxx 3 0 LL co co Si Si z z S S EQxx 3 0 0010 M EQxx 3 0 0000 TXAx 1 0 11 FGxx 1 0 10 TXAx 1 0 11 FGx 1 0 10 0 2 4 6 8 10 0 2 4 6 8 10 FREQUENCY GHz FREQUENCY GHz www maximintegrated com Maxim Integrated 8 MAX24101 15Gbps Octal Linear Equalizer Typical Operating Characteristics continued Typical values are at Vccr Vect Voc_pDG 2 9V Ta 25 C unless otherwise noted MAX24101 SINGLE ENDED OUTPUT AFTER 18in FR4 AT INPUT EQx 3 0 1110 FGx 1 0 01 TXAx 1 0 11 10 3Gbps 50mV div 20ps div SINGLE ENDED OUTPUT FROM BERT SOURCE 12Gbps toc10 100mV div 20ps div MAX24101 SINGLE ENDED OUTPUT AFTER 18in FR4 AT INPUT EQx 3 0 1110 FGx 1 0 01 TXAx 1 0 11 12Gbps toc12 50mV div 20ps div www maximintegrated com MAX24101 SINGLE ENDED OUTPUT AFTER 18in OF INPUT FR4 EQx 3 0 1110 FGx 1 0 01 TXAx 1 0 11 13 5Gbps toc9 50mV div 20ps div SINGLE ENDED OUTPUT FROM BERT SOURCE AFTER 18in FR4 12Gbps toc11 100mV div SS e regen rm e m mn rn rm 20ps div MAX24101 SINGLE ENDED TIME DOMAIN OUTPUT VS EQUALIZATION LEVEL FGx 1 0 01 TXAx 1 0 11
5. WITH 18in FR4 AT 1Gbps toc13 EQxx 3 0 1111 Deeg ET ee SS ies s ui i p a a e N EQxx 3 0 0000 1 62mV div 100ps div Maxim Integrated 9 MAX24101 15Gbps Octal Linear Equalizer Pin Configuration gt z z Z W4 X E lt 4 in e 2 re oOo _ M IE o g e O 2 D Z WO Go z TX1P TX1N VCCT TX2P TX2N VCCT TX3P TX3N VCCT TX4P TX4N MAX24101 VCCT TXSP TXSN VCCT TX6P TX6N VCCT TX7P TX7N VCCT TX8P TX8N VCCT FCLGA 4mm x 13mm Pin Description nm NAME FUNCTION RX1P RXIN Differential Channel 1 Input CML 3 SE st VCCR Positive Receive Power Supply 2 5V Filter each pin with a 0 1uF capacitor to GND 4 5 RX2P RX2N Differential Channel 2 Input CML www maximintegrated com Maxim Integrated 10 MAX24101 15Gbps Octal Linear Equalizer Pin Description continued nm Iw mem SS PC Enable Input LYVCMOS Hardwire low for pin control Hardwire high for RBC control 25 I2C_EN User must select mode of operation before power on reset VCCP Positive Power Supply 2 5V Filter each pin with a 0 1uF capacitor to GND LDO DIG Compensation capacitor pin for internal LDO Bypass pin with a 0 22uF capacitor to GND CL Analog 12C Serial Interface Clock Input Use external 4 7kQ pullup to Vcc Analog 12C Serial Interface Data Input and Output Use external 4 7kQ pullup to Vcc PGM_OUT Cascadable 12C Output LVCMOS See the Slave Address Configu
6. chain can be tied low or left unconnected because the PGM_IN pin has an internal pulldown resistor TO SLAVE TO SLAVE FROM SLAVE Maxim Integrated 19 MAX24101 LC Address Configuration The new features of this interface compared to a conven tional 12C interface are e The daisy chain PGM_IN and PGM_ OUT pins e A device_address register 7 bits 7 1 Bit O in this register is used as a 12C read write bit e An internal write once bit At power up the write_once bit will be set to 1 and the device 12C address will be set to its default value A2h All MAX24101 devices will respond to read and writes to this slave address until a write to register 3Ch is performed The required I2C address of device 1 7 bit 15Gbps Octal Linear Equalizer address 0 is then assigned by writing to pgm_ register 3Ch at 12C address A2h All devices accept the new address value for example 10h Each device then starts to increment it on SCL edges while PGM_IN is high The program_reset signal ripples down the chain fixing the LC address such that device N has an 12C address of address 0 2 N 1 for example device 1 at 10h and 12h device 2 at 14h and 16h and device 3 at 18h and 1Ah Note that each MAX24101 takes two I2C address es with channels 1 to 4 being controlled by the lower address and channels 5 to 8 from the upper address SDA MAX24101 PGM_IN PGM_OUT PGM_IN
7. of these spreadsheets I2C Interface The SDA and SCL pins are referred to as the slave 12C The slave 12C provides external access to the register set within the MAX24101 Typically an MCU is connected to the slave I2C Framing and Data Transfer An individual transaction is framed by a START condition and a STOP condition A START condition occurs when a bus master pulls SDA low while SCL is high A STOP condition occurs when the bus master allows SDA to tran sition low to high when SCL is high Within the frame the master has exclusive control of the bus The MAX24101 supports Repeated START conditions whereby the mas ter may simultaneously end one frame and start another without releasing the bus by replacing the STOP condition with a START condition Within a frame the state of SDA only changes when SCL is low A data bit is transferred on a low to high transition Vour txa Flatgain vgc Peak Gain eq UPDATE 15Gbps Octal Linear Equalizer of SCL Data is arranged in packets of 9 bits The first 8 bits represent data to be transferred most significant bit MSB first The last bit is an acknowledge bit from the slave The recipient of the data holds SDA low during the ninth clock cycle of a data packet to acknowledge ACK the byte Leaving SDA left open on the ninth bit signals a not acknowledged NACK condition The interpretation of the acknowledge bit by the sender depends on the type of transaction and the natu
8. the package regardless of ROHS status ED Exposed pad PACKAGE PACKAGE OUTLINE LAND Chip Information TYPE CODE NO PATTERN NO PROCESS SiGe BICMOS eo FcLGAP teoaarwes 2120650 90 0407 www maximintegrated com Maxim Integrated 26 MAX24101 15Gbps Octal Linear Equalizer Revision History REVISION REVISION PAGES NUMBER DATE OE SCRIT OT CHANGED 11 13 Initial release For pricing delivery and ordering information please contact Maxim Direct at 1 888 629 4642 or visit Maxim Integrated s website at www maximintegrated com Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product No circuit patent licenses are implied Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time The parametric values min and max limits shown in the Electrical Characteristics table are guaranteed Other parametric values quoted in this data sheet are provided for guidance Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products Inc 2013 Maxim Integrated Products Inc 27
9. used In general the lower address controls the lower four channels and the upper I2C address controls the upper four channels Register 01h Lower I2C Address Channel 1 er 7 fe s 3 2 1 0 DEFAULT VALUE ACCESS EQ1 3 0 Sets the equalizer peaking for channel 1 See Table 6 for values FG1 1 0 Sets the flat gain for channel 1 See Table 7 for values TXA1 1 0 Sets the output amplitude for channel 1 See Table 8 for values Register 02h Lower I2C Address Channel 2 o BT 7 6e 5 4 3 2 DEFAULT VALUE ACCESS EQ2 3 0 Sets the equalizer peaking for channel 2 See Table 6 for values FG2 1 0 Sets the flat gain for channel 2 See Table 7 for values TXA2 1 0 Sets the output amplitude for channel 2 See Table 8 for values www maximintegrated com Maxim Integrated 22 MAX24101 15Gbps Octal Linear Equalizer Register 03h Lower I2C Address Channel 3 er 7 6 5 3 2 7 0 DEFAULT VALUE ACCESS EQ3 3 0 Sets the equalizer peaking for channel 3 See Table 6 for values FG3 1 0 Sets the flat gain for channel 3 See Table 7 for values TXA3 1 0 Sets the output amplitude for channel 3 See Table 8 for values Register 04h Lower I2C Address Channel 4 er 7 6 8 8 2 4 6 DEFAULT VALUE ACCESS EQ4 3 0 Sets the equalizer peaking for channel 3 See Table 6 for values FG4 1 0 Sets the flat gain for channel 3 See Table 7 for v
10. 11 D 12 EQx 3 0 1001 12 EQx 3 0 1001 9 EQx 3 0 0101 Table 3 FLAT_GAIN Pin Control 9 EQx 3 0 0101 Eu LONG CHANNEL MEDIUM CHANNEL SHORT CHANNEL UNTE APPLICATION LOW OPEN APPLICATION OPEN APPLICATION HIGH 1 7 FGx 1 0 11 1 7 FGx 1 0 11 0 1 FGx 1 0 10 0 1 FGx 1 0 10 0 1 FGx 1 0 10 1 4 FGx 1 0 01 1 4 FGx 1 0 01 1 4 FGx 1 0 01 2 9 FGx 1 0 00 Table 4 OUTPUT LEVEL Pin Control INPUT LEVEL OUTPUT AMPLITUDE UNITS 000 XATO T 940 TXAx 1 0 10 Vp p tow 700 TXAX1 0 01 Table 5 ENABLE and Reset Pin Control INPUT LEVEL GC CONTROL MODE ENABLE UGC EN high PIN CONTROL MODE GC EN low Upon POR or reset power down all channels Power down all channels Upon POR or reset power on all channels Power on all channels Reset POR Reset POR www maximintegrated com Maxim Integrated 13 MAX24101 Applications Information Linear Equalizer EQ Placement and Use in 3 Steps Placement of linear equalizers in lossy channels is bounded by output linearity and input noise IRN See Figure 5 Although placement is quite flexible it is important to maintain linear operation with sufficient SNR hence the boundary conditions stated in the following two sections Tx1Vp p W 6dB PE 2 0V POSITION 1 15Gbps Octal Linear Equalizer Definitions dBV is defined as dB relative to 1Vp _p differential Hence the Tx leve
11. EN Longest Channel dB lt eee Ree Over PVT gt OverPVT lt 28 02 dR OverPVT lt 43 02 aB T CH Input Ref J n Anput Ref m 7777 T F P N M Keeps Nyquist 010101 Keeps Nyquist 010101 level above Keeps Nyquist 010101 level sufficiently level below EQ HF above EQ IRN input referred noise above DFE IRN input referred noise compression level to meet BER and constrain RJ gen to meet BER and constrain RJ generation A Farthest from Rx dB lt B Nearest to Rx dB gt 6 02 dB Over PVT lt Over PVT gt 8 02 dB CH Output Ref N M n output N Keeps Nyquist above Keeps EQ ORN output ref noise DFE IRN to meet BER below DFE IRN input ref noise If using Typical specs add and constrain RJ gen including channel loss on noise Margin for PVT Variation dB Figure 7 EQ Placement Calculator www maximintegrated com Maxim Integrated 17 MAX24101 Write Transaction In a write transaction the address byte is successfully acknowledged by the slave and the type bit is set low After the first acknowledge the master sends a single data byte All signaling is controlled by the master except for the SDA line during the acknowledge bits During the acknowledge cycle the direction of the SDA line is reversed and the slave pulls SDA low to return a 0 ACK to the master The MAX24101 interprets the first data byte as a register address This is u
12. FE Achieve BER Goals e Lower Power Lower Cost And Smaller Board Footprint Than CDR Solutions e Transparent to Link Training OOB And Idle e Plug and Play Set Control Pins All Channels Set the Same or Independent Control of Each Channel through 12C Bus e 2C Daisy Chain For Addressing Up to 63 ICs e Selectable EQ Peaking Spanning 6dB to 19dB at 7 5GHz e Selectable Flat Gain Spanning 2 9dB to 1 7dB e Selectable Output Linear Swing Spanning 700mVp _p to 1000mVp _p e Low Input Referred Noise lt 1MVRMS e Data Rate and Coding Agnostic e Input Return Loss Better Than 16dB Typical Up to 7 5GHz e Power Down Mode Saves Power When Not In Use e 4mm x 13mm FCLGA Package e Single 2 5V Supply e 131mW Per Channel Power Dissipation with a 700mVp _p Output MAX24101 MAX LOSS CHANNEL 48dB AT 7 5GHz BACKPLANE 4dB TO 12dB LOSS AT 7 5GHz 6dB TO 24dB LOSS AT 7 5GHz 4dB TO 12dB LOSS AT 7 9GHz INCLUDING CONNECTORS Ordering Information appears at end of data sheet For related parts and recommended products to use with this part refer to 19 6804 Rev 0 11 13 www maximinteqrated com MAX24101 related maxim integrated MAX24101 15Gbps Octal Linear Equalizer Absolute Maximum Ratings Power Supply Voltage cccccsecceceseeeeeeeeeeeeees 0 5V to 4 0V Output Current ce ccccceecceceeeececeeeeeeeeeeeeees 90mA to 90mA DC Input Voltage Applied all control pins except SDA Operati
13. MAX24101 General Description The MAX24101 restores high frequency signal level at the decision feedback equalizer DFE receiver for high loss backplane and cable channels This permits the DFE receiver to meet BER goals At 15Gbps the MAX24101 can operate in channels with FR4 and cable HF loss more of than 30dB at 7 5GHz The linear transfer function is transparent to Adaptive DFE equalizers permitting DFE adaptation to track temperature and changing channel conditions Together with the DFE integrated into Serializer Deserializer SERDES the device adds increased mar gin rather than full signal regeneration Unlike conven tional equalizers with limiting output stages the device preserves the linear channel characteristics allowing the DFE to linearly operate over the entire channel This permits extending total channel reach and or improving signal to noise ratio SNR The device typically compen sates for up to 19dB of the total loss in a long channel effectively reducing the channel length seen by the DFE receiver The device has 8 channels and is packaged in a space saving 4mm x 13mm FCLGA package Applications 1Gbps to 15Gbps High Speed Backplanes and Cables 12 5Gbps Quad XAUI Interconnect 14Gbps 16G Fiber Channel 12Gbps SAS III Typical Application Circuit MAX24101 15Gbps Octal Linear Equalizer Benefits and Features e 1Gbps to 15Gbps Linear EQ e Increases High Frequency Signal Level To Help Rx D
14. alues TXA4 1 0 Sets the output amplitude for channel 3 See Table 8 for values Register 05h Lower I2C Address Channel 1 4 Controls Fa Ee ee ee ee ee ee NAME REGCONT14 CH1OFF CH2OFF CH3OFF CH4OFF DEFAULT VALUE ACCESS REGCONT14 Selects channel settings for channels 1 4 from pin control or I C accessible registers 0 pin control equalizer peaking flat gain and output amplitude 1 12C accessible registers CH10OFF Disables channel 1 0 enabled 1 disabled CH2OFF Disables channel 2 0 enabled 1 disabled CH30FF Disables channel 3 0 enabled 1 disabled CH4OFF Disables channel A 0 enabled 1 disabled Register 01h Upper I2C Address Channel 5 m 7 DEFAULT VALUE ACCESS EQ5 3 0 Sets the equalizer peaking for channel 5 See Table 6 for values FG5 1 0 Sets the flat gain for channel 5 See Table 7 for values TXA5 1 0 Sets the output amplitude for channel 5 See Table 8 for values www maximintegrated com Maxim Integrated 23 MAX24101 15Gbps Octal Linear Equalizer Register 02h Upper I2C Address Channel 6 er 7 8 3 2 4 7 0 DEFAULT VALUE ACCESS EQ6 3 0 Sets the equalizer peaking for channel 6 See Table 6 for values FG6 1 0 Sets the flat gain for channel 6 See Table 7 for values TXA6 1 0 Sets the output amplitude for channel 6 See Table 8 for values Register 03h Upper 12C Address Chan
15. es are at Vccr Voct Vece 2 5V Ta 25 C See Figure 1 for typical supply filtering Note 2 PARAMETER SYMBOL CONDITIONS UNITS Supply Current current with all 8 channels enabled TXAx 1 0 11 E a Power Down l www maximintegrated com Maxim Integrated 2 MAX24101 15Gbps Octal Linear Equalizer Electrical Characteristics continued Typical values are at Vecer Vect Vecer 2 5V Ta 25 C See Figure 1 for typical supply filtering Note 2 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Beyond steady state supply current Inrush Current with supply ramp up time less than lt 10 200us Over bit rate with EQ peaking optimized for loss channel in linear range EQx 3 0 1110 18 5 EQx 3 0 1001 15 7 EQx 3 0 0101 13 2 Ta 85 C 3 67 0 82 Variation around Ta 25 C 1 61 1 96 typical TA 40 C 1 62 3 60 FGx 1 0 11 1 68 GNF Residual Deterministic Jitter Notes 3 4 PSPP Peaking Gain Compensation at 7 5GHz relative to 100MHZ 100mVp_p Sine Wave Input FGx 1 0 10 0 14 FGx 1 0 01 1 36 FGx 1 0 00 2 87 H Ta 85 C 4 05 0 95 Variation around Ty 25 C 3 32 1 83 typical Ta 40 C 3 40 2 86 TXAx 1 0 11 1000 1370 1dB Compression Point TXAx 1 0 10 1280 V1dB_OUT Flat Gain 100MHz EQx 3 0 1000 TXAx 1 0 10 3 lt fe Output Swing at 100MHz TXAx 1 0 01 1040 TXAx 1 0 00 920 TXAx 1 0 11 1000 1dB Compre
16. ing Gain 14dB Linear EQ Flat Gain 0dB Linear EQ Output Level setting 1dB Compression Point 3dBV User System Margin 2dB Then Minimum Distance Nyquist Loss from Source Tx 0 14 0 3 2 19dB Step 3 Keep Nyquist Level Sufficiently Above Noise Floor The amplitude of the Nyquist sequence 10101010 must be maintained sufficiently above noise floor to achieve BER goals Hence Nyquist level at input to the Linear EQ needs to be sufficiently above the Linear EQ self noise IRN input referred noise This sets the maximum Nyquist channel loss preceding the Linear EQ e g farthest placement from Source Tx see Position 2 in Figure 5 Maximum Distance Nyquist Loss from Source Tx dB Source Tx Level which is Nyquist level dBV Linear EQ IRNpp at BER goal dBV Margin required to reduce RJ creation User System Margin dB For example Source Tx Level OdBV Linear EQ IRNpp at BER goal 0 5mVrms x 15 9 at BER 1E 15 dBV 43dB Margin required to reduce RJ creation to 0 2Ulpp at BER 10dB User System Margin 3dB Then Maximum Distance Nyquist Loss from Source Tx 0 43 10 3 30dB Maxim Integrated 15 MAX24101 Tools Frequency Response Plotting and EQ Placement in Channel Calculator Several simple Microsoft Excel spreadsheet tools are available to assist in the application of the MAX24101 Linear EQs Please visit www maximintegrated com to access the latest version
17. ith pin control the equalization setting has three avail able compensation levels and all the channels are con trolled globally See Table 2 for details With the I2C serial bus the equalization has 16 settings and each channel can be adjusted independently Gain Stage The MAX24101 data path goes through a wideband flat gain stage With pin control the flat gain can be adjusted globally from 2 9dB to 1 7dB as shown in Table 3 With Table 2 EQ PEAKING Pin Control LONG CHANNEL MEDIUM CHANNEL SHORT CHANNEL INPUT LEVEL NIT APPLICATION LOW OPEN APPLICATION OPEN APPLICATION HIGH 15Gbps Octal Linear Equalizer I2C control the flat gain can be adjusted independently for each channel Output Stage The MAX24101 data path transitions from the gain stages into a linear output buffer with selectable output level With pin control the output levels can be adjusted globally as shown in Table 4 With LSC control the output levels can be adjusted independently for each channel Power Saving The MAX24101 features a power down enable input ENABLE pin to shut down the device and reduce sup ply current at startup Set high to power down the output stage of all channels Set open to power up all channels Set low for reset Reset disables all communication to the chip along with resetting the registers to their default states 15 EQx 3 0 1110 15 EQx 3 0 1110 12 EQx 3 0 1001 6 EQx 3 0 00
18. l of 1Vp_p is OdBV and a Tx level of 0 5Vp_p is 6dBV Source Tx Level dBV is the total measured Tx Vp_p including pre emphasis Desired Margin is a user decision regarding margin needed to account for all system min max variations including source Tx MAX24101 and ASIC receiver POSITION 2 LINEAR EQ OUTPUT REFERRED 1dB COMPRESSION LEVEL Vp p 8 CHANNEL LOSS dB Figure 5 Linear Equalizer Placement www maximintegrated com DESIGN MARGIN J i DFE IRN AT BER TOTAL GAIN AT NYQUIST 208 Es z Se PLACEMENT RANGE IN LOSSY CHANNEL Maxim Integrated 14 MAX24101 Step 1 Maintain EQ Linearity at Low Frequency LF The source Tx low frequency LF amplitude needs to be considered to keep linear EQ within its linear range The source Tx low frequency LF amplitude is the differential peak peak amplitude after any pre emphasis has fully set tled e g the level of long CID continuous identical digits sequences The primary controls over LF levels in Linear EQ are the Used ASIC Source Tx pre emphasis or de emphasis and the Linear EQ Flat Gain MAX24101 Figure 5 shows a typical example with ASIC Source Tx having 6dB pre emphasis with 1Vp p peak swing and 0 5Vp_p swing after pre emphasis e g long CID LF content Note that 0 5Vp _p fits easily under the 1dB Compression line If the Source Tx were to have higher LF swing driving linear EQ into nonlinearity the linear EQ flat gain cont
19. nel 7 er 7 es 8s 3s 2 7 0 DEFAULT VALUE ACCESS EQ7 3 0 Sets the equalizer peaking for channel 7 See Table 6 for values FG7 1 0 Sets the flat gain for channel 7 See Table 7 for values TXA7 1 0 Sets the output amplitude for channel 7 See Table 8 for values Register 04h Upper I2C Address Channel 8 o Bt 7 e 5 4 3 2 1 0 DEFAULT VALUE ACCESS EQ8 3 0 Sets the equalizer peaking for channel 8 See Table 6 for values FG8 1 0 Sets the flat gain for channel 8 See Table 7 for values TXA8 1 0 Sets the output amplitude for channel 8 See Table 8 for values Register 05h Upper I2C Address Channel 5 8 Controls er 7 6 5s 3 2 477 0 DEFAULT VALUE REGCONT58 Selects channel settings for channels 5 8 from pin control or HRC accessible registers 0 pin control equalizer peaking flat gain and output amplitude 1 12C accessible registers CH5OFF Disables channel 5 0 enabled 1 disabled CH6OFF Disables channel 6 0 enabled 1 disabled CH7OFF Disables channel 7 0 enabled 1 disabled CH8OFF Disables channel 8 0 enabled 1 disabled www maximintegrated com Maxim Integrated 24 MAX24101 Exposed Pad Package The exposed pad of the MAX24101 package incorpo rates features that provide a very low thermal resistance path for heat removal from the IC The exposed pad on the MAX24101 must be soldered to the circuit b
20. nel has a program mable equalization network and programmable flat gain adjust All controls for equalization gain output enable disable etc are individually programmed through the on chip programming block The programming block can be controlled either through pin controls or the 12C serial bus APPLICATION Pin Control The placement range of a linear equalizer is limited by its dynamic range and noise performance To allow the widest placement range the MAX24101 has two optimi zations The two cases are Short and Long Channels By selecting the case based on channel loss as shown in Table 1 the best dynamic range and noise operating points are selected for the application www maximintegrated com FLAT GAIN OUTPUT LEVEL Input Termination The input termination consists of two 500 resistors form ing a differential termination between the input pins The excellent return loss minimizes reflections in a channel Table 1 APPLICATION Pin Control High Short Channel 0dB to 18dB channel loss g before MAX24101 Low Open Long Channel 18dB to 33dB channel loss before MAX24101 Maxim Integrated 12 MAX24101 Receive Equalizer For the MAX24101 the input data goes into a selectable equalization stage The receive equalizer is designed to compensate losses up to 19dB at 7 5GHz of channel loss The selectable equalization can be controlled using commands sent over the I2C serial bus or pin control W
21. ng Junction Temperature nna0annnennnneanenanennn 125 C lee D WE 0 5V to Vcc 0 3V Storage Temperature Range n 01nnnnn0111eeee 40 C to 150 C DC Input Voltage Applied SDA SCL 0 5V to 4 0V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Package Thermal Characteristics Note 1 FCLGA Junction to Case Thermal Resistance Oic 10 C W Junction to Ambient Thermal Resistance Oya EIA JESD51 2 standard 29 C W Note 1 Package thermal resistances were obtained using the method described in JEDEC specification JESD51 7 using a four layer board For detailed information on package thermal considerations refer to www maximintegrated com thermal tutorial Operating Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Ambient ene re Be Data Coding and DC balanced NRZ 8B10B or CID CID Scrambled PRBS31 l l LF Baseline without PE Differential Source Diff Low VLAUNCH measured at source source HF 1200 mVp_p Frequency Voltage l pre emphasis swing can be higher Noise Electrical Characteristics Typical valu
22. oard for proper thermal performance and correct electrical grounding For more information on exposed pad pack ages refer to Maxim Application Note 862 HFAN 08 1 Thermal Considerations of QFN and Other Exposed Paddle Packages Interface Schematics MAX24101 Figure 12 CML Equivalent Input Structure www maximintegrated com 15Gbps Octal Linear Equalizer Layout Considerations Circuit board layout and design can significantly affect the performance of the MAX24101 Use good high frequency design techniques including minimizing ground induc tance and using controlled impedance transmission lines on the data signals Power supply decoupling should also be placed as close to the Vcc pins as possible There should be sufficient supply filtering Always connect all Vccs to a power plane Take care to isolate the input from the output signals to reduce feed through MAX24101 Figure 13 CML Equivalent Output Structure Maxim Integrated 25 MAX24101 15Gbps Octal Linear Equalizer Ordering Information Package Information PART TEMP RANGE PIN PACKAGE For the latest package outline information and land patterns S footprints go to www maximintegrated com packages Note MAX24101ELU 20 to 85 C 60 FCLGA EP that a or in the package code indicates RoHS status Denotes a lead Pb free ROHS compliant package only Package drawings may show a different suffix character but the drawing pertains to
23. oise AdBVpp BER L TX LF Level long CID dBVpp CH HF 1dB Compr Level dBVpp D TX De Emphasis dB n Noise ABVpp BER L T D P Peaking Gain HF re LF dB F Flat Gain LF dB Loss A LINEAR EQ Placement Range MEASUREMENT DEFINITIONS HF 0101010101 Sq Wave Nyquist LF Long CID Sq Wave 100MHz Peaking Gain Gain HF relative to LF Noise BW 10MHz to Nyquist Loss C Entry Box in Yellow Pull Down Box in Pink Pull Down Entry Box in Yellow ASIC TX SETTINGS LINEAR EQ SETTINGS ASIC RX SETTINGS T Tx HF Level mVpp P Peaking Gain HF reLF dB 15 N Input Ref Noise dBVrms ABVpp 000 F Flat Gain LF dB H Vpp dBVpp 42 0 D Tx De Emphasis dB 3 0 Input Ref Mult Output Ref n Refer d Noise mVrms M Margin dB 120 STEP 1 Make sure that L Tx LF Level mVpp Nyquist 010101 Vpp above N Vpp BER is less than EQ LF compression level dBVpp recommend gt 16dB for RJ lt 0 10Ulpp L Tx LF Level mVpp lt CL LF 1dB Compress mVpp recommend gt 12dB for RJ lt 0 16Ulpp dBVpp dBVpp CH HF 1dB Compress mVpp BER Target 1E xx where xx dBVpp Vpp Vrms Multiplier for BER in 1E 12 to 1E 17 range 12 0 m Margin dB Nyquist above n dBVpp BER recommend gt 16dB for RJ lt 0 10Ulpp recommend gt 12dB for RJ lt 0 16Ulpp RESULTS EQ PLACEMENT Loss Nyauist cA Nearest to Tx dB gt 16 94 B Farthest from Tx dB lt G
24. racteristics Typical values are at Vccr Vect Voc pe 2 5V Ta 25 C unless otherwise noted DETERMINISTIC JITTER DETERMINISTIC JITTER Jap Compression vs EQUALIZATION SETTING vs EQUALIZATION SETTING p 7 5GHz Nyquist toc01 toc02 toc03 0 25 0 35 oc 5 oc Ba 0 30 3dB Loss Linear Es TXAx 1 0 11 a 0 20 a Geen 0 Range Operation Py 0 25 2 y D D St BZ TXAx 1 0 00 e CH 0 15 16 7dB Loss Linear 4 0 20 16 7dB toss linear gt 5 3dB Loss Linear Range Operation Range Operation S Range Operation 010 g 0i SEH o ad A LUI LUI tu a oi 2 el el 0 05 15 0 05 Data Rate 10 3Gbps TXAx 1 0 10 FGx 1 0 10 Data Rate 15Gbps TXAx 1 0 10 FGx 2 0 10 EQx 3 0 0111 FGx 1 0 10 0 00 0 00 20 0000 0010 0100 0110 1000 1010 1100 1110 0000 0010 0100 0110 1000 1010 1100 1110 30 25 20 15 10 5 EQUALIZATION SETTING EQxx 3 0 EQUALIZATION SETTING EQxx 3 0 INPUT AMPLITUDE dBV 1dB COMPRESSION 100MHz Nyquist FREQUENCY RESPONSE 10 0 oS 30 toc05 FGx 1 0 111 gt a a FGx 1 0 01 TXAx 1 0 00 _ co a E z S S x 1 0 00 D A D a
25. ration section e SS H VCCT Positive Transmit Power Supply 2 5V Filter each pin with a 0 1uF capacitor to GND Power Down Enable Pin LVCMOS Three state pin to program the power mode of the 56 ENABLE part at startup For high and open see Table 5 for settings Set low for reset Reset disables all communication to the chip along with resetting the registers to their default states 57 APPLICATION Application Select Input LVCMOS Select between channel cases Short and Long Set low or open for long Set high for short 58 OUTPUT LEVEL Output Level Control LVCMOS Three state pin to program the output level of all e channels See Table 4 for settings 59 EQ PEAKING Equalization Control Pin LVCMOS Three state pin to program the equalization level of all channels See Table 2 for settings Gain Adjust Control Pin LYCMOS Three state pin to program the flat gain level of all FLAT GAIN channels See Table 3 for settings Exposed Pad Internally connected to GND Ground reference for power supplies three EP state and other low speed pins Connect EP to a large ground plane to maximize thermal performance www maximintegrated com Maxim Integrated 11 MAX24101 Functional Diagram LANE 1 OF 8 15Gbps Octal Linear Equalizer 8 CHANNELS OUTPUT BUFFER EQUALIZER FLAT GAIN a JJJ mg CONTROL EQ PEAKING Detailed Description The MAX24101 is an 8 channel linear equalizer EQ functioning up to 15Gbps Each chan
26. re of the byte being received SDA is bidirectional so that the master may send data bytes during write transactions and the slave may send data bytes during reads Device Addressing The first byte to be sent after a START condition is a slave address byte The first seven bits of the byte contain the target slave address MSB first The eighth bit indicates the transaction type 0 write 1 read Each slave interface on the bus is assigned a 7 bit slave address If no slave matches the address broadcast by the master then SDA will be left open during the acknowledge bit and the master receives a NACK The master must then assert a STOP condition If a slave identifies the address then it acknowledges it by pulling SDA low The master then proceeds with the transaction identified by the type bit The two wire interface of the MAX24101 decodes slave addresses ranging from OOh to 3Fh MAX24101 FREQUENCY RESPONSE MAX24101 TXA2 MECH EQ15 TXA2 VGC EQ7 TXA1 VGC1 EQ3 TXA0 VGO EQO Figure 6 Frequency Response Plotting Microsoft Excel is a registered trademark of Microsoft Corp www maximintegrated com 1E 10 Frequency Hz Maxim Integrated 16 MAX24101 15Gbps Octal Linear Equalizer MAX24101 10 3Gbps Linear EQ Calculate Placement Range in Channel ASIC TX LINEAR EQ ASIC RX T TX HF Level Nyquist ABVpp CL LF 1dB Compr Level ABVpp N Input Referred N
27. rol can be used to attenuate input signal level as needed to maintain linearity For example Maximum Linear EQ Flat Gain setting Linear EQ Output Level setting 1dB compression dBV Source Tx Level dBV Source Tx Pre Emphasis De emphasis dB User System Margin dB For example Linear EQ Output Level setting 1dB compression dBV 3dBV Source Tx Level dBV O0dB Source Tx Pre Emphasis De emphasis dB 6dB User System Margin 2dB Then Maximum Linear EQ Flat Gain setting 3 0 6 2 1dB There are three Flat Gain settings available lower than 1dB They are 3dB 1 5dB OdB Step 2 Maintain EQ Linearity at High Frequency Nyquist A linear equalizer when placed too close to a Source Tx is vulnerable to nonlinear compression at high frequency Nyquist especially if the EQ peaking gain is higher than the preceding channel loss The 1dB compression specification gives maximum output level that guarantees linear operation As a function of the EQ settings the mini mum placement distance from the Source Tx is calculated as follows see Position 1 in Figure 5 www maximintegrated com 15Gbps Octal Linear Equalizer Minimum Distance Nyquist Loss from Source Tx dB Source Tx Level dBV Linear EQ Peaking Gain dB Linear EQ Flat Gain dB Linear EQ Output Level setting 1dB Compression level ABV User System Margin dB For example Source Tx Level OdBV Linear EQ Peak
28. sed to set an internal memory pointer Subsequent data bytes within the same transaction will then be written to the memory location addressed by the pointer The pointer is auto incremented after each byte There is no limit to the number of bytes which may be written in a single burst to the internal registers of the MAX24101 ADDRESS 15Gbps Octal Linear Equalizer Read Transaction In a read transaction the slave address byte is success fully acknowledged by the slave and the type bit is set high After the ACK the slave returns a byte from the loca tion identified by the internal memory pointer This pointer is then auto incremented The slave then releases SDA so that the master can ACK the byte If the slave receives an ACK then it will send another byte The master identi fies the last byte by sending a NACK to the slave The master then issues a STOP to terminate the transaction Thus to implement a random access read transaction a write must first be issued by the master containing a slave address byte and a single data byte the register address This sets up the memory pointer A read is then sent to retrieve data from this address Figure 8 Device Addressing www maximintegrated com Maxim Integrated 18 MAX24101 I2C Access Destination The MAX24101 does not provide any security level on the I2C serial bus Accesses to unimplemented registers in the device are discarded in the case of a write and return
29. ssion Point TXAx 1 0 10 940 Output Swing Note 5 at V1dB OUT 3 lt fe 4 7 5GHz TXAx 1 0 01 700 i TXAx 1 0 00 100MHz to 7 5GHz FGx 1 0 11 EQx 3 0 0000 Figure 3 Input Referred Noise VNOISE 100MHz to 7 5GHz FGx 1 0 11 EQx 3 0 1010 Figure 3 100MHz to 7 5GHz FGx 1 0 11 Output Referred Noise EQx 3 0 0000 Figure 3 Note 3 VNOISE Sg Note 3 100MHz to 7 5GHz FGx 1 0 11 a EQx 3 0 1010 Figure 3 l l www maximintegrated com Maxim Integrated 3 MVRMS o1 MVRMS O MAX24101 15Gbps Octal Linear Equalizer Electrical Characteristics continued Typical values are at Vccr Vect Vecp 2 5V Ta 25 C See Figure 1 for typical supply filtering Note 2 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS HIGH SPEED I O DC differential resistance Input Resistance RIN AC common mode single ended Ss Q resistance 40MHz to 7 5GHz Differential Input Return Loss 44 DC differential resistance ROUT AC common mode single ended resistance Output Resistance 10MHz to 7 5GHz Output Return Loss S e 1GHz to 7 5GHz Common Mode Channel Isolation Vooup es to 7 5GHz Figure 4 LVCMOS I O Q1 TO Wu Differential gt 13 V CO D D iN O ER 0 7 x Vcc Input Logic High Voltage Vec 0 3 Input Logic Low Voltage 0 3 Es Output Logic High Voltage Output Logic Low Voltage At lou 200A VIH VIL VoH Vo 0 2 L At lo 200A
30. te 6 Measured using a vector network analyzer VNA with 15dBm power level applied to the adjacent input The VNA detects the signal at the output of the victim channel All other inputs and outputs are terminated with 50Q Note 7 Refer to UM10204 I2C bus specification and user manual Rev 03 19 June 2007 www maximintegrated com Maxim Integrated 5 MAX24101 15Gbps Octal Linear Equalizer 1uH 2 5V V SUPPLY E A CC 100uF 0 1uF 100uF 0 1uF too tows Figure 1 Recommended Supply Filtering RECEIVE TEST SETUP PCB FRA SIGNAL 3 OSCILLOSCOPE OR SOURCE d x MAX24101 BIT ERROR DETECTOR SMA a N SMA CONNECTORS ain lt L lt 30in CONNECTORS Al FR4 4 0 lt ER lt 4 4 tand 0 022 Figure 2 Receiver Test Setup Points Labeled A B and D are Referenced for AC Parameter Test Conditions www maximintegrated com Maxim Integrated 6 MAX24101 MAX24101 TX_ TX_ 15Gbps Octal Linear Equalizer LOWPASS FILTER BALUN POWER METER PSPL 5315A GIGATRONICS 8652A 200kHz TO 17GHz WITH 80301A HEAD 10MHz to 18GHz 4TH OBT Figure 3 Noise Test Configuration AGGRESSOR SIGNAL 0dBm VICTIM 599 INPUT Figure 4 Channel lsolation Test Configuration www maximintegrated com 4 PORT VECTOR NETWORK ANALYZER N52454 MAX24101 RX1 TX1 RX1 TX1 RX2 TX2 RX2 TX2 Maxim Integrated 7 MAX24101 15Gbps Octal Linear Equalizer Typical Operating Cha
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