Datasheet
Contents
1. 4 5 GPIO Interface There is one 2x3 0 1 header for a GPIO interface This interface contains 4 single ended lines that can be used for general purpose I O However there are some limitations on the IO direction GPIO Out lines can be used for bi directional signals however GPIO Input can only be used as a host board input signal 21 Terasic HSMC Communication Card User Manual www terasic com www terasir pom LL OUT 2 0 2x3 Header 6001 Figure 4 5 GPIO Interface Block Diagram The GPIO head contains 6 pins with the following pin out Table 4 9 GPIO Header Pin out Pin Name Direction Description em Gro 4 6 DVI Output DVI Output with be able to support standard DVI D interface targeting UXGA resolution that implies pixel rate of 165MHz The block diagram is presented on the next figure DATA 0 23 gt Data CLK 0 3 Diff EMEN vu I2C can be shared with other devices Figure 4 6 DVI Interface Block Diagram 22 Terasic HSMC Communication Card User Manual www terasic com www CBrasID DOM The purpose of DVI transmitter is to arrange the inbound pixels and generic sync signals to be compatible with DVI interface standard and transmit the encoded data over 4 differential lanes These lanes are routed to standard DVI connector so it can be connected to imaging device with standard cable The image data is loaded to transmitter through HSMC interface accompanied by2. OMM User Manual HSMC Communication Card i01010101000101010101010101010100101010111010100T0TOTOOTDOTOTOTOTOTOTOO TOTOTO TOTO TOTO TO TQ 10101010100010101010101010101010010101011101010010101001007010101010100101010 NN 101010101000101010101010101010100101011 0101 10100100101010101010 01010 010 0101 510100101 1010101010001010101010101 10101001010101710101001010100100101010101010010101010101 t 10101010100010101010101010101010010101011101010070101001001010101010100101010101010107101010700710717101010171011000101111010011010 00000 T EEE 101010101000101010101010101010100101010111010100101010010010101010 101010101000101010101010101010100101010111010100101010 p0701010101001010101010101010101010010110101 www terasic com Copyright O 2003 2011 Terasic Technologies Inc All Rights Reserved CONTENTS Chapter 1 INUA UA aa AAA AAA AA AAA 3 LT 3 EG a AA TAA NE EEE 4 Chapter 2 Ane AA EE 5 DR Ta ele ID l NO LI TAL E ED DE E ED DD DD OOO Se ea E RB nd 6 Chapter 3 FA SC UPON PERAN tk io E m m 7 3 1 HSMC Expansion Bree Rm m a ia ia aa SR vap ko aa aka 7 Chapter 4 COMPONCIIS ee ads 14 ROTEN tice ces id Si 14 Se oa m 16 TRV NNN 17 FONT 21 A PES T CO a E EEN 21 TON 22 TDN 24 TPM 25 TT 25 Chapter 5 AD 01 10 0 DO EEE EN EE SE 27 SM ka WA Z Z 1000 RD ee 21 JA COPY Sa Aa 27 2 Terasic HSMC Communication Card User Manual www terasic com Www Cerag
3. www terasic cao Pin Number 134 149 146 97 157 138 137 119 115 113 107 103 101 92 90 86 84 133 91 89 85 83 128 126 122 116 110 104 102 139 143 67 151 40 155 98 41 44 56 Terasic HSMC Communication Card User Manual www Denai COM Table 3 1 The pin mappings of the HSMC connector Signal Name CAN 0 RX CAN 0 TX CAN 1 RX CAN 1 TX DVI CLK DVI DATA 0 DVI DATA I DVI DATA 10 DVI DATA 11 DVI DATA 12 DVI DATA 13 DVI DATA 14 DVI DATA 15 DVI DATA 16 DVI DATA 17 DVI DATA 18 DVI DATA 19 DVI DATA 2 DVI DATA 20 DVI DATA 21 DVI DATA 22 DVI DATA 23 DVI DATA 3 DVI DATA 4 DVI DATA 5 DVI DATA 6 DVI DATA 7 DVI DATA 8 DVI DATA 9 DVI DE DVI HSYNC LLL 20 21 22 23 DVI INTn OUT DVI VSYNC ENET CONN RX CLK ENET GTX CLK ENET INTn ENET MDC ENET MDIO ENET RESETn Direction Output Input Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Output Input Output Input Bi directional Input 11 HSMC Expansion Connector Function CAN Receive Data Output CAN Transmit Data Input CAN Receive Data Output CAN Transmit Data Input DVI Transmitter CLK DVI Transmitter Data Bit 0 DVI Transmitte
4. BrAaSIC com www terasic com NUTS RA 4 7 SD SDIO MMC reader Memory Card Reader interface block diagram is shown on the next figure Data 0 3 gt Data 0 3 gt t CMD gt CLK gt lt CLK_RET Figure 4 7 SD Card Reader Block Diagram This interface should include bi directional voltage translators in order to be compatible with SD SDIO cards standard voltage levels The Storage Cards will be plugged into on board connector which will support hot plugging of the card The following table describes the SD Card pin out Table 4 11 SD Card Reader Socket Pin out Pin Name Direction Description 1 CD DAT3 Bidir Card Detect Data line 2 CMD Bidir Command Response 3 Vss Power Ground 4 Vdd Power Supply Voltage 5 CLK Input Clock 6 Vss2 Power Ground 7 DATO Bidir Data line 0 8 DATI Bidir Data line 1 9 DAT Bidir Data line 2 In addition to card interface the card socket contains two physical switches that used to detect card insertion de insertion and status on the write protect switch on the card The status of these switches is routed to HSMC interface as well SD Card bus time diagram is shown below 24 Terasic HSMC Communication Card User Manual www terasic com WAUA Dom VIH VIL VIH Input VIL VOH Output VOL tO DLY max to DLY min Shaded areas are not valid Figure 4 8 SD Card Signal Timing 4 8 EEPROM The Microchip Technol
5. d 120 sn 4 CAN 1 TX CAN 1 RX Figure 2 3 Block diagram of the HSMC Communication card 6 Terasic HSMC Communication Card User Manual www terasic com www Cerai COM ANERAS Chapter 3 Pin Description This chapter describes the detailed information of the connector interfaces and the pin description on the HSMC Communication card 3 1 HSMC Expansion Connector The HSMC Communication card contains a HSMC connector Figure 3 1 Figure 3 2 and Figure 3 3 show the pin outs of the HSMC connector on the Mass Storage and Video card 7 Terasic HSMC Communication Card User Manual www terasic com Www Ceragic COM 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 HSMC SCL 34 33 HSMC SDA 36 35 38 37 ENET CONN RX CLK 40 39 USB CONN CLK 161 162 164 Figure 3 1 Pin outs of Bank 1 on the HSMC connector 8 Terasic HSMC Communication Card User Manual www terasic com Www Ceragic COM USB STP 42 HSMC DI3I 44 46 ENET TXD 1 48 ENET RXDI3 50 52 ENET TXDI2 54 ENET RESETn 56 58 USB DIR 60 USB DATA 4 62 64 USB DATA 3 66 ENET TXDIO 68 70 USB DATA 2 72 ENET RXDI0 74 76 ENET RXD 1 78 ENET RX DV 80 82 DVI DATA 19 84 DVI DATA 18 86 88 DVI DATA 17 90 DVI DATA 16 92 94 SD CONN RCLK 96 HSMC CLKIN N 1 98 100 165 167 167 41 HSMC DIOJ 43 USB DAT
6. 6 RS232 Port 0 Interface Connector Pin out Pin DB9 Name NC RXD TXD NC GND NC NC NC NC O olal ND nM Bi LOTA Direction Output Input Power Description Not Connected Receive Data Line Transmit Data Line Not Connected Signal Ground Not Connected Not Connected Not Connected Not Connected RS 232 port 1 is routed to the 2x5 header as described in the table below pin out and signal description are relative to the connector Table 4 7 RS232 Port 1 Interface Connector Pin out Pin DB9 Name NC NC RXD NC TXD NC NC NC GND NC DC coolalA lu iB IN _ Direction Output Input 20 Description Not Connected Not Connected Receive Data Line Not Connected Transmit Data Line Not Connected Not Connected Not Connected Signal Ground Not Connected Tasic Terasic HSMC Communication Card User Manual www terasic com WWW bErasiC com A DTE RYAN 4 4 CAN Interface There are two CAN interfaces from the HSMC to two DB9 male connectors Figure 4 4 CAN Interface Block Diagram Both CAN circuits are connected the same Table 4 8 CAN DB9 Connector Pin out Pin DB9 Name Direction Description NC Not Connected 2 CANL 2 CAN bus line low I 3 GND Power Signal Ground 4 NC p Not Connected i 5 GND Power Signal Ground 6 GND Power Signal Ground 7 CANH 7 CAN bus line high 8 NC Not Connected 9 NC L Not Connected
7. SE WA LTC3025 i Enet PHY Max 500mA 200mA vDDO AVDD 3 3V 4 37W 3 3V x2 RS485 VCC 11090 1 324A gt 574mA x2 CAN GPIO SD SDIO MMC 12V 5 16W Switcher 5 ov s 16 PI LT3480 5 15v x2 RS485 VCC2ies 430mA Max 2 0A DVI Connector USB 5 0V USB PHY Analog USB VBUS Linear USB 3 3V LTC3025 USB PHY IO Max 500mA 200mA 24M OSC Figure 4 9 Power Tree 26 Terasic HSMC Communication Card User Manual www terasic com www Dres DOM ANU S A Chapter 5 Appendix 5 1 Revision History Change Log Initial Version Preliminary Modify Table 4 9 5 2 Copyright Statement Copyright O 2011 Terasic Technologies All rights reserved ZI Terasic HSMC Communication Card User Manual www terasic com www berasic DO
8. A 0 USB DATA I USB DATA USB DATA 3 USB DATA 4 USB DATA 5 USB DATA 6 USB DATA 7 USB DIR USB NXT Output Output Output Output Output Input Input Input Input Input Output Input Output Input Input Bi directional Output Bi directional Bi directional Bi directional Input Input Output Input Bi directional Output Bi directional Bi directional Bi directional Bi directional Output Output Bi directional Bi directional Bi directional Bi directional Bi directional Bi directional Bi directional Bi directional Output Output 12 RGMII Receive Data bit 0 RGMII Receive Data bit 1 RGMII Receive Data bit 2 RGMII Receive Data bit 3 RGMII Transmit Control RGMII Transmit Data bit 0 RGMII Transmit Data bit 1 RGMII Transmit Data bit 2 RGMII Transmit Data bit 3 RS 485 RS 232 Receive Data RS 485 RS 232 Transmit RS 485 RS 232 Receive RS 485 RS 232 Transmit EEPROM Serial Clock EEPROM Serial Address GPIO Input Data GPIO Bi directional Data GPIO Bi directional Data GPIO Bi directional Data RS 485 Request to Send RS 485 Request to Send SD Card Detection SD Card Reader Clock SD Card Reader Command SD Card Reader Readback from Level Translator SD Card Reader Data Bit SD Card Reader Data Bit SD Card Reader Data Bit SD Card Reader Data Bit SD Card Write Protect USB 60MHz Reference USB Data bit 0 USB Data bit 1 USB Data bit 2 USB Data bit 3 USB Data bit 4 USB Data bit 5 USB Data bit 6 USB Data bi
9. A O 45 47 ENET TXDJ3I 49 USB DATA 51 53 ENET RXDI2 55 PIO 0 OUTI O 57 59 ENET TX EN 61 PIO 0 OUT 2 63 65 USB DATA 5 u 67 DVI INTn OUT 69 a 71 PIO O OUT 1 13 USB DATA 6 75 77 USB DATA T7 19 81 83 DVI DATA 23 85 DVI DATA 22 87 89 DVI DATA 21 91 DVI DATA 20 93 95 SD CLK 97 CAN 1 TX 99 169 170 EN Em T Figure 3 2 Pin outs of Bank 2 on the HSMC connector Terasic HSMC Communication Card User Manual www teras cam www terasic com DVI DATA 9 102 DVI DATA 8 104 106 SD DATA 3 108 DVI DATA 7 110 112 HSMC 1 TXD 114 DVI DATAI6 116 118 SD DATA 2 120 DVI DATA 5 122 124 DVI DATA 4 126 DVI DATA 3 128 130 132 CAN 0 RX 134 136 DVI DATA 0 138 SD DATA 0 140 142 SD CMD 144 CAN 1 RX 146 148 101 DVI DATA 15 103 DVI DATA 14 105 107 DVI_DATA 13 109 USB NXT 111 113 DVI DATA 12 115 DVI DATA 11 117 119 DVI_DATA 10 121 RS485 1 RTS 123 125 SD DATA 127 RS485 0 RTS 129 131 HSMC 1 TXD 133 DVI DATA 135 137 DVI DATA 139 DVI DE 141 143 DVI HSYNC 145 HSMC 0 TXD 147 PIO O IN 150 149 CAN 0 TX HSMC 0 RXD 152 151 DVI VSYNC 154 153 SD WP 156 155 ENET GTX CLK 158 157 DVI CLK 159 SD CD AT H 090 ALTERA Figure 3 3 Pin outs of Bank 3 on the HSMC connector Table 3 1 shows the pin description of the HSMC connector 10 Terasic HSMC Communication Card User Manual www terasic com
10. default to RGMII to copper mode HWCFG MODE 3 0 1011 The table below summarizes the pins of the 10 100 1000 Ethernet interface Signal names and directions are relative to the host board Table 4 1 Ethernet PHY Interface I O ENET GTX CLK 125MHz GMII Transmit 2 5V CMOS output Clock ENET TX CLK 25MHz MI Transmit n a Clock ENET TX ER GMII Transmit Error n a tie to GND 14 Terasic HSMC Communication Card User Manual www terasic com M CEPA Dom ENET TX EN GMII Transmit Enable 2 5V CMOS output ENET TXD 4 GMII Transmit Data Bus ENET TXD 3 0 RGMII Transmit Data Bus 2 5V CMOS output ENET RX CLK GMII Receive Clock 2 5V CMOS input ENET CRS GMII Carrier Sense n a mercn far ue ENET MDC Management Bus Data 2 5V CMOS input Clock ENET ENET MDIO Management Bus Data 2 5V CMOS 25VCMOS input ENET INTn Management Bus Interrupt 2 5V CMOS input ENET MDI 3 0 p n Media Dependent Interface RJ 45 memos ENET S CLKp n SGMII 625MHz Clock ENET S INp n SGMII Receive Data ENET LED LINKI 100Mb Link LED n a driven to LED bemes mene mara ENET LED LINKI 1000Mb Link LED n a driven to LED PE MJ EX TIS E mede aa mo aa pi mem n 15 Terasic HSMC Communication Card User Manual www terasic com www Dra COM VDDO I O Power Pin 2 IV VDDH I O Power Pin 2 5V VDDX I O Power Pin 2 5V AVDD Analog Power Input ZV DVDD Digital Power Input 1 2V GND Ground Ethernet PHY The 88E1111 uses a multi level boot
11. e 4 2 USB 2 0 Block Diagram 4 3 RS 485 RS 232 Interface There are two multiplexer circuit allowing the ability to switch between an RS 232 or RS 485 interface This interface contains two independent RS 485 ports and two independent RS 232 ports Each RS 485 interface is routed to a 2x5 0 1 header and a DB 9 female connector One RS 232 interface 1s routed to a 2x5 0 1 header and the second RS 232 interface 1s routed to a DB 9 male connector A jumper is used on the board to select between RS 485 port 0 or RS 232 port 0 and RS 485 port 1 or RS 232 port 1 17 Terasic HSMC Communication Card User Manual www terasic com www teras Bam ATERA lt lt RS485 0 RTS RS485_0_RXD 4 RS489 0 IXD HSMC 0 RXD gt RS232A RXD 4 HSMC 0 TXD RS232A TXD RS485 1 RTS RS485 1 RXD RS485 1 TXD HSMC 1 RXD gt 4 HSMC 1 TXD RS232B RXD RS232B TXD Figure 4 3 RS 485 RS 232 Interface Block Diagram RS 485 port 0 is connected to the 2x5 header and DB 9 connector as described in the table below pin out and signal description are relative to the header Table 4 4 RS485 Port 0 Interface Connector Pin out PEE Noo E go sav Ti raa TT TT GT Nc TT Nb Connected TT a me orcometet 5 Bidirectional inverting driver output receiver input Bidirectional Non koki driver TE mtp ro 9 GND Power Signal Ground doo NC NetCemeete 18 Terasic HSMC Communicati
12. ents A photograph of the HSMC Communication card is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the location of the connectors and key components RS 232 Header RS 485 Ports CAN Ports RS 232 Port RS 485 Headers CAN Headers GPIO 2x3 Connector at lost a emm m pana ud ds lt ge Ethernet PHY USB 2 0 OTG PHY za DVI Connector SD SDIO MMC Reader zza 2222 ea j E ERE HE AUT JI TI HSMC Connector Figure 2 2 The HSMC Communication card back side 5 Terasic HSMC Communication Card User Manual www terasic com www teras cam 2 1 Block Diagram Figure 2 3 shows the block diagram of the HSMC Communication card ENET_RX_D 3 0 gt 4 ENET TX D 3 0 ET x2 ENET CTL x2 ENET CTL amp USB D 7 0 gt l x3 USB CTL USB STP gt Ethernet D RS485 0 RTS RS485 0 RXD RS485 0 TXD amp PIOO OUT 2 0 gt 4 PIOO IN Hsvc 0 RD RS232A_RXD F 4 HMC o DD RS232A TXD lt SD Data 3 0 gt YOn SD Controls gt EN M RS485 1 RTS RS485_1_RXD 1 RXD FSD Clock DVI 25485 TD 7 1 TXD Encoded zd HSMC 1 RD gt Data DVI DATA 230 gt DVI Clock gt DVI VSync DVI HSync DVI Controls gt RS2526 RAD Ji RXD S HSMC 1 TXD QRS232B DD TXD CAN 0 TX CAN 0 RX
13. ic COM Chapter 1 Introduction The HSMC Communication card adds key interfaces to support a wide range of industrial image processing scientific and measurement reguirements From 10 100 1000 Ethernet PHY to CAN RS232 RS485 the HSMC Communication card can guickly get you started with your designs Also included is a digital DVI transmitter port to display FPGA driven video content The card allows users to evaluate included interfaces with any HSMC interface host boards 1 1 Features Figure 1 1 shows the photo of the HSMC Communication card The important features are listed below RGMII Ethernet PHY RJ 45 connector e USB 2 0 OTG PHY with ULPI e RS 485 x2 with 2x5 0 1 header e CAN x2 with DB9 connector e GPIO with 2x3 0 1 connector e SD Card Socket e DVI Transmitter with DVI D Connector e HSMC identification is facilitated via the on board DC EEPROM 3 Terasic HSMC Communication Card User Manual www terasic com WWW TErasic DOM Figure 1 1 Picture of the HSMC Communication card 1 2 Getting Help Here are some places to get help if you encounter any problem e Email to support terasic com e Taiwan amp China 886 3 550 8800 e Korea 82 2 512 7661 e Japan 81 428 77 7000 4 Terasic HSMC Communication Card User Manual www terasic com www teras cam Chapter 2 Architecture This chapter describes the architecture of the HSMC Communication card including block diagram and compon
14. ogy Inc 24AA08 24LCO8B 24XX08 is an 8 Kbit Electrically Erasable PROM The device is organized as four blocks of 256 x 8 bit memory with a 2 wire serial interface Low voltage design permits operation down to 1 7V with standby and active currents of only 1 uA and 1 mA respectively The 24X X08 also has a page write capability for up to 16 bytes of data The 24XX08 is available in the standard 8 pin PDIP surface mount SOIC TSSOP 2x3 DEFN 2x3 TDFN and MSOP packages and is also available in the 5 lead SOT 23 package 4 9 Power There are two power rails that are supplied through HSMC connector 12V and 43 3 V All the required on board voltages are generated from these voltage rails However due to possible excessive power requirements to support two hard drives there 1s an option to supply the power from external power supply through power plug On board DC DC regulator will generate 12V and supply it to all the downstream power rails This option is selected by on board jumper 29 Terasic HSMC Communication Card User Manual www terasic com www terasir pom Linear 3 3V 825mW 1 0V 1 0V LTC3025 Enet PHY DVDD 250mA M Max 500mA 250mA J9 i Linear 3 3V 330mW 1 8V DVI AVDD LTC3025 DVI Analog VDD 3 3 330mW Linear 1 8V DVI DVDD OA 109025 100mA DVI Digital VDD Max 500mA 3 3V 330mW ions 18V DVI PVDD 100mA Max 500mA 100mA i DVI PLL VDD Linear 2 5V 3 3V 660m
15. on Card User Manual www terasic com www Dra DOM Pin DB9 Name Direction Description 1 GND Power Signal Ground 2 NC Not Connected 3 B Bidirectional inverting driver output receiver input 4 DE Input Driver Enable 9 GND Power signal Ground 6 5 0V Power 5V 7 NC Not Connected 8 A Bidirectional Non Inverting driver output receiver input 9 E E RS 485 port I is a profibus type connection It is connected to the 2x5 header and DB 9 connector as described in the table below pin out and signal description are relative to the header Table 4 5 RS485 profibus Port 1 Interface Connector Pin out Pin 2x5 Name Direction Description 1 NC Not Connected 2 5 0V Power 5V 3 NC Not Connected 4 NC Not Connected 5 A Bidirectional Non inverting driver output receiver input 6 B Bidirectional Inverting driver output receiver input 7 DE Input Driver Enable 8 NC Not Connected 9 GND Power Signal Ground 10 NC Not Connected Pin DB9 Name Direction Description 1 GND Power Signal Ground 2 NC Not Connected 3 A Bidirectional Non inverting driver output receiver input 4 DE Input Driver Enable 5 GND Power Signal Ground 6 5 0V Power 5V 7 NC Not Connected 8 B Bidirectional Inverting driver output receiver input 9 E 19 www terasic com ATERA RS 232 port 0 is routed to the DB 9 connector as described in Table 4 6 below pin out and signal description are relative to the connector Table 4
16. r Data Bit 1 DVI Transmitter Data Bit 10 DVI Transmitter Data Bit 11 DVI Transmitter Data Bit 12 DVI Transmitter Data Bit 13 DVI Transmitter Data Bit 14 DVI Transmitter Data Bit 15 DVI Transmitter Data Bit 16 DVI Transmitter Data Bit 17 DVI Transmitter Data Bit 18 DVI Transmitter Data Bit 19 DVI Transmitter Data Bit 2 DVI Transmitter Data Bit 20 DVI Transmitter Data Bit 21 DVI Transmitter Data Bit 22 DVI Transmitter Data Bit 23 DVI Transmitter Data Bit 3 DVI Transmitter Data Bit 4 DVI Transmitter Data Bit 5 DVI Transmitter Data Bit 6 DVI Transmitter Data Bit 7 DVI Transmitter Data Bit 8 DVI Transmitter Data Bit 9 DVI Transmitter Data Valid DVI Transmitter HSYNC DVI Transmitter VSYNC RGMII Receive Clock RGMII Transmit Clock Management Interrupt Management Data Clock Management Data Ethernet Hardware Reset RGMII Receive Control www terasic com 152 145 114 131 34 33 150 55 71 61 127 121 158 95 144 96 140 125 120 108 156 39 43 49 72 66 62 65 73 7 60 109 Terasic HSMC Communication Card User Manual www Denai COM ENET RX DV ENET RXD O ENET RXD 1 ENET RXD 2 ENET RXD 3 ENET TX EN ENET TXD 0 ENET TXD I ENET TXD 2 ENET TXD 3 HSMC 0 RXD HSMC 0 TXD HSMC 1 RXD HSMC 1 TXD HSMC SCL HSMC SDA PIO 0 IN PIO 0 OUT 0 PIO 0 OUT 1 PIO 0 OUT 2 RS485 0 RTS RS485 1 RTS SD CD SD CLK SD CMD SD CONN RCLK SD DATA 0 SD DATA I SD DATA 2 SD DATA 3 SD WP USB CONN CLK USB DAT
17. required line and field synchronization signals Transmitter has I2C port that 1s used for configuration and diagnostic tasks and it can be shared with other on board I2C enabled devices In addition this interface 1s used to communicate with DDC enabled monitors Here is the pin description of DVI connector Table 4 10 DVI Connector Pin out Pin Name Direction Description 1 TMDS Data2 Out Digital red 2 TMDS Data2 Out Digital red 3 TMDS Data2 4 Shield shield 4 TMDS Data4 Out Not in use 5 TMDS Data4 Out Not in use 6 SCL Out DDC channel clock 7 SDA Bidir DDC channel data 8 Analog vertical sync Out Not in use 9 TMDS Data l Out Digital green 10 TMDS Datal Out Digital green 11 TMDS Datal 3 Shield shield 12 TMDS Data3 Out Not in use 13 TMDS Data3 Out Not in use 14 5V Power Power for monitor during stand by 15 Ground Power Return for 5V pin 14 16 Hot plug detect In Hot plug detect 17 TMDS Data0 Out Digital blue 18 TMDS Data0 Out Digital blue 19 TMDS Data0 5 Shield shield 20 TMDS Data5 Out Not in use 21 TMDS Data5 Out Not in use 22 TMDS Clock Shield shield 23 TMDS Clock Out Digital clock 24 TMDS Clock Out Digital clock C1 Analog red Out Not in use C2 Analog green Out Not in use C3 Analog blue Out Not in use C4 Analog horizontal sync Out Not in use C5 Analog ground Not in use The signal direction is referred to HSMC card 23 Terasic HSMC Communication Card User Manual
18. strap encoding scheme to allow a small set of pins 7 to set up a very large number of default settings within the device The level encoding scheme is shown in the table below from the Marvel datasheet The CONFIG 6 0 signals should be tied directly to VDDO GND or the defined Ethernet pin as described below Table 4 2 Ethernet PHY Bootstrap Encoding Pin Bit 2 0 VDDO 111 LED LINK10 110 LED LINK100 101 LED LINK1000 100 LED DUPLEX 011 LED RX 010 LED TX 001 VSS 000 Table 4 3 Ethernet PHY Bootstrap Settings Pin Pin Connection Setting Definition CONFIGO GND 000 MDIO PHY Address bit 2 0 000 CONFIGI GND 000 Enable Pause 0 PHY Address bits 4 3 00 CONFIG2 VDDO 2 5V 111 Auto negotiate advertise all capabilities prefer CONFIG3 GND 000 Disable crossover disable CLK 125 CONFIG4 LED DUPLEX 011 Hardware Config Mode Reg 2 0 011 CONFIGS LED LINK100 101 Disable fiber copper autosel enable sleep mode CONFIG6 LED RX 010 enable energy detect Hardware Config Mode 4 2 USB 2 0 OTG PHY The USB 2 0 PHY interface supports the On The Go OTG protocol and is pinned out with UTMI Low Pin Interface ULPI The USB transceiver will be routed to a mini AB type connector 16 Terasic HSMC Communication Card User Manual www terasic com www Denai COM 4 DATA 7 0 gt lt CLK lt DIR 4 NXT STP 4 lt VBUS gt te D gt Mini AB M 4 po Figur
19. t 7 USB Data Direction USB NXT www terasic com ANU S RA 42 USB STP Input USB STP 132 79 i Table 3 2 below outlines HSMC power levels that host boards guarantee from on board power supplies minimum according to the HSMC specification Theses power rails will be delivered via designated pins on the HSMC connector Table 3 2 HSMC Power Levels i WAX Voltage Current Rating Wattage 12V 1 0A 12 0W 3 3V HSMC 2 0A 6 6W Total 18 6W 13 www Eerasic COM Tasic Terasic HSMC Communication Card User Manual www terasic com NO S RYAN Chapter 4 Components This chapter gives a simple description of the on board components such as operational mode signaling standard For more detailed information you could refer to its datasheet which 1s available on manufacturer s website or from our provided system CD 4 1 RGMII Ethernet PHY This card supports copper RJ 45 10 100 1000 base T Ethernet using an external Marvell 88E1111 The PHY to MAC interface employs an RGMII interface A block diagram is shown in Figure 4 1 where the MAC is found in the FPGA 10 100 1000 Mbps Transformer Ethernet MAC vise RGMII Interface Figure 4 1 Marvell RGMII Diagram This device uses 2 5V and 1 1V power rails and requires a 25MHz reference clock 50ppm tolerance to be driven from a dedicated oscillator It interfaces to a HALO HFJ11 1G02E model RJ 45 with internal magnetics The bootstrapping pins are wired to
Download Pdf Manuals
Related Search