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P89LPC9331/9341/9351/9361 8-bit microcontroller with

1. 2 7 5 0 002aae36 18 MHz Ipp mA 4 0 12 MHz 3 0 8 MHz 2 0 6 MHz 4 MHz 1 0 2MHz 1 MHz 32 kHz 0 0 2 4 2 8 3 2 3 6 Vpp V Test conditions idle mode entered executing code from on chip flash using an external clock with no active peripherals with the following functions disabled real time clock and watchdog timer Fig 30 Ipp gie VS frequency at 40 C 2 5 0 002aae368 18 MHz Ipp mA 4 0 12 MHz 3 0 8 MHz 2 0 6 MHz a MINER c 4 MHz 1 0 pu em ue e 2 MHz 1 MHz 32 kHz 0 0 24 2 8 3 2 3 6 Vpp V Test conditions idle mode entered executing code from on chip flash using an external clock with no active peripherals with the following functions disabled real time clock and watchdog timer Fig 31 lpp igie VS frequency at 85 C All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 70 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 20 0 002aae369 Ipp uA e 18 0 Et 16 0 2 14 0 NEM omi NN 34 12 0 oe 10 0 24 2 8 3 2 3 6 Vpp V Test conditions p
2. Fig9 Asymmetrical PWM down counting All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 42 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core TOR2 compare value timer value 0 non inverted inverted 002aaa894 Fig 10 Symmetrical PWM 7 22 7 Alternating output mode In asymmetrical mode the user can set up PWM channels A B and C D as alternating pairs for bridge drive control In this mode the output of these PWM channels are alternately gated on every counter cycle TOR2 COMPARE VALUE A or C COMPARE VALUE B or D 4 TIMER VALUE 0 7171 7r 1 l l l l PWM OUTPUT OCA or OCC I I PWM OUTPUT OCB or OCD 002aaa895 Fig 11 Alternate output mode 7 22 8 PLL operation P89LPC9331_9341_9351_9361 The PWM module features a Phase Locked Loop that can be used to generate a CCUCLK frequency between 16 MHz and 32 MHZ At this frequency the PWM module provides ultrasonic PWM frequency with 10 bit resolution provided that the crystal frequency is 1 MHz or higher The PLL is fed an input signal from 0 5 MHz to 1 MHz and generates an output signal of 32 times the input frequency This signal is used to clo
3. start trigger adc clk 1 2 3 4 5 6 7 8 9 10 11 12 13 clk serial_data_out o Y Y vs Y vs Y os X vo Y vt X Do ADCDATA REG ADCDATA 002aae371 Fig 48 ADC conversion timing P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 85 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 1 2 Fig 49 ADC characteristics The ideal transfer curve Example of an actual transfer curve offset gain error error Eo EG 4 p 4 255 254 253 252 L uL X E code out 6 e 5L 4L 3 L aL 1 1LSB ideal 0 e LZ l l E 3 s 5 7 253 254 255 256 offset error Via LSBigea gt E V V 1LSB PPA SSA 256 002aae372 P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 86 of 94 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core NXP Semiconductors 13 Package outline PLCC28 plastic leaded chip carrier 28 leads SOT261 2 En detail
4. DIVIDER BY 4 16 64 128 A SPI clock master SS CLOCK LOGIC P2 4 A A SPI CONTROL REGISTER SPI internal interrupt y data request bus 002aaa900 Fig 16 SPI block diagram The SPI interface has four pins SPICLK MOSI MISO and SS SPICLK MOSI and MISO are typically tied together between two or more SPI devices Data flows from master to slave on MOSI Master Out Slave In pin and flows from slave to master on MISO Master In Slave Out pin The SPICLK signal is output in the Master mode and is input in the Slave mode If the SPI system is disabled i e SPEN SPCTL 6 0 reset value these pins are configured for port functions SSis the optional slave select pin In a typical configuration an SPI master asserts one of its port pins to select one SPI device as the current slave An SPI slave device uses its SS pin to determine whether it is selected Typical connections are shown in Figure 17 through Figure 19 P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 49 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 7 25 1 Typical SPI configurations P89LPC9331_9341_9351_9361 MISO MOSI SPICLK
5. SDA PORT 1 AL DAC1 4 AD13 gt KBld gt CINIA gt eo INTI KBI5 CMPREF RST KBl6 gt CMP1 lt gt ADOO od ae P89LPC9331 CLKOUT lt XTAL2 lt P89LPC9341 4 ADO3 DACO lt gt AD02 XTAL1 gt lt gt gt MOSI 4 l port 2 47 MISO lt gt SS lt gt lt gt SPICLK 4 A 002aae461 Fig 2 Functional diagram P89LPC9331 9341 Voo Vss AD01 gt KBI0 gt CMP2 lt bd lt gt TXD AD10 KBI1 CIN2B bd lt gt RXD AD11 KBI2 CIN2A gt lt gt TO gt on AD12 gt KBI3 gt CIN1B gt INTO SDA DAC1 AD13 gt KBI4 gt CINIA PORTO gt RORTY INTI KBI5 gt CMPREF lt gt I RST KBl6 CMP1 lt gt lt gt gt OCB Kel poer PsoLPC9351 E DU ARON CLKOUT 4 XTAL2 lt P89LPC9361 ICB ADO3 DACO PORT 4 lt gt OCD AD02 XTAL1 a gt lt gt gt MOSI 4 l porr 2 MISO lt gt SS lt gt lt gt SPICLK lt gt OCA 4 ICA 002aad556 Fig 3 Functional diagram P89LPC9351 9361 P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 5 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8
6. ESPI EC EKBI EI2C ool 00x0 0000 BF BE BD BC BB BA B9 B8 PWDRT PBO PS PSR PT1 PX1 PTO PXO ool x000 0000 PWDRTH PBOH PSH PT1H PX1H PTOH PXOH ool x000 0000 PSRH FF FE FD FC FB FA F9 F8 PAD PST PSPI PC PKBI PI2C ool 00x0 0000 PADH PSTH PSPIH PCH PKBIH PI2CH ool 00x0 0000 E E PATN KBIF ooi XxXxX xx0O _SEL 00 0000 0000 FF 11111111 87 86 85 84 83 82 81 80 T1 KB7 CMP1 CMPREF CIN1A CIN1B CIN2A CIN2B CMP2 H KB6 KB5 KB4 KB3 KB2 KB1 KBO 97 96 95 94 93 92 91 90 RST INT1 INTO SDA TO SCL RXD TXD iui AT A6 A5 A4 A3 A2 A1 AO SPICLK SS MISO MOSI 2 Hu B7 B6 B5 B4 B3 B2 B1 BO z XTAL1 XTAL2 H POM1 7 POM1 6 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FFU 11111111 POM2 7 POM2 6 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 00 0000 0000 9102 16209 X20 9 OM pa es9j9998 YIM 19 043u0204J91UI 1q 8 L9 6 LSE6 LVE6 LEEGOd 168d SJOJONPUODIWIIS dXN yoays Lp jonpoJd eL0z 1SnDny oz L S ed sieuirejosip Jeba 0 1oefqns si jueuunoop siu ui pepi oid uoneuuojul y v6 0 ZL 1966 1SE6 LEG LEECOd 168d paniasad suu Iv ZLOZ A 8 dXN GO Table 4 indicates SFRs that are bit addressable Special function registers P89LPC9331 9341 continued Name P1M1 P1M2 P2M1 P2M2 P3M1 P3M2 PCON PCONA PSW PTOAD RSTSRC RTCCON RTCH RTCL SADDR SADEN Description SFR addr Port 1 output 91H mode 1 Por
7. Note Central frequency of internal RC oscillator 7 3728 MHz Fig 35 Average internal RC oscillator frequency vs Vpp at 40 C All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 72 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 P89LPC9331_9341_9351_9361 8 bit microcontroller with accelerated two clock 80C51 core 002aae347 0 2 frequency deviation 0 Voo V Central frequency of internal RC oscillator 7 3728 MHz Fig 36 Average internal RC oscillator frequency vs Vpp at 85 C 002aae348 2 5 frequency deviation 1 5 0 5 1 5 2 4 2 8 3 2 3 6 Vpp V Central frequency of watchdog oscillator 400 KHz Fig 37 Average watchdog oscillator frequency vs Vpp at 25 C All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 73 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 P89LPC9331_9341_9351_9361 8 bit microcontroller with accelerated two clock 80C51 core 002aae349 0 5 frequency deviation 0 5 1 5 24 2 8 3 2 3 6 Vpp V Central frequency of watchdog os
8. internal bus 256 BYTE SCL SPICLK 512 BYTE MOSI AUXILIARY RAM 1 gt SPI MISO SS REAL TIME CLOCK DATA EEPROM 1 C 3 TIMER 0 TO i CONFIGURABLE l Os gt Ens CIN2B Pemra couriGURABLE os o e CONFIGURABLE l Os COMPARATORS CMP1 CIN1A PORT 1 GINTB Piro E CONFIGURABLE l Os OCA eran CCU CAPTURE Gee 1 Po 7 0 CONFIGURABLE C COMPARE UNIT 1 ae ICB INTERRUPT AD11 C ADCI DACI AD12 AD13 WATCHDOG TIMER C9 DAC1 AND OSCILLATOR ADOO ADCO TEMP DOS SER SENSOR DACO ADOS uds WV DACO CRYSTAL X7AE ON CHIP RC POWER MONITOR OR jn CONFIGURABLE OSCILLATOR POWER ON RESET RESONATOR XTAL2 OSCILLATOR WITH CLOCK BROWNOUT RESET DOUBLER 002aad555 P89LPC9351 9361 PGA1 on P89LPC9351 9361 PGAO on P89LPC9351 9361 Fig 1 Block diagram ananasa Q N P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 4 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 5 Functional diagram 8 bit microcontroller with accelerated two clock 80C51 core Vss VDD AD01 KBI0 gt CMP2 lt lt gt TXD AD10 gt KBI1 CIN2B gt lt _ RXD AD11 KBI2 CIN2A lt gt gt TO gt SCL AD12 KBI3 CINiB gt INTO
9. 8 bit microcontroller with accelerated two clock 80C51 core Memory organization The various P89LPC9331 9341 9351 9361 memory spaces are as follows DATA 128 bytes of internal data memory space 00H 7FH accessed via direct or indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area IDATA Indirect Data 256 bytes of internal data memory space 00H FFH accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it e SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing XDATA P89LPC9351 9361 External Data or Auxiliary RAM Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR RO or R1 All or part of this space could be implemented on chip The P89LPC9351 9361 has 512 bytes of on chip XDATA memory plus extended SFRs located in XDATA CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC9331 9341 9351 9361 has 4 kB 8 kB 16 kB of on chip Code memory The P89LPC9351 9361 also has 512 bytes of on chip data EEPROM that is accessed via SFRs see Section 7 14 Data RAM arrangement The 768 bytes of on chip RAM are organized as shown in Table
10. Data pointer 2 bytes Data pointer 83H high Bit functions and addresses Reset value MSB LSB Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 CLKLP EBRR ENT1 ENTO SRST 0 DPS 00 0000 00x0 F7 F6 F5 F4 F3 F2 F1 FO 00 0000 0000 00 0000 0000 00 0000 0000 SBRGS BRGEN _ 00 2 XXXX xx0O CE1 CP1 CN1 OE1 CO1 CMF1 oot xx00 0000 CE2 CP2 CN2 OE2 CO2 CMF2 ool xx00 0000 00 0000 0000 00 0000 0000 8109 16209 X20 9 OM pa1eJ9J929e YIM 19 043u0204J91UI 1q 8 L9 6 LSE6 LVE6 LEEGOd 168d SJOJONPUODIWIIS dXN yooys Lep jonpoJd 1966 1SE6 LEG LE 60d 168d eL0z snbny oz L S ed sieuirejosip Jeba 0 1oefqns si jueuunoop SIY ui pepi oid uoneuuojul y peajiesei suu Ily ZLOZ 8 dXN GO v6 0 SL Table 4 Special function registers P89LPC9331 9341 continued indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses addr MSB DPL Data pointer 82H low FMADRH Program flash E7H address high FMADRL Program flash E6H address low FMCON Program flash E4H BUSY control Read Program flash E4H FMCMD 7 FMCMD 6 control Write FMDATA Program flash EBH data I2ADR l C bus slave DBH I2ADR 6 I2ADR 5 address register Bit address DF DE I2CON I2C bus control D8H I2EN register I2DAT I C bus data DAH register l2SCLH Serial clock DDH generator SCL duty cycle register high I2SCLL Serial clock DCH gen
11. ce P89LPC9331 9341 9351 9361 BUS 8 bit microcontroller with accelerated two clock 80C51 core 4 kB 8 kB 16 kB 3 V byte erasable flash with 8 bit ADCs Rev 5 1 20 August 2012 Product data sheet 1 General description The P89LPC9331 9341 9351 9361 is a single chip microcontroller available in low cost packages based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC9331 9341 9351 9361 in order to reduce component count board space and system cost 2 Features and benefits 2 1 Principal features E 4kB 8 kB 16 kB byte erasable flash code memory organized into 1 kB sectors and 64 byte pages Single byte erasing allows any byte s to be used as non volatile data storage E 256 byte RAM data memory P89LPC9351 and P89LPC9361 also include a 512 byte auxiliary on chip RAM W 512 byte customer data EEPROM on chip allows serialization of devices storage of setup parameters etc P89LPC9351 9361 W Dual 4 input multiplexed 8 bit ADC DAC outputs Two analog comparators with selectable inputs and reference source E Dual Programmable Gain Amplifiers PGA with selectable gains of 2x 4x 8x or 16x can be applied to ADCs and analog comparator inputs P89LPC935 1 9361 B On chip temperature sensor integrated with ADC module B Two 16 bit counter
12. 0 2Vpp V VoL LOW level output voltage lo 20 mA Vpp 2 4 V to e 0 6 1 0 V 3 6 V all ports all modes except high Z lo 3 2 mA Vpp 2 4 V to 6l 0 2 0 3 V 3 6 V all ports all modes except high Z Vou HIGH level output voltage lon 20 pA Vpp 0 3 Vpp 0 2 V Vpp 2 4 V to 3 6 V all ports quasi bidirectional mode lou 3 2 mA Vpp 0 7 Vpp 0 4 V Vpp 2 4 V to 3 6 V all ports push pull mode lou 10 mA 3 2 V Vpp 2 4 V to 3 6 V all ports push pull mode Vstal crystal voltage on XTAL1 XTAL2 pins with 0 5 4 0 V respect to Vss Vn voltage on any other pin except XTAL1 XTAL2 Vpp Z 0 5 5 5 V with respect to Vss Ciss input capacitance 8 15 pF P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 66 of 94 NX P Semiconductors P89LPC9331 9341 9351 9361 Tabl 8 bit microcontroller with accelerated two clock 80C51 core e12 Static characteristics continued Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications 40 C to 125 C extended unless otherwise specified Symbol Parameter Conditions Min Typi Max Unit lu LOW level input current Vi204V 9 80 uA lo input leakage current Vi Vit Vin or Vin HL 10 1 uA lu HIGH LOW transition all ports V 1 5 V a
13. 20 August 2012 47 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 8 NO ADDRESS REGISTER I2ADR P1 3 COMPARATOR INPUT FILTER i P1 3 SDA OUTPUT STAGE gt BIT COUNTER ARBITRATION CCLK 9 INPUT AND SYNC LOGIC TIMING m FILTER AND CONTROL Z P1 2 SCL LOGIC i SERIAL CLOCK E OUTPUT interrupt z STAGE GENERATOR timer 1 1 overflow P12 I2CON CONTROL REGISTERS AND I2SCLH SCL DUTY CYCLE REGISTERS I2SCLL eb STATUS Status OUS DECODER I2STAT STATUS REGISTER CZ 002aaa899 Fig 15 I C bus serial interface block diagram P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 48 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 7 25 SPI The P89LPC9331 9341 9351 9361 provides another high speed serial communication interface the SPI interface SPI is a full duplex high speed synchronous communication bus with two operation modes Master mode and Slave mode Up to 3 Mbit s can be supported in either Master mode or Slave mode It has a Transfer Completion Flag and Write Collision Flag Protection MISO P2 3 CPU clock 8 BIT SHIFT REGISTER MOSI READ DATA BUFFER pae SPICLK P2 5
14. 8 11 10 10 1 10 2 10 3 11 11 1 11 2 12 12 1 12 2 13 14 8 bit microcontroller with accelerated two clock 80C51 core General description iussus 55 Feat res sulelsilimec9 kl 9er ka 55 Flash organization 4 56 Using flash as data storage 56 Flash programming and erasing 56 e dr 56 AP P PMID 56 ISPs cost Cubes iet aoc ieee 57 Power on reset code execution 57 Hardware activation of the bootloader 58 User configuration bytes 58 User sector security bytes 58 p por opp 58 General description 05 58 Features and benefits 58 Block diagram 0 eee eee eee 60 PGA P89LPC9351 9361 61 Temperature sensor 05 61 ADC operating modes 62 Fixed channel single conversion mode 62 Fixed channel continuous conversion mode 62 Auto scan single conversion mode 62 Auto scan continuous conversion mode 62 Dual channel continuous conversion mode 62 Single step mode 20055 63 Conversion start modes 63 Timer triggered start 0 63 Start immediately 2 000 5 63 Edge triggered 220005 63 Dual start immediately 63 Boundary limits interrupt 63 DAC output to a port pin with high
15. Document identifier PS9LPC9331 9341 9351 9361
16. L S ed sieuirejosip Jeba 0 joefqns si jueuunoop SIY ui pepi oid uoneuuojul y v610 8L 1966 LSE6 Lv 6 LEE6Od 168d peajiesei suu Iv ZLOZ A 8 dXN GO Table 4 Special function registers P89LPC9331 9341 continued indicates SFRs that are bit addressable Name SBUF SCON SSTAT SP SPCTL SPSTAT SPDAT TAMOD TCON THO TH1 TLO TL1 TMOD TRIM WDCON Description SFR addr Serial Portdata 99H buffer register Bit address Serial port 98H control Serial port BAH extended status register Stack pointer 81H SPI control E2H register SPI status E1H register SPI data E3H register Timer 0 and 1 8FH auxiliary mode Bit address Timer 0 and 1 88H control Timer 0 high 8CH Timer 1 high 8DH Timer 0 low 8AH Timer 1 low 8BH Timer 0 and 1 89H mode Internal 96H oscillator trim register Watchdog A7H control register Bit functions and addresses Reset value MSB LSB Hex Binary Xx XXXX XXXX 9F 9E 9D 9C 9B 9A 99 98 SMO FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 DBMOD INTLO CIDIS DBISEL FE BR OE STINT 100 0000 0000 07 0000 0111 SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPRO 04 0000 0100 SPIF WCOL 00 OOxx Xxxx 00 0000 0000 T1M2 TOM2 00 Xxx0 xxx0 8F 8E 8D 8C 8B 8A 89 88 TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 TIGATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 0000 0000 RCCLK ENCLK TRIM 5 TRIM 4
17. P2M2 7 P2M2 6 P2M2 5 P2M2 4 P2M2 3 P2M2 2 P2M2 1 P2M2 0 OO 0000 0000 9102 16209 490 9 Om p91eJ9J929 YIM 19 043u0204J91UI 1Iq 8 L9 6 L6 6 Lv 6 L6 60d 168d SJOJONPUODIWIIS dXN yooys Lep jonpoJd eL0z snbny oz L S ed sieuirejosip Jeba 0 joefqns si jueuunoop SIY ui pepi oid uoneuuojul y V6 J0 9c 1966 LSE6 Lv 6 LEE6Od 168d paniasad suu Iv ZLOZ A 8 dXN GO Table 6 Special function registers P89LPC9351 9361 indicates SFRs that are bit addressable Name P3M1 P3M2 PCON PCONA PSW PTOAD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF SCON SSTAT SP SPCTL Description SFR addr Port 3 output B1H mode 1 Port 3 output B2H mode 2 Power control 87H register Power control B5H register A Bit address Program status DOH word Port Odigital input F6H disable Reset source DFH register RTC control D1H RTC register high D2H RTC register low D3H Serial port A9H address register Serial port B9H address enable Serial Port data 99H buffer register Bit address Serial port control 98H Serial port BAH extended status register Stack pointer 81H SPI control E2H register Bit functions and addresses Reset value MSB LSB Hex Binary s P3M1 1 P3M1 0 03U ooxx xx11 P3M2 1 P3M2 0 00l xxxx xx00 SMOD1 SMODO BOI GF1 GFO PMOD1 PMODO 00 0000 0000 RTCPD DEEPD VCPD ADPD I2PD SPPD SPD CCUPD l
18. P89LPC9351FDH P89LPC9361FDH Package Name Description Version TSSOP28 plastic thin shrink small outline package 28 SOT361 1 leads body width 4 4 mm TSSOP28 plastic thin shrink small outline package 28 SOT361 1 leads body width 4 4 mm TSSOP28 plastic thin shrink small outline package 28 SOT361 1 leads body width 4 4 mm PLCC28 plastic leaded chip carrier 28 leads SOT261 2 TSSOP28 plastic thin shrink small outline package 28 SOT361 1 leads body width 4 4 mm TSSOP28 plastic thin shrink small outline package 28 SOT361 1 leads body width 4 4 mm Ordering options Table 2 Ordering options Type number Flash memory Temperature range Frequency P89LPC9331FDH 4kB 40 C to 85 C 0 MHz to 18 MHz P89LPC9331HDH 4 kB 40 C to 125 C 0 MHz to 18 MHz P89LPC9341FDH 8 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC9351FA 8 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC9351FDH 8 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC9361FDH 16 kB 40 C to 85 C 0 MHz to 18 MHz All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 3 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 4 Block diagram P89LPC9331 9341 9351 9361 ACCELERATED 2 CLOCK 80C51 CPU A TXD 4 kB 8 kB 16 kB CODE FLASH C G amp T DART RXD
19. commercial EPROM programmers Flash security bits prevent reading of sensitive application programs Serial flash In System Programming ISP allows coding while the device is mounted in the end application In Application Programming IAP of the flash code memory This allows changing the code in a running application Watchdog timer with separate on chip oscillator nominal 400 kHz calibrated to 5 96 requiring no external components The watchdog prescaler is selectable from eight values High accuracy internal RC oscillator option with clock doubler option allows operation without external oscillator components The RC oscillator option is selectable and fine tunable Clock switching on the fly among internal RC oscillator watchdog oscillator external clock source provides optimal support of minimal power active mode with fast switching to maximum performance Idle and two different power down reduced power modes Improved wake up from Power down mode a LOW interrupt input starts execution Typical power down current is 1 uA total power down with voltage comparators disabled Active LOW reset On chip power on reset allows operation without external reset components A software reset function is also available Configurable on chip oscillator with frequency range options selected by user programmed flash configuration bits Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz Oscill
20. 0000 0000 CLKLP EBRR ENT1 ENTO SRST 0 DPS 00 0000 00x0 F7 F6 F5 F4 F3 F2 F1 FO 00 0000 0000 00 0000 0000 00 0000 0000 SBRGS BRGEN 002 xxxxx00 ICECA2 ICECA1 ICECAO ICESA ICNFA FCOA OCMA1 OCMAO 00 0000 0000 ICECB2 ICECB1 ICECBO ICESB ICNFB FCOB OCMB1 OCMBO 00 0000 0000 E FCOC OCMC1 OCMCO 00 Xxxx x000 FCOD OCMD1 OCMDO 00 XXxx x000 z CE1 CP1 CN1 OE1 CO1 CMF1 ool xx00 0000 z CE2 CP2 CN2 OE2 CO2 CMF2 ool xx00 0000 EEIF HVERR ECTL1 ECTLO EWERR1 EWERRO EADR8 80 1000 0000 00 0000 0000 00 0000 0000 3109 16209 20J 2 0M1 pa es9j9998 YUM 19 043u0204J91UI 1q 8 L9 6 LSE6 LVE6 LEEGOd 168d SJOJONPUODIWIIS dXN Jays Lep 19npoJd zLoz isnbny oz L S ed sieuirejosip Jeba 0 joefqns si jueuunoop SIY ui pepi oid uoneuuojul y V6 J0 C 196 LGE6 Lv 6 LEE6Od 168d penjiesei sIYBu Iv ZLOZ A 8 dXN GO Table 6 indicates SFRs that are bit addressable Special function registers P89LPC9351 9361 Name DIVM DPTR DPH DPL FMADRH FMADRL FMCON FMDATA I2ADR I2CON I2DAT I2SCLH I2SCLL I2STAT Description SFR addr CPU clock 95H divide by M control Data pointer 2 bytes Data pointer high 83H Data pointer low 82H Program flash E7H address high Program flash E6H address low Program flash E4H control Read Program flash E4H control Write Program flash E5H data I2C bus slave DBH address register Bit address l C bus c
21. 5 may be configured by software Pin P1 5 is input only Pins P1 2 and P1 3 are configurable for either input only or open drain Every output on the P89LPC9331 9341 9351 9361 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to Table 12 Static characteristics for detailed specifications All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times Power monitoring functions The P89LPC9331 9341 9351 9361 incorporates power monitoring functions designed to prevent incorrect operation during initial power up and power loss or reduction during operation This is accomplished with two hardware functions Power on detect and brownout detect All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 37 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 17 1 7 17 2 7 18 7 18 1 7 18 2 P89LPC9331_9341_9351_9361 8 bit microcontroller with accelerated two clock 80C51 core Brownout detection The brownout detect function determines if the power supply voltage drops below a certain level Enhanced brownout detection has 3 independent functions BOD
22. 8 Table8 On chip data memory usages Type Data RAM Size bytes DATA Memory that can be addressed directly and indirectly 128 IDATA Memory that can be addressed indirectly 256 XDATA Auxiliary External Data on chip memory that is accessed 512 using the MOVX instructions P89LPC9351 9361 Interrupts The P89LPC9331 9341 9351 9361 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the many interrupt sources The P89LPC9331 9341 9351 9361 supports 15 interrupt sources external interrupts 0 and 1 timers 0 and 1 serial port TX serial port RX combined serial port RX TX brownout detect watchdog RTC I2C bus keyboard comparators 1 and 2 SPI CCU data EEPROM write ADC completion All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 33 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 15 1 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IENO or IEN1 The IENO register also contains a global disable bit EA which disables all interrupts Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registe
23. A D converters must select an identical number of channels Any trigger of either A D will start a simultaneous conversion of both A Ds Boundary limits interrupt Each of the A D converters has both a high and low boundary limit register The user may select whether an interrupt is generated when the conversion result is within or equal to the high and low boundary limits or when the conversion result is outside the boundary limits An interrupt will be generated if enabled if the result meets the selected interrupt criteria The boundary limit may be disabled by clearing the boundary limit interrupt enable All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 63 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 9 8 10 8 11 P89LPC9331_9341_9351_9361 8 bit microcontroller with accelerated two clock 80C51 core An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits In this case after the four MSBs have been converted these four bits are compared with the four MSBs of the boundary high and low registers If the four MSBs of the conversion meet the interrupt criteria i e outside the boundary limits an interrupt will be generated if enabled If the four MSBs do not meet the interrupt criteria the boundary limits will again be compared after a
24. Pin Type Description PLCC28 TSSOP28 P0 6 CMP1 KBI6 20 l O P0 6 Port 0 bit 6 High current source O CMP1 Comparator 1 output KBI6 Keyboard input 6 PO 7 T1 KBI7 19 lO P0 7 Port 0 bit 7 High current source lO T1 Timer counter 1 external count input or overflow output l KBI7 Keyboard input 7 P1 0 to P1 7 l O 1 Port 1 Port 1 is an 8 bit I O port with a user configurable output type except for three pins as noted below During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to Section 7 16 1 Port configurations and Table 12 Static characteristics for details P1 2 to P1 3 are open drain when used as outputs P1 5 is input only All pins have Schmitt trigger inputs Port 1 also provides various special functions as described below P1 0 TXD 18 l O P1 0 Port 1 bit 0 O TXD Transmitter output for serial port P1 1 RXD 17 VO P1 1 Port 1 bit 1 RXD Receiver input for serial port P1 2 TO SCL 12 lO P1 2 Port 1 bit 2 open drain when used as output lO TO Timer counter 0 external count input or overflow output open drain when used as output lO SCL I C bus serial clock input output P1 3 INTO SDA 11 lO P1 3 Port 1 bit 3 open drain when used as outpu
25. Power reduction modes for details All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 34 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core IEO EX0 IE1 EX1 BOIF EBO RTCF o KBIF ERTC EKBI 12 J RTCCON 1 np WDOVE EWDRT CMF2 CMF1 EC EA IEO 7 TFO ETO TF1 ET1 TI amp RI RI ES ESR TI EST SI El2C SPIF ESPI any CCU interrupt ECCU iil j 12 zn _ EEIF 2 oe 9 ADCIO ENADCI1 ADCH EADEE 2 EAD 3 dm D BNDIO BNDI1 1 See Section 7 22 CCU P89LPC9351 9361 2 P89LPC9351 9361 3 P89LPC9331 9341 002aad560 Fig8 Interrupt sources interrupt enables and power down wake up sources wake up if in power down interrupt to CPU P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 35 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 16 7 16 1 7 16 1 1 7 16 1 2 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core l O ports The P89LPC9331 9341 9351 936
26. X 5 scale DIMENSIONS mm dimensions are derived from the original inch dimensions A4 b max P by DM E e ep eg Hp unit A _ Ag 11 58 11 58 3 05 11 43 11 43 1 27 0 456 0 456 inches i i 0 12 0 450 0 450 Note 1 Plastic or metal protrusions of 0 25 mm 0 01 inch maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT261 2 112E08 MS 018 EDR 7319 Ee 99 42 27 01 11 15 Fig 50 PLCC28 package outline SOT261 2 P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 87 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core TSSOP28 plastic thin shrink small outline package 28 leads body width 4 4 mm SOT361 1 pin 1 index 7 lt detail X DIMENSIONS m
27. as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 16 1 Port configurations and Table 12 Static characteristics for details All pins have Schmitt trigger inputs Port 2 also provides various special functions as described below P2 0 ICB DACO 1 VO P2 0 Port 2 bit 0 ADO3 l ICB Input Capture B PB9LPC9351 9361 O DACO Digital to analog converter output l AD03 ADCO channel 3 analog input P2 1 0CD AD02 2 O P2 1 Port 2 bit 1 O OCD Output Compare D P89LPC9351 9361 l AD02 ADCO channel 2 analog input P2 2 MOSI 13 lO P2 2 Port 2 bit 2 l O MOSI SPI master out slave in When configured as master this pin is output when configured as slave this pin is input P2 3 MISO 14 lO P2 3 Port 2 bit 3 l O MISO When configured as master this pin is input when configured as slave this pin is output P2 4 SS 15 VO P2 4 Port 2 bit 4 SS SPI Slave select P2 5 SPICLK 16 lO P2 5 Port 2 bit 5 l O SPICLK SPI clock When configured as master this pin is output when configured as slave this pin is input P2 6 0CA 27 lO P2 6 Port 2 bit 6 O OCA Output Compare A P89LPC9351 9361 P2 7 ICA 28 lO P2 7 Port 2 bit 7 l ICA Input Capture A P89LPC9351 9361 P3 0 to P3 1 lO Port 3 Port 3 is a 2 bit I O port with a user configurable output type During reset Port 3 la
28. bit microcontroller with accelerated two clock 80C51 core 6 Pinning information 6 1 Pinning 002aae462 P2 0 AD03 DACO P2 7 P2 1 AD02 C P2 6 P0 0 CMP2 KBIO ADO1 P0 1 CIN2B KBH AD10 P1 7 ADO0 P0 2 CIN2A KBI2 AD1 1 P1 6 P0 3 CIN1B KBI3 AD12 P1 5 RST PO 4 CIN1A KBI4 DAC1 AD13 s o P oLPCOXTEDHI eee P89LPC9341FDH DD P3 0 XTAL2 CLKOUT P0 6 CMP1 KBI6 P1 4 INT1 P0 7 T1 KBI7 P1 3 INTO SDA P1 0 TXD P1 2 TO SCL P1 1 RXD P2 2 MOSI P2 5 SPICLK P2 3 MISO P2 4 SS Fig 4 P89LPC9331 9341 TSSOP28 pin configuration P2 0 ICB DACO ADOS P2 7 ICA P2 1 OCD AD02 C P2 6 0CA P0 0 CMP2 KBIO ADO1 P0 1 CIN2B KBI1 AD10 P1 7 OCC ADO00 P0 2 CIN2A KBI2 AD11 P1 6 OCB P0 3 CIN1B KBI3 AD12 P1 5 RST PO 4 CIN1A KBI4 DAC1 AD13 V P0 5 CMPREF KBI5 P89LPC9351FDH PSCABSLAET P89LPC9361FDH VoD P3 0 XTAL2 CLKOUT P0 6 CMP1 KBI6 P1 4 INT1 P0 7 T1 KBI7 P1 3 INTO SDA P1 0 TXD P1 2 TO SCL P1 1 RXD P2 2 MOSI P2 5 SPICLK P2 3 MISO P2 4 SS 002aad557 Fig 5 P89LPC9351 9361 TSSOP28 pin configuration P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers Rev 5 1 20 August 2012 NXP B V 2012 All rights reserved 6 of 94 Product data sheet NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core ict o o eo a o a lt a lt oS a omo go a xaa x INLA a Ono lt y o2o0B8nsSsoz oo
29. circuit Input only configuration The input only port configuration has no output drivers It is a Schmitt trigger input that also has a glitch suppression circuit Push pull output configuration The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit The P89LPC9331 9341 9351 9361 device has high current source on eight pins in push pull mode See Table 11 Limiting values Port 0 analog functions The P89LPC9331 9341 9351 9361 incorporates two Analog Comparators In order to give the best analog function performance and to minimize power consumption pins that are being used for analog functions must have the digital outputs and digital inputs disabled Digital outputs are disabled by putting the port output into the Input Only high impedance mode Digital inputs on Port 0 may be disabled through the use of the PTOAD register bits 1 5 On any reset PTOAD 1 5 defaults to logic Os to enable digital functions Additional port features After power up all pins are in Input Only mode Please note that this is different from the LPC76x series of devices e After power up all I O pins except P1
30. cycles plus 60 us to 100 us If the clock source is the internal RC oscillator the delay is 200 us to 300 us If the clock source is watchdog oscillator or external clock the delay is 32 OSCCLK cycles CCLK modification DIVM register The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register DIVM to generate CCLK This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate This can also allow bypassing the oscillator start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution Low power select The P89LPC9331 9341 9351 9361 is designed to run at 18 MHz CCLK maximum However if CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to logic 1 to lower the power consumption further On any reset CLKLP is logic 0 allowing highest performance access This bit can then be set in software if CCLK is running at 8 MHz or slower All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 32 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 13 7 14 7 15 P89LPC9331 9341 9351 9361
31. during power down These include Brownout detect watchdog timer comparators note that comparators can be powered down separately and RTC system timer The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled Total Power down mode This is the same as Power down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled If the internal RC oscillator is used to clock the RTC during power down there will be high power consumption Please use an external low frequency clock to achieve low power with the RTC running during power down Reset The P1 5 RST pin can function as either a LOW active reset input or as a digital input P1 5 The Reset Pin Enable RPE bit in UCFG1 when set to logic 1 enables the external reset input function on P1 5 When cleared P1 5 may be used as an input pin Remark During a power up sequence the RPE selection is overridden and this pin always functions as a reset input An external circuit connected to this pin should not hold this pin LOW during a power on sequence as this will keep the device in reset After power up this pin will function as defined by the RPE bit Only a power up reset will temporarily override the selection defined by RPE
32. output impedance seseseees reels 64 Clock divider 0 0 0 00 00 cece ee eae 64 Power down and Idle mode 64 Limiting values eese 65 Static characteristics 66 Current characteristics 68 Internal RC watchdog oscillator characteristics 72 BOD characteristics 75 Dynamic characteristics 76 Waveforms 0 000 eee ee eee 80 ISP entry mode nananana nananana 82 Other characteristics 83 Comparator electrical characteristics 83 ADC PGA temperature sensor electrical characteristicS 200 00000 84 Package outline 87 Abbreviations 22 5 21 m Re 89 15 Revision history lesse 90 16 Legal information seee 91 16 1 Data sheet status 00 91 16 2 Definitions llle 91 16 3 Disclaimers sssr ae ee cele edo wae 2ee ease 91 16 4 Trademarks 0 00 cece eee 92 17 Contact information 92 18 Content 20ici cece elk ix Ru wx 93 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2012 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 20 August 2012
33. oz L S ed sieuirejosip Jeba 0 joefqns si jueuinoop SIY ui pepi oid uoneuuojul y V6 40 6c 1966 LSE6 Lv 6 LEE6Od 168d pamasa siuBu Ily ZLOZ A d dXN Table 7 Extended special function registers PS9LPC9351 9361 1 Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary BODCFG BOD FFC8H BOICFG1 BOICFGO 2 configuration register CLKCON CLOCK FFDEH CLKOK XTALWD CLKDBL FOSC2 FOSC1 FOSCO 8 1000 xxxx Control register PGACON1 PGA1 control FFE1H ENPGA1 PGASEL1 PGASEL1 PGATRIM PGAG11 PGAG10 00 00000000 register 1 0 1 PGACON1B PGA1 control FFE4H PGAENO 00 0000 0000 register B FF1 PGA1TRIM8X16X PGA trim FFE3H 16XTRIM3 16XTRIM2 16XTRIM1 16XTRIMO 8XTRIM3 8XTRIM2 8XTRIM1 8XTRIMO register PGA1TRIM2X4X PGA1 trim FFE2H 4XTRIM3 4XTRIM2 4XTRIM1 4XTRIMO 2XTRIM3 2XTRIM2 2XTRIM1 2XTRIMO 4 register PGACONO PGAO control FFCAH ENPGAO PGASELO PGASELO PGATRIM J TSEL1 TSELO PGAGO1 PGAGOO 00 0000 0000 register 1 0 0 PGACONOB PGAO control FFCEH PGAENO 00 0000 0000 register B FFO PGAOTRIM8X16X PGAO trim FFCDH 16XTRIM3 16XTRIM2 16XTRIM1 16XTRIMO 8XTRIM3 8XTRIM2 8XTRIM1 8XTRIMO 4 register PGAOTRIM2X4X PGAO trim FFCCH 4XTRIM3 4XTRIM2 4XTRIM1 4XTRIMO 2XTRIM3 2XTRIM2 2XTRIM1 2XTRIMO l register RTCDATH Real time FFBFH 00 0000 0000 clock data register high RTCDATL Real time FFBEH 00 0000 0000 clock data register lo
34. s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing
35. the flash configuration It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source and if XTAL1 XTAL2 are not used to generate the clock for the RTC system timer Ground 0 V reference Power supply This is the power supply voltage for normal operation as well as Idle and Power down modes 1 Input output for P1 0 to P1 4 P1 6 P1 7 Input for P1 5 P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 11 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 7 Functional description Remark Please refer to the P89LPC9331 9341 9351 9361 User manual for a more detailed functional description 7 1 Special function registers Remark SFR accesses are restricted in the following ways User must not attempt to access any SFR locations not defined Accesses to any defined SFR locations must be strictly for the functions for the SFRs e SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 must be written with 0 and will return a 0 when
36. to 0 Hz P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers Rev 5 1 20 August 2012 NXP B V 2012 All rights reserved 79 of 94 Product data sheet NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 11 1 Waveforms tcHcx tCLCH tCHCL tcLex Toy clk 002aaa907 Fig 41 External clock timing with an amplitude of at least Viigus 200 mV e TXLXL clock output data write to SBUF ss tXHDX tXxHDV set TI gn QUK KX eX Kx Ke Ke Kee Ke clear RI I set RI 002aaa906 Fig 42 Shift register mode timing SS JA I TsPIcYC gt tSPIF e tSPICLKH tSPICLKL SPICLK CPOL 0 output tsPIF I tsPIR dM tSPICLKL tsPICLKH SPICLK CPOL 1 output tsPIDsU SPIDH MSB LSB in gt tsPIDV MISO input tsPIOH tsPIDV MOSI tsPIF output 7 VA master MSB LSB out master LSB MSB out IN Fa LN 002aaa908 Fig 43 SPI master timing CPHA 0 P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 80 of 94 NXP Semiconductors P89LPC9331 9341 9351 936
37. trip voltage falling stage 2 25 2 60 V rising stage 2 35 2 65 V 1 Typical ratings are not guaranteed The values listed are at room temperature 3 V VDD Vtrip BOF BOIF can be cleared in software BOF BOIF i set by hardware i i BOF BOIF l a 002aae352 Fig 40 BOD interrupt reset characteristics P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 75 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 11 Dynamic characteristics Table 14 Dynamic characteristics 12 MHz Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications 40 C to 125 C extended unless otherwise specified 12 Symbol Parameter Conditions Variable clock fosc 12 MHz Unit Min Max Min Max fosc RC internal RC oscillator nominal f 2 7 3728 MHz 7 189 7 557 7 189 7 557 MHz frequency trimmed to 1 at Tamb 25 C clock doubler option OFF default nominal f 14 7456 MHz 14 378 15 114 14 378 15 114 MHz clock doubler option ON Vpp 2 7 V to 3 6 V fosc WD internal watchdog Tamb 25 C 380 420 380 420 kHz oscillator frequency fose oscillator frequency 0 12 MHz Toy clk clock cycle time see Figure 41 83 ns CLKLP
38. 0o0c t OO Ms Oe O TS Oe rOoONAAN OS aodq aoaeaad o ou amp RII amp P1 6 0CB P1 5 RST Vss P0 2 CIN2A KBI2 AD1 1 P0 3 CIN1B KBI3 AD12 PO 4 CIN1A KBI4 DAC1 AD13 P3 1 XTAL1 P89LPC9351FA P0 5 CMPREF KBI5 P3 0 XTAL2 CLKOUT VDD P1 4 INT1 P0 6 CMP1 KBI6 P1 3 INTO SDA P0 7 T1 KBI7 e OO sr to cCo B CO T viru 002aad558 d o0 Qoxcnunon 289232 0zz 29 FEaagare Daan ee a Fig 6 P89LPC9351 PLCC28 pin configuration P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 7 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 6 2 Pin description Table 3 Pin description Symbol Pin Type Description PLCC28 TSSOP28 P0 0 to P0 7 l O Port 0 Port 0 is an 8 bit I O port with a user configurable output type During reset Port 0 latches are configured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 16 1 Port configurations and Table 12 Static characteristics for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt trigger inputs Port 0 also provides various s
39. 1 8 bit microcontroller with accelerated two clock 80C51 core TsPIcvc tsPiF gt tsPIR tSPICLKL tSPICLKH SPICLK CPOL 0 jf CHE em output tsPIF gt tsPIR tSPICLKL _i SPICLK tsPICLKH 7 CPOL 1 7 output UN yN tsPIDsU tsPIDH hie 7 input MSB LSBin P i LSB MSB in tsPIDV tsPIOH tsPIDV tsPIR MOSI 7 7 output X master LSB MSB out lh 002aaa909 Fig 44 SPI master timing CPHA 1 SS lt tSPIF tsPIR I Tspicyc tsPILEAD tSPIF cS tsPIR tsPILAG I tsPICLKL tsPICLKH SPICLK A N N N CPOL 0 input tsPIF tsPIR tSPICLKL 24 SPICLK tSPICLKH CPOL 1 input N N V tsPIA J tsPIOH tsPioH gt lt tsPIOH lt gt tsPIDIS tsPIDV gt tsPIDv 7 y 7 MISO slave MSB LSB out X Y slave LSB MSB out Hot defined output LN LN ZN 4 ra tspipsu tsPIDH tsPIDSU tsPIDSU tsPIDH O I XX XX canem X input A MSBLSBin X X A A LSBMSBin X 002aaa910 Fig 45 SPI slave timing CPHA 0 P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 81 o
40. 1 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC9331 9341 9351 9361 does include an independent baud rate generator The baud rate can be selected from the oscillator divided by a constant Timer 1 overflow or the independent baud rate generator In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection automatic address recognition selectable double buffering and several interrupt options The UART can be operated in four modes shift register 8 bit UART 9 bit UART and CPU clock 32 or CPU clock 16 Mode 0 Serial data enters and exits through RXD TXD outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is fixed at 4G of the CPU clock frequency All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 44 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 23 2 7 23 3 7 23 4 7 23 5 7 23 6 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Mode 1 10 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first and a stop bit logic 1 When data is received the stop bit is stored in RB8 in special function register SCON The ba
41. 1 has four I O ports Port 0 Port 1 Port 2 and Port 3 Ports 0 1 and 2 are 8 bit ports and Port 3 is a 2 bit port The exact number of I O pins available depends upon the clock and reset options chosen as shown in Table 9 Table 9 Number of I O pins available Clock source Reset option Number of I O pins 28 pin package On chip oscillator or watchdog No external reset except during 26 oscillator power up External RST pin supported 25 External clock input No external reset except during 25 power up External RST pin supported 24 Low medium high speed No external reset except during 24 oscillator external crystal or power up resonator External RST pin supported 23 Port configurations All but three I O port pins on the P89LPC9331 9341 9351 9361 may be configured by software to one of four types on a bit by bit basis These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each port pin 1 P1 5 RST can only be an input and cannot be configured 2 P1 2 SCL TO and P1 3 SDA INTO may only be configured to be either input only or open drain Quasi bidirectional output configuration Quasi bidirectional output type can be used as both an input and output without the need to reconfigure the port This is possible because when the port outputs a logic HIGH it is weakly driven allowing an external
42. 15 ns tsa signal acceptance time P1 5 RST pin 125 125 ns any pin except P1 5 RST 50 50 ns External clock tcHcx clock HIGH time see Figure 41 22 Tey clk tcLex 22 ns tcLox clock LOW time see Figure 41 22 Tey clk tcHcx 22 ns tcicH clock rise time see Figure 41 5 5 ns tcHcL clock fall time see Figure 41 5 5 ns Shift register UART mode 0 TXEXL serial port clock cycle see Figure 42 16T cy clk 888 ns time tavxH output data set up to see Figure 42 13T cy clk 722 ns clock rising edge time txHax output data hold after see Figure 42 Tey clk 20 75 ns clock rising edge time txupx input data hold after see Figure 42 0 0 ns clock rising edge time txupv input data valid to clock see Figure 42 150 150 ns rising edge time SPI interface spi SPI operating frequency slave 0 CCLKy 0 3 0 MHz master CCLKy 4 5 MHz Tspicvc SPI cycle time see Figure 43 44 45 46 slave Sook 333 ns master A CCLK 222 ns P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers Rev 5 1 20 August 2012 NXP B V 2012 All rights reserved 78 of 94 Product data sheet NXP Semiconductors P89LPC9331 9341 9351 9361 Table 15 8 bit microcontroller with accelerated two clock 80C51 core Dynamic characteristics 18 MHz continued Vpp 3 0 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications 40 C t
43. 351 9361 8 bit microcontroller with accelerated two clock 80C51 core Reset vector Following reset the P89LPC9331 9341 9351 9361 will fetch instructions from either address 0000H or the Boot address The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address OOH The boot address will be used if a UART break reset occurs or the non volatile boot status bit BOOTSTAT 0 1 or the device is forced into ISP mode during power on see P89LPC9331 9341 9351 9361 User manual Otherwise instructions will be fetched from address 0000H Timers counters 0 and 1 The P89LPC9331 9341 9351 9361 has two general purpose counter timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1 Both can be configured to operate either as timers or event counters An option to automatically toggle the TO and or T1 pins upon timer overflow has been added In the Timer function the register is incremented every machine cycle In the Counter function the register is incremented in response to a 1 to 0 transition at its corresponding external input pin TO or T1 In this function the external input is sampled once during every machine cycle Timer 0 and Timer 1 have five operating modes Modes 0 1 2 3 and 6 Modes 0 1 2 and 6 are the same for both Timers Counters Mode 3 is different Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer whic
44. 351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 90 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 16 Legal information 16 1 Data sheet status Document status J 2 Product status Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 16 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of informa
45. 61 flash memory provides in circuit electrical erasure and programming The flash can be erased read and written as bytes The Sector and Page Erase functions can erase any flash sector 1 kB or page 64 bytes The Chip Erase operation will erase the entire program memory ICP using standard commercial programmers is available In addition IAP and byte erase allows code memory to be used for non volatile data storage On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC9331 9341 9351 9361 flash reliably stores memory contents even after 100 000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms The P89LPC9331 9341 9351 9361 uses Vpp as the supply voltage to perform the Program Erase algorithms When voltage supply is lower than 2 4 V the BOD FLASH is tripped and flash erase program is blocked Features Programming and erase over the full operating voltage range Byte erase allows code memory to be used for data storage Read Programming Erase using ISP IAP ICP Internal fixed boot ROM containing low level IAP routines available to user code Default loader providing ISP via the serial port located in upper end of user program memory Boot vector allows user provided flash loader code to reside anywhere in the flash memory space providing flexibility to the user e Any flash program erase operation in 2 ms Programming w
46. 67 167 ns 0 0 ns 100 100 ns 2000 2000 ns 100 100 ns 2000 2000 ns 1 Parameters are valid over operating temperature range unless otherwise specified 2 Parts are tested to 2 MHz but are guaranteed to operate down to 0 Hz P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 77 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 Table 15 8 bit microcontroller with accelerated two clock 80C51 core Dynamic characteristics 18 MHz Vpp 3 0 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications 40 C to 125 C extended unless otherwise specified l Symbol Parameter Conditions Variable clock fosc 18 MHz Unit Min Max Min Max fosc Rc internal RC oscillator nominal f 7 3728 MHz 7 189 7 557 7 189 7 557 MHz frequency trimmed to 1 at Tamb 25 C clock doubler option OFF default nominal f 14 7456 MHz 14 378 15 114 14 378 15 114 MHz clock doubler option ON fosewp internal watchdog Tamb 25 C 380 420 380 420 kHz oscillator frequency fosc oscillator frequency 0 18 MHz Tcy ck Clock cycle time see Figure 41 55 ns foLKLP low power select clock 0 8 MHz frequency Glitch filter tgr glitch rejection time P1 5 RST pin 50 50 ns any pin except P1 5 RST 15
47. 85 C for industrial applications 40 C to 125 C extended unless otherwise specified 1 Symbol Tspicyc tsPILEAD tsPILAG tsPICLKH tsPICLKL tspipsu tsPIDH tspia tspipis tspipv tsPIOH tsPIR tspir Parameter SPI cycle time slave master SPI enable lead time slave SPI enable lag time slave SPICLK HIGH time master slave SPICLK LOW time master slave SPI data set up time master or slave SPI data hold time master or slave SPI access time slave SPI disable time slave SPI enable to output data valid time slave master SPI output data hold time SPI rise time SPI outputs SPICLK MOSI MISO SPI inputs SPICLK MOSI MISO SS SPI fall time SPI outputs SPICLK MOSI MISO SPI inputs SPICLK MOSI MISO SS Conditions see Figure 43 44 45 46 see Figure 45 46 see Figure 45 46 see Figure 43 44 45 46 see Figure 43 44 45 46 see Figure 43 44 45 46 see Figure 43 44 45 46 see Figure 45 46 see Figure 45 46 see Figure 43 44 45 46 see Figure 43 44 45 46 see Figure 43 44 45 46 see Figure 43 44 45 46 Variable clock fosc 12 MHz Unit Min Max Min Max ScLk 500 ns Y oCLK 333 ns 250 250 ns 250 250 ns cock 165 ns Yocik 250 ns P CCLK 165 ns Yocik 250 ns 100 100 ns 100 100 ns 0 120 0 120 ns 0 240 240 ns z 240 240 ns 1
48. All rights reserved Product data sheet Rev 5 1 20 August 2012 82 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 12 Other characteristics 12 1 Comparator electrical characteristics Table 17 Comparator electrical characteristics Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications 40 C to 125 C extended unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vio input offset voltage 10 mV Vic common mode input voltage 0 Vpp O03 V CMRR common mode rejection ratio 0 50 dB tres tot total response time 250 500 ns t cE ov chip enable to output valid time 10 us lu input leakage current OV lt Vi lt Vpp t1 uA 1 This parameter is characterized but not tested in production P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 83 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 12 2 ADC PGA temperature sensor electrical characteristics Table 18 ADC PGA temperature sensor electrical characteristics Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications 40 C to 125 C extended unle
49. CFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 9102 16209 490 9 Om pa1eJ9 929e YIM 19 043u0204J91UI 1Iq 8 L9 6 L6 6 Lv 6 L6 60d 168d SJOJONPUODIWIIS dXN Jays Lep 19npoJd eL0z snbny oz L S nay sieuirejosip Jeba 0 joefqns si jueuunoop siut ui PEPIAOI uoneuuojul y V6 10 Ic L9 6 LSE6 Lv 6 LEE6Od 168d penjiesei suu Iv ZLOZ A a dXN GO Table 6 Special function registers P89LPC9351 9361 indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 EO ACC Accumulator EOH 00 0000 0000 ADCONO A D control 8EH ENBIO ENADCIO TMMO EDGEO ADCIO ENADCO ADCSO01 ADCSOO 00 0000 0000 register 0 ADCON1 A D control 97H ENBI1 ENADCI1 TMM1 EDGE1 ADCH ENADC1 ADCS11 ADCS10 00 0000 0000 register 1 ADINS A D input select A3H ADI13 ADI12 ADI11 ADI10 ADI03 ADIO2 ADIO1 ADIOO 00 0000 0000 ADMODA A D mode COH BNDI1 BURST1 SCC1 SCAN1 BNDIO BURSTO SCCO SCANO 00 0000 0000 register A ADMODB A D mode A1H CLK2 CLK1 CLKO INBNDO ENDAC1 ENDACO BSA1 BSAO 00 000x 0000 register B ADOBH A D 0 boundary BBH FF 1111 1111 high register ADOBL A D 0 boundary A6H 00 0000 0000 low register ADODATO A D O0 data C5H 00 0000 0000 register 0 ADODAT1 A D O data C6H 00 0000 0000 register 1 ADODAT2 A D O0 data C7H 00 0000 0000 register 2 ADODAT3 A D 0 data F4H 00 0000 0000 register 3 AD1BH A D_1
50. FH 7 30 10 Hardware activation of the bootloader The bootloader can also be executed by forcing the device into ISP mode during a power on sequence see the P89LPC9331 9341 9351 9361 User manual for specific information This has the same effect as having a non zero status byte This allows an application to be built that will normally execute user code but can be manually forced into ISP operation If the factory default setting for the boot is changed it will no longer point to the factory pre programmed ISP bootloader code After programming the flash the status byte should be programmed to zero in order to allow execution of the user s application code beginning at address 0000H 7 31 User configuration bytes Some user configurable features of the P89LPC9331 9341 9351 9361 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured through the use of the flash byte UCFG1 and UCFG2 Please see the P89LPC9331 9341 9351 9361 User manual for additional details 7 32 User sector security bytes There are 4 8 6 User Sector Security Bytes on the P89LPC9331 9341 9351 9361 Each byte corresponds to one sector Please see the P89LPC9331 9341 9351 9361 User manual for additional details 8 ADC 8 1 General description The P89LPC9331 9341 9351 9361 has two 8 bit 4 channel multiplexed successive approximation analog to digital converter modules An on chip temperature sensor is integrated with
51. GAO M Vref bg Anin03 I Vsen 8 a DACO MAN EAEE EEREN E AEEA BEATAE MENTIS a ew Oe ue EAR CONTROL diit OEA LOGIC l com AD10 p ADI2 a i SAR AD13 Anini3 T MEM ae DAC1 eruere eee EE CCLK gt 4 I 10 comparators 002aad576 Fig 24 P89LPC9351 9361 ADC block diagram 8 4 PGA P89LPC9351 9361 Additional PGA module is integrated in each ADC module to improve the effective resolution of the ADC A single channel can be selected for amplification The gain of PGA can be programmable to 2 4 8 and 16 Please refer to Table 12 Static characteristics for detailed specifications Register PGACONx and PGACONXxB are used to for PGA configuration Register PGAxTRIM2X4X and PGAxTRIM8X1 6X provide trim value of PGA gain level As power on default trim value for each gain setting is loaded into the PGA trim registers For accurate measurements offset calibration is required Please see the P89LPC9331 9341 9351 9361 User manual for detail configuration calibration and usage information 8 5 Temperature sensor An on chip wide temperature range temperature sensor is integrated with ADCO module It provides temperature sensing capability of 40 C 85 C It is necessary to measure the 1 2 V reference voltage via the ADC before measuring temperature In P89LPC9351 9361 the reference voltage temperature sensor and ADO3 input pin multiplex one input to PGAO Pleas
52. O E3 ADCIO ADCI1 ADIOS BNDIO ENDAC1 E2 ENADCO ENADC1 ADIO2 BURSTO ENDACO E1 ADCS01 ADCS11 ADIO1 SCCO BSA1 LSB EO ADCSO00 ADCS10 ADIOO SCANO BSAO Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 000x 0000 FF 1111 1111 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 FF 1111 1111 00 0000 0000 9102 16209 490 9 Om p91eJ9J929e YUM 19 043u020J91UI 1Iq 8 L9 6 LG 6 Lv 6 L6 60d 168d SJOJONPUODIWIIS dXN Jays Lep 19npoJd eL0z snbny oz L S ed sieuirejosip Jeba 0 joefqns si jueuunoop SIY ui pepi oid uoneuuojul y v6 9 HL 1966 LSE6 Lv 6 LEE6Od 168d peaiesei suu Iv ZLOZ A a dXN GO Table 4 indicates SFRs that are bit addressable Special function registers P89LPC9331 9341 continued Name AD1DATO AD1DAT1 AD1DAT2 AD1DATS AUXR1 B BRGROE BRGR1EI BRGCON CMP1 CMP2 DIVM DPTR DPH SFR addr Description A D_1 data D5H register 0 A D_1 data D6H register 1 A D_1 data D7H register 2 A D_1 data F5H register 3 Auxiliary A2H function register Bit address B register FOH Baud rate BEH generator 0 rate low Baud rate BFH generator 0 rate high Baud rate BDH generator 0 control Comparator1 ACH control register Comparator 2 ADH control register CPU clock 95H divide by M control
53. TRIM 3 TRIM 2 TRIM 1 TRIM O S516 PRE2 PRE1 PREO WDRUN WDTOF WDCLK Mis 8109 16209 20J 9 0M p91eJ9 929 YIM 19 043u0204J91UI 1Iq 8 L9 6 L6 6 Lv 6 L6 60d 168d SJOJONPUODIWIIS dXN J9yS Lep 19npoJd eL0z snbny oz L S ed sieuirejosip Jeba o1 1oefqns si jueuunoop SIY ui pepi oid uoneuuojul Iv v6 10 6L 1966 LSE6 Lv 6 LEE6Od 168d paniasad suu Iv ZLOZ A 8 dXN GO Table 4 Special function registers P89LPC9331 9341 continued indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary WDL Watchdog load C1H FF 1111 1111 WFEED1 Watchdog C2H feed 1 WFEED2 Watchdog C3H feed 2 1 2 3 4 5 6 All ports are in input only high impedance state after power up BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable The RSTSRC register reflects the cause of the P89LPC9331 9341 reset except BOIF bit Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is x011 0000 After reset the value is 1110 01x1 i e PRE2 to PREO are all logic 1 WDRUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF On power on reset and watchdog reset the TRIM SFR is initialized with a factory pr
54. a few seconds Please refer to the P89LPC9331 9341 9351 9361 User manual for more details MOV WFEED 1 0A5H MOV WFEED2 05AH if Y PCLK watchdog PRESCALER Lo 8 BIT DOWN reset 1 oscillator crystal PRESCALER Z COUNTER oscillator A A n MR XTALWD i D I D D D D D SHADOW REGISTER Peale 2s v WDCON A7H PRE2 PRE1 PReo WDRUN woTOF WOCLK sequence 1 Watchdog reset can also be caused by an invalid feed sequence or by writing to WDCON not immediately followed by a feed Fig 22 Watchdog timer in Watchdog mode WDTE 1 002aae015 7 29 7 29 1 7 29 2 P89LPC9331 9341 9351 9361 Additional features Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or watchdog reset had occurred Care should be taken when writing to AUXH1 to avoid accidental software resets Dual data pointers The dual Data Pointers DPTR provides two different Data Pointers to specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register All information provided in this document is subject to le
55. ailable to interface your application to a commercial programmer in order to use this feature Additional details may be found in the P89LPC9331 9341 9351 9361 User manual IAP IAP is performed in the application under the control of the microcontroller s firmware The IAP facility consists of internal hardware resources to facilitate programming and erasing The NXP IAP has made in application programming in an embedded application possible All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 56 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 30 8 7 30 9 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core without additional components Two methods are available to accomplish IAP A set of predefined IAP functions are provided in a Boot ROM and can be called through a common interface PGM MTP Several IAP calls are available for use by an application program to permit selective erasing and programming of flash sectors pages security bits configuration bytes and device ID These functions are selected by setting up the microcontroller s registers before making a call to PGM MTP at FFO3H The Boot ROM occupies the program memory space at the top of the address space from FFOOH to FEFFH thereby not conflicting with the user program memory space In addition IAP operatio
56. ator fail detect The watchdog timer has a separate fully on chip oscillator allowing it to perform an oscillator fail detect function Programmable port output configuration options quasi bidirectional open drain push pull input only High current sourcing sinking 20 mA on eight I O pins P0 3 to P0 7 P1 4 P1 6 P1 7 All other port pins have high sinking capability 20 mA A maximum limit is specified for the entire chip Port input pattern match detect Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern Controlled slew rate port outputs to reduce EMI Outputs have approximately 10 ns minimum ramp times Only power and ground connections are required to operate the P89LPC9331 9341 9351 9361 when internal reset option is selected Four interrupt priority levels Eight keypad interrupt inputs plus two additional external interrupt inputs Schmitt trigger port inputs Second data pointer Emulation support All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 2 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 3 Ordering information 8 bit microcontroller with accelerated two clock 80C51 core P89LPC9331_9341_9351_9361 3 1 Table 1 Ordering information Type number P89LPC9331FDH P89LPC9331HDH P89LPC9341FDH P89LPC9351FA
57. bit Other sources of reset will not override the RPE bit When this pin functions as a reset input an internal pull up resistance is connected see Table 12 Static characteristics Note During a power cycle Vpp must fall below Vpog before power is reapplied in order to ensure a power on reset see Table 12 Static characteristics Reset can be triggered from the following sources External reset pin during power up or if user configured via UCFG1 Power on detect Brownout detect Watchdog timer e Software reset UART break character detect reset For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a logic 0 to the corresponding bit More than one flag bit may be set During a power on reset both POF and BOF are set but the other flag bits are cleared A Watchdog reset is similar to a power on reset both POF and BOF are set but the other flag bits are cleared e For any other reset previously set flag bits that have not been cleared will remain set All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 39 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 19 1 7 20 7 20 1 7 20 2 7 20 3 7 20 4 7 20 5 P89LPC9331 9341 9
58. boundary C4H FF 1111 1111 high register AD1BL A D_1 boundary BCH 00 0000 0000 low register AD1DATO A D_1 data D5H 00 0000 0000 register 0 AD1DAT1 A D 1 data D6H 00 0000 0000 register 1 AD1DAT2 A D 1 data D7H 00 0000 0000 register 2 9102 16209 490 9 Om p91eJ9 9929 YIM 19 043u0204J91UI 1Iq 8 L9 6 LG 6 Lv 6 L6 60d 168d SJOJONPUODIWIIS dXN yooys Lep jonpoJd eL0z isnbny oz L S ed sieuirejosip Jeba 0 joefqns si jueuunoop SIY ui pepi oid uoneuuojul y V6 JO ZZ 196 LSE6 Lv 6 LEEGOdT68d penjiesei suu Ily ZLOZ A a dXN GO Table 6 Special function registers P89LPC9351 9361 indicates SFRs that are bit addressable Name AD1DATS AUXR1 B BRGROE BRGR1EI BRGCON CCCRA CCCRB CCCRC CCCRD CMP1 CMP2 DEECON DEEDAT DEEADR Description SFR addr A D_1 data F5H register 3 Auxiliary function A2H register Bit address B register FOH Baud rate BEH generator 0 rate low Baud rate BFH generator 0 rate high Baud rate BDH generator 0 control Capture compare EAH A control register Capture compare EBH B control register Capture compare ECH C control register Capture compare EDH D control register Comparator 1 ACH control register Comparator 2 ADH control register Data EEPROM F1H control register Data EEPROM F2H data register Data EEPROM F3H address register Bit functions and addresses Reset value MSB LSB Hex Binary 00
59. can also be optionally divided to a slower frequency see Section 7 11 CCLK modification DIVM register Remark fosc is defined as the OSCCLK frequency CCLK CPU clock output of the clock divider There are two CCLK cycles per machine cycle and most instructions are executed in one to two machine cycles two or four CCLK cycles RCCLK The internal 7 373 MHz RC oscillator output The clock doubler option when enabled provides an output frequency of 14 746 MHz PCLK Clock for the various peripheral devices and is CCLK CPU clock OSCCLK The P89LPC9331 9341 9351 9361 provides several user selectable oscillator options in generating the CPU clock This allows optimization for a range of needs from high precision to lowest possible cost These options are configured when the flash is programmed and include an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source Crystal oscillator option The crystal oscillator option can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 18 MHz It can be the clock source of OSCCLK and RTC Low speed oscillator option can be the clock source of WDT Low speed oscillator option This option supports an external crystal in the range of 20 kHz to 100 kHz Ceramic resonators are also supported in this configuration Medium speed oscillator option This option supports an externa
60. cillator 400 KHz Fig 38 Average watchdog oscillator frequency vs Vpp at 40 C 002aae350 1 5 frequency deviation 0 5 1 5 24 2 8 3 2 3 6 Vpp V Central frequency of watchdog oscillator 400 KHz Fig 39 Average watchdog oscillator frequency vs Vpp at 85 C All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 74 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 10 3 BOD characteristics Table 13 BOD static characteristics Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications 40 C to 125 C extended unless otherwise specified Symbol Parameter Conditions Min Typi Max Unit BOD interrupt Vtrip trip voltage falling stage BOICFG1 BOICFGO 01 2 25 2 55 V BOICFG1 BOICFGO 10 2 60 2 80 V BOICFG1 BOICFGO 11 3 10 3 40 V rising stage BOICFG1 BOICFGO 01 2 40 2 60 V BOICFG1 BOICFGO 10 2 70 2 90 V BOICFG1 BOICFGO 11 3 10 3 40 V BOD reset Virip trip voltage falling stage BOE1 BOEO 01 2 10 2 30 V BOE1 BOEO 10 2 35 2 50 V BOE1 BOEO 11 2 90 3 20 V rising stage BOE1 BOEO 01 2 20 2 40 V BOE1 BOEO 10 2 45 2 60 V BOE1 BOEO 11 2 90 3 30 V BOD EEPROM FLASH Vtrip
61. ck the timer The user will have to set a divider that scales PCLK by a factor from 1 to 16 This divider is found in the SFR register TCR21 The PLL frequency can be expressed as shown in Equation 1 PCLK 1 PLL frequency N 1 Where N is the value of PLLDV3 0 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 43 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 22 9 8 bit microcontroller with accelerated two clock 80C51 core Since N ranges from 0 to 15 the CCLK frequency can be in the range of PCLK to PCLK 16 CCU interrupts There are seven interrupt sources on the CCU which share a common interrupt vector EA ECCU TOIE2 TICR2 7 TOIF2 TIFR2 7 TICIE2A TICR2 0 TICF2A TIFR2 0 TICIE2B TICR2 1 TICF2B T TOCIE2A TICR2 3 TOCF2A T TOCIE2B TICR2 4 TOCF2B TIFR2 4 ICR2 5 TOCF2C TIFR2 5 ICR2 6 TOCF2D TIFR2 6 TOCIE2C T TOCIE2D T Fig 12 Capture compare unit interrupts IENO 7 IEN1 4 IFR2 1 IFR2 3 interrupt to other CPU interrupt Sources QOUDUOCU gt ENCINT O PRIORITY ENCODER gt ENCINT 1 ENCINT 2 002aaa896 7 23 7 23 1 P89LPC9331 9341 9351 9361 UART The P89LPC9331 9341 9351 936
62. continue until terminated by the user In P89LPC9351 9361 in fixed channel mode the PGA channel selection is independent and can be different to A D conversion channel selection If different the gain of the selected ADC channel is 1 Auto scan single conversion mode Any combination of the four input channels can be selected for conversion A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel An interrupt if enabled will be generated after all selected channels have been converted If only a single channel is selected this is equivalent to single channel single conversion mode In P89LPC9351 9361 in auto scan mode the PGA channel selection is dependent on the ADC channel selection If PGA is enabled all the selected channel for A D conversion will be amplified and the gain amplify level is the same Auto scan continuous conversion mode Any combination of the four input channels can be selected for conversion A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel An interrupt if enabled will be generated after all selected channels have been converted The process will repeat starting with the first selected channel Additional conversion results will again cycle through the eight result register pairs overwriting the previous results Cont
63. ctional output configuration 36 s f 7 26 Analog comparators 0 51 7 16 1 2 Open drain output configuration 36 7 26 1 Internal reference voltage 52 7 16 1 3 Input only configuration 37 7 26 2 Comparator interrupt 04 53 7 16 1 4 Push pull output configuration 37 7462 Port 0 analog functions 37 7 26 3 Comparators and power reduction modes 53 Nx Np a 7 27 KBl ilustre EC REED 53 7 16 3 Additional port features 37 oj 7 28 Watchdog timer 2 00 54 7 17 Power monitoring functions 37 n 7 29 Additional features lees 54 7 17 1 Brownout detection 005 38 7 29 1 Software reset 0 02 eee eee eee 54 7 17 2 Power on detection 0000 38 748 Power reduction modes toe eo a n 38 7 29 2 Dual data pointers 0 54 7 18 1 idle mode 38 7 29 3 Data EEPROM P89LPC9351 9361 55 7 18 2 Power down mode 20 00 38 s Fe progra MEMON cu pipinek pyts continued gt gt P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 93 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 6 1 8 6 2 8 6 3 8 6 4 8 6 5 8 6 6 8 7 8 7 1 8 7 2 8 7 3 8 7 4 8 8 8 9 8 10
64. device to pull the pin LOW When the pin is driven LOW it is driven strongly and able to sink a fairly large current These features are somewhat similar to an open drain output except that there are three pull up transistors in the quasi bidirectional output that serve different purposes The P89LPC9331 9341 9351 9361 is a 3 V device but the pins are 5 V tolerant In quasi bidirectional mode if a user applies 5 V on the pin there will be a current flowing from the pin to Vpp causing extra power consumption Therefore applying 5 V in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt trigger input that also has a glitch suppression circuit Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port driver when the port latch contains a logic 0 To be used as a logic output a port configured in this manner must have an external pull up typically a resistor tied to Vpp All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 36 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 16 1 3 7 16 1 4 7 16 2 7 16 3 7 17 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core An open drain port pin has a Schmitt trigger input that also has a glitch suppression
65. document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors prod
66. e bit addressable Name OCRBL OCRCH OCRCL OCRDH OCRDL Po P1 P2 P3 POM1 POM2 P1M1 P1M2 P2M1 P2M2 Description SFR addr Output compare FAH B register low Output compare FDH C register high Output compare FCH C register low Output compare FFH D register high Output compare FEH D register low Bit address Port 0 80H Bit address Port 1 90H Bit address Port 2 AOH Bit address Port 3 BOH Port 0 output 84H mode 1 Port 0 output 85H mode 2 Port 1 output 91H mode 1 Port 1 output 92H mode 2 Port 2 output A4H mode 1 Port 2 output A5H mode 2 Bit functions and addresses Reset value MSB LSB Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 87 86 85 84 83 82 81 80 T1 KB7 CMP1 CMPREF CIN1A CIN1B CIN2A CIN2B CMP2 H KB6 KB5 KB4 KB3 KB2 KB1 KBO 97 96 95 94 93 92 91 90 OCC OCB RST INT1 INTO SDA TO SCL RXD TXD iui A7 A6 A5 A4 A3 A2 A1 AO ICA OCA SPICLK SS MISO MOSI OCD ICB 0l B7 B6 B5 B4 B3 B2 B1 BO XTAL1 XTAL2 i POM1 7 POM1 6 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FFE 11111111 POM2 7 POM2 6 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 OO 0000 0000 P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D30 11x1 xx11 P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 O0 00x0 xx00 P2M1 7 P2M1 6 P2M1 5 P2M1 4 P2M1 3 P2M1 2 P2M1 1 P2M1 0 FFE 1111 1111
67. e buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters as long as the next character is written between the start bit and the stop bit of the previous character Double buffering can be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SBUF while the previous data is being shifted out Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD 0 Transmit interrupts with double buffering enabled modes 1 2 and 3 Unlike the conventional UART in double buffering mode the TI interrupt is generated when the double buffer is ready to receive new data The 9th bit bit 8 in double buffering modes 1 2 and 3 If double buffering is disabled TB8 can be written before or after SBUF is written as long as TB8 is updated some time before that bit is shifted out TB8 must not be changed until the bit is shifted out as indicated by the TI interrupt If double buffering is enabled TB must be updated before SBUF is written as TB8 will be double buffered together with SBUF data I C bus serial interface The I C bus uses two wires SDA and SCL to transfer information be
68. e see the P89LPC9331 9341 9351 9361 User manual for detail usage of temperature sensor P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 61 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 6 8 6 1 8 6 2 8 6 3 8 6 4 8 6 5 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core ADC operating modes Fixed channel single conversion mode A single input channel can be selected for conversion A single conversion will be performed and the result placed in the result register pair which corresponds to the selected input channel An interrupt if enabled will be generated after the conversion completes In P89LPC9351 9361 in fixed channel mode the PGA channel selection is dependent on the ADC channel selection If PGA is enabled all the selected channels for A D conversion will be amplified and the gain amplify level is the same Fixed channel continuous conversion mode A single input channel can be selected for continuous conversion The results of the conversions will be sequentially placed in the four result register The user may select whether an interrupt can be generated after every four conversions Additional conversion results will again cycle through the four result register overwriting the previous results Continuous conversions
69. ek cones eet he E EE pus be 44 7 4 8 High speed oscillator option 30 7 23 1 Mode ire ee ER ER RRE 44 7 5 Clock output 2 2 00 0c eee esee 31 7 23 2 Mod W sikerei ER RE RR ER RA 45 7 6 On chip RC oscillator option 31 7 23 3 Mode 2 iiia tinae bid edie dee wie is 45 7 7 Watchdog oscillator option 31 7 23 4 Mode 3 0 cece eee eee eee 45 7 8 External clock input option 31 pt 7 23 5 Baud rate generator and selection 45 7 9 Clock source switching on the fly 31 f 7 23 6 Framing error 02 00sec ee eee 45 7 10 CCLK wake up delay sues 32 LS 7 23 7 Breakdetect llllllllsseun 46 7 11 CCLK modification DIVM register 32 f 7 23 8 Double buffering 004 46 7 12 Low power select 0 0e ee aee 32 e 7 13 Memory organization 33 ieee Transmit interrupts with double buffering 7 14 Data RAM arrangement 33 ananena modes 1 aan Shee aa s 7 15 Interrupts scere he ens 33 VERE TNE S bit Oit 8 double buffering 7 15 1 External interrupt inputs 34 mones 2 and ME 2 716 l O ports 36 7 24 l C bus serial interface 46 P tS RM 7 25 SPls saw iue mi mi aina aee idu 49 7 16 1 Port configurations 004 36 AP abe 7 25 1 Typical SPI configurations 50 7 16 1 1 Quasi bidire
70. eprogrammed value Other resets will not cause initialization of the TRIM register The only reset sources that affect these SFRs are power on reset and watchdog reset 9102 16209 20J 2 0M pa1eJ9J929 YIM 19 043u0204J91UI 1Iq 8 L9 6 L6 6 Lv 6 L6 60d 168d SJOJONPUODIWIIS dXN yooys ejep jonpoJd eL0z 1SnDny oz L S ed sieuirejosip Jeba 0 joefqns si jueuunoop SIY ui PEPIAOI uoneuuojul Iv V6 1o 0c 196 LGE6 Lv 6 LEE6Od 168d paniasad suu Iv ZLOZ A 8 dXN GO Table 5 Extended special function registers P89LPC9331 93411 Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary BODCFG BOD FFC8H BOICFG1 BOICFGO El configuration register CLKCON CLOCK Control FFDEH CLKOK XTALWD CLKDBL FOSC2 FOSC1 FOSCO B register TPSCON Temperature FFCAH TSEL1 TSELO 00 0000 0000 sensor control register RTCDATH Real time clock FFBFH 00 00000000 data register high RTCDATL Real time clock FFBEH 00 0000 0000 data register low 1 2 3 Extended SFRs are physically located on chip but logically located in external data memory address space XDATA The MOVX A DPTR and MOVX DPTR A instructions are used to access these extended SFRs The BOICFG1 0 will be copied from UCFG1 5 and UCFG1 3 when power on reset CLKCON register reset value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to U
71. er Output Compare Interrupt Flag TOCFx becomes set An interrupt will occur if enabled Input capture Input capture is always enabled Each time a capture event occurs on one of the two input capture pins the contents of the timer is transferred to the corresponding 16 bit input capture register The capture event can be programmed to be either rising or falling edge triggered A simple noise filter can be enabled on the input capture by enabling the Input Capture Noise Filter bit If set the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event An event counter can be set to delay a capture by a number of capture events PWM operation PWM operation has two main modes symmetrical and asymmetrical In asymmetrical PWM operation the CCU timer operates in down counting mode regardless of the direction control bit In symmetrical mode the timer counts up down alternately The main difference from basic timer operation is the operation of the compare module which in PWM mode is used for PWM waveform generation As with basic timer operation when the PWM compare pins are connected to the compare logic their logic state remains unchanged However since bit FCO is used to hold the halt value only a compare event can change the state of the pin TOR2 compare value timer value 0x0000 non inverted inverted 002aaa893
72. erator SCL duty cycle register low I2STAT I2C bus status D9H STA 4 STA 3 register Bit address AF AE IENO Interrupt A8H EA EWDRT enable 0 Bit address EF EE FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 Reset value Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 70 0111 0000 00 0000 0000 00 0000 0000 00 x000 00x0 00 0000 0000 00 0000 0000 F8 1111 1000 00 0000 0000 SJOJONPUODIWIIS dXN 8109 16209 490 9 Om pa es9j9998 YIM 19 043u0204J91UI 1Iq 8 L9 6 LSE6 LVE6 LEEGOd 168d Jays Lep 19npoJd eL0z snbny oz L S ed sieuirejosip Jeba 0 joe qns si jueuinoop SIY ui pepi oid uoneuuojul y v6 10 OL 196 LGE6 Lv 6 LEE60d 168d pamasa Syu Iv ZLOZ N8 dXN Table 4 indicates SFRs that are bit addressable Special function registers P89LPC9331 9341 continued Name IEN1 IPO IPOH IP1 IP1H KBCON KBMASK KBPATN PO P1 P2 P3 POM1 POM2 Description SFR addr Interrupt E8H enable 1 Bit address Interrupt B8H priority 0 Interrupt B7H priority O high Bit address Interrupt F8H priority 1 Interrupt F7H priority 1 high Keypad control 94H register Keypad 86H interrupt mask register Keypadpattern 93H register Bit address Port 0 80H Bit address Port 1 90H Bit address Port 2 AOH Bit address Port 3 BOH Port 0 output 84H mode 1 Port 0 output 85H mode 2 Bit functions and addresses Reset value MSB LSB Hex Binary EAD EST
73. f 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core SS I tsPIF I tsPIR F TsPICYC md gt t gt t LP tSPILEAD spp l ISPICLKL A SRIR tsPILAG tSPICLKH SPICLK N N N CPOL 0 input tsPIF lt tsPIR tSPICLKL F8 1 SPICLK tSPICLKH CPOL 1 input N y tsPIOH gt tsPIOH i tsPIDV tsPIDV tsPIDv gt tsPIDIS tsPIA MISO y K not defined slave MSB LSB out Pd iinet S slave LSB MSB out p outpu Mo x tsPIDH lt gt HS tsPIDSU tsPIDsU tsPIDH MOSI v 2 NAV a X usus XX X X mens X XX LSB MSB in AN 002aaa911 Fig 46 SPI slave timing CPHA 1 11 2 ISP entry mode Table 16 Dynamic characteristics ISP entry mode Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications 40 C to 125 C extended unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit tyr Vpp active to RST active delay pin RST 50 us time tnu RST HIGH time pin RST 1 32 us ta RST LOW time pin RST 1 us Vpp Bn tRH RST TRL 002aaa912 Fig 47 ISP entry waveform P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012
74. gal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 54 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 29 3 7 30 7 30 1 7 30 2 P89LPC9331_9341_9351_9361 8 bit microcontroller with accelerated two clock 80C51 core Data EEPROM P89LPC9351 9361 The P89LPC9351 9361 has 512 bytes of on chip Data EEPROM The Data EEPROM is SFR based byte readable byte writable and erasable via row fill and sector fill The user can read write and fill the memory via SFRs and one interrupt This Data EEPROM provides 100 000 minimum erase program cycles for each byte Byte mode In this mode data can be read and written one byte at a time Row fill In this mode the addressed row 64 bytes is filled with a single value The entire row can be erased by writing 00H Sector fill In this mode all 512 bytes are filled with a single value The entire sector can be erased by writing OOH After the operation finishes the hardware will set the EEIF bit which if enabled will generate an interrupt The flag is cleared by software Remark When voltage supply is lower than 2 4 V the BOD EEPROM is tripped and Data EEPROM program or erase is blocked EWERR1 and EWERRO bits are used to indicate the write error for BOD EEPROM Both can be cleared by power on reset watchdog reset or software write Flash program memory General description The P89LPC9331 9341 9351 93
75. gister WDCON Watchdog control A7H register WDL Watchdog load C1H WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H Bit functions and addresses Reset value MSB LSB TPCR2L 7 TPCR2L 6 TPCR2L 5 TPCR2L 4 TPCR2L3 TPCR2L2 TPCR2L 1 TPCR2L 0 RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O PRE2 PRE1 PREO WDRUN WDTOF WDCLK Hex Binary 00 0000 0000 5 6 gre FF 1111 1111 1 2 3 4 All ports are in input only high impedance state after power up BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable The RSTSRC register reflects the cause of the P89LPC9351 9361 reset except BOIF bit Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is x011 0000 After reset the value is 1110 01x1 i e PRE2 to PREO are all logic 1 WORUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF On power on reset and watchdog reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register The only reset sources that affect these SFRs are power on reset and watchdog reset 94102 16209 20J 2 0M pa es9j9998 YIM 19 043u0204J91UI 1Iq 8 SJOJONPUODIWIIS dXN L9 6 LSE6 LVE6 LEEGOd 168d Jays Lep 19npoJd eL0z 1snDny
76. h is an 8 bit Counter with a divide by 32 prescaler In this mode the Timer register is configured as a 13 bit register Mode 0 operation is the same for Timer 0 and Timer 1 Mode 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register are used Mode 2 Mode 2 configures the Timer register as an 8 bit Counter with automatic reload Mode 2 operation is the same for Timer 0 and Timer 1 Mode 3 When Timer 1 is in Mode 3 it is stopped Timer 0 in Mode 3 forms two separate 8 bit counters and is provided for applications that require an extra 8 bit timer When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator Mode 6 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 40 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 20 6 7 21 7 22 7 22 1 7 22 2 7 22 3 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs are also used for the timer toggle outputs The port outputs will be a logic 1 prior to the first time
77. ile data storage Flash programming and erasing Four different methods of erasing or programming of the flash are available The flash may be programmed or erased in the end user application IAP under control of the application s firmware Another option is to use the ICP mechanism This ICP system provides for programming through a serial clock serial data interface As shipped from the factory the upper 512 bytes of user code space contains a serial ISP routine allowing for the device to be programmed in circuit through the serial port The flash may also be programmed or erased using a commercially available EPROM programmer which supports this device This device does not provide for direct verification of code memory contents Instead this device provides a 32 bit CRC result on either a sector or the entire user code space Remark When voltage supply is lower than 2 4 V the BOD FLASH is tripped and flash erase program is blocked ICP ICP is performed without removing the microcontroller from the system The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC9331 9341 9351 9361 through a two wire serial interface The NXP ICP facility has made in circuit programming in an embedded application using commercially available programmers possible with a minimum of additional expense in components and circuit board area The ICP function uses five pins Only a small connector needs to be av
78. in ADCO and operates over wide temperature In P89LPC9351 9361 two high speed programmable gain amplifiers PGA are integrated The PGAs provide selectable gains of 2x 4x 8x or 16x A block diagram of the ADC is shown in Figure 23 and Figure 24 Each ADC consists of a 4 input multiplexer which feeds a sample and hold circuit providing an input signal to comparator inputs The control logic in combination with the SAR drives a digital to analog converter which provides the other input to the comparator The output of the comparator is fed to the SAR 8 2 Features and benefits P89LPC9331 9341 9351 9361 W Two 8 bit 4 channel multiplexed input successive approximation ADCs All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 58 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 P89LPC9331_9341_9351_9361 8 bit microcontroller with accelerated two clock 80C51 core Programmable Gain Amplifier PGA with selectable gains of 2x 4x 8x or 16x P89LPC9351 9361 On chip wide range temperature sensor Four result registers for each A D Six operating modes Fixed channel single conversion mode Fixed channel continuous conversion mode Auto scan single conversion mode Auto scan continuous conversion mode Dual channel continuous conversion mode Single step mode Four conversion
79. in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 91 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b 17 Contact information whenever customer uses the product for automotive ap
80. ing System IEC 60134 Symbol Parameter Conditions Min Max Unit Tamb bias bias ambient temperature 55 125 C Tstg storage temperature 65 150 C loH 1 0 HIGH level output current per 20 mA input output pin loLq o LOW level output current per 20 mA input output pin Ivotot max maximum total input output current 100 mA Vstal crystal voltage on XTAL1 XTAL2 pin to Vss Vpp 0 5 V Vn voltage on any other pin except XTAL1 XTAL2 to Vss 0 5 45 5 V Ptot pack total power dissipation per package based on package heat 1 5 W transfer not device power consumption Vesp electrostatic discharge voltage human body model all pins 2 3000 3000 V charged device model all 700 700 V pins 1 The following applies to Table 11 a This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over ambient temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted 2 Human body model equivalent to discharging a 100 pF capacitor through a 1 5 kQ series resistor system frequency MHz 2 4 2 7 3 0 3 3 3 6 Vpp V 002aae351 Fig 25 Frequency vs supply voltage P89LPC9331 9341 9351 9361 All information provided in this d
81. inuous conversions continue until terminated by the user In P89LPC9351 9361 in auto scan mode the PGA channel selection is dependent on the ADC channel selection If PGA is enabled all the selected channel for A D conversion will be amplified and the gain amplify level is the same Dual channel continuous conversion mode This is a variation of the auto scan continuous conversion mode where conversion occurs on two user selectable inputs The result of the conversion of the first channel is placed in the result register ADxDATO The result of the conversion of the second channel is placed All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 62 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 6 6 8 7 8 7 1 8 8 8 P89LPC9331_9341_9351_9361 7 2 7 3 7 4 8 8 8 bit microcontroller with accelerated two clock 80C51 core in result register ADXDAT1 The first channel is again converted and its result stored in ADxDAT2 The second channel is again converted and its result placed in ADxDAT3 An interrupt is generated if enabled after every set of four conversions two conversions per channel In P89LPC9351 9361 in dual channel mode the PGA channel selection is independent and can be different to A D conversion channel selection If different the gain of the selected ADC channel
82. is 1 Single step mode This special mode allows single stepping in an auto scan conversion mode Any combination of the four input channels can be selected for conversion After each channel is converted an interrupt is generated if enabled and the A D waits for the next start condition May be used with any of the start modes In P89LPC9351 9361 in single step mode the PGA channel selection is independent and can be different to A D conversion channel selection If different the gain of the selected ADC channel is 1 Conversion start modes Timer triggered start An A D conversion is started by the overflow of Timer 0 Once a conversion has started additional Timer 0 triggers are ignored until the conversion has completed The Timer triggered start mode is available in all ADC operating modes Start immediately Programming this mode immediately starts a conversion This start mode is available in all ADC operating modes Edge triggered An A D conversion is started by rising or falling edge of P1 4 Once a conversion has started additional edge triggers are ignored until the conversion has completed The edge triggered start mode is available in all ADC operating modes Dual start immediately Programming this mode starts a synchronized conversion of both A D converters This start mode is available in all A D operating modes Both A D converters must be in the same operating mode In the continuous conversion modes both
83. ith industry standard commercial programmers All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 55 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 30 3 7 30 4 7 30 5 7 30 6 7 30 7 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Programmable security for the code in the flash for each sector 100 000 typical erase program cycles for each byte 10 year minimum data retention Flash organization The program memory consists of sixteen 1 kB sectors on the P89LPC9361 devices and eight 1 kB sectors on the P89LPC9341 9351 devices and four 1 kB sectors on the P89LPC9331 device Each sector can be further divided into 64 byte pages In addition to sector erase page erase and byte erase a 64 byte page register is included which allows from 1 byte to 64 bytes of a given page to be programmed at the same time substantially reducing overall programming time Using flash as data storage The flash code memory array of this device supports individual byte erasing and programming Any byte in the code memory array may be read using the MOVC instruction provided that the sector containing the byte has not been secured a MOVC instruction is not allowed to read code memory contents of a secured sector Thus any byte in a non secured sector may be used for non volat
84. l crystal in the range of 100 kHz to 4 MHz Ceramic resonators are also supported in this configuration High speed oscillator option This option supports an external crystal in the range of 4 MHz to 18 MHz Ceramic resonators are also supported in this configuration All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 30 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 P89LPC9331 9341 9351 9361 7 5 7 6 7 7 7 8 7 9 8 bit microcontroller with accelerated two clock 80C51 core Clock output The P89LPC9331 9341 9351 9361 supports a user selectable clock output function on the XTAL2 CLKOUT pin when crystal oscillator is not being used This condition occurs if another clock source has been selected on chip RC oscillator watchdog oscillator external clock input on XTAL1 and if the RTC and WDT are not using the crystal oscillator as their clock source This allows external devices to synchronize to the P89LPC9331 9341 9351 9361 This output is enabled by the ENCLK bit in the TRIM register The frequency of this clock output is that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power On chip RC oscillator option The P89LPC9331 9341 9351 9361 has a 6 bit TRIM register that can be used to tune the frequency of the RC osci
85. ll 8 bits have been converted The boundary status register BNDSTAO flags the channels which caused a boundary interrupt DAC output to a port pin with high output impedance Each ADC s DAC block can be output to a port pin In this mode the ADxDATS register is used to hold the value fed to the DAC After a value has been written to the DAC written to ADxDAT3 the DAC output will appear on the channel 3 pin Clock divider The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to maintain accuracy A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose Power down and Idle mode In Idle mode the ADC if enabled will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A D interrupt is enabled In Power down mode or Total Power down mode the A D PGA and temperature sensor do not function If the PGAs temperature sensor or the A D are enabled they will consume power Power can be reduced by disabling the PGA temperature sensor and A D All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 64 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 9 Limiting values Table 11 Limiting values In accordance with the Absolute Maximum Rat
86. llator During reset the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7 373 MHz 1 at room temperature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies When the clock doubler option is enabled UCFG2 7 1 the output frequency is 14 746 MHz If CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to logic 1 to reduce power consumption On reset CLKLP is logic 0 allowing highest performance access This bit can then be set in software if CCLK is running at 8 MHz or slower When clock doubler option is enabled BOE1 bit UCFG1 5 and BOEO bit UCFG1 3 are required to hold the device in reset at power up until Vpp has reached its specified level Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz calibrated to 5 96 at room temperature This oscillator can be used to save power when a high clock frequency is not needed External clock input option In this configuration the processor clock is derived from an external source driving the P3 1 XTAL1 pin The rate may be from 0 Hz up to 18 MHz The P3 0 XTAL2 pin may be used as a standard port pin or a clock output When using an oscillator frequency above 12 MHz BOE1 bit UCFG1 5 and BOEO bit UCFG1 3 are required to hold the device in reset at power up until Vpp has reached its specified level Clock source switching o
87. low power select clock 0 8 MHz frequency Glitch filter tgr glitch rejection time P1 5 RST pin 50 50 ns any pin except P1 5 RST 5 15 15 ns tsa signal acceptance time P1 5 RST pin 125 125 ns any pin except P1 5 RST 50 5 50 ns External clock tcHcx clock HIGH time see Figure 41 33 Toy clk tcLcx 33 ns teicx clock LOW time see Figure 41 33 Tey cik tcHcx 33 ns tcLcH clock rise time see Figure 41 8 8 ns tcHcL clock fall time see Figure 41 8 8 ns Shift register UART mode 0 TxixL serial port clock cycle see Figure 42 16Tey cli 1333 ns time tovxH output data set up to see Figure 42 13T gy ctk 1083 ns clock rising edge time txHax output data hold after see Figure 42 Tey clk 20 103 ns clock rising edge time txHpx input data hold after see Figure 42 0 0 ns clock rising edge time txupv input data valid to clock see Figure 42 150 150 ns rising edge time SPI interface spi SPI operating frequency slave 0 CCLKy 0 2 0 MHz master CCLK 3 0 MHz P89LPC9331_9341_9351_9361 Product data sheet All information provided in this document is subject to legal disclaimers Rev 5 1 20 August 2012 NXP B V 2012 All rights reserved 76 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Table 14 Dynamic characteristics 12 MHz continued Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to
88. m are the original dimensions A max UNIT Ay A2 A3 bp c pM E2 0 15 0 95 030 02 98 45 mm 11 005 080 999 o19 01 96 43 Notes 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included 2 Plastic interlead protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION ISSUE DATE IEC JEDEC JEITA PROJECTION SOT361 1 MO 153 Et 03 02 19 Fig 51 TSSOP package outline SOT361 1 P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers Product data sheet Rev 5 1 20 August 2012 NXP B V 2012 All rights reserved 88 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 14 Abbreviations 8 bit microcontroller with accelerated two clock 80C51 core P89LPC9331_9341_9351_9361 Table 19 Abbreviations Acronym ADC CPU CCU CRC DAC EPROM EEPROM EMI LSB MSB PGA PLL PWM RAM RC RTC SAR SFR SPI UART WDT Description Analog to Digital Converter Central Processing Unit Capture Compare Unit Cyclic Redundancy Check Digital to Analog Converter Erasable Programmable Read Only Memory Electrically Erasable Programmable Read Only Memory Electro Magnetic Interference Least Significant Bit Most Significant Bit Programmable Gain Amplifier Phase Locked Loop P
89. master MISO 8 BIT SHIFT lt REGISTER MOSI SPICLK SPI CLOCK GENERATOR PORT 1214 Fig 17 SPI single master single slave configuration slave 8 BIT SHIFT REGISTER 002aaa901 MISO gt MOSI gt SPICLK master MISO 8 BIT SHIFT lt REGISTER MOSI SPICLK SPI CLOCK GENERATOR gs n SS gt slave 8 BIT SHIFT REGISTER SPI CLOCK GENERATOR 002aaa902 Fig 18 SPI dual device configuration where either can be a master or a slave All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 50 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core master slave MISO 8 BIT SHIFT REGISTER MOSI MISO 8 BIT SHIFT MOS REGISTER SPICLK mam SS SPICLK SPI CLOCK GENERATOR port 8 BIT SHIFT REGISTER SPICLK port SS gt 002aaa903 Fig 19 SPI single master multiple slaves configuration 7 26 Analog comparators P89LPC9331_9341_9351_9361 Two analog comparators are provided on the P89LPC9331 9341 9351 9361 Input and output options allow use of the comparators in a number of different configurations Comparator operation is such that the output is a logical one which may be read in a register and or routed t
90. mation sess 3 7 20 1 Mode sies tA ERPEEEEY E be Rx AREA 40 34 Orderi ti 3 7 20 2 Mode ies I RR BE sauna i yio 40 i TOGT OPONSE E 7 20 3 Mode 2 ununao 40 4 Block diagram ssssssssssrssrsne 4 yon Mode a cetcuctviencateeuernsoedumuene 40 5 Functional diagram 5 7 20 5 Meu c c 40 6 Pinning information 6 7 20 6 Timer overflow toggle output 41 6 1 PUDE ot ccded wardnas ada Ep bde Re ice us e 721 RTO system timer crees 41 6 2 Pin dSSerbaDti ducc oce ceres VOV PIOS g 7 22 CCU P89LPC9351 9361 41 int 7 22 1 CCU clock reisais ragat i nanain uapa DE 41 7 Functional description 12 piae ie 7222 CCUCLK prescaling u un 41 7 1 Special function registers 12 iss 72 Enhanced CPU ee cese 30 7 22 3 Basic timer operation 41 73 Clocks 30 7 22 4 Output compare 00 eee ee eee 42 7 3 1 Clockdefinitions 0 00 ee ee dp fee OPU opra ane a din en eda iei igne b 7 22 6 PWM operation sels 42 7 3 2 CPU clock OSCCLK 0 30 7 22 7 Alternating output mode 43 7 4 Crystal oscillator option 30 7 22 8 PLL operation 02000e eee 43 7 4 1 Low speed oscillator option 30 7 22 9 CCU interrupts llle essen 44 7 4 2 Medium speed oscillator option 30 7 23 VART
91. n capacitance is characterized but not tested Measured with port in quasi bidirectional mode Measured with port in high impedance mode Port pins source a transition current when used in quasi bidirectional mode and externally driven from logic 1 to logic 0 This current is highest when V is approximately 2 V 9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 67 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 10 1 Current characteristics P89LPC9331 9341 9351 9361 Note The graphs provided are a statistical summary based on a limited number of samples and only for information purposes The performance characteristics listed are not tested or guaranteed 16 002aae363 l 18 MHz DD mA 12 12 MHz 8 8 MHz C e 6 MHz 2 MHz ne A 1 MHz 0 32 kHz 2 4 2 8 32 3 6 Vpp V Test conditions normal mode code while 1 executed from on chip flash using an external clock Fig 26 lIpp oper VS frequency at 25 C 16 002aae364 IDD 18 MHz mA 12 12 MHz 8 2 4 2 8 3 2 3 6 Vpp V Test conditions normal mode code while 1 executed from on chip flash using an external clock Fig 27 lpp oper VS frequenc
92. n the fly P89LPC9331 9341 9351 9361 can implement clock switching on any sources of watchdog oscillator 7 MHz 14 MHz internal RC oscillator crystal oscillator and external clock input during code is running CLKOK bit in CLKCON register is used to indicate the clock switch status CLKOK is cleared when starting clock source switch and set when completed Notice that when CLKOK is 0 writing to CLKCON register is not allowed All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 31 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Fig 7 XTAL1 XTAL2 OSCCLK CCLK CPU RC OSCILLATOR RCCLK En i WITH CLOCK DOUBLER PCLK 7 3728 MHz 14 7456 MHz 1 R ae 4 4 WATCHDOG i 4 OSCILLATOR 400 kHz 5 PCLK Block diagram of oscillator control HIGH FREQUENCY MEDIUM FREQUENCY gt RTC LOW FREQUENCY M T ADC1 T1 ADCO CCU 002aad559 7 10 7 11 7 12 P89LPC9331 9341 9351 9361 CCLK wake up delay The P89LPC9331 9341 9351 9361 has an internal wake up timer that delays the clock until it stabilizes depending on the clock source used If the clock source is any of the three crystal selections low medium and high frequencies the delay is 1024 OSCCLK
93. ns can be accomplished through the use of four SFRs consisting of a control status register a data register and two address registers Additional details may be found in the P89LPC9331 9341 9351 9361 User manual ISP ISP is performed without removing the microcontroller from the system The ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC9331 9341 9351 9361 through the serial port This firmware is provided by NXP and embedded within each P89LPC9331 9341 9351 9361 device The NXP ISP facility has made in system programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins Vpp Vss TXD RXD and RST Only a small connector needs to be available to interface your application to an external circuit in order to use this feature Power on reset code execution The P89LPC9331 9341 9351 9361 contains two special flash elements the Boot Vector and the Boot Status bit Following reset the P89LPC9331 9341 9351 9361 examines the contents of the Boot Status bit If the Boot Status bit is set to zero power up execution starts at location 0000H which is the normal start address of the user s application code When the Boot Status bit is set to a value other than zero the contents of the Boot Vector are used as the high byte of the execution address and the low byte is se
94. ntrol C8H PLEEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20 00 0000 0000 register 0 CCU control F9H TCOU2 PLLDV3 PLLDV 2 PLLDV 1 PLLDV O 00 Oxxx 0000 register 1 Timer 0 high 8CH 00 0000 0000 Timer 1 high 8DH 00 0000 0000 CCU timer high CDH 00 0000 0000 CCU interrupt C9H TOIE2 TOCIE2D TOCIE2C TOCIE2B TOCIE2A TICIE2B TICIE2A 00 0000 0x00 control register CCUinterruptflag E9H TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A TICF2B TICF2A 00 0000 0x00 register CCU interrupt DEH ENCINT 2 ENCINT 1 ENCINT O 00 xxxx x000 status encode register Timer 0 low 8AH 00 0000 0000 Timer 1 low 8BH 00 0000 0000 CCU timer low CCH 00 0000 0000 Timer 0 and 1 89H T1GATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 0000 0000 mode CCU reload CFH 00 0000 0000 register high CCU reload CEH 00 0000 0000 register low Prescaler control CBH TPCR2H 1 TPCR2H 0 00 Xxxx xx0O register high 9102 16209 490 9 Om pa1eJ9J929e YIM 19 043u0204J91UI 1Iq 8 L9 6 L6 6 Lv 6 L6 60d 168d 40 9npuooliul9S dXN yoays Lep jonpoJd eL0z snbny oz L S ed sieuirejosip 259 0 joefqns si jueuunoop SIY ui pepi oid uoneuuojul Iv V6 J0 8c 1966 LGE6 Lv 6 LEE6Od 168d paniasad suu Iv ZLOZ A 8 dXN GO Table 6 indicates SFRs that are bit addressable Special function registers P89LPC9351 9361 Name Description SFR addr TPCR2L Prescaler control CAH register low TRIM Internal oscillator 96H trim re
95. o 125 C extended unless otherwise specified L 2 Symbol Parameter Conditions Variable clock fose 18 MHz Unit Min Max Min Max tspiteaD SPI enable lead time see Figure 45 46 slave 250 250 ns tspiag SPI enable lag time see Figure 45 46 slave 250 250 ns tspicLkH SPICLK HIGH time see Figure 43 44 45 46 slave Yocik 167 ns master CCLK 111 ns tspicLkKL SPICLK LOW time see Figure 43 44 45 46 slave Yocik 167 ns master V CCLK 111 ns tspipsu SPI data set up time see Figure 43 44 45 46 master or slave 100 100 ns tsPIDH SPI data hold time see Figure 43 44 45 46 master or slave 100 100 ns tsPIA SPI access time see Figure 45 46 slave 0 80 0 80 ns tsPIDIS SPI disable time see Figure 45 46 slave 0 160 160 ns tspipv SPI enable to output see Figure 43 44 45 46 data valid time slave 160 160 ns master 111 111 ns tsPIOH SPI output data hold see Figure 43 44 45 46 0 0 ns time tspiR SPI rise time see Figure 43 44 45 46 SPI outputs SPICLK 100 100 ns MOSI MISO SPI inputs SPICLK 2000 2000 ns MOSI MISO SS tspiF SPI fall time see Figure 43 44 45 46 SPI outputs SPICLK 100 100 ns MOSI MISO SPI inputs SPICLK 2000 2000 ns MOSI MISO SS 1 Parameters are valid over operating temperature range unless otherwise specified 2 Parts are tested to 2 MHz but are guaranteed to operate down
96. o a pin when the positive input one of two selectable inputs is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes In P89LPC9351 9361 the positive inputs of comparators could be amplified by Programmable Gain Amplifier 1 PGA1 module The PGA1 can supply gain factors of 2x 4x 8x or 16x eliminating the need for external op amps in the end application The overall connections to both comparators are shown in Figure 20 and Figure 21 The comparators function to Vpp 2 4 V When each comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 us The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service When a comparator is disabled the comparator s output COn goes HIGH If the comparator output was LOW and then is disabled the resulting transition of the comparator output from a LOW to HIGH state will set the comparator flag CMFn This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the comparator flag CMFn after disabling the comparato
97. ocument is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 65 of 94 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core NXP Semiconductors 10 Static characteristics Table 12 Static characteristics Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications 40 C to 125 C extended unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit lDD oper Operating supply current Vpp 3 6 V fos 12 MHz 2 10 15 mA Vpp 3 6 V fosc 18 MHz 2 14 23 mA lDD idle Idle mode supply current Vpp 3 6 V fos 12 MHz BI 2 3 5 mA Vpp 3 6 V fosc 18 MHz BI 3 5 mA IDD pd Power down mode supply Vpp 3 6 V voltage 4 20 40 uA current comparators powered down IpD tpd total Power down mode all devices except B 0 5 5 pA supply current P89LPC9331HDH Vpp 3 6 V P89LPC9331HDH only BI 25 uA Vpp 3 6 V dV dt rise rate of Vpp to ensure power on 5 5000 V S reset signal Vpor power on reset voltage 0 5 V VppR data retention supply 1 5 V voltage Vin HL HIGH LOW threshold except SCL SDA 0 22Vpp 0 4Vpp V voltage Vit LOW level input voltage SCL SDA only 0 5 0 3Vpp V Vin LH LOW HIGH threshold except SCL SDA 0 6Vpp 0 7Vpp V voltage Vin HIGH level input voltage SCL SDA only 0 7Vpp 5 5 V Vhys hysteresis voltage port 1
98. ontrol D8H register I C bus data DAH register Serial clock DDH generator SCL duty cycle register high Serial clock DCH generator SCL duty cycle register low I2C bus status D9H register Bit functions and addresses Reset value MSB LSB Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 BUSY HVA HVE SV Ol 70 0111 0000 FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD O 00 0000 0000 I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR O GC 00 0000 0000 DF DE DD DC DB DA D9 D8 I2EN STA STO SI AA CRSEL 00 x000 00x0 00 0000 0000 00 0000 0000 STA 4 STA 3 STA 2 STA 1 STA O 0 0 0 F8 1111 1000 9102 16209 490 9 Om p91eJ9J929 YIM 19 043u0204J91UI 1Iq 8 L9 6 L6 6 Lv 6 L6 60d 168d SJOJONPUODIWIIS dXN 1eeus Lep 19npoJd eL0z snBny oz L S ed sieuirejosip Jeba 0 joefqns si jueuunoop siu ui pepi oid uoneuuojul y V6 J0 tc 196 LGE6 Lv 6 LEE6Od 168d panasad suu Iv ZLOZ A 8 dXN GO Table 6 Special function registers P89LPC9351 9361 indicates SFRs that are bit addressable Name ICRAH ICRAL ICRBH ICRBL IENO IEN1 IPO IPOH IP1 IP1H KBCON KBMASK KBPATN OCRAH OCRAL OCRBH Description SFR addr Input capture A ABH register high Input capture A AAH register low Input capture B AFH register high Input capture B AEH register low Bit address Interrupt enable 0 A8H Bit addres
99. ool 0000 0000 D7 D6 D5 D4 D3 D2 D1 DO CY AC FO RS1 RSO OV F1 P 00 0000 0000 PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00 000x BOIF BOF POF R_BK R_WD R_SF REX B RTCF RTCS1 RTCSO ERTC RTCEN 6024116 011x xx00 O0 6 0000 0000 O0 6 0000 0000 00 0000 0000 00 0000 0000 XX XXXX XXXX 9F 9E 9D 9C 9B 9A 99 98 SMO FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 07 0000 0111 SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPRO 04 0000 0100 9102 16209 320J 2 0M1 p91eJ9 929 YIM 19 043u0204J91UI 1Iq 8 L9 6 L6 6 Lv 6 L 6 60d 168d SJOJONPUODIWIIS dXN yooys Lep jonpoJd eL0z isnbny oz L S ed sieuirejosip Jeba 0 joefqns si jueuunoop SIY ui pepi oid uoneuuojul Iv V6 JO 7c 1966 LSE6 Lv 6 LEE6Od 168d penjiesei suu Iv ZLOZ A 8 dXN GO Table 6 Special function registers P89LPC9351 9361 indicates SFRs that are bit addressable Name SPSTAT SPDAT TAMOD TCON TCR20 TCR21 THO TH1 TH2 TICR2 TIFR2 TISE2 TLO TL1 TL2 TMOD TOR2H TOR2L TPCR2H Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary SPI status E1H SPIF WCOL 00 OOxx xxxx register SPI data register E3H 00 0000 0000 Timer 0 and 1 8FH T1M2 TOM2 00 xxx0 xxx0 auxiliary mode Bit address 8F 8E 8D 8c 8B 8A 89 88 Timer 0 and 1 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 0000 0000 control CCU co
100. ower down mode using internal RC oscillator with the following functions disabled comparators real time clock and watchdog timer 1 85 C 2 25 C 8 40 C Fig 32 Ipp pa VS VoD 002aae370 0 4 0 0 24 2 8 3 2 3 6 Vpp V Test conditions Total power down mode using internal RC oscillator with the following functions disabled comparators brownout detect real time clock and watchdog timer 1 85 C 2 40 C 3 25 C Fig 33 Ipp tpd VS VoD All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 71 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 10 2 Internal RC watchdog oscillator characteristics P89LPC9331 9341 9351 9361 Note The graphs provided are a statistical summary based on a limited number of samples and only for information purposes The performance characteristics listed are not tested or guaranteed 002aae344 0 2 frequency deviation 0 1 Voo V Central frequency of internal RC oscillator 7 3728 MHz Fig 34 Average internal RC oscillator frequency vs Vpp at 25 C 002aae346 0 2 frequency deviation 0 1 Vpp V
101. pecial functions as described below P0 0 CMP2 3 O P0 0 Port 0 bit 0 KBIO ADO1 O CMP2 Comparator 2 output l KBIO Keyboard input 0 ADO01 ADCO channel 1 analog input P0 1 CIN2B 26 l O P0 1 Port O bit 1 KBI1 AD10 CIN2B Comparator 2 positive input B l KBI1 Keyboard input 1 AD10 ADC1 channel 0 analog input P0 2 CIN2A 25 O P0O 2 Port 0 bit 2 KBI2 AD11 l CIN2A Comparator 2 positive input A l KBI2 Keyboard input 2 AD11 ADC1 channel 1 analog input P0 3 CIN1B 24 l O P0 3 Port 0 bit 3 High current source KBIS AD12 l CIN1B Comparator 1 positive input B KBI3 Keyboard input 3 AD12 ADC1 channel 2 analog input P0 4 CIN1A 23 l O P0 4 Port 0 bit 4 High current source KBI4 DAC1 AD13 l CIN1A Comparator 1 positive input A l KBI4 Keyboard input 4 O DAC1 Digital to analog converter output 1 l AD13 ADC1 channel 3 analog input P0 5 CMPREF 22 l O P0 5 Port 0 bit 5 High current source KBIS CMPREF Comparator reference negative input KBI5 Keyboard input 5 P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 8 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Table 3 Pin description continued Symbol
102. plications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 16 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP B V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 92 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 18 Contents 1 General description 1 7 18 3 Total Power down mode 39 2 Features and benefits ee 1 7 19 HGSGl used a eased dor Noc diu diet su e 39 24 Principal features 0 0 00 0 e eee e eee 1 7 19 1 Reset vector lleseeseeseesess 40 2 2 Additional features 000 000 2 720 Timers counters 0 and 1 40 3 Ordering infor
103. r All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 51 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Fig 21 Comparator input and output connections P89LPC9351 9361 CP1 i OE1 P0 4 CIN1A i comparator 1 P0 3 CIN1B CMP 1 P0 6 P0 5 CMPREF e Vref bg 4 2 CN1 gt interrupt change detect CP2 EC Ex P0 2 CIN2A comparator 2 P0 1 CIN2B vat CMP2 P0 0 3 CO2 OE2 CN2 002aae483 Fig 20 Comparator input and output connections P89LPC9331 9341 CP1 P0 4 CIN1A comparator 1 e P0 3 CIN1B CO1 gt A CMP1 P0 6 PGA1 P0 5 CMPREF n C Vret bg change detect P0 2 CIN2A P0 1 CIN2B CN1 Ea gt interrupt change detect B 2c 9 i i CMF2 comparator 2 na CMP2 P0 0 CO2 i OE2 CN2 002aad561 7 26 1 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used The value of the internal reference voltage referred to as Vref bg is 1 23 V 10 P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All right
104. r manner as Timer 1 but is much more accurate If the baud rate generator is used Timer 1 can be used for other timing functions The UART can use either Timer 1 or the baud rate generator output see Figure 13 Note that Timer T1 is further divided by 2 if the SMOD1 bit PCON 7 is cleared The independent baud rate generators use OSCCLK timer 1 overflow SMOD1 1 PCLK based LU SBRGS 0 o baud rate modes 1 and 3 SMOD1 0 baud rate generator SBRGS 1 CCLK based 002aaa897 Fig 13 Baud rate sources for UART Modes 1 3 Framing error Framing error is reported in the status register SSTAT In addition if SMODO PCON 6 is logic 1 framing errors can be made available in SCON 7 respectively If SMODO is logic 0 SCON 7 is SMO It is recommended that SMO and SM1 SCON 7 6 are set up when SMODO is logic O All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 45 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 23 7 7 23 8 7 23 9 7 23 10 7 24 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Break detect Break detect is reported in the status register SSTAT A break is detected when 11 consecutive bits are sensed LOW The break detect can be used to reset the device and force the device into ISP mode Doubl
105. r overflow when this mode is turned on RTC system timer The P89LPC9331 9341 9351 9361 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down The RTC can be a wake up or an interrupt source The RTC is a 23 bit down counter comprised of a 7 bit prescaler and a 16 bit loadable down counter When it reaches all logic Os the counter will be reloaded again and the RTCF flag will be set The clock source for this counter can be either the CPU clock CCLK or the XTAL oscillator Only power on reset and watchdog reset will reset the RTC and its associated SFRs to the default state The 16 bit loadable counter portion of the RTC is readable by reading the RTCDATL and RTCDATH registers CCU P89LPC9351 9361 This unit features A 16 bit timer with 16 bit reload on overflow Selectable clock with prescaler to divide clock source by any integral number between 1 and 1024 Four compare PWM outputs with selectable polarity Symmetrical asymmetrical PWM selection Two capture inputs with event counter and digital noise rejection filter Seven interrupts with common interrupt vector one overflow two capture four compare Safe 16 bit read write via shadow registers CCU clock The CCU runs on the CCUCLK which is either PCLK in basic timer mode or the output of a PLL The PLL is designed to use a clock source between 0 5 MHz to 1 MHz that is multiplied by 32 to p
106. read 1 must be written with 1 and will return a 1 when read P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 12 of 94 yooys ejep jonpoJd eL0z snbny oz L S ed sieuirejosip Jeba 0 joefqns si jueuunoop SIY ui pepi oid uoneuuojul y v6 0 L 196 LSE6 Lv 6 LEE6Od 168d pamasa suu Iv ZLOZ A 8 dXN GO Table 4 indicates SFRs that are bit addressable Special function registers P89LPC9331 9341 Name ACC ADCONO ADCON1 ADINS ADMODA ADMODB ADOBH ADOBL ADODATO ADODAT1 ADODAT2 ADODAT3 AD1BH AD1BL Description SFR addr Bit address Accumulator EOH A D control 8EH register 0 A D control 97H register 1 A D input ASH select A D mode COH register A A D mode A1H register B A D 0 BBH boundary high register A D 0O A6H boundary low register A D 0 data C5H register 0 A D_0 data C6H register 1 A D 0 data C7H register 2 A D 0 data F4H register 3 A D 1 C4H boundary high register A D_1 BCH boundary low register Bit functions and addresses Reset value MSB E7 ENBIO ENBI1 ADI13 BNDI1 CLK2 E6 ENADCIO ENADCI1 ADI12 BURST1 CLK1 E5 TMMO TMM1 ADI11 SCC1 CLKO E4 EDGEO EDGE1 ADI10 SCAN1 INBND
107. reset BOD interrupt and BOD EEPROM FLASH BOD reset is always on except in total Power down mode It could not be disabled in software BOD interrupt may be enabled or disabled in software BOD EEPROM FLASH is always on except in Power down modes and could not be disabled in software BOD reset and BOD interrupt each has four trip voltage levels BOE1 bit UCFG1 5 and BOEO bit UCFG1 3 are used as trip point configuration bits of BOD reset BOICFG1 bit and BOICFGO bit in register BODCFG are used as trip point configuration bits of BOD interrupt BOD reset voltage should be lower than BOD interrupt trip point BOD EEPROM FLASH is used for flash Data EEPROM programming erase protection and has only 1 trip voltage of 2 4 V Please refer to P89LPC933 1 934 1 935 1 9361 User manual for detail configurations If brownout detection is enabled the brownout condition occurs when Vpp falls below the brownout trip voltage and is negated when Vpp rises above the brownout trip voltage For correct activation of brownout detect the Vpp rise and fall times must be observed Please see Table 12 Static characteristics for specifications Power on detection The Power on detect has a function similar to the brownout detect but is designed to work as power comes up initially before the power supply voltage reaches a level where brownout detect can work The POF flag in the RSTSRC register is set to indicate an initial power up condition The POF flag
108. roduce a CCUCLK between 16 MHz and 32 MHz in PWM mode asymmetrical or symmetrical The PLL contains a 4 bit divider to help divide PCLK into a frequency between 0 5 MHz and 1 MHz CCUCLK prescaling This CCUCLK can further be divided down by a prescaler The prescaler is implemented as a 10 bit free running counter with programmable reload at overflow Basic timer operation The timer is a free running up down counter with a direction control bit If the timer counting direction is changed while the counter is running the count sequence will be reversed The timer can be written or read at any time All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 41 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 22 4 7 22 5 7 22 6 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core When a reload occurs the CCU Timer Overflow Interrupt Flag will be set and an interrupt generated if enabled The 16 bit CCU timer may also be used as an 8 bit up down timer Output compare There are four output compare channels A B C and D Each output compare channel needs to be enabled in order to operate and the user will have to set the associated I O pin to the desired output mode to connect the pin When the contents of the timer matches that of a capture compare control register the Tim
109. rs IPO IPOH IP1 and IP1H An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are pending at the start of an instruction the request of higher priority level is serviced If requests of the same priority level are pending at the start of an instruction an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used to resolve pending requests of the same priority level External interrupt inputs The P89LPC9331 9341 9351 9361 has two external interrupt inputs as well as the Keypad Interrupt function The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers These external interrupts can be programmed to be level triggered or edge triggered by setting or clearing bit IT1 or ITO in Register TCON In edge triggered mode if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle the interrupt request flag IEn in TCON is set causing an interrupt request If an external interrupt is enabled when the P89LPC9331 9341 9351 9361 is put into Power down or Idle mode the interrupt will cause the processor to wake up and resume operation Refer to Section 7 18
110. s Interrupt enable 1 E8H Bit address Interrupt priority 0 B8H Interrupt priority O B7H high Bit address Interrupt priority 1 FBH Interrupt priority 1 F7H high Keypad control 94H register Keypad interrupt 86H mask register Keypad pattern 93H register Output compare EFH A register high Output compare EEH A register low Output compare FBH B register high Bit functions and addresses Reset value MSB LSB Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 AF AE AD AC AB AA A9 A8 EA EWDRT EBO ES ESR ET1 EX1 ETO EXO 00 0000 0000 EF EE ED EC EB EA E9 E8 EADEE EST ECCU ESPI EC EKBI EI2C ool 00x0 0000 BF BE BD BC BB BA B9 B8 PWDRT PBO PS PSR PT1 PX1 PTO PXO ool x000 0000 PWDRTH PBOH PSH PT1H PX1H PTOH PXOH ool x000 0000 PSRH FF FE FD FC FB FA F9 F8 PADEE PST PCCU PSPI PC PKBI PI2C ool 00x0 0000 PAEEH PSTH PCCUH PSPIH PCH PKBIH PI2CH ool 00x0 0000 E E E E 3 PATN KBIF ool xxxx xx00 SEL 00 0000 0000 FF 1111 1111 00 0000 0000 00 0000 0000 00 0000 0000 9109 16209 490 9 Om p91eJ9 929 UM 19 043u0204J91UI 1Iq 8 L9 6 LG 6 Lv 6 L6 60d 168d SJOJONPUODIWIIS dXN yooys Lep jonpoJd zLoz 1SnDny oz L S ed sieuirejosip Jeba o1 1oefqns si jueuunoop SIY ui pepi oid uoneuuojul y V6 JO SC 1966 LSE6 Lv 6 LEE6Od 168d pamasa suu Iv ZLOZ A a dXN GO Table 6 Special function registers P89LPC9351 9361 indicates SFRs that ar
111. s as well as in the normal operating mode This fact should be taken into account when system power consumption is an issue To minimize power consumption the user can disable the comparators via PCONA 5 or put the device in Total Power down mode KBI The Keypad Interrupt function KBI is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks The Keypad Interrupt Mask Register KBMASk is used to define which input pins connected to Port 0 can trigger the interrupt The Keypad Pattern Register KBPATN is used to define a pattern that is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Interrupt function is active An interrupt will be generated if enabled The PATN_SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in P87LPC76x series the user needs to set KBPATN OFFH and PATN_SEL 1 not equal then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled The interrupt may be used to wake up
112. s reserved Product data sheet Rev 5 1 20 August 2012 52 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 26 2 7 26 3 7 27 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Comparator interrupt Each comparator has an interrupt flag contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by software or may be used to generate an interrupt The two comparators use one common interrupt vector If both comparators enable interrupts after entering the interrupt service routine the user needs to read the flags to determine which comparator caused the interrupt Comparators and power reduction modes Either or both comparators may remain enabled when Power down or Idle mode is activated but both comparators are disabled automatically in Total Power down mode If a comparator interrupt is enabled except in Total Power down mode a change of the comparator output state will generate an interrupt and wake up the processor If the comparator output to a pin is enabled the pin should be configured in the push pull mode in order to obtain fast switching times while in Power down mode The reason is that with the oscillator stopped the temporary strong pull up that normally occurs during switching on a quasi bidirectional port pin does not take place Comparators consume power in Power down and Idle mode
113. ss otherwise specified All limits valid for an external source impedance of less than 10 kQ Symbol ViA Cia Ep EL adj Eo Eg Euttot Mcrc Oct port SRin Tey ADC tapc PGA ts PGA GPGA tstartup Votfset O nom Parameter Conditions analog input voltage analog input capacitance differential linearity error integral non linearity offset error gain error total unadjusted error channel to channel matching crosstalk between port inputs 0 kHz to 100 kHz input slew rate ADC clock cycle time ADC conversion time ADC enabled PGA settling time within accuracy of ADC PGA gain G G 2 G 4 G 8 G 16 start up time nominal output offset voltage temperature sensor Vsen TC tstartup sensor voltage Tamb 25 C temperature coefficient start up time Min Vss 0 4 0 95 1 87 3 70 7 22 14 38 Typ 1 00 1 97 3 89 7 60 15 14 100 570 11 200 Max Vpp 0 4 15 t1 t1 2 t1 2 t1 60 100 2000 13Tcy apC 1 05 2 07 4 08 7 98 15 90 Unit pF LSB LSB LSB 96 LSB LSB dB V ms ns us V V V V V V V V V V mV mV mV C us P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 84 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core
114. start modes Timer triggered start Start immediately Edge triggered Dual start immediately 8 bit conversion time of 2 1 61 us at an A D clock of 8 0 MHz Interrupt or polled operation Boundary limits interrupt DAC output to a port pin with high output impedance Clock divider Power down mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 59 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 8 3 Block diagram input MUX REESE ADOO an comp I ADO1 v Anin02 SAR ADOS Anin03 I AD03 Vref bg Vsen input MUX 8 o DACO I I eee M CONTROL input MUX i LOGIC AD10 Anin10 comp AD11 Anin11 AD12 ne ae SAR AD13 4 Y AE a cae DAC1 a ee eee CCLK 4 I to comparators 002226463 Fig 23 P89LPC9331 9341 ADC block diagram P89LPC9331 9341 9351 9361 All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 60 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core ADOO input MUX ADO1 Anin00 comp Abos P
115. t l INTO External interrupt 0 input lO SDA l C bus serial data input output P1 4 INT1 10 l O P1 4 Port 1 bit 4 High current source l INT1 External interrupt 1 input P1 5 RST 6 l P1 5 Port 1 bit 5 input only l RST External Reset input during power on or if selected via UCFG1 When functioning as a reset input a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 Also used during a power on sequence to force ISP mode P1 6 OCB 5 lO P1 6 Port 1 bit 6 High current source O OCB Output Compare B P89LPC9351 9361 P1 7 OCC ADOO 4 lO P1 7 Port 1 bit 7 High current source O OCC Output Compare C P89LPC9351 9361 P89LPC9331_9341_9351_9361 AD00 ADCO channel 0 analog input All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 9 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Table 3 Pin description continued Symbol Pin Type Description PLCC28 TSSOP28 P2 0 to P2 7 l O Port 2 Port 2 is an 8 bit I O port with a user configurable output type During reset Port 2 latches are configured in the input only mode with the internal pull up disabled The operation of Port 2 pins
116. t 1 output 92H mode 2 Port 2 output A4H mode 1 Port 2 output A5H mode 2 Port 3 output B1H mode 1 Port 3 output B2H mode 2 Power control 87H register Power control B5H register A Bit address Program status DOH word Port 0 digital F6H input disable Reset source DFH register RTC control D1H RTC register D2H high RTC register D3H low Serial port A9H address register Serial port B9H address enable Bit functions and addresses Reset value MSB LSB Hex Binary P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D3U 11x1 xx11 P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 00 00x0 xx00 P2M1 7 P2M1 6 P2M1 5 P2M1 4 P2M1 3 P2M1 2 P2M1 1 P2M1 0 FFOI 1111 1111 P2M2 7 P2M2 6 P2M2 5 P2M2 4 P2M2 3 P2M2 2 P2M2 1 P2M2 0 ool 0000 0000 P3M1 1 P3M1 0 03U xxxx xx11 P3M2 1 P3M2 0 ool Xxxx xx00 SMOD1 SMODO BOI GF1 GFO PMOD1 PMODO 00 0000 0000 RTCPD i VCPD ADPD I2PD SPPD SPD ool 0000 0000 D7 D6 D5 D4 D3 D2 D1 DO CY AC FO RS1 RSO OV F1 P 00 0000 0000 PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00 000x BOIF BOF POF R_BK R_WD R_SF REX B RTCF RTCS1 RTCSO x ERTC RTCEN 60l 6 011x xx00 00181 0000 0000 00181 0000 0000 00 0000 0000 00 0000 0000 9102 16209 490 9 Om pa1eJ9 929 UM 19 043u0204J91UI 1Iq 8 L9 6 LSE6 LVE6 LEEGOd 168d SJOJONPUODIWISS dXN Jays Lep 19npoJd eL0z isnbny oz
117. t m 30 450 uA current Vpp 3 6 V Rrst_n int internal pull up resistance pin RST 10 30 kQ on pin RST Vref bg band gap reference voltage 1 19 1 23 1 27 V TCbg band gap temperature 10 20 ppm coefficient oC 1 2 3 4 5 6 7 8 9 10 11 P89LPC Typical ratings are not guaranteed The values listed are at room temperature 3 V The Ipp oper Specification is measured using an external clock with code while 1 executed from on chip flash The Ipp gie Specification is measured using an external clock with no active peripherals with the following functions disabled real time clock and watchdog timer The Ipp pa specification is measured using internal RC oscillator with the following functions disabled comparators real time clock and watchdog timer The Ipp tpa specification is measured using an external clock with the following functions disabled comparators real time clock brownout detect and watchdog timer See Section 9 Limiting values for steady state non transient limits on loi or lou If loi Ioy exceeds the test condition VoL Vo may exceed the related specification This specification can be applied to pins which have A D input or analog comparator input functions when the pin is not being used for those analog functions When the pin is being used as an analog input pin the maximum voltage on the pin must be limited to 4 0 V with respect to Vss Pi
118. t to 00H Table 10 shows the factory default Boot Vector setting for these devices A factory provided bootloader is pre programmed into the address space indicated and uses the indicated bootloader entry point to perform ISP functions This code can be erased by the user Remark Users who wish to use this loader should take precautions to avoid erasing the 1 kB sector that contains this bootloader Instead the page erase function can be used to erase the first eight 64 byte pages located in this sector A custom bootloader can be written with the Boot Vector set to the custom bootloader if desired Table 10 Default boot vector values and ISP entry points Device Default Default Default bootloader 1 kB sector boot vector bootloader code range range entry point P89LPC9331 OFH OFOOH OEO0H to OFFFH OCOOH to OFFFH All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 57 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Table 10 Default boot vector values and ISP entry points continued Device Default Default Default bootloader 1 kB sector boot vector bootloader code range range entry point P89LPC9341 1FH 1F00H 1EO00H to 1FFFH 1C00H to 1FFFH P89LPC9351 1FH 1F00H 1E00H to 1FFFH 1C00H to 1FFFH P89LPC9361 3FH 3F00H 3E00H to 3FFFH 3C00H to 3FF
119. tches are configured in the input only mode with the internal pull up disabled The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 16 1 Port configurations and Table 12 Static characteristics for details All pins have Schmitt trigger inputs Port 3 also provides various special functions as described below P3 0 XTAL2 9 O P3 0 Port 3 bit 0 CLKOUT O XTAL2 Output from the oscillator amplifier when a crystal oscillator option is selected via the flash configuration O CLKOUT CPU clock divided by 2 when enabled via SFR bit ENCLK TRIM 6 P89LPC9331_9341_9351_9361 It can be used if the CPU clock is the internal RC oscillator watchdog oscillator or external clock input except when XTAL1 XTAL2 are used to generate clock source for the RTC system timer All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 10 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 Table 3 Pin description continued 8 bit microcontroller with accelerated two clock 80C51 core Symbol P3 1 XTAL1 Vss Vpp Pin PLCC28 TSSOP28 8 21 Type Description 1 0 P3 1 Port 3 bit 1 XTAL1 Input to the oscillator circuit and internal clock generator circuits when selected via
120. the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use In order to set the flag and cause an interrupt the pattern on Port 0 must be held longer than six CCLKs All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 53 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 7 28 Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count It consists of a programmable 12 bit prescaler and an 8 bit down counter The down counter is decremented by a tap taken from the prescaler The clock source for the prescaler can be the PCLK the nominal 400 kHz watchdog oscillator or low speed crystal oscillator The watchdog timer can only be reset by a power on reset When the watchdog feature is disabled it can be used as an interval timer and may generate an interrupt Figure 22 shows the watchdog timer in Watchdog mode Feeding the watchdog requires a two byte sequence If PCLK is selected as the watchdog clock and the CPU is powered down the watchdog is disabled The watchdog timer has a time out period that ranges from a few us to
121. timers each may be configured to toggle a port output upon timer overflow or to become a PWM output E A 23 bit system timer that can also be used as a real time clock consisting of a 7 bit prescaler and a programmable and readable 16 bit timer E Enhanced UART with a fractional baud rate generator break detect framing error detection and automatic address detection 400 kHz byte wide I C bus communication port and SPI communication port B Capture Compare Unit CCU provides PWM input capture and output compare functions PB9LPC9351 9361 B 2 4 V to 3 6 V Vpp operating range I O pins are 5 V tolerant may be pulled up or driven to 5 5 V B Enhanced low voltage brownout detect allows a graceful system shutdown when power fails E 28 pin TSSOP and PLCC packages with 23 I O pins minimum and up to 26 I O pins while using on chip oscillator and reset options NXP Semiconductors P89LPC9331 9341 9351 9361 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 2 2 Additional features A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz This is six times the performance of the standard 80C51 running at the same clock frequency A lower clock frequency for the same performance results in power savings and reduced EMI Serial flash In Circuit Programming ICP allows simple production coding with
122. tion included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 16 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this
123. tween devices connected to the bus and it has the following features Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer e The I C bus may be used for test and diagnostic purposes A typical 1 C bus configuration is shown in Figure 14 The P89LPC9331 9341 9351 9361 device provides a byte oriented I C bus interface that supports data transfers up to 400 kHz All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 46 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 P89LPC9331_9341_9351_9361 8 bit microcontroller with accelerated two clock 80C51 core 12C bus Rp Rp SDA SCL P89LPC9331 9341 P1 3 SDA P1 2 SCL OTHER DEVICE WITH I2C BUS 9351 9361 INTERFACE Fig 14 I C bus configuration OTHER DEVICE WITH I C BUS INTERFACE 002aad731 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1
124. uct can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer
125. ud rate is variable and is determined by the Timer 1 overflow rate or the baud rate generator described in Section 7 23 5 Baud rate generator and selection Mode 2 11 bits are transmitted through TXD or received through RXD start bit logic 0 8 data bits LSB first a programmable 9 data bit and a stop bit logic 1 When data is transmitted the 9th data bit TB8 in SCON can be assigned the value of logic 0 or logic 1 Or for example the parity bit P in the PSW could be moved into TB8 When data is received the 9t data bit goes into RB8 in special function register SCON while the stop bit is not saved The baud rate is programmable to either 16 or 1 2 of the CPU clock frequency as determined by the SMOD bit in PCON Mode 3 11 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first a programmable 9 data bit and a stop bit logic 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the baud rate generator described in Section 7 23 5 Baud rate generator and selection Baud rate generator and selection The P89LPC9331 9341 9351 9361 enhanced UART has an independent baud rate generator The baud rate is determined by a baud rate preprogrammed into the BRGR1 and BRGRO SFRs which together form a 16 bit baud rate divisor value that works in a simila
126. ulse Width Modulator Random Access Memory Resistance Capacitance Real Time Clock Successive Approximation Register Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver Transmitter WatchDog Timer All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 89 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core 15 Revision history Table 20 Revision history Document ID P89LPC9331_9341_9351_ 9361 v 5 1 Modifications P89LPC9331_9341_9351_ 9361 v 5 Modifications Release date Data sheet status Change notice Supersedes 20120820 Product data sheet P89LPC9331 9341 9351 9361 v 5 e Table 6 Special function registers P89LPC9351 9361 Corrected reset value for DEECON register 20110110 Product data sheet P89LPC9331 9341 9351 9361 v 4 Table 12 Static characteristics Added Vpon Section 7 19 Reset Added sentence When this pin functions as a reset input P89LPC9331 9341 9351 20100910 Product data sheet z P89LPC9331_9341_ 9361 v 4 9351_ 9361 v 3 P89LPC9331_9341_9351_ 20090602 Product data sheet P89LPC9331_9341_ 9361 v 3 9351 v 2 P89LPC9331_9341_9351 v 2 20090505 Product data sheet P89LPC9351 v 1 P89LPC9351 v 1 20081119 Preliminary data sheet P89LPC9331_9341_9
127. w 1 Extended SFRs are physically located on chip but logically located in external data memory address space XDATA The MOVX A DPTR and MOVX DPTR A instructions are used to access these extended SFRs 2 The BOICFG1 0 will be copied from UCFG1 5 and UCFG1 3 when power on reset 3 CLKCON register reset value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 4 On power on reset and watchdog reset the PGAxTRIM8X16X and PGAxTRIM2XAX registers are initialized with a factory preprogrammed value Other resets will not cause initialization 9102 16209 320J 2 0M p91eJ9 929 YIM 19 043u0204J91UI 1Iq 8 L9 6 L6 6 Lv 6 L6 60d 168d SJOJONPUODIWIIS dXN NXP Semiconductors P89LPC9331 9341 9351 9361 7 2 7 3 7 3 1 7 3 2 7 4 7 4 1 7 4 2 7 4 3 P89LPC9331_9341_9351_9361 8 bit microcontroller with accelerated two clock 80C51 core Enhanced CPU The P89LPC9331 9341 9351 9361 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices A machine cycle consists of two CPU clock cycles and most instructions execute in one or two machine cycles Clocks Clock definitions The P89LPC9331 9341 9351 9361 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of four clock Sources see Figure 7 and
128. will remain set until cleared by software Power reduction modes The P89LPC9331 9341 9351 9361 supports three different power reduction modes These modes are Idle mode Power down mode and total Power down mode Idle mode Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may terminate Idle mode Power down mode The Power down mode stops the oscillator in order to minimize power consumption The P89LPC9331 9341 9351 9361 exits Power down mode via any reset or certain interrupts In Power down mode the power supply voltage may be reduced to the data retention supply voltage Vppn This retains the RAM contents at the point where Power down mode was entered SFR contents are not guaranteed after Vpp has been lowered to Vppn therefore it is highly recommended to wake up the processor via reset in this case Vpp must be raised to within the operating range before the Power down mode is exited All information provided in this document is subject to legal disclaimers NXP B V 2012 AII rights reserved Product data sheet Rev 5 1 20 August 2012 38 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 7 18 3 7 19 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core Some chip functions continue to operate and draw power during Power down mode increasing the total power used
129. y at 40 C All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 68 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 P89LPC9331_9341_9351_9361 8 bit microcontroller with accelerated two clock 80C51 core 16 002aae365 18 MHz IDD mA 12 12 MHz 8 8 MHz 6 MHz 4 T Ls ee 4 MHz 2 MHz 1 MHz 0 32 kHz 2 4 2 8 3 2 3 6 Vpp V Test conditions normal mode code while 1 executed from on chip flash using an external clock Fig 28 lIpp oper VS frequency at 85 C 002aae366 5 0 18 MHz Ipp mA 4 0 12 MHz 3 0 8 MHz 2 0 6 MHz Eee es 4 MHz 1 0 a 2MHz 1 MHz 32 kHz 0 0 24 2 8 3 2 3 6 Vpp V Test conditions idle mode entered executing code from on chip flash using an external clock with no active peripherals with the following functions disabled real time clock and watchdog timer Fig 29 Ipp igie VS frequency at 25 C All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Product data sheet Rev 5 1 20 August 2012 69 of 94 NXP Semiconductors P89LPC9331 9341 9351 9361 P89LPC9331 9341 9351 9361 8 bit microcontroller with accelerated two clock 80C51 core

P89LPC9331/9341/9351/9361 8-bit microcontroller with

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