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"TMS320C6000 Expansion Bus to MPC860

1. X mon mpce860_breq E ie mpc860_bgnt mpe860_bb gt E B Jmpc860 277777754 2 BS POS 1 mpc860_bdip ER 00 ns 5 us 00 ns 00 ns 15300 ns 00 ns Entity chiptb Architecture bhv Date Mon Mar 15 15 07 19 1999 Page 1 gorsvtuds SLNAINNULSN SVX3L 35 TEXAS INSTRUMENTS SPRA540B Table 4 Timing Requirements for TMS320C6000 MPC860 Expansion Bus Master MPC860 Symbol C6000 Symbol Parameter MPC860 C6000 Min ns Min ns Tcyc B8 tPAL Tsu XCSV XCKIH Chip select XCS valid before 10 3 5 XCLKIN high B12 tPAL Th XCKIH XCSV Chip select XCS valid after 11 25 2 8 XCLKIN high 11 Tsu XASV XCKIH Address strobe XAS valid before 15 75 3 5 XCLKIN high B11 Th XCKIH XASV Address strobe XAS valid after 6 25 2 8 XCLKIN high Tcyc B8a Tsu XBLTV XCKIH Burst last XBLAST valid before 15 3 5 XCLKIN high B8a Th XCKIH XBLTV Burst last XBLAST valid after 6 25 2 8 XCLKIN high Tcyc B8 Tsu XD XCKIH Data XD valid before XCLKIN 15 3 5 high WRITE B7 Th XCKIH XD Data XD valid after XCLKIN high 6 25 2 8 WRITE Tcyc B8 tPAL Tsu XBEV XCKIH Byte Enable XBE 3 0 valid 10 3 5 before XCLKIN high B7 tPAL Th XCKIH XB
2. TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 17 35 TEXAS SPRA540B INSTRUMENTS Page 6 Synario 3 10 Device Utilization Chart Fri Apr 09 15 19 36 1999 xbus860 bls P22V10C Unused Resources Pin Pin Product Flip flop Number Type Terms Type 11 INPUT 12 13 16 21 BIDIR NORMAL 16 D 23 BIDIR NORMAL 16 D 18 TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 35 TEXAS INSTRUMENTS SPRA540B Page 7 Synario 3 10 Device Utilization Chart Fri Apr 09 15 19 30 1999 xbus860 bls P22V10C Fuse Map di SS Sa Sa ex 88 2 Sao 44037 eS 484 X ERER e 024 mee SS eee 968 9 lt 23 Re SSS Se ee I 96 E Se 1540 X X X 96525 te eS Soe 96061 2 lt ee SS SSeS X X uM occ 4356 re 4884 SS Se SSS SSS 4928 SRS XMS SKS te SS SSS SSeS SSS 5368 SSS SSSR URS ee 5808 X X XX XXX X X X TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 19 IMPORTANT NOTICE
3. Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its products to the specifications applicable at the time of sale in accordance with standard warranty Testing and other quality control techniques are utilized to the extent Tl deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using Tl components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination mac
4. 2 8 0 16 5 5 4 5 16 5 Min ns Max ns 3 5 2 8 3 5 2 8 3 5 2 8 5 16 5 5 16 5 5 16 5 5 16 5 0 16 5 5 4 5 16 5 TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface The timing requirements in Table B 1 and Table 2 are provided for quick reference only For detailed description notes and restrictions please see the corresponding Fixed Point Digital Signal Processor data sheet 35 TEXAS INSTRUMENTS SPRA540B Appendix C PAL Equations Page 1 Synario 3 10 Device Utilization Chart Apr 09 15 19 35 1999 xbus860 bls Input files ABEL PLA file xbus860 tt3 Device library P22V10C dev Output files Report file xbus860 rep Programmer load file xbus860 jed TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 13 SPRA540B Page 2 Synario 3 10 Device Utilization Chart Fri Apr 09 15 19 35 1999 xbus860 bls P22V10C Programmed Logic BGn N_7 Q N_3 0 XCSn TSn A2 8 1 amp 0 54D BBn BRn ISTYPE BUFFER t15 C XCLIKIN 1 XHOLDA ISTYPE BUFFER XCLIKIN 3 D 11 0 N 5 0 ISTYPE BUFFER Me XCL BENED N 11 0 amp N_7 Q ISTYPE BUFFER uu XCL 7 0 N 11 0 ISTYPE BUFFER XCL XHOLD IN 15 0 14 TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 35 TEXAS INSTRUMENTS 35 TEXAS INSTRUMENTS SP
5. A 28 0 TSIZE 1 0 and A 31 30 TA 35 TEXAS INSTRUMENTS Table 1 MPC860 to Expansion Bus Pin Connections Comments Address bits of MPC860 are used as control signals A31 is the LSB of the MPC860 address bus Indicates a burst transfer The polarity of XBLAST in this case active high is determined during reset using pull up resistor on XD 13 Indicates a read or write access The polarity of XW R is determined during reset using pull up resistor on XD 12 MPC860 uses D 0 31 for 32 bit port interface DO is the MSB of the MPC860 data bus while XD31 is the MSB of expansion bus Local Expansion bus clock Expansion bus arbitration signals Note that internal expan sion bus Arbiter is enabled Expansion bus arbitration signals Note that internal expan sion bus arbiter is enabled Indicates the beginning of a new transfer The MPC860 address is decoded to generate the XCS signals Byte enables are decoded using TSIZE and A 31 30 SETA bit in the MPC860 option register is set to 1 to indicate that TA is generated externally by expansion bus The internal bus arbiter of the MPC860 is disabled and the internal bus arbiter of the expansion bus is enabled The byte enables signals of the DSP are decoded using the TSIZE 1 0 and the address lines A 31 30 of the MPC860 Conversions are presented in Table 2 Table 2 DSP Byte Enable Conversion Table TSIZE Address A30 01 0 01 0 01 1 01 1 10 0 10 1 00
6. Both devices can operate with the internal bus arbiter enabled or disabled In this interface the internal expansion bus arbiter TMS320C6000 DSP expansion bus handles the bus arbitration The arbiter configuration external or internal for both devices is set at system reset The ERAB bit of the MPC860 must be set to one in the hard reset configuration word sampled by the MPC860 from the data bus during reset external arbitration is assumed The XARB bit of the C6000 DSP must be set to one in the hard reset configuration word sampled by the DSP from the data bus during reset to enable the internal bus arbiter The TMS320C6202 B C6203 C6204 boot configuration is presented in Table 3 Table 3 Expansion Bus Boot Configuration via Pull Up Pull Down Resistors on 0 31 0 Field Description BLPOL Determines polarity of XBLAST signal BLPOL 1 XBLAST is active high RWPOL Determines polarity of expansion bus read write signal RWPOL 1 XR W_ HMOD Host mode status in XB HPIC HMOD 1 external host interface is in synchronous master slave Mode XARB Expansion bus arbiter status in XBGC XARB 1 internal expansion bus arbiter is enabled FMOD FIFO mode status in XBGC LEND Little endian mode LEND 1 system operates in little endian mode BootMode 4 0 Dictates the boot mode of the device including host port boot ROM boot memory map selection For a complete list of boot modes see the TMS320C6000 Peripherals Reference Guide
7. 0 XBE 3 0 A31 0 0111 1 1011 0 1101 1 1110 0 0011 0 1100 0 0000 The MPC860 as well as the expansion bus uses the pull up down resistors on the data bus expansion data bus for boot configuration during hard reset However the MPC860 and the DSP require a different configuration of pull up resistors One way around this is to use a bus switch see Figure 1 The bus switch two 16 bit to 32 bit FET SN74CBT16390 multiplexer demultiplexer bus switches are used separates the DSP and the MPC860 data buses during reset allowing different reset configuration words for each device TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 35 TEXAS INSTRUMENTS SPRA540B Another way to reset the system is to first bring the MPC860 from hard reset pull up pull downs on the XBUS are used to configure the MPC860 during reset The DSP should come out from reset after the MPC860 During reset of the DSP the MPC860 should actively drive values required to configure the DSP on the data bus this way the DSP will be configured The glue logic presented in Figure 1 can not fit in a single PALLV22V10 The PAL equations given in Appendix C describe only the glue required for address decoding and converting the MPC860 bus arbitration signals BR BG and BB to the expansion bus arbitration signals XHOLD and XHOLDA The DSP byte enable conversion table is not implemented in the PAL equations provided in Appendix C 2 Configuration
8. G bit asserted forces the access to stall until either the access is non speculative or is canceled by the core Cacheable and non cacheable regions must be defined and write back or write through mode for the cacheable region of main memory must be selected by initializing the MMU before enabling the data cache Timing Verification To verify proper operation two functions have been examined 1 an MPC860 write to the expansion bus and 2 an MPC860 read from the expansion bus In each instance timing requirements were compared for each of the devices and the results are shown in the following tables and timing diagrams The interface was verified using VHDL simulation Synopsys MPC860 SmartModel was used in the test bench Diagrams presented are outputs from the simulation The clock ratio between the operating frequency of the TMS320C6000 DSP and the XCLKIN frequency was set to 6 2 When the bus clocks speed is faster than 37 MHz the MPC860 timing requirement B16 setup time is violated due to maximum data delay time Td XCKIH XRY of the expansion bus The numbers in Table 4 and Table 5 are based on an 860 local bus is running at 36 MHz Tcyc 28 ns and a TMS320C6000 DSP the TMS320C6202 was used specifically for the simulations presented device operating at any frequency ranging from 100 MHz 250 MHz Note that the expansion bus timing parameters for the TMS320C6202 C6202B C6203 and C6204 are similar for the specific freque
9. SPRU 190 The MPC860 cache must be disabled for the interface to function correctly The data cache may be enabled or disabled through the use of data cache enable and data cache disable written to the CST register In the disabled state the cache tag state bits are ignored and all accesses are propagated to the bus as single beat transactions The default after reset state of the data cache is disabled Disabling the data cache does not affect the data address translation logic and translation is still controlled by the MSRpp bit Any write to the CST register must be preceded by a sync instruction This prevents the data cache from being disabled or enabled in the middle of a data access When the data cache generates an interrupt as a result of the bus error on the copy back or on the implementation specific flush cache line command it enters the disable state Operation of the cache when it is disabled is similar to cache inhibit operation TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 5 6 35 TEXAS SPRA540B INSTRUMENTS Each page can have different storage control attributes The MPC860 supports cache inhibit Cl write through WT and guarded G attributes but not the memory coherence M attribute A page that must be memory coherent must be programmed cache inhibited The G attribute is used to map devices that are sensitive to speculative accesses An attempt to access a page marked guarded
10. to XD invalid Delay time XCLKIN high XD high impedance Delay time XCLKIN high to XRDY valid Symbol Tsu XCSV XCKIH Th XCKIH XCSV Tsu XASV XCKIH Th XCKIH XASV Tsu XCTL XCKIH Th XCKIH XCTL Tsu XWR XCKIH Th XCKIH XWR Tsu XBLTV XCKIH Th XCKIH XBLTV Tsu XBEV XCKIH Th XCKIH XBEV Tsu XD XCKIH Th XCKIH XD Td XCKIH XDLZ Td XCKIH XDV Td XCKIH XDIV Td XCKIH XDHZ Td XCKIH XRY 35 TEXAS INSTRUMENTS Table B 2 TMS320C6202 C6202B C6203 C6204 Timing Parameters TMS320C620x is a Master Characteristic Setup time XD valid before XCLKIN high Hold time XD valid after XCLKIN high Setup time XRDY valid before XCLKIN high Hold time XRDY valid after XCLKIN high Setup time XBOFF valid before XCLKIN high Hold time XBOFF valid after XCLKIN high Delay time XCLKIN high to XAS valid Delay time XCLKIN high to XWR valid Delay time XCLKIN high to XBLAST valid Delay time XCLKIN high to XBE valid Delay time XCLKIN high to XD low impedance Delay time XCLKIN high to XD valid Delay time XCLKIN high to XD invalid Delay time XCLKIN high to XD high impedance Delay time XCLKIN high to XWE XWAIT valid Symbol Tsu XDV XCKIH Th XCKIH XDV Tsu XRY XCKIH Th XCKIH XRY Tsu XBFF XCKIH Th XCKIH XBFF Td XCKIH XAS Td XCKIH XWR Td XCKIH XBLTV Td XCKIH XBEV Td XCKIH XDLZ Td XCKIH XDV Td XCKIH XDIV Td XCKIH XDHZ Td XCKIH XWTV Min ns Max ns 3 5 2 8 3 5 2 8 3 5 2 8 3 5 2 8 3 5 2 8 3 5 2 8 3 5
11. 1 Pg wi 1 a L i bob d E i BG DE H z0 gt opts frets AE qub d te ED E E H 2 de dde ee E Lm Ett ts Eo do 5 N 5 gt 9 o o 8 5852 5555858 5 X IMS VOS pv X oO lo lt E x x o 9 2 a amp EE 5 gt 2 c Figure 2 Burst Read by an External Master MPC860 From Expansion Bus Synchronous Host Port TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 7 8 JOSSEDOIAOIDIF 0982dIA 01 Sng 0009202 SIALL SOH snouo1ugou AS sng uoisuedx3 0982 1995 M 1sung aniy E _ 0007 MEE F RAN Spe ie ae Se aie rn Jxbe XS Es x E xhold c ES a xholda z m 17777 PEPER MEBs xblast ES cR E NE Ixd 25 El X 44444444 ES 55555555 66666666 71777777 X FFFFFFFF lmpc860 a
12. 35 TEXAS Application Report INSTRUMENTS SPRA540B August 2001 TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface Zoran Nikolic DSP Applications ABSTRACT This application report describes how to interface the TMS320C6000 C6000 digital signal processor DSP expansion bus to the Motorola MPC860 microprocessor This document contains e block diagram of the interface and PAL equations e Information required for configuring the MPC680 e Timing diagrams illustrating the interface functionality Note The information presented in this application report has been verified using VHDL simulation Contents List of Figures Figure 1 TMS320C6202 to MPC860 Interface Using the Expansion Figure 2 Burst Read by an External Master MPC860 From Expansion Bus Synchronous POr cet ean veh Figure 3 Burst Write by an External Master MPC860 From Expansion Bus synchronous Host Port List of Tables Table 1 MPC860 to Expansion Bus Pin Connections TMS320C6000 and C6000 are trademarks of Texas Instruments Trademarks are the property of their respective owners MPC860 Interface 2 copie Ic E E PE eee ER PER e ee GONntQUIATION Tuning Verification EU E RUE E RGIGI
13. CNCES Appendix MPC860 Timing Requirements Appendix TMS320C6000 Timing Parameters Appendix PAL Equations ee ee ees 35 TEXAS SPRA540B INSTRUMENTS Table 2 DSP Byte Enable Conversion Table 4 Table Expansion Bus Boot Configuration via Pull Up Pull Down Resistors on 31 0 5 Table 4 Timing Requirements for TMS320C6000 MPC860 Expansion Bus Master 9 Table 5 Timing Requirements for MPC860 MPC860 Expansion Bus Master 9 Table 1 Motorola MPC860 Timing Parameters 11 Table 1 TMS320C6202 C6202B C6204 Timing Parameters External Device is a Master 12 Table 2 TMS320C6202 C6202B C6203 C6204 Timing Parameters 5320 620 is 12 1 MPC860 Interface The MPC860 integrates an embedded PowerPC core with a communications processor module CPM that uses a specialized RISC processor for communications This two processor architecture is more efficient than traditional architectures because the CPM offloads peripheral tasks from the embedded PowerPC core Figure 1 illustrates the interface between the TMS320C6202 in synchronous host port mode and the MPC860 Note that the C6202 internal expansion bus arbiter is enabled Altho
14. EV Byte enable XBE 3 0 valid after 11 25 2 8 XCLKIN high Tcyc B8 Tsu XWR XCKIH Read write XR W valid before 15 3 5 XCLKIN high B7 Th XCKIH XWR Read write XR W valid after 6 25 2 8 XCLKIN high C6000 refers to the C6202 C6202B C6203 and C6204 devices Table 5 Timing Requirements for MPC860 MPC860 Expansion Bus Master MPC860 Symbol C6000 Symbol Parameter MPC860 C6000 Min ns Min ns B16 Teyc Td XCKIH XRY Ready signal XRDY valid 9 75 11 5 before XCLKIN high B17 Td XCKIH XRY Ready signal XRDY valid 1 5 after XCLKIN high B18 Teyc Td XCKIH XDV Data XD valid before 6 11 5 XCLKN high READ B19 Td XCKIH XDIV Data XD invalid after 1 5 XCLKIN high READ refers to the evices TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 9 4 10 35 TEXAS SPRA540B INSTRUMENTS References TMS320C6000 Peripherals Reference Guide SPRU190 TMS320C6202 TMS320C6202B Fixed Point Digital Signal Processors SPRS104 TMS320C6203 TMS320C6203B Fixed Point Digital Signal Processor SPRS086 TMS320C6204 Fixed Point Digital Signal Processor SPRS152 860 User s Manual Motorola Inc gt TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 35 TEXAS SPRA540B Min ns Max ns 13 13 12 25 13 INSTRUMENTS Appendix A MPC860 Timing Requirements Table A 1 Motorola MPC860 Timing Parameters Characteristic Symbol CLKOUT to A 0 31 RD WR D 0 31 BDI
15. P invalid B7 B7a 6 25 CLKOUT to A 0 31 RD WR D 0 31 DP 0 3 BDIP valid B8 B8a 6 25 CLKOUT to A 0 31 RD WR D 0 31 High Z B9 6 25 CLKOUT to TS BB assertion B11 6 25 CLKOUT to TS BB negation B12 6 25 Data DP valid to CLKOUT rising edge setup time B18 6 CLKOUT Rising edge to Data DP valid hold time B19 1 TA valid to CLKOUT setup time B16 9 75 CLKOUT to TA hold time B17 1 The timing requirements in Table A 1 are provided for quick reference only For detailed description notes and restrictions please the MPC860 User s Manual TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 11 SPRA540B 12 Appendix TMS320C6000 Timing Parameters Table B 1 TMS320C6202 C6202B C6204 Timing Parameters External Device is a Master Characteristic Setup time XCS valid before XCLKIN high Hold time XCS valid after XCLKIN high Setup time XAS valid before XCLKIN high Hold time XAS valid after XCLKIN high Setup time XCNTL valid before XCLKIN high Hold time XCNTL valid after XCLKIN high Setup time XWR valid before XCLKIN high Hold time XWR valid after XCLKIN high Setup time XBLAST valid before XCLKIN high Hold time XBLAST valid after XCLKIN high Setup time XBE valid before XCLKIN high Hold time XBE valid after XCLKIN high Setup time XD valid before XCLKIN high Hold time XD valid after XCLKIN high Delay time XCLKIN high to XD low impedance Delay time XCLKIN high to XD valid Delay time XCLKIN high
16. RA540B Page 3 Synario 3 10 Device Utilization Chart Fri Apr 09 15 19 35 1999 xbus860 bls P22V10C Chip Diagram TSn N11 A2 XCSn A1 P22V10C XHOLDA A0 IBGn 15 12 13 14 15 16 17 SIGNATURE N A TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 15 35 TEXAS SPRA540B INSTRUMENTS Page 4 Synario 3 10 Device Utilization Chart Fri Apr 09 15 19 35 1999 xbus860 bls P22V10C Resource Allocations Device Resource Design Resources Available Requirement Unused Input Pins Input 12 8 4 33 5 Output Pins In Out 10 8 Zt ep o Output E 5 Buried Nodes Input Reg Pin Reg 10 5 5 50 Buried Reg 16 TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 35 TEXAS INSTRUMENTS SPRA540B Page 5 Synario 3 10 Device Utilization Chart Apr 09 12 19 36 1999 xbus860 bls P22V10C Product Terms Distribution Signal Pin Terms Terms Terms Name Assigned Used Max Unused SSS SSS SSS SS SS SS SS SS SSS SSS SSS SS SS SSS SSS SSS SESS SSS SSS BGn 20 1 14 13 XCSn 24 ik 14 13 N_15 D 19 1 12 11 N_11 D 25 1 12 11 N_3 D 18 1 10 9 N_5 D 26 1 10 9 N 7 D 17 1 8 7 XHOLD 27 1 8 7 List of Inputs Feedbacks Signal Name Pin Pin Type XCLIKIN 2 CLK IN BBn 3 INPUT BRn 4 INPUT TSn 5 INPUT A2 6 INPUT Al 7 INPUT XHOLDA 9 INPUT AO 10 INPUT
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18. ncy range TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 35 TEXAS a c mM E p OF 1 1 1 vos di zs 1 1 1 lt 1 1 x e gt lt gt a E iC ccm see sies BRE e dea tater de eec eem 5 E 6 D 0 m E 5 3 1 1 5 20 a Rate eae EIL LIT BIA uc loe o 09 d 2 1 1 1 UE A a toh 1 4 41 gt lt 39 2 a 1 i i Q i zE 8 Hdi die ibe 5 4 5 24 8 8 ze i z E 9 1 1 8 52 gt aes teat SS 5 i 3 2 69 gt lt i 1 1 e RAE are ee he foe fee eT DEW ol pan x edere ena e er SS 29 og E i ie 42 47 T9 gt lt to ot 1 S ai Ai qr EA o dee i dictu sur rt duc AK DEDE d 1 i
19. ugh the C6202 is a slave in the following diagram it still has the ability to arbitrate for the bus in order to use the asynchronous port or FIFO interface of the expansion bus If only these two devices share the bus the internal arbiter of the MPC860 can be used Although the C6202 device is used to illustrate the interface the configuration for the C6202B C6203 and C6204 devices should be similar Table 1 lists the MPC860 to expansion bus pin connections 2 TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 35 TEXAS INSTRUMENTS MPC860 CLKOUT TSIZE 1 0 A 31 30 RD WR TS A 0 28 29 BDIP D 0 31 HRESET Optional Reset E 5 lt lt Byte Enable R Conversion Address Decoder 2X SN74CBT16390 32 XBUS Boot Configuration MPC860 Boot Configuration SPRA540B TMS320C6202 XHOLDA XCLKIN XBE 3 0 XW R XAS XCS XCNTL XRDY XBLAST XD 31 0 RESET Figure 1 TMS320C6202 to MPC860 Interface Using the Expansion Bus TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface 3 SPRA540B Expansion Bus Pin MPC860 Pin XCNTL XBLAST XW R XD 31 0 XCLK XHOLD XHOLDA XAS XCS XBE 3 0 XRDY A 29 BDIP RD WR D 0 31 CLKOUT Glue logic is needed to connect to BR BG and BB Glue logic is needed to connect to BR BG and BB TS

"TMS320C6000 Expansion Bus to MPC860

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