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MBX Series Embedded Controller Version C Programmer`s

1. Resource Enabled at eid OR Description FDC Yes PRI 3F0 3F7 Floppy Disk Controller Keyboard Yes COMI 3F8 3FF Serial Port 1 Mouse Yes COM2 2F8 2FF Serial Port 2 Parallel Port Yes LPTI 3BC 3BF Parallel Port KBC Yes 060 064 Keyboard Mouse Controller 1 20 Computer Group Literature Center Web Site I O Device Configuration I O Device Configuration Table 1 12 lists the firmware initialization values in hexadecimal format for configuration type registers of the 37C672 As previously stated these are just the initialization values Operation of specific 37C672 drivers may require additional initialization such as interrupt enabling DMA operations operation modes parameters etc Table 1 12 37C672 I O Device Configuration Index Type a uua Hard Reset Soft Reset m Global Configuration Registers 02 W Configuration Control 00 00 03 R W Index Address 03 N A 07 R W Logical Device Number 00 00 XX 20 R Device Identifier 40 40 21 R Device Revision 01 01 22 R W Power Control 00 00 3F 23 R W Power Management 00 N A 00 24 R W OSC 04 N A 2B R W Test 4 00 N A 2C R W Test 5 00 N A 2D R W Test 1 00 N A 2E R W Test2 00 N A 2F R W Test 3 00 N A Logical Device 0 Configuration Registers FDD 30 R W Activate 00 00 01 60 R W Primary Base I O Address 15 8 03 03 03 61 R W Primary Base I O Address 7 0 FO
2. 1 20 Table 1 12 SPOTS DO Device Configuratio 5 6 dei babet ee DAE e cde e Eme Eque 1 21 Table 1 13 Interrupt Structure ISA and PCI eene 1 24 Table 1 14 Interrupt Structure MPG BXX 2er iee docet rieri 1 25 Table 1 15 Hard Reset Configuration Word Bit Definitions 1 27 Table 2 1 PCMCIA IPA Port Pin Definition vs Function sesss 2 2 Table 2 2 Interrupts Pin Definition vs Function 5 onem 2 3 Table 2 3 IPB Port Pin Definition vs Function esee nene 2 4 Table 2 4 Debug IEEE 1149 Port Pin Definition vs Function 2 5 Table 2 5 Miscellaneous Signals Pin Definition vs Function 2 6 Table 2 6 Peripheral Port A iius rrr tie repe ro gh waren 2 7 Table 2 7 Pernpheri PORE B ounce oiii en bre pte EAERI EEST 2 8 Table 7 8 Penpberal Fon E 2aocase UC E d besote Uie Ete tunbit bat bd eM DM Etpe 2 9 Telle 29 People Pon DC ooo iio cu ise ue ur pit eee MORE UE EE RE EYE 2 11 Table 3 1 Control Register 12 Bit Definitions 2er tte tope eee seno cues 3 2 Table 3 2 Status Register 1 Bit Definitions 1s essent bees ane stsnvehansstacesssoes 3 3 Table 3 3 Control Register 42 Bit Definitions 1e eec tre tne ee ee iens 3 4 Table 3 4 Status Register 82 Bit Debinitlong Lu acsoeocce rrt rre cies 3 5 Table 3 5 2C Address AssIppduente iiis sedes sascevuive redes pb ep Ao x e eps oske 3 7 Ta
3. 324 RTCK Real Time Clock Register Key 55CC AA33 328 RTCECK Real Time Alarm Seconds Key 55CC AA33 32C RTCALK Real Time Alarm Register Key 55CC AA33 Memory Controller In hardware all address decoding originates with the eight chip select banks of the memory controller incorporated into the MPC8xx processor Table 1 3 lists the initial values established by EPPCBug firmware for the memory controller registers Some values are dependent on the state of jumper J4 boot ROM device selection the size of the on board DRAM memory and the size of the optional DIMM memory Underlined values in Table 1 3 identify parameters required by the design of the MBX board they should not be modified Other values are user selectable For additional details about the processor Base and Option registers refer to the MPC821 or MPC860 processor manuals listed in Appendix B Related Documentation http www motorola com computer literature 1 5 MBX Initialization Table 1 3 Memory Controller Register Initial Values Value Offset Mnemonic Name Device 50MHz Notes FEO00 0001 Base Register LE 100 BRO Bank 0 On Board or or 1 Socketed FC00 0401 Flash 104 ORO Option Register FF80 0940 2 Bank 0 108 BRI Base Register XXX0 0081 Bank 1 On board i DRAM 10C ORI Option Register XXX0 0400 Bank 1 Base Register 110 BR2 Bank 2 DIMM XXXO0 0081 DRAM
4. All of them are available on the 8xx COMM expansion connector In addition all other Port C signals except PC15 PC11 and PC10 are routed to the 8xx COMM expansion connector They may be redefined as interrupt lines to the MPC8xx processor core when not in use for another function purpose Each available Port C pin when configured as an interrupt signal has a unique interrupt vector as defined in Table 16 44 Encoding the Interrupt Vector in the MPC860 User s Manual and the PowerPC MPC821 Portable Systems Microprocessor User s Manual Port D Pins Definition vs Function The Port D pins are described in Table 2 9 Port D is a dual purpose port L MPCS8060 Port D is used for SCC3 SCC4 and several user selectable functions All signals except PD 5 3 are routed to the 8xx COMM expansion connector Each of the SCC3 and SCC4 Computer Group Literature Center Web Site Port D Pins Definition vs Function signals listed in Table 2 9 may be redefined as user selectable All of them are available on the 8xx COMM expansion connector m MPC821 All pins are reserved for an LCD interface If no LCD interface is used then the PD 15 3 signals can serve as general purpose I O lines All signals except PD 5 3 are routed to the 8xx COMM expansion connector Table 2 9 Peripheral Port D Function Function On Pin Pin Name on MPC860 on MPC821 Header U17 PD 1
5. 0000 FA20 FFFF 64 KB MPC8xx dual port RAM N A 9 16K internal decode FA21 0000 FA21 FFFF 64 KB PCI bus bridge control status CS6 5 8 registers 4K internal decode FA22 0000 FBFF FFFF 30592 KB Unused 10 1 8 Computer Group Literature Center Web Site Notes for System Address Map Table 1 4 System Memory Map MPU View continued Start End Size Definition CS Notes FC00 0000 FC7F FFFF 1 2 4 8 Flash memory 1 2 4 8 MB CSO 7 13 14 MB 32 bit CS7 15 FC80 0000 FDFF FFFF 24 MB Reserved 10 FE00 0000 FE7F FFFF 8 MB Boot ROM 128 256 512KB CS7 9 3 14 8 bit CSO 15 FE80 0000 FFFF FFFF 24 MB Reserved 10 Notes for System Address Map Entries in the Notes column of Table 1 4 System Memory Map MPU View refer to the items below 1 Depending upon the size of memory installed plugged into the DIMM slot the on board memory may or may not be located at address 0000 0000 If the installed memory is larger than the on board memory then the installed memory should be located at address 0000 0000 When you configure the bank address registers of the MPC8 xx the base address of the bank must be a modulus of the bank size For example if a bank is 32MB it can only be located at addresses 0000 0000 0200 0000 0400 0000 0600 0000 The DIMM is 64 data bits wide but it can be accessed only 32 bits at a time The 32 bit data width is a
6. FO FO 70 R W Primary Interrupt Select 06 06 07 http www motorola com computer literature 1 21 MBX Initialization Table 1 12 37C672 I O Device Configuration continued Index Type s pun T Hard Reset Soft Reset E 74 R W DMA Channel Select 02 02 02 FO R W FDD Mode Register OE N A 06 Fl R W FDD Option Register 00 N A 0C F2 R W FDD Type Register FF N A 55 F4 R W FDDO 00 N A 01 F5 R W FDDI 00 N A 01 Logical Device 1 Configuration Registers Reserved Logical Device 2 Configuration Registers Reserved Logical Device 3 Configuration Registers Parallel Port 30 R W Activate 00 00 01 60 R W Primary Base I O Address 15 8 00 00 03 61 R W Primary Base I O Address 7 0 00 00 BC 70 R W Primary Interrupt Select 00 00 OB 74 R W DMA Channel Select 04 04 04 FO R W Parallel Port Mode Register 1 3C N A 3C F1 R W Parallel Port Mode Register 2 00 N A Logical Device 4 Configuration Registers Serial Port 1 30 R W Activate 00 00 01 60 R W Primary Base I O Address 15 8 00 00 03 61 R W Primary Base I O Address 7 0 00 00 F8 70 R W Primary Interrupt Select 00 00 04 FO R W Serial Port 1 Mode Register 00 N A 00 Logical Device 5 Configuration Registers Serial Port 2 30 R W Activate 00 00 01 60 R W Primary Base I O Address 15 8 00 00 02 1 22 Computer Grou
7. Table 3 3 Control Register 2 Bit Definitions Bit s Mnemonic Definition 0 and 1 VDDSEL 0 1 These two bits define the supply V or Vaa voltage that is presented to the PCMCIA card socket Bit0 Bit1 0 0 Hi Z 0 1 4 5 0V 1 0 43 3V 1 1 Hi Z 2 and 3 VPPSEL 0 1 These two bits define the programming V pp voltage that is presented to the PCMCIA card socket Bit0 Bit1 0 0 Ground 0 1 12 0V if bits O and 1 are 01 or 10 Hi Z if bits O and 1 are 00 or 11 1 0 The value specified by bits 0 and 1 above 1 1 Hi Z 4 BRDFAIL LED 4 orange 0 On fail 1 Off pass 3 4 Computer Group Literature Center Web Site Status Register 2 Table 3 3 Control Register 2 Bit Definitions continued Bit s Mnemonic Definition 5 Battery Low LED 5 yellow 0 On 1 Off 6 Flash LED 6 yellow Programming 0 2 On 1 Off 7 QSPANRST 0 Normal operation QSpan host PCI bridge device not reset 1 Reset QSpan host PCI bridge device PCI bus not reset Notes 1 The functions of LEDs 4 5 and 6 respectively are defined and controlled in software through these registers The mnemonics for bits 4 6 represent the recommended configuration These bits may be used in other applications however 2 Burst accesses to Flash memory are not supported Status Register 2 The first four bits in Status Register 2 bits 0 through 3 are a read back of bits 0 3
8. WP or IOCS16 DREQ W2 IPA3 CD2 UA IPA4 CDI US IPAS BVDI or SPKR DREQ T6 IPA6 BVD2 or STSCHG T3 IPA7 RDY or IRQ R3 WAITA WAIT L4 OP 0 RESET L2 OP 1 PC Card Enable for Control Signal Buffer The PCMCIA signal INPACK is not needed for non DMA type PCMCIA cards in this design To support PCMCIA cards that have DMA capability and use the INPACK pin for the DREQ signal a jumper J11 on the board enables you to connect the INPACK signal to the IPA5 pin For a description of J11 functionality refer to the MBX Series Embedded Controller Version C Installation and Use manual listed under Motorola Computer Group Documents in Appendix B Related Documentation 2 2 Computer Group Literature Center Web Site Interrupt Pins Interrupt Pins The external interrupt pins available on the MPC8xx are defined in Table 2 2 The interrupt signals can be defined as active low or falling edge Table 2 2 Interrupts Pin Definition vs Function Processor Pin Number Pin Name Function V14 8xx_IRQO Power Fail Interrupt U14 8xx_IRQ1 Temperature Interrupt H3 RSV 8xx_IRQ2 8xx_IRQ2 as QSpan Interrupt F2 CR 8xx_IRQ3 8xx_IRQ3 as ISA Bus Interrupt V5 DP1 8xx_IRQ4 DP1 IRQ4 unavailable W4 DP2 8xx_IRQ5 DP2 IRQ5 unavailable G3 FRZ 8xx_IRQ6 8xx_IRQ6 as 8xx COMM Expansion Interrupt W15 8xx_IRQ7 Stop or Abort Interrupt D18 PC14 User sel
9. a common chip select the specified selection is further decoded by the appropriate address lines MBX control and status registers are byte addressed Control Status Register 1 is located at all even addresses FA10 0000 FA1F FFFE Control Status Register 2 is located at all odd addresses FA10 0001 FATF FFFF The MBX is designed to boot from either the on board Flash or the socketed Flash as determined by jumper J4 which variously routes CSO and CS7 to the two devices The actual chip select used is dependent upon the position of jumper J4 The MPC8xx processor always uses CSO as the source to the reset vector By default the on board Flash is on CSO and the socketed Flash is at CS7 After reset CSO is active for the entire memory Software should reconfigure to limit the range of CSO Computer Group Literature Center Web Site ISA Memory Map 14 EPPCBug can be executed from either the on board Flash or the socketed Flash EPPCBug configures the reset Flash device at the lower address and the nonreset Flash device at the higher address Refer to the MBX Series Embedded Controller Version C Installation and Use manual for information about selecting a boot ROM device via jumper J4 15 CS7 can alternatively be used for the 8xx COMM expansion connector P1 if you boot from the 32 bit on board Flash device and the socketed Flash device is removed from XUI 16 PCMCIA decodes are enabled only if a PCMCIA card i
10. addresses FA10 0001 FA1F FFFF Data lines 0 through 7 of the processor data bus connect to the respective registers with data line 0 carrying the most significant bit The following sections define the bits in those registers NVRAM and the control status registers all share chip select signal CS4 PowerPC address line A11 distinguishes NVRAM from the control and status registers Control Register 1 Control Register 1 sets and defines the configuration of the Ethernet Port bits 0 through 5 and the configuration of the on board EIA 232 D serial port transceiver bits 6 and 7 The default setting of this register after reset is 00 Firmware then initializes the register to 90 entry level boards or 92 standard boards The bits are defined in Table 3 2 3 1 Additional Programming Information Table 3 1 Control Register 1 Bit Definitions Bit Mnemonic Definition 0 ETEN 0 Disable Ethernet transceiver Low Power mode 1 Enable Ethernet transceiver 1 ELEN 0 Disable Ethernet transceiver loopback capability 1 Enable Ethernet transceiver internal loopback 2 EAEN 0 Disable 10BaseT TP AUI auto selection feature Port selected via bit 3 1 Enable auto selection of 10BaseT TP or AUI port 3 TPEN This bit is functional only if bit 2 0 0 AUI port is manually selected 1 10BaseT TP port is manually selected 4 FDDIS This bit is functional only if the 10BaseT port is operational Do n
11. in Control Register 2 The last four bits are defined in Table 3 4 Table 3 4 Status Register 2 Bit Definitions Bit s Mnemonic Definition Oand 1 VDDSEL 0 1 These two bits define the supply Vec or Vga voltage that is presented to the PCMCIA card socket Bit0 Bit1 0 0 Hi Z 0 1 4 5 0V 1 0 43 3V 1 1 Hi Z http www motorola com computer literature 3 5 Additional Programming Information Table 3 4 Status Register 2 Bit Definitions continued Bit s Mnemonic 2 and 3 VPPSEL 0 1 Definition These two bits define the programming Vj voltage that is presented to the PCMCIA card socket Bit0 Bit1 0 0 Ground 0 1 12 0V if bits O and 1 are 01 or 10 Hi Z if bits 0 and 1 are 00 or 11 1 0 The voltage as specified by bits 0 and 1 above 1 1 Hi Z 4 BATGD Low battery voltage indication for the on board or external backup battery 0 Battery voltage is low Battery requires replacement 1 Battery is good 5 NVBATGD Low Battery Voltage indication for the on board battery backed SRAM NVRAM 0 Battery voltage is low and NVRAM device should be replaced 1 Battery voltage is good in the NVRAM device 6 RDY BSY Flash programming status bit Valid only with Flash devices that have a dedicated output pin to indicate programming status otherwise read as logical 1 0 On board Flash programming cycle not complete 1 On board
12. limitation of the MPC8xx With this in mind the DIMM can be viewed as two contiguous banks of memory bank 0 and bank 1 The RASO signal is logically connected to the first chip selection and the RAS2 signal is logically connected to the second chip selection When installing DIMM modules ensure that the jumpers 18 9 10 on the MBX Series board are configured to match the size of the DIMM being installed Both the on board DRAM and the DIMM DRAM share utilize the same UPM UPMA http www motorola com computer literature 1 9 MBX Initialization 10 11 12 13 The location of these address spaces is dependent upon the presence of the PCI bus host bridge PCI ISA I O space and PCI ISA memory space are programmable via the PCI bus host bridge device QSpan On entry level boards CS5 and CS6 are available at the 8xx COMM expansion connector P1 as well For details see ZSA Memory Map on page 1 11 The size of these address spaces is queried from the C SROM device The presence of the PCI bus host bridge device is queried from the I C SROM device These address spaces are smaller than the indicated size The actual decode is dependent upon the device Address wrapping may occur Access to any reserved unused address space is undefined with respect to boundaries One cannot assume a behavior predicted or experienced and any outcome is uncertain These address spaces share
13. more information about using the command buffer refer to the EPPCBug Firmware Package User s Manual 0010 4 Amount of NVRAM in bytes allocated to the command buffer 0014 4 Time to delay in milliseconds before EPPCBug begins execution of the commands contained in the command buffer 0018 4 Specifies the address in memory that binary images will be loaded into when using the PL command This affects binary loads only ELF files and S records are loaded into the location s indicated by the file loaded 001C 4 Specifies the offset from the binary load address that execution will start from This affects binary loads only ELF files and S records are loaded into the location s indicated by the file loaded 0020 4 Specifies the address in memory that files will initially be loaded into From this area in memory they will be relocated to the appropriate area in memory for execution 0024 4 These are currently unused but are reserved for future support of an OEM 0028 4 specified startup message 002C 16 Reserved for future use A 2 Computer Group Literature Center Web Site NVRAM Map Table A 1 NVRAM Map continued Size Offset Bytes Description 003C 1 Contains the CLUN and DLUN of the network device which EPPCBug should consider the primary network device There is no distinction 003D 1 f between the primary network device and all
14. pins are defined in Table 2 6 Table 2 6 Peripheral Port A Pin Pin Name Interface Function ede C18 PA 15 RXDI SCCI ETHERNET RXD No D17 PA 14 TXDI SCCI ETHERNET TXD No E17 PA 13 RXD2 SCC2 RXD Yes F17 PA 12 TXD2 SCC2 TXD Yes G16 PA 11 LITXDb User selectable Yes J17 PA 10 LIRXDb User selectable Yes K18 PA 9 LITXDa User selectable Yes L17 PA SYLIRXDa User selectable Yes M19 PA 7DCLKI TINI LIRCLKa BRGOI User selectable Yes M17 PA 6 CLK2 TOUT1 BRGCLK1 SCC1_ETHERNET_TCLK No N18 PA 5 CLK3 TIN2 L 1TCLKa BRGOUT2 User selectable Yes P19 PA 4 CLK4 TOUT4 SCC1_ETHERNET_RCLK No http www motorola com computer literature 2 7 MPC8xx Multiple Function Pins Table 2 6 Peripheral Port A continued Pin Pin Name Interface Function ae P17 PA G CLKS TIN3 BRGOUT3 User selectable Yes R18 PA 2 CLK6 TOUT3 L1RCLKb BRGOUT2 User selectable Yes T19 PA D CLKT TINA BRGO4 User selectable Yes U19 PA O CLKS TOUTAZ LITCLKb User selectable Yes Port B Pins Definition vs Function Port B is a dual purpose port If the MPC8xx parallel port is used the Port B pins function as described in the Alternate Parallel Port column in Table 2 7 If the parallel port is not used then the pins function as described in the Interface Function column in Table 2 7 User selectable pins are routed to the 8xx COMM expansion conne
15. polarities refer to Interrupt Pins on page 2 3 To preserve the energy of the on board battery the battery will not supply the processor keep alive power KAPWR circuits until the board is first placed in service When power is first applied to the MBX the KAPWR supply is generally below a minimum voltage threshold because of the freshness seal on the battery As a result the reset circuitry on the board issues a power on reset POR to the entire board including the registers powered by the KAPWR circuits The POR signal also causes the MPC8xx processor to assert a hardware reset HRESET signal After this initialization the freshness seal is broken and the battery always supplies power to the processor KAPWR circuits when the main power is removed The processor never sees another POR signal unless the battery is removed and the main power disconnected Hardware Reset The hardware reset HRESET signal resets the entire system except the portion of the processor powered by the KAPWR circuits When coming out of a hardware reset the processor samples the data bus for a hard reset configuration word The configuration word is built in part 1 26 Computer Group Literature Center Web Site Software Reset from jumper settings the jumpers should be set before you power up the board The 32 bits that comprise the configuration word are defined in Table 1 15 Table 1 15 Hard Reset Configuration
16. signal on pin 92 which is defined as IRQ12 in the device Pin 92 is then hardwired on the board to ISA interrupt ISA_IRQ12 1 Parallel port interrupt signal on pin 94 which is defined as IRQ11 in the device Pin 94 is then hardwired on the board to ISA interrupt ISA_IRQ7 Table 1 10 37C672 I O Device Interrupt Routing Function Pin Number Signal Name Parens d Keyboard Pin 97 DSR SAI5 ISA_IRQ10 ISA IRQI COM2 Pin 33 SER IRQ ISA IRQ3 ISA IRQ3 COMI Pin 32 PCI CLK ISA IRQ4 ISA_IRQ4 FDC Pin 100 DTR SA14 ISA_TRQ7 ISA_IRQ6 Parallel Port Pin 94 DCD 8042P12 ISA_IRQI1 ISA_IRQ7 Mouse Pin 92 RI 8042P16 ISA_IRQ12 ISA_IRQ12 http www motorola com computer literature 1 19 MBX Initialization I O Device Address Offsets The 37C672 is plug and play PnP compatible The PnP compatibility requires that each of the I O peripherals be located in the ISA address map and that each of these address spaces be enabled To initialize the hardware program each I O peripheral s base address register and enable the address decode for it Device initialization beyond this occurs as needed by the specific device driver This is the same level of initialization that occurs with EPPCBug Table 1 11 lists the I O address offsets into PCI ISA I O space for the different 37C672 entities These address offsets are a result of the firmware initialization Table 1 11 37C672 I O Device Address Offsets
17. 00 0000 0078 0008 1 14 Computer Group Literature Center Web Site QSpan Initialization Values Table 1 8 QSpan Registers Initial Values continued Address Register Description Default Initialization Offset Value Value 404 IDMA_ADD IDMA Address XXXX XXXX Note 1 408 IDMA CNT IDMA Transfer Count OOxx xxxx Note 1 500 CON ADD Configuration Address 0000 0000 Note 2 504 CON DATA Configuration Data 0000 0000 Note 2 508 IACK GEN IACK Cycle Generator Register 0000 0000 600 INT STAT Interrupt Status 0000 0000 EFFO 000F QSpan 1 2 604 INT CTL Interrupt Control 0000 0000 0000 0000 608 INT DIR Interrupt Direction Control 0000 0000 0000 0000 800 MISC CTL Miscellaneous Control and Status 0000 0003 000C 0043 QSpan 1 2 FOO QBSIO_CTL QBus Slave Image 0 Control 0000 0000 0100 0000 F04 QBSIO AT QBus Slave Image 0 Address xxxx 00x0 0000 00D1 Translation F10 OBSII CTL QBus Slave Image 1 Control 0000 0000 0000 0000 F14 OBSII AT QBus Slave Image 1 Address xxxx 00x0 0000 00D1 Translation F80 QB_ERRCS QBus Error Log Control and Status 0000 0000 8100 0000 F84 QB_AERR QBus Address Error Log 0000 0000 F88 QB_DERR QBus Data Error 0000 0000 Notes 1 IDMA not supported 2 Variable depending on PCI peripherals The QSpan PCI Bus Bridge device can act either as master or as slave on the local processor bus as well as on the PCI bus http www motorola c
18. 1 OFAF C404 OFAF C404 OFFF 0404 OFFF 0404 COFF C004 2 OCAF 8C04 OCAF 8C04 OCFFOCOO OCFFOCOO 01FF C004 3 10AF 0C04 00AF 0CO4 13FF 4804 03FF OCOC OFFF C004 4 FOAF 0C00 07AF0C08 FFFF C004 OCFFOC0O 1FFF C004 5 F3BF 4805 OCAFO0COA4 FFFF C005 O3FFOCOC FFFF C004 6 FFFF C005 01AF 0C04 OCFF 0C00 FFFF C005 7 OFAF 0C08 03FF 0COC 8 OCAF 0C04 OCFF 0C00 9 OLAF 0C04 13FF 4804 A OFAF 0C08 FFFF C004 B OCAF 0C04 FFFF C005 C 10AF 0C04 D FOAF C000 E F3BF 4805 F FFFF C005 Computer Group Literature Center Web Site DRAM Configuration Table 1 7 Enhanced UPM A RAM Array for DRAM at 50 MHz Single Read Burst Read Single Write Burst Write Refresh Exception Word Offset 00 Offset 08 Offset 18 Offset 20 Offset 30 Offset 3C 0 CFEF C004 CFEF C004 CFFF 0004 CFFF 0004 FCFF C004 FFFF C007 1 OFAF C404 OFAF C404 OFFF 0404 OFFF 0404 COFF C004 2 OCAF 0C04 OCAF0C04 OCFFOCOO OCFFOC00 OIFF C004 3 30AF 0CO0 O3AFOC08 33FF 4804 03FF OCOC OFFF C004 4 F3BF 4805 OCAFO0CO4 FFFF C005 OCFFOC00 1FFF C004 5 03AF 0C08 03FF OCOC FFFF C004 6 OCAF 0C04 OCFF 0COO FFFF C005 7 03AF 0C08 03FF 0COC 8 OCAF 0C04 OCFF 0C00 9 30AF 0C00 33FF 4804 A F3BF 4805 FFFF C004 B OCAF 0C04 FFFF C005 C D E F http www motorola com computer literature MBX Initialization QSpan Initial
19. 1 or MPC860 processor manuals listed in Appendix B Related Documentation Table 1 2 SIU Registers Initial Values MBX Firmware Internal Register Eni i Register Name Default Initialization Address Mnemonic Value Value 000 SIUMCR SIU Module Configuration Register 006A 2900 0060 2900 004 SYPCR System Protection Control Register FFFF FF88 FFFF FF88 008 SWT Software Watchdog Timer Current Value 00E SWSR Software Service Register 010 SIPEND SIU Interrupt Pending Register 014 SIMASK SIU Interrupt Mask Register 018 SIEL SIU Interrupt Edge Level Mask AAAA 0000 Register 01C SIVEC SIU Interrupt Vector Register 0000 020 TESR Transfer Error Status Register 0001 0000 FFFF FFFF 030 SDCR SDMA Configuration Register 0000 0001 200 TBSCR Timebase Status and Control 0003 00C3 Register 220 RTCSC Real Time Clock Status and Control 00C3 00C3 Register 240 PISCR Periodic Interrupt Status and 0083 0083 Control Register 280 SCCR System Clock Control Register 6200 0000 6200 0000 1 4 Computer Group Literature Center Web Site Memory Controller Table 1 2 SIU Registers Initial Values continued MBX Firmware Internal Register rier ange Register Name Default Initialization Address Mnemonic Value Value 284 PLPRCR PLL Low Power and Reset Control 0000 D000 0000 D000 Register 320 RTCSCK Real Time Clock Status Control 55CC AA33 Register Key
20. 5 LITSYNCa or LD8 User selectable LD8 Yes V19 PD 14 LIRSYNCa or LD7 User selectable LD7 Yes V18 PD 13 LITSYNCb or LD6 User selectable LD6 Yes R16 PD 12 LIRSYNCb or LD5 User selectable LD5 Yes T16 PD 11 RXD3 or LD4 SCC3_RXD LD4 Yes W18 PD 10 TXD3 or LD3 SCC3_TXD LD3 Yes V17 PD 9 RXD4 or LD2 SCC4_RXD LD2 Yes W17 PD 8 TXD4 or LD1 SCC4_TXD LDI Yes T15 PD 7 RTS3 or LDO SCC3_RTS LDO Yes V16 PD 6 RTS4 or LCD AC OE SCC4_RTS LCD_AC OE Yes U15 PD 5 REJECT2 or FRAME VSYNC User selectable FRAME VSYNC Yes U16 PD 4 REJECT3 or LOAD HSYNC User selectable LOAD HSYNC Yes W16 PD 3 REJECT4 or SHIFT CLK Userselectable SHIFT CLK Yes Notes 1 The SCC3 and SCC4 signals are not available on the MPC821 2 LCD signals are not available on the MPC860 http www motorola com computer literature MPC8xx Multiple Function Pins 2 12 Computer Group Literature Center Web Site Additional Programming Information Introduction This chapter describes various control and status registers on the MBX as well as the board s IC address assignments and the DS1621 digital thermometer and thermostat implementation Control and Status Registers The MBX design includes two control and status registers Both registers are byte addressed Control Status Register 1 is located at all even addresses FA10 0000 FA1F FFFE Control Status Register 2 is located at all odd
21. 64 Bootfile name 00B8 64 Argument string 00F8 72 Reserved CRC Calculation Routine There is a two byte checksum field at 0FFE of the EPPCBug NVRAM block If a user application modifies the contents of EPPCBug s NVRAM area it must also update the checksum field to reflect the new checksum otherwise EPPCBug will detect the bad checksum at the next boot and re initialize NVRAM The following algorithm is used to recalculate the checksum unsigned int Srom crc elements p elements n register unsigned char elements p buffer pointer register unsigned int elements n number of elements http www motorola com computer literature A 5 A NVRAM Map and EPPCBug A register unsigned int crc register unsigned int crc_flipped register unsigned char cbyte register unsigned int index dbit msb crc Oxffffffff for index 0 index lt elements n index cbyte elements_ptt for dbit 0 dbit lt 8 dbitt msb crc gt gt 31 amp 1 crc lt lt 1 if msb cbyte amp 1 crc 0x04clldb6 cre 1 cbyte gt gt 1 crc_flipped 0 for index 0 index lt 32 index crc flipped lt lt 1 dbit crc amp 1 crc gt gt 1 crc_flipped dbit A 6 Computer Group Literature Center Web Site CRC Calculation Routine A ere orco flipped Oxfffffffi return crc http www motorola com c
22. 7 MBX Initialization Note that the above is one of many ways to enter Debug mode For further information refer to the appropriate processor manual or to the EPPCBug Firmware Package User s Manual listed in Appendix B Related Documentation 1 28 Computer Group Literature Center Web Site MPC8xx Multiple Function Pins Introduction The MPC821 and MPC860 processors are highly integrated a number of pins serve multiple functions Multi function pins must be programmed in accordance with the requirements of your application This chapter describes how the pins associated with the MPC821 860 processor bus interface and peripheral ports are multiplexed on the MPMC8xx Processor Bus Interface This section describes pins on the MPC8xx bus and control interface that have multiple functions but have dedicated functionality Programmable pins must be set accordingly PCMCIA and or IPA Port Pins The PCMCIA interface signals for slot 1 are routed to the MPC8xx as defined in Table 2 1 The MPC8xx IPA port is used for the PCMCIA slot interface signals The active low signals those with names followed by a pound sign can be defined as signals active on a low logic level or on the falling edge 2 1 MPC8xx Multiple Function Pins Table 2 1 PCMCIA IPA Port Pin Definition vs Function Processor Pin Number Pin Name PCMCIA Function Alternate T5 IPAO VSI T4 IPA1 VS2 U3 IPA2
23. 9 83C554 Interrupt Initialization continued 1 Internally generated by the 83C554 2 Initialize the PIRQ registers with the associated ISA IRQ value 3 The PIRQ values reside in NVRAM These values are used upon a reset condition to initialize the PIRQ registers located within the PCI to ISA bridge This allows for a custom initialization FRI Ro i 3 Contr jo Polarity Interrupt Source Notes 11 IRQ3 INT1 Edge High COM2 Async Serial Port 2 12 IRQ4 Edge High COMI Async Serial Port 1 13 IRQ5 Edge High 14 IRQ6 Edge High Floppy 15 IRQ7 Edge High Parallel Port Notes 37C672 Peripheral I O Device The 37C672 I O device is a collection of industry standard PC I O peripherals e g two UARTS parallel port FDC keyboard mouse controller The 37C672 peripheral I O device register initialization values are subject to change based upon driver and application requirements Required Interrupt Routing The 37C672 device must be programmed to bring out the L1 Floppy Disk Controller FDC interrupt signal on pin 100 which is defined as IRQ7 in the device Pin 100 is then hardwired on the board to ISA interrupt ISA_IRQ6 lL Keyboard interrupt signal on pin 97 which is defined as IRQ10 in the device Pin 97 is then hardwired on the board to ISA interrupt ISA_IRQI Computer Group Literature Center Web Site Required Interrupt Routing 1 Mouse interrupt
24. A 232 transceiver is disabled The C signals should be configured as open drain type outputs If you are using the parallel port functionality of Port B the appropriate parallel port output signals should also be configured as open drain type outputs Port C Pins Definition vs Function Port C pins are described in Table 2 8 Table 2 8 Peripheral Port C Function Function On Pin Pin Name on MPC860 on MPC821 Header D16 PC 15 DREQIU RTS1 L1ST1 SCC1_ETHERNET_TXEN No D18 PC 14 DREQ2 RTS2 L1ST2 SCC2_RTS Yes E18 PC 13 LIRQb L1ST3 User selectable Yes F18 PC 12 LIRQa LIST4 User selectable Yes JI9 PC 11 CTS1 SCCI ETHERNET CLSN No http www motorola com computer literature MPC8xx Multiple Function Pins Table 2 8 Peripheral Port C continued Function Function On Pin Pin Name on MPC860 on MPC821 Header K19 PC 10 CD1 TGATE1 SCC1_ETHERNET_RXEN No L18 PC 9 CTS2 SCC2_CTS Yes M18 PC 8 CD2 TGATE2 SCC2_DCD Yes M16 PC 7 CTS3 LITSYNCb SDACK2 SCC3_CTS User selectable Yes R19 PC 6 CD2 LIRSYNCb SCC3_DCD User selectable Yes T18 PC S CTS4 LITSYNCa SDACK1 SCC4_CTS User selectable Yes T17 PC 4 CD4 LIRSYNCa SCC4_DCD Userselectable Yes Note The SCC3 and SCC4 signals are not available on the MPC821 Each of the SCC2 SCC3 and SCC4 signals listed above can be redefined as user selectable
25. Bank 114 OR2 Option Register 0 XXX0 0400 Bank 2 Base Register 118 BR3 Bank 3 DIMM XXX0 0081 DRAM Bank uc OR3 Option Register 1 XXX0 0400 Bank 3 120 BR4 Base Register NVRAM FA00 0401 Bank 4 board local Option Register control status 124 OR4 Bank 4 register spaces FFEO 0930 3 Base Register 128 BR5 Bank 5 PCI I O 8000 0001 PCI memory 12C OR5 Option Register spaces A000 0008 3 Bank 5 Base Register 130 BR6 Bank 6 PCI Bus FA21 0001 bridge 134 OR6 Option Register registers FFFF 0108 3 Bank 6 Computer Group Literature Center Web Site Memory Controller Table 1 3 Memory Controller Register Initial Values continued s Value Offset Mnemonic Name Device 50MHz Notes FE00 0401 Base Register m 138 BR7 Bank 7 Socketed or or 1 On Board FC00 0001 i Flash 13C OR7 Ppa Reese FF80 0940 2 Bank 7 1880 1000 Machine A no DIMM achine 170 MAMR Mode Register All DRAM 0880 1000 4 DIMM installed Machine B BR oe Mode Register Memory 17A MPTPR Periodic Timer All DRAM 0200 Prescaler Notes 1 EPPCBug configures the reset Flash device at the lower address and the nonreset Flash device at the higher address based on the setting of jumper header J4 boot ROM device selection These initialization values assume 90ns or better access timing These initialization values assume 70ns or better access timing With a DIMM installed the system has three banks of memo
26. ES 3 7 MPU AMR e E ebdt celta cis E E E eee eels 3 8 prd i 0 ET 3 8 DU due Eei p s fT mE 3 9 APPENDIX A NVRAM Map and EPPCBug docu emm A 1 DURS BID EE TA TEI TEA da cec ENEA Crord Pres E ede EE A 2 Primary Network Configuration Parameters i2 eee riter qec tetrum c A 4 CRC Calculation con as ses coca case euroni upizgubsenapte sabia taped Rne tastes dosages A 5 APPENDIX B Related Documentation NIC OU DO TM EE PII rn E anise deitas bises ilis stan lal it Satomi hee asin aes B 1 Minutes DOCE 1e eco RE MEME SESIE DR IN Eas pa bon anu ER Me c betae B 2 Related Spectfi callo diucius retpetvetek RA ORT PUR EVI PUES EQUO eL GR B 3 GLOSSARY viii List of Tables Table 1 1 Processor Core Configuration Initialization esee 1 2 Table 1 3 SIU Registers Uinta Values 1s prie rhet For Rp eire eo eu RSS 1 4 Table 1 3 Memory Controller Register Initial Values eet 1 6 Table 1 4 System Memory Map MPU View sseeseeeeeeemn e 1 8 Table 1 5 ISA Address Map aiias e ERES ERU Ip ESEES ER a 1 11 Table 1 6 UPM A RAM Array for DRAM at 50 MHz eee 1 12 Table 1 7 Enhanced UPM A RAM Array for DRAM at 50 MHz 1 13 Table 1 8 OSpan Registers Initial Vales Laer 1 14 Table 1 9 83554 Interrupt Inmtsl2aU08 25er ineine insa iee 1 17 Table 1 10 37672 VO Device Interrupt Routing ione etd eee dts 1 19 Table 1 11 37072 VO Device Address Oftsets 12e ne et satin toaaeen
27. Endian Modes chapter in the PowerPC MPC821 Portable Systems Microprocessor User s Manual or MPC660 User s Manual for information on big endian small endian and PowerPC little endian byte ordering For information on byte ordering in the PowerSpan PCI interface refer to the PowerSpan PowerPC to PCI Bus Switch Manual listed in the Related Documentation appendix The terms control bit and status bit are used extensively in this document The term control bit describes a bit in a register that can be set and cleared under software control The term true indicates that a bit is in the state that enables the function it controls The term false indicates that the bit is in the state that disables the function it controls The terms 0 and describe the actual value that should be written to a bit or the value that it yields when read The term status bit describes a bit in a register that reflects a specific condition The status bit can be read by software to determine operational or exception conditions Conventions Used in This Manual The following typographical conventions are used in this document bold is used for user input that you type just as it appears it is also used for commands options and arguments to commands and names of programs directories and files italic is used for names of variables to which you assign values for function parameters and for structure names and fields Italic is also used for comments in
28. Ficmwate pecia Up Ain Type Initialization Notes Register Value Mnemonic Value amp 568 DC CST Supervisor 0A00 0000 2 0400 0000 0C00 0000 amp 638 IMMR Supervisor FA20 0000 3 MSR Supervisor 0000 1002 Notes 1 This register is reserved by the firmware 2 Theseries of values shown is written to cause invalidation of the code and data cache 3 The firmware uses this register as a pointer to its internal data structures When system calls are made the programmatic interface function this register must be restored to the same value at the time of client target execution I C SPI Parameter RAM Patch Due to an overlap in the parameter RAM of the MPC8xx processor I C SPI entries must be relocated in order to implement Ethernet SCC1 and I C SPI concurrently Since IDMA1 is not used on the MBX its parameter RAM is reused for relocating the PC EPPCBUG firmware downloads the MPC8xx PC SPI Microcode Package and then relocates the C parameter RAM base to DPRAM_Base 1CCO IDMAI parameter base Information about the microcode patch can be found at http www mot com SPS ADC pps subpgs etoolbox 8X X i2c_spi html http www motorola com computer literature 1 3 MBX Initialization System Interface Unit SIU Registers Table 1 2 lists hardware initialization values used for SIU registers after reset For additional information about the state of the SIU Module Configuration Register SIUMCR after reset refer to the MPC82
29. Flash programming cycle complete Reserved for factory test purposes Computer Group Literature Center Web Site I2C Address Assignments 2 I C Address Assignments The MBX uses four of the 128 possible C connections Table 3 5 lists the address assignments in hexadecimal format for the devices implemented These I C signals are also routed to the 8xx COMM connector Table 3 5 C Address Assignments Device Write Read Address Address A4 A5 Board configuration EEPROM A6 A7 DIMM Serial Presence Detect A2 A3 Reserved A8 A9 Digital Thermometer and Thermostat 90 91 Note The Board Configuration serial EEPROM is partitioned in two halves The first half responds to addresses A4 and A5 the second half responds to addresses A6 and A7 Digital Thermometer Thermostat The MBX provides a DS1621 digital thermometer and thermostat for temperature sensitive applications The DS1621 device supports the PC protocol It can be programmed to assert an interrupt TOUT active on 8xx_IRQ1 when the temperature exceeds a user defined upper limit TH or lower limit TL The interrupt signal remains active until the temperature crosses the other threshold allowing for any amount of hysteresis The DS1621 device is accurate to within 0 5 C from 0 C to 70 C This device is assigned PC address 90 for write operations and address 91 for read operations For additional prog
30. MBX Series Embedded Controller Version C Programmer s Reference Guide MBXCA PG1 December 2001 Edition Copyright 1997 1998 2001 Motorola Inc All rights reserved Printed in the United States of America Motorola and the Motorola logo are registered trademarks of Motorola Inc PowerQUICC is a trademark of Motorola Inc PowerPC is a trademark of International Business Machines Corporation and is used by Motorola with permission QSpan is a trademark of Tundra Semiconductor Corporation PC 104 and PC 104 Plus are trademarks of the PC 104 Consortium IC isa registered trademark of Philips Electronics All other products and or services mentioned in this document may be trademarks or registered trademarks of their respective holders Safety Summary The following general safety precautions must be observed during all phases of operation service and repair of this equipment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment The safety precautions listed below represent warnings of certain dangers of which Motorola is aware You as the user of the product should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment Ground the Instrument To minimize shock hazard the equipment chassis and enclosure must be connected to a
31. NVRAM Map and EPPCBug Table A 1 NVRAM Map continued Size Offset Bytes Description 0F00 254 EPPCBug private NVRAM area The contents of this area are subject to change from release to release OFFE 2 Contains the checksum of the EPPCBug NVRAM block See CRC Calculation Routine on page A 5 for the algorithm to recalculate the checksum 1000 Remainder User definable area of NVRAM Primary Network Configuration Parameters Configuration parameters for the network device designated as primary are stored in NVRAM from 0040 to 013F The following table shows the exact locations of these parameters Table A 2 Primary Network Configuration Parameters Size Offset Bytes Description 0040 4 Magic number 1230 1983 0044 4 Reserved 0048 4 Reserved 004C 4 Reserved 0050 4 Reserved 0054 4 Reserved 0058 4 Reserved 005C 4 Reserved 0060 4 Client i e EPPCBug IP address 0064 4 Server i e host IP address A 4 Computer Group Literature Center Web Site CRC Calculation Routine Table A 2 Primary Network Configuration Parameters Size Offset Bytes Description 0068 4 Subnet mask 006C 4 Broadcast IP address 0070 4 Gateway IP address 0074 1 Maximum BOOTP RARP retries 0075 1 Maximum TFTP ARP retries 0076 1 Reserved 0077 1 Reserved 0078
32. Q5 3 ISA_IRQ6 Floppy Disk F ISA_IRQ7 Parallel Port ISA IRQS i ISA_IRQ9 ISA_IRQIO PCI INTA IDE s s gt ISA IRQ11 PCIINTB S ai ISA_IRQ12 Mouse F 5 s oZ ISA IRQI13 F Sle ISA_IRQ14 PCI INTC S E ISA IRQI5 PCIINTD S ISA_IROA S T ISA_IRQB S d ISA IRQC S 9 ISA_IRQD S Y 1 24 Computer Group Literature Center Web Site Interrupt Routing Table 1 14 Interrupt Structure MPC8 xx Interrupt Source ForS m 8xx IRQO Power Fail F LEVELO S 8xx IRQI Temperature High Low F LEVELI S 8xx_IRQ2 QSpan F LEVEL2 S 8xx_IRQ3 ISA CNTLR 1 F LEVEL3 S E 8xx IRQ4 Unavailable 8 LEVEL4 S 8 Sxx IRQS Unavailable z LEVELS S f 8xx IRQ6 COMMINT L F LEVEL6 S 8xx_IRQ7 Stop Abort F LEVEL7 S NMI Watchdog Timer or IRQ F DEC Decrementer F SIU DEC TB PIT RTC PCMCIA S CPM Port C Pins Timers SCCs SMCs S m SPI PC PIP DMA http www motorola com computer literature 1 25 MBX Initialization Resets Notes 1 S Software configurable 2 F Fixed hardware connection 3 TB PIT RTC PIP PCMCIA and CPM IRQ Controller are all software configurable to any LEVELx Watchdog Timer is configurable to generate NMI or HRESET 5 PCI interrupts and IDE interrupt are routable to any ISA interrupt except 0 1 2 8 or 13 Default maps are A 10 B 11 C 14 D 15 6 For
33. Version 1 1 For information visit the EBX Form Factor Overview available at the Motorola Computer Group Web site Publication Number The following IEEE specifications are available from Web http www ieee org Institute of Electrical and Electronics Engineers Inc Customer Service Department 445 Hoes Lane P O Box 1331 Piscataway NJ 08855 1331 Telephone 732 981 0060 PCI Special Interest Group 2575 NE Kathryn St 17 Hillsboro OR 97124 Telephone 1 800 433 5177 or 503 693 6232 FAX 503 693 8344 Web http www pcisig com IEEE Common Mezzanine Card Specification CMC P1386 Draft 2 0 IEEE PCI Mezzanine Card Specification PMC P1386 1 Draft 2 0 IEEE P996 1 Standard for Compact Embedded PC Modules IEEE P996 1 Bidirectional Parallel Port Interface Specification IEEE Standard 1284 IEEE Standard for Local Area Networks Carrier Sense Multiple IEEE 802 3 Access with Collision Detection CSMA CD Access Method and Physical Layer Specifications Peripheral Component Interconnect PCI Local Bus Specification PCI Local Bus Revision 2 2 Specification http www motorola com computer literature Related Documentation Table B 3 Related Specifications continued Document Title and Source PC Card Standard PCMCIA 2635 N First Street San Jose CA 95134 Telephone 408 433 2273 FAX 408 433 9558 E mail office pcmcia org Web http www pc card com Pub
34. Word Bit Definitions Bits Definition 0 15 J100 0JO1 0110 JOOO where J represents a jumper setting 16 31 0000 0000 0000 0000 reserved and must be zero Notes 1 The jumper for bit position 0 J6 specifies internal or external arbitration 2 The jumper for bit position 5 J4 specifies a boot port size of 8 bits or 32 bits 3 Thejumper for bit position 12 J5 defines whether the DEBUG signals or the IEEE 1149 signals are active on the multiplexed DEBUG IEEE1149 processor pins The reset vector for the MPC8xx is set to 0000 0100 IP 1 MSRIP 0 5 The Initial IMMR value is FF00 0000 The CLKOUT frequency is divided by 1 EBDF 00 The Power Monitor circuit monitors both 3 3V and 5V At power up it pulls HRESET low until 350ms after both voltages reach their proper operating levels HRESET is kept low asserted for as long as either 3 3V or 5V is out of tolerance When the processor detects an HRESET signal it also drives SRESET low Software Reset The software reset SRESET signal is for use with an emulator or debugger in development applications SRESET is present at pin 2 of the MBX Debug connector J24 it is routed to the MPC8xx SRESET pin To enter Debug mode SRESET can be cleared to 0 while DSCK pin 8 on the Debug connector is set to 1 DSCK should remain set to 1 after negation of SRESET to enable the Debug mode immediately http www motorola com computer literature 1 2
35. alization Memory maps and guidelines for initialization of the board L Chapter 2 MPC8xx Multiple Function Pins An examination of the multiple function pins on the MPC821 and MPC860 processors 1 Chapter 3 Additional Programming Information A description of various control and status registers on the MBX embedded controller as well as the board s C devices L Appendix A NVRAM Map and EPPCBug A discussion of stored data items that are pertinent to board configuration and operation Q Appendix B Related Documentation A listing of other publications that may be helpful in using the MBX board Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation We want to know what you think about our manuals and how we can make them better Mail comments to Motorola Computer Group Reader Comments DW164 2900 S Diablo Way Tempe Arizona 85282 You can also submit comments to the following e mail address reader comments mcg mot com In all your correspondence please list your name position and company Be sure to include the title and part number of the manual and tell how you used it Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements Terminology Throughout this manual a convention is used which precedes data and address parameters by a character identifying the numeric format as follows dollar specifies a hexade
36. battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du m me type ou d un type quivalent recommand par le constructeur Mettre au rebut les batteries usag es conform ment aux instructions du fabricant Explosionsgefahr bei unsachgem Dem Austausch der Batterie Ersatz nur durch denselben oder einen vom Hersteller empfohlenen Typ Entsorgung gebrauchter Batterien nach Angaben des Herstellers CE Notice European Community Motorola Computer Group products with the CE marking comply with the EMC Directive 89 336 EEC Compliance with this directive implies conformity to the following European Norms EN55022 Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment this product is tested to Equipment Class B EN55024 Information technology equipment Immunity characteristics Limits and methods of measurement Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will maintain the required EMC safety performance In accordance with European Community directives a Declaration of Conformity has been ma
37. ble A 1 NVRAM Map erect arp erp ncn ncn FRE EAR VETRE URGE FERMER ER A 2 Table A 2 Primary Network Configuration Parameters eese A 4 Table B 1 Motorola Computer Group Documents eee B 1 Table B 2 Manulactureis DOCUDIOHIS 5 port e ciotesooustnndonaseanntuetaauvestalcaees B 2 Table B 3 Related SpectDesD BI iae es ciue ue vL ERU UE Ie S aon rears B 3 ix About This Book The MBX Series Embedded Controller Version C Programmer s Reference Guide provides board level information complete memory maps and detailed chip information including register bit descriptions for the MBX family of embedded controller boards It is intended for use as a companion to the MBX Series Embedded Controller Version C Installation and Use manual listed under Motorola Computer Group Documents in Appendix B Related Documentation This manual is intended for anyone who wants to program these boards in order to design OEM systems add capability to an existing compatible system or work in a lab environment for experimental purposes A knowledge of computers and digital logic is assumed The information in this manual applies to MBX version C models in both entry level and standard configurations The following table lists the specific MBX models documented in this manual Model Number Description Entry Level MBX821 001C 50 MHz MPC821 processor 4AMB DRAM 2MB Flash 10BaseT Ethernet 32KB NVRAM COMM inter
38. cimal value 9b percent specifies a binary number amp ampersand specifies a decimal number For example amp 12 is the decimal number twelve and 12 is the hexadecimal equivalent of the decimal number eighteen xiii Unless otherwise specified all address references are in hexadecimal format A pound sign or underscore L _L following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low A pound sign or underscore L _L following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transitions In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent Data and address sizes for MPC8xx chips are defined as follows L A byte is eight bits numbered 0 through 7 with bit 0 being the most significant L A half word is 16 bits numbered 0 through 15 with bit 0 being the most significant L A word or single word is 32 bits numbered 0 through 31 with bit 0 being the most significant L A double word is 64 bits numbered 0 through 63 with bit 0 being the most significant Refer to the
39. ction for resetting the MBX When pulled to ground this line produces an HRESET signal on the board The switched Reset signal is pulled up to 3 3V via a 40KQ resistor The Reset signal is debounced and filtered it provides an active pulse at least 350msec in duration once the Reset switch has been pressed and released 6 An active low switch connection for stopping or aborting processes running on the MPC8xx This signal is pulled up and filtered via an RC network The pullup is 4 7KQ If possible 3 8 Computer Group Literature Center Web Site Utility Connector 2 aborts should be initiated before board resets so that all processes running can be shut down in an orderly fashion 7 Four status lines relating to board activity Battery_Low Flash_Programming MBX_Bus_Activities and PCI_Bus_Activities The status lines are provided for use with an LED interface 8 3V 5V GND 5V 12V are provided as reference voltages These are outputs but hey should only be used in low power applications Utility Connector 2 A 16 pin dual row header referred to as Utility Connector 2 J19 collects a number of MBX I O signals for use with an external user supplied expansion board if necessary in a given application This utility connector is only available on standard board configurations Utility Connector 2 is present on standard versions of the board only It provides a connection point for the following func
40. ctor Table 2 7 Peripheral Port B Interface Alternate On Pin Pin Name Function Parallel Port Header C17 PB 31 SPISEL REJECT1 User selectable BUSY Yes C19 PB 30 SPICLK User selectable SELECTOUT Yes E16 PB 29 SPIMOSI User selectable PE or PERROR Yes D19 PB 28 SPIMISO User selectable FAULT or ERROR Yes E19 PB 27 I2CSDA BRGO1 DC SDA Yes F19 PB26 DCSCL BRGO2 I2C SCL Yes J16 PB 25 SMTXD1 SMC1_TXD Yes J18 PB24 SMRXDI SMCI RXD Yes K17 PB 23 SMSYN1 SDACK1 User selectable DO Yes L19 PB 22 SMSYN2 SDACK2 User selectable DI Yes K16 PB 21 SMTXD2 LICLKOb User selectable D2 Yes 2 8 Computer Group Literature Center Web Site Port C Pins Definition vs Function Table 2 7 Peripheral Port B continued Interface Alternate On Pin Pin Name Function Parallel Port Header L16 PB 20 SMRXD2 LICLKOa User selectable D3 Yes N19 PB 19 RTSI LIST1 User selectable D4 No N17 PB 18 RTS2 L1ST2 User selectable D5 No P18 PB 17 LIRQb L1ST3 User selectable D6 No N16 PB 16 L1RQa LIST4 User selectable D7 No R17 PB 15 BRGO3 User selectable STROBE_OUT No U18 PB 14 RSTRT1 User selectable STROBE_IN No The PB 25 and PB 24 signals are also routed to the 8xx COMM expansion connector and are available for general purpose user selectable use if the on board EI
41. de and is available on request Please contact your sales representative Notice While reasonable efforts have been made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to the Motorola Computer Group Web site The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to rest
42. defined in Table 2 3 Table 2 3 IPB Port Pin Definition vs Function Processor Pin Number Pin Name Function H2 IPBO IWPO VFLSO VFLSO Debug Port J3 IPB1 IWPI VFLS1 VFLS1 Debug Port J2 IPB2 IOIS16B AT2 AT2 Unused Gl IPB3 IWP2 VF2 VF2 No connection on board G2 IPB4 IWPO VFO VFO No connection on board J4 IPB5 IWPI VFI VF1 No connection on board K3 IPB6 DSDI ATO ATO Unused HI IPB7 PTR AT3 AT3 Unused Computer Group Literature Center Web Site Debug IEEE 1149 Port Pins Debug IEEE 1149 Port Pins The MPC8xx Debug and or Test Port pins are defined in Table 2 4 Table 2 4 Debug IEEE 1149 Port Pin Definition vs Function Processor Pin Number Pin Name Function H16 TCK DSCK If J5 1 2 then TCK If J5 2 3 then DSCK H17 TDI DSDI If J5 1 2 then TDI If J5 2 3 then DSDI G17 TDO DSDO If J5 1 2 then TDO If J5 2 3 then DSDO Note Leaving J5 empty has the same effect as placing the jumper on pins 2 3 it enables Debug functionality at the Debug header on the board Miscellaneous Pins A number of miscellaneous MPC8xx signals not covered in previous sections are defined in Table 2 5 The active low signals those with names followed by a pound sign can be defined as signals active on a low logic level or on the falling edge http www motorola com computer literature 2 5 MPC8xx Multiple Function P
43. e Multiple Access with Collision Detection CSMA CD Access Method and Physical Layer Specifications Global Engineering Documents Suite 400 1991 M Street NW Washington DC 20036 Telephone 1 800 854 7179 or 303 397 7956 Web http global ihs com This document can also be obtained through the national standards body of member countries Interface Between Data Terminal Equipment and Data Circuit ANSI EIA 232 D Terminating Equipment Employing Serial Binary Data Interchange Standard EIA 232 D Electronic Industries Association Engineering Department 2001 Eye Street N W Washington D C 20006 http www motorola com computer literature B 5 Related Documentation B 6 Computer Group Literature Center Web Site Glossary ACK Acknowledgement signal ANSI American National Standards Institute BBRAM Battery Backed up RAM BDM Background Debug Mode Big Endian Byte ordering method in memory whereby bytes are ordered 0 1 2 3 left to right with 0 being the most significant byte See also Little Endian CPM Communication Processor Module CPU Central Processor Unit DMA Direct Memory Access DRAM Dynamic Random Access Memory ECC Error Checking and Correction GL 1 lt DrPnnorga Glossary EEPROM Electrically Erasable PROM EIA Electronic Industries Association EMI Electromagnetic Interference ESD Electrostatic Discharge HDLC High l
44. e disabled 1 Auto selection of 10BaseT TP or AUI port enabled 3 TPEN This bit is valid only if bit 2 0 0 AUI port is manually selected 1 10BaseT TP port is manually selected 4 FDDIS This bit is valid only if the 10BaseT port is operational 0 Full Duplex mode of operation on 10BaseT port enabled 1 Full Duplex mode of operation on 10BaseT port disabled 5 FCTEN 0 Forced Collision Testing on TP enabled 1 Collision Testing on transceiver disabled 6 COMIEN 0 SMCI communication signals routed to the EIA 232 transceiver COMI communication signals routed to the EIA 232 transceiver 7 XCVRDIS Set to 1 this bit indicates that SMC1 can be utilized at the Sx COMM interface 0 On board EIA 232 transceiver enabled 1 On board EIA 232 transceiver disabled and in Low Power mode all transceiver outputs are tri stated http www motorola com computer literature Additional Programming Information Control Register 2 The first four bits in Control Register 2 bits 0 through 3 set and define the voltage requirements of the PCMCIA card that plugs into the on board PCMCIA socket Bits 4 through 6 control status LEDs 4 through 6 When Bit 7 is set the processor has the ability to reset the PCI interface After reset the default setting of this register is 00 If the board passes startup diagnostics and a PCMCIA card is not installed the register is initialized by firmware to 0E The bits are defined in Table 3 3
45. ectable E18 PC13 User selectable F18 PC12 User selectable L18 PC9 User selectable M18 PC8 User selectable M16 PC7 User selectable R19 PC6 User selectable T18 PC5 User selectable T17 PC4 User selectable External interrupt lines 4 and 5 are not available as interrupt lines see Miscellaneous Pins on page 2 5 All external interrupts feeding the external interrupt pins of the MPC8xx are active low in polarity The 8xx_IRQ1 interrupt temperature interrupt polarity is programmed in the http www motorola com computer literature MPC8xx Multiple Function Pins digital thermometer and thermostat DS 1621S device itself depending on whether the interrupt is desired on a high temperature limit or a low temperature limit The MPC8xx allows for both level detection or edge detection For more information refer to the EPPCBug Firmware Package User s Manual The Port C pins identified above can be redefined as interrupt lines to the MPC8x processor core when not used for another function purpose Each available Port C pin when configured as an interrupt signal has a unique interrupt vector as defined in Table 16 44 Encoding the Interrupt Vector in the MPC860 User s Manual and PowerPC MPC821 Portable Systems Microprocessor User s Manual Making use of these pins involves trade offs with the other functionality they provide See Port C Pins Definition vs Function on page 2 9 IPB Port Pins The MPC8xx IPB 0 7 signals are
46. en to mappa e Rr REY neds Rabip Ran pAdER bases inseg Mave Mrd 1 20 VO Dei Ql OPE de P co ERR 1 21 BISHEBDE RK ONE ipiri pannin vans ud epi qd coins dit P SHE RUN n uiri id lg s Nips 1 24 i d 1 26 place ate RESSE adea euet NpUOR R IM KUM C AR 1 26 vui gll FC 1 27 CHAPTER2 MPC8xx Multiple Function Pins liuc or uU sis eatdomnpieies diana EEE 2 1 Processor Pus nieri dce e 2 1 PCMCIA andor IPA Fort PINS sais scvicss sunteisnsessecssuvccapelensoedzaebeenmearavvyiowislacship bie 2 1 rice lui d M 2 3 IPB POr Pini qe 2 4 vii Debus IBEE 1149 Pott PINS i55 ron re eerte edi tv ect rs eria betes 2 5 Dose ione oue DS os eH RUD NDS SENS NEP x uA dE 2 5 Iur DO DOS ende HR ERREUR RR 2 7 Port A Pins Definition vs PUicllOn cia casciccsancassocesnoinsaves EPPHODRSI VENDESI Spb A AE 2 7 Port B Pins Definition Vs FUNGUO ais eas Er RRIR S PARUNIN EEAEK PER UU SFERRRAE RE 2 8 Port Pins Definition vs PUDCTON iiec pip br II EEUU PARINDIE CE DUREE p 0E 2 9 Port D Ping Dennen Vs PUDBQOB usce deterior Rr PERRA 2 10 CHAPTER 3 Additional Programming Information Ipsis E 3 1 Control and Stats BOPISIGIS 1e riedeldecito ribs eie pde Edd DEUS Bb Ce Hber Di Mae rius 3 1 dac d ug cw dae E 3 1 epis itn MP MM E Ek 3 3 Cont BIDS iui dia deti al eles alana peste 3 4 SOS c irj jT 3 5 LCE unc P caduca ep T 3 7 Digital Fheranosmeterm Tete bab i e ener ER PDIpRIPREPI kipi REIHE pe LASS ENSER
47. er for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail Idcformotorola hibbertco com Web http www mot com SPS RISC netcomm W83C554 Enhanced System I O Controller with PCI Arbiter PIB W83C554 Winbond Electronics Corporation America Headquarters 2727 North First Street San Jose CA 95134 Telephone 1 800 677 0769 or 408 943 6666 FAX 408 544 1789 Web http www winbond com tw Peripheral I O Controller FDC37C67X Standard Microsystems Corporation 80 Arkay Drive P O Box 18047 Hauppage NY 11788 Telephone 1 800 443 SEMI or 631 435 6000 Web http www smsc com QSpan User s Manual CA91C860 50 Tundra Semiconductor Corporation 603 March Road Kanata Ontario Canada K2K 2M5 Telephone 1 800 267 7231 or 613 592 0714 FAX 613 592 1320 or Tundra Semiconductor Corporation 39 Darling Avenue Portland ME 04106 Telephone 207 773 2662 FAX 207 773 1550 Web http www tundra com B 2 Computer Group Literature Center Web Site Related Specifications Related Specifications The related specifications listed in the following table are a source of additional information As a further aid sources for the listed documents are also supplied Please note that while these sources have been verified the information is subject to change without notice Table B 3 Related Specifications Document Title and Source EBX Specification
48. evel Data Link Control Hz Hertz IEEE Institute of Electrical and Electronics Engineers c Inter IC I O Input Output JTAG Joint Test Action Group Kb Kilobit 1024 bits KB Kilobyte 1024 bytes GL 2 Computer Group Literature Center Web Site LAN Local Area Network Mb Megabit 1024 Kb MB Megabyte 1024 KB Mbps Megabits per second MHz Megahertz msec Millisecond NVRAM Non Volatile RAM PCI Peripheral Component Interconnect PLL Phase Lock Loop RAM Random Access Memory ROM Read Only Memory RTC Real Time Clock http www motorola com computer literature GL 3 I o0o00o0r o lt DrPnnorga Glossary SCC Serial Communication Controller SDRAM Synchronous DRAM SRAM Static RAM UPM User Programmable Machine in the MPC8xx processor VME VersaModule Eurocard VMEbus VPD Vital Product Data WAN Wide Area Network GL 4 Computer Group Literature Center Web Site Index A assertion defined xiv B base registers configuration 1 5 binary number symbol for xiii boot vectors configuring addresses for 1 10 byte defined xiv C checksum calculation EPPCBug A 5 chip selects configuration 1 5 comments sending xiii configuration base and option registers 1 5 boot vectors 1 10 chip selects 1 5 control status registers 1 10 DRAM 1 12 Ethernet port 3 1 primary network device A 4 serial port 3 1 control bit defined xiv co
49. face connector MBX860 001C 50 MHz MPC860 processor 4MB DRAM 2MB Flash 10BaseT Ethernet 32KB NVRAM COMM interface connector Standard MBX821 models include 50 MHz MPC821 processor PC 104 Plus 10BaseT Ethernet EIDE and Floppy interfaces 32KB NVRAM keyboard mouse IR COMI and COM2 ports LCD panel connector MBX821 002C 4MB DRAM 4MB Flash MBX821 004C 16MB DRAM 4MB Flash MBX821 006C 16MB DRAM 8MB Flash xi Model Number Description MBX860 models include 50 MHz MPC860 processor PC 104 Plus 10BaseT Ethernet EIDE and Floppy interfaces 32KB NVRAM keyboard mouse IR COM1 and COMZ ports COMM interface connector MBX860 002C 4MB DRAM 4MB Flash MBX860 004C 16MB DRAM 4MB Flash MBX860 006C 16MB DRAM 8MB Flash For programming reference information about other versions of the MBX821 or MBX800 refer to the documentation that covers your model For MBX Model Numbers Referto MBX821 00x MBX860 00x MBX Series Embedded Controller Programmer s Reference Guide MBXA PG1 MBX821 00xA MBX860 00xA MBX Series Embedded Controller Programmer s Reference Guide MBXA PG1 and MBX Series version A customer letter MBXA LT1 MBX860 00xB MBX Series Embedded Controller Version B Programmer s Reference Guide MBXA PG3 Overview of Contents This manual is divided into the chapters and appendices listed below L Chapter 1 MBX Initi
50. ins Table 2 5 Miscellaneous Signals Pin Definition vs Function Processor Pin Number Pin Name Function D2 BDIP GPLB5 BDIP Kl KR RETRY 8xx_IRQ4 SPKROUT RETRY H3 RSV 8xx_IRQ2 8xx_IRQ2 F2 CR 8xx_IRQ3 8xx_IRQ3 V3 DP0 8xx IRQ3 DPO V5 DP1 8xx_IRQ4 DPI WA DP2 8xx IRQ5 DP2 V4 DP3 8xx_IRQ6 DP3 G3 FRZ 8xx_IRQ6 8xx_IRQ6 D5 CS6 CE1B CS6 C4 CS7 CE2B CS7 D7 GPLAO GPLBO DRAM Output Enable C6 GPLA1 GPLB 1 General Output Enable B6 GPLA2 GPLB2 Unused and unconnected C5 GPLA3 GPLB3 DRAM Buffer Output Enable Cl UPWAITA GPLA4 Unused and unconnected Bl UPWAITB GPLB4 Unused and unconnected D3 GPLA5 GPLB5 DRAM Row Column Selector Ji ALEB DSCK ATI AT1 unused L1 OP2 MODCK1 STS MODCK1 M4 OP3 MODCK2 DSDO MODCK2 M3 BADDR30 REG Unused and unconnected 2 6 Computer Group Literature Center Web Site Processor I O Ports Processor I O Ports MPC8xx I O Ports A B C and D have multiple functions but dedicated functionality In the following tables User selectable means that any of the signals listed under Pin Name are available for use Wherever applicable the port pins must be programmed according to the tables below Port A Pins Definition vs Function The following tables list the pin assignments of the MPC8xx I O ports with respect to the processor pin name and the associated interface function Port A
51. itialization 1 1 interface unit SIU registers 1 4 T terminology xiii thermometer thermostat digital 3 7 true defined xiv typeface meaning of xv U underscore L _L defined xiv W word defined xiv http www mcg mot com literature IN 3 lt moz
52. ization Values The QSpan R W registers are initialized by firmware to the values listed in Table 1 8 Read only registers are left blank Table 1 8 QSpan Registers Initial Values Address Register Description Default Initialization Offset Value Value 000 PCI ID PCI Configuration Space ID 0860 10E3 004 PCI CS PCI Configuration Space Control 0280 0000 FBOO 0147 and Status 008 PCI CLASS PCI Configuration Class 0680 0000 00C PCI MISCO PCI Configuration Miscellaneous 0 0000 0000 0000 0000 010 PCI BSM AEG Base Address oox x000 0100 0000 014 PCI_BSIO PCI Configuration Base Address xxxx x001 1FFF F001 for I O 02C PCI_SID PCI Configuration Subsystem ID XXXX XXXX 030 PCI_BSROM PCI Configuration Expansion ROM 0000 0000 0000 0000 Base Address 03C PCI_MISC1 PCI Configuration Miscellaneous 1 0000 0100 0000 0100 100 PBTIO_CTL PCI Bus Target Image 0 Control 0000 0000 8F80 0080 QSpan 1 2 104 PBTIO_ADD PCI Bus Target Image 0 Address XXXX XXXX 8000 0000 110 PBTII CTL PCI Bus Target Image 1 Control 0000 0000 0000 0000 114 PBTII ADD PCI Bus Target Image 1 Address XXXX XXXX 0000 0000 13C PBROM CTL PCI Bus Expansion ROM Control 0000 0000 0000 0000 140 PB ERRCS PCI Bus Error Control and Status 0000 0070 8000 0000 144 PB AERR PCI Bus Address Error Log 0000 0000 148 PB DERR PCI Bus Data Error Log 0000 0000 400 IDMA CS IDMA Control and Status 00
53. le configuration For further details on board initialization you may also wish to review the MBX Version C Installation and Use manual or the EPPCBug Firmware Package User s Manual listed in Appendix B Related Documentation 1 1 MBX Initialization PowerPC Core Within the processor chip is a module the core that embodies the PowerPC architecture within the MPC8xx Table 1 1 lists the firmware initialization values for the principal control registers located within the core Core registers not listed in the table either have indeterminate values or use the processor default values For more information refer to the MPC821 or MPC860 processor manuals listed in Appendix B Related Documentation Table 1 1 Processor Core Configuration Initialization Special Purpose Register armare p vidis p 8 i Type Initialization Notes Register Value Mnemonic Value amp 22 DEC Supervisor FFFF FFFF amp 148 ICR Debug 0000 0000 amp 149 DER Debug 0000 0000 amp 158 ICTRL Debug 0000 0000 amp 275 SPRG3 Supervisor Reserved 1 amp 284 TB Write Supervisor 0000 0000 amp 285 TBU Write Supervisor 0000 0000 amp 560 IC_CST Supervisor 0A00 0000 2 0400 0000 0C00 0000 0200 0000 1 2 Computer Group Literature Center Web Site I2C SPI Parameter RAM Patch Table 1 1 Processor Core Configuration Initialization continued Special Purpose Register
54. lication Number PCMCIA JEIDA PowerPC Microprocessor Common Hardware Reference Platform A System Architecture CHRP Version 1 0 Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbertco com Web http www mot com SPS RISC netcomm TB338 D The above specification is also available from IBM 1580 Route 52 Bldg 504 Hopewell Junction NY 12533 6531 Telephone 1 800 PowerPC 1 800 769 3772 MPRP CHRP 01 And from Morgan Kaufmann Publishers Inc 340 Pine Street Sixth Floor San Francisco CA 94104 3205 USA Telephone 415 392 2665 FAX 415 982 2665 ISBN 1 55860 394 8 PC 104 and PC 104 Plus Specifications PC 104 Consortium P O Box 4303 Mountain View CA 94040 Telephone 415 903 8304 FAX 415 967 0995 PC 104 PC 104 Plus PowerPC Reference Platform PRP Specification Third Edition Version 1 0 Volumes I and II International Business Machines Corporation Power Personal Systems Architecture 11400 Burnet Rd Austin TX 78758 3493 Telephone 1 800 PowerPC 1 800 769 3772 or 708 296 9332 MPR PPC RPU 02 B 4 Computer Group Literature Center Web Site Related Specifications Table B 3 Related Specifications continued Document Title and Source Publication Number Information Technology Local and Metropolitan Networks Part 3 ISO IEC 8802 3 Carrier Sens
55. n electrical ground If the equipment is supplied with a three conductor AC power cable the power cable must be plugged into an approved three contact electrical outlet with the grounding wire green yellow reliably connected to an electrical ground safety ground at the power outlet The power jack and mating plug of the power cable meet International Electrotechnical Commission IEC safety standards and local electrical regulatory codes Do Not Operate in an Explosive Atmosphere Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage Keep Away From Live Circuits Inside the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries such personnel should always disconnect power and discharge circuits before touching components Use Caution When Exposing or Handling a CRT Breakage of a Cathode Ray Tube CRT causes a high velocity scattering of glass fragments implosion To prevent CRT implosion do no
56. ntrol status registers configuring addresses for 1 10 description of 3 1 conventions used in the manual xv conventions numeric xiii CS7 line use on 8xx COMM 1 11 D Debug IEEE 1149 port multifunction pins 2 5 decimal number symbol for xiii definitions xiii digital thermometer thermostat 3 7 double word defined xiv DRAM bank address configuration 1 9 values for configuration 1 12 E EBX specification B 3 EIA 232 transceiver enable disable 3 2 3 3 Ethernet port configuration 3 1 F features by model xi Flash memory configuring bank address 1 11 programming signal on Utility connector 1 3 9 G GPCM general purpose chip select machine controlling QSpan device 1 16 H half word defined xiv hardware features xi hexadecimal value symbol for xiii l T O map system 1 8 C bus address assignments 3 7 initialization boot vectors 1 10 chip selects 1 5 control status registers 1 10 DRAM 1 9 1 12 Flash memory 1 11 ISA address map 1 11 xXmoz ISA devices 1 24 memory controller 1 5 1 12 PCIdevices 1 24 PCI to ISA bridge Winbond chip 1 16 PowerPC core 1 2 QSpan bridge 1 14 system 1 1 system interface unit SIU 1 4 initialization sequence 1 1 interrupt keyboard 1 18 mouse 1 19 pins IPB port 2 4 pins MPC8xx processor 2 3 polarity 2 3 routing required 1 24 signals O 1 18 structure 2 3 2 4 IPB port interrupt pins 2 4 ISA address map 1 11 K KAPWR keep alive power hard
57. om computer literature MBX Initialization As a Slave on the processor bus the QSpan device can accept single beat or burst accesses from the processor The GPCM general purpose chip select machine is used to interface to the QSpan enabling the burst read capability of the GPCM will enhance system performance As a master on the processor bus the QSpan device performs memory accesses to the area of memory controlled by the UPMA user programable machine A Due to the nature of the MPC8xx UPM memory controller interface the QSpan interface on the MPC8xx processor bus cannot perform bursting in this case The burst write feature should be disabled QSpan register space is on chip select line CS6 QSpan PCI space is on CS5 On entry level boards CS5 and CS6 are available at the 8xx COMM expansion connector P1 as well All accesses to the QSpan register space must be single beat The programmer should mark this area noncacheable to inhibit bursting to the QSpan register space see BR6 and OR6 in Table 1 3 Memory Controller Register Initial Values Accesses to the QSpan PCI memory space can be burst or single from the processor perspective To enable bursting to PCI memory space from the processor enable the burst bit in the BRn controlled by the GPCM see BR5 and ORS in Table 1 3 Memory Controller Register Initial Values Winbond 83C554 Initialization Values The Winbond 83C554 PCI to ISA bridge register initiali
58. omputer literature A 7 NVRAM Map and EPPCBug A A 8 Computer Group Literature Center Web Site Related Documentation MCG Documents The Motorola Computer Group publications listed below are referenced in this manual You can obtain paper or electronic copies of MCG publications by Ll Contacting your local Motorola sales office Ll Visiting MCG s World Wide Web literature site http www motorola com computer literature Table B 1 Motorola Computer Group Documents Publication Document Title Number MBX Series Embedded Controller Version C Installation and Use MBXCA IH EPPCBug Firmware Package User s Manual EPPCBUGA UM EPPCBug Diagnostic Firmware User s Manual EPPCDIAA UM To locate and view the most up to date product information in PDF or HTML format visit http www motorola com computer literature B 1 Related Documentation pg Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user s manuals As a further help a source for the listed document is also provided Please note that while these sources have been verified the information is subject to change without notice Table B 2 Manufacturers Documents Document Title and Source Publication Number PowerPC MPC821 Portable Systems Microprocessor User s Manual MPC821UM PowerPC PowerQUICC MPCS 660 User s Manual MPC860UM Literature Distribution Cent
59. ot enable if Loopback is enabled bit 1 1 0 Enable Full Duplex mode of operation on 10BaseT port Disable Half Duplex 1 Disable Full Duplex mode of operation Enable Half Duplex 3 FCTEN 0 Enable Forced Collision Testing on TP 1 Disable Collision Testing capability on transceiver 6 COMIEN This bit is irrelevant if the EIA 232 transceiver is disabled bit 7 1 see Note 0 Route SMCI communication signals to the EIA 232 transceiver 1 Route COMI communication signals to the E A 232 transceiver 7 XCVRDIS Setting this bit to 1 allows SMC to be utilized at the 3X COMM interface 0 Enable on board EIA 232 transceiver 1 Disable the on board EIA 232 transceiver place it in Low Power mode and tri state all transceiver outputs Note On entry level boards bit 6 should be programmed to select SMC1 On standard boards program bit 6 to select COMI 3 2 Computer Group Literature Center Web Site Status Register 1 Status Register 1 Status Register 1 provides read back capability of Control Register 1 The bits are defined in Table 3 2 Table 3 2 Status Register 1 Bit Definitions Bit Mnemonic Definition 0 ETEN 0 Ethernet transceiver disabled and in Low Power mode 1 Ethernet transceiver enabled 1 ELEN 0 Ethernet transceiver not looped back 1 Ethernet transceiver in internal loopback 2 EAEN 0 10BaseT TP AUI auto selection featur
60. others except that the primary device parameters are stored in the NVRAM primary network configuration block beginning at offset 0040 003E 2 Reserved 0040 256 Primary network configuration block See Primary Network Configuration Parameters on page A 4 for details 0140 256 Reserved for future use 0240 1 ISA IRQ number corresponding to PCI INT 0 0241 1 ISA IRQ number corresponding to PCI INT 1 0242 1 ISA IRQ number corresponding to PCI INT 2 0243 1 ISA IRQ number corresponding to PCI INT 3 0244 1 Y or N character which indicates whether or not to reset the system SCSI buses during startup 0245 1 Y or N character which indicates whether or not to probe the system for controllers during startup 0246 1 Y or N character which indicates whether or not to always negate SYSFAIL at startup This capability is not currently used on the MBX but is available for possible future use 0247 1 Reserved 0248 64 PCI probe list This is not yet used on the MBX but is available for possible future use 0288 64 Reserved for future expansion 02C8 3116 Heap for dynamic NVRAM allocation The command and OEM buffers are located here The actual locations of items in this area may change from release to release but will always be determinable from information stored in NVRAM at fixed offsets as described previously http www motorola com computer literature A 3 A
61. p Literature Center Web Site I O Device Configuration Table 1 12 37C672 I O Device Configuration continued Index Type c s Eua Hard Reset Soft Reset om 61 R W Primary Base I O Address 7 0 00 00 F8 62 R W Fast IR Base I O Address 15 8 00 00 63 R W Fast IR Base I O Address 7 0 00 00 70 R W Primary Interrupt Select 00 00 03 74 R W DMA Channel Select 04 04 FO R W Serial Port 2 Mode Register 00 N A 00 Fl R W IP Options Register 02 N A 00 F2 R W IP Half Duplex Timeout 03 N A Logical Device 6 Configuration Registers Reserved Logical Device 7 Configuration Registers Keyboard 30 R W Activate 00 00 01 70 R W Primary Interrupt Select 00 00 0A 72 R W Secondary Interrupt Select 00 00 0C FO R W KRESET and GateA20 Select 00 N A Logical Device 8 Configuration Registers Auxiliary I O 30 R W Activate 00 00 CO R W Pin Multiplex Controls 00 N A 00 http www motorola com computer literature 1 23 MBX Initialization Interrupt Routing Table 1 13 and Table 1 14 present the interrupt structure of the MBX Series embedded controller Table 1 13 Interrupt Structure ISA and PCI Interrupt Source ForS ISA IRQO Timer F ISA IRQI Keyboard F ISA IRQ2 Cascaded from ISA CNTLR 2 F ISA IRQ3 UART 2 COM2 F ISA_IRQ4 UART 1 COMI F ISA_IR
62. ramming information including commands refer to the DS1621 data sheet listed in Appendix C Related Documentation http www motorola com computer literature 3 7 Additional Programming Information Utility Connectors No actual switches or LEDs are mounted on the MBX board Instead a pair of headers is provided for user interface purposes Utility Connector 1 A 20 pin dual row header referred to as Utility Connector 1 J16 supplies the interface between the MBX series embedded controller and external devices such as status LEDs Reset and Abort switches and power sources The header enables an end user application to route these signals via cable to a panel of some sort Utility Connector 1 is present on both entry level and standard versions of the board It provides a connection point for the following functions 1 A Power Fail Sense input This signal activates an NMI to the processor when the voltage falls out of tolerance typically below 0 8V The signal is pulled up via a 3 3KQ resistor and filtered on the board 2 An external connection for battery backup of the processor in deep sleep mode The external battery will also power the keep alive circuits of the MPC8xx 3 Five status lines relating to Ethernet functionality Eth_Tx Eth Rx Eth Col Eth TPIZ Eth_TPP The status lines are provided for use with an LED interface 4 A status line for hard disk activity 5 An active low switch conne
63. rictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 Contents About This Book Over eC One fla aca EHE RIPE NIE AFER NUR xii Comments and BUDGE SONG sin xiii icv ier enn xiii Conventions Used in Ths Mannal 15432 reped e reor bEr EXPRESS pex Enpi S repr br t ne XV CHAPTER 1 MBX Initialization Lice UAL an bon E OEE OT beU E E ERE E E E FORSE nr tre 1 1 POZA Gly p n Mem meansetance musatas lage A 1 1 GCE IMG A terns PT PE EE A RRR E RaanES 1 2 BOSP Parameter RAM Pateh iacuit vis eem o EXEAS HR APER E QUAE Ea E 1 3 system Interface Unit SIU Registers 12e iere Hen sspbt abet esa b ont ieii 1 4 lar pax rcl ge iT d 1 5 svi cugino dur p M 1 8 Notes Tor S veter Address Map creaire oorte eet e necne deqein qe tgo e eS go 1 9 IA Memory MiP serr oen geieaui tas oft pa rn E RS kept pH PIA RN Me eS 1 11 DRAME ORDRE o5 opido d ebd a Mella oe URGE SIR bdo qe tere 1 12 OSpan Imtalization In qe 1 14 Winbond S3C554 Initialization Vales 44 ec iere taedet eese tp etie edens 1 16 37C 2 Pecrpberal VO DEVICE ionieenistec uae uti part pic ER ppl ER HEIE Mete eels aes 1 18 Roequied Intent ROSE casae deuaedeedete d tivae N LR LR EE S Euge UE 1 18 VO Device Address FSCS iiusc
64. ry from a hardware perspective one soldered and two on the DIMM The refresh periodic timer should be scaled back to 5us so that the aggregate refresh time comes to 15ps http www motorola com computer literature MBX Initialization System Memory Map Table 1 4 shows the system address map established by the firmware initialization of the processor s SIU registers and memory controller The notes that follow the table provide device specific information important in programming the MBX to suit your application Table 1 4 System Memory Map MPU View Start End Size Definition CS Notes 0000 0000 00XF FFFF 4 16 MB On board DRAM 32 bit CS1 1 4 7 X 3 for 4M X F for 16M 00X0 0000 OXXX XXXX x MB DIMM slot Bank 0 and 1 CS2 1 2 3 4 8 16 32 64 128M CS3 8000 0000 9FFF FFFF 512 MB PCI ISA I O space CS5 5 6 8 11 A000 0000 BFFF FFFF 512 MB Reserved 10 C000 0000 DFFF FFFF 512 KB PCI ISA memory space CS5 5 8 11 E000 0000 E3FF FFFF 64 MB PCMCIA memory space N A 9 16 E400 0000 E7FF FFFF 64 MB PCMCIA DMA memory space N A 9 16 E800 0000 EBFF FFFF 64 MB PCMCIA attribute space N A 9 16 EC00 0000 EFFF FFFF 64 MB PCMCIA I O space N A 9 16 F000 0000 F9FF FFFF 160 MB Unused 10 FA00 0000 FAOF FFFF 1 MB NVRAM BBSRAM 8 bit CS4 9 11 32 128 512K internal decode FA10 0000 FAIF FFFF 1 MB MBX status control registers 1 CS4 9 11 12 and 2 FA20
65. s present in the PCMCIA socket ISA Memory Map Table 1 5 lists the firmware initialization values for the ISA address map beginning at 80000000 Table 1 5 ISA Address Map Port Description Nun Enabled FDC Floppy disk controller 3F0 3F7 Y UARTI Serial port 1 3F8 3FF Y UARTZ IR Serial port 2 Infrared 2F8 2FF Y Parallel Parallel port 3BC 3BF N KBC Keyboard controller 060 064 Y MOUSE Mouse controller 060 064 Y Notes 1 Base address of the peripheral I O controller is 370 the alternate may be 3F0 2 Addresses are relocatable through software http www motorola com computer literature 1 11 MBX Initialization DRAM Configuration Configuration values for DRAM vary depending on the speed of the processor They are stored in User Programmable Machine A Table 1 6 specifies the configuration values for DRAM at 50 MHz Table 1 7 specifies the configuration values for enhanced DRAM at 50 MHz All values assume 60 ns or faster EDO DRAM with 1 2 or 4K refresh For additional details on the configuration of DRAM refer to notes 1 4 Table 1 4 Table 1 6 UPM A RAM Array for DRAM at 50 MHz Single Read Burst Read Single Write Burst Write Refresh Exception Word Offset 00 Offset 08 Offset 18 Offset 20 Offset 30 Offset 3C 0 CFAF C004 CFAF C004 CFFF 0004 CFFF 0004 FCFF C004 FFFF C007
66. screen displays and examples and to introduce new terms courier is used for system output for example screen displays reports examples and system prompts Enter Return or CR represents the carriage return or Enter key Ctrl represents the Control key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d XV MBX Initialization Introduction This chapter details the default MBX initialization values as well as the EPPCBug firmware initialization values It is organized according to the initialization hierarchy inherent in the hardware Initialization Sequence At start up or reset the MPC8xx processor samples the data bus for initial configuration based on current jumper settings and the design of the MBX board It then passes control to firmware for further initialization Initialization flows in a sequence determined by the hierarchy inherent in the hardware 1 8 MPC821 860 PowerPC core 2 MPC821 860 System Interface Unit SIU 3 4 Primary PCI Bus Bridge device Tundra QSpan chip standard MPC821 860 Memory Controller and memory configurations only ISA Bus Bridge device Winbond W83C554F standard configurations only Super I O device Standard Microsystems Corporation 37C672 standard configurations only PCI Address Spaces configuration and PCI Device configuration standard configurations only PCMCIA Modu
67. t handle the CRT and avoid rough handling or jarring of the equipment Handling of a CRT should be done only by qualified service personnel using approved safety mask and gloves Do Not Substitute Parts or Modify Equipment Do not install substitute parts or perform any unauthorized modification of the equipment Contact your local Motorola representative for service and repair to ensure that all safety features are maintained Observe Warnings in Manual Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment caution when handling testing and adjusting this equipment and its To prevent serious injury or death from dangerous voltages use extreme components Warning Flammability All Motorola PWBs printed wiring boards are manufactured with a flammability rating of 94V 0 by UL recognized manufacturers Caution EMI Caution This equipment generates uses and can radiate electromagnetic energy It may cause or be susceptible to electromagnetic interference EMI if not installed and used with adequate EMI protection Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry Caution Aitention Vorsicht Danger of explosion if
68. tions 1 The COM2 signals from the Peripheral I O controller 2 The Keyboard and Mouse interface signals These signals are intended for direct connection to standard keyboard and mouse connectors 3 Fuse protected 5V drawn from the board The fuse will open if the current drawn by the keyboard and mouse totals more than 0 75A 4 The infrared TTL serial signals from the Peripheral I O controller All the signals present on Utility Connector 2 are EMC filtered and ESD protected It is recommended however that you use a keyboard and mouse that are FCC certified and UL approved The pin assignments for Utility Connectors 1 and 2 can be found in the MBX Series Embedded Controller Version C Installation and Use manual listed under Motorola Computer Group Documents in Appendix B Related Documentation http www motorola com computer literature 3 9 Additional Programming Information 3 10 Computer Group Literature Center Web Site NVRAM Map and EPPCBug Overview EPPCBug uses the first 4B of NVRAM on the MBX for storage of various user tunable parameters such as the ENV and NIOT parameters The remainder of NVRAM is unused by EPPCBug and is available for user applications The first portion 0000 to 0EFF of EPPCBug s 4K NVRAM block is public Any future changes to the public segment of EPPCBug s NVRAM block will be backwards compatible In other words elements added to the public area in future EPPCB
69. ug releases will be placed in previously unused areas of NVRAM and the NVRAM revision field at offset 0008 will be updated to reflect the presence of the additional elements The second portion 0F00 to 0FFD of EPPCBug s NVRAM block is private User applications should avoid modifying or relying on its contents NVRAM and the control status registers all share chip select signal CS4 PowerPC address line A11 distinguishes NVRAM from the control and status registers EPPCBug does not use NVRAM to store board specific information such as serial number Ethernet address artwork id etc This type of information is stored in the IC SROM instead For more information refer to the EPPCBug Firmware Package User s Manual listed in Appendix B Related Documentation A NVRAM Map and EPPCBug NVRAM Map Data items in the NVRAM are mapped at the following offsets from the beginning of NVRAM Table A 1 NVRAM Map Size Offset Bytes Description 0000 4 The magic constant 1230 1983 used to detect uninitialized NVRAM 0004 4 The size of NVRAM claimed by EPPCBug 0008 4 NVRAM structure revision The value 0001 0001 indicates a structure layout as described in this table 000C 4 Offset to EPPCBug startup command buffer Add the contents of this location to the base address of NVRAM FA00 0000 to find the starting address of the EPPCBug command buffer For
70. ware reset 1 26 power on reset 1 26 keyboard interrupt 1 18 L LCD interface configuring 2 11 LEDs configuration 3 4 manual conventions xv manual terminology xiii manufacturers documents B 2 MBX models xi memory controller 1 5 1 12 memory map system 1 8 mouse interrupt 1 19 MPC8xx processor interrupt pins 2 3 memory controller 1 5 1 12 multifunction pins 2 3 2 4 2 5 parameter RAM patch 1 3 multifunction pins Debug IEEE 1149 port 2 5 miscellaneous signals 2 5 MPC8x processor 2 3 2 4 2 5 PCMCIA IPA port 2 1 processor port A 2 7 processor port B 2 8 processor port C 2 9 processor port D 2 11 N negation defined xiv network device configuation A 4 numeric format xiii NVRAM allocation A 1 O option registers configuration 1 5 P parallel port configuring 2 8 interrupt 1 19 PCI to ISA bridge Winbond chip registers 1 16 PCMCIA configuring voltage requirements 3 4 multifunction pins PCMCIA IPA port 2 1 peripheral I O controller address offsets 1 20 interrupt routing 1 19 polarity interrupt signals 2 3 pound sign defined xiv PowerPC core registers 1 2 Q QSpan bridge registers 1 14 R related specifications B 3 IN 2 Computer Group Literature Center Web Site resets HRESET vs POR 1 26 Utility connector 1 3 8 S serial port configuration 3 1 single word defined xiv suggestions submitting xiii symbols meaning of xiii system address map 1 8 in
71. zation values are subject to change based on driver and application requirements This includes the support for application specific EIDE type devices Interrupts are defined in Table 1 13 For more information refer to the EPPCBug Firmware Package User s Manual The 83C554 wakes up in an operational state Initialization consists of L Programming the PCI interrupt routing registers L Programming the interrupt edge level detect registers Computer Group Literature Center Web Site Winbond 83C554 Initialization Values L Setting up the three PC type timers L Programming the ISA bus control registers to a state conducive to host operation The Interrupt Controller portion of the 83C554 device is initialized by firmware to the values listed in Table 1 9 Table 1 9 83C554 Interrupt Initialization PRI RG x 5 Contr pud Polarity Interrupt Source Noles 1 IRQO INT1 Edge High Timer 0 Counter 0 1 2 IRQI Edge High Keyboard 3 10 IRQ2 Edge High Cascaded Interrupt from INT2 3 IRQ8 INT2 Edge Low 4 IRQ9 Edge Low 5 IRQIO INTA Edge Low PCI Slot INTA 2 3 6 IRQI1 INTB Edge Low PCI Slot INTB 2 3 7 IRQ12 Edge High Mouse 8 IRQ13 Edge High 9 IRQ14 INTC Edge Low PCI Slot INTC 2 3 10 IRQI5 INTD Edge Low PCI Slot INTD 2 3 http www motorola com computer literature 1 17 MBX Initialization Table 1

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