S5U13700B00C Rev. 1.0 Evaluation Board User Manual - Digi-Key
Contents
1. L L I i I Eliminator on WE amp RDA L a 1 Ro NE gt gt nDe HOVDD o vec dis CON RDA 4 BIA A 0 p 0 tuF 2 Can A GND SN74LVC2G17 aC uaB NZ VC2G 1 wal VC2G HIOVDD us 41 Vo resets H2 5 Y Lise MBR 1 nur f GND 1 GND 1 TPS3801K33DCKR E swi sH9 SW TACT SPST r 100 in Jumper Shunt e CPU Bus Connector gt y RESETE L I RESET Selector 2 A 5V CON SUPPLY 5V CON SUPPLY 3 vec GND GND GND ag lt KA15 0 o vec Do x 21 cset Y GND Di 1 ose 34 cse 2 cLock BUSCLK D2 x 4 wre gt 27 GND D3 x H Bst 1 WAITH WAIT D4 X ADE x H ce os E X i RDWR4 x OE D6 D7 X 2 wor qh REG D7 E Y WETF RESET_BUS aT INPACK GND BIZ NP 11 GND 4 weroister D8 Lx OD 1 ase ER A25 1 F 2 GND D9 29 x o gt A24 A p 127 RDYIREOF D10 28 X X 13 A23 4 H avozsPkue D11 FAX x14 A con wey 7 BvovsTscHar D12 2x dis WE D13 FEB XIE 420 CONDE Al ogg D14 24 x Pk SH A19 gt towne D15 E x ats 512 Lz2 52 20 IORD GND 21 RESET_BUS 20 ATT GND RESET EL GND PT PE HEADER MODULE P1 HEADER MODULE P2 us connector It was intended to be as generic and to mate with the Signals on the Ix that are not used have The power supply for the module is pulled in ec Te should be SV DC regulated LI E A A2. JP5 B B Disable CLKI input Disable XCG1input Top View Figure 3 6 Configuration Jumper JP5 Location S5U13700B00C Rev 1 0 Evaluation Board User Manual Issue Date 2005 07 15 Revision 1 0 Epson Research and Development Page 15 Vancouver Design Center JP6 Crystal Enable JP6 is used to enable or disable the S1D13700 crystal output XCD1 When the jumper is at position 1 2 XCD1 output is enabled by connecting it to the crystal When the jumper is at position 2 3 XCD1 output is disabled by disconnecting it from the crystal Note When jumper JP6 is at position 1 2 jumper JP5 must also be at position 1 2 When jumper JP6 is at position 2 3 jumper JP5 must also be at position 2 3 E m LI ar mE JP6 E nar Doe NA i T Enable XCD1 output Disable XCD1 output N l Top View Figure 3 7 Configuration Jumper JP6 Location S5U13700B00C Rev 1 0 Evaluation Board User Manual S1D13700 Issue Date 2005 07 15 X42A G 002 01 Revision 1 0 Page 16 Epson
3. L JP9 a E r q Manual reset Host interface reset Top View Figure 3 10 Configuration Jumper JP9 Location S5U13700B00C Rev 1 0 Evaluation Board User Manual S1D13700 Issue Date 2005 07 15 X42A G 002 01 Revision 1 0 Page 18 Epson Research and Development Vancouver Design Center 4 Technical Description 4 1 Host interface 4 1 1 Epson PC Card Extender Support The evaluation board is designed to connect to the Epson PC Card Extender SS5UPCMCIABOOC The extender provides an easy connection to any computer with an available PC Card slot The S5U13700B00C directly connects to the extender via connectors P1 and P2 see Section 8 Connecting the S3U13700B00C to the PC Card Adapter on page 28 Note When using this evaluation board with the Epson PC Card Extender the maximum cur rent draw of 750mA provided by the PC Card slot may be exceeded If the combination of module and LCD panel exceeds this limit an external 5V power supply may be re quired The 5V regulated power supply may be connected to the SV test point TP5V 1 and the GND test point TPGND1 to power the on board regulator In this case the 0 Ohm resistor R2 must be removed from the board 4 1 2 Host Bus Interface Support S1D13700 X42
4. 32 A 8 Epson Evaluation Board Header Pin Mapping 32 S5U13700B00C Rev 1 0 Evaluation Board User Manual S1D13700 Issue Date 2005 07 15 X42A G 002 01 Revision 1 0 Page 4 Epson Research and Development Vancouver Design Center S1D13700 S5U13700B00C Rev 1 0 Evaluation Board User Manual X42A G 002 01 Issue Date 2005 07 15 Revision 1 0 Epson Research and Development Page 5 Vancouver Design Center 1 Introduction This manual describes the setup and operation of the S3U13700B00C Rev 1 0 Evaluation Board This evaluation board is designed as an evaluation platform for the S1D13700 Embedded Memory Graphics LCD Controller The S5U13700B00C is designed for connection to the Epson PC Card Extender S5UPCMCIABOOC thus providing an easy connection to a laptop or a desktop computer with a PC Card reader This module can also be used with other native platforms via the host connectors which provide the appropriate signals to support a variety of CPUs This user manual is updated as appropriate Please check the Epson Research and Devel opment Website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com S5U13700B00C Rev 1 0 Evaluation Board User Manual S1D13700 Issue Date 2005 07 15 X42A G 002
5. EN Md I 119 5c N LEM I O CO Op lt r Figure 7 2 SSU13700B00C Board Layout Bottom View S5U13700B00C Rev 1 0 Evaluation Board User Manual S1D13700 Issue Date 2005 07 15 Revision 1 0 X42A G 002 01 Page 28 Epson Research and Development Vancouver Design Center 8 Connecting the S5U13700B00C to the PC Card Adapter S5U13700B00C Type ll lt PC Card lt Slot lt PC Card Adapter Figure 8 1 Connecting the SSU13700B00C to the PC Card Adapter S1D13700 S5U13700B00C Rev 1 0 Evaluation Board User Manual X42A G 002 01 Issue Date 2005 07 15 Revision 1 0 Epson Research and Development Page 29 Vancouver Design Center 9 References 9 1 Documents Epson Research and Development Inc S1D13700F01 Hardware Functional Specifica tion document number X42A A 002 xx 9 2 Document Sources Epson Research and Development Website http www erd epson com PC Card Standard March 1997 S5U13700B00C Rev 1 0 Evaluation Board User Manual S1D13700 Issue Date 2005 07 15 X42A G 002 01 Revision 1 0 Page 30 10 Technical Support 10 1 EPSON Mobile Graphics Engines S1D13700 Japan Seiko Epson Corporation IC International Sales Group 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 htt
6. 10 v YSCL ue 5 4 Hiovab PRAE AZ 23 FPSHIFT T FPSHIFT NW Fur Fee Web vos NIOVOD A5 10 26 FPLINE XECL E 1 45 FPLINE sv A3 13 HEADER 8X2 A xecL eaeoe Y Y AT 1514 pe eck 30 FFFRAME AD 18 27 mo Nl MOD En d Diop D7 44 pz CONFIG SW sv NIOVDD D 45 D6 o o e 31 vos D4 47 D5 YDIS C21 C23 D3 49 24 c20 0 1uF c22 0 1uF DZ 50 e Di 5r 47uF 10V 47uF 10V Do 56 CNFO E ONF 2 98 CNF2 E NES eil 3 ASH a 51 asg GNF4 60___CNF 3 RD RD 3 wer WR 3 cse L cse 3 waite K wag x SCANEN 32 3 RESET P RESETE Leds 2 xeo 4 xor TSTEN 38 2 X68 13 8 xcat 2 cx S Ibak 28888 Jy S1D13700_TOFP13 64 TE S1D13700 Sis Document Number Rey B 13700B00C PC Card Module 10 Date Wednesday Apil 06 2005 Sheet I 1 ri E I sule1Be1gq neways 9 491u95 ubIseg 49AnooueA 1uouidojoAog pue yo2429soM uosd3 g ebeg O I UOISIA8H 2 bd ON amp Ss D o Mm a c pre Co 3 o Uw o o o m o lt o m m S BS C sp OD D 2 So N 0 op e a SE N 3 35 at Jo Z SaUDWUAYIS 900400L 1NSS Z 9 4n814 1 El ri TPSVI TP SMT Fi 5V CON SUPPLY Re o 1 SN m MINISMDC1 152 1100mA c2
7. 4 Technical Description 18 4 Hostint rface m ang i 423 Gas Bgl a aes Me ta a eee al ace te ver ALS 4 1 1 Epson PC Card Extender Support 18 4 1 2 Host Bus Interface Support 18 42 LCD Panel Interface o o vo noe vo eo 4 42 4 s ers or ss s ss s s 20 4 3 Clocks ico out Ge Rute LA uvm et se cd D de RE yd deus 4 20 5 Parts List ue AEREA Sure vu e CORE Cete due Napa A 21 6 Schematic Diagrams ouv kam lm E Xov RUN ti anne met HAUS wa 23 7 S5U13700B00C Board Layout 26 8 Connecting the S5U13700B00C to the PC Card Adapter 28 9 References iria RAP sex xS o iui eui ka 29 91 Documents s r zoo EU o Rui xu mox E Riv XM US Le 29 92 Document Sources s sor I 29 10 Technical Support soi E a ar en feat 30 10 1 EPSON Mobile Graphics Engines S1D13700 30 10 2 Orderme Informatio E acd ie cette a a a ah uo so Appendix A Epson PC Card Extender 31 Awl Feats d a caca Tu la da Dot Ge ee da e e de a Tune hoe SL AQ General ca how Abe da ue ts s data e AL eat kh sl A MPOWEF a ec a ee A xe Wut ceu e CR E ee a AA Bus Disable ce s se lin dou set he a TG a ut de ur ue p a BZ A 5 16 Bit PC Card Mode 3 AO GenericHl ARO BUS a ges por OB A aa a a X 32 A 7 Epson Evaluation Boards
8. U2 Host Interface Connector Disable CLKI Input Disable Crystal Input u id GERFHDUF ISANG CLKI is tied to VSS XCG is tied to VSS JP6 Crystal Enable Enable Crystal Output Disable Crystal Output JP7 HIOVDD Voltage 5V JP8 NIOVDD Voltage 3 3V 5V JP9 RESET Source Manual Reset Host Interface Reset Required settings when using the PC Card adapter S5U13700B00C Rev 1 0 Evaluation Board User Manual S1D13700 Issue Date 2005 07 15 Revision 1 0 X42A G 002 01 Page 10 Epson Research and Development Vancouver Design Center JP1 HIOVDD JP1 can be used to measure the current consumption of the S1D13700 host interface When the jumper is at position 1 2 normal operation is selected When no jumper is installed host interface current consumption can be measured across JP1 Note The HIOVDD voltage can be selected to be 3 3V or 5V using jumper JP7 B E Normal Operation HIOVDD current measurement Top View Figure 3 2 Configuration Jumper JP1 Location S1D13700 S5U13700B00C Rev 1 0 Evaluation Board User Manual X42A G 002 01 Issue Date 2005 07 15 Revision 1 0 Epson Research and Development Page 11 Vancouver Design Center JP2 NIOVDD JP2 can be used to measure the current c
9. 01 Revision 1 0 Page 6 2 Features S1D13700 X42A G 002 01 Epson Research and Development Vancouver Design Center The S5U13700B00C Rev 1 0 evaluation board includes the following features e 64 pin TOFP13 S1D13700F0x Embedded Memory Graphics LCD Controller Headers for connecting to various Host Bus Interfaces or to the Epson PC Card Extender e 0 1x0 1 header with all the LCD interface signals allowing connection to a LCD panel On board 32MHz crystal and option to use an oscillator instead of the crystal On board 3 3V regulator S5U13700B00C Rev 1 0 Evaluation Board User Manual Issue Date 2005 07 15 Revision 1 0 Epson Research and Development Page 7 Vancouver Design Center 3 Installation and Configuration The S5U13700B00C evaluation board incorporates a DIP switch and 9 jumpers which allow configuration of the board 3 1 Configuration DIP Switches An 8 position DIP switch S1 is used to configure the S1D13700 for different Host Bus interfaces and to select the FPSHIFT cycle time The following figure shows the location of DIP switch S1 on the 55U13700B00C DIP Switch S1 Top View Figure 3 1 Configuration DIP Switch S1 Location S5U13700B00C Rev 1 0 Evaluation Board Us
10. 5 024 te our T wr 10v T HIOVDD f ve xz t vcc nop ces Zeno our lo 1uF TPGND1 EB Oscillator Socket Ie sur J CLKI Select pa 1 2 Oscilator zr P iid 23 Pi 3l Connector up4 Voltage regulator TPP3 3V1 WZ CLKI Select 33V O 800mA IP SMT PCB HeatSinked JP5 3 CLOCKSH PEST ug Input Disable 7 1 2 Oscilator 3 VN vour O 33V Sr o 2L 1 VOUT A a Crysta 3 3 Le CER ae AS lt 120R 0 1 A 100UF tov T 33V 100 in Jumper Shunt SHS TTCS o EA 0 LN j R4 100 in Jumper Shunt 240R R5 4 200R 0 1962 JP6 d f Crystal Di Crystal 7 Power 1 2 Enabled FB AIM XCG1 1 2 3 Disabled 5 EA SHE 100R FN x cioe e should be as short HIOVDD Select po Isolate Crystal with 12 33V 100 in Jumper Shunt 1 CYD ground 23 50V xn XOUT 4 lt nc gt Nc S C30 CystaBEMHz MAGUS on SH7 JP7 12 pF 12 pF y 1 a 3v f 2 movo lt l 100 in Jumper Shunt 3 sv HO Voltage NIOVDD Selection 12 33V 23 50V sue JP8 A 1 33v 2 NIOVDD 100 in Jumper Shunt 3 sy NO Voltage ua Panel Connector Size Document Number Rey B 13700B00C PC Card Module 1 0 Dale Thursday Apa 07 2005 ES 1 i x 401u95 uDise 4eAnooueA ve obed uouidojo Aog pue yo1essay uosd3 O I UOISIAGH 912g onss S1 70 8002 Jenueyy Jes p190g uolj2njeA3 O I 9H 2008002810198 L0 200 D VcrX 00ZELALS Jo soyvomoyos D00400L 1NSS 9 24N814
11. 5 is in position 1 2 to connect the CLKI input to ground because it is not used Jumper JP6 is in position 1 2 to connect the XCD1 output to the crystal The board can use the CLKI input instead of the crystal To use the CLKI input JP5 must be moved to position 2 3 to connect the XCG1 input to ground Also jumper JP6 must be moved to position 2 3 to disconnect the XCD1 output from the crystal The CLKI signal can be provided on the host interface connector or by an on board oscil lator Jumper JP4 is used to select the clock source In position 1 2 the clock is provided by populating an oscillator into the 14 pin DIP socket U2 In position 2 3 the clock must be provided on pin 4 of the host interface connector P1 S5U13700B00C Rev 1 0 Evaluation Board User Manual Issue Date 2005 07 15 Revision 1 0 Epson Research and Development Vancouver Design Center 5 Parts List Table 5 1 Parts List Page 21 Item Qty Reference Part Mfg PN Notes 1 5 C1 C12 C13 C20 47uF 10V Kemet T494B476M010AS CAPACITOR TANT 47UF 10V 20 C22 SMT C2 C3 C4 C10 2 8 C11 C14 C15 C16 0 01uF Panasonic ECG PCC103BQCT C5 C6 C7 C8 C9 3 16 C17 C18 C19 C21 0 1uF Yageo America C23 C25 C26 C27 04022F104Z7B20D C29 C32 C33 4 2 C24 C28 100uF 10VT Kemet T494D107K010AS CARACITOR re TOMAR Panasonic ECG ECJ 5 2 C31 C30 12 pF Y MOD CAP 12PF 50V CERAMIC 0603 SMD 6 1 D1 Power Panaso
12. A G 002 01 The S1D13700 supports several host bus interfaces All S1D13700 host interface pins are available on connectors P1 and P2 allowing the 55U13700B00C to be used for interfacing to other platforms All host interface signals must match HIOVDD of the S1D13700 The default value for HIOVDD on the board is 3 3V so it will work with the Epson PC Card Extender SS5UPCMCIABOOC HIOVDD can be selected between 3 3V and 5V using jumper JP7 S5U13700B00C Rev 1 0 Evaluation Board User Manual Issue Date 2005 07 15 Revision 1 0 Epson Research and Development Page 19 Vancouver Design Center The following diagram shows the location of the host bus connectors P1 and P2 Connectors P1 and P2 are 2x2mm headers 40 pins 20x2 each E P1 and P2 CPU Bus Connectors El n LJ _ Bottom View Figure 4 1 CPU Bus Connectors P1 and P2 Location For the pinout of connectors P1 and P2 refer to the schematics see Section 6 Schematic Diagrams on page 23 Note 1 When the board is connected to a PC using the Epson PC Card Extender the signal AS is not used and R12 must NOT be populated AS input of S1D13700 should be connected to HIOVDD by setting the dip switch S1 position 6 to ON 2 When the board is connected to different platforms the Epson PC Card Extender is not used If using MC68K Family Bus interface the signal AS is used and it can be provided t
13. EPSON EXCEED YOUR VISION S1D13700 Embedded Memory Graphics LCD Controller S5U13700B00C Rev 1 0 Evaluation Board User Manual Document Number X42A G 002 01 Status Revision 1 0 Issue Date 2005 07 15 O SEIKO EPSON CORPORATION 2005 All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Revision 1 0 Page 2 Epson Research and Development Vancouver Design Center S1D13700 S5U13700B00C Rev 1 0 Evaluation Board User Manual X42A G 002 01 Issue Date 2005 07 15 Revision 1 0 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T introduction a as ee de A ESORDADORY 24 e 5 2 Features Le S vk D LR AN eee n Gi Y de IO dite ee Ne 6 Installation and Configuration 7 3 1 Configuration DIP Switches FF FFI 7 32 Configuration Jumpers 9
14. Research and Development Vancouver Design Center JP7 HIOVDD Voltage JP7 is used to select the voltage for HIOVDD When the jumper is at position 1 2 HIOVDD is 3 3V When the jumper is at position 2 3 HIOVDD is 5V Top View Figure 3 8 Configuration Jumper JP7 Location JP8 NIOVDD Voltage JP8 is used to select the voltage for NIOVDD When the jumper is at position 1 2 NIOVDD is 3 3V When the jumper is at position 2 3 NIOVDD is 5V Top View Figure 3 9 Configuration Jumper JP8 Location S1D13700 S5U13700B00C Rev 1 0 Evaluation Board User Manual X42A G 002 01 Issue Date 2005 07 15 Revision 1 0 Epson Research and Development Page 17 Vancouver Design Center JP9 RESET Source JP9 is used to select the source of the RESET signal to the S1D13700 When the jumper is at position 1 2 the S1D13700 is reset by the on board reset button SW1 When the jumper is at position 2 3 the S1D13700 is reset by the system connector P1 pin 21
15. d bus The signals on the bus have been level shifted from 5V to 3 3V Vcc from the PC Card Bus is provided on the header but considerations to the current draw should be noted The evaluation board needs to supply it s own Vcc if the current draw is greater than what the PC Card bus can provide A 8 Epson Evaluation Board Header Pin Mapping The CPU interface uses two female connectors P1 and P2 which provide all the signals and power connections needed for direct PC Card Generic 1 and Generic 2 bus control signals have been decoded and are selectable using SW2 Refer to the schematics for the pinout of P1 and P2 S1D13700 S5U13700B00C Rev 1 0 Evaluation Board User Manual X42A G 002 01 Issue Date 2005 07 15 Revision 1 0 Epson Research and Development Vancouver Design Center Change Record X42A G 002 01 Revision 1 0 released as revision 1 0 X42A G 002 00 Revision 0 01 initial draft added parts list added schematics added board layout S5U13700B00C Rev 1 0 Evaluation Board User Manual Issue Date 2005 07 15 Revision 1 0 Page 33 S1D13700 X42A G 002 01
16. er Manual S1D13700 Issue Date 2005 07 15 X42A G 002 01 Revision 1 0 Epson Research and Development Page 8 Vancouver Design Center All S1D13700 configuration inputs CNF 4 0 are fully configurable using DIP switch S1 as described below Table 3 1 Summary of Configuration Options o TU S1D13700 Configuration State Configuration PI 1 ON 0 OFF S1 8 7 Not used S1 6 AS M68K Family Bus Interface S1 5 CNF4 Indirect Addressing Mode Selects the host bus interface as follows CNF3 CNF2 Host Bus S1 4 3 CNF 3 2 0 1 Reserved 1 0 M6800 Family Bus Interface 1 1 MC68K Family Bus Interface Selects the FPSHIFT cycle time FPSHIFT Clock Input as follows CNF1 CNFO FPSHIFT Cycle Time 0 0 FPSHIFT Divide 4 1 MU GMAO 0 1 FPSHIFT Divide 8 1 1 0 FPSHIFT Divide 16 1 1 1 Reserved Required settings when using the PC Card adapter S1D13700 S5U13700B00C Rev 1 0 Evaluation Board User Manual X42A G 002 01 Issue Date 2005 07 15 Revision 1 0 Epson Research and Development Vancouver Design Center 3 2 Configuration Jumpers Page 9 The S5U13700B00C has 9 jumper blocks which allow the configuration of the board Table 3 2 Jumper Summary Jumper Function Position 1 2 Position 2 3 No Jumper JP1 HIOVDD E HIOVDD current measurement JP2 NIOVDD NIOVDD current measurement JP3 COREVDD E COREVDD current measurement JP4 CLKI Source On Board Oscillator
17. es o OE SN74LVC2G17DBVR 23 6 TPS3801K33D Texas Instruments 30 1 U5 CKR TPS3801K33DCKR IC 2 93V SUPPLY MON SOT 323 5 Crystal32MHz_ 31 1 X1 MA306 Epson MA 306 32 0000M CO S1D13700 S5U13700B00C Rev 1 0 Evaluation Board User Manual X42A G 002 01 Revision 1 0 Issue Date 2005 07 15 O I UOISIAGH 912g onss S1 70 8002 Jenueyy Jes p190g uolj2njeA3 O I 9H 200800Z 10 19S L0 200 D VcrX 00ZELALS Jo I soupuouyo 200800 STDSS I 9 24N814 L 1 L i I HIOVDD Place a 0 01uF and a 0 1uF cap on each o HIOVDD power pin of the S1D13700 Y T 1 T sH1 ca bs t y wr et itur Jor jour bur ue ur d 47uF 10V 1 1 1 l Place a 0 01uF and a 0 1uF cap on each NIOVDD 700 i Jumper Shunt 1 NIOVDD power pin of the S1D13700 o PT HIOVDD 1 T T ce c9 c10 cn C12 SH2 33V Place a 0 01uF and a 0 1uF cap on each p o COREVDD power pin of the S1D13700 0 1uF I TuF lo0tuF lo 0tuF 47uF 10V A A se a RES inr oorr Jootur bur due jour MOVOD TE Ea y i 93898 T00 in Jumper Shunt u 73 Erro 88932399 iu 9 8 grees a A501 y A15 amp as A14 63 At4 Ais y7 18 FPDAT3 AZ 2145 FDA S 19 FFDATZ FPDATO FPDATI Af 3 PDA Te 1720 FFDATI FPDAT2 FPDAT3 Ai 4 Att Eoo Cet FPDATO FPLINE aT
18. gnals for connecting Epson S1D137xx Mobile Graphics Engine Evaluation Boards Epson Identification EEPROM Current limiting resettable fuse LED power indicators Voltage Level shifting to 3 3V The PC Card Extender Board is designed to be connected to a laptop supporting a PC Card Type II or Type III slot The extender board includes an EEPROM containing the identifi cation to specify it as an EPSON LCD controller The software driver supplied by Epson will recognize this PC Card as an Epson LCD Controller The power supplies from the PC Card host are passed to the evaluation board headers A resettable PolySwitch fuse 750mA is placed on Vcc to protect the PC Card bus from excessive current consumption If necessary the evaluation board can be connected to an external power supply Note Permanent damage to the host is possible if signals are shorted on the connector Care must be taken in attaching the modules The performance of the Mobile Graphics Engine in this environment is directly propor tional to the PC Card bus speeds The maximum data bus transfer speed is 10MHz The maximum transfer rate is 20M bytes sec in 16 bit mode and 10M Bytes sec in 8 bit mode Note that the PC Card bus itself is 100 asynchronous and has no clock signals A 3 Power The PC Card Extender Board requires SV to be supplied supported from the PC Card Slot The extender board will not operate in a 3 3V only PC Card slot S5U13700B00C Rev 1 0 Eval
19. ion S5U13700B00C Rev 1 0 Evaluation Board User Manual Issue Date 2005 07 15 Revision 1 0 Epson Research and Development Vancouver Design Center Page 13 JP4 CLKI Source JP4 is used to select the clock source for the S1D13700 CLKI input When the jumper is at position 1 2 the clock source is the on board oscillator U2 When the jumper is at position 2 3 the clock source is from the host interface connector connector P1 pin 4 JP4 B B On board oscillator Host interface r U2 connector S Top View Figure 3 5 Configuration Jumper JP4 Location S5U13700B00C Rev 1 0 Evaluation Board User Manual S1D13700 Issue Date 2005 07 15 X42A G 002 01 Revision 1 0 Page 14 Epson Research and Development Vancouver Design Center JP5 CLKI Input Disable JPS is used to disable the S1D13700 clock input that is not used by connecting it to ground When the jumper is at position 1 2 CLKI input is disabled When the jumper is at position 2 3 XCG1 input is disabled Note When jumper JPS is at position 1 2 jumper JP6 must also be at position 1 2 When jumper JP5 is at position 2 3 jumper JP6 must also be at position 2 3 S1D13700 X42A G 002 01
20. l Tite Host Bus Connect size Document Number Rev B 137008000 PC Card Module 10 1 1 L L Date m sy April Siar 491u95 ubIseg 49AnooueA iuouidojo Aog pue yo2429soM uosd3 Ge eDed Page 26 7 S5U13700B00C Board Layout Epson Research and Development Vancouver Design Center R2 mS R4 DI e o an 2 O POWER QUI a o o lt r AY A A dE SET vye swi J3 RESET C 4 U5 BED D Jr n12 o oa HIO LV Y JPE d x 5 NIO LM CO o a H1 NU NE NO fes R13 U4 Dum AA RG Rf uo S 2 g E PE LE o XC ENABLES I gt A X a Si RI U 5 4 SEIKO EPSON CORPORATION S5U15700BOOC REV 1 0 a A 2005 erd epson cc m Figure 7 1 SSU13700B00C Board Layout Top View S1D13700 S5U13700B00C Rev 1 0 Evaluation Board User Manual X42A G 002 01 Revision 1 0 Issue Date 2005 07 15 Epson Research and Development Page 27 Vancouver Design Center 5 o NI po P1 N NI NI x O Pai NO O 2 NEN ss ET O D 00 RRA C X a OO C C ll ME 3 ost x
21. nic SSG LNJ308G8LRA PED GREEN PEFOWEUH 7 1 F1 MINISMDC 1 10 Raychem Corp Polyswitch POLYSWITCH 1 1A RESET FUSE 2 1100mA Division MINISMDC110 2 SMD 8 1 H1 HEADER 8X2 3M ESD 2516 6002UB CONN HEADER VERT 2POS 100 3 3 ARES TIN or GENERIC 10 6 JP4 JP5 JP6 JP7 CONN HEADER VERT 3POS 100 JP8 JP9 TIN or GENERIC Sullins Electronics Corp 2 ne PRPN202PAEN CTS Corporation 12 1 H1 22K 742C163223JTR RES ARRAY 16TRM 8RES SMD 13 1 H2 0 14 1 H3 120R 0 1 Panasonic ECG ERA 3YEB120V Or equivalent 15 1 H4 240R 16 1 R5 200R 0 1 Panasonic ECG ERA 3YEB200V RES 200 OHM 0 1 SMD 0603 17 1 R6 1M 18 1 R7 100R 19 0 R8 R9 R12 NP 20 2 R10 R11 0 21 1 R13 22k SH1 SH2 SH3 22 9 SH4SH5SHG6 10 Has idi edi dual Pp JUMPER SHORTING TIN SH7 SH8 SH9 23 1 SW1 z yo ds ITT Industries KSC241J SWITCH TACT SILVER PLT J TYPE 24 1 S1 CONFIG SW C amp K TDAOSHOSK1 SWITCH DIP BPOS HACE RITCH SMT S5U13700B00C Rev 1 0 Evaluation Board User Manual Issue Date 2005 07 15 Revision 1 0 S1D13700 X42A G 002 01 Page 22 Epson Research and Development Vancouver Design Center Table 5 1 Parts List Item Qty Reference Part Mfg PN Notes 25 3 TORRES TP_SMT Keystone 5015 PC TEST POINT MINIATURE SMT TPP3 3V1 S1D13700_TQ mr FP13 64 Oscillator 14 pin narrow DIP screw machine E dE Socket socket 28 1 U3 LT1117CST Linear Technology LT1117CST a ei SOT223 Texas Instruments IC BUFFER DUAL SHMT TRG SOT all
22. o the P2 connector by populating R12 and the dip switch S1 position 6 must be set to OFF position to disconnect AS input from HIOVDD S5U13700B00C Rev 1 0 Evaluation Board User Manual S1D13700 Issue Date 2005 07 15 X42A G 002 01 Revision 1 0 Page 20 Epson Research and Development Vancouver Design Center 4 2 LCD Panel Interface All the LCD interface signals are available on connector H1 Connector H1 is a 8x2 header 0 1x0 1 pitch The following diagram shows the location of the LCD connector H1 H1 L E LCD Connector nu Top View 4 3 Clock S1D13700 X42A G 002 01 Figure 4 2 LCD Connector H1 Location For the pinout of connector H1 refer to the schematics see Section 6 Schematic Diagrams on page 23 The S1D13700 accepts a clock signal from an oscillator or from a crystal If the oscillator is used the crystal input XCG1 must be connected to ground and the crystal output XCD1 must not be connected If the crystal is used the clock input CLKT must be connected to ground For details on connecting CLKI or XCG1 to ground refer to the JP5 description see JP6 Crystal Enable on page 15 The default configuration of the S5U13700B00C uses a 32M Hz crystal Jumper JP
23. onsumption of the S1D13700 LCD panel interface When the jumper is at position 1 2 normal operation is selected When no jumper is installed panel interface current consumption can be measured across JP2 Note The NIOVDD voltage can be selected to be 3 3V or 5V using jumper JP8 Lj E y JP2 F q Normal Operation NIOVDD current measurement 4 Fi Top View Figure 3 3 Configuration Jumper JP2 Location S5U13700B00C Rev 1 0 Evaluation Board User Manual S1D13700 Issue Date 2005 07 15 X42A G 002 01 Revision 1 0 Page 12 Epson Research and Development Vancouver Design Center JP3 COREVDD JP3 can be used to measure the current consumption of the S1D13700 core When the jumper is at position 1 2 normal operation is selected When no jumper is installed core current consumption can be measured across JP3 S1D13700 X42A G 002 01 B b Normal Operation COREVDD current measurement Top View Figure 3 4 Configuration Jumper JP3 Locat
24. p www epson com hk 10 2 Ordering Information North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 htto www epson electronics de Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology amp Trading Ltd 14F No 7 Song Ren Road Taipei 100 Taiwan ROC Tel 02 8786 6688 Fax 02 8786 6677 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg To order the S5U13700B00C Evaluation Board contact the Epson sales representative in your area and order part number SSU13700P00C000 S1D13700 X42A G 002 01 Revision 1 0 S5U13700B00C Rev 1 0 Evaluation Board User Manual Issue Date 2005 07 15 Epson Research and Development Page 31 Vancouver Design Center Appendix A Epson PC Card Extender A 1 Features A 2 General This section describes the setup and operation of the PC Card Extender Board Rev 1 0 This board was designed as an evaluation interface for connecting Epson S1D137xx Mobile Graphics Engine Evaluation Boards to the PC Card Bus The PC Card Extender Board Rev 1 0 includes the following features Header Si
25. uation Board User Manual S1D13700 Issue Date 2005 07 15 X42A G 002 01 Revision 1 0 Page 32 Epson Research and Development Vancouver Design Center A 4 Bus Disable Switch SW1 is used to disable the bus to the Epson Mobile Graphics Engine evaluation board When the bus is disabled the red LED D2 turns ON For normal operations the bus should be enabled with SW1 positioned towards the clock X1 location Note On some systems the Bus Disable function must be ON when the PC Card Extender Board Evaluation board combination is first plugged into the PC Card host Once the OS has detected the PC Card the Bus Disable function can be turned OFF A 5 16 Bit PC Card Mode To select 16 bit PC Card mode switch SW2 must be positioned toward the clock X1 location The 1D13700 is a 16 bit device and the drivers for the PC Card have been configured for 16 bit devices only Therefore 8 bit byte steering logic is not needed from the PC Card and should be placed in the 16 bit position A 6 Generic 1 2 Bus Switch SW3 selects the control signals between Generic 1 or Generic 2 bus The S5U13700B00C Evaluation Board does not require the setting of this switch and it should be positioned towards the clock X1 location A 7 Epson Evaluation Boards The extender card provides a header to interface to Epson Mobile Graphics Engine Evalu ation Boards The header contains all the signals necessary for interfacing to the PC Car
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