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SMT8121

1. T Advanced Analog gain fo Offset compensation kon 128 DRDA Ore K m FP Built in test p Shutdown 1 I U I 566668 16666686 566666 1666666 l Frequency Frequency H com sundance example smt381 smt368a PRO Processor root loading module EDMAi6 NOD S E com sundance example smt350 smt368 smt395Q PROCESSING Processor root loading module c xload mod H com sdsp example smt318 PROCESSING Creating bitstream for FPGA fpga391 H com 3L diamond example subone PROCESSING Using FPGA options from optfpga391 W com 3L diamond example multiply PROCESSING Creating bitstream for FPGA fpga381 E com 3L diamond example addone PROCESSING Using FPGA options from optfpga361 Build complete Gel lt Jul J Z Jln Writable Smart Insert 553 1 S Read Me Trim Bottom Figure 8 SMT8121 control panel A graphical user interface allows the user to control the system SMT391 Control The window SMT391 control allows configuring some of the settings of the SMT391 board SM 12391 control Sampling rate Clock source VCO 600 1000Msps ze Channel only Base board SMT358 _ Advanced Analog gain Offset compensation DADA Built in test Figure 9 control panel of the SMT391 Clock source the SMT391 provides three clock sources for the sampling clock of the ADC This drop down list allows selecting whic
2. 500 000 MR II Figure 13 no input 1Gsps J 2 9 2 Input sinewave at 100MHz 1Gsps spectrum Analyzer Data j1 01 06 2007 08 05 46 spectrum Analyzer DUU 100 0 150 0 200 0 250 0 300 0 350 0 400 0 450 0 Center Freq 250 000 000 MHz Span 500 000 000 ME 400 000 0 WHz 2 dBm 375 454 5 MHz HA dm 300 000 0 MHZ U dm 124 545 5 MHz 21 dBm bu fe Tm Fa ae Lal Measurement Parameters Start Frequency OZ DeviceName o S Stop Frequency 500 000 MR II Figure 14 output from J1 spectrum Analyzer Data 12 01 06 2007 08 05 19 Spectrum Analyzer 50 0 100 0 150 0 400 0 450 0 Center Freq 250 000 000 MHz Span 500 000 000 WHz Ref Delta Ref Frec LTI 8 200 000 0 MHz 1 400 000 0 MHz 375 454 5 MHz 300 000 0 MHz 124 545 5 MHz LO fe LTI LT Es I Tm in 13 41 dm da Lal Measurement Parameters Start Frequency OZ DeviceName o S Stop Frequency 500 000 Me II Figure 15 output from J2 9 3 Input sinewave at 250MHz 1Gsps spectrum Analyzer Data 11 250mbz 01 06 2007 08 14 32 Spectrum Analyzer 50 0 100 0 150 0 200 0 250 0 300 0 350 0 400 0 450 0 Center Freq 250 000 000 MHz Span 500 000 000 WHz Ret Delta Ref Frec 410 000 0 MHZ LO fe U dem dBm dBm der Tm da Lal Measurement Parameters Start Frequency Oz DeviceName o S Stop Frequency 500 000 Me II Figure 16 250MHz 1Gsps J 1 spectrum
3. Analyzer Data D 250mbz 01 06 2007 08 15 17 Spectrum Analyzer 50 0 100 0 150 0 200 0 250 0 300 0 350 0 400 0 450 0 Center Freq 250 000 000 MHz Span 500 000 000 WHz Ref Delta Ref Frec 410 000 0 MHz GO pa S C En C A Tm Fa ie O Le Cn CTH fa e H E S Cn I Ger Cn Measurement Parameters Start Frequency OZ DeviceName o S Stop Frequency 500 000 MR II Figure 17 250MHz 1Gsps J 2 10 System power consumption The SMT8121 system power rail measurements show Running the application 12V 85mA EH 11 Summary
4. CONE UON ea A E ho NE go aa Eng rei na 15 8 1 2 RUINS 0 STR 15 N ene Ia en NOE ea 18 oe Doc o cin nc ais e Te EE 18 oo PUN O en EE 20 ie TRO SOUT C E 20 9 Performan Gi E 21 d SS Tale s KY WER L un ssa ada ER S 21 9 2 Input sinewave at LOOMHZ 1GSPS sse 23 9 3 Input sinewave at 250MHZ 1GSPS sese sese 24 10 System power consumption eeeeeseeeeeeReREREREREEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEen 26 Ii SUNMA E 26 Application Note SMT8121 _ Page3of26 Last Edited 19 02 2009 16 32 00 Table of Figures Figure 1 assembling the boards GMT 8 Figure 2 assembling the boards GMT2OS0O sss 9 Figure 3 picture of the front of the aMTISIZTL ENEE 10 Figure 4 picture of the back of the SMT8121 ENNEN 10 Figure 5 SMT8121 inside the EE 11 Figure 6 overview of the SM 1802 FU vic ccosnzcctnsnccetncswsaneddesovesisindensuinedesootsiedensuatedss onuifedenssededetons 12 Figure 7 hardware description of the SMTISIZT EEN 12 Figure 8 SMT8121 control panel ENEE 16 Figure 9 control panel Of the SMT391 ENEE 17 Figure 10 control panel of the aMIZ8TL EEN 18 Figure 11 main tasks used in the applicaton 19 Figure 12 no input 1Gsps OI 21 Foure Ree 0 8 C6 Gr 0 CH J2 E 2 POAT IL ett nn ee J eene EEEE RS 23 Maelo onOne E N 24 Figure 16 250MH2 1GSPS JI ami sras decades ardida insana 25 Fiore do OI EK CSS J EE 26 1 Introduction The Sundance SMT8121 development platform is a modular system
5. an SMT368 and one SMT381 paired with an SMT368A The modules are held on an SMT310Q PCI carrier board SMT395 SMT368 SMT368A SMT391 1GBs SMT381 20MB s LH Ma 20MB s E 1GB s P PCI Input Output Control channel Data channel a CR Analog signals Figure 7 hardware description of the SMT8121 Application Note Samples are sent from the ADC to the DAC via SDB connection Two 32 bits SDBs running at 1 8 of the sampling frequency are used to transport the samples of each channel A snapshot of the samples captured by the ADC is also sent to the DSP via two comport connections The DSP computes the FFT of the data and sends the raw data and the result of the FFT to host to be displayed 6 1 Sampling clock For the system to work without loss of sample the sampling clocks of the ADC and the DAC need to be the same There are two ways to supply the sampling clock to the ADC and the DAC You can either use the SMT391 on board VCO or use an external signal generator 1 Use the SMT391 on board VCO The SMT391 is configured to use its on board VCO The SMT381 is configured to use external RF clock source The sampling clock generated on the SMT391 is provided to the SMT381 by connecting SMT391 J8 to SMT381 J5 The range of frequencies available goes from 600Msps to 1Gsps 2 Use external clock Both SMT391 and SMT381 are configured to use external sampling clock An external si
6. made of multiple FPGAs and DSPs that can be used for multi carrier multi standard cellular systems High Direct IF infrastructures and test equipments It accommodates two input channels and two output channels each sampling at 1Gsps Three Xilinx FPGAs Virtex4 and VirtexlI pro and one TI C64 DSP running at 1GHz are available for the processing of the signals The SMT8121 is fully supported by 3L Diamond design environment Diamond allows to easily and efficiently implement algorithms on the multiple DSPs and FPGAs available in the system 2 Related Documents 2 1 Referenced Documents 2 2 Applicable Documents SMT3100 user manual SMT391 user manual SMT381 user manual SMT368 user manual SMT395 user manual 3L Diamond Sundance Help File 3 Acronyms Abbreviations and Definitions 3 1 Acronyms and Abbreviations 3 2 Definitions 4 Quick start 4 1 What s in the kit The Smt8121 is made of the following hardware Name Joy Description SMT3100 PCI carrier board SMT395 VP30 DSP board SMT381 DAC board SMT368A FPGA board SMT391 ADC board SMT368 FPGA board SMT500 FMS cables SMT506 or 4 MMBX BNC or MMBX SMA SMT507 analogue cable SMT509 100 1 MMBX MMBX cable 10 cm SMT596 H Dual SHB lt gt SHB module SMT531 320 E SHB cable right angled SMT516 et SHB lt gt SHB module The Smt8121 requires the following software Name Qty Description TI CCS TI development environment Xilinx ISE Xilinx FPGA de
7. 4 no Al ai HOF 4 HOF TEKE Cx Taca 0 cma E x laal wd GEL H Leg e a e e er e Ce ba pd a Figure 4 picture of the back of the SMT8121 The following picture shows how the system fits inside the PC Application Note SMT8121 Last Edited 19 02 2009 16 32 00 E 0 7 WW ptg AN d i TY Eus e e pe Gy x 1D o e a reece rece U gt A A a sA e D A re 7 o CNN gt Figure 5 SMT 8121 inside the PC 4 3 Example An example application illustrating the capabilities of the components in the system is provided The example is developed using 3L Diamond design tool 5 Overview The SMT8121 system is made of a 1Gsps dual channel ADC and a 1Gsps dual channel DAC The system allows samples captured by the ADC to be processed and then sent to the DAC Three FPGAs and one DSP are available to implement the algorithms The diagram shows an overview of the SMT8121 Figure 6 overview of the SMT8121 The input signal applied to the input of the Analog to Digital converter is digitalized and the samples are sent to the Digital to Analog Converter which generates the output signal Processing takes place in FPGAs and in DSP Applications are developed using 3L Diamond design tool which allows easy implementation of the algorithm on the DSP and FPGAs of the system 6 The SMT8121 system The system is made of one SMT395 one SMT391 paired with
8. Unit Module Description 1Gsps development platform Unit Module Number SMT8121 Issue Date 19 02 09 Original Author Jean Philippe Arnaud Application Note for SMT8121 Sundance Multiprocessor Technology Ltd Chiltern House Waterside Chesham Bucks HDS 1PS This document is the property of Sundance and may not be copied nor communicated to a third party without prior written permission Sundance Multiprocessor Technology Limited 2006 Certificate Number FM 55022 Revision History Changes Mid EH First release 15 06 07 penne Added resource usage figures 08 08 07 JPA Updated kit s description Corrected figure 1 IT Added system power consumption 09 08 07 Added system based on SMT3950 30 10 08 Corrected comport connection for SMT3950 19 02 09 based system Table of Contents 1 ise e Tei OND EEN 5 2 Related BW Re el Tu 6 ZA Roerne Documents smisiaso dor catenins EEE 6 GE elen ER ebe TE E 6 3 Acronyms Abbreviations and Definitions sssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 6 3 1 Acronyms and Abbreviations sss 6 do 672 8 yE e 1 e ee saeco cets te nde E Sd S 6 4 Quick A c lt Tn EEN 7 c 5 ET Ch ge E e e E 7 42 Assembling th ee 8 GC Ea E ee 11 5 OVV TON EEN nina o add ira doidas 11 D The SMT 8121 Sy Stem H 12 ZS EE Geet alte CIOCIS EEN 13 7 WU LA 8 A Simple exampl sssrinin aaa anaana Aarna a anana Aian naA Aann aadi 15 SL R nno the nie te EE 15 ol
9. gnal generator is used to generate the sampling clock Application Note 7 Hardware SMT 395 SMT395 is based on the 1GHz 64 bit IMS320C6416T DSP manufactured on the latest 90nm wafer technology and offers the highest fixed point processing power ever Sundance have not stopped here and have implemented a scalable solution using Xilinx Virtex II Pro FPGAs SMT 381 The SMT381 is a single width Daughter Module that plugs onto SLB base module SMT368A Virtex4 FPGA It is capable of converting two external digital inputs coming from the Virtex4 FPGA using the SLB interface on the SMT368A with a resolution of 14 bits at 1Gsps A Fujitsu dual channel DAC MB86064 performs the digital to analogue conversion SMT391 The SMT391 is a single width expansion TIM that plugs onto SLB base module SMT368 Virtex4 FPGA It is capable of sampling two analog inputs at 1 GSPS with a resolution of 8 bits An Atmel duel channel ADC AT84AD001 performs the analogue to digital conversion SMT310Q The SMT3100 is a quad 4 site module carrier developed to provide access to TIM Modules over the PCI bus running The card has an on board JTAG controller allowing Code Composer Studio and 3L Diamond applications to be used to debug upload software to Modules 8 A simple example This simple example illustrates the functioning of the SMT8121 This example can be used as a Starting point for users to develop their own applications o
10. h one to use Sampling rate select the sampling frequency of the ADC Channel I only when selected input Jl is sampled by both channels of the ADC When un selected inputs Jl and J2 are each sampled by one channel of the ADC Base board select the base board used The section advanced should not be used when on board clocks are used DRDA the DRDA value depends on the sampling frequency and the base board used You may need to change this value if you are using external sampling clock as the application then doesn t know the sampling frequency Refer to function calcDRDA in task Smt391Control c for the value to use SMT381 control The window SMT381 control allows configuring some of the settings of the SMT381 board Application Note SM1381 control Sampling rate Clock Source Advanced EU dk Oh Loop dk du Figure 10 control panel of the SMT381 Clock source the SMT391 provides three clock sources for the sampling clock of the ADC This drop down list allows selecting which one to use Sampling rate select the sampling frequency of the DAC Note the clock source must be set to External RF when the clock of the SMT391 is used as the sampling clock for the SMT381 via connector J 5 8 1 3 Stand alone mode com sundance example smt8121 sa is a stand alone version of the application The application doesn t interact with the host PC There is no display of t
11. he FFT and the parameters of the application are hard coded in the DSP source code 8 2 Implementation The example is developed with 3L Diamond Source code for the example is provided The diagram shows the main tasks used in the application The tasks in yellow run on the DSP of the SMT395 the tasks in red run on the FPGA of the SMT368 391 the tasks in blue run on the FPGA of the SMT368A 381 To keep the diagram clear only the tasks playing a major role in the application are shown The functionality and use of the tasks which don t appear can usually be deduced from their name and connection in the application Application Note SMT8121 _ Page 180f26 SMT391 control Sampling rate Clock source VCD 600 1000Msps SMT381 control Channel only Base board SMT368 Sampling rate Q C Advanced Clock Source External AF 2 Analog gain Advanced Offset compensation ClkOutt_clk_dly DADA Loop ck du Control channel Data channel a BS Analog signals DSP task placed on SMT395 FPGA task placed on SMT368 SMT391 aa FPGA task placed on SMT368A SMT381 Figure 11 main tasks used in the application The samples coming from the ADC are captured by task SMT391 ADC which outputs four samples at a time at of the sampling frequency The samples for each ADC channel are output output on a separate port of the task Task Pack32to64 groups the samples eight by eight This g
12. n the SMT8121 The samples of the ADC are looped back to the DAC A copy of the samples is routed to the DSP which computes an FFT on them and displays both the raw data and the FFT result 8 1 Running the example 8 1 1 Connections Make sure all connections described in the Quick start section are made Connect a signal generator to the input of the SMT391 and a scope or spectrum analyser to the output of the SMT381 The amplitude of the input signal should be less than 400mV 8 1 2 Running the software Select project com sundance example smt8121 In the Diamond IDE click the run button to compile and run the example If you are using Diamond in command line double click the app file to run the example The following windows should appear The top two windows show the raw data Samples captured by the ADC The bottom two windows display their FFT Zs Time domain Channel 2 OX SMT381 control Sampling rate D fra Clock Source Extemal RF DI gt 29 7 Time domain Channel 1 BAR x Et Amplitude s Amplitude 25 25 26 26 T Advanced 45 i 15 ClkQutl_clk_dly fe y Loop ck dy 2 Shutdown 1 1 1 1 a 1 1 1 1 1 560 1000 1566 2608 560 1000 1566 2608 SMT391 control x Time Time Z Channel 1 FFT 5X f 7 Channel 2 FFT Sampling rate fi 000 Mhz appro Clock source vco 600 1000Msps DI Iw Channel only Amplitude Amplitude Base board SMT368
13. rce usage The resource usage for the FPGA of the SMT391 is as follow BUFG DCM RAM16 SLICES 8 out of 32 44 out of 192 2267 out of 15360 The resource usage for the FPGA of the SMT381 is as follow BUFG DCM RAM16 SLICES 8 out of 32 16 out of 192 1998 out of 15360 Application Note SMT8121 Page 20 of 26 Last Edited 19 02 2009 16 32 00 9 Performance The following screen captures are from a spectrum analyser Anritsu MS2717A 100KHz 7 1GHz Note 1 the system displays rays at 125MHz and 375MHz when sampling at 1Gsps These are images of the clock used by the SDB interfaces They appear always at 1 8 of the sampling frequency Note 2 no filtering has been applied to the input signal Filtering accordingly the input signal could reduce the spur frequencies displayed in the following measurements 9 1 No input 1Gsps spectrum Analyzer Data noinput 11 01 06 2007 07 54 22 Spectrum Analyzer 50 0 100 0 150 0 200 0 250 0 300 0 350 0 400 0 450 0 Center Freq 250 000 000 MHz Span 500 000 000 MHz Measurement Parameters Start Frequency Oz Device Mame Stop Frequency 500 000 MR II Figure 12 no input 1Gsps J 1 spectrum Analyzer Data noinput 12 01 06 2007 07 55 22 Spectrum Analyzer 50 0 100 0 150 0 200 0 250 0 300 0 350 0 400 0 450 0 Center Freq 250 000 000 MHz Span 500 000 000 MHz Measurement Parameters Start Frequency OZ DeviceName o S Stop Frequency
14. rouping enables the tasks connected afterwards to use a clock twice slower The data are then duplicated One copy is sent to the storage task which captures a snapshot of the samples and sends them to the main task for display and FFT processing This is a non real time loop The other copy is sent to task split which separates the samples coming on its input channel on two output channels each having four samples Each output channel is mapped onto one SDB link linking the SMT368 to the SMT368A Each SDB runs at 1 8 the sampling frequency producing a data rate of 500MB s On the SMT368A the samples are received by tasks unsplit which merges the data arriving on its two input ports onto one output port The samples are then packed on 2 samples at a time and accelerated to 500MHz by the task pack64to16 Because the samples coming from the SMT391 are 8 bits and the DAC of the SMT381 expects 14 bits samples the task scaler multiplies each sample by a constant value The samples are finally sent to task DAC381 which forwards them to the DAC on the SMT381 8 3 Building the example Make sure that you have Xilinx ISE9 2sp4 as well as Diamond V3 1 10 or later installed on your PC In the Diamond IDE press CNTRL B to build the application When using Diamond in command line run the MAKE in directory com sundance example smt8121 export or com sundance example smt8121 sa export 8 4 Resou
15. velopment environment Diamond 1 3L development environment 1xDSP 2xFPGA IxFPGA Diamond Optional to target the FPGA of the SMT395 Sundance Multiprocessor Technology Limited ran ocF32 Application Note Date 6 July 2006 4 2 Assembling the boards The following diagram shows the position of the boards on the SMT310Q and the cable connections Q H 8 D ecc FMS cable SHB cable H Signal generator Scope ere re FMS cable doesn t appear in the list of wires in the Diamond application Used by the DAC to send a synchronization signal to the ADC Figure 1 assembling the boards SMT395 Application Note SMT8121 Last Edited 19 02 2009 16 32 00 S H B S H B CP1 CP3 secs Comport switch connection SHR cable N Gesi d Gi NE NE R Comport switch connection or wire modification on the SMT300Q signal generator doesn t appear in the list of wires in the Diamond application Scope Used by the DAC to send a synchronization signal to the ADC Figure 2 assembling the boards SMT395Q Application Note SMT8121 Page 9 of 26 Last Edited 19 02 2009 16 32 00 Sundance Multiprocessor Technology Limited a OCE3 Appl ication Note Date 6 July 2006 The following pictures show the complete system with all cable connections SMT395 SMT368 SMT368A SMT310Q SMT391 SMT381 e qu q an ca 1 E aen tele sis SSGn0S Geng i T ane er rd

SMT8121

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