BBL.2 USER`S MANUAL by N.-P. Chen, C.-C. Chen, C.
Contents
1. 00 1 0000 1 00 1 0000 1 00 1 0000 1 00 1 0000 1 00 1 0000 1 00 1 0000 1 00 1 0000 1 00 1 0000 1 00 1 0000 1 00 1 000 O 1 00 1 0000 1 00 1 0000 1 00 1 0000 0 80 40 T 10 200N6111 1 00 1 0000 300N8111 1 00 1 0000 600N29111 1 00 1 0000 80 20 N11211 1 00 1 0000 60 40 N273 11 1 00 1 0000 40 40 N26 311 1 00 1 0000 20 40 N25 311 1 00 1 0000 1040 N5311 1 00 1 0000 030 N1411 1 00 1 0000 010 N7 411 1 00 1 0000 MOD 00 SIX 0 30 50 T 4 100N10111 1 00 1 0000 30 20 N31211 1 00 1 0000 20 50 N27311 1 00 1 0000 0 40 N29 411 1 00 1 0000 MOD 00 SEVEN 0 50 30 T 8 200N9111 1 00 1 0000 400N12111 1 00 1 0000 50 10 N36 211 1 00 1 0000 40 30 N35 311 1 00 1 0000 30 30 N343 1 1 1 00 1 0000 20 30 N333 1 1 1 00 1 0000 1030 N323 1 1 1 00 1 000 O 0 20 N31 411 1 00 1 0000 MOD 00 EIGHT 0 40 130 T 10 200 NI2111 1 00 1 0000 40 50 N13211 1 00 1 0000 40 80 Ni14 211 1 00 1 0000 40 110 N15 211 1 00 1 0000 30 130 N38 3 1 1 1 00 1 0000 20 130 N37 3 1 1 1 00 1 0000 0 120 N37 411 1 00 1 0000 0110 N30411 1 00 1 0000 030 N28411 1 00 1 0000 020N36 411 1 00 1 0000 4 Restrictions on input data The current version o BBL placement has the following restrictions on input data The top level module must be rectangular The bottom level modules are rectangular functional blocks Module type is always O regular The type of the terminals on2. 1 00 1 0000 En Ep 0100N5421 1 00 1 000 0 PI Pi Low 030 N6 421 1 00 1 0000 por MA oi 400N7121 1 00 1 0000 Ken pS AA lm 700N8121 1 00 1 0000 FV 2 900 N9121 1 00 1 0000 i A i cae dee 1400 N10121 1 00 1 0000 by vr bl I Mul o 180 0 N11121 1 00 1 0000 i U D i 2100 NI2121 1 00 1 0000 FIVE Eh MS 330 80 N13 221 1 00 1 0000 is hog pe s 330 130 N14 221 100 10000 oe oes 330 190 N15 221 1 00 10000 270 230 N16321 1 00 10000 i l 240 230 N17 321 1 00 1 0000 3 200 230 N18 321 1 00 1 0000 f 3 180 230 N19321 1 00 1 0000 EIGHT 160 230 N20321 1 00 1 0000 l 120 230 N21 321 1 00 1 0000 90 230 N22 321 1 00 1 0000 60 230 N23321 1 00 1 0000 30 230 N243 21 1 00 1 0000 13 400N26111 1 00 1 000 0 600N28 111 1 00 1 0000 700N29111 1 00 1 0000 8030NI8211 1 00 1 0000 80 50 N30 211 1 00 1 0000 5070 N21311 1 00 1 000 0 4070N23311 1 00 1 0000 3070N22311 2070N24311 1 00 1 0000 1 00 1 0000 060N4411 1 00 1 0000 040N5411 1 00 1 0000 020N2411 1 00 1 0000 010N3411 1 00 10000 MOD 00 TWO 0 70 40 T 6 500N30111 70 10 N17 211 70 20 N37 211 40 40 N20 3 1 1 30 40 N19 31 1 20 40 N18 31 1 MOD 00 THREE 0 40 30 T 5 100N17111 200N16111 300N38 111 0 20 N18 411 0 10 N37 411 MOD 00 FOUR 3 o o Z co to FN 90 0 N34 60 20 N25 3 1 1 10 20 N30 3 1 1 MOD 00 FIVE 100 10000 1 00 1 0000 1 00 1 0000 1 00 1 0000 1 00 1 0000 1
3. Edition 1 11 85 1 LOOKDB 1 BBL System s Manual LOdKDB 1 NAME SYNOPSIS DESCRIPTION FILES BUGS lookdb database display routine for BBL lookdb filename This program displays all the database information on an HP2648 termin manual for usage can be printed by typing the HELP command Curr following commands are supported by lookdb help quit change plot flag change print flag print all the signal and module names s identify the specified signal m identify the specified module d display regular modules dw display regular modules with default window da display chip routing daw display chip routing with default window x find the name of a module by cursor xr find the name of a routing module by cursor xm find the name of a regular module by cursor R run channel router in the specified routing module R2 run 2D router in the specified routing module W define new window f find input file name r read input file w write output file escape una rr BBL ROSE LOOKDB For display on terminals other than hp2548a you must BBL ROSE LIB display c with your own graphics program 2nd Edition 1 11 85 al The ntly the replace PARADE 1 BBL System s Manual PARADE 1 NAME parade automatic placement system for BBL Building Block Layout SYNOPSIS parade DESCRIPTION Parade is the placement system for BBL 1 It is a completely
4. b the net list input file for ROSE 6 What is the output of BBL The output generated by PARADE is a routing input textfile The coordi nates of the modules are specified The locations of the terminals are updated if rotations and or reflections are performed on the parent module The size and the shape of the boundary of the top level module are modified The I o pads are reassigned subject to the sequence constraints specified in the placement input textfile The spacings between I O pads are calculated proportionally to the spacings given by the input i The routing pattern generated by ROSE is written into a data base tex tfile whose name is specified by the user at the beginning of the program The format of this output file is described in detail in Appendix D The user can lobk at the final placement and routing by using the LOOKDB command A CIF file can also be generated by the CIFGEN command Then the interactive graphics edi tor KIC can be incorporated to do the interactive routing or modific ation A final plot can be obtained by using the CIFPLOT Both KIC and dIFPLOT are in the Berkeley VLSI Tools package 7 Appendix 7 1 Appendix A Commands and application programs 7 2 Appendix B Input format for BBL placement 7 3 Appendix C Input format for BBL routing 7 4 Appendix D Output format for BBL database Appendiz A Commands and Application Programs Contents c
5. in Appendix B i 5 2 A net list routing input textfile This is the standard input for ROSE It includes the description of modules terminals design rules and the net list information Two levels of modules are used The top level module which entloses all the modules on the bottom level is usually the chip boundary The bottom level modules which are treated as blockages are regular modules terminal must be on the boundary of a module For terminals on the chip boundary usually I O pads their positions will be moved proportionally when the chip boundary changes during the routing process Every terminal must have a routing direction which should point toward the routing region Powet ground terminals may have different widths The width of the source terminal should be equal to the sum of the widths of sink terminals If the power terminal is On a horizontal edge the width will grow leftward If the terminal is on a vertical edge the width will grow downward The distance between the powet ground terminal and its neighboring terminal or the corner of its parent module should be enough to cover the wire width and the design rule spacing Four parameters of the design rules should be specified The hprizontal vertical track spacing is the minimum spacing required between two hbrizontal lines The horizontal vertical edge clearance is the minimum distance required between a horizontal wire and a horizon
6. routing system rose system may shift functional blocks and compact the layout to achieve 100 rout ing completion The terminal positions should be fixed on the bounldaries of functional blocks The I O pads are represented by the terminals on the boun dary of the bounding box The bounding box may be shrunk or enlarged in size so that it will become the smallest rectangle which encloses all the functional blocks and interconnections Although the positions of these I O pad may be changed after the routing the ratio of the distances between pads will be kept the same The design rules of wire to wire separations wire to edge clearances are specified in multiples of the unit width Since no additional restrictign will be put on the contact to contact separation the user is responsible to specify the wire to wire separation large enough to take care of this situation Rose is the automatic routing system for BBL 1 2 In the process of E the This routing system can handle convex rectilinear blocks with arbitrary shape and sizes No over the block routing is allowed Currently the system assumes that two layers are available for routing A prerouting analysis is equipped with this system The purpose of this prerout ing analysis is to allocate routing space for a given placement based on a simple uniform probabilistic model The prerouting analysis is not needed if a good manual placement or automatic placement has been done but it wi
7. 5 integer param 6 Line 5 integer param 7 integer param 8 Line 6 integer adjx integer adjy geom Line 1 integer gtp gterm pointer integer rpar rmpar pointer Line 2 integer lgtp integer lbndp Line 3 integer locxy X integer locxy Y Line n for n size locxy array gterm Line 1 integer length of name string x If non zero next line is string vereren If zero next line is 2 below Line 2 integer loc xy X integer loc xy Y Line 3 integer eeg integer leg integer rdg Line 4 integer placg integer clasg float pwc integer msklvi signal Line 1 integer length of name string seeeeese If non zero next line is string s If zero next line is 2 below Line 2 integer alls signal pointer integer rtls sroot pointer integer smp module pointer integer trmls term pointer term Line 1 integer mtc term pointer integer stc term pointer integer mp module pointer integer sig signal pointer integer rsp rseg pointer Line 2 integer tnum srjun Line 1 integer alljr srjun pointer integer sljr rseg pointer Line 2 integer locjr xy X integer locjr xy Y Line 3 short integer conjr rseg Line 1 integer widsr integer msklvl Line 2 integer type of jOsr 0 srjun 1 term integer type of jlsr 0 srjun 1 term Line 3 integer allsr rseg pointer integer hsr sroot pointer Line 4 integer jOsr record pointer see line
8. BBL 2 USER S MANUAL by N P Chen C C Chen C P Hsu H H Chen E S Kuh and M Marek Sadowska Memorandum No UCB ERL M85 2 24 January 1985 BBL 2 USER S MANUAL by N P Chen C C Chen C P Hsu H H Chen E S Kuh and M Marek Sadowska Memorandum No UCB ERL M85 2 24 January 1985 ELECTRONICS RESEARCH LABORATORY College of Engineering University of California Berkeley 94720 BBL 2 User s Manual Nang Ping Chen Chao Chiang Chen Chi Ping Hsu Howard H Chen Ernest S Kuh and M Marek Sadowska Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory University of California Berkeley CA 94720 ABSTRACT BBL is an automatic layout system for placement and routing in VLSI design The building block modules are assumed to be rectilinear and two layers of interconnection are used The placement system of BBL consists of three major phases the bottom up phase to handle the highly connected module pairs and clusters the top down phase to deal with the size and the shape of rhodules and the trade off phase to minimize the global connections as well as thd overall chip area The current placement system can only handle rectangular rhodules The routing system of BBL includes prerouting analysis global routing and detailed routing The purpose of prerouting analysis is to allocate routing space if the original placement is not desirable In global rout
9. e placement is not allowed However the user may change the coordinates of the modules afterwards by editing the routing textfile 4 The routing system of BBL The routing system of BBL is called ROSE It can be divided into three parts prerouting analysis global routing and detailed routing The new features of this routing system are power ground routing and bus routing At the beginning of routing process a set of bottlenecks is generated Bottleneck is defined as a region between the parallel edges of two neighboring modules It is a critical region where congestion is most likely fo occur Bottlenecks are very important for the whole routing system As modules are shifted the structure of some bottlenecks will be changed The prerouting analysis will estimate and allocate the routing space needed if the initial placement is not desirable It assumes that the interconn ction for each net will be done inside the smallest rectangle which encloses all of its termi nals The probability for a bottleneck to be passed through by this n t is then calculated and the sum of probabilities over all nets is the expected roulting den sity in the bottleneck The number of tracks needed will be the smalle t integer larger than the expected density Modules are then shifted to allocate the rout ing space The next step is global routing The purpose of global routing is to assign each net a wiring path without actually emb
10. e stored in the following order schip module rmpar geom gterm signal term srjun rseg sroot and designrl All records type are dumped consecutively The output format for each type of record is as size Line 1 Line 2 schip Line 1 module Line 1 Line 2 Line 3 Line 4 integer number of schip records in file integer number of module records in file integer number of rmpar records in file integer number of geom records in file integer number of gterm records in file integer number of signal records in file integer number of term records in file integer number of srjun records in file integer number of rseg records in file integer number of sroot records in file integer number of designrl records in file integer module pointer integer designrl pointer integer signal pointer integer length of module name string If non zero the next line contains the string If zero the next line is 2 below integer ansmp module pointer integer desmp module pointer integer sibmp module pointer integer mtc term pointer integer geop geom pointer integer loc xy X integer loc xy Y integer rot integer rfl integer placg of a given follows Line 5 integer type integer globrt rmpar Line 1 integer routbnd integer chdr integer rtflag Line 2 integer param 1 integer param 2 Line 3 integer param 3 integer param 4 Line 4 integer param
11. edding it A global routing graph is generated by representing each bottleneck by an edge The weight for each edge s defined as follows edge weight A L B CN 1 where L is the length of the active bottleneck region N is the number of avail able tracks and A B C are the parameters specified by the user If a shortest path is desired the length factor A should be large to dominate the edge weight If the chip area and routing congestion are of primary concern the congestion factors B and C should be large to avoid allocating extra space According to our experiences a combination of A 1 B 50 and C 2 tends to give the best result A Steiner Tree On Graph algorithm is then applied on the global routing graph to find the minimum weighted tree which connects all the terminals in a net The net ordering is determined by the available routing space The net with less routing space will be routed first For those nets which bel ng to a common bus they will be assigned the same global route After all the hets have been assigned their routes we get a better estimation of the routihg space needed The required number of tracks in each bottleneck is equal tolits max imum routing density and a compaction process will be done to remove redun dant routing space After the compaction the minimum chip size is obtained by the global router though it might be increased later in detailed routing Two detailed rout
12. er of dissected blocks and merged blocks as small as possible On the other hand the minimization of the maximum difference of the row lengths is achieved by an efficient multi way set partitioning algorithm where repeated differenking and backtracing are employed The number of rows to be partitioned is determined by the estimated chip area and the sum of the horizontal dimension of the cells after bandwidth minimization The goal of the tradeoff phase is to assign blocks properly in th general ized row structure such that the dissected modules are restored and the global connection lengths are minimized This phase begins with an initial arrangement where rows of cells are placed and all the constraints are satisfied The dissected blocks are restored in the initial arrangement Then an iterative process is activated to do the global paths assignment and the detail placement The spac ings between blocks are determined and the difference of the row lengths is kept as small as possible by using pair wise swappings Finally the horizon al global tracks are assigned and the rows are vertically compacted After all the internal modules are placed we start to place the I O pads sub ject to the sequence constraints specified in the placement textfile ThelI O pads are free to be placed anywhere however their sequence on the boundary of the chip must obey the given constraints This placement system is completely automatic and pr
13. ers are used in BBL One is the channel router and the other is the switch box router The channel router is suitable for the routing problem in a rectangular region with fixed terminals on two opposite qe and floating terminals on the other two edges The switch box router on the other hand can handle any rectilinear region with fixed or floating terminals E is not as efficient as the channel router but it is more flexible In BBL the active region of a bottleneck is routed by the channel router and all other regions are routed by the switch box router Power ground nets are given higher priorities during the routing process In global routing the wire widths for power ground nets will be calculated after their global routes are found In detailed routing the channel router and switch box router use preprocessors to route the power ground nets on one layer if possible and postprocessors to make jumpers for those signal wires which cross the power ground nets Both the channel router and the switch box router will return a request for extra space if the given routing area is not sufficient Some modules will then be shifted to allocate additional space for routing A 100 routing completion can thus be guaranteed while the increase in chip size is kept as small as possible 5 How do you enter input data 5 1 A placement input textfile The input format of PARADE is very similar to that of ROSE The details can be found
14. f input_file A typical command of using cifgen to generate the layout for the whole hip from our text example test db is cifgen c n 2 test db test cif FILES BBL ROSE CIF 2nd Edition 1 11 85 1 CIF2ROSE 1 BBL System s Manual CIF2ROSE 1 NAME cif2rose translate a CIF file into the ROSE input format SYNOPSIS cif2rose input cif input rose DESCRIPTION Cif2rose is an input interface between CIF format and BBL format In order to generate the net list a standard input format for ROSE the CIF input file must include the following layer definitions TRM symbolic layer for terminal definition BNDI symbolic layer for chip boundary BND2 symbolic layer for regular module frame To define a routing problem the modules and terminals shouid be specified as follows 1 Chip boundary is represented by a rectangular box to Regular modules are represented by boxes or rectilinear polygons 3 Terminals are represented by boxes on the TRM laver The center of a terminal box must be on the boundary of a regular module 4 Terminal labels are specified on the TRM layer The lower left corner of a label must be inside its associated terminal box FILES BBL ROSE CIF SEE ALSO Berkeley VLSI Tools KIC cad 1 CIFPLOT cad 2 BUGS This program generates the old input format for ROSE Modifications must be made to generate informations for pcwer ground routing and bus routing 2nd
15. ifgen 1 CIF format generator for BBL cif2rose 1 translate CIF format to ROSE format lookdb 1 database look or dump program parade 1 automatic placement system for BBL rose 1 automatic routing system for BBL rose2parade 1 translate ROSE format to PARADE format CIFGEN 1 BBL System s Manual CIFGEN 1 NAME cifgen generate a CIF file from BBL database SYNOPSIS cifgen option option input file output file DESCRIPTION Cifgen is a CIF format generator for BBL It takes BBL database as the input and outputs a CIF file The actual size of layout is controlled by input parame ters The result can be examined by an interactive graphics editor kie 1 or the CIF plotter cifplot 2 The options are h HPterminal Display a layout on the HP2648A terminal d defaults Allow you to change default values of geometrical ASCL interac tively during the program execution Default values in CIF units are 1 metal segment width 300 2 poly segment width 200 3 contact size 400 4 terminal size 400 5 6 metal to metal separation 300 poly to poly separation 200 c chip Generate the whole chip m module module name Generate the specified module only n number maz_depth Specify how many levels in the hierarchy are to be translated into the CIF file I input tezt file Input data from tezt_file A database file will also be created with the name o
16. ing a a Graph algorithm is used to assign each net a specific route without Actually embedding it Nets which belong to a common bus will be assigned the same glo bal route In detailed routing channel router and switch box router are used to do the track assignment Power and ground nets may have different wire widths and they will be routed on one layer unless they cross each other Since modules can be shifted during the routing process 100 routing completion a always guaranteed Currently BBL runs on a VAX 11 780 under 4 2 Berkeley UNIX HP 2648A terminal is used as the graphics display and the final layout will be gen erated in CIF format The entire BBL system is implemented in C language except the channel router which is written in PASCAL Many examples from industry have been tested Experimental results show that the chip areal can be reduced by 10 25 with the BBL layout For an AMI chip with 33 modules 132 nets and 440 pins it takes 69 CPU seconds to finish the placement And 5 5 minutes to complete the routing BBL 2 User s Manual Nang Ping Chen Chao Chiang Chen Chi Ping Heu Howard H Chen Ernest S Kuh and M Marek Sadowska Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory University of California Berkeley CA 94720 1 What is BBL BBL is an abbreviation for the Berkeley Building Block Layout System It can be used as an automatic tool to generate the
17. is to arrange the modules of each cluster or module pair to fotm super modules which optimize the usage of space and the distance of connectidns Dur ing this step pins of different modules are aligned relative positions of the modules in each cluster are determined and wiring areas are allocated for both the local nets and global nets The supermodules can be of any rectilindar shape but the cluster placement tends to simplify them For the single modules local wiring areas are estimated and attached to their peripheries This estimation is based on a simple probabilistic model which calculates the average lodal wiring area irrespective of the placement and routing algorithms used The input of the top down phase is a set of supermodules and single modules with estimated local wiring area attached From now on we simply call them blocks The top down process partitions the blocks into several coarsk rows of cells on the chip The cell in each row can be a single block a set df merged blocks or a piece of a dissected block The goal of this phase is to minfmize the maximum difference of the row lengths while keeping the maximum difference of the cell heights in each row sufficiently small A novel geometric bandwidth minimization is devised to make the maximum difference of the cell heights in each row sufficiently small The minimization of the bandwidth is achieved by orienting merging and dissecting the blocks while keeping the numb
18. j 2 2 MOD 00 c 0 75 45 90 45 90 80 75 80 T 80 45 power 12 11 0 90 50 f 2 2 90 60 x 2 2 9075d 22 7680 c 3 2 80 80 b 3 2 85 80 ground 321 1 0 89 80 t 3 2 75 55 g 02 7565102 7575r02 MOD 00 d 0 85 15 85 35 60 35 60 15 T 85 20122 85 25 k 2 2 85 30 power 2 2 1 1 0 65 35 e 3 2 7035 d 3 2 7535032 60 20 ground 0 211 0 60 25 e 0 2 60 30 g 0 2 6034702 6515n12 7015m12 7515b12 8015212 5 Restrictions on input data The current version of BBL has the following restrictions on input data The top level module must be rectangular The bottom level modules are rectilinear functional blocks Module type is always O regular Terminal type is always 2 fixed The module and terminal coordinates should be integers All the design rule parameters must be 1 Power ground width can be any positive real number Each power ground net has one source terminal and several drain terminals The width of the source terminal must be equal to the sum of the widths of the drain terminals bus number must be a positive integer Appendiz D Output Format for BBL Database The output file of ROSE is created by the DBWRITE subroutine It can be checked directly by using the LOOKDB command or translated into a CIF file by the CIFGEN command The first two lines of the output file contain information about the size of each data type Then 11 types of data ar
19. layout of integrated eircuits The design style of building block layout has the following features 1 It uses library cells or user designed macros as the building block modules 2 Each module may have terminals along its boundary 4 The objective of the placement and routing is to minimize the layout area 1 2 3 All the terminals with the same net name should be connected together 4 5 100 routing completion can always be achieved This approach has a wide application in the random logic custom chip design It can also be applied in a hierarchical design where BBL is us d as the layout tool on each level 2 What can BBL do BBL can generate automatic placement and routing of integrated circuits provided the following conditions are satisfied 1 Al the modules are convex rectilinear polygons Note that the current placement system restricts the modules to be rectangular automatic routing process However interactive routing and wire mo can be done after automatic routing 3 The placement system of BBL phases the bottom up phase the top down phase and the tradeoff phase Each module may have terminals on its boundary Terminals with the same net name are to be connected together While the positions for terminals along the chip boundary can be shifted according to the size of the chip their relative positions will not be changed All other terminals are fixed on the boundary
20. ll be helpful if the original placement is not good The user also has to specify three parameters which control the global routing If the user is happy with the placement and does not want to change it drastically then a large congestion factor Blor place ment adjustability factor C should be used If the user cares more about the shor test length connections for all nets then a large length factor A should be used The system will interactively ask user the following questions rose Enter input file name lt filel gt Enter output database file name lt file2 gt Enter length factor for bottlenecks default 1 Enter congestion factor for bottlenecks default 50 Enter placement adjustability factor default 2 Prerouting analysis y n Compaction after global routing y n Final plotting y n 2nd Edition 1 11 85 1 ROSE 1 BBL System z Mianual ROSE The system will generate a file named debug under the same directory This file contains all the bottleneck information for debugging purpose Filel is the input file whose format is described in appendix C File2 is the yni t of the database which can be seen by using lookdb or generate the CIF fil do using cifgen SEE ALSO 1 Chen N P The Routing System for Building Block Ph D thesis U C Berkeley 1983 2 Chen N P Hsu C P Kuh E S The Berkeley Building Block Layout System for VLSI Design Proc Internati
21. ma c process No pre placement is allowed The modules are restricted to be rectangular and free to rotate and reflect in any orientation as long as the edges are vertical or horizontal The objective of the placement is to place and orient the modules in an optimal way such that the final layout area including the intercbnnection area is minimized The boundary of the top level module is determined after all the bottom level modules are placed and the wiring area allocated The I O pads are assigned on the boundary subject to the sequence constraints specified in the placement input textfile The spacings between the I O pads are calcu ated pro portionally to the spacings given in the input file i The system will interactively ask user the following questions parade ENTER THE INPUT PLACEMENT TEXTFILE NAME lt filel gt ENTER THE OUTPUT ROUTING TEXTFILE NAME lt file2 gt WHOLE CHIP PLOT lt y n gt where filel is the input placement textfile whose format is described in appendix B and file2 is the output routing textfile for ROSE DIAGNOSTICS new program which can handle rectilinear modules is under development It will be provided in our next version of BBL PARADE SEE ALSO 1 Chen C Kuh E S Automatic Placement for Building Block Lay out Proc ICCAD 1984 pp 90 92 2nd Edition 1 11 85 1 ROSE NAME SYNOPSIS DESCRIPTION 1 BBL System s Manual ROSE 1 rose automatic BBL
22. of their parent modules All the modules are treated as blockages No wires are allowed to cross the modules Pre placement is not allowed in the BBL placement system sein since the output of the placement is a routing textfile the placement system and routing system can be used separately That is the coordinates of modules can be specified by the user without using the the completely alutomatic placement system Modules should not overlap each other and all the bot tom level modules must be inside the boundary of the top level module Two layers are available for interconnection Four design rule parameters should be specified namely horizontal vertical track spacing and horizontal vertical edge clearance The current version of BBL does not allow any prewiring before the ne The placement system of BBL is called PARADE It consists of three major The bottom up phase starts with the module wise connectivity analysis Based on this result the pairing process is activated to pair the highly connected modules The pairing process continues until some threshold value is reached that is when connectivity is no longer considered vital The outcome of this pro cess is a set of clusters module pairs and single modules For each highly con nected module pair a set of potentially good wiring patterns is generated The information will be used in the next step i e the cluster place ent Its objective
23. onal Conference on VLSI Nor way August 1983 pp 37 44 3 Chen N P New Algorithms for Steiner Tree on Graphs Proc IEEE ISCAS 1983 pp 1217 1219 4 Hsu C P A New Two Dimensional Routing Algorithm AM 19th Design Automation Conference June 1982 pp 46 50 5 Yoshimura T Kuh E S Efficient Algorithms for Channel Routing i IEEE Transaction on Computen Aided Design of Integrated Cirpuits and Systems January 1982 pp 25 35 BUGS An early version of this program was sent to several cooperating compahies who tried our program and gave us feedback We fixed some bugs and in addition added new features in this present version but by no means will this program be perfect We continue to welcome comments and will improve it in the f iture ver sions of BBL ond Edition 1 11 85 2 ROSE2PARADE 1 BBL System s Manual ROSE2PAHADE 1 NAME rose2parade convert from ROSE format to PARADE format SYNOPSIS rose2parade DESCRIPTION Rose2parade will interactively ask the user to enter the PARADE en to be generated and the ROSE input file to be translated This program is imple mented to help those who already had their own placement and would like to try the new BBL placement for comparison FILES BBL PARADE rose2parade 2nd Edition 1 11 85 1 Appendiz B Input Format for BBL Placement 1 The input text file format lt Date gt BBL PLACEMENT TEXTFILE lt of module
24. s gt modules lt of nets gt nets top level module data module data at this level 2 The format of module data MOD top level module 00 origin coordinates lt module name gt up to 20 characters lt module type gt the type of module lt dim X gt lt dim Y gt the dimension of the module T terminals lt of terminals gt number of terminals on the module lt x gt lt y gt lt net gt lt edge gt lt type gt lt layer gt lt width gt lt depth gt ae lt bus gt x y terminal coordinates relative to the bottom left corner of the module net name of the net up to 20 characters edge the edge of the module on which the terminal locates i e bottom 1 right 2 top 3 left 4 type I fixed 2 edge fixed 3 floating layer the wiring layer that the terminal resides width the physical width of the terminal depth the depth of the terminal toward the inside of the module boundary p g the power and ground flag bus the bus flag see also App C 3 A sample input file for placement DATE BBL PLACEMENT TEXTFILE 8 modules 38 nets MOD 00 ar i bound i 0 t i i 330 230 ft i roscas eo T p 24 oO i 0 160 N1421 1 00 1 0000 iJj 4 0140N2421 1 00 1 000 0 O Lj 0130 N3421 1 00 1 0000 Evil ONE ATWO I 0110N4421
25. ssigned the same b b ith th b b ill b igned th global route The specifications of lt p g gt lt width gt and lt bus gt are optional 3 The design rule format DES ht lt horizontal track spacing gt vt lt vertical track spacing gt he lt horizontal edge clearance gt ve lt vertical edge clearance gt Currently all the parameters must be 1 4 A sample input file SN 29 MOD 00 bound 0 00 100 0 100 100 0 100 T 200432 400832 50 0 bus132011 55 0 bus23 2011 60 0 bus33 2011 900k 32 0 40 ground 22 1 4 0 075 v22 090022 10 100 x 1 2 25 100 j 1 2 50 100 s 1 2 75 100 x 12 100 45 power 0 2 1 4 0 DES ht 1 vt 1 he 1 ve 5 MOD 00 a 0 10 85 10 10 50 10 50 50 20 50 20 85 T 10 15 ground 0 2 1 1 0 10 35 p 0 2 10 40 p02 1045002 1050a02 10 64 bus1 02011 10 67 bus20 2011 1070 bus302011 1080502 15 102 1 2 2010b12 3010p12 35 10r12 45 10 w 1 2 49 10 v 1 2 50 15 g 22 50 20 f 2 2 50 30 b 2 2 50 35 a 2 2 50 40 d 2 2 50 45 e 2 2 25 50 m 3 2 30 50 13 2 35 50 n 3 2 40 50 t 3 2 20 55 n 22 20 65 y 22 2070 x 2 2 20 80 w 2 2 1585x 32 MOD 00 b 0 65 90 30 90 30 65 65 65 T 40 90 bus1 32011 45 90 bus23201 1 50 90 bus3 3 201 1 60 90 1 3 2 30 70 i 0 2 30 80 ground 0 2 1 1 0 35 65 u 1 2 45 65x 1 2 50 65 j 12 60 65 power 1 2 1 1 0 65 70 g 22 6575 y 22 65 80k 22 65 35
26. tal boundary segment Currently all the design rule parameters must be set as 1 so all the coordinates should be scaled down i e divided by the track pitch before they are used as the input A detailed description of the input format is in Appendix C Thepretically there is no limit on the number of modules and terminals However to make BBL run more efficiently it is recommended that the input data be limited to 50 modules 1000 terminals and 1000x 1000 chip size 5 3 A CIF input file The user can enter the input data by using the interactive graphics editor KIC In fact any graphics editor will do as long as the CIF file generated con tains the following layers TRM symbolic layer for terminals BNDI symbolic layer for the chip boundary BND2 symbolic layer for modules The chip boundary is a rectangular box which contains all the modules A module is represented by a box or a rectilinear polygon and terminals are represented by boxes The center of a terminal box must be on the boundary of its parent module Each terminal has a label and the lower left corner of a label should be inside the terminal box The spacing between the center of terminals and between the center of a terminal and the corner of its parent module should be equal to multiples of the minimum track spacing The CIF input file can be transformed into the standard ROSE inpht format by using the CIF2ROSE command The new file generated will then
27. top level module is 2 edge fixed e The type of the terminals on bottom level modules is 1 fixed The layer and depth of the terminals are set to 1 The width and depth of the terminals are floating number The module and terminal coordinates should be integers Appendiz C Input Format for BBL Routing 1 The input text file format SN lt number of nets gt top level module data design rules module data at this level 2 The format of module data MOD top level module lt x gt lt y gt origin coordinates all module coordinates are relative to this position lt module name gt up to 8 characters lt module type gt 1 routing module 0 otherwise lt x1 gt lt yl gt corner coordinates of the module in the counterclockwise direction lt x2 gt lt y2 gt T terminals lt x gt lt y gt lt name gt lt dir gt lt type gt lt p g gt lt width gt lt bus gt x y terminal coordinates relative to the origin inal di lati he origi name of net is restricted to 6 characters routing direction left 0 down 1 right 2 up 3 ing di 1 left 0 d 1 right 2 3 terminal type 2 fixed other types are for internal use only terminal 2 fixed other t for int l I power ground flag 1 power ground 0 otherwise power ground width meaningless if power ground flag 0 bus number nets with the same bus number will be a
28. two for type sroot Line 1 designrl Line 1 Line 2 integer jlsr record pointer see line two for type integer sOlsr rseg pointer integer sllsr rseg pointer integer allseg rseg pointer integer alljun srjun pointer integer nrts sroot pointer integer mp module pointer integer shr signal pointer nteger htrksp integer vtrksp integer hegcl integer vegcl
Download Pdf Manuals
Related Search